Download datasheet for ML2286X-XXX by LAPIS Semiconductor

Download datasheet for ML2286X-XXX by LAPIS Semiconductor
FEDL228XXDIGEST-04
Issue Date: Aug. 25, 2011
ML2282X-XXX/ML2286X-XXX
Speech Synthesis LSI with Built-in P2ROM Including 2-Channel Mixing Function
GENERAL DESCRIPTION
ML2282X(ML22825/ML22824/ML22823-XXX) and ML2286X (ML22865/ML22864/ML22783-XXX) are
voice synthesis LSIs with built-in P2ROM that stores speech data.
These LSIs include edit ROM, ADPCM2 decoder, 16-bit DA converter, low pass filter and monaural speaker
amplifier. Also, ML2282X supports the synchronous serial interface and ML22865/ML22864/ML22863
supports the I2C interface.
By integrating all the functions required for voice output into a single chip, these LSIs can be more easily
incorporated in compact portable devices.
 Built-in memory capacity and maximum vocal reproduction time:
(at the case of 4-bit ADPCM2 algorithm)
Product name
ROM capacity
ML22825-XXX/ML22865
ML22824-XXX/ML22864
ML22823-XXX/ML22863
16 Mbits
8 Mbits
4 Mbits
Maximum vocal reproduction time (sec)
FS = 4.0 kHz
FS = 8.0 kHz
FS = 16 kHz
1,044
522
261
520
260
130
258
129
64
 Voice synthesis method:
4-bit ADPCM2
8-bit Nonlinear PCM
8-bit PCM , 16-bit PCM
Can be specified for each phrase.
 Sampling frequency(Fs):
4.0 / 5.3 / 6.4 / 8.0 / 10.6 / 12.0 / 12.8 / 16.0 / 21.3 / 24.0 / 25.6 / 32.0 /
48.0 kHz
fs can be specified for each phrase.
 Built-in low-pass filter and 16-bit DA converter
 Speaker driving amplifier:
0.7 W (when 8 , DVDD=5 V, Ta=25C)
2ch analog input (internal: 1ch; external: 1ch)
 CPU command interface:
3-wired serial clock-synchronized (ML2282X)
I2C interface (ML2286X)
 Maximum number of phrases:
4,096 phrases from 000h to 3FFh (1024 phrases/bank)
 Memory bank switching:
Enabled between bank 1 and bank 4 using the SEL0 and SEL1 pins
 Volume control:
32 levels (OFF is included) can be set by CVOL command.
50 levels (OFF is included) can be set by AVOL command
 Repeat function:
LOOP commands
 2-channel mixing function:
Available except case using 32kHz as sampling frequencys
 Source oscillation frequency:
4.096 MHz
 Power supply voltage:
2.7 to 3.6V / 4.5 to 5.5 V
 Operating temperature range:
–40 to +85C
 Package:
30-pin plastic SSOP (SSOP30-P-56-0.65-K-MC)
 Product name:
ML22825-xxxMB, ML22824-xxxMB, ML22823-xxxMB
ML22865-xxxMB, ML22864-xxxMB, ML22863-xxxMB
(xxx: ROM code No.)
1/27
FEDL228XXDIGEST-04
ML2282X-XXX/ ML2286X -XXX
The following table shows the differences among the other speech synthesis LSIs.
Parameter
CPU interface
Playback method

ML22825/ML22824/
ML22823-XXX

ML22865/ML22864/
ML22863-XXX
I2C



1,024 (256/bank)
4,096 (1,024/bank)


4.0/5.3/6.4/8.0/
10.6/12.0/12.8/
16.0/21.3/24.0/
25.6/32.0/48.0

ML2216
ML22800 series
Serial
4-bit ADPCM2
8-bit nonlinear PCM
8-bit straight PCM
16-bit straight PCM
Maximum number
of phrases
256
4.0/5.3/6.4/
8.0/10.6/12.8
16.0
Sampling
frequency (kHz)
Clock frequency
DA converter
Low-pass filter
Speaker driving
amplifier
Edit ROM function
Simultaneous
sound production
function (mixing
function)
Volume control
Silence insertion
Repeat function
Interval at which a
seam is silent
during continuous
playback (Note)
Memory bank
switching
Power supply
voltage
Package
4.096MHz
(with a built-in crystal
oscillator circuit)
12 bits
3rd order comb filter
Built-in 0.3W
(8, DVDD = 5 V)
Yes



12 bits
3rd order comb filter



16 bits
FIR interpolation filter
Built-in 0.7W
(8, DVDD = 5 V)

No

2-channel

16 levels
Yes
20 ms to 1024 ms
(4 ms/step)
Yes

32 levels







No



No
Yes


2.7 V to 5.5 V
2.7 V to 3.6 V
44-pin QFP
30-pin SSOP
2.7 to 3.6V
4.5 to 5.5 V

2.7 to 3.6V
4.5 to 5.5 V

No


*1: Continuous playback as shown below is possible.
1 phrase
1 phrase
No silence interval
2/27
FEDL228XXDIGEST-04
ML2282X-XXX/ ML2286X -XXX
BLOCK DIAGRAMS
(ML22825/ML22824/ML22823-XXX : Synchronous serial interface)
DVDD
DGND
Multiplexer
Address Controller
16/8/4Mbit ROM
VDDL
VDDR
CSB
SCK
SI
SO
CBUSYB
DIPH
SEL0
SEL1
TESTI0,1
TESTO
RESETB
XT
XTB
Phrase Address
Latch
ADPCM Synthesizer
Address Counter
PCM Synthesizer
I/O
Interface
LPF
Timing
Controller
16bit DAC
SP-AMP
OSC
PLL
SPVDD SPGND
SPM SPP
AIN
(ML22865/ML22864/ML22863-XXX : I2C interface)
DVDD
DGND
Multiplexer
Address Controller
16/8/4Mbit ROM
VDDL
VDDR
Phrase Address
Latch
ADPCM Synthesizer
Address Counter
SDA2-0
SCL
SDA
CBUSYB
SEL0
SEL1
TESTI0,1
TESTO
RESETB
XT
XTB
PCM Synthesizer
I/O
Interface
LPF
Timing
Controller
16bit DAC
SP-AMP
OSC
PLL
SPVDD SPGND
SPM SPP
AIN
3/27
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ML2282X-XXX/ ML2286X -XXX
PIN CONFIGURATIONS (TOP VIEW)
(ML22825/ML22824/ML22823-XXXMB : Synchronous serial interface)
AIN
TESTI0
RESETB
TESTO
DIPH
SEL0
SEL1
DGND
CSB
SCK
SI
SO
CBUSYB
DGND
XT
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
SPM
SPP
SPGND
SPVDD
DGND
SG
TESTI1
VDDR
DVDD
VDDL
NC
DGND
NC
DVDD
XTB
NC: No Connection
30-Pin Plastic SSOP
(ML22865/ML22864/ML22863-XXXMB : I2C interface)
AIN
TESTI0
RESETB
TESTO
SAD0
SEL0
SEL1
DGND
SAD1
SCL
SDA
SAD2
CBUSYB
DGND
XT
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
SPM
SPP
SPGND
SPVDD
DGND
SG
TESTI1
VDDR
DVDD
VDDL
NC
DGND
NC
DVDD
XTB
NC: No Connection
30-Pin Plastic SSOP
4/27
FEDL228XXDIGEST-04
ML2282X-XXX/ ML2286X -XXX
PIN DESCRIPTION (COMMON TO ALL PRODUCTS)
Initial value
Description
(*1)
0
Input pin for speaker amplifier.
Input pin for testing.
0
Fix this pin to “L” level (DGND level). This pin has a pull-down resistor
built in.
Input pin for reset.
At the “L” level, the LSI enters initial state. During reset, the entire
circuitry stops and enters power down state. Input “L” level when power is
0
supplied. After the power supply voltage is stable, drive this pin to “H”
(*2)
level. Then the entire circuitry can be powered up.
This pin has a pull-up resistor built in.
Output pins for testing.
Hi-Z
Leave these pins open.
Memory bank switching pins.
0
Fix these pins to “L” level when the memory bank function is not used.
Pin
Symbol
I/O
1
AIN
I
2
TESTI0
I
3
RESETB
I
4
TESTO
O
6, 7
SEL0
SEL1
I
8, 14,
19, 26
DGND
—
—
13
CBUSYB
O
1
15
XT
I
0
16
XTB
O
1
17, 22
DVDD
—
—
18, 20
N.C
—
—
21
VDDL
—
0
23
VDDR
—
0
24
TESTI1
—
0
25
SG
—
0
27
SPVDD
—
—
28
SPGND
—
—
29
SPP
O
0
30
SPM
O
Hi-Z
Digital ground pin.
Also serves as a ground pin for the internal memory.
Output pin for command processing status.
This pin outputs “L” level during command processing. Any command
should be entered when this pin is “H” level.
Connect to the crystal or ceramic resonator.
A feedback resistor around 1 M is built in between this pin and the XTB
pin. Use this pin if need to use an external clock.
If the resonator is used, connect it as close to this pin as possible.
Connect to the crystal or ceramic resonator.
When to use an external clock, leave this pin open.
If the resonator is used, connect it as close to this pin as possible.
Power supply pins for logic circuitry.
Connect a capacitor of 0.1F or more between these pins and DGND pins.
Non connected pins. Leave these pins open.
Regulator output pin for internal logic circuitry.
Connect a capacitor recommended between this pin and DGND pin.
Regulator output pin for Built-in ROM.
Connect a capacitor recommended between this pin and DGND pin.
Test pin. Fix this pin to a DGND level.
Reference voltage output pin for the speaker amplifier built-in.
Connect a capacitor recommended between this pin and DGND pin.
Power supply pin for the speaker amplifier.
Connect a bypass capacitor of 0.1F or more between this pin and SPGND
pin.
Ground pin for the speaker amplifier.
Positive(+) output pin of the speaker amplifier built-in.
Serves as the LINE output (*3), if built-in speaker amplifier is not used.
Negative(-) output pin of the speaker amplifier built-in.
*1: Indicates the initial value during reset input or power down.
*2: “H” during power down.
*3: Outputs a voice signal before amplified by the speaker amplifier built-in.
5/27
FEDL228XXDIGEST-04
ML2282X-XXX/ ML2286X -XXX
PIN DESCRIPTION (FOR ML2282X SYNCHRONOUS SERIAL INTERFACE)
Pin
Symbol
I/O
Initial value
(*1)
5
DIPH
I
0
9
CSB
I
1
10
SCK
I
0
11
SI
I
0
12
SO
O
Hi-Z
Description
Set pin of the SCK clock edge.
When this pin is “L” level, rising edge is available for input(SI) and falling
edge is available for output(SO).
When this pin is “H” level, falling edge is available for input(SI) and rising
edge is available for output(SO).
Chip select pin.
At the “L” level, data input/output is available.
Synchronous clock input pin for serial interface.
Input pin of synchronous serial data.
When the DIPH pin is “L” level, data is shifted in at the rising edges of
the SCK clock pulses.
When the DIPH pin is “H” level, data is shifted in at the falling edges of
the SCK clock pulses.
Output pin of synchronous serial data.
When the DIPH pin is “L” level, data is output at the falling edges of the
SCK clock pulses.
When the DIPH pin is “H” level, data is output at the rising edges of the
SCK clock pulses.
When the CSB pin is “H” level, this pin is Hi-Z state.
*1: Indicate the initial value during reset or power down.
PIN DESCRIPTION (FOR ML2286X I2C INTERFACE)
Pin
Symbol
I/O
Initial value
(*1)
5, 9, 12
SAD0
SAD1
SAD2
I
0
10
SCL
I
1
11
SDA
IO
1
Description
Set pin of the slave address.
Clock input pin for I2C serial interface.
This pin should be connected to pull-up resistor.
Input/output pin for I2C serial data.
Use for setting the mode of write/read and writing address, writing data
or reading data.
This pin should be connected to pull-up resistor.
(N-ch MOS) open drain, when output mode.
High impedance(Hi-Z), when input mode.
*1: Indicate the initial value during reset or power down.
6/27
FEDL228XXDIGEST-04
ML2282X-XXX/ ML2286X -XXX
ABSOLUTE MAXIMUM RATINGS
Parameter
Power supply voltage
Input voltage
Power dissipation
Output short-circuit
current
Storage temperature
Symbol
DVDD,
SPVDD
VIN
PD
IOS
TSTG
Condition
(DGND = SPGND = 0 V, Ta = 25°C)
Rating
Unit
0.3 to +7.0
—
V
0.3 to DVDD+0.3
V
938
mW
Applies to all pins except
SPM, SPP, VDDL, and VDDR.
10
mA
Applies to SPM and SPP
pins.
300
mA
50
mA
55 to +150
°C
—
Applies to VDDL and VDDR
pins.
—
RECOMMENDED OPERATING CONDITIONS
(DGND = SPGND = 0 V)
Parameter
Symbol
Condition
Range
Unit
Power supply voltage
DVDD,
SPVDD
—
2.7 to 3.6
4.5 to 5.5
V
Operating temperature
TOP
—
40 to +85
°C
Master clock frequency
fOSC
—
External capacitors for
crystal oscillator
Cd, Cg
—
Min.
Typ.
Max.
3.5
4.096
4.5
15
30
45
MHz
pF
7/27
FEDL228XXDIGEST-04
ML2282X-XXX/ ML2286X -XXX
ELECTRICAL CHARACTERISTICS
DC Characteristics (for the 3V applications)
Parameter
“H” input voltage
“L” input voltage
“H” output voltage 1
“H” output voltage 2 (*1)
“L” output voltage 1
“L” output voltage 2 (*1)
“L” output voltage 3 (*2)
“H” input current 1
“H” input current 2 (*3)
“H” input current 3 (*4)
“L” input current 1
“L” input current 2 (*3)
“L” input current 3 (*5)
“H” output leak current 3
(*6)
“L” output leak current 3
(*6)
Supply current during
playback
Power-down supply
current
Symbol
VIH
VIL
VOH1
VOH2
VOL1
VOL2
VOL3
IIH1
IIH2
IIH3
IIL1
IIL2
IIL3
DVDD = SPVDD = 2.7 to 3.6 V, DGND = AGND = 0 V, Ta = 40 to +85°C
Condition
Min.
Typ.
Max.
Unit
—
0.86DVDD
—
DVDD
V
—
0
—
0.14DVDD
V
IOH = 1 mA
DVDD0.4
—
—
V
IOH = 50 µA
DVDD0.4
—
—
V
IOL = 2 mA
—
—
0.4
V
IOL = 50 µA
—
—
0.4
V
IOL = 3 mA
—
—
0.4
V
VIH = DVDD
—
—
10
µA
VIH = DVDD
0.3
2.0
15
µA
VIH = DVDD
2
30
200
µA
VIL = GND
10
—
—
µA
VIL = GND
15
2.0
0.3
µA
VIL = GND
200
30
2
µA
IILOH
VOH = DVDD
—
—
10
µA
IILOL
VOL = GND
10
—
—
µA
—
—
20
mA
—
—
1
1
10
20
µA
µA
IDD
IDDS
fOSC = 4.096 MHz
No output load
Ta = 40 to +40°C
Ta = 40 to +85°C
*1: Applies to the XTB pin.
*2: Applies to the SCL, SDA pin.
*3: Applies to the XT pin.
*4: Applies to the TESTI0 pin.
*5: Applies to the RESETB pin.
*6: Applies to the TESTO pin.
8/27
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ML2282X-XXX/ ML2286X -XXX
DC Characteristics (for the 5V applications)
Parameter
“H” input voltage
“L” input voltage
“H” output voltage 1
“H” output voltage 2 (*1)
“L” output voltage 1
“L” output voltage 2 (*1)
“L” output voltage 3 (*2)
“H” input current 1
“H” input current 2 (*3)
“H” input current 3 (*4)
“L” input current 1
“L” input current 2 (*3)
“L” input current 3 (*5)
“L” output leak current 2
(*6)
“L” output leak current 3
(*6)
Supply current during
playback
Power-down supply
current
Symbol
VIH
VIL
VOH1
VOH2
VOL1
VOL2
VOL3
IIH1
IIH2
IIH3
IIL1
IIL2
IIL3
DVDD = SPVDD = 4.5 to 5.5 V, DGND = SPGND = 0 V, Ta = 40 to +85°C
Condition
Min.
Typ.
Max.
Unit
—
0.8DVDD
—
DVDD
V
—
0
—
0.2DVDD
V
IOH = 1 mA
DVDD0.4
—
—
V
IOH = 50µA
DVDD0.4
—
—
V
IOL = 2 mA
—
—
0.4
V
IOL = 50 µA
—
—
0.4
V
IOL = 3 mA
—
—
0.4
V
VIH = DVDD
—
—
10
µA
VIH = DVDD
0.8
5.0
20
µA
VIH = DVDD
20
100
400
µA
VIL = GND
10
—
—
µA
VIL = GND
20
5.0
0.8
µA
VIL = GND
400
100
20
µA
IILOH
VOH = DVDD
—
—
10
µA
IILOL
VOL = GND
10
—
—
µA
—
—
25
mA
—
—
1
1
15
30
µA
µA
IDD
IDDS
fOSC = 4.096 MHz
No output load
Ta = 20 to +40°C
Ta = 20 to +85°C
*1: Applies to the XTB pin.
*2: Applies to the SCL and SDA pins.
*3: Applies to the XT pin.
*4: Applies to the TESTI0 pin.
*5: Applies to the RESETB pin.
*6: Applies to the TESTO pin.
9/27
FEDL228XXDIGEST-04
ML2282X-XXX/ ML2286X -XXX
Characteristics of Analog Circuitry (for the 3V applications)
Parameter
AIN input resistance
AIN input voltage range
LINE output load
resistance
LINE output voltage
range
SG output voltage
SG output resistance
SPM, SPP output load
resistance
Speaker amplifier output
power
Output offset voltage
between SPM and SPP
with no signal present
Symbol
RAIN
VAIN
DVDD = SPVDD = 2.7 to 3.6 V, DGND = SPGND = 0 V, Ta = 40 to +85°C
Condition
Min.
Typ.
Max.
Unit

15
20
25
k


DVDD2/3
Vp-p
RLA
During 1/2 DVDD output
10


k
VAO
No output load
DVDD/6

DVDD5/6
V
VSG
RSG

During power down
0.95VDDL/2
57
VDDL/2
96
1.05VDDL/2
135
V
k
RLSP

8



PSPO
SPVDD = 3.3V, f = 1kHz
RSPO = 8, THD10%
100
300

mW
VOF
SPIN–SPM gain = 0dB
With a load of 8
50

+50
mV
Characteristics of Analog Circuitry (for the 5V applications)
Parameter
AIN input resistance
AIN input voltage range
LINE output load
resistance
LINE output voltage
range
SG output voltage
SG output resistance
SPM, SPP output load
resistance
Symbol
RAIN
VAIN
DVDD = SPVDD = 4.5 to 5.5 V, DGND = SPGND = 0 V, Ta = 20 to +85°C
Condition
Min.
Typ.
Max.
Unit

15
20
25
k


DVDD2/3
Vp-p
RLA
During 1/2 DVDD output
10


k
VAO
No output load
DVDD/6

DVDD5/6
V
VSG
RSG

During power down
0.95VDDL/2
57
VDDL/2
96
1.05VDDL/2
135
V
k
RLSP

8



Speaker amplifier output
power
PSPO
SPVDD = 5.0V, f = 1kHz
RSPO = 8, THD10%
Ta=25°C
500
700

mW
Output offset voltage
between SPM and SPP
with no signal present
VOF
SPIN–SPM gain = 0dB
With a load of 8
50

+50
mV
10/27
FEDL228XXDIGEST-04
ML2282X-XXX/ ML2286X -XXX
AC Characteristics (Common to All Products)
DVDD = SPVDD = 2.7 to 5.5 V, DGND = SPGND = 0 V, Ta = 40 to +85°C,
Applicable
Symbol
Condition
Min. Typ. Max. Unit
Parameter
command
Master clock duty cycle
fduty
—
40
50
60
%
RESETB input pulse width
tRST
—
100
—
—
s
Reset noise rejection pulse width
tNRST
—
—
—
0.1
s
STOP, SLOOP,
CLOOP, CVOL,
tINT
2
—
—
ms
AVOL
Command input interval time
fOSC = 4.096 MHz
PUP
tINTP
10
—
—
ms
Command input enable time
RDSTAT
(After status read)
SLOOP
Continuous play
by PLAY/MUON
tINTRD
500
—
—
s
tcm
fOSC = 4.096 MHz
—
—
10
ms
PUP
tPUP1
fOSC = 4.096 MHz
2.0
2.5
3.0
ms
PDWN
tPD1
fOSC = 4.096 MHz
—
—
20
s
tPOPA1
fOSC = 4.096 MHz
58
60
62
ms
tPOPA2
fOSC = 4.096 MHz
90
93
95
ms
tPDA1
fOSC = 4.096 MHz
108
110
112
ms
tPDA2
fOSC = 4.096 MHz
140
142
144
ms
tCB1
fOSC = 4.096 MHz
—
—
2
ms
2nd byte of AMODE
(POP = “0”
DAEN or SPEN
= “0” ”1”)
2nd byte of AMODE
(POP = “1”
DAEN
= “0” ”1”
CBUSYB “L” level output time
SPEN = “0”)
2nd byte of AMODE
(POP = “0”
DAEN or SPEN
= “1” ”0”)
2nd byte of AMODE
(POP = “1”
DAEN = “1” ”0”
SPEN = “0”)
)
(*1)
Note: Output pin load capacitance = 45 pF
*1:
Applies to cases where a command is input except after a PUP, PDWN, or 2nd byte of AMODE command
input.
11/27
FEDL228XXDIGEST-04
ML2282X-XXX/ ML2286X -XXX
AC Characteristics of Synchronous Serial Command Interface (Applied to ML2282X)
DVDD = SPVDD = 2.7 to 5.5 V, DGND = SPGND = 0 V, Ta = 40 to +85°C
Applicable
Symbol
Condition
Min. Typ. Max. Unit
Parameter
command
SCK input enable time from CSB fall edge
tESCK
—
100
—
—
ns
SCK hold time from CSB rise edge
tCSH
—
100
—
—
ns
Data floating time from CSB rise edge
tDOZ
RL = 3 k
—
—
100
ns
Data setup time from SCK rise edge
tDIS1
DIPH = “0”
50
—
—
ns
Data hold time from SCK rise edge
tDIH1
DIPH = “0”
50
—
—
ns
Data output delay time from SCK rise edge
tDOD1
RL = 3 k
—
—
80
ns
Data setup time from SCK fall edge
tDIS2
DIPH = “1”
50
—
—
ns
Data hold time from SCK fall edge
tDIH2
DIPH = “1”
50
—
—
ns
Data output delay time from SCK rise edge
tDOD2
RL = 3 k
—
—
80
ns
SCK “H” level pulse width
tSCKH
—
100
—
—
ns
SCK “L” level pulse width
tSCKL
—
100
—
—
ns
CBUSYB output delay time from SCK rise edge
tDBSY1
DIPH = “0”
—
—
150
ns
CBUSYB output delay time from SCK fall edge
tDBSY2
DIPH = “1”
—
—
150
ns
Note: Output pin load capacitance = 45 pF
12/27
FEDL228XXDIGEST-04
ML2282X-XXX/ ML2286X -XXX
AC Characteristics of I2C Command Interface (Applied to ML2286X)
DVDD = SPVDD = 2.7 to 5.5 V, DGND = SPGND = 0 V, Ta = 40 to +85°C
(High-speed mode)
Parameter
Symbol
Unit
Min.
Max.
SCL clock frequence
tSCL
0
400
kHz
Hold time (repeated) START condition
tHD;STA
0.6
—
s
After this period, the first clock pulse is generated.
SCL “L” level pulse width
tLOW
1.3
—
s
SCL “H” level pulse width
tHIGH
0.6
—
s
Setup time for repeated START condition
tSU;STA
0.6
—
s
Data hold time: For I2C bus devices
tHD;DAT
0
0.9
s
Data setup time
tSU;DAT
100
—
ns
SDA and SCL signal rise time
tr
20
300
ns
SDA and SCL signal fall time
tf
20
300
ns
STOP condition setup time
tSU;STO
0.6
—
s
Bus free time between STOP condition and START condition
tBUF
1.3
—
s
Capacitive load for each bus line
Cb
—
400
PF
0.1
Noise margin at a “L” level in each device connected (including
VnL
—
V
DVDD
hysteresis)
0.1
Noise margin at a “H” level in each device connected (including
VnH
—
V
DVDD
hysteresis)
Pulse width of spikes which must be suppressed by the input
filter
tsp
0
50
ns
Note: Output pin load capacitance = 45 pF
13/27
FEDL228XXDIGEST-04
ML2282X-XXX/ ML2286X -XXX
FUNCTIONAL DESCRIPTION
Synchronous Serial Command Interface
The CSB, SCK, SI, and SO pins are used to input the command data or to read the status. Driving the CSB pin
to “L” level enables the serial CPU interface.
After the CSB pin is driven to “L” level, the command data are input through the SI pin from the MSB
synchronized with the SCK clock. The command data shifts in through the SI pin at the rising or falling edge
of the SCK clock pulse. Then, a command is executed at the rising or falling edge of the eighth pulse of the
SCK clock.
As for status reading, status is output from the SO pin, synchronized with the SCK clock after the CSB pin is
driven to “L” level.
The SCK clock edge is specified by the input level of the DIPH pin.
- When the DIPH pin is “L” level, rising edge is available for input from SI pin and falling edge is available
for output from SO pin.
- When the DIPH pin is “H” level, falling edge is available for input from SI pin and rising edge is available
for output from SO pin.
It is possible to input command data, even if the CSB pin is fixed by “L” level. However, if unexpected pulses
caused by noise are induced through the SCK pin, SCK clock pulses are incorrectly counted, causing a failure in
normal recognition of command. Then it is recommended that the CSB pin is “L” level only for command
input.
The count of the SCK clock pulse is initialized when the CSB pin goes to “H” level.
Command Data Input or Status Read Timing
 When DIPH pin is “L” level
CSB
SCK
SI
D7
D6
D5
D4
D3
D2
D1
( MSB )
SO
D7
D0
(LSB)
D6
D5
D4
D3
D2
D1
D6
D5
D4
D3
D2
D1
D0
 When DIPH pin is “H” level
CSB
SCK
SI
D7
( MSB )
SO
D7
D0
(LSB)
D6
D5
D4
D3
D2
D1
D0
14/27
FEDL228XXDIGEST-04
ML2282X-XXX/ ML2286X -XXX
The following table shows the contents of each data output at a status read.
Output status signal
MSB

7SB

6SB
Channel 2 BUSYB output (BUSYB1)
5SB
Channel 1 BUSYB output (BUSYB0)
4SB

3SB

2SB
Channel 2 NCR output (NCR1)
LSB
Channel 1 NCR output (NCR0)
The BUSYB output is “L” level when a command is being processed or the playback of a particular channel is
going on. In other states, the BUSYB output is “H” level. The NCR output is “L” level when a command is
being processed or particular channel is in standby for playback. In other states, the NCR output is “H” level.
15/27
FEDL228XXDIGEST-04
ML2282X-XXX/ ML2286X -XXX
I2C Command Interface (Applies to ML2286X)
The I2C Interface built-in is an serial interface (: slave side) that is compliant with I2C bus specification. It
supports Fast mode and enables data transmission/reception at 400 kbps. The SCL and SDA pins are used to
input the command data or to read the status. Pins (:SAD0, 1 and 2) are used to set the slave address.
Pull-up resister should be connected to SCL pin and SDA pin.
For the master on the I2C bus to communicate with this device (: slave), input the slave address with the first
seven bits after setting the start condition. The upper three bits of the slave address can be set using the SAD0
to 2 pins. The eighth bit of slave address is used to set the direction (: write or read) of communication. If the
eighth bit is “0” level, it is write mode from master to slave. And, if the eighth bit is “1” level, it is read mode
from master.
The communication is made in the unit of byte. And acknowledge is needed for each byte.
The protocol of I2C communication is shown below.
 Command flow at data write
START condition
Slave address +W (0)
Write address (ex. 1st byte of a command)
Write data (ex. 2nd byte of a command)
STOP condition
 Data write timing
SCL
SDA
A6 A5 A4 A3 A2 A1 A0 W A D7 D6 D5 D4 D3 D2 D1 D0 A D7 D6 D5 D4 D3 D2 D1 D0 A
S
Slave Address
A
1st Command Data
A
2nd Command Data
A P
 Command flow at data read
Start condition
Slave address +R(1)
Read data (ex. Status read)
STOP condition
 Data read timing
SCL
SDA
A6 A5 A4 A3 A2 A1 A0 R A D7 D6D5 D4 D3 D2 D1 D0 A D7 D6 D5 D4 D3 D2 D1 D0 A
S
Slave Address
A
Read Data
A
Read Data
A
P
16/27
FEDL228XXDIGEST-04
ML2282X-XXX/ ML2286X -XXX
Setting of the slave address using the SAD0 to 2 pins
SAD2
SAD1
SAD0
Lower 4 bits
0
0
0
0101
0
0
1
0101
0
1
0
0101
0
1
1
0101
1
0
0
0101
1
0
1
0101
1
1
0
0101
1
1
1
0101
The following table shows the contents of each data output at a status read. Status is updated by the
RDSTAT command; therefore, be sure to input the RDSTAT command in order to read status.
Output status signal
MSB
7SB
6SB
Channel 2 BUSYB output (BUSYB1)
5SB
Channel 1 BUSYB output (BUSYB0)
4SB
3SB
2SB
Channel 2 NCR output (NCR1)
LSB
Channel 1 NCR output (NCR0)
The BUSYB signal is “L” level when either a command is being processed or the playback of a particular
channel is going on. In other states, the BUSYB signal is “H” level.
The NCR signal is “L” level when either a command is being processed or a particular channel is in standby for
playback. In other states, the NCR signal is “H” level.
17/27
FEDL228XXDIGEST-04
ML2282X-XXX/ ML2286X -XXX
Command List
Each command is configured by the unit of byte (8-bit).
PLAY, MUON, and CVOL, use two bytes.
Command
D7
D6
D5
D4
D3
D2
The following commands, AMODE, AVOL FADR,
D1
D0
PUP
0
0
0
0
0
0
S1
S0
PDWN
0
0
1
0
0
0
0
0
RDSTAT
1
0
1
1
0
0
0
0
0
0
0
0
0
1
0
0
AMODE
FAD
DAG1 DAG0 AIG1
AIG0 DAEN SPEN POP
Description
Power-up command.
Shifts from the power down state to
the command waiting state. Also,
sets the number of memory banks.
Power-down command.
Shifts form the command waiting
state to the power down state.
Status read command.
Reads the command status on each
channel.
Control command of analog circuitry.
Setoperation of
power-up/dpwn
and input/output.
Playback start command.
Use the data of the 2nd byte to
specify a phrase number. Can be
specified for each channel.
Playback stop command.
Can be set for each channel.
Set command of playback phrase.
Can be set for each channel.
Use START command to start.
Playback start command without
phrase spec. Use FADR command
to set phrase.Can start playback on
multiple channels simultaneously.
After played back by PLAY
command, the same phrase can be
played back with this command.
Silence insertion command.
Set the silent time length for each
channel using M7 to M0 bits in the
2nd byte.
Set command of repeat playback.
Setting is enabled during playback.
Can be specified for each channel.
Stop command of repeat playback.
Can be specified for each channel.
Also, repeat playback is released by
STOP command automatically.
0
1
0
0
F9
F8
0
CH
F7
F6
F5
F4
F3
F2
F1
F0
0
1
1
0
0
0
CH1
CH0
0
0
1
1
F9
F8
0
CH
F7
F6
F5
F4
F3
F2
F1
F0
0
1
0
1
0
0
CH1
CH0
0
1
1
1
0
0
CH1
CH0
M7
M6
M5
M4
M3
M2
M1
M0
SLOOP
1
0
0
0
0
0
CH1
CH0
CLOOP
1
0
0
1
0
0
CH1
CH0
1
0
1
0
0
0
CH1
0
0
0
CV4
CV3
CV2
CV1
CH0 Volume control command.
Set volume for each channel using
CV0 CV4 to CV0 bits in the 2nd byte.
0
0
0
0
1
0
0
0
0
AV5
AV4
AV3
AV2
AV1
PLAY
STOP
FADR
START
MUON
CVOL
AVOL
Analog volume control command.
Set volume after channel mixing
AV0 using AV5 to AV0 bits.
0
18/27
FEDL228XXDIGEST-04
ML2282X-XXX/ ML2286X -XXX
Voice Synthesis Algorithm
Four types of voice synthesis algorithm are supported. They are 4-bit ADPCM2, 8-bit non-linear PCM, 8-bit
straight PCM and 16-bit straight PCM. Select the best one according to the characteristics of playback voice.
The following table shows key features of each algorithm.
Voice synthesis
algorithm
Applied waveform
4-bit ADPCM2
Normal voice waveform
8-bit Nonlinear PCM
Waveform including
high frequency signals
(sound effect, etc.)
8-bit straight PCM
16-bit straight PCM
Feature
Up version of LAPIS Semiconductor’s specific voice
synthesis algorithm (: 4-bit ADPCM).
Voice quality is improved.
Algorithm, which plays back mid-range of waveform as
10-bit equivalent voice quality.
Normal 8-bit PCM algorithm
Normal 16-bit PCM algorithm
19/27
FEDL228XXDIGEST-04
ML2282X-XXX/ ML2286X -XXX
Memory Allocation and Creating Voice Data
The ROM is partitioned into four data areas: voice (i.e., phrase) control area, test area, voice area, and edit ROM
area.
The voice control area manages the voice data in the ROM. It contains data for controlling the start/stop
addresses of voice data for 1,024 phrases, use/non-use of the edit ROM function and so on.
The test area contains data for testing.
The voice area contains actual waveform data.
The edit ROM area contains data for effective use of voice data. For the details, refer to the section of “Edit
ROM Function.”
The edit ROM area is not available if the edit ROM is not used.
The ROM data is created using a dedicated tool.
Configuration of ROM data
0x00000
Voice control area
(Fixed 64 Kbits)
0x01FFF
0x02000
Test area
0x0205F
0x02060
Voice area
max: 0x1FFFFF
Edit ROM area
Depends on creation
of ROM data.
max: 0x1FFFFF
Playback Time and Memory Capacity
The playback time depends on the memory capacity, sampling frequency, and playback method.
The equation to know the playback time is shown below. But this is not applied if the edit ROM function is
used.
Playback time [sec] =
1.024  (Memory capacity – 64.75 [Kbits]
Sampling frequency [kHz]  Bit length
(Bit length is 4 at the 4-bit ADPCM2 and 8/16 at the PCM.)
Example) In the case that the sampling frequency is 16 kHz, algorithm is 4-bit ADPCM2 and ROM capacity
is 16 Mbits, the playback time is approx. 261 seconds, as shown below.
Playback time =
1.024(16834 – 64.75) [Kbits]
 261 [sec]
16 [kHz]  4 [bits]
20/27
FEDL228XXDIGEST-04
ML2282X-XXX/ ML2286X -XXX
Edit ROM Function
The edit ROM function makes it possible to play back multiple phrases in succession.
are set using the edit ROM function:
 Continuous playback:
 Silence insertion function:
The following functions
There is no limit to set the number of times of continuous playback.
depends on the memory capacity only.
20ms to 1,024 ms
It
It is possible to use voice ROM effectively to use the edit ROM function.
Below is an example of the ROM structure, case of using the edit ROM function.
Example 1)
Phrases using the Edit ROM Function
Phrase 1
A
B
D
Phrase 2
A
C
D
Phrase 3
E
B
D
Phrase 4
E
C
D
Phrase 5
A
Example 2)
B
D
Silence
E
C
D
Structure of the ROM that contents of Example 1 are stored
Address control area
A
B
C
D
E
Editing area
Mixing Function
It is possible to perform mixing of two channels simultaneously. And also, it is possible to specify PLAY,
STOP, and CVOL commands for each channel respectively. The mixing function is available if the sampling
frequency (FS) is 32 kHz or less.
- Precautions for Waveform Clamp
Adjust the volume of each channel using the CVOL command, if the waveform clamp is increased by channel
mixing.
21/27
FEDL228XXDIGEST-04
ML2282X-XXX/ ML2286X -XXX
Memory Bank Switching Function
The memory bank switching function enables the the built-in ROM area that is divivided into up to four banks to
be used. When four banks are used, the maximum number of phrases per bank is 1,024 so that up to 4096
phrases can be played back.
Using this function, multiple ROM codes can be grouped into one code.
The settings of SEL1 pin and SEL0 pin determines which memory bank is used. To playback phrases, the
number of memory banks must be specified in PUP.
When using a memory bank switching function, data must be divided and saved in the specified areas at ROM
data creation.
 When the number of memory banks is 1
SEL1
SEL0
ML22825
ML22865
ML22824
ML22864
ML22823
ML22863
0
0
00000h – 1FFFFFh
00000h – FFFFFh
00000h -7FFFFh
ML22824
ML22864
ML22823
ML22863
 When the number of memory banks is 2
SEL1
SEL0
ML22825
ML22865
0
0
00000h – FFFFFh
00000h – 7FFFFh
00000h – 3FFFFh
0
1
100000h – 1FFFFFh
80000h – FFFFFh
40000h – 7FFFFh
 When the number of memory banks is 4
SEL1
SEL0
ML22825
ML22865
ML22824
ML22864
ML22823
ML22863
0
0
00000h – 7FFFFh
00000h – 3FFFFh
00000h – 1FFFFh
0
1
80000h – FFFFFh
40000h – 7FFFFh
20000h – 3FFFFh
1
0
100000h – 17FFFFh
80000h – BFFFFh
40000h – 5FFFFh
1
1
180000h – 1FFFFFh
C0000h – FFFFFh
60000h – 7FFFFh
The memory (16 Mbits) in the ML22825 is divided as shown below.
0-7FFFFh
Bank 1
Capacity: 16 Mbits
Max. Phrase count: 1024
Bank 1
Capacity: 8 Mbits
Max. Phrase count: 1024
Bank 1
Capacity: 4 Mbits
Max. Phrase count: 1024
Bank 2
Capacity: 4 Mbits
Max. Phrase count: 1024
80000-FFFFFh
Bank 2
Capacity: 8 Mbits
Max. Phrase count: 1024
100000-17FFFFh
Bank 3
Capacity: 4 Mbits
Max. Phrase count: 1024
Bank 4
Capacity: 4 Mbits
Max. Phrase count: 1024
180000-1FFFFFh
Memory divide count: 1
16 Mbits  1 area
Memory divide count: 2
8 Mbits  2 areas
Memory divide count: 4
4 Mbits  4 areas
22/27
FEDL228XXDIGEST-04
ML2282X-XXX/ ML2286X -XXX
APPLICATION CIRCUIT (ML2282X: DVDD = SPVDD = 5V)
MCU
RESETB
CSB
SCK
SI
SO
CBUSYB
DIPH
SPM
SPP
Speaker
SG
TESTI1
AIN
0.1F
0.1F
TESTI0
33pF
XT
VDDL
VDDR
DVDD
SPVDD
4.096MHz
10F
0.1F
XTB
33pF
10F
0.1F
5V
DGND
SPGND
APPLICATION CIRCUIT (ML2282X: DVDD = SPVDD = 3V)
MCU
RESETB
CSB
SCK
SI
SO
CBUSYB
DIPH
TESTI1
SPM
SPP
Speaker
SG
0.1F
AIN
0.1 F
TESTI0
33pF
XT
VDDL
VDDR
DVDD
SPVDD
4.096MHz
0.1F
XTB
33pF
10F
DGND
SPGND
0.1F
0.1F
3V
23/27
FEDL228XXDIGEST-04
ML2282X-XXX/ ML2286X -XXX
APPLICATION CIRCUIT (ML2286X: DVDD=SPVDD=5V)
7k
7k
SCL
SDA
(CBUSYB)
MCU
SPM
SPP
Speaker
SAD2-0
SG
TESTI0
AIN
0.1F
0.1F
TESTI1
33pF
XT
VDDL
VDDR
DVDD
SPVDD
4.096MHz
10F
0.1F
XTB
33pF
10F
0.1F
5V
DGND
SPGND
APPLICATION CIRCUIT (ML2286X: DVDD=SPVDD=3V)
7k
7k
SCL
SDA
(CBUSYB)
MCU
SPM
SPP
Speaker
SAD2-0
SG
TESTI0
AIN
0.1F
0.1F
TESTI1
33pF
XT
VDDL
VDDR
DVDD
SPVDD
4.096MHz
0.1F
XTB
33pF
DGND
SPGND
0.1F
0.1F
10F
3V
24/27
FEDL228XXDIGEST-04
ML2282X-XXX/ ML2286X -XXX
PACKAGE DIMENSIONS
(Unit: mm)
Notes for Mounting the Surface Mount Type Package
The surface mount type packages are very susceptible to heat in reflow mounting and humidity absorbed in
storage. Therefore, before you perform reflow mounting, contact ROHM’s responsible sales person for the
product name, package name, pin number, package code and desired mounting conditions (reflow method,
temperature and times).
25/27
FEDL228XXDIGEST-04
ML2282X-XXX/ ML2286X -XXX
REVISION HISTORY
Page
Previous
Current
Edition
Edition
Description
Document No.
Date
PEDL2282XFULL-01
Dec. 17, 2007
–
–
Preliminary edition 1
FEDL228XXFULL-01
Apr. 18, 2008
–
–
Final edition 1
FEDL228XXFULL-02
May. 29, 2008
–
–
Final edition 2
1
1
2-channel mixing function
48kHz-> 32kHz
2
2
Power supply voltage
2.7 to 5.5V -> 2.7 to 3.6V / 4.5 to 5.5 V
10
10
LINE output voltage range
MAX. DVDD x 4/6 -> DVDD x 5/6
10
10
SG output resistance
Min 52 -> Min 57
10
10
AIN input voltage range(for the 5V app..)
Max. DVDD x 2/4 -> DVDD x 2/3
15
15
PUP(AMODE) -> POP(AMODE)
17
17
Correct ROM address and calculation
20,21
20,21
FEDL228XXFULL-03
Mar. 24, 2009
Modify application circuit
26/27
FEDL228XXDIGEST-04
ML2282X-XXX/ ML2286X -XXX
NOTICE
No copying or reproduction of this document, in part or in whole, is permitted without the consent of LAPIS
Semiconductor Co., Ltd.
The content specified herein is subject to change for improvement without notice.
The content specified herein is for the purpose of introducing LAPIS Semiconductor's products (hereinafter
"Products"). If you wish to use any such Product, please be sure to refer to the specifications, which can be
obtained from LAPIS Semiconductor upon request.
Examples of application circuits, circuit constants and any other information contained herein illustrate the
standard usage and operations of the Products. The peripheral conditions must be taken into account when
designing circuits for mass production.
Great care was taken in ensuring the accuracy of the information specified in this document. However, should
you incur any damage arising from any inaccuracy or misprint of such information, LAPIS Semiconductor
shall bear no responsibility for such damage.
The technical information specified herein is intended only to show the typical functions of and examples of
application circuits for the Products. LAPIS Semiconductor does not grant you, explicitly or implicitly, any
license to use or exercise intellectual property or other rights held by LAPIS Semiconductor and other parties.
LAPIS Semiconductor shall bear no responsibility whatsoever for any dispute arising from the use of such
technical information.
The Products specified in this document are intended to be used with general-use electronic equipment or
devices (such as audio visual equipment, office-automation equipment, communication devices, electronic
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While LAPIS Semiconductor always makes efforts to enhance the quality and reliability of its Products, a
Product may fail or malfunction for a variety of reasons.
Please be sure to implement in your equipment using the Products safety measures to guard against the
possibility of physical injury, fire or any other damage caused in the event of the failure of any Product, such
as derating, redundancy, fire control and fail-safe designs. LAPIS Semiconductor shall bear no responsibility
whatsoever for your use of any Product outside of the prescribed scope or not in accordance with the
instruction manual.
The Products are not designed or manufactured to be used with any equipment, device or system which
requires an extremely high level of reliability the failure or malfunction of which may result in a direct threat
to human life or create a risk of human injury (such as a medical instrument, transportation equipment,
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representative before purchasing.
If you intend to export or ship overseas any Product or technology specified herein that may be controlled
under the Foreign Exchange and the Foreign Trade Law, you will be required to obtain a license or permit
under the Law.
Copyright
2009 - 2011 LAPIS Semiconductor Co., Ltd.
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