Download datasheet for ML610402 by LAPIS Semiconductor

FEDL610403-01
Issue Date: Dec.6, 2010
ML610401/ML610402/ML610403
8-bit Microcontroller with a Built-in LCD driver
GENERAL DESCRIPTION
ML610401/ML610402/ML610403 is a high-performance 8-bit CMOS microcontroller into which peripheral circuits, such as
UART,melody driver, RC oscillation type A/D converter, and LCD driver, are incorporated around LAPIS Semiconductor
-original 8-bit CPU nX-U8/100. ML610401/ML610402/ML610403 operates in both high/low-speed mode and power-saving
mode, it is most suitable for battery operated products.
ML610401P/ ML610402P/ML610403P support industrial temperature -40C to +85C, are added to the product lineup.
FEATURES
 CPU
 8-bit RISC CPU (CPU name: nX-U8/100)
 Instruction system: 16-bit instructions
 Instruction set:
Transfer, arithmetic operations, comparison, logic operations, multiplication/division, bit
manipulations, bit logic operations, jump, conditional jump, call return stack manipulations, arithmetic
shift, and so on
 Minimum instruction execution time
30.5 s (@32.768 kHz system clock)
2s (@500kHz system clock)
 Internal memory
 Internal 6KByte Mask ROM (3K16 bits) (including unusable 256 Byte TEST area)
 Internal 192Byte Data RAM (1928 bits)
 Interrupt controller
 1 non-maskable interrupt sources
Internal source: 1 (Watch dog timer)
 17 maskable interrupt sources
Internal sources: 9 (Timer2, Timer3, UART0, Melody0, RC-A/D converter, TBC128Hz, TBC32Hz, TBC16Hz, TBC2Hz)
External sources: 8 (P00, P01, P02, P03, P50, P51, P52, P53)
(One interrupt request is generated from P50 to P53 interrupt sources.)
 Time base counter
 Low-speed time base counter 1 channel
Frequency compensation (Compensation range: Approx. 488ppm to +488ppm. Compensation accuracy: Approx.
0.48ppm)
 High-speed time base counter 1 channel

Watchdog timer
 Non-maskable interrupt and reset
 Free running
 Overflow period: 4 types selectable (125ms, 500ms, 2s, and 8s)
 Timers
 8 bits  2 channels (16-bit x 1 configuration available by using Timer2-3)
 Clock frequency measurement mode (in one channel of 16-bit configuration)
 Capture
 Time base capture  2 channels (4096 Hz to 32 Hz)
FEDL610403-01
LAPIS Semiconductor
ML610401/ML610402/ML610403
 UART
 TXD/RXD  1 channel
 Bit length, parity/no parity, odd parity/even parity, 1 stop bit/2 stop bits
 Positive logic/negative logic selectable
 Built-in baud rate generator
 Melody driver
 Scale: 29 types (Melody sound frequency: 508 Hz to 32.768 kHz)
 Tone length: 63 types
 Tempo: 15 types
 Buzzer output mode (4 output modes, 8 frequencies, 16 duty levels)
 RC oscillation type A/D converter
 16-bit counter
 Time division  2 channels
 General-purpose ports
 Input-only port  4 channels (including secondary functions)
 Output-only port
ML610401:  12 channels (including secondary functions)
ML610402:  8 channels (including secondary functions)
ML610403:  4 channels (including secondary functions)
 Input/output port  18 channels (including secondary functions)
 LCD driver
 The number of segments
ML610401: 55 dots max. (11seg5com, 12seg4com, 13seg3com, and 14seg2com selectable)
ML610402: 75 dots max. (15seg5com, 16seg4com, 17seg3com, and 18seg2com selectable)
ML610403: 95 dots max. (19seg5com, 20seg4com, 21seg3com, and 22seg2com selectable)
 1/1 to 1/5 duty
 1/2, 1/3 bias (built-in bias generation circuit)
 Frame frequency selecable: approx. 64Hz, 73Hz, 85Hz, and 102Hz
 Bias voltage multiplying clock selectable (8 types)
 LCD drive stop mode, LCD display mode, all LCDs on mode, and all LCDs off mode selectable
 Programmable display allocation function
 Reset
 Reset through the RESET_N pin
 Power-on reset generation when powered on
 Reset when oscillation stop of the low-speed clock is detected (Cancellation by a mask option is possible)
 Reset by the watchdog timer (WDT) overflow
 Clock
 Low-speed clock: Crystal oscillation (32.768 kHz)
(This LSI can not guarantee the operation withoug low-speed crystal oscillation clock)
 High-speed clock: Built-in RC oscillation (500 kHz)
 Power management
 HALT mode: Instruction execution by CPU is suspended (peripheral circuits are in operating states).
 STOP mode: Stop of low-speed oscillation and high-speed oscillation (Operations of CPU and peripheral circuits are
stopped.)
 High-speed Clock gear: The frequency of high-speed system clock can be changed by software (1/1, 1/2, 1/4, 1/8 of the
oscillation clock)
 Block Control Function: Resets and completely turns circuits of unused peripherals off.
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FEDL610403-01
LAPIS Semiconductor
ML610401/ML610402/ML610403
 Shipment
 Chip
ML610401WA
ML610402WA
ML610403WA
ML610401PWA
ML610402PWA
ML610403PWA
 64-pin plastic TQFP
ML610401TBZ03A
ML610402TBZ03A
ML610403TBZ03A
ML610401PTBZ03A
ML610402PTBZ03A
ML610403PTBZ03A
xxx: ROM code number
P: Wide range temperature version
WA: Chip
TBZ03A: TQFP
 Guaranteed operating range
 Operating temperature: 20C to +70C (P version: C to +85C)
 Operating voltage: VDD = 1.25V to 3.6V
3/31
FEDL610403-01
LAPIS Semiconductor
ML610401/ML610402/ML610403
ML610401/ML610402/ML610403 Block Diagram
Figure 1 show the block diagram of the ML610401/ML610402/ML610403.
"*" indicates the secondary function of each port.
"(*1)" 11seg×5com, 12seg×4com, 13seg×3com, and 14seg×2com selectable
"(*2)" 15seg×5com, 16seg×4com, 17seg×3com, and 18seg×2com selectable
"(*3)" 19seg×5com, 20seg×4com, 21seg×3com, and 22seg×2com selectable
CPU (nX-U8/100)
EPSW1 3
GREG
0 15
PSW
Timing
Controller
DSR/CSR
EA
PC
Instruction
Register
BUS
Controller
Program
Memory
(ROM)
6Kbyte
Data-bus
RAM
192byte
RESET &
TEST
Interrupt
Controller
XT0
XT1
INT
1
OSC
LSCLK*
OUTCLK*
IN0*
CS0*
RS0*
RT0*
CRT0*
RCM*
IN1*
CS1*
RS1*
RT1*
LR
SP
VDD
VSS
VDDL
ECSR1 3
ALU
Instruction
Decoder
RESET_N
TEST0
ELR1 3
INT
4
RC-ADC
2
UART
RXD0*
TXD0*
Melody/
Buzzer
MD0*
INT
5
P00 to P03
P20 to P22, P24
P30 to P35
P40 to P47
P50 to P53
P60 to P67 (ML610401)
P60 to P63 (ML610402)
TBC
Capture
2
INT
2
INT
1
WDT
Power
INT
1
INT
1
GPIO
8bit Timer
2
Display
Allocation
RAM
Display
register
176bit
LCD
Driver
COM0 to COM4 (*1)(*2)(*3)
SEG0 to SEG13 (ML610401) (*1)
SEG0 to SEG17 (ML610402) (*2)
SEG0 to SEG21 (ML610403) (*3)
LCD
BIAS
VL1, VL2, VL3
C1, C2
Figure 1 ML610401/ML610402/ML610403 Block Diagram
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FEDL610403-01
LAPIS Semiconductor
ML610401/ML610402/ML610403
PIN CONFIGURATION
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
P00
P24
P22
P21
P20
VSS
P60
P61
P62
P63
P64
P65
P66
P67
SEG13
SEG12
ML610401 TQFP64 Pin Layout
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
SEG11
SEG10
SEG9
SEG8
SEG7
SEG6
SEG5
SEG4
SEG3
COM4/SEG2
COM3/SEG1
COM2/SEG0
COM1
COM0
C2
C1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
P43
P44
P45
P46
P47
VDD
VSS
VDDL
(NC)
XT0
XT1
RESET_N
TEST0
VL1
VL2
VL3
P01
P02
P03
P30
P31
P34
P32
P33
P35
P53
P52
P51
P50
P40
P41
P42
Note:
The assignment of the P30 to P35 are not in order.
Figure 2 ML610401 TQFP64 Pin Configuration
5/31
FEDL610403-01
LAPIS Semiconductor
ML610401/ML610402/ML610403
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
P00
P24
P22
P21
P20
VSS
P60
P61
P62
P63
SEG17
SEG16
SEG15
SEG14
SEG13
SEG12
ML610402 TQFP64 Pin Layout
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
SEG11
SEG10
SEG9
SEG8
SEG7
SEG6
SEG5
SEG4
SEG3
COM4/SEG2
COM3/SEG1
COM2/SEG0
COM1
COM0
C2
C1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
P43
P44
P45
P46
P47
VDD
VSS
VDDL
(NC)
XT0
XT1
RESET_N
TEST0
VL1
VL2
VL3
P01
P02
P03
P30
P31
P34
P32
P33
P35
P53
P52
P51
P50
P40
P41
P42
Note:
The assignment of the P30 to P35 are not in order.
Figure 3 ML610402 TQFP64 Pin Configuration
6/31
FEDL610403-01
LAPIS Semiconductor
ML610401/ML610402/ML610403
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
P00
P24
P22
P21
P20
VSS
SEG21
SEG20
SEG19
SEG18
SEG17
SEG16
SEG15
SEG14
SEG13
SEG12
ML610403 TQFP64 Pin Layout
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
SEG11
SEG10
SEG9
SEG8
SEG7
SEG6
SEG5
SEG4
SEG3
COM4/SEG2
COM3/SEG1
COM2/SEG0
COM1
COM0
C2
C1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
P43
P44
P45
P46
P47
VDD
VSS
VDDL
(NC)
XT0
XT1
RESET_N
TEST0
VL1
VL2
VL3
P01
P02
P03
P30
P31
P34
P32
P33
P35
P53
P52
P51
P50
P40
P41
P42
Note:
The assignment of the P30 to P35 are not in order.
Figure 4 ML610403 TQFP64 Pin Configuration
7/31
FEDL610403-01
LAPIS Semiconductor
ML610401/ML610402/ML610403
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
P00
P24
P22
P21
P20
VSS
P60
P61
P62
P63
P64
P65
P66
P67
SEG13
SEG12
ML610401 Chip Pin Layout & Dimension
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
XT1
RESET_N
TEST0
VL1
VL2
VL3
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
P43
P44
P45
P46
P47
VDD
VSS
VDDL
XT0
P01
P02
P03
P30
P31
P34
P32
P33
P35
P53
P52
P51
P50
P40
P41
P42
SEG11
SEG10
SEG9
SEG8
SEG7
SEG6
SEG5
SEG4
1.75mm
SEG3
COM4/SEG2
COM3/SEG1
COM2/SEG0
COM1
COM0
C2
C1
Y
1.82mm
X
Note:
The assignment of the pads P30 to P35 are not in order.
Chip size: 1.82 mm × 1.75 mm
PAD count: 63 pins
Minimum PAD pitch: 80m
PAD aperture: 70m×70m
Chip thickness: 350m
Voltage of the rear side of chip: VSS level.
Figure 5 ML610401 Chip Layout & Dimension
8/31
FEDL610403-01
LAPIS Semiconductor
ML610401/ML610402/ML610403
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
P00
P24
P22
P21
P20
VSS
P60
P61
P62
P63
SEG17
SEG16
SEG15
SEG14
SEG13
SEG12
ML610402 Chip Pin Layout & Dimension
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
XT1
RESET_N
TEST0
VL1
VL2
VL3
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
P43
P44
P45
P46
P47
VDD
VSS
VDDL
XT0
P01
P02
P03
P30
P31
P34
P32
P33
P35
P53
P52
P51
P50
P40
P41
P42
SEG11
SEG10
SEG9
SEG8
SEG7
SEG6
SEG5
SEG4
1.75mm
SEG3
COM4/SEG2
COM3/SEG1
COM2/SEG0
COM1
COM0
C2
C1
Y
1.82mm
X
Note:
The assignment of the pads P30 to P35 are not in order.
Chip size: 1.82 mm × 1.75 mm
PAD count: 63 pins
Minimum PAD pitch: 80m
PAD aperture: 70m×70m
Chip thickness: 350m
Voltage of the rear side of chip: VSS level.
Figure 6 ML610402 Chip Layout & Dimension
9/31
FEDL610403-01
LAPIS Semiconductor
ML610401/ML610402/ML610403
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
P00
P24
P22
P21
P20
VSS
SEG21
SEG20
SEG19
SEG18
SEG17
SEG16
SEG15
SEG14
SEG13
SEG12
ML610403 Chip Pin Layout & Dimension
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
XT1
RESET_N
TEST0
VL1
VL2
VL3
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
P43
P44
P45
P46
P47
VDD
VSS
VDDL
XT0
P01
P02
P03
P30
P31
P34
P32
P33
P35
P53
P52
P51
P50
P40
P41
P42
SEG11
SEG10
SEG9
SEG8
SEG7
SEG6
SEG5
SEG4
1.75mm
SEG3
COM4/SEG2
COM3/SEG1
COM2/SEG0
COM1
COM0
C2
C1
Y
1.82mm
X
Note:
The assignment of the pads P30 to P35 are not in order.
Chip size: 1.82 mm × 1.75 mm
PAD count: 63 pins
Minimum PAD pitch: 80 m
PAD aperture: 70 m×70 m
Chip thickness: 350 m
Voltage of the rear side of chip: VSS level.
Figure 7 ML610403 Chip Layout & Dimension
10/31
FEDL610403-01
LAPIS Semiconductor
ML610401/ML610402/ML610403
ML610401/ML610402/ML610403 Pad Coordinates
Table 1 ML610401/ML610402/ML610403 Pad Coordinates
PAD
No.
Pad
Name
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
P43
P44
P45
P46
P47
VDD
VSS
VDDL
XT0
XT1
RESET_N
TEST0
VL1
VL2
VL3
C1
C2
COM0
COM1
COM2/SEG0
COM3/SEG1
COM4/SEG2
SEG3
SEG4
SEG5
SEG6
SEG7
SEG8
SEG9
SEG10
SEG11
SEG12
SEG13
P67 (*1)
SEG14 (*2)(*3)
34
(*1)
ML610401/2/3
X ( m)
Y ( m)
-598
-518
-438
-358
-278
-198
-118
-38
42
202
282
362
522
602
682
804
804
804
804
804
804
804
804
804
804
804
804
804
804
804
804
645
565
-769
-769
-769
-769
-769
-769
-769
-769
-769
-769
-769
-769
-769
-769
-769
-600
-520
-440
-360
-280
-200
-120
-40
40
120
200
280
360
440
520
600
769
769
455
769
PAD
No.
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
Pad
Name
P66 (*1)
SEG15 (*2)(*3)
P65 (*1)
SEG16 (*2)(*3)
P64 (*1)
SEG17 (*2)(*3)
P63 (*1)(*2)
SEG18 (*3)
P62 (*1)(*2)
SEG19 (*3)
P61 (*1)(*2)
SEG20 (*3)
P60 (*1)(*2)
SEG21 (*3)
VSS
P20
P21
P22
P24
P00
P01
P02
P03
P30
P31
P34
P32
P33
P35
P53
P52
P51
P50
P40
P41
P42
Chip Center: X=0,Y=0
ML610401/2/3
X ( m)
Y ( m)
375
769
295
769
215
769
135
769
55
769
-25
769
-105
769
-185
-265
-345
-425
-505
-605
-804
-804
-804
-804
-804
-804
-804
-804
-804
-804
-804
-804
-804
-804
-804
-804
769
769
769
769
769
769
600
520
440
360
280
200
120
40
-40
-120
-200
-280
-360
-440
-520
-600
ML610401 pad name, (*2) ML610402 pad name, (*3) ML610403 pad name
11/31
FEDL610403-01
LAPIS Semiconductor
ML610401/ML610402/ML610403
PIN LIST
Primary function
PIN
No.
PAD
No.
Pin name
I/O
Function
7,43
6
7,42
6
Vss
VDD


8
8
VDDL

14
13
VL1

15
14
VL2

16
15
VL3

17
16
C1

18
17
C2

13
12
10
11
12
11
9
10
TEST0
RESET_N
XT0
XT1
I
I
I
O
48
47
P00/EXI0/
CAP0
I
49
48
P01/EXI1/
CAP1
I
50
49
P02/EXI2/
RXD0
I
51
50
P03/EXI3
I
Negative power supply pin
Positive power supply pin
Power supply pin for internal logic
(internally generated)
Power supply pin for LCD bias
(internally generated or connected
to positive power supply pin)(*2)
Power supply pin for LCD bias
(internally generated or connected
to positive power supply pin)(*2)
Power supply pin for LCD bias
(internally generated)
Capacitor connection pin for LCD
bias generation
Capacitor connection pin for LCD
bias generation
Test pin
Reset input pin
Low-speed clock oscillation pin
Low-speed clock oscillation pin
Input port,
External interrupt,
Capture 0 input
Input port,
External interrupt,
Capture 1 input
Input port,
External interrupt,
UART0 received data
Input port,
External interrupt
Secondary function
Pin
name


I/O
Function














































LSCL
K
OUTC
LK
MD0

44
43
P20/LED0
O
Output port
45
44
P21/LED1
O
Output port
46
47
45
46
P22/LED2
P24/LED4
O
O
Output port
Output port
52
51
P30
I/O
Input/output port
IN0
I
53
52
P31
I/O
Input/output port
CS0
O
54
53
P34
I/O
Input/output port
RCT0
O
55
54
P32
I/O
Input/output port
RS0
O
56
55
P33
I/O
Input/output port
57
62
63
64
1
56
61
62
63
1
P35
P40
P41
P42
P43
I/O
I/O
I/O
I/O
I/O
2
2
P44/T2CK
I/O
3
3
P45/T3CK
I/O
Input/output port
Input/output port
Input/output port
Input/output port
Input/output port
Input/output port,
Timer2 external clock input
Input/output port,
Timer3 external clock input
4
4
P46
I/O
5
5
P47
I/O
61
60
P50/EXI8
I/O
60
59
P51/EXI8
I/O
O
Low-speed clock output
O
High-speed clock output
O

Melody 0 output

RC type ADC0 oscillation
input pin
RC type ADC0 reference
capacitor connection pin
RC type ADC0 resistor/capacitor
sensor connection pin
RC type ADC0 reference resistor
connection pin
RC type ADC0 measurement
resistor sensor connection pin
RC type ADC oscillation monitor


UART data input
UART data output
RC type ADC1 oscillation
input pin
RC type ADC1 reference
capacitor connection pin
RC type ADC1 reference resistor
connection pin
RC type ADC1 measurement
resistor sensor connection pin
RT0
O
RCM


RXD0
TXD0
O


I
O
IN1
I
CS1
O
Input/output port
RS1
O
Input/output port
RT1
O
MD0
O


Input/output port,
External interrupt
Input/output port,
External interrupt
Melody 0 output

12/31
FEDL610403-01
LAPIS Semiconductor
ML610401/ML610402/ML610403
Primary function
PIN
No.
PAD
No.
Pin name
I/O
59
58
P52/EXI8
I/O
58
57
P53/EXI8
I/O
19
20
18
19
21
20
22
21
23
22
24
25
26
27
28
29
30
31
32
33
34
23
24
25
26
27
28
29
30
31
32
33
35
34
36
35
37
36
38
37
39
38
40
39
41
40
42
41
COM0
COM1
COM2/SEG
0
COM3/SEG
1
COM4/SEG
2
SEG3
SEG4
SEG5
SEG6
SEG7
SEG8
SEG9
SEG10
SEG11
SEG12
SEG13
P67(*2)
SEG14(*3)
P66(*2)
SEG15(*3)
P65(*2)
SEG16(*3)
P64(*2)
SEG17(*3)
P63(*4)
SEG18(*5)
P62(*4)
SEG19(*5)
P61(*4)
SEG20(*5)
P60(*4)
SEG21(*5)
Function
Secondary function
Pin
name
I/O
Function






O
O
Input/output port,
External interrupt
Input/output port,
External interrupt
LCD common pin
LCD common pin






O
LCD common/segment pin



O
LCD common/segment pin



O
LCD common/segment pin



O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
LCD segment pin
LCD segment pin
LCD segment pin
LCD segment pin
LCD segment pin
LCD segment pin
LCD segment pin
LCD segment pin
LCD segment pin
LCD segment pin
LCD segment pin
Output port
LCD segment pin
Output port
LCD segment pin
Output port
LCD segment pin
Output port
LCD segment pin
Output port
LCD segment pin
Output port
LCD segment pin
Output port
LCD segment pin
Output port
LCD segment pin

















































































1
(* ) Internally generated, or connect to either positive power supply pin (VDD) or power supply pin for internal logic
(VDDL). For details, see user’s manual.
2
(* ) Pin for ML610401/ML610402.
3
(* ) Pin for ML610403.
4
(* ) Pin for ML610401.
5
(* ) Pin for ML610402/ML610403.
13/31
FEDL610403-01
LAPIS Semiconductor
ML610401/ML610402/ML610403
PIN DESCRIPTION
Pin name
I/O
Description
Primary/
Secondary/
Tertiary
Logic
—
Negative
—
—
—
—
Secondary
—
Secondary
—
Primary
Positive
Primary
Positive
Primary
Positive
Primary
Positive
Primary
Positive
Primary
Positive
Primary
Positive
System
Reset input pin. When this pin is set to a “L” level, system reset mode is
set and the internal section is initialized. When this pin is set to a “H” level
subsequently, program execution starts. A pull-up resistor is internally
connected.
Crystal
connection pin for low-speed clock.
XT0
I
A
32.768
kHz crystal oscillator (see measuring circuit 1) is connected to
XT1
O
this pin. Capacitors CDL and CGL are connected across this pin and VSS.
LSCLK
O Low-speed clock output pin. This pin is used as the secondary function of
the P20 pin.
OUTCLK
O High-speed clock output pin. This pin is used as the secondary function of
the P21 pin.
General-purpose input port
RESET_N
I
P00-P03
I General-purpose input port.
General-purpose output port
P20-P22,P24 O General-purpose output port.
Since these pins have secondary functions, the pins cannot be used as a
port when the secondary functions are used.
General-purpose input/output port
P30-P35
I/O General-purpose input/output port.
Since these pins have secondary functions, the pins cannot be used as a
port when the secondary functions are used.
P40-P47
I/O General-purpose input/output port.
Since these pins have secondary functions, the pins cannot be used as a
port when the secondary functions are used.
P50-P53
I/O General-purpose input/output port.
Since these pins have secondary functions, the pins cannot be used as a
port when the secondary functions are used.
P60-P63
O General-purpose output port.
These pins are for the ML610401/ML610402, but are not provided in the
ML610403.
P64-P67
O General-purpose output port.
These pins are for the ML610401, but are not provided in the
ML610402/ML610403.
14/31
FEDL610403-01
LAPIS Semiconductor
Pin name
I/O
UART
TXD0
O
RXD0
I
External interrupt
EXI0-3
I
EXI8
Capture
CAP0
I
CAP1
I
Timer
T2CK
I
T3CK
I
ML610401/ML610402/ML610403
Primary/
Secondary/
Tertiary
Logic
Secondary
Positive
Primary/
Secondary
Positive
External maskable interrupt input pins. Interrupt enable and edge
selection can be performed for each bit by software. These pins are used
as the primary functions of the P00-P03 pins.
External maskable interrupt input pins. Interrupt enable and edge
selection can be performed for each bit by software. These pins are used
as the primary functions of the P50-P53 pins.
Primary
Positive/
negative
Primary
Positive/
negative
Capture trigger input pins. The value of the time base counter is captured
in the register synchronously with the interrupt edge selected by software.
These pins are used as the primary functions of the P00 pin(CAP0) and
P01 pin(CAP1).
Primary
Positive/
negative
Positive/
negative
Description
UART data output pin. This pin is used as the secondary function of the
P43 pin.
UART data input pin. This pin is used as the secondary function of the
P42 or the primary function of the P02 pin.
External clock input pin used for Timer 2. The clock for this timer is
selected by software. This pin is used as the primary function of the P44
pin.
External clock input pin used for Timer 3. The clock for this timer is
selected by software. This pin is used as the primary function of the P45
pin.
Melody
MD0
O
Melody/Buzzer signal output pin. This pin is used as the secondary
function of the P22 pin and P50 pin.
LED drive
LED0-2,4
O
Nch open drain output pins to drive LED.
Primary
Primary
—
Primary
—
Secondary Positive/
negative
Primary
Positive/
negative
15/31
FEDL610403-01
LAPIS Semiconductor
Pin name
I/O
ML610401/ML610402/ML610403
Description
RC oscillation type A/D converter
IN0
I Channel 0 oscillation input pin. This pin is used as the secondary function
of the P30 pin.
CS0
O Channel 0 reference capacitor connection pin. This pin is used as the
secondary function of the P31 pin.
RCT0
O Resistor/capacitor sensor connection pin of Channel 0 for measurement.
This pin is used as the secondary function of the P34 pin.
RS0
O This pin is used as the secondary function of the P32 pin which is the
reference resistor connection pin of Channel 0.
RT0
O Resistor sensor connection pin of Channel 0 for measurement. This pin is
used as the secondary function of the P33 pin.
RCM
O RC oscillation monitor pin. This pin is used as the secondary function of
the P35 pin.
IN1
I Oscillation input pin of Channel 1. This pin is used as the secondary
function of the P44 pin.
CS1
O Reference capacitor connection pin of Channel 1. This pin is used as the
secondary function of the P45 pin.
RS1
O Reference resistor connection pin of Channel 1. This pin is used as the
secondary function of the P46 pin.
Resistor
sensor connection pin for measurement of Channel 1. This pin is
RT1
O
used as the secondary function of the P47 pin.
LCD drive signal
COM0-4
O Common output pins.
SEG0-13
O Segment output pins.
Segment output pin. These pins are for the ML610402/ML610403, but are
not provided in the ML610401.
SEG18-21
O Segment output pin. These pins are for the ML610403, but are not
provided in the ML610401/ML610402.
LCD driver power supply
VL1
— Power supply pins for LCD bias (internally generated or positive power
VL2
— supply pin connected ). Depending on LCD Bias setting and VDD voltage
level, VDD or VDDL or capacitor is connected. For details of the connection
VL3
— method, see user’s manual.
C1
— Power supply pins for LCD bias (internally generated). Capacitors C12 is
connected between C1 and C2.
C2
—
For testing
TEST0
I/O Input/output pin for testing. A pull-down resistor is internally connected.
SEG14-17
O
Power supply
VSS
—
VDD
—
VDDL
—
Negative power supply pin.
Positive power supply pin for I/O, internal regulator, battery low detector,
and power-on reset.
Positive power supply pin (internally generated) for internal logic.
Capacitor CL (see Appendix C measuring circuit 1) is connected between
this pin and VSS.
Primary/
Secondary/
Tertiary
Secondary
Secondary
Secondary
Secondary
Secondary
Secondary
Secondary
Secondary
Secondary
Secondary
Logic
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
16/31
FEDL610403-01
LAPIS Semiconductor
ML610401/ML610402/ML610403
TERMINATION OF UNUSED PINS
Table 2 shows methods of terminating the unused pins.
Table 2
Pin
VL1, VL2, VL3
C1, C2
RESET_N
TEST0
P00 to P03
P20 to P22, P24
P30 to P35
P40 to P47
P50 to P53
P60 to P67
COM0 to 4
SEG0 to 21
Termination of Unused Pins
Recommended pin termination
Open
Open
Open
Open
VDD or VSS
Open
Open
Open
Open
Open
Open
Open
Note:
It is recommended to set the unused input ports and input/output ports to the inputs with pull-down resistors/pull-up resistors or
the output mode since the supply current may become excessively large if the pins are left open in the high impedance input
setting.
17/31
FEDL610403-01
LAPIS Semiconductor
ML610401/ML610402/ML610403
ELECTRICAL CHARACTERISTICS
ABSOLUTE MAXIMUM RATINGS
(VSS = 0V)
Parameter
Symbol
Condition
Rating
Unit
Power supply voltage 1
VDD
Ta = 25C
0.3 to +4.6
V
Power supply voltage 2
VDDL
Ta = 25C
0.3 to +3.6
V
Power supply voltage 3
VL1
Ta = 25C
0.3 to +2.0
V
Power supply voltage 4
VL2
Ta = 25C
0.3 to +4.0
V
Power supply voltage 5
VL3
Ta = 25C
0.3 to +6.0
V
VIN
Ta = 25C
0.3 to VDD+0.3
V
Output voltage
VOUT
Ta = 25C
0.3 to VDD+0.3
V
Output current 1
IOUT1
Port3–6, Ta = 25C
12 to +11
mA
Output current 2
IOUT2
Port2, Ta = 25C
12 to +20
mA
Power dissipation
PD
Ta = 25C
0.9
W
Storage temperature
TSTG

55 to +150
C
Input voltage
RECOMMENDED OPERATING CONDITIONS
(VSS = 0V)
Parameter
Symbol
Condition
Range
20 to +70
40 to +85
1.25 to 3.6
30k to 625k
Unit
V
Hz
Operating temperature
TOP
Operating voltage
Operating frequency (CPU)
Low-speed crystal oscillation
frequency
Low-speed crystal oscillation
external capacitor
Capacitor externally connected to
VDDL pin
Capacitors externally connected to
VL1, 2, 3 pins
Capacitors externally connected
across C1 and C2 pins
VDD
fOP
non-P version
P version
fOP = 30k to 625kHz
VDD = 1.25 to 3.6V
fXTL

32.768k
Hz
CDL
CGL


3 to 18
3 to 18
pF
CL

0.4730%
F
Ca, b, c

0.130%
F
C12

0.4730%
F
C
18/31
FEDL610403-01
LAPIS Semiconductor
ML610401/ML610402/ML610403
DC CHARACTERISTICS (1/5)
(VDD = 1.25 to 3.6V, VSS = 0V, Ta = 20 to +70C, Ta = 40 to +85C for P version, unless otherwise specified)
Measuring
Rating
Parameter
Symbol
Condition
Unit
circuit
Min.
Typ.
Max.
Typ.
Typ.
500
Ta = 25C
10%
10%
VDD = 1.25
500kHz/2MHz RC oscillation
kHz
fRC
frequency
to 3.6V
Typ.
Typ.
3
500
*
25%
25%
Low-speed crystal oscillation
TXTL


0.6
2
s
2
start time*
500kHz/2MHz RC oscillation
TRC



3
s
1
start time
Low-speed oscillation stop

12
16.4
41
ms
TSTOP
*1
detect time
Reset pulse width
PRST

200


s
Reset noise elimination



0.3
PNRST
pulse width
Power-on reset activation
TPOR



10
ms
power rise time
1
* : When low-speed crystal oscillation stops for a duration more than the low-speed oscillation stop detect time, the system is
reset to shift to system reset mode.
2
* : Use 32.768KHz Crystal resonator DT-26 (Load capacitance 6pF) (made by KDS:DAISHINKU CORP.) is used
(CGL=CDL=12pF).
3
* : Recommended operating temperature (Ta = 20 to +70C, Ta = 40 to +85C for P version)
RESET
VIL1
RESET_N
VIL1
PRST
RESET_N pin reset
0.9xVDD
VDD
0.1xVDD
TPOR
Power on reset
19/31
FEDL610403-01
LAPIS Semiconductor
ML610401/ML610402/ML610403
DC CHARACTERISTICS (2/5)
(VDD = 1.25 to 3.6V, VSS = 0V, Ta = 20 to +70C, Ta = 40 to +85C for P version, unless otherwise specified)
Measuring
Rating
Parameter
Symbol
Condition
Unit
circuit
Min.
Typ.
Max.
VDDL voltage
VDDL
fOP = 30k to 625kHz
1.1
1.2
1.3
V
VDDL temperature
1
VDD = 3.0V

-1

mV/C
VDDL
1
deviation *
VDDL voltage


5
20
mV/V
VDDL
1
dependency *
1
* :VDDL can not exceed VDD level. The maximum VDDL becomes VDD level when the VDDL calculated by the temperature
deviation and voltage dependency is going to exceed the VDD level.
20/31
FEDL610403-01
LAPIS Semiconductor
ML610401/ML610402/ML610403
DC CHARACTERISTICS (3/5)
Parameter
Supply current 1
Supply current 2
Supply current 3
Supply current 4
Symbol
IDD1
IDD2
IDD3
IDD4
(VDD = 3.0V, VSS = 0V, Ta = 20 to +70C, Ta = 40 to +85C for P version)
Measuring
Rating
Condition
Unit
circuit
Min.
Typ.
Max.
CPU: In STOP state.
Low-speed/high-speed RC500kHz
oscillation: stopped.
CPU: In HALT state (LTBC and WDT
3 4
are Operating).* *
High-speed 500kHz oscillation:
Stopped.
6
LCD and BIAS circuits: Operating. *
CPU: In 32.768kHz operating
1 3
state.* *
High-speed 500kHz oscillation:
Stopped.
2
LCD and BIAS circuits: Operating. *
CPU: In RC 500kHz operating state.
2
LCD and BIAS circuits: Operating. *
Ta= 25C

0.3
0.8
A
5
*


3
Ta= 25C

0.9
1.8
A
5
*


4
1
Ta= 25C

3
6
A
5
*


9
Ta= 25C

50
70
A
5
*


80
1
* : When the CPU operating rate is 100% (No HALT state).
2
* : All SEGs: off waveform, No LCD panel load, 1/3 bias, 1/3 duty, Frame frequency: Approx. 64 Hz, Bias voltage multiplying
clock: 1/128 LSCLK (256Hz)
3
* : Use 32.768KHz Crystal resonator DT-26 (Load capacitance 6pF) (made by KDS:DAISHINKU CORP.) is used (CGL=CDL=6pF)
4
* : Significant bits of BLKCON0~BLKCON4 registers except DLCD bit on BLKCON4 are all “1”.
5
* : Recommended operating temperature (Ta = 20 to +70C, Ta = 40 to +85C for P version)
6
* : LCD Stop mode, 1/3 bias, Bias voltage multiplying clock: 1/128 LSCLK (256Hz)
21/31
FEDL610403-01
LAPIS Semiconductor
ML610401/ML610402/ML610403
DC CHARACTERISTICS (4/5)
(VDD = 1.25 to 3.6V, VSS = 0V, Ta = 20 to +70C, Ta = 40 to +85C for P version, unless otherwise specified)
Rating
Measuring
Parameter
Symbol
Condition
Unit
circuit
Min.
Typ.
Max.
Output voltage 1
(P20–P22,P24/
nd
2 function is
selected)
(P30–P35)
(P40–P47)
(P50–P53)
*1 *2
(P60-P63)
*1
(P64-P67)
Output voltage 2
(P20–P22,P24/
nd
2 function is Not
selected)
Output voltage 3
(COM0–4)
*1
(SEG0–13)
*2
(SEG0–17)
*3
(SEG0–21)
VDD
0.5
VDD
0.3




IOL1 = +0.5mA, VDD = 1.8 to 3.6V


0.5
IOL1 = +0.1mA, VDD = 1.25 to 3.6V


0.3
IOL2 = +5mA, VDD = 1.8 to 3.6V


0.5
VOH3
IOH3 = 0.05mA, VL1=1.2V
VL3
0.2


VOMH3
IOMH3 = +0.05mA, VL1=1.2V


VL2
+0.2
VOMH3S
IOMH3S = 0.05mA, VL1=1.2V
VL2
0.2


VOML3
IOML3 = +0.05mA, VL1=1.2V


VL1
+0.2
VOML3S
IOML3S = 0.05mA, VL1=1.2V
VL1
0.2


VOL3
IOL3 = +0.05mA, VL1=1.2V


0.2
IOOH
VOH = VDD (in high-impedance state)


1
IOH1 = 0.5mA, VDD = 1.8 to 3.6V
VOH1
IOH1 = -0.03mA, VDD = 1.25 to 3.6V
VOL1
VOL2
Output leakage
(P20–P22, P24)
(P30–P35)
(P40–P47)
(P50–P53)
*1 *2
(P60-P63)
*1
(P64-P67)
Input current 1
(RESET_N)
Input current 2
(TEST0)

VOL = VSS (in high-impedance state)
IIH1
VIH1 = VDD
0

1
IIL1
IIH2
IIL2
VIL1 = VSS
VIH2 = VDD
VIL2 = Vss
VIH3 = VDD ,VDD = 1.8 to 3.6V
(when pulled-down)
VIH3 = VDD ,VDD = 1.25 to 3.6V
(when pulled-down)
VIL3 = VSS , VDD = 1.8 to 3.6V
(when pulled-up)
VIL3 = VSS , VDD = 1.25 to 3.6V
(when pulled-up)
-600
2
-1
-300
300

-2
600

2
30
200
0.01
30
200
-200
-30
-2
-200
-30
-0.01
IIL3
2
A
3
A
4

IOOL
IIH3
Input current 3
(P00-P03)
(P30-P35)
(P40-P47)
(P50-P53)
1
V
IIH3Z
VIH3 = VDD (in high-impedance state)


1
IIL3Z
VIL3 = VSS (in high-impedance state)
1


1
* : pins for ML610401
2
* : pins for ML610402
3
* : pins for ML610403
22/31
FEDL610403-01
LAPIS Semiconductor
ML610401/ML610402/ML610403
DC CHARACTERISTICS (5/5))
(VDD = 1.25 to 3.6V, VSS = 0V, Ta = 20 to +70C, Ta = 40 to +85C for P version, unless otherwise specified)
Rating
Measuring
Parameter
Symbol
Condition
Unit
circuit
Min.
Typ.
Max.
Input voltage 1
(RESET_N)
(TEST0)
(P00–P03)
(P30–P35)
(P40–P47)
(P50–P53)
Input pin
capacitance
(P00–P03)
(P30–P35)
(P40–P47)
(P50–P53)
VIH1

0.7
VDD

VDD
VDD = 1.8 to 3.6V
0

VDD = 1.25 to 3.6V
0

0.3
VDD
0.2
VDD
f = 10kHz
Vrms = 50mV
Ta = 25C


VIL1
CIN
5
V
5
pF

23/31
FEDL610403-01
LAPIS Semiconductor
ML610401/ML610402/ML610403
MEASURING CIRCUITS
MEASURING CIRCUIT 1
CGL
32.768kHz
crystal
XT0
XT1
C2
CDL
C12
C1
VDD
VDDL
VL1 VL2 VL3
VSS
CV:
CL:
Ca,Cb,Cc:
C12:
32.768kHz crystal:
A
CV
CL
Ca
Cc
1F
0.47F
0.1F
0.47F
DT-26 (Load capacitance 6pF)
(made by KDS:DAISHINKU CORP.)
CGL, CDL:
6pF
MEASURING CIRCUIT 2
(*2)
VIL
Input pins
(*1)
Output pins
VIH
VDD VDDL
VL1
VL2
VL3
V
VSS
(*1) Input logic circuit to determine the specified measuring conditions.
(*2) Measured at the specified output pins.
24/31
FEDL610403-01
LAPIS Semiconductor
ML610401/ML610402/ML610403
MEASURING CIRCUIT 3
(*2)
VIL
Input pins
(*1)
Output pins
VIH
VDD VDDL
VL1
VL2
VL3
A
VSS
*1: Input logic circuit to determine the specified measuring conditions.
*2: Measured at the specified output pins.
MEASURING CIRCUIT 4
Input pins
Output pins
(*3)
A
VDD VDDL
VL1
VL2
VL3
VSS
*3: Measured at the specified output pins.
VIL
Input pins
(*1)
Output pins
VIH
VDD VDDL
VL1
VL2
VL3
Waveform monitoring
MEASURING CIRCUIT 5
VSS
*1: Input logic circuit to determine the specified measuring conditions.
25/31
FEDL610403-01
LAPIS Semiconductor
ML610401/ML610402/ML610403
AC CHARACTERISTICS (External Interrupt)
(VDD = 1.25 to 3.6V, VSS = 0V, Ta = 20 to +70C, Ta = 40 to +85C for P version, unless otherwise specified)
Rating
Parameter
Symbol
Condition
Unit
Min.
Typ.
Max.
External interrupt disable period
TNUL
Interrupt: Enabled (MIE = 1),
CPU: NOP operation
System clock: 32.768kHz

76.8
106.8
s
P00–P03
(Rising-edge interrupt)
tNUL
P00–P03
(Falling-edge interrupt)
tNUL
P00–P03
P50–P53
(Both-edge interrupt)
tNUL
AC CHARACTERISTICS (UART)
(VDD = 1.25 to 3.6V, VSS = 0V, Ta = 20 to +70C, Ta = 40 to +85C for P version, unless otherwise specified)
Rating
Parameter
Symbol
Condition
Unit
Min.
Typ.
Max.
Transmit baud rate

tTBRT

1
BRT*
1

s
1
BRT*
BRT*
1
BRT*
3%
+3%
*1: Baud rate period (including the error of the clock frequency selected) set with the serial port baud rate register
(UA0BRTL,H) and the serial port mode register 0 (UA0MOD0).
Receive baud rate

tRBRT
s
tTBRT
TXD0*
tRBRT
RXD0*
*: Indicates the secondary function of the port.
26/31
FEDL610403-01
LAPIS Semiconductor
ML610401/ML610402/ML610403
AC CHARACTERISTICS (RC Oscillation A/D Converter)
Condition for VDD=1.8 to 3.6V
(VDD=1.8 to 3.6V, VSS=0V, Ta=-20 to +70°C, Ta=-40 to +85°C for P version, unless otherwise specified)
Rating
Parameter
Symbol
Condition
Unit
Min.
Typ.
Max.
RS0,RS1,RT0,
1
Oscillation resistor
CS0, CT0, CS1740pF
k
RT0-1,RT1
fOSC1
457.3
525.2
575.1
kHz
Resistor for oscillation=1k
Oscillation frequency
fOSC2
53.48
58.18
62.43
kHz
Resistor for oscillation=10k
VDD = 3.0V
fOSC3
5.43
5.89
6.32
kHz
Resistor for oscillation=100k
Kf1
7.972
9.028
9.782
RT0,
RT0-1,
RT1=1k

RS to RT oscillation
*1
frequency ratio
Kf2
0.981
1
1.019
RT0, RT0-1, RT1=10k

VDD = 3.0V
Kf3
0.099
0.101
0.104
RT0, RT0-1, RT1=100k

*1: Kfx is the ratio of the oscillation frequency by the sensor resistor to the oscillation frequency by the reference resistor on the
same conditions.
,
fOSCX(RT0-1-CS0 oscillation)
fOSCX(RS0-CS0 oscillation)
IN0 CS0 RCT0
VIL
VDDL
fOSCX(RT1-CS1 oscillation)
fOSCX(RS1-CS1 oscillation)
RT0, RT0-1, RT1: 1k /10k
RS0, RS1: 10k
CS0, CT0, CS1: 560pF
CVR0, CVR1: 820pF
/100k
IN1 CS1 RS1 RT1
RCM
VDD
CV
RT1
RT0
RS0
RS0 RT0
Input pin
VIH
,
CVR1
RT0-1
CT0
CS0
CVR0
RS1
fOSCX(RT0-CS0 oscillation)
fOSCX(RS0-CS0 oscillation)
( x = 1, 2, 3 )
CS1
Kfx =
Frequency measurement (fOSCX)
VSS
CL
*1: Input logic circuit to determine the
specified measuring conditions.
27/31
FEDL610403-01
LAPIS Semiconductor
ML610401/ML610402/ML610403
Condition for VDD=1.25 to 3.6V
(VDD=1.25 to 3.6V, VSS=0V, Ta=-20 to +70°C, Ta=-40 to +85°C for P version, unless otherwise specified)
Rating
Parameter
Symbol
Condition
Unit
Min.
Typ.
Max.
RS0,RS1,RT0,
1
Oscillation resistor
CS0, CT0, CS1740pF
k
RT0-1,RT1
fOSC1
81.93
93.16
101.2
kHz
Resistor for oscillation=6k
Oscillation frequency
fOSC2
35.32
38.75
41.48
kHz
Resistor for oscillation=15k
VDD = 1.5V
fOSC3
5.22
5.65
6.03
kHz
Resistor for oscillation=105k
Kf1
2.139
2.381
2.632
RT0, RT0-1, RT1=1k

RS to RT oscillation
*1
frequency ratio
Kf2
0.973
1
1.028
RT0, RT0-1, RT1=10k

VDD = 1.5V
Kf3
0.142
0.147
0.152
RT0, RT0-1, RT1=100k

fOSC1
85.28
94.58
103.3
kHz
Resistor for oscillation=6k
Oscillation frequency
fOSC2
35.72
38.87
41.78
kHz
Resistor for oscillation=15k
VDD = 3.0V
fOSC3
5.189
5.622
6.012
kHz
Resistor for oscillation=105k
Kf1
2.227
2.432
2.626
RT0, RT0-1, RT1=1k

RS to RT oscillation
*1
frequency ratio
Kf2
0.982
1
1.018
RT0, RT0-1, RT1=10k

VDD = 3.0V
Kf3
0.141
0.145
0.149
RT0, RT0-1, RT1=100k

*1: Kfx is the ratio of the oscillation frequency by the sensor resistor to the oscillation frequency by the reference resistor on the
same conditions.
fOSCX(RT0-1-CS0 oscillation)
fOSCX(RS0-CS0 oscillation)
,
IN0 CS0 RCT0
VIH
,
fOSCX(RT1-CS1 oscillation)
fOSCX(RS1-CS1 oscillation)
RS0 RT0
RT1
RT0
RS0
RA0
RA1
CVR1
RT0-1 RA0-1
CT0
CS0
CVR0
RS1
fOSCX(RT0-CS0 oscillation)
fOSCX(RS0-CS0 oscillation)
( x = 1, 2, 3 )
CS1
Kfx =
RT0, RT0-1, RT1: 1k /10k
RA0, RA0-1, RA1: 5k
RS0, RS1: 15k
CS0, CT0, CS1: 560pF
CVR0, CVR1: 820pF
/100k
IN1 CS1 RS1 RT1
Frequency measurement (fOSCX)
Input pin
RCM
VIL
VDD
CV
VDDL
VSS
CL
*1: Input logic circuit to determine the
specified measuring conditions.
Note:
- Please have the shortest layout for the common node (wiring patterns which are connected to the external capacitors, resistors
and IN0/IN1 pin), including CVR0/CVR1. Especially, do not have long wire between IN0/IN1 and RS0/RS1. The coupling
capacitance on the wires may occur incorrect A/D conversion. Also, please do not have signals which may be a source of noise
around the node.
- When RT0/RT1 (Thermistor and etc.) requires long wiring due to the restricted placement, please have VSS(GND) trace next to
the signal.
- Please make wiring to components (capacitor, resisteor and etc.) necessory for objective measurement. Wiring to reserved
components may affect to the A/D conversion operation by noise the components itself may have.
28/31
FEDL610403-01
LAPIS Semiconductor
ML610401/ML610402/ML610403
Package Dimensions
(Unit: mm)
Notes for Mounting the Surface Mount Type Package
The surface mount type packages are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore,
before you perform reflow mounting, contact our responsible sales person for the product name, package name, pin number,
package code and desired mounting conditions (reflow method, temperature and times).
29/31
FEDL610403-01
LAPIS Semiconductor
ML610401/ML610402/ML610403
REVISION HISTORY
Document No.
Date
FEDL610403-01
Dec.6,2010
Page
Previous Current
Edition
Edition
–
–
Description
Formally edition 1
30/31
FEDL610403-01
LAPIS Semiconductor
ML610401/ML610402/ML610403
NOTICE
No copying or reproduction of this document, in part or in whole, is permitted without the consent of LAPIS Semiconductor
Co., Ltd.
The content specified herein is subject to change for improvement without notice.
The content specified herein is for the purpose of introducing LAPIS Semiconductor's products (hereinafter "Products"). If
you wish to use any such Product, please be sure to refer to the specifications, which can be obtained from LAPIS
Semiconductor upon request.
Examples of application circuits, circuit constants and any other information contained herein illustrate the standard usage
and operations of the Products. The peripheral conditions must be taken into account when designing circuits for mass
production.
Great care was taken in ensuring the accuracy of the information specified in this document. However, should you incur any
damage arising from any inaccuracy or misprint of such information, LAPIS Semiconductor shall bear no responsibility for
such damage.
The technical information specified herein is intended only to show the typical functions of and examples of application
circuits for the Products. LAPIS Semiconductor does not grant you, explicitly or implicitly, any license to use or exercise
intellectual property or other rights held by LAPIS Semiconductor and other parties. LAPIS Semiconductor shall bear no
responsibility whatsoever for any dispute arising from the use of such technical information.
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While LAPIS Semiconductor always makes efforts to enhance the quality and reliability of its Products, a Product may fail
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Copyright
2010 - 2011 LAPIS Semiconductor Co., Ltd.
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