Download datasheet for ML610Q346 by LAPIS Semiconductor

Download datasheet for ML610Q346 by LAPIS Semiconductor
FEDL610Q346DIGEST-01
Issue Date: January 7, 2010
ML610Q346/ML610346
8-bit Microcontroller with Voice Output Function
GENERAL DESCRIPTION
Equipped with an LAPIS Semiconductor original 8-bit CPU nX-U8/100, the ML610Q346/ML610346 is a
high-performance 8-bit CMOS microcontroller that integrates a wide variety of peripherals such as an op-amp,
12-bit A/D converter, timer, synchronous serial port, UART, and voice output function. The nX-U8/100 CPU is
capable of executing instructions efficiently on a one-instruction-per-clock-pulse basis through parallel
processing by the 3-stage pipelined architecture. The microcontroller is also equipped with a flash memory that
has achieved low voltage and low power consumption (at read) equivalent to mask ROMs, so it is best suited to
battery-driven applications such as cellular phones. In addition, it has an on-chip debugging function, which
allows software debugging/rewriting with the LSI mounted on the board.
FEATURES
 CPU
 8-bit RISC CPU (CPU name: nX-U8/100)
 Instruction repertoire: 16-bit length instructions
 Instruction set: Transfer, arithmetic operations, comparison, logical operations, multiply/divide operations,
bit manipulation, bit logical operations, jump, conditional jump, call return stack manipulation, and
arithmetic shift instructions.
 Built-in on-chip debugging function
 Minimum instruction execution time:
31.25 s (@ 32kHz system clock)
0.244 s (@ 4.096 MHz system clock)
 Internal memory
 ML610Q346
Has 128-Kbyte flash memory (64K  16-bit) built in. (including unusable 1KByte TEST area)
 ML610346
Has 128-Kbyte mask memory (64K  16-bit) built in. (including unusable 1KByte TEST area)
 Has 1-Kbyte RAM (1024  8-bit) built in.
 Interrupt controller
 Non-maskable interrupt: 2 sources (1 internal source and 1 external sources)
 Maskable interrupt: 18 sources (10 internal sources and 8 external sources)
 Time-base counter
 Low-speed side time-base counter  1ch
 High-speed side time-base counter  1ch
 Watchdog timer
 Generates a non-maskable interrupt upon the first overflow and a system reset occurs upon the second
 Free-running
 Selectable overflow period: 4 types (125 ms, 500 ms, 2 sec, 8 sec)
 Timer
 8-bit  2ch (16-bit configuration also enabled)
1/19
FEDL610Q346DIGEST-01
ML610Q346/346
 Voice output function
 Voice synthesis method: HQ-ADPCM / 4-bit ADPCM2 / 8-bit non-linear PCM / 8-bit PCM / 16-bit PCM
 Sampling frequency: 6.4/8/10.7/12.8/16/21.3/25.6/32 kHz
 Speaker amplifier output power
 1W(at 5V)
 Synchronous serial port
 Master/slave selectable
 LSB/MSB-first selectable
 8-bit/16-bit length selectable
 UART
 Half-Duplex Communication
 TXD/RXD  1 channel
 Bit length, with/without parity, odd/even parity, 1 or 2 stop bits
 Positive/negative logic selectable
 Built-in baud-rate generator
 Successive-approximation type A/D converter
 12-bit A/D converter
 Input: 3ch
 Conversion time: 26.86 s per channel at 4.096 MHz
 Op-amp
 3ch
 Composition is possible as reversal amplifier, reversed amplifier, and a comparator.
 General-purpose port
 Input-only port  8ch
 Output-only port  4ch (those as secondary functions are also included)
 Input-output port  16ch (those as secondary functions are also included)
 Reset
 Resetting by the RESET_N pin
 Resetting upon power-on detection
 Resetting upon WDT overflow detection
 Clock
 Low-speed side clock
Built-in RC oscillator (32 kHz)
 High-speed side clock
Crystal/ceramic oscillation (4.096 MHz), external clock
 Power management
 HALT mode: Halts the execution of instructions issued by the CPU (the peripheral circuits continue
operating)
 STOP mode: Stops low-speed and high-speed oscillation (the CPU and the peripheral circuits stop
operating)
 Clock gear: Allows changing the frequency of the high-speed system clock by software (oscillator clock
divided by 1, 2, 4, or 8)
 Block Control Function: Power down (reset registers and stop clock supply) the circuits of unused
peripherals.
2/19
FEDL610Q346DIGEST-01
ML610Q346/346
 Shipment
 64-pin TQFP
 High-speed side clock Crystal/ceramic oscillation (4.096 MHz)
Flash Memory ML610Q346-xxxTB (blank product: ML610Q346-NNNTB)
Mask Memory ML610346-xxxTB
 High-speed side clock external clock
Flash Memory ML610Q346J-xxxTB (blank product: ML610Q346J-NNNTB)
Mask Memory ML610346J-xxxTB
xxx: ROM code number
 Guaranteed operating range
 Operating temperature: 40C to +85C
 Operating voltage: VDD = 2.2 to 5.5 V, SPVDD = 2.3 to 5.5 V, AVDD = 2.2 to 5.5 V
(Be sure to apply the same voltage to VDD and SPVDD power supplies.)
3/19
FEDL610Q346DIGEST-01
ML610Q346/346
BLOCK DIAGRAM
Figure 1 is a block diagram of the ML610Q346.
Symbols with an asterisk “*” indicate that each of them is the secondary or tertiary function of the corresponding
port.
CPU (nX-U8/100)
EPSW1 3
GREG
0 15
PSW
Timing
Controller
ALU
VDD
VSS
RESET_N
TEST
OSC0
OSC1
LSCLK*
OUTCLK*
RESET &
TEST
RC32K
AIN0 to AIN2
EA
PC
Instruction
Register
Program
Memory
Flash
128Kbyte
BUS
Controller
INT
1
RAM
1024byte
INT
1
Interrupt
Controller
INT
9
TBC
POWER
INT
2
INT
1
VOICECNT
VPP
SSIO
SCK0*1
SIN0*1
SOUT0*1
UART
RXD0*1
TXD0*1
8bit Timer
2
NMI
P00 to P07
GPIO
P20 to P23
P30 to P37
P40 to P47
INT
WDT
AVDD
AVSS
VREF
DSR/CSR
OSC
SPVDD
SPVSS
SG
SPP
SPM
AOUT
SPIN
LR
Data-bus
INT
4
VDDL
ECSR1 3
SP
Instruction
Decoder
On-Chip
ICE
ELR1 3
INT
1
12bit-ADC
MOP0_l1
MOP0_l2
MOP0_O
OP-AMP0
MOP1_l1
MOP1_l2
MOP1_O
OP-AMP1
MOP2_l1
MOP2_l2
MOP2_O
OP-AMP2
Figure 1
Block Diagram of ML610Q346
4/19
FEDL610Q346DIGEST-01
ML610Q346/346
Figure 2 is a block diagram of the ML610346.
Symbols with an asterisk “*” indicate that each of them is the secondary or tertiary function of the corresponding
port.
CPU (nX-U8/100)
EPSW1 3
GREG
0 15
PSW
Timing
Controller
On-Chip
ICE
TEST
OSC0
OSC1
LSCLK*
OUTCLK*
Instruction
Decoder
RESET &
TEST
VREF
PC
Instruction
Register
Program
Memory
Mask
128Kbyte
BUS
Controller
INT
1
RAM
1024byte
INT
1
Interrupt
Controller
INT
9
SSIO
SCK0*1
SIN0*1
SOUT0*1
UART
RXD0*1
TXD0*1
OSC
RC32K
TBC
POWER
INT
2
INT
1
VOICECNT
8bit Timer
2
NMI
P00 to P07
GPIO
P20 to P23
P30 to P37
P40 to P47
INT
WDT
AVDD
AVSS
AIN0 to AIN2
EA
Data-bus
SPVDD
SPVSS
SG
SPP
SPM
AOUT
SPIN
DSR/CSR
SP
INT
4
V
VDDL
DDL
ECSR1 3
LR
ALU
VDD
VSS
RESET_N
ELR1 3
INT
1
12bit-ADC
MOP0_l1
MOP0_l2
MOP0_O
OP-AMP0
MOP1_l1
MOP1_l2
MOP1_O
OP-AMP1
MOP2_l1
MOP2_l2
MOP2_O
OP-AMP2
Figure 2
Block Diagram of ML610346
5/19
FEDL610Q346DIGEST-01
ML610Q346/346
PIN CONFIGURATION
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
NMI
AVDD
VREF
AVSS
AIN0
AIN1
AIN2
MOP2_O
MOP2_I2
MOP2_I1
MOP1_O
MOP1_I2
MOP1_I1
MOP0_O
MOP0_I2
MOP0_I1
VPP
P43
P42
P41
P40
P07
P06
P05
P04
VSS
P03
P02
P01
P00
RESET_N
TEST
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
(NC)
(NC)
SPM
SPP
VDD
OSC0
OSC1
VDDL
P33
P32
P31
P30
P47
P46
P45
P44
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
SPVSS
SPVDD
P34
P35
P36
P37
SPIN
AOUT
SG
VSS
(NC)
(NC)
P20
P21
P22
P23
ML610Q346 TQFP package product
NC:
Figure 3
No Connection
Pin Configuration of ML610Q346 Package Product
6/19
FEDL610Q346DIGEST-01
ML610Q346/346
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
NMI
AVDD
VREF
AVSS
AIN0
AIN1
AIN2
MOP2_O
MOP2_I2
MOP2_I1
MOP1_O
MOP1_I2
MOP1_I1
MOP0_O
MOP0_I2
MOP0_I1
(NC)
P43
P42
P41
P40
P07
P06
P05
P04
VSS
P03
P02
P01
P00
RESET_N
TEST
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
(NC)
(NC)
SPM
SPP
VDD
OSC0
OSC1
VDDL
P33
P32
P31
P30
P47
P46
P45
P44
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
SPVSS
SPVDD
P34
P35
P36
P37
SPIN
AOUT
SG
VSS
(NC)
(NC)
P20
P21
P22
P23
ML610346 TQFP package product
NC:
Figure 4
No Connection
Pin Configuration of ML610346 Package Product
7/19
FEDL610Q346DIGEST-01
ML610Q346/346
LIST OF PINS
Primary function
PAD
No
Pin name
I/O
10,39
Vss

53
VDD

56
VDDL

48
SPVSS

47
SPVDD

29
AVSS

31
AVDD

1
VPP(*)

16
TEST
I/O
15
RESET_N
I
54
OSC0
I
55
OSC1
O
41
AOUT
O
42
SPIN
I
40
SG
O
52
SPP
O
51
SPM
O
30
VREF

28
AIN0
I
27
AIN1
I
26
AIN2
I
Description
Negative power
supply pin
Positive power supply
pin
Power supply for
internal logic
(internally generated)
Negative power
supply pin for built-in
speaker amplifier
Positive power supply
pin for built-in speaker
amplifier
Negative power
supply pin for
successive-approxima
tion type
ADC/OP-amp
Positive power supply
pin for
successive-approxima
tion type
ADC/OP-amp
Power supply pin for
flash memory
Input/output pin for
testing
Reset input pin
Connection pin for
high-speed clock
oscillation
Connection pin for
high-speed clock
oscillation
LINE output
Analog input to the
built-in speaker
amplifier
Reference power
supply pin of the
built-in speaker
amplifier
Positive output pin of
the built-in speaker
amplifier
Negative output pin of
the built-in speaker
amplifier
Reference power
supply pin for
successive-approxima
tion type ADC
Successive-approxim
ation type ADC input
Successive-approxim
ation type ADC input
Successive-approxim
ation type ADC input
Secondary function
Tertiary function
Pin name
I/O
Description
Pin name
I/O
Description


































































P11
I
Input port

























































8/19
FEDL610Q346DIGEST-01
ML610Q346/346
Primary function
PAD
No
Pin name
I/O
32
NMI
I
14
P00/EXI0
I
13
P01/EXI1
I
12
P02/EXI2/
RXD0
I
11
P03/EXI3
I
9
P04/EXI4/
T0P0CK
I
8
P05/EXI5/
T1P1CK
I
7
P06/EXI6
I
6
P07/EXI7
I
36
P20/LED0
O
35
P21/LED1
O
34
P22/LED2
O
33
P23/LED3
O
60
59
58
57
46
45
P30
P31
P32
P33
P34
P35
I/O
I/O
I/O
I/O
I/O
I/O
Description
Input port,
non-maskable
interrupt
Input port / External
interrupt
Input port / External
interrupt
Input port / External
interrupt / UART0 data
input
Input port / External
interrupt
Input port / External
interrupt / Timer 0
external clock input
Input port / External
interrupt / Timer 1
external clock input
Input port / External
interrupt
Input port / External
interrupt
Output port / LED
drive
Output port / LED
drive
Output port / LED
drive
Output port / LED
drive
Input/output port
Input/output port
Input/output port
Input/output port
Input/output port
Input/output port
44
P36
I/O
43
P37
5
Secondary function
Tertiary function
Pin name
I/O
Description
Pin name
I/O
Description




























































Low-speed
clock output
high-speed
clock output
LSCLK
O
OUTCLK
O










































Input/output port
LSCLK
O



I/O
Input/output port
OUTCLK
O



P40
I/O
Input/output port



SIN0
I
4
P41
I/O
Input/output port



SCK0
I/O
3
P42
I/O
Input/output port
RXD0
I
SOUT0
O
2
P43
I/O
Input/output port
TXD0
O


I/O
Input/output port,
Timer 0 external clock
input


SIN0
I



SCK0
I/O






Low-speed
clock output
high-speed
clock output
UART0 data
input
UART0 data
output
64
P44/T0P0
CK
63
P45/T1P1
CK
I/O
Input/output port,
Timer 1 external clock
input
62
P46
I/O
Input/output port



SOUT0
O
61
P47
I/O
Input/output port






SSIO0 data
input
SSIO0
synchronous
clock
input/output
SSIO0 data
output

SSIO0 data
input
SSIO0
synchronous
clock
input/output
SSIO0 data
output

9/19
FEDL610Q346DIGEST-01
ML610Q346/346
Primary function
PAD
No
Pin name
17
MOP0_I1
18
MOP0_I2
19
MOP0_O
20
MOP1_I1
21
MOP1_I2
22
MOP1_O
23
MOP2_I1
24
MOP2_I2
25
MOP2_O
I/O
I
I
O
I
I
O
I
I
O
Description
Op-amp0 positive
analog input
Op-amp0 negative
analog input
Op-amp0 analog
output
Op-amp1 positive
analog input
Op-amp1 negative
analog input
Op-amp1 analog
output
Op-amp2 positive
analog input
Op-amp2 negative
analog input
Op-amp2 analog
output
Secondary function
Tertiary function
Pin name
I/O
Description
Pin name
I/O
Description






















































*: Applies to the ML610Q346.
10/19
FEDL610Q346DIGEST-01
ML610Q346/346
PIN DESCRIPTION
Pin name
I/O
Description
Primary/
Secondary/
Tertiary
Logic
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Positive
—
Negative
—
—
—
—
Secondary
—
Secondary
—
Primary
Positive
Primary
Positive
Primary
Positive
Power supply
VSS
VDD
VDDL
SPVSS
SPVDD
AVSS
AVDD
VPP(*)
— Negative power supply pin
— Positive power supply pin
— Positive power supply pin for internal logic (internally generated)
Capacitors CL(see measuring circuit 1) are connected between
this pin and VSS.
— Negative power supply pin for built-in speaker amplifier
— Positive power supply pin for built-in speaker amplifier
— Negative power supply pin for successive-approximation type
ADC/OP-amp
— Positive power supply pin for successive-approximation type
ADC/Op-amp
— Power supply pin for flash memory
Test
TEST
System
RESET_N
I/O Input/output pin for testing. Has a pull-down resistor built in.
Reset input pin. When this pin is set to a “L” level, the device is
placed in system reset mode and the internal circuit is initialized.
If after that this pin is set to a “H” level, program execution
starts. This pin has a pull-up resistor built in.
OSC0
I Pins for connecting a crystal unit for high speed clock.
OSC1
O Connect a 4.096 MHz crystal unit (see Measuring Circuit 1) to
these pins. Also, connect capacitors (CDH and CGH) between
these pins and VSS as required.
LSCLK
O Low-speed clock output. This function is allocated to the
secondary function of the P20 and P36 pins.
OUTCLK
O High-speed clock output. This function is allocated to the
secondary function of the P21 and P37 pins.
General-purpose Input port
P00–P07
I General-purpose input ports.
I
General-purpose Output port
P20–P23
O General-purpose output ports.
Provided with a secondary function. Cannot be used as ports if
their secondary function is used.
General-purpose Input/output port
P30–P37
I/O General-purpose input/output ports.
P40–P47
I/O Provided with a secondary function. Cannot be used as ports if
their secondary function is used.
*Applies to the ML610Q346.
11/19
FEDL610Q346DIGEST-01
ML610Q346/346
Pin name
UART
TXD0
I/O
Primary/
Secondary/
Tertiary
Logic
Secondary
Positive
Secondary
Positive
Tertiary
Positive
Tertiary
—
Tertiary
Positive
External non-maskable interrupt input pin. The interrupt occurs
on both the rising and falling edges.
External maskable interrupt input pins. It is possible, for each
bit, to specify whether the interrupt is enabled and select the
interrupt edge by software. Allocated to the primary function of
the P00–P07 pins.
Primary
Positive/
Negative
Primary
Positive/
Negative
External clock input pin for timer 0. Allocated to the primary
function of the P04 and P44 pins.
External clock input pin for timer 1. Allocated to the primary
function of the P05 and P45 pins.
Primary
NMOS open drain pins to allow direct driving of LED. Allocated
to the secondary function of the P20–P22 pins.
Primary
Description
UART0 data output pin. Allocated to the secondary function of
the P43 pin.
RXD0
I UART0 data input pin. Allocated to the primary function of the
P02 pin and the secondary function of the P42 pin.
Synchronous serial (SSIO)
SIN0
SCK0
SOUT0
O
I
Synchronous serial data input pin. Allocated to the tertiary
function of the P40 pin and P44 pins.
I/O Synchronous serial clock input/output pin. Allocated to the
tertiary function of the P41 and P45 pins.
O Synchronous serial data output pin. Allocated to the tertiary
function of the P42 and P46 pins.
External interrupt
NMI
I
EXI0–7
I
Timer
T0P0CK
I
T1P1CK
I
LED drive
LED0–3
O
Voice output function
AOUT
O LINE output pin. When you use built-in speaker amplifier,
connect with the SPIN pin.
SPIN
I Analog input pin of the internal speaker amplifier.
SG
O Reference voltage output pin of the internal speaker amplifier.
SPP
O Positive output pin of the internal speaker amplifier.
SPM
O Negative output pin of the internal speaker amplifier.
Successive-approximation type A/D converter
VREF
— Reference power supply pin for the successive-approximation
type A/D converter.
AIN0–AIN2
I Analog inputs to Ch0 to Ch2 of the successive-approximation
type A/D converter.
Op-amp
I Positive analog input pins of the op-amp0.
MOP0_I1
I Negative analog input pins of the op-amp0.
MOP0_I2
O
Analog output pins of the op-amp0.
MOP0_O
I Positive analog input pins of the op-amp1.
MOP1_I1
I Negative analog input pins of the op-amp1.
MOP1_I2
O Analog output pins of the op-amp1.
MOP1_O
I Positive analog input pins of the op-amp2.
MOP2_I1
I Negative analog input pins of the op-amp2.
MOP2_I2
O Analog output pins of the op-amp2.
MOP2_O
Primary
—
—
Positive/
Negative
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
12/19
FEDL610Q346DIGEST-01
ML610Q346/346
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings
(VSS = AVSS = SPVSS = 0V)
Parameter
Power supply voltage 1
Symbol
Condition
Rating
Unit
VDD
Ta = 25C
0.3 to +7.0
V
Power supply voltage 2
AVDD
Ta = 25C
0.3 to +7.0
V
Power supply voltage 3
SPVDD
Ta = 25C
0.3 to +7.0
V
Power supply voltage 4
VDDL
Ta = 25C
0.3 to +3.6
V
Power supply voltage 5
VPP
Ta = 25C
0.3 to +9.5
V
VIN
Ta = 25C
0.3 to VDD+0.3
V
Output voltage
VOUT
Ta = 25C
0.3 to VDD+0.3
V
Output current 1
IOUT1
P03, P04, Ta = 25C
12 to +11
mA
Output current 2
Input voltage
IOUT2
P02, Ta = 25C
12 to +20
mA
Power dissipation
PD
Ta = 25C
861
mW
Storage temperature
TSTG
55 to +150
C
Recommended Operating Conditions
(VSS = AVSS = SPVSS = 0V)
Parameter
Operating temperature
Operating voltage
Operating frequency (CPU)
High-speed crystal/ceramic
oscillation frequency
High-speed crystal oscillation
external capacitor
Capacitor externally connected
to VDDL pin
Capacitor externally connected
to SG pin
Symbol
Condition
Range
Unit
TOP
40 to +85
C
VDD
2.2 to 5.5
SPVDD
2.3 to 5.5
V
AVDD
fOP
2.2 to 5.5
27k to 4.2M
Hz
fXTH
4.0M, 4.096M
Hz
CDH
CGH
15 to 32
15 to 32
pF
CL
1030%
F
CSG
0.130%
F
13/19
FEDL610Q346DIGEST-01
ML610Q346/346
Flash Memory Operating Conditions
Parameter
Operating temperature
Operating voltage
Maximum rewrite count
Data retention period
Symbol
TOP
VDD
VDDL
VPP
CEP
YDR
(VSS = AVSS = SPVSS = 0V)
Range
Unit
0 to +40
C
2.7 to 3.6
V
2.5 to 2.75
7.7 to 8.3
80
times
10
years
Condition
At write/erase
At write/erase (*1)
At write/erase (*1)
At write/erase (*1)
*1: When writing data to, or erasing data from, flash ROM, it is necessary to apply a voltage within the range
specified above to the VDDL pin.
DC Characteristics (1 of 5)
Parameter
High-speed oscillation start
time
Low-speed RC oscillator
frequency
Reset pulse width
Reset noise rejection pulse
width
Time from power-on reset to
power-up
Symbol
(VDD = SPVDD = AVDD = 2.2 to 5.5V, VSS = AVSS = SPVSS = 0V,
Ta = 40 to +85C, unless otherwise specified)
Measuring
Condition
Min.
Typ.
Max.
Unit
circuit
TXTH
fLCR
27.2k
PRST
100
2
20
ms
32k
36.8k
Hz
1
PNRST
0.4
TPOR
10
s
ms
14/19
FEDL610Q346DIGEST-01
ML610Q346/346
DC Characteristics (2 of 5)
Parameter
LINE amplifier output
load resistance
LINE amplifier output
voltage range
(VDD = SPVDD = 2.3 to 5.5V, AVDD = 2.2 to 5.5V, VSS = AVSS = SPVSS = 0V,
Ta = 40 to +85C, unless otherwise specified)
Measuring
Symbol
Condition
Min.
Typ.
Max.
Unit
circuit
RLA
At 1/2VDD output
10


k
VAD
At output load
DVDD1/6

DVDD5/6
V
SG output voltage
VSG
0.95 
DVDD/2
DVDD/2
1.05 
DVDD/2
V
SG output resistance
SPM, SPP output load
resistance
RSG
57
96
135
k
RLSP
8
PSPO1
Speaker amplifier output
power
PSPO2
Output offset voltage
between SPM and SPP
with no signal present
VOF
SPVDD = 3.3V,
f = 1kHz,
RSPO = 8,
THD  10%
At SPIN Input
SPVDD = 5.0V,
f = 1kHz,
RSPO = 8,
THD  10%
At SPIN Input
SPVDD=3.0V,
SPIN – SPM gain
= +6dB
With a load of 8

—
0.5
—
W
—
1
—
W
50
—
+50
mV
1
Electrical Characteristics of Op-Amp
(VDD = SPVDD = AVDD = 2.2 to 5.5V, VSS = SPVSS = AVSS = 0V,
Ta = 40 to +85C, unless otherwise specified)
Parameter
Supply current
Input voltage range
High-level output
voltage
Low-level output
voltage
Input offset
Output current
Symbol
Condition
IDDOP
VDD = 3.0V, one op-amp used
VDD = 5.0V, one op-amp used
VIP
VOH
If = 150A
VOL
If = 150A
VSS
0.1
AVDD
0.1
VSS
10
VIO
IOUT
Min.
When configured as a non-inverting op-amp
(Gain = 1)
VDD = 3.0V, Vout = 0.5 to 1.8V
Typ.
Max.
Unit
50
60
80
90
AVDD
1.2
A
A
AVDD
V
V
VSS
0.1
+10
mV
1
mA
V
15/19
FEDL610Q346DIGEST-01
ML610Q346/346
DC Characteristics (3 of 5) ML610Q346
(VDD = SPVDD = AVDD = 2.2 to 5.5V, VSS = AVSS = SPVSS = 0V,
Ta = 40 to +85C, unless otherwise specified)
Meas
Parameter
Symbol
Condition
Min. Typ. Max. Unit uring
circuit
CPU: In STOP state.
Ta  +40C
0.5
2.0
Supply current 1
IDD1
Low-speed/high-speed
Ta  +85C
0.5
8
oscillation: stopped
CPU: In HALT state
Ta  +40C
1.5
3.0
*3
A
(LTBC: Operating )
Supply current 2
IDD2
High-speed
Ta  +85C
1.5
10
oscillation:Stopped
1
CPU: Running at 32 kHz*
Supply current 3
IDD3
10
35
High-speed oscillation: Stopped
VDD = AVDD =
1.7
4
CPU: Running at
SPVDD = 3.0V
Supply current 4
4.096MHz Crystal/ceramic
IDD4
1
2
VDD = AVDD =
oscillating mode*
2.2
4
SPVDD = 5.0V
CPU: Running at
VDD = AVDD =
3
12
4.096MHz Crystal/ceramic
SPVDD = 3.0V
2
Supply current 5
oscillating mode*
mA
IDD5
VDD = AVDD =
During voice playback (no
8
12
output load)
SPVDD = 5.0V
VDD = AVDD =
CPU: Running at
1.9
5.5
4.096MHz Crystal/ceramic SPVDD = 3.0V
Supply current 6
IDD6
2
oscillating mode*
VDD = AVDD =
3.2
5.5
ADC: Operating
SPVDD = 5.0V
*1: Case when the CPU operating rate is 100% (with no HALT state)
2
* : Use 4.096MHz Crystal Oscillator CHC49SFWB (Kyocera).
3
* : Significant bits of BLKCON0~BLKCON4 registers are all “1”.
16/19
FEDL610Q346DIGEST-01
ML610Q346/346
DC Characteristics (3 of 5) ML610346
(VDD = SPVDD = AVDD = 2.2 to 5.5V, VSS = AVSS = SPVSS = 0V,
Ta = 40 to +85C, unless otherwise specified)
Meas
Parameter
Symbol
Condition
Min. Typ. Max. Unit uring
circuit
CPU: In STOP state.
Ta  +40C
0.5
2.0
Supply current 1
IDD1
Low-speed/high-speed
Ta  +85C
0.5
8
oscillation: stopped
CPU: In HALT state
Ta  +40C
1.2
3.0
*3
A
(LTBC: Operating )
Supply current 2
IDD2
High-speed
Ta  +85C
1.2
10
oscillation:Stopped
1
CPU: Running at 32 kHz*
Supply current 3
IDD3
5
35
High-speed oscillation: Stopped
VDD = AVDD =
1
4
CPU: Running at
SPVDD = 3.0V
4.096MHz Crystal/ceramic
Supply current 4
IDD4
1
2
VDD = AVDD =
oscillating mode*
2
4
SPVDD = 5.0V
CPU: Running at
VDD = AVDD =
2.8
12
4.096MHz Crystal/ceramic
SPVDD = 3.0V
2
Supply current 5
oscillating mode*
mA
IDD5
VDD = AVDD =
During voice playback (no
8
12
output load)
SPVDD = 5.0V
VDD = AVDD =
CPU: Running at
1.1
5.5
4.096MHz Crystal/ceramic SPVDD = 3.0V
Supply current 6
IDD6
2
oscillating mode*
VDD = AVDD =
2.3
5.5
ADC: Operating
SPVDD = 5.0V
*1: Case when the CPU operating rate is 100% (with no HALT state)
2
* : Use 4.096MHz Crystal Oscillator CHC49SFWB (Kyocera).
3
* : Significant bits of BLKCON0~BLKCON4 registers are all “1”.
17/19
FEDL610Q346DIGEST-01
ML610Q346/346
PACKAGE DIMENSIONS
(Unit: mm)
18/19
FEDL610Q346DIGEST-01
ML610Q346/346
NOTICE
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Copyright
2008 - 2011 LAPIS Semiconductor Co., Ltd.
19/19
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