Download datasheet for ML9059E by LAPIS Semiconductor

Download datasheet for ML9059E by LAPIS Semiconductor

LAPIS Semiconductor

ML9059E

132-Channel LCD Driver with Built-in RAM for LCD Dot Matrix Displays

FEDL9059E-01

Issue Date: April. 13, 2007

GENERAL DESCRIPTION

The ML9059E is an LSI for dot matrix graphic LCD devices carrying out bit map display. This LSI can drive a dot matrix graphic LCD display panel under the control of an 8-bit microcomputer (hereinafter described MPU).

Since all the functions necessary for driving a bit map type LCD device are incorporated in a single chip, using the

ML9059E makes it possible to realize a bit map type dot matrix graphic LCD display system with only a few chips.

Since the bit map method in which one bit of display RAM data turns ON or OFF one dot in the display panel, it is possible to carry out displays with a high degree of freedom such as Chinese character displays, etc. With one chip, it is possible to construct a graphic display system with a maximum of 49

 132 dots. The display can be expanded further using two chips. However, the ML9059E is not used in a multiple chip configuration when a line reversal drive is set.

The ML9059E is made using a CMOS process. Because it has a built-in RAM, low power consumption is one of its features, and is therefore suitable for displays in battery-operated portable equipment.

The ML9059E has 49 common signal outputs and 132 segment signal outputs and one chip can drive a display of up to 49

 132 dots.

FEATURES

 Direct display of the RAM data using the bit map method

Display RAM data “1” ... Dot is displayed

Display RAM data “0” ... Dot is not displayed (during forward display)

 Display RAM capacity

 132 = 8580 bits

 LCD Drive circuits

49 common outputs, 132 segment outputs

 MPU interface: Can select an 8-bit parallel or serial interface

 Built-in voltage multiplier circuit for the LCD drive power supply

 Built-in LCD drive voltage adjustment circuit

 Built-in LCD drive bias generator circuit

 Can select frame reversal drive or line reversal drive by command

 Built-in oscillator circuit (Internal RC oscillator/external clock input)

 A variety of commands

Read/write of display data, display ON/OFF, forward/reverse display, all dots ON/all dots OFF, set page address, set display start address, etc.

 Power supply voltage

Logic power supply: V

DD

-V

SS

= 3.7 V to 5.5 V

Voltage multiplier reference voltage: V

IN

-V

SS

= 3.7 V to 5.5 V

(2- to 4-time multiplier available)

LCD Drive voltage: V

BI

-V

SS

= 6.0 to 18 V

 Package: Gold bump chip (Bump hardness: Low, DV)

: Gold bump chip (Bump hardness: High, CV)

 This device is not resistant to radiation and light.

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BLOCK DIAGRAM

VS1–

VS2–

VC3+

VC4+

VC5+

VC6+

V

OUT

V

IN

VR

VRS

IRS

V

DD

V1

V2

V3

V4

V5

V

SS

SEGMENT

Drivers

COMMON

Drivers

Common Output state selection circuit

Display data latch circuit

Display data RAM

65

 132

Column address circuit

FRS

FR

CL

DOF

M/S

CLS

TEST1

Bus holder

Command decoder

MPU lnterface

Status

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ABSOLUTE MAXIMUM RATINGS

Parameter

Power supply voltage

Bias voltage

Voltage multiplier output voltage

Symbol

V

DD

V

BI

V

OUT

Condition

Tj = 25°C

Tj = 25°C

Tj = 25°C

Voltage multiplier reference voltage

V

IN

2-time multiplication

3-time multiplication

4-time multiplication

Input voltage V

I

Tj = 25°C

Storage temperature range T

STG

Chip

Tj: Chip surface temperature

RECOMMENDED OPERATING CONDITIONS

Rated value

–0.3 to +6.5

–0.3 to +20

–0.3 to +20

V

SS

= 0 V

Unit Applicable pins

V

V

V

DD

V1 to V5

V V

OUT

–0.3 to +5.5

–0.3 to +5.5

–0.3 to +5.0

V V

IN

–0.3 to V

DD

+0.3 V All

–55 to +125 °C —

Parameter

Power supply voltage

Bias voltage

Voltage multiplier reference voltage

Symbol Rated value Unit

V

DD

— 3.7

V

BI

V

IN

Condition

2-time multiplication

3-time multiplication

4-time multiplication

6 to 18

3.7 to 5.5

3.7 to 5.5

3.7 to 4.5

V

Applicable pins

V1 to V5

V V

V

SS

= 0 V

IN

Voltage multiplier output voltage

V

OUT

External input 6.0 to 18 V V

OUT

Operating temperature range T

JOP

— –40 to +85 °C —

Note 1: The electrical characteristics are influenced by COG trace resistance. This LSI always has to be evaluated before using.

V

CC

V

IN

V

DD

V

OUT

V1 to V5

GND

System (MPU)

V

SS

ML9059E

Note 2: The voltages V

DD

, V1 to V5, and V

OUT

are values taking V

SS

= 0 V as the reference.

Note 3: The highest bias potential is V1 and the lowest is V

SS

.

Note 4: Always maintain the relationship V1

 V2  V3  V4  V5  V

SS

among these voltages.

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Note 5: When using an external power supply, follow the procedure for power application.

When applying external power to the V

OUT

pin only, apply V

OUT

after V

DD.

When applying external power to the V1 pin only, apply V1 after V

DD

.

When applying external power to the V1 pin to V5 pin, apply V1 to V5 after V

DD

.

Note that the above (Note 4) must be satisfied including transient state at power application.

Note 6: When using an external power supply, follow the procedure for power removal described

below.

When external power is in use for the V

OUT

pin only, remove V

OUT

after V

DD

.

When external power is in use for the V1 pin only, remove V1 after V

DD

.

When external power is in use for the V1 pin to V5 pin, remove V1 to V5 after V

DD

.

Note that the above (Note 4) must be satisfied including transient state at power removal.

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ELECTRICAL CHARACTERISTICS

DC Characteristics

“L” Input voltage

Hysteresis width

“H” output voltage

“L” output voltage

[V

SS

= 0 V, V

DD

= 3.7 to 5.5 V, Tj =–40 to +85°C]

Applicable

Parameter Symbol Condition Min Typ Max Unit pins

“H” Input voltage

“L” Input voltage

“H” Input voltage

V

IH

 V

DD

— V

DD

V

IL

0

V *1

0.2

V

IH

 V

DD

— V

DD

V

IL

0

V V

DD

= 5.0 V

V

V

OH

OL

I

OH

I

OL

= –0.5 mA

= 0.5 mA

0.85

0.8

 V

DD

1.0

1.55

— —

0.2

 V

DD

V *2

V *3

“H” Input current

“L” Input current

I

IH

I

IL

Input capacitance

V1 output voltage temperature gradient

Reference voltage

V1 output voltage

Voltage multiplier output voltage

V

OUT

- V1 voltage

LCD driver ON resistance

C

I

V1TC

V

REG

V1

V

OUT

Vot1

R

ON

V

I

= V

DD

–1.0

V

I

= 0 V –3.0 — +3.0

Tj=25°C

F=10kHz

Tj = 25°C

V1 = 12 V

Tj = 25°C

*6

–0.03 –0.05

2.925

10.58

3.00

10.85

–0.08 %/°C

3.075

11.12

V

V

V1

V

RS

V1

3-time multiplication *7

4-time multiplication *8

*9

13.0 — — V V

15.9 — — V V

0.6 — — V

OUT

OUT

I

O

=

50 µA

— — 10 k

V

OUT,

V1

SEG1 to 131,

COMS0,

COMS1,

COM0 to 47

Internal

Oscillator oscillation frequency External input f

OSC

Tj = 25°C f

EXT

14

*1: DB0 to DB5, DB7 (SI), FR, DOF Pins

*2: A0, CS1, CS2, CLS, M/S, C86, P/S, IRS,RD (E), WR (R/W), RES, CL, DB6 (SCL) Pins

*3: DB0 to DB7, FR, FRS, DOF, CL Pins

*5: Applicable to the pins DB0 to DB5, DB6 (SCL), DB7 (SI), CL, FR, DOF in the high impedance state.

*6: Tj = 25°C,

*7: V

IN

 = 31, (1+Rb/Ra) = 4, V

OUT

= 13.5 V (External input), LCD drive output = no-load

= 4.8 V, voltage multiplier capacitor C1 = 2.6 to 4.0

F, voltage multiplier output load current

I = 500

A. Only a voltage multiplier circuit operates, not activating the voltage adjustment circuit and V/F circuit, by command “2C”.

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*8: V

IN

= 4.5 V, voltage multiplier capacitor C1 = 2.6 to 4.0

F, voltage multiplier output load current

I = 500

A. Only a voltage multiplier circuit operates, not activating the voltage adjustment circuit and V/F circuit, by command “2C”.

*9: V1 load current I = 400

A. 8 V is externally input to V

OUT.

The voltage adjustment circuit and V/F circuit operate by command “2B”. LCD output = no load

*10: See Table 1 for the relationship between the oscillator frequency and the frame frequency.

Table 1. Relationship among the oscillator frequency (f

OSC

), external input frequency

(f

EXT

) display clock frequency (f

LCDCK

), and LCD frame frequency (f

FR

)

Display clock frequency

Parameter

When the internal oscillator is used

(f

LCDCK

)

LCD frame frequency

(f

FR

) f

OSC

/8 f

OSC

/(8

 49)

ML9059E

When the internal oscillator is not used f

EXT

/4 f

EXT

/(4

 49)

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 Operating current consumption value

(1) During display operation, internal power supply OFF (The current flowing through V

DD

with V1 to V5 externally applied when an external power supply is used, not including the current for the LCD drive)

Display mode Symbol

All-white I

DD

[V

SS

= 0 V, Tj = 25°C]

Rated value

Condition Unit

Min Typ Max

V

DD

= 5 V, V1- V

SS

= 11 V, no load

V

DD

= 3.7 V, V1- V

SS

= 8 V, no load

16

12

45

35

A

Checker pattern I

DD

V

DD

= 5 V, V1- V

SS

= 11 V, no load — 16 45

A

V

DD

= 3.7 V, V1- V

SS

= 8 V, no load — 12 35

(2) During display operation, internal power supply ON (Total of currents flowing through V

DD

and V

IN

)

[V

SS

= 0 V, Tj = 25°C]

Display mode

Rated value

Symbol Condition

Min Typ Max

All-white I

DDIN

Frame reversal,

V

DD,

V

IN

= 5 V, 3-time voltage multiplication

V1 - V

SS

= 11 V, no load

Frame reversal,

V

DD,

V

IN

= 3.7 V, 4-time voltage multiplication

V1 - V

SS

= 8 V, no load

16-line reversal,

V

DD,

V

IN

= 5 V, 3-time voltage multiplication

V1 - V

SS

= 11 V, no load

Frame reversal,

V

DD,

V

IN

= 5 V, 3-time voltage multiplication

V1 - V

SS

= 11 V, no load

Checker pattern

I

DDIN

Frame reversal,

V

DD,

V

IN

= 3.7 V, 4-time voltage multiplication

V1 - V

SS

= 8 V, no load

16-line reversal,

V

DD,

V

IN

= 5 V, 3-time voltage multiplication

V1 - V

SS

= 11 V, no load

 Power save mode current consumption

Unit

[V

SS

= 0 V, Tj = 25°C]

Parameter Symbol Condition

Sleep mode

Standby mode I

I

DDS1

DDS2

V

V

DD

DD

= 3.7 V

= 3.7 V

Rated value

Min Typ Max

Unit

0.3

9

5

15

A

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Parallel Interface Timing Characteristics

 System bus Write characteristics 1 (80-series MPU)

A0

CS1

V

IH

V

IL t

AW8

(CS2 = “H”)

WR

DB0 to DB7

V

IH

V

IL t

CCLW

V

IH

(Write)

V

IL

 System bus Read characteristics 1 (80-series MPU) t

DS8

A0

V

IH

V

IL

CS1

(CS2 = “H”)

RD

DB0 to DB7

(Read) t

AW8

V

IH

V

IL t

ACC8 t

CCLR

V

OH

V

OL

V

IL

V

IL

V

IH

V

IL

V

IH

V

IL t

AH8 t

CYC8

V

IH

V

IH

V

IL t

AH8 t

CYC8

V

IH t

OH8 t

DH8 t

CCHW t

CCHR

V

OH

V

OL

V

IH

V

IH

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[V

DD

= 4.5 to 5.5 V, Tj = –40 to +85°C]

Parameter Symbol

Rated value

Condition

Min Max

Unit

Address hold time

Address setup time

System cycle time t

AH8

— t

AW8

— t

CYC8

Control L pulse width (WR) t

CCLW

Control L pulse width (RD)

Control H pulse width (WR) t

CCLR

— t

CCHW

55

Control H pulse width (RD) t

CCHR

Data setup time t

DS8

Data hold time

RD Access time

Output disable time t

DH8

— t

ACC8

CL = 100 pF t

OH8

5 50

[V

DD

= 3.7 to 4.5 V, Tj = –40 to +85°C]

Parameter Symbol

Rated value

Condition

Min Max

Unit

Address hold time t

AH8

Address setup time

System cycle time t

AW8

— t

CYC8

Control L pulse width (WR) t

CCLW

Control L pulse width (RD) t

CCLR

Control H pulse width (WR) t

CCHW

60

Control H pulse width (RD) t

CCHR

Data setup time t

DS8

Data hold time t

DH8

RD Access time

Output disable time t

ACC8

CL = 100 pF t

OH8

10 100

Note 1: The input signal rise and fall times are specified as 15ns or less.

When using the system cycle time for fast speed, the specified values are (tr + tf)

 (t

CYC8

– t

CCLW

– t

CCHW

) or (tr + tf)

 (t

CYC8

– t

CCLR

– t

CCHR

).

Note 2: All timings are specified taking the levels of 20% and 80% of V

DD

as the reference.

Note 3: The values of t

CCLW

and t

CCLR

are specified during the overlapping period of CS1 at “L” (CS2 =

“H”) and the “L” levels of WR and RD, respectively.

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 System bus Write characteristics 2 (68-series MPU)

A0

V

IH

V

IL

R/W V

IL t

AW6

CS1

(CS2 = “H”)

E t

EWHW

V

IL

V

IH t

DS6

DB0 to DB7

(Write)

V

IH

V

IL

 System bus Read characteristics 2 (68-series MPU)

A0

V

IH

V

IL

R/W

V

IH t

AW6

CS1

(CS2 = “H”)

E

DB0 to DB7

(Read)

V

IL

V

IH t

ACC6 t

EWHR

V

OH

V

OL

V

IH

V

IH

V

IH

V

IL t

AH6

V

IL t

CYC6

V

IL t

DH6

V

IH

V

IL t

EWLW

V

IH

V

IL t

AH6

V

IH t

CYC6

V

IL t

EWLR t

OH6

V

OH

V

OL

FEDL9059E-01

ML9059E

V

IL

V

IL

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Parameter Symbol

Rated value

Condition

Min Max

Unit

Address hold time

Address setup time t t

AH6

AW6

[V

DD

= 4.5 to 5.5 V, Tj = –40 to +85°C]

System cycle time

Data setup time

Data hold time

Access time

Output disable time t t

CYC6 t

DS6 t

DH6

ACC6

CL = 100 pF — 70 ns

Enable H pulse width

Enable L pulse width t

OH6

50

Read t

EWHR

Write t

EWHW

Read t

EWLR

Write t

EWLW

[V

DD

= 3.7 to 4.5 V, Tj = –40 to +85°C]

Parameter Symbol

Rated value

Condition

Min Max

Unit

Address hold time

Address setup time

System cycle time t t t

AH6

AW6

CYC6

Data setup time

Data hold time

Access time

Output disable time t

DS6 t

DH6

— t

ACC6 t

OH6

CL = 100 pF

— 140

10 100 ns

Read t

EWHR

Enable H pulse width

Write t

EWHW

Read t

EWLR

Enable L pulse width

Write t

EWLW

Note 1: The input signal rise and fall times are specified as 15ns or less.

When using the system cycle time for fast speed, the specified values are (tr + tf)

 (t

CYC6

– t

EWLW

– t

EWHW

) or (tr + tf)

 (t

CYC6

– t

EWLR

– t

EWHR

).

Note 2: All timings are specified taking the levels of 20% and 80% of V

DD

as the reference.

Note 3: The values of t

EWLW

and t

EWLR

are specified during the overlapping period of CS1 at “L” (CS2 =

“H”) and the “H” level of E.

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Serial Interface Timing Characteristics

 Serial interface

CS1

(CS2 = “1”)

A0

SCL

SI

V

IH

V

IL

V

IL t f t

CSS

V

IH

V

IL

V

IH

V

IL t

SAS t

SLW t

SDS

V

IL t

SAH

V

IH

V

IL t

SCYC

V

IH t r t

CSH t

SDH

V

IH

V

IL t

SHW

V

IL

V

IH

V

IL

[V

DD

= 4.5 to 5.5 V, Tj = –40 to +85°C]

Parameter Symbol

Rated value

Condition

Min Max

Unit

Serial clock period t

SCYC

SCL “H” Pulse width

SCL “L” Pulse width

Address setup time

Address hold time

Data setup time

Data hold time t t t t t t

SHW

SLW

SAS

SAH

SDS

SDH

100

CS setup time t

CSS

CS hold time t

CSH

Note 1: The input signal rise and fall times are specified as 15ns or less.

Note 2: All timings are specified taking the levels of 20% and 80% of V

DD

as the reference.

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Parameter Symbol

Rated value

Condition

Min Max

Unit

Serial clock period

SCL “H” Pulse width t

SCYC t

SHW

[V

DD

= 3.7 to 4.5 V, Tj = –40 to +85°C]

SCL “L” Pulse width t

SLW

Address setup time

Address hold time

Data setup time

Data hold time t

SAS t

SAH

150 t

SDS t

SDH

CS setup time t

CSS

CS hold time t

CSH

Note 1: The input signal rise and fall times are specified as 15ns or less.

Note 2: All timings are specified taking the levels of 20% and 80% of V

DD

as the reference.

 Display control output timing

V

OH

CL(OUT) t

DFR

FR

V

IH

V

IL

[V

DD

= 4.5 to 5.5 V, Tj = –40 to +85°C]

Parameter Symbol

Rated value

Condition

Min Typ Max

Unit

FR Delay time t

DFR

CL = 50 pF — 10 40 ns

[V

DD

= 3.7 to 4.5 V, Tj = –40 to +85°C]

Parameter Symbol

Rated value

Condition

Min Typ Max

Unit

FR Delay time t

DFR

CL = 50 pF — 20 80

Note 1: All timings are specified taking the levels of 20% and 80% of V

DD

as the reference.

Note 2: Valid only when the device operates in master mode. ns

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 Reset input timing

RES

Internal state

V

IH t f

V

IL t

RW

V

IL

V

IH

Being reset t r t

R

Reset complete

[V

DD

= 4.5 to 5.5 V, Tj = –40 to +85°C]

Parameter Symbol

Rated value

Condition

Min Typ Max

Unit

Reset time

Reset “L” pulse width t

R

— t

RW

0.5

0.5 — —

µs

[V

DD

= 3.7 to 4.5 V, Tj = –40 to +85°C]

Parameter Symbol

Rated value

Condition

Min Typ Max

Unit

Reset time

Reset “L” pulse width t

R

— t

RW

1

1 — —

µs

Note 1: The input signal rise and fall times (t r

, t f

) are specified as 15 ns or less.

Note 2: All timings are specified taking the levels of 20% and 80% of V

DD

as the reference.

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PIN DESCRIPTION

Number of pins

I/O Description

These are 8-bit bi-directional data bus pins that can be connected to

8-bit standard MPU data bus pins. When a serial interface is selected

(P/S = “L”):

DB7: Serial data input pin (SI)

DB0 to

DB7

RES

In this case, DB0 to DB5 will be in the high impedance state. DB0 to

DB7 will all be in the high impedance state when the chip select is in the inactive state.

Fix the DB0 to DB5 pins at “H” or “L” level.

Normally, the lowest bit of the MPU address bus is connected and used for distinguishing between data and commands.

I

A0 = “H”: Indicates that DB0 to DB7 is display data.

A1 = “L”: Indicates that DB0 to DB7 is control data.

Initial setting is made by making RES = “L”. The reset operation is

1 I made during the active level of the RES signal.

These are the chip select signals. The Chip Select of the LSI

CS1

CS2

MPU

Interface input/output of data or commands.

The active level of this signal is “L” when connected to an 80-series

MPU. This pin is connected to the RD signal of the 80-series MPU, and the data bus of the ML9059E goes into the output state when this signal is “L”.

RD

(E)

MPU. This pin will be the Enable and clock input pin when connected to a 68-series MPU.

When a serial interface is selected (P/S = “L”), fix this pin at “H” or “L” level.

The active level of this signal is “L” when connected to an 80-series

MPU. This pin is connected to the WR signal of the 80-series MPU.

The data on the data bus is latched into the ML9059E at the rising edge of the WR signal.

WR

(R/W) for the Read/Write control signal.

R/W = “H”: Read, R/W = “L”: Write

When a serial interface is selected (P/S = “L”), fix this pin at “H” or “L” level.

This is the pin for selecting the MPU interface type.

C86 = “L”: 80-Series MPU interface.

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MPU

Interface

Oscillator circuit

Display timing generator circuit

Number of pins

I/O Description

This is the pin for selecting parallel data input or serial data input.

P/S = “H”: Parallel data input.

P/S = “L”: Serial data input.

The pins of the LSI have the following functions depending on the

P/S 1 state of P/S input.

P/S Data/command

“H” A0 DB0 to DB7

RD, WR

“L” A0 SI SCL(DB6)

During serial data input, it is not possible to read the display data in the RAM

This is the pin for selecting whether to enable or disable the internal oscillator circuit for the display clock.

CLS = “L”: The internal oscillator circuit is disabled (External input).

When CLS = “L”, the display clock is input at the pin CL.

This is the pin for selecting whether master operation or slave operation is made towards the ML9059E. During slave operation, the synchronization with the LCD display system is achieved by inputting the timing signals necessary for LCD display.

M/S = “H”: Master operation

M/S = “L”: Slave operation

The functions of the different circuits and pins will be as follows depending on the states of M/S and CLS signals.

Oscillator Power

M/S CLS circuit supply circuit

“H”

“H” Enabled Enabled Output Output Output

“L” Disabled Enabled Input Output Output Output

“L”

“H” Disabled Disabled Input

“L” Disabled Disabled Input Input Output Input

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FEDL9059E-01

ML9059E

LAPIS Semiconductor

Display timing generator circuit

Power supply circuit

Number of pins

I/O Description

CL 1

This is the clock input/output pin.

The function of this pin will be as follows depending on the states of

M/S and CLS signals.

M/S CLS CL

“H” Output

“L” Input

“H” Input

“L”

“L” Input

When the ML9059E is used in the master/slave mode, the corresponding CL pin has to be connected.

This is the input/output pin for LCD display frame reversal signal.

M/S = “H”: Output

V

V

V

DD

SS

IN

12

12

5

When the ML9059E is used in the master/slave mode, the corresponding FR pin has to be connected.

This is the blanking control pin for the LCD display.

M/S = “H”: Output

When the ML9059E is used in the master/slave mode, the corresponding DOF pin has to be connected.

This is the output pin for static drive.

O

This pin is used in combination with the FR pin.

This is the pin for selecting the resistor for adjusting the voltage V1.

IRS = “H”: The internal resistor is used.

I adjusted using the external potential divider resistors connected to the pins VR. This pin is effective only in the master operation. This pin is tied to the “H” or the “L” level during slave operation.

— These pins are tied to the MPU power supply pin V

CC

.

— These are the 0 V pins connected to the system ground (GND).

These are the reference power supply pins of the voltage multiplier

— circuit for driving the LCD.

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FEDL9059E-01

ML9059E

LAPIS Semiconductor

Power supply circuit

Number of pins

I/O Description

These are the test pins for the LCD power supply voltage adjustment

V

RS

2 circuit. Leave these pins open.

These are the output pins during voltage multiplication. Connect a

V

OUT

2 capacitor between these pins and V

SS

.

V1

V2

These are the multiple level power supply pins for the LCD power supply. The voltages specified for the LCD cells are applied to these pins after resistor network voltage division or after impedance transformation using operational amplifiers. The voltages are specified taking V

SS

as the reference, and the following relationship should be maintained among them.

V1

 V2  V3  V4  V5  V

SS

Master operation: When the power supply is ON, the following

V3

V4

V5 circuit. The selection of voltages is determined by the LCD bias set command.

ML9059E

5/6

 V1

4/6

 V1

2/6

 V1

1/6

 V1

Voltage adjustment pins. Voltages between V1 and V

SS

are applied using a resistance voltage divider.

I

V1 adjustment are not used (IRS = “L”).

Do not use these pins when the internal resistors for voltage V1 adjustment are used (IRS = “H”).

These are the pins for connecting the negative side of the capacitors

Connect capacitors between these pins and VC3+, VC5+.

These are the pins for connecting the negative side of the capacitors

Connect capacitors between these pins and VC4+, VC6+.

These are the input pins for voltage multiplication.

VC3+ 3 O

IN

to the pins or leave them open, depending on voltage multiplication values.

These are the pins for connecting the positive side of the capacitors for voltage multiplication.

For 3-time voltage multiplication, the pins are configured as inputs for voltage multiplication.

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FEDL9059E-01

ML9059E

LAPIS Semiconductor

Power supply circuit

SEG0 to

SEG131

Number of pins

I/O Description

These are the pins for connecting the positive side of the capacitors for voltage multiplication.

For 2-time voltage multiplication, the pins are configured as inputs for voltage multiplication.

These are the pins for connecting the positive side of the capacitors

Connect capacitors between VS2– and these pins.

These are the LCD segment drive outputs.

One of the levels among V1, V3, V4, and V

SS

is selected depending on the combination of the display RAM content and the FR signal

Output voltage

RAM Data FR

Forward display Reverse display

132 O

H L V

SS

V4

LCD

Drive output

Test pin

L L V4

SS

Power save — V

SS

COM0 to

COM47

COMS0

COMS1

TEST1

The output voltage is V

SS

when the Display OFF command is executed.

These are the LCD common drive outputs.

One of the levels among V1, V2, V5, and V

SS

is selected depending on the combination of the scan data and the FR signal.

Scan data FR Output voltage

H H V

SS

48 O

H L V1

L H V2

L L V5

Power save — V

SS

The output voltage is V SS

when the Display OFF command is executed.

These are the common output pins only for indicators. Both pins output the same signal. Leave these pins open when they are not

2 O used. The same signal is output in both master and slave operation modes.

1 O

These are the pins for testing the IC chip. Leave these pins open during normal use.

DUMMY 67

DUMMY-

B

11

— Leave this pin open.

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FEDL9059E-01

ML9059E

LAPIS Semiconductor

FUNCTIONAL DESCRIPTION

MPU Interface

Pin WR = “L”

Pin R/W = “H” Pin R/W = “L”

68-Series

Pin E = “H” Pin E = “H”

In the case of the 80-series MPU interface, a command is started by applying a low pulse to the RD pin or the WR pin.

In the case of the 68-series MPU interface, a command is started by applying a high pulse to the E pin.

 Selection of interface type

The ML9059E carries out data transfer using either the 8-bit bi-directional data bus (DB0 to DB7) or the serial data input line (SI). Either the 8-bit parallel data input or serial data input can be selected as shown in Table 2 by setting the P/S pin to the “H” or the “L” level.

Table 2 Selection of interface type (parallel/serial)

P/S

CS1 CS2 A0 RD WR C86

D7 D6 DB0 to DB5

H: Parallel input

CS1

CS2 A0

RD WR

C86

L: Serial input

CS1

CS2 A0 — — —

A hyphen (—) indicates that the pin can be tied to the “H” or the “L” level.

 Parallel interface

D7

SI

D6

SCL

DB0 to DB5

When the parallel interface is selected, (P/S = “H”), it is possible to connect this LSI directly to the MPU bus of either an 80-series MPU or a 68-series MPU as shown in Table 3. depending on whether the pin C86 is set to “H” or “L”.

Table 3 Selection of MPU during parallel interface (80–/68–series)

C86

H: 68-Series MPU bus

L: 80-Series MPU bus

CS1

CS1

CS2

CS2

A0

A0

E

RD

R/W

WR

DB0 to DB7

DB0 to DB7

The data bus signals are identified as shown in Table 4 below depending on the combination of the signals A0, RD

(E), and WR (R/W) of Table 3.

Table 4 Identification of data bus signals during parallel interface

Common 68-Series 80-Series

A0 R/W RD WR

Display data read

Display data write

Status read

Control data write (command)

1

1

0

0

1

0

1

0

0

1

0

1

1

0

1

0

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FEDL9059E-01

ML9059E

LAPIS Semiconductor

Serial Interface

When the serial interface is selected (P/S = “L”), the serial data input (SI) and the serial clock input (SCL) can be accepted if the chip is in the active state (CS1 = “L” and CS2 = “H”). The serial interface consists of an 8-bit shift register and a 3-bit counter. The serial data is read in from the serial data input pin in the sequence DB7, DB6, ... ,

DB0 at the rising edge of the serial clock input, and is converted into parallel data at the rising edge of the 8th serial clock pulse and processed further. The identification of whether the serial data is display data or command is judged based on the A0 input, and the data is treated as display data when A0 is “H” and as command when A0 is

“L”. The A0 input is read in and identified at the rising edge of the (8

 n) th serial clock pulse after the chip has become active. Fig. 1 shows the signal chart of the serial interface. (When the chip is not active, the shift register and the counter are reset to their initial states. No data read out is possible in the case of the serial interface. It is necessary to take sufficient care about wiring termination reflection and external noise in the case of the SCL signal. We recommend verification of operation in an actual unit.)

CS1

CS2

SI

SCL

A0

DB7

1

DB6 DB5 DB4

2 3 4

DB3

5

DB2

6

DB1

7

DB0

8

DB7

9

DB6

10

DB5

11

DB4 DB3 DB2

12 13 14

Fig. 1 Signal chart during serial interface

 Chip select

The ML9059E has the two chip select pins CS1and CS2, and the MPU interface or the serial interface is enabled only when CS1 = “L” and CS2 = “H”. When the chip select signals are in the inactive state, the DB0 to DB7 lines will be in the high impedance state and the inputs A0, RD, and WR will not be effective. When the serial interface has been selected, the shift register and the counter are reset when the chip select signals are in the inactive state.

 Accessing the display data RAM and the internal registers

Accessing the ML9059E from the MPU side requires merely that the cycle time (t

CYC

) be satisfied, and high speed data transfer without requiring any wait time is possible. Also, during the data transfer with the MPU, the

ML9059E carries out a type of pipeline processing between LSIs via a bus holder associated with the internal data bus. For example, when the MPU writes data in the display data RAM, the data is temporarily stored in the bus holder, and is then written into the display data RAM before the next data read cycle. Further, when the MPU reads out data in the display data RAM, first a dummy data read cycle is carried out to temporarily store the data in the bus holder which is then placed on the system bus and is read out during the next read cycle. There is a restriction on the read sequence of the display data RAM, which is that the read instruction immediately after setting the address does not read out the data of that address, but that data is output as the data of the address specified during the second data read sequence, and hence care should be taken about this during reading.

Therefore, always one dummy read is necessary immediately after setting the address or after a write cycle: (The status read cannot use dummy read cycles.) This relationship is shown in Figs 2(a) and 2(b).

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FEDL9059E-01

ML9059E

LAPIS Semiconductor

 Data write

WR

DATA

BUS Holder

Write Signal

Dn

Latch

Dn

Dn + 1

Dn + 1

Dn + 2

Dn + 2

Dn + 3

Dn + 3

Fig. 2(a) Write sequence of display data RAM

 Data read

WR

RD

DATA

Address

Preset

Read Signal

Column

Address

BUS Holder

N

Address Set

N unknown

Preset N unknown

Data Read

(Dummy)

Dn

Increment N + 1

Dn

Data Read

Dn

Fig. 2(b) Read sequence of display data RAM

N + 2

Dn + 1

Dn + 1

Dn + 2

Data Read

Dn + 1

Dn = Data

N = Address data

 Busy flag

The busy flag being “1” indicates that the ML9059E is carrying out reset operations, and hence no instruction other than a status read instruction is accepted during this period. The busy flag is output at pin DB7 when a status read instruction is executed.

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FEDL9059E-01

ML9059E

LAPIS Semiconductor

Display Data RAM

 Display data RAM

This is the RAM storing the dot data for display and has an organization of 65 (8 pages

 8 bits +1)  132 bits. It is possible to access any required bit by specifying the page address and the column address. Since the display data

DB7 to DB0 from the MPU corresponds to the LCD display in the direction of the common lines as shown in Fig.

3, there are fewer restrictions during display data transfer when the ML9059E is used in a multiple chip configuration, thereby making it easily possible to realize a display with a high degree of freedom. Also, since the display data RAM read/write from the MPU side is carried out via an I/O buffer, it is done independent of the signal read operation for the LCD drive. Consequently, the display is not affected by flickering, etc., even when the display data RAM is accessed asynchronously during the LCD display operation.

DB0 0 1 1



0 COM0

DB1 1 0 0

DB2 0 0 0

DB3 0 1 1

DB4 1 0 0

0

0

0

0

COM1

COM2

COM3

COM4

Display data RAM LCD Display

Fig. 3 Relationship between display data RAM and LCD display

 Page address circuit

The page address of the display data RAM is specified using the page address set command as shown in Fig. 4.

Specify the page address again when accessing after changing the page. The page address 8 (DB3, DB2, DB1,

DB0

 1, 0, 0, 0) is the RAM area dedicated to the indicator, and only the display data DB0 is valid in this page.

 Column address circuit

The column address of the display data RAM is specified using the column address set command as shown in Fig.

4. Since the specified column address is incremented (by +1) every time a display data read/write command is issued, the MPU can access the display data continuously. Further, the incrementing of the column address is stopped at the column address of 83(H). Since the column address and the page address are independent of each other, it is necessary, for example, to specify separately the new page address and the new column address when changing from column 83(H) of page 0 to column 00(H) of page 1. Also, as is shown in Table 5, it is possible to reverse the correspondence relationship between the display data RAM column address and the segment output using the ADC command (the segment driver direction select command). This reduces the IC placement restrictions at the time of assembling LCD modules.

Table 5 Correspondence relationship between the display data RAM column address and the segment output

SEGMENT Output

ADC

DB0 = “0”

DB0 = “1”

SEG0

0(H)

83(H)





Column Address

Column Address

SEG131

 83(H)

 0(H)

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FEDL9059E-01

ML9059E

LAPIS Semiconductor

 Line address circuit

The line address circuit is used for specifying the line address corresponding to the common output when displaying the contents of the display data RAM as is shown in Fig. 4. Normally, the topmost line in the display is specified using the display start line address set command (COM0 output in the forward display state of the common output, and COM47 output in the reverse display state). The display area is 48 lines in the direction of increasing line address from the specified display start line address. When the indicator–dedicated common output pin (COMS) is selected, data in Line Address 40 H = page 8 and bit 0 is displayed irrespective of the display start line address. COMS selection is 49th in order.

It is possible to carry out screen scrolling by dynamically changing the line address using the display start line address set command.

 Display data latch circuit

The display data latch circuit is a latch for temporarily storing the data from the display data RAM before being output to the LCD drive circuits. Since the commands for selecting forward/reverse display and turning the display ON/OFF control the data in this latch, the data in the display data RAM will not be changed.

Oscillator Circuit

This is an RC oscillator that generates the display clock. The oscillator circuit is effective only when M/S = “H” and also CLS = “H”. The oscillations will be stopped when CLS = “L”, and the display clock has to be input to the

CL pin.

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LAPIS Semiconductor

Page Address

Data

0 0

0 0

0 0

0 0

0 1

0 1

0 1

0 1

1 0

0

0

1

1

0

0

1

1

0

0

1

0

1

0

1

0

1

0

DB0

DB1

DB2

DB3

DB4

DB5

DB6

DB7

DB0

DB0

DB1

DB2

DB3

DB4

DB5

DB6

DB7

DB0

DB1

DB2

DB3

DB4

DB5

DB6

DB7

DB0

DB1

DB2

DB3

DB4

DB5

DB6

DB7

DB0

DB1

DB2

DB3

DB4

DB5

DB6

DB7

DB0

DB1

DB2

DB3

DB4

DB5

DB6

DB7

DB0

DB1

DB2

DB3

DB4

DB5

DB6

DB7

DB0

DB1

DB2

DB3

DB4

DB5

DB6

DB7

FEDL9059E-01

ML9059E

Page0

Page1

Page2

Page3

Page4

Page5

Page6

Page7

Page8

Line

Address

When the common output state is normal display

38H

39H

3AH

3BH

3CH

3DH

3EH

3FH

40H

31H

32H

33H

34H

35H

36H

37H

25H

26H

27H

28H

29H

2AH

2BH

2CH

1DH

1EH

1FH

20H

21H

22H

23H

24H

2DH

2EH

2FH

30H

0EH

0FH

10H

11H

12H

13H

14H

15H

16H

17H

18H

19H

1AH

1BH

1CH

00H

01H

02H

03H

04H

05H

06H

07H

08H

09H

0AH

0BH

0CH

0DH

(Start)

COM

Output

COM0

COM1

COM2

COM3

COM4

COM5

COM6

COM7

COM8

COM9

COM10

COM11

COM12

COM13

COM14

COM15

COM16

COM17

COM18

COM19

COM20

COM21

COM22

COM23

COM24

COM25

COM26

COM27

COM28

COM29

COM30

COM31

COM32

COM33

COM34

COM35

COM36

COM37

COM38

COM39

COM40

COM41

COM42

COM43

COM44

COM45

COM46

COM47

COMS

The 40(H) is displayed irrespective of the display start line address.

Fig. 4 Display data RAM address map

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FEDL9059E-01

ML9059E

LAPIS Semiconductor

Display Timing Generator Circuit

This circuit generates the timing signals for the line address circuit and the display data latch circuit from the display clock. The display data is latched in the display data latch circuit and is output to the segment drive output pins in synchronization with the display clock. This circuit generates the timing signals for the line address circuit and the display data latch circuit from the display clock. The display data is latched in the display data latch circuit and is output to the segment drive output pins in synchronization with the display clock. The read out of the display data to the LCD drive circuits is completely independent of the display data RAM access from the MPU.

As a result, there is no bad influence such as flickering on the display even when the display data RAM is accessed asynchronously during the LCD display. Also, the internal common timing and LCD frame reversal (FR) signals are generated by this circuit from the display clock. The drive waveforms of the frame reversal drive method shown in Fig. 5(a) for the LCD drive circuits are generated by this circuit. The drive waveforms of the line reversal drive method shown in Fig. 5(b) are also generated by the command.

48 49 1 2 3 4 5 6 44 45 46 47 48 49 1 2 3 4 5 6

LCDCK

(display clock)

FR

V1

V2

COM0

V5

V

SS

V1

V2

COM1

V5

V

SS

RAM

DATA

SEGn

V1

V3

V4

V

SS

Fig. 5(a) Waveforms in the frame reversal drive method

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FEDL9059E-01

ML9059E

LAPIS Semiconductor

LCDCK

(display clock)

FR

48 1 2 3 4 5 6

44 45 46 47 48 49

1 2 3 4 5 6

COM0

V1

V2

V5

V

SS

V1

V2

COM1

V5

V

SS

RAM

DATA

V1

SEGn

V3

V4

V

SS

Fig. 5(b) Waveforms in the line reversal drive method

When the ML9059E is used in a multiple chip configuration, it is necessary to supply the slave side display timing signals (FR, CL, and DOF) from the master side. However, when the line reversal drive is set, the ML9059E is not used in a multiple chip configuration.

The statuses of the signals FR, CL, and

DOF

are shown in Table 6.

Table 6 Display timing signals in master mode and slave mode

Operating mode FR CL

DOF

Internal oscillator circuit enabled (CLS = H) Output Output Output

Master mode (M/S = “H”)

Internal oscillator circuit disabled (CLS = L) Output Input Output

Internal oscillator circuit disabled (CLS = H) Input Input Input

Slave mode (M/S = “L”)

Internal oscillator circuit disabled (CLS = L) Input Input Input

Note: During master mode, the oscillator circuit operates from the time the power is applied. The oscillator circuit can be stopped only in the sleep state.

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FEDL9059E-01

ML9059E

LAPIS Semiconductor

Common Output State Selection Circuit (See Table 7)

Since the common output scanning directions can be set using the common output state selection command in the

ML9059E, it is possible to reduce the IC placement restrictions at the time of assembling LCD modules.

Table 7 Common output state settings

Forward Display

Reverse Display

COM0

 COM47

COM47

 COM0

LCD Drive Circuit

This LSI incorporates 181 sets of multiplexers for the ML9059E, that generate 4-level outputs for driving the LCD.

These output the LCD drive voltage in accordance with the combination of the display data, common scanning signals, and the FR signal. Fig. 6 shows examples of the segment and common output waveforms in the frame reversal drive method.

Static Indicator Circuit

The FR pin is connected to one side of the LCD drive electrode of the static indicator and the FRS pin is connected to the other side.

The static indicator display is controlled by a command only independently of other display control commands.

The electrode of the static indicator should has a wiring pattern that is distant from the dynamic drive electrode.

If the wiring pattern is placed too near to the dynamic drive electrode, the LCD and electrode may be degraded.

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LAPIS Semiconductor

C O M 0

C O M 1

C O M 2

C O M 3

C O M 4

C O M 5

C O M 6

C O M 7

C O M 8

C O M 9

C O M 1 0

C O M 1 1

C O M 1 2

C O M 1 3

C O M 1 4

C O M 1 5

F R

C O M 0

C O M 1

C O M 2

S E G 0

S E G 1

S E G 2

C O M 0 -S E G 0

C O M 0 -S E G 1

FEDL9059E-01

ML9059E

V

D D

V

S S

V 1

V 2

V 3

V 4

V 5

0 V

-V 5

-V 4

-V 3

-V 2

-V 1

V 1

V 2

V 3

V 4

V 5

0 V

-V 5

-V 4

-V 3

-V 2

-V 1

V 1

V 2

V 3

V 4

V 5

V

S S

V 1

V 2

V 3

V 4

V 5

V

S S

V 1

V 2

V 3

V 4

V 5

V

S S

V 1

V 2

V 3

V 4

V 5

V

S S

V 1

V 2

V 3

V 4

V 5

V

S S

V 1

V 2

V 3

V 4

V 5

V

S S

Fig. 6 Output waveforms in the frame reversal drive method (FR waveform/common waveform/segment waveform/voltage difference between common and segment)

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FEDL9059E-01

ML9059E

LAPIS Semiconductor

Power Supply Circuit

This is the low power consumption type power supply circuit for generating the voltages necessary for driving

LCD devices, and consists of voltage multiplier circuits, voltage adjustment circuits, and voltage follower circuits.

In the power supply circuit, it is possible to control the ON/OFF of each of the circuits of the voltage multiplier, voltage adjustment circuits, and voltage follower circuits using the power control set command. As a result, it is also possible to use parts of the functions of both the external power supply and the internal power supply. Table

8 shows the functions controlled by the 3-bit data of the power control set command and Table 9 shows a sample combination.

Table 8 Details of functions controlled by the bits of the power control set command

Control bit Function controlled by the bit

DB2

DB1

DB0

Voltage multiplier circuit control bit

Voltage adjustment circuit (V1 voltage adjustment circuit) control bit

Voltage follower circuit (V/F circuit) control bit

Table 9 Sample combination for reference

Circuit

V

Adjustment

V/F

External voltage input

Voltage multiplier pins *1

Only the internal power supply is used

DB2 DB1 DB0

1 1 1

Voltage multiplier

V

IN

Used

Only V adjustment and

V/F circuits are used

0 1 1

Only V/F circuits are used 0 0 1



V

OUT

OPEN

Only the external power supply is used

0 0 0

  

V1 to V5 OPEN

*1: The voltage multiplier pins are the pins VS1–, VS2–, VC3+, VC4+, VC5+, and VC6+.

If combinations other than the above are used, normal operation is not guaranteed.

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LAPIS Semiconductor

 Voltage multiplier circuits

The connections for 2- to 4-time voltage multiplier circuits are shown below.

V

IN

V

IN

+

+

V

SS

V

OUT

VC6+

+

+

V

SS

V

OUT

VC6+

+

+

+

OPEN

VC4+ VC4+

VS2–

VC5+

VC3+

VS2–

VC5+

VC3+

OPEN OPEN

+

+

VS1–

2-time voltage multiplier circuit

VS1–

3-time voltage multiplier circuit

V

IN

V

SS

V

OUT

VC6+

VC4+

VS2–

VC5+

VC3+

VS1–

4-time voltage multiplier circuit

FEDL9059E-01

ML9059E

Fig. 7 Connection examples for voltage multiplier circuits

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FEDL9059E-01

ML9059E

LAPIS Semiconductor

The voltage relationships in voltage multiplication are shown in Fig. 8.

V

OUT

= 3

 V

IN

= 15.0 V

V

OUT

= 4

 V

IN

= 18 V

*1 V

IN

= 5.0 V

V

SS

= 0 V

*1 V

IN

= 4.5 V

V

SS

= 0 V

Voltage relationship in 3-time multiplication Voltage relationship in 4-time multiplication

Fig. 8 Voltage relationships in voltage multiplication

*1: The voltage range of V

IN

should be set from 6V to 18.33V so that the voltage at the pin V

OUT

does not exceed the voltage multiplier output voltage operating range.

Voltage adjustment circuit

The voltage multiplier output V

OUT

produces the LCD drive voltage V1 via the voltage adjustment circuit. Since the ML9059E incorporates a high accuracy constant voltage generator, a 64-level electronic potentiometer function, and also resistors for voltage V1 adjustment, it is possible to build a high accuracy voltage adjustment circuit with very few components. In addition, the ML9059E is available with the temperature gradients of a

VREG - about –0.05%/°C.

(a) When the internal resistors for voltage V1 adjustment are used

It is possible to control the LCD power supply voltage V1 and adjust the intensity of LCD display using commands and without needing any external resistors, if the internal voltage V1 adjustment resistors and the electronic potentiometer function are used. The voltage V1 can be obtained by the following equation A-1 in the range of V1<VOUT.

V1 = (1 + (Rb/Ra))

 VEV = (1 + (Rb/Ra))  (1 – (/324))  VREG (Eqn. A-1)

VEV (Constant voltage supply +

+ electronic potentiometer)

V1

VRS

(VREG)

VR

Internal Ra

Internal Rb

Fig. 9 V1 voltage adjustment circuit (equivalent circuit)

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VREG is a constant voltage generated inside the IC and VRS pin output voltage.

Here,

 is the electronic potentiometer function which allows one level among 64 levels to be selected by merely setting the data in the 6-bit electronic potentiometer register. The values of

 set by the electronic potentiometer register are shown in Table 10.

Table 10 Relationship between electronic potentiometer register and



DB5 DB4 DB3 DB2 DB1 DB0

63 0 0 0 0 0 0

62 0 0 0 0 0 1

61 0 0 0 0 1 0

1 1 1 1 1 1 0

0 1 1 1 1 1 1

Rb/Ra is the voltage V1 adjustment internal resistor ratio and can be adjusted to one of 7 levels by the voltage V1 adjustment internal resistor ratio set command. The reference values of the ratio (1 + Rb/Ra) according to the 3-bit data set in the voltage V1 adjustment internal resistor ratio setting register are listed in Table 11.

Table 11 Voltage V1 adjustment internal resistor ratio setting register values and the ratio (1+Rb/Ra) (Nominal)

Register

(1 + Rb/Ra)

DB2 DB1 DB0

0 0 0

0 0 1

0 1 0

0 1 1

1 0 0

1 0 1

3.0

3.5

4.0

4.5

5.0

5.5

1 1 0 6.0

Note: Use V1 gain in the range from 3 to 6 times. Because this LSI has temperature gradient, V1 voltage rises at lower temperatures. When using V1 gain of 6 times, adjust the built-in electronic potentiometer so that V1 voltage does not exceed 18 V.

When V1 is set using the built-in resistance ratio, the accuracies are shown in Table 12.

Table 12 Relation between V1 Output Voltage Accuracy and V1 Gain Using Built-in Resistor

Parameter

V1 gain

3 times 3.5 times 4 times 4.5 times 5 times 5.5 times 6 times

Unit

V1 output voltage accuracy

2.5 2.5 2.5 2.5 2.5 2.5 2.5 %

V1 maximum output voltage

9 10.5 12 13.5 15 16.5 18 V

Note: The V1 maximum output voltages in Table 12 are nominal values when Tj = 25°C and electronic potentiometer

 = 0. The V1 output voltage accuracy in Table 12 are values when V1 load current

I = 0

A, 20 V is externally input to V

OUT

, and display is turned OFF.

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(b) When external resistors are used (voltage V1 adjustment internal resistors are not used)

It is also possible to set the LCD drive power supply voltage V1 without using the internal resistors for voltage V1 adjustment but connecting external resistors (Ra' and Rb') between V

SS

& VR and between VR & V1. Even in this case, it is possible to control the LCD power supply voltage V1 and adjust the intensity of LCD display using commands if the electronic potentiometer function is used.

The voltage V1 can be obtained by the following equation B-1 in the range of V1<V

OUT

by setting the external resistors Ra' and Rb' appropriately.

V1 = (1 + (Rb'/Ra'))

 VEV = (1 + (Rb'/Ra'))  (1 – (/324))  VREG (Eqn. B-1)

External Rb'

VR

External Ra'

V

SS

+

V1

VEV (Constant voltage supply + electronic potentiometer)

Fig. 10 V1 voltage adjustment circuit (equivalent circuit)

Setting example: Setting V1 = 7 V at Tj = 25°C

When the electronic potentiometer register value is set to the middle value of (DB5, DB4, DB3, DB2, DB1, DB0)

= (1, 0, 0, 0, 0, 0), the value of

 will be 31 and that of VREG will be 3.0 V, and hence the equation B-1 becomes as follows:

V1 = (1 + (Rb'/Ra'))

 (1 – (/324))  VREG

7 = (1 + (Rb'/Ra'))

 (1 – (31/324))  3.0 (Eqn. B-2)

Further, if the current flowing through Ra' and Rb' is set as 5 µA, the value of Ra' + Rb' will be - Ra' + Rb' = 1.4

M

 (Eqn. B-3) and hence,

Rb'/Ra' = 1.58, Ra' = 543 k

, Rb' = 857 k.

In this case, the variability range of voltage V1 using the electronic potentiometer function will be as given in

Table 13.

Table 13 Example 1 of V1 variable-voltage range using electronic potentiometer function

Variable-voltage range 6.24 (

 = 63)

7.0 (

 = 31)

7.74 (

 = 0)

[V]

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(c) When external resistors are used (voltage V1 adjustment internal resistors are not used) and a variable resistor is also used

It is possible to set the LCD drive power supply voltage V1 using fine adjustment of Ra' and Rb' by adding a variable resistor to the case of using external resistors in the above case. Even in this case, it is possible to control the LCD power supply voltage V1 and adjust the intensity of LCD display using commands if the electronic potentiometer function is used.

The voltage V1 can be obtained by the following equation C-1 in the range of V1<V

OUT

by setting the external resistors R

1

, R

2

(variable resistor), and R

3

appropriately and making fine adjustment of R

2

(

R

2

).

V1 = (1 + (R

3

+ R

2

R

= (1 + (R

3

+ R

2

2

)/(R

1

+

R

2

)/(R

1

+

R

2

R

2

))

 VEV

))

 (1 – (/324))  VREG (Eqn. C-1)

Rb'

External R

3

External R

2

VR

 R

2

Ra'

External R

1

+

V1

VEV (Constant voltage supply + electronic potentiometer)

V

SS

Fig. 11 V1 voltage adjustment circuit (equivalent circuit)

Setting example: Setting V1 in the range 5 V to 9 V using R

2

at Tj = 25°C .

When the electronic potentiometer register value is set to (DB5, DB4, DB3, DB2, DB1, DB0) = (1, 0, 0, 0, 0, 0), the value of

 will be 31 and that of VREG will be 3.0 V, and hence in order to make V1 = 9 V when R

2

= 0

, the equation C-1 becomes as follows:

9 = (1 + (R

3

+ R

2

)/R

1

)

 (1 – (31/324))  (3.0) (Eqn. C-2)

In order to make V1 = 5 V when

5 = (1 + R

3

/(R

1

+R

2

))

R

2

= R

2

,

 (1 – (31/324))  (3.0) (Eqn. C-3)

Further, if the current flowing between V

SS

and V1 is set as 5 µA, the value of R

1

R

1

+ R

2

+ R

3

= 1.8 M

 (Eqn. C-4)

+ R

2

+ R

3

becomes- and hence,

R

1

= 542 k

, R

2

= 436 k

, R

3

= 822 k

.

In this case, the variability range of voltage V1 using the electronic potentiometer function and the increment size will be as given in Table 13.

Table 14 Example 2 of V1 variable-voltage range using electronic potentiometer function and variable resistor

Variable-voltage range 4.45 (

 = 63)

7.0 (

 = 31)

9.96 (

 = 0)

[V]

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In Figures 10 and 11, the voltage VEV is obtained by the following equation by setting the electronic potentiometer between 0 and 63.

VEV = (1 - (

/324))  VREG

 = 0: VEV = (1 – (0/324))  3.0 V = 3.0 V

 = 31: VEV = (1 – (31/324))  3.0 V = 2.712 V

 = 63: VEV = (1 – (63/324))  3.0 V = 2.416 V

The increment size of the electronic potentiometer at VEV when VREG = 3.0 is :

 =

2.416

= 9.27 mV (Nominal)

63

When VREG = 3.069 V,

 = 0 : VEV = 3.069 V,  = 63 : VEV = 2.472 V

The increment size is :

 =

3.069 V – 2.472 V

= 9.476 mV

63

When VREG = 2.931 V,

 = 0 : VEV = 2.931 V,  = 63 : VEV = 2.361 V

The increment size is :

2.931 V – 2.361 V

 =

= 9.047 mV

63

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* When using the voltage V1 adjustment internal resistors or the electronic potentiometer function, it is necessary to set at least the voltage adjustment circuit and the voltage follower circuits both in the operating state using the power control setting command. Also, when the voltage multiplier circuit is OFF, it is necessary to supply a voltage externally to the V

OUT

pin.

* The pin VR is effective only when the voltage V1 adjustment internal resistors are not used (pin IRS = “L”).

Leave this pin open when the voltage V1 adjustment internal resistors are being used (pin IRS = “H”).

* Since the input impedance of the pin VR is high, it is necessary to take noise countermeasures such as using short wiring length or a shielded wire .

* The supply current increases in proportion to the panel capacitance. When power consumption increases, the

V

OUT

level may fall. The voltage (V

OUT

– V1) should be more than 3 V.

 LCD Drive voltage generator circuits

The voltage V1 is divided using resistors inside the IC to generate the voltages V2, V3, V4, and V5 that are necessary for driving the LCD. In addition, these voltages V2, V3, V4, and V5 are impedance transformed using voltage follower circuits and fed to the LCD drive circuits. The bias ratio of 1/8 or 1/6 can be selected using the

LCD bias setting command.

 At built-in power-on, and transition from power save state to display mode

After built-in power-on, at the command "2F(H)" input, or on transition from power save state to display mode, the display does not operate for a maximum period of 300 ms until the built-in power is stabilized. This period of no display is not influenced by display ON/OFF command. Despite input of display ON command during this period, the display does not operate for this period. However, the command is valid. After the wait time is finished, the display operates. (During this period of no display, all commands are acceptable.)

 Command sequence for shutting off the internal power supply

When shutting off the internal power supply, it is recommended to use the procedure given in Fig. 12 of switching

OFF the power after putting the LSI in the power save state using the following command sequence.

Procedure Description Commands

OFF 0 1 0 1 1 1 0 Power save commands



Step2





Display all ON



1 0 1 0 0 1 0 1

(multiple

End Internal supply

Fig. 12 Command sequence for shutting off the internal power supply

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 Application circuits

(Two V1 pins are described in the following examples for explanation, but they are the same.)

(1) When the voltage multiplier circuit, voltage adjustment circuit, and V/F circuits are all used

When using the internal voltage V1 adjustment resistors

V

IN

= V

DD

3-time voltage multiplication

(2) When the voltage multiplier circuit, voltage adjustment circuit, and V/F circuits are all used

When not using the internal voltage V1 adjustment resistors

V

IN

= V

DD

3-time voltage multiplication

V

DD

V

DD

C1

+

IRS

V

IN

VC6+

VC4+

M/S

C1

+

IRS

V

IN

VC6+

VC4+

M/S

VS2– VS2–

+

C1

OPEN

OPEN

VC5+

VC3+

VS1–

V1

VR

V

SS

C1

OPEN

+

R

1

R

2

R

3

VC5+

VC3+

VS1–

V1

VR

V

SS

V

SS

V

SS

C1: *1

C2: *2

C1

C1

C2

C2

C2

C2

+

+

+

+

+

+

V

OUT

V1

V2

V3

V4

V5

Rall=R1+R2+R3

Rall: *3

C1:*1

C1

C1

C2

C2

C2

C2

+

+

+

+

+

+

V

OUT

V1

V2

V3

V4

V5

C2: *2

(3) When only the voltage adjustment circuit and V/F circuits are used

(4) When only the voltage adjustment circuit and V/F circuits are used

When not using the internal voltage V1 adjustment resistors When using the internal voltage V1 adjustment resistors

V

DD

V

DD

V

SS

External power supply

Rall=R1+R2+R3

Rall: *3

C1: *1

C2: *2

OPEN

OPEN

OPEN

IRS

V

IN

VC6+

VC4+

VS2–

OPEN

OPEN

OPEN

R

1

R

2

R

3

VC5+

VC3+

VS1–

V1

VR

V

SS

M/S

C1

C2

C2

C2

C2

+

+

+

+

+

V

OUT

V1

V2

V3

V4

V5

V

SS

External power supply

C1: *1

C2: *2

OPEN

OPEN

OPEN

OPEN

OPEN

OPEN

OPEN

C1

C2

C2

C2

C2

+

+

+

+

+

IRS

V

IN

VC6+

VC4+

M/S

VS2–

VC5+

VC3+

VS1–

V1

VR

V

SS

V

OUT

V1

V2

V3

V4

V5

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(5) When only the V/F circuits are used (6) When not using the internal power supply

V

DD

V

DD

OPEN

OPEN

IRS

V

IN

VC6+

VC4+

M/S

OPEN

OPEN

IRS

V

IN

VC6+

VC4+

M/S

OPEN

VS2–

OPEN

VS2–

V

SS

OPEN

OPEN

OPEN

OPEN

VC5+

VC3+

VS1–

V1

VR

V

SS

V

SS

OPEN

OPEN

OPEN

OPEN

VC5+

VC3+

VS1–

V1

VR

V

SS

External power supply

OPEN

C2

C2

C2

C2

+

+

+

+

V

OUT

V1

V2

V3

V4

V5

OPEN

External power supply

V

OUT

V1

V2

V3

V4

V5

C2: *2

Note: When trace resistance external to COG-mounted chip does not exist,

 when C1 (*1) = 0.9

F to 5.7 F, C2 (*2) = 0.42 F to 1.2 F, use in the range Rall (*3) = 1 M

 to 5 M.

 when C1 (*1) = 1.8

F to 5.7 F, C2 (*2) = 0.42 F to 1.2 F, use in the range Rall (*3) = 500 k

 to 1 M.

Make sure that voltage multiplier output voltage, and V1 output voltage have enough margin before using this LSI.

 Initial setting

Note: If electric charge remains in smoothing capacitor connected between the LCD driver voltage output pins (V1 to V5) and the V

SS

pin, a malfunction might occur: the display screen gets dark for an instant when powered on.

To avoid a malfunction at power-on, it is recommended to follow the flowchart in the “EXAMPLES OF

SETTINGS FOR THE INSTRUCTIONS” section in page 54.

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LIST OF OPERATION

DBn

No Operation

7 6 5 4 3 2 1 0 A0

RD WR

1

Display OFF

Display ON

1 0 1 0 1 1 1 0

1 0 1 0 1 1 1 1

0

0

1

1

0

0

2 Display start line set 0 1 Address 0 1 0

0 1 0

Comment

LCD Display:

OFF when DB0 = 0 ON when DB0 = 1

The display starting line address in the display RAM is set.

The page address in the display RAM is set.

3 Page address set 1 0 1 1 Address

4

6

7

Column address set

(upper bits)

Column address set

(lower bits)

Display data write

Display data read

0 0 0 1 Address

(upper)

0 0 0 0 Address

(lower)

Status * * * *

Write data

Read data

Forward 1 0 1 0 0 0 0 0

1

1

0

1

0

1

13 End

14 Reset

Reverse 1 0 1 0 0 0 0 1

Forward 1 0 1 0 0 1 1 0

9 Display

Reverse 1 0 1 0 0 1 1 1

10

OFF

(Normal

LCD display)

All-on display

ON

1 0 1 0 0 1 0 0

1 0 1 0 0 1 0 1

11 LCD bias set

1 0 1 0 0 0 1 0

1 0 1 0 0 0 1 1

12 Read-modify-write

15

Common output state select

16 Power control set

17

Voltage V1 adjustment internal resistance ratio set

1 1 1 0 0 0 0 0

1 1 1 0 1 1 1 0

1 1 1 0 0 0 1 0

1 1 0 0 0 * * *

1 1 0 0 1 * * *

0 0 1 0 1

Operating state

0 0 1 0 0

Resistance ratio setting

0

0

0

0

0

0

0

0

0

0

0

0

1

1

1

1

1

1

1

1

1

1

1

1

0 Writes data to the display data RAM.

1 Reads data from the display data RAM.

0

Correspondence to the segment output for the display data RAM address

0

Forward when DB0 = 0

Reverse when DB0 = 1

0

0

0

0

Forward or reverse LCD display mode

Forward when DB0 = 0

Reverse when DB0 = 1

LCD

Normal display when DB0 = 0

All-on display when DB0 = 1

0

Sets the LCD drive voltage bias ratio.

1/8 when DB0 = 0 and 1/6 when DB0 = 1

0

0

Incrementing column address

During a write: +1

During a read: 0

0 Releases the read-modify-write state.

0 Internal reset

0

0

Selects the common output scanning direction.

Forward when DB3 = 0

Reverse when DB3 = 1

Selects the internal resistor ratio.

0 1 0

Set the lower 3 bits.

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No Operation

DBn

7 6 5 4 3 2 1 0 A0

RD WR

Comment

18

Electronic potentiometer

Electronic

Potentiometer mode set

Electronic potentiometer register set

1 0 0 0 0 0 0 1

* * Electronic potentiometer value

0 1

0 1

0

Sets a 6-bit data in the electronic potentiometer register to adjust the V1

output voltage.

0

(2-byte command)

19

20

1)

Static indicator

Static indicator register set

LCD drive method set

Line reversal number set

22 NOP

OFF

ON

1 0 1 0 1 1 0 0

1 0 1 0 1 1 0 1

* * * * * * State

1 1 0 1 0 * * *

1 1 0 1 1 * * *

0 1

0 1

* * *

Number of lines

0 1

1 1 1 0 0 0 1 1

0 1

0 1

0 1

0 1

0 OFF when DB0 = 0

0

0

ON when DB0 = 1

Sets the blinking state.

(2-byte command)

0

0

Frame reversal when

DB3 = 0.

0 Line reversal when DB3 = 1

0

Sets the number (2-byte command) of line reversal.

Compound command of

Display OFF and Display all-on.

The “No Operation” command.

The command for factory

23 Test 1 1 1 1 * * * * 0 1 0

testing of the IC chip.

*: Invalid data (input: Don’t care, output: Unknown)

Note 1: When the line reversal drive is set, the ML9059E is not used in a multiple chip configuration.

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DESCRIPTIONS OF OPERATION

Display ON/OFF (Write)

This is the command for controlling the turning on or off the LCD panel. The LCD display is turned on when a “1” is written in bit DB0 and is turned off when a “0” is written in this bit.

A0 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0 1 0 1 0 1 1 1 1

0 1 0 1 0 1 1 1 0

Display Start Line Set (Write)

This command specifies the display starting line address in the display data RAM.

Normally, the topmost line in the display is specified using the display start line set command.

It is possible to scroll the display screen by dynamically changing the address using the display start line set command.

A0 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0

1

2

0 0 1 0 0 0 0 0 0

0 0 1 0 0 0 0 0 1

0 0 1 0 0 0 0 1 0

62

63

0 0 1 1 1 1 1 1 0

0 0 1 1 1 1 1 1 1

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Page Address Set (Write)

This command specifies the page address which corresponds to the lower address when accessing the display data

RAM from the MPU side.

It is possible to access any required bit in the display data RAM by specifying the page address and the column address.

Page A0 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0

1

2

0 1 0 1 1 0 0 0 0

0 1 0 1 1 0 0 0 1

0 1 0 1 1 0 0 1 0

7 0 1 0 1 1 0 1 1 1

8 0 1 0 1 1 1 0 0 0

Note: Do not specify values that do not exist as an address.

Column Address Set (Write)

This command specifies the column address of the display data RAM. The column address is specified by successively writing the upper 4 bits and the lower 4 bits. Since the column address is automatically incremented

(by + 1) every time the display data RAM is accessed, the MPU can read or write the display data continuously.

The incrementing of the column address is stopped at the address 83(H).

A0 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0

1

2

0 0 0 0 0 0 0 0

0 0 0 0 0 0 0 1

0 0 0 0 0 0 1 0

130 1 0 0 0 0 0 1 0

131 1 0 0 0 0 0 1 1

Note: Do not specify values that do not exist as an address.

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Status Read (Read)

A0 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

*: Invalid data

BUSY

ADC

ON/OFF

When BUSY is '1', it indicates that the internal operations are being made or the LSI is being reset. Although no command is accepted until BUSY becomes '0', there is no need to check this bit if the cycle time can be satisfied.

This bit indicates the relationship between the column address and the segment driver.

0: Reverse (SEG131

 SEG0); column address 0(H)  83(H)

1: Forward (SEG0

 SEG131); column address 0(H)  83(H)

(Opposite to the polarity of the ADC command.)

This bit indicates the ON/OFF state of the display. (Opposite to the polarity of the display ON/OFF command.)

0: Display ON

1: Display OFF

RESET

This bit indicates that the LSI is being reset due to the RES signal or the reset command.

0: Operating state

1: Being reset

Display Data Write (Write)

This command writes an 8-bit data at the specified address of the display data RAM. Since the column address is automatically incremented (by +1) after writing the data, the MPU can write successive display data to the display data RAM.

A0 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

Display Data Read (Read)

This command read the 8-bit data from the specified address of the display data RAM. Since the column address is automatically incremented (by +1) after reading the data, the MPU can read successive display data from the display data RAM. Further, one dummy read operation is necessary immediately after setting the column data.

The display data cannot be read out when the serial interface is being used.

A0 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

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ADC Select (Segment driver direction select) (Write)

Using this command it is possible to reverse the relationship of correspondence between the column address of the display data RAM and the segment driver output. It is possible to reverse the sequence of the segment driver output pin by the command.

A0 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

Forward 0 1 0 1 0 0 0 0 0

Reverse 0 1 0 1 0 0 0 0 1

Forward/Reverse Display Mode (Write)

It is possible to toggle the display on and off condition without changing the contents of the display data RAM. In this case, the contents of the display data RAM will be retained.

A0 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

Forward

Reverse

LCD Display All-on ON/OFF (Write)

Using this command, it is possible to forcibly turn ON all the dots in the display irrespective of the contents of the display data RAM. In this case, the contents of the display data RAM will be retained.

This command is given priority over the Forward/reverse display mode command.

A0 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

All-on display OFF

(Normal display)

0 1 0 1 0 0 1 0 0

All-on ON 0 1 0 1 0 0 1 0 1

The power save mode will be entered into when the Display all-on ON command is executed in the display OFF condition.

LCD Bias Set (Write)

This command is used for selecting the bias ratio of the voltage necessary for driving the LCD device or panel.

A0 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0 1 0 1 0 0 0 1 0

0 1 0 1 0 0 0 1 1

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LAPIS Semiconductor

Read Modify Write (Write)

This command is used in combination with the End command. When this command is issued once, the column address is not changed when the Display data read command is issued, but is incremented (by +1) only when the

Display data write command is issued. This condition is maintained until the End command is issued. When the

End command is issued, the column address is restored to the address that was effective at the time the

Read-modify-write command was issued last. Using this function, it is possible to reduce the overhead on the

MPU when repeatedly changing the data in special display area such as a blinking cursor.

A0 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0 1 1 1 0 0 0 0 0

End (Write)

This command releases the read-modify-write mode and restores the column address to the value at the beginning of the mode.

A0 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0 1 1 1 0 1 1 1 0

Restored

Column address

N N + 1 N + 2

N + 3

....

N + m N

Read-modify-write mode set End

Reset (Write)

This command initializes the display start line number, column address, page address, common output state, voltage V1 adjustment internal resistor ratio, electronic potentiometer function, and the static indicator function, and also releases the read-modify-write mode or the test mode. This command does not affect the contents of the display data RAM.

The reset operation is made after issuing the reset command.

The initialization after switching on the power is carried out by the reset signal input to the RES pin.

A0 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0 1 1 1 0 0 0 1 0

Common Output State Select (Write)

This command is used for selecting the scanning direction of the common output pins.

DB6 DB5 DB4 DB3

*: Invalid data

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LAPIS Semiconductor

Power Control Set (Write)

This command set the functions of the power supply circuits.

Voltage multiplier circuit: OFF

Voltage multiplier circuit: ON

0

0

0

0

0

0

DB5 DB4

1

1

0

0

DB3

1

1

Voltage adjustment circuit: OFF

Voltage adjustment circuit: ON

Voltage follower circuits: OFF

0

0

0

0

0

0

0

0

0

1

1

1

0

0

0

1

1

1

Voltage follower circuits: ON 0 0 0 1 0

Voltage V1 Adjustment Internal Resistor Ratio Set

This command sets the ratios of the internal resistors for adjusting the voltage V1.

1

Resistor ratio A0 DB7 DB6 DB5 DB4 DB3

0

1

0

1

0

1

DB2 DB1 DB0

3.0

3.5

4.0

4.5

5.0

5.5

6.0

0 0 0 1 0 0 0 0 0

0 0 0 1 0 0 0 0 1

0 0 0 1 0 0 0 1 0

0 0 0 1 0 0 0 1 1

0 0 0 1 0 0 1 0 0

0 0 0 1 0 0 1 0 1

0 0 0 1 0 0 1 1 0

0 0 0 1 0 0 1 1 1

Note: Because this LSI has temperature gradient, V1 rises at lower temperatures. When using V1 gain of 6 times, adjust the built-in electronic potentiometer so that V1 does not exceed 18 V.

Electronic Potentiometer (2-byte command)

This command is used for controlling the LCD drive voltage V1 output by the voltage adjustment circuit of the internal LCD power supply and for adjusting the intensity of the LCD display.

This is a two-byte command consisting of the Electronic potentiometer mode set command and the Electronic potentiometer register set command, both of which should always be issued successively as a pair.

 Electronic potentiometer mode set (Write)

When this command is issued, the electronic potentiometer register set command becomes effective.

Once the electronic potentiometer mode is set, it is not possible to issue any command other than the Electronic potentiometer register set command. This condition is released after data has been set in the register using the

Electronic potentiometer register set command.

A0 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0 1 0 0 0 0 0 0 1

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LAPIS Semiconductor

 Electronic potentiometer register set (Write)

By setting a 6-bit data in the electronic potentiometer register using this command, it is possible to set the LCD drive voltage V1 to one of the 64 voltage levels.

The electronic potentiometer mode is released after some data has been set in the electronic potentiometer register using this command.



A0 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

63

62

61

60

0 * * 0 0 0 0 0 1

0 * * 0 0 0 0 0 1

0 * * 0 0 0 0 1 0

0 * * 0 0 0 0 1 1

1 1 1 1 1 1 0

0 0 * * 1 1 1 1 1 1

*: Invalid data

Set the data (*, *, 1, 0, 0, 0, 0, 0) when not using the electronic potentiometer function.

Sequence of setting the electronic potentiometer register:

Static Indicator (2-byte command)

Electronic potentiometer mode set

Electronic potentiometer register set

The electronic potentiometer mode is released

This command is used for controlling the static drive type indicator display.

Static indicator display is controlled only by this command and is independent of all other display control commands.

Since the Static indicator ON command is a two-byte command used in combination with the static indictor register set command, these two commands should always be used together.

(The Static indicator OFF command is a single byte command.)

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LAPIS Semiconductor

 Static indicator ON/OFF (Write)

When the Static indicator ON command is issued, the Static indicator register set command becomes effective.

Once the Static indicator ON command is issued, it is not possible to issue any command other than the Static indicator register set command. This condition is released only after some data is written into the register using the static indicator register set command.

Static indicator A0 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

OFF 0 1 0 1 0 1 1 0 0

ON 0 1 0 1 0 1 1 0 1

 Static indicator register set (Write)

This command is used to set data in the 2-bit static indicator register thereby setting the blinking state of the static indicator.

Indicator A0 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

OFF

ON(Blinking at about 1sec intervals)

ON(Blinking at about 0.5sec intervals)

0 * * * * * * 0 0

0 * * * * * * 0 1

0 * * * * * * 1 0

0 * * * * * * 1 1

*: Invalid data

Sequence of setting the static indicator register:

Static indicator ON

Static indicator register set

The static indicator mode is released

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LAPIS Semiconductor

LCD Drive Method Set (Write)

This command sets the LCD drive method.

 Line reversal drive (2-byte command)/frame reversal drive select

Line or frame reversal drive can be selected as the LCD drive method.

When selecting line reversal drive, which is 2-byte command used with line reversal number set command, be sure to use both commands successively.

Once line reversal drive is set, commands other than line reversal number set command cannot be used. This state is released after data is set to the register by line reversal number set command.

The frame reversal set command is a single byte command.

LCD drive method A0 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0 1 1 0 1 0 * * *

0 1 1 0 1 1 * * *

*: Invalid data

 Line reversal number set (Write)

The number of lines is set when the line reversal is set using the LCD drive method set command.

Number of line reversal A0 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

1

2

3

4

0 * * * 0 0 0 0 0

0 * * * 0 0 0 0 1

0 * * * 0 0 0 1 0

0 * * * 0 0 0 1 1

31 1 1 1 1 0

32 0 * * * 1 1 1 1 1

*: Invalid data

LCD drive method set

Number of line is set in case of line reversal

Note 1: Because the number of line reversal depends on panel size and panel load capacitance, set the optimum number of lines at the time of ES evaluation.

Note 2: When line reversal drive is used, a multiple chip configuration cannot be achieved.

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LAPIS Semiconductor

Power Save (Compound command)

The LSI goes into the power save state when the Display all-on ON command is issued when the LSI is in the display OFF state, and it is possible to greatly reduce the current consumption in this state. The power save state is of two types, namely, the sleep state and the standby state, and the LSI goes into the standby state when the static indicator has been made ON.

The display data and the operating mode just before entering the power save mode are retained in both the sleep state and the standby state, and also the MPU can access the display data RAM and other registers in these states.

The power save mode is released by issuing the Display all-on OFF command. (See the following figure.)

Static indicator OFF

Static indicator ON

Power save command issue (compound command)

Sleep state Standby state

Power save OFF command

(Display all-on OFF command)

Sleep state released

Power save OFF command

(Display all-on OFF command)

Standby state released

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LAPIS Semiconductor

 Sleep state

In this state, all the operations of the LCD display system are stopped and it is possible to reduce the current consumption to a level near the idle state current consumption unless there are accesses from the MPU. The internal conditions in the sleep state are as follows:

(1) The oscillator circuit and the LCD power supply are stopped.

(2) All the LCD drive circuits are stopped and the segment and common driver outputs will be at the V

SS

level.

 Standby state

All operations of the dynamic LCD display section are stopped, only the static display circuits for the indicators operate and hence the current consumption will be the minimum necessary for static drive. The internal conditions in the standby state are as follows:

(1) The power supply circuit for LCD drive is stopped. The oscillator circuit will be operating.

(2) The LCD drive circuits for dynamic display are stopped and the segment and common driver outputs will be at the V

SS

level. The static display section will be operating.

Note: When using an external power supply, stop external power supply at power save start-up.

For example, when providing each level of LCD drive voltage with external voltage divider, add a circuit for cutting off current flowing through the resistors of the voltage divider when initiating power save.

The ML9059E has LCD display blanking control pin, DOF, which goes "L" at power save start-up. The external power supply can be stopped using DOF output.

NOP (Write)

This is a No Operation command.

A0 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0 1 1 1 0 0 0 1 1

Test (Write)

This is a command for testing the IC chip. Do not use this command. When the test command is issued by mistake, this state can be released by issuing a NOP command.

A0 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0 1 1 1 1 * * * *

*: Invalid data

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LAPIS Semiconductor

Initialized Condition Using the RES Pin

This LSI goes into the initialized condition when the RES input goes to the “L” level. The initialized condition consists of the following conditions.

(2)

Forward display mode

(3) ADC select: Incremented (ADC command DB0 = “L”)

(4) Power control register: (DB2, DB1, DB0) = (0, 0, 0)

(5) The registers and data in the serial interface are cleared.

(6) LCD Power supply bias ratio: 1/8 bias

(7) All display dots OFF

(9) Static indicator: OFF

Static indicator register: (DB1, DB0) = (0, 0)

(10) Line 1 is set as the display start line.

(11) The column address is set to address 0.

(12) The page address is set to 0.

(13) Common output state: Forward

(14) Voltage V1 adjustment internal resistor ratio register: (DB2, DB1, DB0) = (1, 0, 0)

(15) The electronic potentiometer register set mode is released.

Electronic potentiometer register: (DB5, DB4, DB3, DB2, DB1, DB0) = (1, 0, 0 ,0, 0, 0)

(16) The LCD drive method is set to the frame reversal drive.

Line reversal number register: (DB4, DB3, DB2, DB1, DB0) = (1, 0, 0, 0, 0)

On the other hand, when the reset command is used, only the conditions (8) to (15) above are set.

As is shown in the “MPU Interface (example for reference)”, the RES pin is connected to the Reset pin of the MPU and the initialization of this LSI is made simultaneously with the resetting of the MPU. This LSI always has to be reset using the RES pin at the time the power is switched ON. Also, excessive current can flow through this LSI when the control signal from the MPU is in the high impedance state. It is necessary to take measures to ensure that the input pins of this LSI do not go into the high impedance state after the power has been switched ON. When the built-in LCD drive power supply circuit of the ML9059E is not used, it is necessary that RES = “L” when the external LCD drive power supply goes ON. During the period when RES = “L”, although the oscillator circuit is operating, the display timing generator would have stopped and the pins CL, FR, FRS, and DOF would have been tied to the “H” level. There is no effect on the pins DB0 to DB7.

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LAPIS Semiconductor

EXAMPLES OF SETTINGS FOR THE INSTRUCTIONS

When Using the Internal Power Supply Immediately After Power-on

V

DD

-V

SS

Power supply ON when the pin RES = “L”

Power supply stabilization

Release reset state (RES Pin = “H”)

Initial settings state (default) *1

Function setting using command input (user settings)

LCD bias set

*2

ADC select

*3

Common output state select

Line reversal/frame reversal drive select

*4

*5

Function setting using command input (user settings)

Setting voltage V1 adjustment internal resistor ratio

Electronic potentiometer

*6

*7

Function stabilization using command input (user settings)

Power control set *8

Wait for more than 300 ms

*(a)

*(b)

Initial setting state complete

*(a): Carry out power control set within 5ms after releasing the reset state.

The 5ms duration changes depending on the panel characteristics and the value of the smoothing capacitor. We recommend verification of operation using an actual unit.

*(b): When trace resistance in COG mounting does not exist, wait for over 300 ms.

Since this value varies with trace resistance, V1, smoothing capacitors, or voltage multiplier capacitors in COG mounting, confirm operation on an actual circuit board when using this LSI.

Notes: Sections to be referred to

*1: Functional description “Reset circuit”

*2: Description of operation “LCD bias set”

*3: Description of operation “ADC select”

*4: Description of operation “Common output state select”

*5: Description of operation “Line reversal/frame reversal drive select”

*6: Functional description “Power supply circuit”, Operation description “Voltage V1 adjustment internal resistor ratio set”

*7: Functional description “Power supply circuit”, Description of operation “Electronic potentiometer”

*8: Functional description “Power supply circuit”, Description of operation “Power control set”

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LAPIS Semiconductor

When Not Using the Internal Power Supply Immediately After Power-on

V

DD

-V

SS

Power supply ON when the pin RES = “L”

Power supply stabilization

Release reset state (RES Pin = “H”)

Initial settings state (default) *1

Start power save mode (compound command) *9

Function setting using command input (user settings)

LCD bias set

*2

ADC select

*3

Common output state select

*4

Line reversal/frame reversal drive select

*5

*(a)

Function setting using command input (user settings)

Setting voltage V1 adjustment internal resistor ratio

Electronic potentiometer

*6

*7

Power save OFF

*9

Function setting using command input (user settings)

Power control set

*8

*(b)

Wait for more than 300 ms

Initial setting state complete

*( c)

*(a): Enter the power save state within 5ms after releasing the reset state.

*(b): Carry out power control set within 5ms after releasing the power save state.

The 5ms duration in *(a) and *(b) changes depending on the panel characteristics and the value of the smoothing capacitor. We recommend verification of operation using an actual unit.

*(c): When trace resistance in COG mounting does not exist, wait for over 300 ms.

Since this value varies with trace resistance, V1, smoothing capacitors, or voltage multiplier capacitors in COG mounting, confirm operation on an actual circuit board when using this LSI.

Notes: Sections to be referred to

*1: Functional description “Reset circuit”

*2: Description of operation “LCD bias set”

*3: Description of operation “ADC select”

*4: Description of operation “Common output state select”

*5: Description of operation “Line reversal/frame reversal drive select”

*6: Functional description “Power supply circuit”, Description of operation “Voltage V1 adjustment internal resistor ratio set”

*7: Functional description “Power supply circuit”, Description of operation “Electronic

potentiometer”

*8: Functional description “Power supply circuit”, Description of operation “Power control set”

*9: The power save state can be either the sleep state or the standby state.

Description of operation “Power save (compound command)”

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LAPIS Semiconductor

Data Display

End of initial settings

Function stabilization using command input (user settings)

Display start line set

Function stabilization using command input (user settings)

Page address set

Function stabilization using command input (user settings)

Column address set

*11

*12

Function stabilization using command input (user settings)

Display data write

*10

*13

No

No

End of page write?

Yes

End of display data write?

Yes

Function stabilization using command input (user settings)

Display ON/OFF

End of data display

Notes: Sections to be referred to

*10: Description of operation “Display start line set”

*11: Description of operation “Page address set”

*14

*12: Description of operation “Column address set”

*13: Description of operation “Display data write”

*14: Description of operation “Display ON/OFF”

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Power Supply OFF (*15)

Any state

Function stabilization using command input (user settings)

*16

V

DD

-V

SS

Power supply OFF

Notes: Sections to be referred to

*15: The power supply of this LSI is switched OFF after switching OFF the internal power supply.

Function description “Power supply circuit”

If the power supply of this LSI is switched OFF when the internal power supply is still ON, since the state of supplying power to the built-in LCD drive circuits continues for a short duration, it may affect the display quality of the LCD panel. Always follow the power supply switching OFF

sequence.

*16: Description of operation “Power save”

*17: After reset is input the power supply may off without obeying above sequence.

Refresh

Although the ML9059E holds operation state by commands, excessive external noise might change the internal state.

On a chip-mounting and system level, it is necessary to take countermeasures against preventing noise from occurring. It is recommended to use the refresh sequence periodically to control sudden noise.

Set to the state in which all commands have been set.

- LCD bias set

- ADC select

- Display Forwar/Reverse

- Set “LCD ALL-on display“ ON

- Common output state select

- LCD drive mode set

- Static indecator register set

- Voltage V1 adjustment internal resistance ratio set

- Electronic potnetiometer

- Power control set

- Release the read-modify-write sate(END)

(*18)

Test mode release command

(E3(H))

Refresh RAM

- Set “NOP” operation

- Display start line set

- Page address set

- Column address set

- Display data write

- Display ON

*18: Regardless of presence of setting of “Read-modify-write”commanfd, please carry out “END” command.

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MPU INTERFACE

The ML9059E series ICs can be connected directly to the 80-series and 68-series MPUs.

Further, by using the serial interface, it is possible to operate the LSI with a minimum number of signal lines.

In addition, it is possible to expand the display area by using the ML9059E series LSIs in a multiple chip configuration. In this case, it is possible to select the individual LSI to be accessed using the chip select signals.

80-Series MPU

V

DD

V

CC

A0

A1 to A7

IORQ

GND

DB0 to DB7

RD

WR

RES

Decoder

A0

CS1

V

DD

CS2

DB0 to DB7

RD

WR

RES

V

SS

C86

P/S

RESET

V

SS



68-Series MPU

V

DD

V

CC

A0

A1 to A15

VMA

DB0 to DB7

E

R/W

RES

GND

Decoder

A0

CS1

V

DD

CS2

DB0 to DB7

E

R/W

RES

V

SS

C86

P/S

RESET

V

SS



Serial interface

V

DD

V

CC

V

DD

C86 Port 3

Port 4

Port 5

A0

CS1

CS2

Can be tied to either level.

GND

Port1

Port2

RES

SI

SCL

RES

V

SS

P/S

RESET

V

SS

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PAD CONFIGURATION

Pad Layout

Chip Size : 9.164

 2.982 mm

309

347

308

1

149

104

148

105

Pad Coordinates

Pad No. Pad Name X (µm) Y (µm) Pad No. Pad Name

-4462.5 21

X (µm)

-4377.5 22 CS2

Y (µm)

-4292.5 23 V

DD

-1376.0

24

26 V

SS

-2337.5

27

28

9 V

SS

-3782.5 29 V

DD

-1376.0

-3272.5 35 DB5

18 CL -3017.5 38 -1376.0

-1376.0 V

DD

-1376.0

20 V

SS

-2847.5 40 V

DD

-1147.5

Note: Leave DUMMY and DUMMY-B pads open.

Do not run traces around. Run traces through DUMMY and DUMMY-B pads individually, not in common.

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Y (µm) Pad No. Pad Name X (µm) Pad No. Pad Name X (µm) Y (µm)

41 V

DD

-1062.5 81 V1 2337.5

42 V

DD

-977.5 82 V1 2422.5

43 V

DD

-892.5 83 V2 2507.5

44 V

DD

-807.5 84 V2 2592.5

45 V

IN

-722.5 85 V3 2677.5

46 V

IN

-637.5 86 V3 2762.5

47 V

IN

-552.5 87 V4 2847.5

48 V

IN

-467.5 88 V4 2932.5

49 V

IN

-382.5 89 V5 3017.5

50 V

SS

-297.5 90 V5 3102.5

51 V

SS

-212.5 91 VR 3187.5

52 V

SS

-127.5 92 VR 3272.5

53 V

SS

-42.5 93 V

DD

3357.5

54 V

SS

42.5

55 V

SS

127.5

56 V

SS

212.5 96 V

SS

3612.5

57 V

OUT

297.5

58 V

OUT

382.5 98 P/S 3782.5

-1376.0

DD

-1376.0

-1376.0

SS

-1376.0

-1376.0

DD

-1376.0

77 V

SS

1997.5

78 V

RS

2082.5

79 V

RS

2167.5

80 V

DD

2252.5

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LAPIS Semiconductor

Pad No. Pad Name X (µm) Y (µm) Pad No. Pad Name X (µm) Y (µm)

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Pad No. Pad Name X (µm) Y (µm) Pad No. Pad Name X (µm) Y (µm)

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LAPIS Semiconductor

Pad No. Pad Name X (µm) Y (µm) Pad No. Pad Name X (µm) Y (µm)

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LAPIS Semiconductor

ML9059E ALIGNMENT MARK SPECIFICATION 1

Alignment Mark Coordinates

E

A

D

Y

         



Alignment mark X(µm) Y(µm)

B

FEDL9059E-01

ML9059E

X

C

F

Coordinate point

F 4458.5 –1368

Alignment Mark Construction Layer

A, B, C, D: Metal Layer E,F:Bump Layer

Alignment Mark Specification

Coordinate point mark

A, B, C, D

Width

E, F b Alignment mark Size

Alignment mark-to-adjacent pad metal Distance (MIN.)

A, B, C, D

E, F

A, B, C 60

D 106.6 c

34

43

100

98

Alignment mark-to-adjacent pad bump Distance (MIN.)

E 109.4

F 77 b a c b c

Bump a

Metal

b a b c c a

Bump

Metal

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LAPIS Semiconductor

ML9059E GOLD BUMP SPECIFICATION

Gold Bump Specification

Symbol Parameter Max.

A Bump Pitch (Min.Section:Segment Section) 52 — —

m

B

C

Bump Size (Segment Section:Pitch Direction)

Bump Size (Segment Section:Depth Direction)

29

114

32

117

35

120

m

m

D

E

F

G

Bumo-to-Bump Distance

(Segment Section:Pitch Direction)

Bump Pitch (Min.Section:Input Section)

Bump Size (Input Section:Pitch Direction)

Bump Size (Input Section:Depth Direction)

85

57

67

60

70

63

73

m

m

m

H

I

J

L

Bumo-to-Bump Distance

(Input Section:Pitch Direction)

Bump Size (Figure “L” alignment mark: Length)

Bump Size (Figure “L” alignment mark: width)

Pad center-to-Bump center allowable error

Bumph Height Dispersion Inside Chip (Range)

Bump Edge Height

Shear Strength (g)

95

40

12

18

50

30

98

43

15

101

46

2

m

18

m

3

3

110

70

m

m

m

m g

Hv

Hv

Bump hardness: High (Hv: 25g load)

Bump hardness: Low (Hv: 25g load)

• Chip Thickness: 625

15 m

• Chip Size: 9.164mm

 2.982mm

Top View and Cross Section View

A B

Segment

Section

E

D

F

Figure “L”

Alignment Mark

Input Section H

Cross Section View

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15

14

13

12

11

10

9

8

7

6

0

REFERENCE DATA

VIN=4.8V

C1

+

C1

+

R

R

R

R

R

R

R

OPEN

VIN

VSS

VC6+

VC4+

VS2



VS1

VC5+

VC3+

VOUT

ML9059E Chip

R

I LOAD

+

C1

Equivalent circuit to 3-time voltage multiplier with trace resistances external to COG-mounted chip

ML9059E voltage multiplier load characteristics

- Load current dependency at 3-time multiplication

0.1

0.2

0.3

0.4

0.5

0.6

0.7

Load current ILoad [mA]

0.8

0.9

1

R=0

R=100

R=200

Evaluation

Conditions

Tj=90

C

Voltage multiplier

Capacitor

C1=1

F

VIN=4.8V, 3-time multiplication

Only a voltage multiplier circuit operates by power control set command

“2C”

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FEDL9059E-01

ML9059E

LAPIS Semiconductor

12

11

10

9

8

7

0

18

17

16

15

14

13

REFERENCE DATA

VIN=4.5V

C1

C1

+

+

C1

+

R

R

R

R

R

R

R

R

VIN

VSS

VC6+

VC4+

VS2

VS1

VC5+

VC3+

VOUT

ML9059E Chip

R

I LOAD

+

C1

Equivalent circuit to 4-time voltage multiplier with trace resistances external to COG-mounted chip

ML9059E voltage multiplier load characteristics

- Load current dependency at 4-time multiplication

0.1

0.2

0.3

0.4

0.5

0.6

Load current ILoad [mA]

0.7

0.8

0.9

1

Evaluation

Conditions

Tj=90

C

Voltage multiplier

Capacitor

C1=1

F

VIN=4.5V,4-time multiplication

Only a voltage multiplier circuit operates by power control set command

“2C”

R=0

R=100

R=200

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FEDL9059E-01

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LAPIS Semiconductor

EQUIVALENT CIRCUIT FOR EVALUATING POWER-UP STABILIZATION TIME IN COG MOUNTING

VIN=5.0V

C1

C1

+

+

C1

+

R

R

R

R

R

R

R

R

R

OPEN

VIN

VIN

VSS

VOUT

VC6+

Dummy

VC4+

VS2

VS1

VC5+

VC3+

VSS

VOUT

VC6+

Dummy

VC4+

VS2

VS1

VC5+

VC3+

Chip

V1

V2

V3

V4

V5

ML9059E

Chip

V1

V2

V3

V4

V5

ML9059E

200

200

200

200

200

C1

+

C2

+

C2

+

C2

+

C2

+

Equivalent circuit to 3-time voltage multiplier with trace resistances external to COG-mounted chip

VIN=4.5V

C1

C1

+

C1

C1

+

+

+

R

R

R

R

R

R

R

R

200

200

200

200

200

+

+

+

+

+

C1

C2

C2

C2

C2

Equivalent circuit to 4-time voltage multiplier with trace resistances external to COG-mounted chip

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LAPIS Semiconductor

REFERENCE DATA

(The rise time until V1-V5 is stabilized when command “2F” is input after power-on in COG mounting.)

3-time voltage multiplication

Reference value of V1-V5 rise stabilization time in ML9059E COG mounting

Conditions :VIN=5V,3-time multiplication,V1=12V,trace resistance external to COG-mounted chip

R=150

, Tj=-40C to +85C

300

250

Parameter: smoothing capacitor C2

C2=0.47 F

C2=1.0 F

200

150

100

50

0

0 0.5

1 1.5

2 2.5

3 3.5

Value of voltage multiplier capacitor C1 [

F]

4 4.5

5

4-time voltage multiplication

Reference value of V1-V5 rise stabilization time in ML9059E COG mounting

Conditions :VIN=4.5V,4-time multiplication,V1=12V,trace resistance external to COG-mounted chip

R=150

, Tj=-40C to +85C

300

250

Parameter: smoothing capacitor C2

C2=0.47 F

C2=1.0 F

200

150

100

50

0

0 0.5

1 1.5

2 2.5

3 3.5

Value of voltage multiplier capacitor C1 [

F]

4 4.5

5

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ML9059E

LAPIS Semiconductor

REFERENCE DATA

(The rise time until V1-V5 is stabilized when command “2F” is input after power-on in COG mounting.)

3-time voltage multiplication

Reference value of V1-V5 rise stabilization time in ML9059E COG mounting

Conditions :VIN=5V, 3-time multiplication, Tj=-40

C to +85C

Voltage multiplier capacitor C1=3.3

F, smoothing capacitor C2=1F

300

250

200

Parameter: trace resistance external to COG-mounted chip

R=100

R=200

150

100

50

0

10 10.5

11 11.5

12 12.5

V1 Voltage [V]

13 13.5

14 14.5

15

4-time voltage multiplication

Reference value of V1-V5 rise stabilization time in ML9059E COG mounting

Conditions :VIN=4.5V, 4-time multiplication, Tj=-40

C to +85C

Voltage multiplier capacitor C1=3.3

F, smoothing capacitor C2=1F

300

Parameter: trace resistance external to COG-mounted chip

250

R=100

R=200

200

150

100

50

0

10 10.5

11 11.5

12 12.5

V1 Voltage [V]

13 13.5

14 14.5

15

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LAPIS Semiconductor

REVISION HISTORY

Document No.

FEDL9059E-01

Date

April. 13, 2007

Page

Previous

Edition

Current

Edition

– – Final edition 1

Description

FEDL9059E-01

ML9059E

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FEDL9059E-01

ML9059E

LAPIS Semiconductor

NOTICE

No copying or reproduction of this document, in part or in whole, is permitted without the consent of LAPIS

Semiconductor Co., Ltd.

The content specified herein is subject to change for improvement without notice.

The content specified herein is for the purpose of introducing LAPIS Semiconductor's products (hereinafter

"Products"). If you wish to use any such Product, please be sure to refer to the specifications, which can be obtained from LAPIS Semiconductor upon request.

Examples of application circuits, circuit constants and any other information contained herein illustrate the standard usage and operations of the Products. The peripheral conditions must be taken into account when designing circuits for mass production.

Great care was taken in ensuring the accuracy of the information specified in this document. However, should you incur any damage arising from any inaccuracy or misprint of such information, LAPIS Semiconductor shall bear no responsibility for such damage.

The technical information specified herein is intended only to show the typical functions of and examples of application circuits for the Products. LAPIS Semiconductor does not grant you, explicitly or implicitly, any license to use or exercise intellectual property or other rights held by LAPIS Semiconductor and other parties.

LAPIS Semiconductor shall bear no responsibility whatsoever for any dispute arising from the use of such technical information.

The Products specified in this document are intended to be used with general-use electronic equipment or devices (such as audio visual equipment, office-automation equipment, communication devices, electronic appliances and amusement devices).

The Products specified in this document are not designed to be radiation tolerant.

While LAPIS Semiconductor always makes efforts to enhance the quality and reliability of its Products, a

Product may fail or malfunction for a variety of reasons.

Please be sure to implement in your equipment using the Products safety measures to guard against the possibility of physical injury, fire or any other damage caused in the event of the failure of any Product, such as derating, redundancy, fire control and fail-safe designs. LAPIS Semiconductor shall bear no responsibility whatsoever for your use of any Product outside of the prescribed scope or not in accordance with the instruction manual.

The Products are not designed or manufactured to be used with any equipment, device or system which requires an extremely high level of reliability the failure or malfunction of which may result in a direct threat to human life or create a risk of human injury (such as a medical instrument, transportation equipment, aerospace machinery, nuclear-reactor controller, fuel-controller or other safety device). LAPIS Semiconductor shall bear no responsibility in any way for use of any of the Products for the above special purposes. If a Product is intended to be used for any such special purpose, please contact a ROHM sales representative before purchasing.

If you intend to export or ship overseas any Product or technology specified herein that may be controlled under the Foreign Exchange and the Foreign Trade Law, you will be required to obtain a license or permit under the

Law.

Copyright 2007 - 2011 LAPIS Semiconductor Co., Ltd

.

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