Download datasheet for MR26T51203L by LAPIS Semiconductor

Download datasheet for MR26T51203L by LAPIS Semiconductor
FEDR26T51203L-002-02
Issue Date: Oct. 01, 2008
MR26T51203L
32M–Word × 16–Bit or 64M–Word × 8–Bit
P2ROM
FEATURES
· 33,554,432-word × 16-bit/67,108,864-word × 8-bit
electrically switchable configuration
· Access time
2.7 V to 3.6 V power supply.........120 ns MAX
3.0 V to 3.6 V power supply.........100 ns MAX
· Operating current ..........................35 mA MAX(5MHz)
· Standby current .............................10 µA MAX
· Input/Output TTL compatible
· Three-state output
PACKAGES
· MR26T51203L-xxxTM
50-pin plastic TSOP (P-TSOP(2)50- 400-0.80-K-MC)
P2ROM ADVANCED TECHNOLOGY
PIN CONFIGURATION (TOP VIEW)
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A23
GND
BYTE#
A0
D0
D8
D1
D9
Vcc
D2
D10
D3
D11
GND
1
50 CE#
2
49 A12
3
48 A13
4
47 A14
5
46 A15
6
45 Vcc
7
44 A16
8
43 A17
9
42 A18
10
41 A19
40 A20
11
12
13
14
50TSOP
(Type2)
39 A21
38 GND
37 A22
15
36 A24
16
35 OE#
17
34 D15/A-1
18
33 D7
19
32 D14
20
31 D6
21
30 D13
22
29 D5
23
28 D12
24
27 D4
25
26 Vcc
P2ROM stands for Production Programmed ROM. This
exclusive LAPIS Semiconductor technology utilizes factory
test equipment for programming the customers code into the
P2ROM prior to final production testing.
Advancements in this technology allows production costs to be
equivalent to MASKROM and has many advantages and added
benefits over the other non-volatile technologies, which
include the following;
· Short lead time, since the P2ROM is programmed at the final stage of the production process, a large P2ROM
inventory "bank system" of un-programmed packaged products are maintained to provide an aggressive
lead-time and minimize liability as a custom product.
· No mask charge, since P2ROMs do not utilize a custom mask for storing customer code, no mask charges
apply.
· No additional programming charge, unlike Flash and OTP that require additional programming and handling
costs, the P2ROM already has the code loaded at the factory with minimal effect on the production throughput.
The cost is included in the unit price.
· Custom Marking is available at no additional charge.
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FEDR26T51203L-002-02
MR26T51203L / P2ROM
BLOCK DIAGRAM
A–1
OE#
CE
OE
Row Decoder
CE#
BYTE#
Memory Cell Matrix
32M × 16-Bit or 64M × 8-Bit
Column Decoder
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
Address Buffer
× 8/× 16 Switch
Multiplexer
Output Buffer
D0
D2
D1
D4
D3
D6
D5
D8
D7
D10
D9
D12
D11
D14
D13
D15
In 8-bit output mode, these pins
are placed in a high-Z state and
pin D15 functions as the A-1
address pin.
PIN DESCRIPTIONS
Pin name
D15 / A–1
A0 to A24
D0 to D14
CE#
OE#
BYTE#
VCC
VSS
Functions
Data output / Address input
Address inputs
Data outputs
Chip enable input
Output enable input
Word / Byte select input
Power supply voltage
Ground
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FEDR26T51203L-002-02
MR26T51203L / P2ROM
FUNCTION TABLE
Mode
Read (16-Bit)
Read (8-Bit)
CE#
L
L
OE#
L
L
Output disable
L
H
Standby
H
∗
BYTE#
H
L
H
L
H
L
VCC
2.7 V
to
3.6 V
D0 to D7
DOUT
D8 to D14
DOUT
Hi–Z
Hi–Z
Hi–Z
D15/A–1
L/H
∗
∗
∗: Don’t Care (H or L)
ABSOLUTE MAXIMUM RATINGS
Parameter
Operating temperature under bias
Storage temperature
Input voltage
Output voltage
Power supply voltage
Power dissipation per package
Output short circuit current
Symbol
Ta
Tstg
VI
VO
VCC
PD
IOS
Condition
—
Relative to VSS
Ta = 25°C
—
Value
0 to 70
–55 to 125
–0.5 to VCC+0.5
–0.5 to VCC+0.5
–0.5 to 5
1.0
10
Unit
°C
°C
V
V
V
W
mA
RECOMMENDED OPERATING CONDITIONS
Parameter
VCC power supply voltage
Input “H” level
Input “L” level
Symbol
VCC
VIH
VIL
Condition
VCC = 2.7 to 3.6 V
Min.
2.7
2.2
–0.5∗∗
Typ.
—
—
—
(Ta = 0 to 70°C)
Max.
Unit
3.6
V
VCC+0.5∗
V
0.6
V
Voltage is relative to VSS.
∗ : Vcc+1.5V(Max.) when pulse width of overshoot is less than 10ns.
∗∗ : -1.5V(Min.) when pulse width of undershoot is less than 10ns.
PIN CAPACITANCE
Parameter
Input
BYTE#
Output
Symbol
CIN1
CIN2
COUT
Condition
VI = 0 V
VO = 0 V
Min.
—
—
—
(VCC = 3.0 V, Ta = 25°C, f = 1 MHz)
Typ.
Max.
Unit
—
16
pF
—
200
—
20
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FEDR26T51203L-002-02
MR26T51203L / P2ROM
ELECTRICAL CHARACTERISTICS
DC Characteristics
Parameter
Input leakage current
Output leakage current
VCC power supply current
(Standby)
VCC power supply current
(Read)
Input “H” level
Input “L” level
Output “H” level
Output “L” level
Symbol
ILI
ILO
ICCSC
ICCST
ICCA
VIH
VIL
VOH
VOL
Condition
VI = 0 to VCC
VO = 0 to VCC
CE# = VCC
CE# = VIH
CE# = VIL, OE# = VIH
f=5MHz
—
—
IOH = –1 mA
IOL = 2 mA
Min.
—
—
—
—
2.2
–0.5∗∗
2.4
—
(VCC = 2.7 to 3.6 V, Ta = 0 to 70°C)
Typ.
Max.
Unit
—
5
µA
—
5
µA
—
10
µA
—
1
mA
—
—
—
—
35
mA
VCC+0.5∗
0.6
—
0.4
V
V
V
V
Voltage is relative to VSS.
∗ : Vcc+1.5 V(Max.) when pulse width of overshoot is less than 10 ns.
∗∗ : –1.5 V(Min.) when pulse width of undershoot is less than 10 ns.
AC Characteristics
Parameter
(VCC = 2.7 to 3.6 V, Ta = 0 to 70°C)
Min.
Max.
Unit
100∗
—
ns
120∗∗
Symbol
Condition
tC
—
Address access time
tACC
CE# = OE# = VIL
—
CE# access time
tCE
OE# = VIL
—
OE# access time
tOE
tCHZ
tOHZ
tOH
CE# = VIL
OE# = VIL
CE# = VIL
CE# = OE# = VIL
—
0
0
0
Address cycle time
Output disable time
Output hold time
100∗
120∗∗
100∗
120∗∗
30
20
20
—
ns
ns
ns
ns
ns
ns
∗ : Vcc=3.0 to 3.6V
∗∗ : Vcc=2.7 to 3.6V
Measurement conditions
Input signal level ....................................... 0 V/Vcc
Input timing reference level....................... 1/2Vcc
Output load ............................................... 50 pF
Output timing reference level .................... 1/2Vcc
Output load
Output
50 pF
(Including scope and jig)
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FEDR26T51203L-002-02
MR26T51203L / P2ROM
TIMING CHART (READ CYCLE)
16-Bit Read Mode (BYTE# = VIH)
tC
tC
A0 to A24
tOH
tACC
tCE
CE#
tOE
tCHZ
tOH
OE#
tOHZ
tACC
D0 to D15
Valid Data
Hi-Z
Valid Data
Hi-Z
8-Bit Read Mode (BYTE# = VIL)
tC
tC
A-1 to A24
tACC
tCE
tOH
CE#
tOE
tCHZ
tOH
OE#
tOHZ
tACC
D0 to D7
Hi-Z
Valid Data
Valid Data
Hi-Z
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FEDR26T51203L-002-02
MR26T51203L / P2ROM
PACKAGE DIMENSIONS
(Unit: mm)
Notes for Mounting the Surface Mount Type Package
The surface mount type packages are very susceptible to heat in reflow mounting and humidity absorbed in storage.
Therefore, before you perform reflow mounting, contact ROHM s responsible sales person for the product name,
package name, pin number, package code and desired mounting conditions (reflow method, temperature and
times).
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FEDR26T51203L-002-02
MR26T51203L / P2ROM
REVISION HISTORY
Page
Document
No.
Date
Previous
Edition
Current
Edition
FEDR26T51203L-02-01
Oct. 30, 2007
–
–
4
4
–
–
FEDR26T51203L-002-02
Oct. 01, 2008
Description
Final edition 1
Changed Input signal level from “0V/3V” to
“0V/Vcc”.
Changed company logo and name to OKI
SEMICONDUCTOR
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FEDR26T51203L-002-02
MR26T51203L / P2ROM
NOTICE
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Examples of application circuits, circuit constants and any other information contained herein illustrate the
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Great care was taken in ensuring the accuracy of the information specified in this document. However, should
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The technical information specified herein is intended only to show the typical functions of and examples of
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Copyright 2008 - 2011 LAPIS Semiconductor Co., Ltd.
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