Download datasheet for MR27V1652L by LAPIS Semiconductor

Download datasheet for MR27V1652L by LAPIS Semiconductor
FEDR27V1652L-002-03
Issue Date:Jan.06, 2009
MR27V1652L
1M–Word × 16–Bit or 2M–Word × 8–Bit Page Mode
P2ROM
FEATURES
PIN CONFIGURATION (TOP VIEW)
· 1,048,576-word × 16-bit / 2,097,152-word × 8-bit
electrically switchable configuration
· Page size of 8-word x 16-Bit or 16-word x 8-Bit
· 3.0 V to 3.6 V power supply
· Random Access time........... 80 ns MAX
· Page Access time ................ 25 ns MAX
· Operating current ................ 60 mA MAX (5MHz)
· Standby current ................... 10 µA MAX
· Input/Output TTL compatible
· Three-state output
PACKAGES
· MR27V1652L-xxxMA
44-pin plastic SOP (SOP44-P-600-1.27-K)
· MR27V1652L-xxxTN
48-pin plastic TSOP (TSOP I 48-P-1220-0.50-1K)
NC 1
A18 2
A17 3
A7 4
A6 5
A5 6
A4 7
A3 8
A2 9
A1 10
A0 11
CE# 12
44 NC
VSS
OE#
D0
D8
D1
D9
D2
D10
D3
D11
13
32 VSS
14
31 D15/A–1
15
30 D7
16
29 D14
17
28 D6
18
27 D13
19
26 D5
20
25 D12
21
24 D4
22
23 VCC
43 A19
42 A8
41 A9
40 A10
39 A11
38 A12
37 A13
36 A14
35 A15
34 A16
33 BYTE#
44SOP
P2ROM ADVANCED TECHNOLOGY
P2ROM stands for Production Programmed ROM. This
exclusive LAPIS Semiconductor technology utilizes factory
test equipment for programming the customers code into the
P2ROM prior to final production testing.
Advancements in this technology allows production costs to be
equivalent to MASKROM and has many advantages and added
benefits over the other non-volatile technologies, which
include the following;
· Short lead time, since the P2ROM is programmed at the
final stage of the production process, a large P2ROM
inventory "bank system" of un-programmed packaged
products are maintained to provide an aggressive lead-time
and minimize liability as a custom product.
· No mask charge, since P2ROMs do not utilize a custom
mask for storing customer code, no mask charges apply.
· No additional programming charge, unlike Flash and
OTP that require additional programming and handling
costs, the P2ROM already has the code loaded at the factory
with minimal effect on the production throughput. The cost
is included in the unit price.
· Custom Marking is available at no additional charge.
· Pin Compatible with Mask ROM and some FLASH
products.
A15
A14
A13
A12
A11
A10
A9
A8
A19
NC
NC
NC
NC
NC
NC
A18
A17
A7
A6
A5
A4
A3
A2
A1
1
48 A16
2
47 BYTE#
3
46 VSS
4
45 D15/A–1
5
44 D7
6
43 D14
7
42 D6
8
41 D13
9
40 D5
10
39 D12
11
38 D4
12
37 VCC
13
36 D11
14
35 D3
15
34 D10
16
33 D2
17
32 D9
18
31 D1
19
30 D8
20
29 D0
21
28 OE#
22
27 VSS
23
26 CE#
24
25 A0
48TSOP(Type-I)
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FEDR27V1652L-002-03
MR27V1652L / P2ROM
BLOCK DIAGRAM
A–1
OE#
CE
OE
BYTE#
Row Decoder
CE#
Memory Cell Matrix
1M × 16-Bit or 2M × 8-Bit
Column Decoder
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
Address Buffer
× 8/× 16 Switch
Multiplexer
Output Buffer
D0
D2
D1
D4
D3
D6
D5
D8
D7
D10
D9
D12
D11
D14
D13
D15
In 8-bit output mode, these pins
are placed in a high-Z state and
pin D15 functions as the A-1
address pin.
PIN DESCRIPTIONS
Pin name
Functions
D15 / A–1
Data output / Address input
A0 to A19
Address inputs
D0 to D14
Data outputs
CE#
Chip enable input
OE#
Output enable input
BYTE#
Word / Byte select input
VCC
Power supply voltage
VSS
Ground
NC
No connect
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FEDR27V1652L-002-03
MR27V1652L / P2ROM
FUNCTION TABLE
Mode
Read (16-Bit)
Read (8-Bit)
CE#
L
L
OE#
L
L
Output disable
L
H
Standby
H
∗
BYTE#
H
L
H
L
H
L
VCC
D0 to D7
D8 to D14
DOUT
Hi–Z
DOUT
3.3 V
Hi–Z
D15/A–1
L/H
∗
Hi–Z
∗
∗: Don’t Care (H or L)
ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
Operating temperature under bias
Ta
Storage temperature
Condition
Value
Unit
0 to 70
°C
–55 to 125
°C
–0.5 to VCC+0.5
V
–0.5 to VCC+0.5
V
—
Tstg
Input voltage
VI
Output voltage
VO
Power supply voltage
VCC
–0.5 to 5
V
Power dissipation per package
PD
Ta = 25°C
1.0
W
Output short circuit current
IOS
—
10
mA
relative to VSS
RECOMMENDED OPERATING CONDITIONS
Parameter
Symbol
VCC power supply voltage
VCC
Input “H” level
VIH
Input “L” level
VIL
Condition
(Ta = 0 to 70°C)
Unit
Min.
Typ.
Max.
3.0
—
3.6
2.2
—
VCC+0.5∗
V
–0.5∗∗
—
0.6
V
VCC = 3.0 to 3.6 V
V
Voltage is relative to VSS.
∗ : Vcc+1.5V (Max.) when pulse width of overshoot is less than 10ns.
∗∗ : -1.5V (Min.) when pulse width of undershoot is less than 10ns.
PIN CAPACITANCE
Parameter
Symbol
Input
CIN1
BYTE#
CIN2
Output
COUT
Condition
VI = 0 V
VO = 0 V
Min.
(VCC = 3.3 V, Ta = 25°C, f = 1 MHz)
Typ.
Max.
Unit
—
—
10
—
—
120
—
—
10
pF
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FEDR27V1652L-002-03
MR27V1652L / P2ROM
ELECTRICAL CHARACTERISTICS
DC Characteristics
Parameter
(VCC = 3.0 V to 3.6 V, Ta = 0 to 70°C)
Min.
Typ.
Max.
Unit
Symbol
Condition
Input leakage current
ILI
VI = 0 to VCC
—
—
10
µA
Output leakage current
ILO
VO = 0 to VCC
—
—
10
µA
ICCSC
CE# = VCC
—
—
10
µA
ICCST
CE# = VIH
—
—
1
mA
—
—
60
mA
—
2.2
—
VCC+0.5∗
V
VCC power supply current
(Standby)
VCC power supply current
(Read)
ICCA
Input “H” level
VIH
CE#= VIL, OE# = VIH,
f = 5MHz
Input “L” level
VIL
—
–0.5∗∗
—
0.6
V
Output “H” level
VOH
IOH = –1 mA
2.4
—
—
V
Output “L” level
VOL
IOL = 2 mA
—
—
0.4
V
Voltage is relative to VSS.
∗ : Vcc+1.5V (Max.) when pulse width of overshoot is less than 10ns.
∗∗ : -1.5V (Min.) when pulse width of undershoot is less than 10ns.
AC Characteristics
Parameter
Symbol
Address cycle time
Address access time
Condition
(VCC = 3.0 V to 3.6 V, Ta = 0 to 70°C)
Min.
Max.
Unit
tC
—
80
—
ns
tACC
CE# = OE# = VIL
—
80
ns
Page cycle time
tPC
—
25
—
ns
Page access time
tPAC
—
—
25
ns
CE# access time
tCE
OE# = VIL
—
80
ns
OE# access time
Output disable time
Output hold time
tOE
CE# = VIL
—
25
ns
tCHZ
OE# = VIL
0
20
ns
tOHZ
CE# = VIL
0
20
ns
tOH
CE# = OE# = VIL
0
—
ns
Measurement conditions
Input signal level ................................... 0 V/3 V
Input timing reference level................... 1/2Vcc
Output load ........................................... 50 pF
Output timing reference level ................ 1/2Vcc
Output load
Output
50 pF
(Including scope and jig)
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FEDR27V1652L-002-03
MR27V1652L / P2ROM
TIMING CHART (READ CYCLE)
RANDOM ACCESS MODE READ CYCLE
tC
tC
Address
tOH
tACC
tCE
CE#
tCHZ
tOE
tOH
OE#
tOHZ
tACC
Dout
Valid Data
Valid Data
Hi-Z
Hi-Z
PAGE ACCESS MODE READ CYCLE
tC
A3 to A19
tPC
tPC
A-1 to A2 (Byte mode)
A0 to A2 (Word mode)
tCE
tOH
CE#
tCHZ
tOE
OE#
tACC
Dout
Hi-Z
tPAC
tPAC
tOHZ
Hi-Z
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FEDR27V1652L-002-03
MR27V1652L / P2ROM
PACKAGE DIMENSIONS
(Unit: mm)
Notes for Mounting the Surface Mount Type Package
The surface mount type packages are very susceptible to heat in reflow mounting and humidity absorbed in
storage.
Therefore, before you perform reflow mounting, contact ROHM s responsible sales person for the product name,
package name, pin number, package code and desired mounting conditions (reflow method, temperature and
times).
6/9
FEDR27V1652L-002-03
MR27V1652L / P2ROM
(Unit: mm)
Notes for Mounting the Surface Mount Type Package
The surface mount type packages are very susceptible to heat in reflow mounting and humidity absorbed in
storage.
Therefore, before you perform reflow mounting, contact ROHM s responsible sales person for the product name,
package name, pin number, package code and desired mounting conditions (reflow method, temperature and
times).
7/9
FEDR27V1652L-002-03
MR27V1652L / P2ROM
REVISION HISTORY
Document
Page
Date
Previous
Edition
Current
Edition
FEDR27V1652L-02-01
Jun. 16, 2005
–
–
FEDR27V1652L-02-02
Feb. 2, 2006
1
1, 7
Added package 48TSOP(Type-I)
1, 4
1, 4
Change tC, tACC, tCE to 80ns
Change tPC, tPAC, tOE to 25ns
–
–
No.
FEDR27V1652L-002-03
Jan.6, 2009
Description
Final edition 1
Changed company logo and name
to OKI SEMICONDUCTOR
8/9
FEDR27V1652L-002-03
MR27V1652L / P2ROM
NOTICE
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The content specified herein is subject to change for improvement without notice.
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"Products"). If you wish to use any such Product, please be sure to refer to the specifications, which can be
obtained from LAPIS Semiconductor upon request.
Examples of application circuits, circuit constants and any other information contained herein illustrate the
standard usage and operations of the Products. The peripheral conditions must be taken into account when
designing circuits for mass production.
Great care was taken in ensuring the accuracy of the information specified in this document. However, should
you incur any damage arising from any inaccuracy or misprint of such information, LAPIS Semiconductor shall
bear no responsibility for such damage.
The technical information specified herein is intended only to show the typical functions of and examples of
application circuits for the Products. LAPIS Semiconductor does not grant you, explicitly or implicitly, any
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The Products specified in this document are intended to be used with general-use electronic equipment or devices
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While LAPIS Semiconductor always makes efforts to enhance the quality and reliability of its Products, a
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Please be sure to implement in your equipment using the Products safety measures to guard against the
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The Products are not designed or manufactured to be used with any equipment, device or system which requires
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Copyright 2009 - 2011 LAPIS Semiconductor Co., Ltd.
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