Download datasheet for MR36V01G52B by LAPIS Semiconductor

Download datasheet for MR36V01G52B by LAPIS Semiconductor
FEDR36V01G52B-002-01
Issue Date: Nov. 18, 2009
MR36V01G52B
64M–Word × 16–Bit or 128M–Word × 8–Bit Page Mode
P2ROM
FEATURES
PIN CONFIGURATION (TOP VIEW)
64Mx16 or 128Mx8-bit
electrically switchable configuration
· Page size of 8-word x 16-Bit or 16-word x 8-Bit
· 3.0 V to 3.6V power supply
·Random Access time
110 ns MAX
·Page Access time
25 ns MAX
· Operating current
50 mA MAX
· Standby current
25 mA MAX
· Input/Output TTL compatible
· Three-state output
PACKAGES
·56-pin plastic TSOP (TSOP(1)56-P-1420-0.50-K-MC)
P2ROM ADVANCED TECHNOLOGY
P2ROM stands for Production Programmed ROM. This
exclusive LAPIS Semiconductor technology utilizes factory
test equipment for programming the customers code into the
P2ROM prior to final production testing. Advancements in this
technology allows production costs to be equivalent to
MASKROM and has many advantages and added benefits over
the other non-volatile technologies, which include the
following;
A23
A22
A15
A14
A13
A12
A11
A10
A9
A8
A19
A20
NC
NC
A21
NC
NC
A18
A17
A7
A6
A5
A4
A3
A2
A1
NC
NC
1
2
3
56
55
54
4
53
5
52
6
51
7
50
8
49
9
10
11
12
56
TSOP
(type1)
48
47
46
45
13
44
14
43
15
42
16
41
17
40
18
39
19
38
20
37
21
36
22
35
23
34
24
33
25
26
32
31
27
28
30
29
A24
A25
A16
BYTE#
Vss
D15/A-1
D7
D14
D6
D13
D5
D12
D4
Vcc
D11
D3
D10
D2
D9
D1
D8
D0
OE#
Vss
CE#
A0
NC
Vcc
· Short lead time, since the P2ROM is programmed at the final stage of the production process, a large P2ROM
inventory "bank system" of un-programmed packaged products are maintained to provide an aggressive lead-time
and minimize liability as a custom product.
· No mask charge, since P2ROMs do not utilize a custom mask for storing customer code, no mask charges apply.
· No additional programming charge, unlike Flash and OTP that require additional programming and handling
costs, the P2ROM already has the code loaded at the factory with minimal effect on the production throughput.
The cost is included in the unit price.
· Custom Marking is available at no additional charge.
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FEDR36V01G52B-002-01
MR36V01G52B / P2ROM
BLOCK DIAGRAM
A-1
× 8/× 16 Switch
CE
OE
Row Decoder
OE#
BYTE#
Memory Cell Matrix
32M × 16-Bit or 64M × 8-Bit
Column Decoder
Address Buffe
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
CE#
Multiplexer & Sense Amp.
Output Buffer
D0
D2
D1
D4
D3
D6
D5
D8
D7
D10
D9
D12
D11
D14
D13
D15
In 8-bit output mode, these pins
are placed in a high-Z state and
pin D15 functions as the A-1
address pin.
PIN DESCRIPTIONS
Pin name
Functions
D15 / A–1
Data output / Address input
A0 to A25
Address inputs
D0 to D14
Data outputs
CE#
Chip enable input
OE#
Output enable input
BYTE#
Word / Byte select input
VCC
Power supply voltage
VSS
Ground
NC
No connect
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FEDR36V01G52B-002-01
MR36V01G52B / P2ROM
FUNCTION TABLE
Mode
CE#
OE#
BYTE#
Read (16-Bit)
L
L
H
Read (8-Bit)
L
L
L
Output disable
L
H
Standby
H
∗
VCC
D0 to D7
D8 to D15
A-1
DOUT
DOUT
H
3.3 V
L
H
L
∗
Hi–Z
L/H
Hi–Z
∗
Hi–Z
∗
∗: Don’t Care (H or L)
ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
Operating temperature under bias
Ta
Storage temperature
Condition
Value
Unit
0 to 70
°C
–55 to 125
°C
–0.5 to VCC+0.5
V
–0.5 to VCC+0.5
V
—
Tstg
Input voltage
VI
Output voltage
VO
Power supply voltage
VCC
–0.5 to 5
V
Output short circuit current
Ios
—
10
mA
Power dissipation per package
PD
Ta=25°C
1.0
W
relative to VSS
RECOMMENDED OPERATING CONDITIONS
(Ta = 0 to 70°C)
Parameter
Symbol
VCC power supply voltage
VCC
Input “H” level
VIH
Input “L” level
VIL
Condition
Min.
Typ.
Max.
Unit
3.0
—
3.6
V
2.2
—
VCC+0.5∗
V
–0.5∗∗
—
0.6
V
VCC = 3.0 to 3.6 V
Voltage is relative to VSS.
∗ : Vcc+1.5V(Max.) when pulse width of overshoot is less than 10ns.
∗∗ : -1.5V(Min.) when pulse width of undershoot is less than 10ns.
PIN CAPACITANCE
(VCC = 3.3 V, Ta = 25°C, f = 1 MHz)
Parameter
Symbol
Input(except BYTE#)
CIN1
Output
Cout
Condition
VI = 0 V
Min.
Typ.
Max.
—
—
20
—
—
20
Unit
pF
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FEDR36V01G52B-002-01
MR36V01G52B / P2ROM
ELECTRICAL CHARACTERISTICS
DC CHARACTERISTICS
(VCC = 3.3 V ± 0.3 V, Ta = 0 to 70°C)
Parameter
Input leakage current
Output leakage current
Symbol
Condition
Min.
Typ.
Max.
Unit
ILI
VI = 0 to VCC
—
—
20
µA
ILO
VO = 0 to VCC
—
—
20
µA
VCC power supply current
ICCSC
CE# = Add.=VCC
—
—
25
mA
(Standby)
ICCST
CE# = Add.=VIH
—
—
25
mA
—
—
50
mA
VCC power supply current
(Read)
ICCA1
CE# = VIL
OE# = VIH
tc = 200 ns
Input “H” level
VIH
—
2.2
—
VCC+0.5∗
V
Input “L” level
VIL
—
–0.5∗∗
—
0.6
V
Output “H” level
VOH
IOH = –2 mA
2.4
—
—
V
Output “L” level
VOL
IOL = 2 mA
—
—
0.4
V
Voltage is relative to VSS.
∗ : Vcc+1.5V(Max.) when pulse width of overshoot is less than 10ns.
∗∗ : -1.5V(Min.) when pulse width of undershoot is less than 10ns.
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FEDR36V01G52B-002-01
MR36V01G52B / P2ROM
AC CHARACTERISTICS
(VCC = 3.3 V ± 0.15 V, Ta = 0 to 40°C)
Parameter
Symbol
Condition
Min.
Max.
Unit
tC
—
100
—
ns
Address access time
tACC
—
—
100
ns
Address skew time
tASK
—
—
10
ns
CE Address skew time
TCSK
—
—
10
ns
Address cycle time
Page cycle time
tPC
—
25
—
ns
Page access time
tPAC
CE# = OE# = VIL
—
25
ns
CE# access time
tCE
OE# = VIL
—
100
ns
OE# access time
tOE
CE# = VIL
—
25
ns
tCHZ
OE# = VIL
0
20
ns
Output disable time
Output hold time
tOHZ
CE# = VIL
0
20
ns
tOH
CE# = OE# = VIL
0
—
ns
(VCC = 3.3 V ± 0.3 V, Ta = 0 to 70°C)
Parameter
Address cycle time
Symbol
Condition
Min.
Max.
Unit
tC
—
110
—
ns
Address access time
tACC
—
—
110
ns
Address skew time
tASK
—
—
10
ns
CE Address skew time
TCSK
—
—
10
ns
Page cycle time
tPC
—
25
—
ns
Page access time
tPAC
CE# = OE# = VIL
—
25
ns
CE# access time
tCE
OE# = VIL
—
110
ns
OE# access time
tOE
CE# = VIL
—
25
ns
Output disable time
Output hold time
tCHZ
OE# = VIL
0
20
ns
tOHZ
CE# = VIL
0
20
ns
tOH
CE# = OE# = VIL
0
—
ns
Measurement conditions
Input signal level-------------------------------- 0 V/3 V
Input timing reference level ------------------ 1/2Vcc
Output load -------------------------------------- 30 pF
Output timing reference level---------------- 1/2Vcc
Output load
Output
30 pF
(Including scope and jig)
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FEDR36V01G52B-002-01
MR36V01G52B / P2ROM
TIMING CHART (READ CYCLE)
Random Access Mode Read Cycle
tC
tC
Address
tOH
ASK
tCE
tACC
CE#
tCHZ
tOE
tOH
OE#
tOHZ
tACC
Dout
Valid Data
Valid Data
Hi-Z
Hi-Z
Page Access Mode Read Cycle
tC
A3 to A25
tPC
tPC
A-1 to A2 (X16 mode)
A0 to A2 (X32 mode)
tCE
tOH
CE#
tOE
CSK
tCHZ
OE#
tACC
tPAC
tPAC
tOHZ
Dout
Hi-Z
Hi-Z
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FEDR36V01G52B-002-01
MR36V01G52B / P2ROM
POWER ON CHARACTERISTICS
(VCC = 3.3 V ± 0.3 V, Ta = 0 to 70°C)
Parameter
Symbol
Condition
Min.
Max.
Unit
VCC set up time
tvset
—
5
270
us
Power on sequence hold time
tposh
—
1
—
ms
Power off hold time
tvpoff
—
1
—
ms
TIMING CHART (POWER ON)
Unavailable
Don’t power-on
tvpoff
VCC
LEVEL = 3.0 V
tposh
LEVEL=VSS
VCC
0.1V
tvset
Note: A start-up delay of 1ms is required after power-on.
If you power-off VCC ,you must wait 1ms to power-on.
CE# must be HIGH while VCC power on sequence.
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FEDR36V01G52B-002-01
MR36V01G52B / P2ROM
PACKAGE DIMENSIONS
(Unit: mm)
Notes for Mounting the Surface Mount Type Package
The surface mount type packages are very susceptible to heat in reflow mounting and humidity absorbed in
storage.
Therefore, before you perform reflow mounting, contact ROHM’s responsible sales person for the product name,
package name, pin number, package code and desired mounting conditions (reflow method, temperature and
times).
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FEDR36V01G52B-002-01
MR36V01G52B / P2ROM
REVISION HISTORY
Page
Document
No.
Date
FEDR36V01G52B-002-01
Nov. 18,2009
Previous
Edition
Current
Edition
–
–
Description
Final edition 1
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FEDR36V01G52B-002-01
MR36V01G52B / P2ROM
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