Download datasheet for LTC3766 by Linear Technology

Download datasheet for LTC3766 by Linear Technology
LTC3766
High Efficiency,
Secondary-Side Synchronous
Forward Controller
DESCRIPTION
FEATURES
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Direct Flux Limit™ Guarantees No Saturation
Fast and Accurate Average Current Limit
Clean Start-Up Into Pre-Biased Output
Secondary-Side Control for Fast Transient Response
Simple, Self-Starting Architecture
Synchronous MOSFET Reverse Current Limit
PolyPhase® Operation Eases High-Power Design
True Remote Sense Differential Amplifier
Remote Sense Reverse Protection
High Voltage Linear Regulator Controller
Internal LDO Powers Gate Drive from VOUT
Overtemperature/Overvoltage Protection
Low Profile 4mm × 5mm QFN and Narrow 28-Lead
SSOP Packages
APPLICATIONS
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The LTC®3766 is a PolyPhase-capable secondary-side
controller for synchronous forward converters. When used
in conjunction with the LTC3765 active-clamp forward
controller and gate driver, the part creates a complete
isolated power supply that combines the power of multiphase operation with the speed of secondary-side control.
The LTC3766 has been designed to simplify the design of
active clamp forward converters. Working in concert with
the LTC3765, the LTC3766 forms a robust, self-starting
converter that eliminates the need for the separate bias
regulator that is commonly used in secondary-side control
applications. A precision current-limit coupled with clean
start-up into a pre-biased load make the LTC3766 an excellent choice for high-power battery charger applications.
The LTC3766 provides extensive remote sensing and output
protection features, while Direct Flux Limit guarantees no
transformer saturation without compromising transient
response. A linear regulator controller and internal bypass
LDO are also provided to simplify the generation of the
secondary-side bias voltage.
Isolated 48V Telecommunication Systems
Isolated Battery Chargers
Automotive and Military Systems
Industrial, Avionics and Heavy Equipment
L, LT, LTC, LTM, PolyPhase, Linear Technology and the Linear logo are registered and Direct
Flux Limit is a trademark of Linear Technology Corporation. All other trademarks are the
property of their respective owners. Protected by U.S. Patents, including 7200014 and 6144194.
Other patents pending.
TYPICAL APPLICATION
36V-72V to 5V/15A Active Clamp Isolated Forward Converter
+VIN
36V TO 72V
•
6:2
1.4µH
+VOUT
5V
15A
•
EFFICIENCY: 94% AT 48VIN/15AOUT
2.2µF
100V
×3
FDMS86201
15mΩ
0.5W
BSC0901NS
100nF
200V
33nF
200V
220µF
6.3V
×2
SiR414DP
3mΩ
2W
168Ω
–VIN
–VOUT
Si3440DV
Si3437DV
(SOT23)
200k
2.2nF
250VAC
FG SW SG RUN VIN NDRV VCC FS/SYNC VS+ VS–
1Ω
365k
NDRV PG
IS+ IS–
15.0k
LTC3765
SSFLT
RCORE
33nF
AG
ISMAG
0.1µF
IN+
RUN
VCC
4.7µF
IS–
10.5k
DELAY
14k
1.0µF
•
IN–
2:1
•
IS+
LTC3766
PT+
ITH
PT–
SS
FS/UV
SGND PGND
GND
18.2k
33nF
4.42k
FB
PGND
IPK
SGD
26.1k
15k
FGD
470pF
MODE
22.1k
604Ω
47pF
17.8k
3766 TA01
3766f
1
LTC3766
ABSOLUTE MAXIMUM RATINGS
(Note 1)
VCC Voltage .................................................–0.3V to 12V
VIN Voltage ................................................. –0.3V to 33V
RUN Voltage............................................... –0.3V to 33V
SW
Low Impedance Source ............................ –5V to 40V
Current Fed .......... 2mA DC or 0.2A for <1μs Into Pin*
VAUX, VS+, VS –, VSOUT, NDRV Voltages ...... –0.3V to 16V
ITH, IS+, REGSD Voltages ............................ –0.3V to 6V
PHASE Voltage............................................. –0.3V to 6V
IS –, SGD, FGD Voltages ...............................–0.3V to 12V
FS/SYNC, FB, MODE Voltages .....................–0.3V to 12V
VSEC Voltage ................................................ –0.3V to 3V
IPK, SS Voltages ........................................... –0.3V to 4V
Operating Junction Temperature Range (Notes 2,3)
LTC3766E, LTC3766I ......................... –40°C to 125°C
LTC3766H .......................................... –40°C to 150°C
LTC3766MP ....................................... –55°C to 150°C
Storage Temperature Range .................. –65°C to 150°C
Lead Temperature (Soldering, 10 sec )
GN Package ..................................................... 300°C
*The LTC3766 contains an internal 50V clamp that limits the voltage on the
SW pin.
PIN CONFIGURATION
TOP VIEW
26 PT+
MODE
4
25
PT–
PHASE
5
24 VAUX
FB
6
23 SW
ITH
7
22 VIN
RUN
8
21 NDRV
SS 6
SS
9
20 FGD
IPK 7
IPK 10
19 SGD
VSOUT 8
GND 14
15 FS/SYNC
GN PACKAGE
28-LEAD NARROW PLASTIC SSOP
TJMAX = 125°C, θJA = 95°C/W
19 VIN
29
GND
RUN 5
18 NDRV
17 FGD
16 SGD
15 IS+
9 10 11 12 13 14
IS–
16 REGSD
20 SW
ITH 4
REGSD
VS– 13
21 VAUX
FB 3
FS/SYNC
17 IS–
PHASE 2
GND
VS+ 12
22 PT–
VS–
18 IS+
28 27 26 25 24 23
MODE 1
VS+
VSOUT 11
PT+
27 PGND
3
PGND
2
VCC
FG
VSEC
SG
28 VCC
VSEC
1
FG
TOP VIEW
SG
UFD PACKAGE
28-LEAD (4mm × 5mm) PLASTIC QFN
TJMAX = 125°C, θJA = 43°C/W
EXPOSED PAD (PIN 29) IS GND, MUST BE SOLDERED TO PCB
3766f
2
LTC3766
ORDER INFORMATION
LEAD FREE FINISH
LTC3766EGN#PBF
LTC3766IGN#PBF
LTC3766HGN#PBF
LTC3766MPGN#PBF
LTC3766EUFD#PBF
TAPE AND REEL
LTC3766EGN#TRPBF
LTC3766IGN#TRPBF
LTC3766HGN#TRPBF
LTC3766MPGN#TRPBF
LTC3766EUFD#TRPBF
PART MARKING*
LTC3766GN
LTC3766GN
LTC3766GN
LTC3766GN
3766
PACKAGE DESCRIPTION
28-Lead Narrow Plastic SSOP
28-Lead Narrow Plastic SSOP
28-Lead Narrow Plastic SSOP
28-Lead Narrow Plastic SSOP
28-Lead (4mm × 5mm) Plastic QFN
LTC3766IUFD#PBF
LTC3766IUFD#TRPBF
3766
28-Lead (4mm × 5mm) Plastic QFN
TEMPERATURE RANGE
–40°C to 125°C
–40°C to 125°C
–40°C to 150°C
–55°C to 150°C
–40°C to 125°C
–40°C to 125°C
28-Lead (4mm × 5mm) Plastic QFN
–55°C to 150°C
28-Lead (4mm × 5mm) Plastic QFN
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
Consult LTC Marketing for information on non-standard lead based finish parts.
LTC3766HUFD#PBF
LTC3766HUFD#TRPBF
3766
LTC3766MPUFD#PBF
LTC3766MPUFD#TRPBF
3766
–40°C to 150°C
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the specified operating
junction temperature range, otherwise specifications are at TA = 25°C. (Note 2) VIN = 15V, GND = PGND = 0V, unless otherwise noted.
SYMBOL
PARAMETER
Main Control Loop
Regulated Feedback Voltage
VFB
Feedback Input Current
IFB
Feedback Voltage Line Regulation
ΔVFB(LINREG)
ΔVFB(LOADREG) Feedback Voltage Load Regulation
Average Current Sense Threshold
VISAVG
VISADJ
Current Sense Ripple Compensation
VISOC
Overcurrent Shutdown Threshold
ISIN
gm
REA
ISOFT(C)
ISOFT(D)
VRUNR
VRUNF
IRUN
tON(MIN)
DMAX
ΔVSEC(TH)
IS+ and IS– Input Current
Error Amplifier gm
Error Amplifier Output Resistance
Soft-Start Charge Current
Soft-Start Discharge Current
RUN Pin On Threshold
RUN Pin Off Threshold
RUN Pin Hysteresis Current
Minimum Controllable On Time
Maximum Duty Cycle
Volt-Second Limit Threshold Accuracy
RVSDN
VSWCL
ΔVFB(OV)
Volt-Second Discharge Resistance
SW Clamp Voltage
Output Overvoltage Threshold
CONDITIONS
(Note 4) ITH = 1.2V
(Note 4)
VIN = 5V to 32V, ITH = 1.2V
Measured in Servo Loop, ITH = 0.5V to 2V
Resistor Sense (RS) Mode
Current Transformer (CT) Mode
RS Mode
CT Mode
VSW = 10V, VS+ = 5V, FS/SYNC = VCC,
RIPK = 23.7k
RS Mode: VIS–= 0V
CT Mode: VIS– = VCC
l
MIN
TYP
MAX
UNITS
0.592
0.600
2
0.001
–0.01
55
0.73
10
140
0.608
50
V
nA
%/V
%
mV
V
mV
mV
100
1.33
280
2.7
5
5
3
1.22
1.17
3.0
200
79
113
1.44
500
3.2
l
47
0.66
86
1.22
2.2
(Note 7)
VSS = 2V
VSS = 2V
VRUN Rising
VRUN Falling
VRUN = 0.5V
FGD = SGD = GND
2V ≤ VSW < 5V
5V ≤ VSW ≤ 40V
ISW = 1mA
VFB Rising
4
l
l
1.18
1.13
2.2
77
–6
–4
43
15
75
51
17
–0.1
63
0.80
6
1.26
1.21
3.6
81
6
4
60
19
mV
V
nA
mS
MΩ
μA
μA
V
V
μA
ns
%
%
%
Ω
V
%
3766f
3
LTC3766
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the specified operating
junction temperature range, otherwise specifications are at TA = 25°C. (Note 2) VIN = 15V, GND = PGND = 0V, unless otherwise noted.
SYMBOL
PARAMETER
Drivers and Control
FG, SG Driver Pull-Up On-Resistance
FG, SG RUP
FG, SG RDOWN FG, SG Driver Pull-Down On-Resistance
PT+, PT– Driver Pull-Up Resistance
PT+, PT– RUP
+
–
PT ,PT RDOWN PT+, PT– Driver Pull-Down Resistance
FGD Delay
tFGD
tSGD
SGD Delay
VSW(REV)
SG Reverse Overcurrent SW Threshold
ISW(REV)
SG Reverse Overcurrent Adjust Current
VCC Supply
VCCOP
ICC
VUVLOR
VCC Operating Voltage Range
Supply Current
Normal Mode
Shutdown
UV Lockout Rising
VUVLOF
UV Lockout Falling
VREGSD
IREGSD(C)
IREGSD(D)
VAUX Supply
VAUXOP
VCCVAUX
REGSD Threshold Voltage
REGSD Charge Current
REGSD Discharge Current
VAUXLR
VAUXSWP
VCC Load Regulation
VAUX Switchover Voltage Rising
VAUXSWN
VAUX Switchover Voltage Falling
RAUX
RPSL
VIN Supply
VINOP
VINCL
ICLMAX
VCCVIN
VAUX Dropout Resistance
VAUX Pre-Switchover Load
IIN
Supply Current
Operating
Shutdown
VIN Undervoltage Lockout
VINUVLO
VAUX Operating Voltage Range
Regulated VCC Output Voltage
VIN Operating Voltage Range
VIN Clamp Voltage
VIN Clamp Current Limit
Regulated VCC Output Voltage
CONDITIONS
RFGD = 10kΩ
RFGD = 100kΩ
RSGD = 15kΩ
RSGD = 50kΩ
LV MODE
HV MODE
LV MODE
HV MODE
MIN
TYP
50
436
60
195
66
140
–86
–34.5
1.5
1.0
1.5
1.5
65
545
75
230
73
148
–103
–42
5
VFS/SYNC = VCC = 7V (Note 5)
VRUN = GND
VCC Rising, LV MODE
VCC Rising, HV MODE
VCC Falling, LV MODE
VCC Falling, HV MODE
VREGSD Rising
VREGSD = 0.7V
VREGSD = 0.7V
VAUX = 15V, LV MODE
VAUX = 15V, HV MODE
ICC = 0mA to 120mA, VAUX = 8V, LV MODE
VAUX Ramping Positive, LV MODE
VAUX Ramping Positive, HV MODE
VAUX Ramping Negative, LV MODE
VAUX Ramping Negative, HV MODE
ICC = 120mA, VAUX = 4.9V
VAUX = 4V
IVIN = 2mA, VRUN = GND
VIN = 33V, VRUN = GND
LV MODE (Note 6)
HV MODE (Note 6)
VFS/SYNC = VCC
VRUN = GND
VIN Rising
l
l
l
l
4.6
7.7
3.8
6.7
5
6.7
8.1
4.50
7.65
4.30
7.35
MAX
UNITS
80
654
90
265
79
156
–120
–49
Ω
Ω
Ω
Ω
ns
ns
ns
ns
mV
mV
µA
µA
10
5
210
4.7
7.9
3.9
6.9
1.21
13
3
7.0
8.5
0.8
4.70
8.00
4.50
7.70
1.7
920
5
28
3.8
6.7
8.1
30
5.5
7.2
8.5
2.6
900
450
3.2
4.8
8.1
4.0
7.1
V
mA
µA
V
V
V
V
V
μA
μA
15
7.3
8.9
2
4.88
8.35
4.70
8.05
2.5
V
V
V
%
V
V
V
V
Ω
Ω
32
32
7.2
7.3
8.9
V
V
mA
V
V
1200
µA
µA
V
3.8
3766f
4
LTC3766
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the specified operating
junction temperature range, otherwise specifications are at TA = 25°C. (Note 2) VIN = 15V, GND = PGND = 0V, unless otherwise noted.
SYMBOL
PARAMETER
Oscillator and Phase-Locked Loop
FS/SYNC Pin Sourcing Current
IFS/SYNC
Oscillator
High Frequency Set Point
fHIGH
Oscillator Resistor Set Accuracy
Δf (RFS/SYNC)
PLL Sync Frequency Range
fPLL(RANGE)
Differential Amplifier
Gain
ADA
Common Mode Rejection Ratio
CMRRDA
VS+ Input Resistance
RINP
VS– Input Resistance
RINM
Output Sourcing Current
IOH
Output High Fault Threshold
VIN-VOHST
CONDITIONS
MIN
VFS/SYNC = VCC
18.75kΩ < RFS/SYNC < 125kΩ
234
–12
100
1.5V ≤ VSOUT ≤ 15V, VIN = 20V
VIN = 20V
VIN = 20V
VIN = 20V
VIN = 20V, VS+ = 5V, VSOUT = 2.5V
VS+ Rising
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: The LTC3766E is guaranteed to meet specifications from 0°C
to 85°C with specifications over the –40°C to 125°C operating junction
temperature range assured by design, characterization and correlation with
statistical process controls. The LTC3766I is guaranteed over the –40°C to
125°C operating junction temperature range, the LTC3766H is guaranteed
over the –40°C to 150°C operating junction temperature range, and the
LTC3766MP is tested and guaranteed over the –55°C to 150°C operating
junction temperature range. High junction temperatures degrade operating
lifetimes; operating lifetime is derated for junction temperatures greater
than 125°C. Note that the maximum ambient temperature consistent with
these specifications is determined by specific operating conditions in
conjunction with board layout, the rated package thermal impedance and
other environmental factors.
l
0.99
l
0.8
TYP
20
275
1
75
120
160
3.0
1.2
MAX
UNITS
316
12
500
μA
kHz
%
kHz
1.01
1.5
V/V
dB
kΩ
kΩ
mA
V
Note 3: TJ is calculated from the ambient temperature, TA, and power
dissipation, PD, according to the following formula:
TJ = TA + (PD • θJA°C/W)
where θJA is 95°C/W for the SSOP and 43°C/W for the QFN package.
Note 4: The LTC3766 is tested in a feedback loop that servos VFB to a
voltage near the internal 0.6V reference voltage to obtain the specified ITH
voltage (VITH = 1.2V).
Note 5: Operating supply current is measured in test mode. Dynamic
supply current is higher due to the internal gate charge being delivered at
the switching frequency. See Typical Performance Characteristics.
Note 6: The VIN Regulator employs an external pass device to produce the
regulated VCC output voltage. The LTC3766 is tested using a 2N3904 NPN
transistor as an external pass device.
Note 7: Guaranteed by design.
3766f
5
LTC3766
TYPICAL PERFORMANCE CHARACTERISTICS
VCC Regulator Output Voltage
vs Temperature
9.0
13
8.5
Error Amplifier Transconductance
vs Temperature
2.90
VIN REGULATOR USING 2N3904
TRANSCONDUCTANCE (mS)
14
HV MODE
12
VCC VOLTAGE (V)
VCC SUPPLY CURRENT (mA)
VCC Supply Current
vs VCC Voltage
11
10
8.0
7.5
5
6
9
8
10
VCC INPUT VOLTAGE (V)
7
11
6.0
–55 –25
12
65
35
95
5
TEMPERATURE (°C)
125
102
2.5
0.745
55.5
99
1.315
98
65
35
95
5
TEMPERATURE (°C)
2.0
1.5
1.0
1.222
65
35
95
5
TEMPERATURE (°C)
125
155
53.5
0.720
–55 –25
1.214
Oscillator Frequency vs RFS
VRUN = 0.5V
500
3.00
2.95
2.90
2.85
155
3766 G07
2.80
–55 –25
53.0
155
125
600
FREQUENCY (kHz)
RUN CURRENT (µA)
1.216
65
35
95
5
TEMPERATURE (°C)
3766 G04
3.05
1.218
54.0
0.725
RUN Hysteresis Current
vs Temperature
3.10
125
CT MODE
3766 G05
RUN VOLTAGE RISING
65
35
95
5
TEMPERATURE (°C)
54.5
0.730
0
–55 –25
RUN Threshold vs Temperature
1.220
55.0
0.735
3766 G04
1.212
–55 –25
RS MODE
0.740
0.5
97
155
125
Average Current Sense Threshold
vs Temperature
CT MODE THRESHOLD (V)
CT MODE THRESHOLD (V)
RS MODE
1.310
–55 –25
3766 G03
56.0
100
1.320
155
0.750
101
1.325
125
RS MODE THRESHOLD (mV)
CT MODE
95
5
35
65
TEMPERATURE (°C)
3.0
RS MODE THRESHOLD (mV)
1.335
–25
103
RESISTANCE (Ω)
1.340
1.330
2.70
–55
155
VAUX Drop-Out Resistance
vs Temperature
Overcurrent Shutdown Threshold
vs Temperature
RUN VOLTAGE (V)
2.75
3766 G02
3766 G01
1.224
2.80
6.5
8
7
LV MODE
7.0
9
2.85
400
300
200
100
65
35
95
5
TEMPERATURE (°C)
125
155
3766 G08
0
0
25
50
100
75
RFS (kΩ)
125
150
3766 G09
3766f
6
LTC3766
TYPICAL PERFORMANCE CHARACTERISTICS
Oscillator Frequency
vs Temperature
FB Voltage vs Temperature
2.0
SGD Delay vs Resistance
250
599.8
MODE = 100k TO GND
SW TIED TO PT+
1.5
200
599.4
0.5
DELAY (ns)
599.2
1.0
VFB (mV)
CHANGE IN FREQUENCY (%)
599.6
599.0
598.8
FS = 18.7k
FS = 124k
FS = VCC
–0.5
–1.0
–55 –25
65
35
95
5
TEMPERATURE (°C)
125
155
598.4
50
598.0
–55
0
–25
5
35
65
95
TEMPERARTURE (°C)
125
155
FGD Delay vs Resistance
30
20
RSGD (kΩ)
40
50
3766 G12
SGD Delay vs Temperature
FGD Delay vs Temperature
250
600
600
RSGD = 49.9k
200
RFGD = 100k
500
500
400
300
DELAY (ns)
400
DELAY (ns)
DELAY (ns)
10
0
3766 G11
700
150
100
RSGD = 15k
50
20
40
80
60
RFGD (kΩ)
0
–55
120
100
RFGD = 10k
100
100
0
300
200
200
–25
65
5
95
35
TEMPERATURE (°C)
125
3766 G13
155
0
–55 –25
65
35
95
5
TEMPERATURE (°C)
Efficiency (Figure 39 Circuit)
2.25
125
155
3766 G15
3766 G14
Gate Driver On-Resistance
vs VCC Voltage
Load Step (Figure 39 Circuit)
96
VOUT
200mV/DIV
2.00
94
1.75
PT+, PT–
PULL-DOWN
1.50
1.25
EFFICIENCY (%)
RESISTANCE (Ω)
FG FALLING
100
598.2
3766 G10
ALL GATES
PULL-UP
IOUT
5A/DIV
92
90
1.00
FG,SG
PULL-DOWN
0.75
0.50
SG RISING
598.6
0
0
150
5
6
7
9
8
10
VCC VOLTAGE (V)
11
88
12
3766 G16
86
VIN = 48V
20µs/DIV
VOUT = 5V
LOAD STEP = 5A TO 15A
VIN = 36V
VIN = 48V
VIN = 72V
3
5
7
9
11
LOAD CURRENT (A)
13
3766 G18
15
3766 G17
3766f
7
LTC3766
PIN FUNCTIONS
(SSOP/QFN)
SG (Pin 1/Pin 26): Gate Drive for the Synchronous MOSFET.
FG (Pin 2/Pin 27): Gate Drive for the Forward MOSFET.
VSEC (Pin 3/Pin 28): Volt-Second Limit. Connect a resistor
from SW to VSEC, and a capacitor from VSEC to GND to set
the maximum volt-second product that is applied to the
main power transformer. The PWM on-time is terminated
when the VSEC voltage exceeds the internally generated
threshold. Tie to GND if not used.
MODE (Pin 4/Pin 1): For normal isolated applications
using the LTC3765, tie to either GND or VCC to set the
operating voltage to either low voltage or high voltage
modes respectively, as needed to drive the gates of the
synchronous and forward MOSFETs. For nonisolated
applications, tie to ground through either a 100k or 50k
resistor to activate standalone mode (for low voltage or
high voltage operation respectively). In this mode, the PT+
pin may be directly connected to the gate of a primary-side
MOSFET, and a reference clock signal is generated on the
PT– pin. In standalone mode, the FGD pin is ignored and
the associated delay is set adaptively.
PHASE (Pin 5/Pin 2): Control Input to the Phase Selector.
This pin determines the phasing of the internal controller
CLK relative to the synchronizing signal at the FS/SYNC pin.
FB (Pin 6/Pin 3): The Inverting Input of the Main Loop
Error Amplifier. Tie to VCC to enable slave mode in
PolyPhase applications.
ITH (Pin 7/Pin 4): The Output of the Main Loop Error
Amplifier. Place compensation components between the
ITH pin and GND.
RUN (Pin 8/Pin 5): Run Control Input. Holding this pin
below 1.22V will shut down the IC and reset the soft-start
and REGSD pins to 0V.
SS (Pin 9/Pin 6): Soft-Start Inputs. A capacitor to ground
sets the ramp time of the output voltage.
IPK (Pin 10/Pin 7): Peak Current Limit Inductor Ripple
Cancellation. This pin is used to adjust the peak current
limit based on the amount of inductor current ripple, thereby
providing a constant average output current during current
limit. Place a resistor to GND that is proportional to the main
output inductor. Leave this pin floating for constant peak
current limit. Minimize parasitic capacitance on this pin.
VSOUT, VS+, VS– (Pins 11, 12, 13/Pins 8, 9, 10): VSOUT is
the output of a precision, unity-gain differential amplifier.
Tie VS+ and VS– to the output of the main DC/DC converter
to achieve true remote differential sensing. Also, VS+ is
used for directly sensing the output voltage for inductor
ripple cancellation. See the Applications Information section for details.
GND (Pin 14/Pin 11, Exposed Pad Pin 29): Signal Ground
and Kelvin Sense for SG Reverse Overcurrent. Connect to
power ground at the source of the synchronous MOSFET.
The exposed pad must be soldered to PCB ground for
rated thermal performance.
FS/SYNC (Pin 15/Pin 12): Combination Frequency Set and
Sync Pin. Tie to VCC to run at 275kHz. Place a resistor to
ground at this pin to set the frequency between 75kHz and
500kHz. To synchronize, drive this pin with a clock signal
to achieve PLL synchronization from 100kHz to 500kHz.
Sources 20μA of current.
REGSD (Pin 16/Pin 13): Regulator Shutdown Timer. Place
a capacitor to ground to limit the time allowed for the high
voltage linear regulator controller to operate. When the
REGSD voltage exceeds 1.21V, the linear regulator is shut
down. This pin sources 13μA of current when the linear
regulator is active.
IS– (Pin 17/Pin 14): Negative Input to the Current Sense
Circuit. Connect to the negative end of a low side current
sense resistor. When using a current sense transformer,
tie this pin to VCC for single-ended sensing on IS+ with a
higher maximum trip level.
IS+ (Pin 18/Pin 15): Positive Input to the Current Sense
Circuit. Connect to the positive end of a low side current sense resistor or to the output of a current sense
transformer.
SGD (Pin 19/Pin 16): Synchronous Gate Rising Edge Delay.
A resistor to GND sets the delay from primary gate turnoff (PT+ falling) to SG rising (and FG falling). This delay
is used to optimize the dead time between the turn-off of
the primary-side MOSFET and the turn-on of SG. Tie SGD
to GND to set this delay adaptively based on the falling
edge of the SW pin voltage. See Setting the Gate Driver
Delays in the Applications Information section.
3766f
8
LTC3766
PIN FUNCTIONS
(SSOP/QFN)
FGD (Pin 20/Pin 17): Forward Gate Rising Edge Delay. A
resistor to GND sets the delay from PT+ rising to FG rising
(and SG falling). This delay is used to optimize the dead
time between the turn-off of SG and the turn-on of the
primary-side MOSFET. In standalone mode (100k or 50k
resistor on MODE), this dead time is set adaptively and
the FGD pin can be grounded. See Setting the Gate Driver
Delays in the Applications Information section.
NDRV (Pin 21/Pin 18): Drive Output for the External Pass
Device of the High Voltage Linear Regulator Controller.
Connect to the base (NPN) or gate (MOSFET) of an external N-type device. Tie to VCC pin if only using the internal
LDO (VAUX pin).
VIN (Pin 22/Pin 19): Connect to a higher voltage bias
supply when using the linear regulator controller. The VIN
pin supplies bias to the internal standby and monitoring
circuits, the linear regulator controller, and the differential
amplifier. Tie to VAUX pin if only using the internal LDO.
SW (Pin 23/Pin 20): Connect (Kelvin) to the drain of the
synchronous MOSFET. This input is used for adaptive
shoot-through prevention and leading-edge blanking,
monitoring the high level SW node voltage and SG reversecurrent protection. When SW is high, the voltage on this
pin is internally measured for use in the inductor ripple
cancellation and volt-second limit circuits. When SW is
low and SG is high, this pin sources a small current and
is used for SG reverse overcurrent protection. A resistor
can be placed between the SW pin and the drain of the
synchronous MOSFET to adjust the SG reverse-overcurrent
threshold. The SW pin is internally clamped to 50V.
VAUX (Pin 24/Pin 21): Auxiliary Power Input. This is the
power input to an internal LDO that is connected to VCC.
Whenever VAUX is greater than 4.7V (or 8V for high voltage
mode), this LDO will supply power to VCC, bypassing the
main linear regulator that is powered from VIN. See VAUX
Connection in the Applications Information section. Do
not exceed 16V on the VAUX pin.
PT –, PT+ (Pin 25, 26/Pin 22, 23): Pulse Transformer Driver
Outputs. For most applications, these connect to a pulse
transformer through a series DC-blocking capacitor. The
PWM information is multiplexed together with DC power
and sent through the pulse transformer to the primary side.
The PWM signal is then decoded by the LTC3765 active
clamp forward controller and gate driver. In standalone
mode (100k or 50k resistor on MODE), the PT+ pin has a
standard PWM signal and may be directly connected to
the gate of a primary-side MOSFET, while a reference clock
is generated on the PT– pin.
PGND (Pin 27/Pin 24): Gate Driver Ground Pin. Connect to
power ground at the source of the synchronous MOSFET.
VCC (Pin 28/Pin 25): Main VCC Input for All Driver and
Control Circuitry.
3766f
9
LTC3766
BLOCK DIAGRAM
VCC
SG
2.2x
PEAK CURRENT
COMPARATOR
IS+
IS–
+
29.3x
–
+
+
2V
–
+
+
C
–
ITH
+
C
–
0.305V
RESET
DOMINANT
ITRP
+
C
–
0.2V
PGND
WAIT
OVP
RQ
S
SKIP
DMAX
SWHI
WAIT
ADAPTIVE
BLANKING
AND DELAY
OVP
+
EA
–
0.60V
gm = 2.7mS
+
ERROR
AMPLIFIER
2.93V
+
C
–
DRIVER
ENCODING
AND
LOGIC
OC
MAIN
XFMR
FG
PGND
VCC
PT+
+
PGND
BLANKING
OSC
AND
PLL
1.9V
BLANK
PULSE
XFMR
BLANK
VSEC(TH)
DMAX
C
PT+/PT–DRIVE TYPE
(PULSE ENCODED/STANDARD)
MODE
DRIVE/VCC
CONTROL
•
PT–
+
–
PHASE
•
VCC
FS/SYNC
SWHI
•
50V
SS
SLOPE
COMP
•
1.4V
VCC
PWM
OVERCURRENT
FB
SW
+
–
VSW
VSEC
SWHI
FGD
HV/LV MODE
SGD
VIN
4VSB
RUN
SD
FB
SS
UVLO
VIN(UV)
30V
5.5mA LIMIT
VREF
4VSB
REG
WAIT
SOFTSTART
4VSB
VS–
+
–
VCC
80k
VS+
80k
+
AMP
–
80k
80k
DIFFERENTIAL AMPLIFIER
275k
UVLO
SD
VCC(UV)
1.22V
LV: 4.7V/4.5V
HV: 8V/7.7V
HV LINREG DISABLE
RIPPLE
CANCELLATION
VOUT SENSE
VCC
GND
EN
VAUX
5V TO 15V DC
12µA
+
–
C
LV: 4.7V/3.9V
HV: 7.9V/6.9V
IPEAK ADJUST
+
A
–
5V TO 32V DC
NDRV
EN
RQ
S
OVERCURRENT
VIN
–
+A
LV: 58k
HV: 46k
SSLO
VSOUT
1.22V
VIN SENSE
REGSD
1.21V
SW
IPK
3766 BD
3766f
10
LTC3766
TIMING DIAGRAM
PULSE ENCODED
PWM
VPT+ – VPT–
PWM ON TIME
LTC3765 AG
LTC3765 PG
~
VIN
1 – DUTY CYCLE
VIN
SWP NODE
0V
LTC3766 SG
LTC3766 FG
~
VOUT
1 – DUTY CYCLE
SWB NODE
0V
VIN •
SW NODE
NS
NP
0V
3766 TD01
SET BY LTC3766 FGD PIN
SET BY LTC3766 SGD PIN
SET BY LTC3765 DELAY PIN
FIXED 180ns DELAY
SW
VIN+
•
SWP
PG
VOUT+
•
SWB
PG
FG
FG
LTC3765
AG
AG
IN+
IN–
•
•
PT+
SW
LTC3766
SG
SG
PT –
VIN–
3766 F01
VOUT–
Figure 1. Reference Schematic for Timing Diagram
3766f
11
LTC3766
OPERATION
The LTC3766 is a secondary-side PWM controller designed
for use in a forward converter with active clamp reset and
synchronous rectification. When used in conjunction with
the LTC3765 active-clamp forward controller and gate
driver, it forms a highly efficient and robust isolated power
supply with a minimum number of external components.
By making use of a secondary-side control architecture, the
LTC3766 is able to provide exceptional transient response
while directly monitoring the load to ensure that both output
voltage and output current are precisely controlled. This
architecture provides superior performance and greater
simplicity, and is particularly well suited to high power
battery charger applications.
Self-Starting Start-Up
In most applications, the LTC3766 will be used with the
LTC3765 to create a self-starting forward converter with
secondary-side control. Since there is initially no bias
voltage available on the secondary side, the LTC3765
must manage the start-up in an open-loop fashion on the
primary side. When power is first applied on the primary
side, the LTC3765 begins an open-loop soft-start using its
own internal oscillator. Power is supplied to the secondary
by switching the main primary-side MOSFET with a gradually increasing duty cycle from 0% to 70%, as controlled
by the rate of rise of the voltage on the SSFLT pin. On the
secondary side, bias voltage can be generated directly from
the main transformer using a peak charge circuit, or other
technique as appropriate. When the LTC3766 has adequate
voltage to satisfy its start-up requirements, it provides
duty cycle information through the pulse transformer as
shown in Figure 2. The LTC3765 detects this signal and
transfers control of the gate drivers to the LTC3766, which
continues the soft-start of the output voltage. Typically,
this hand-off from primary to secondary occurs when the
output voltage is less than one half of its final level. The
LTC3765 then turns off the linear regulator and, through
an on-chip rectifier, extracts bias power for the primaryside MOSFETs from this signal.
Linear Regulators
In general, the bias voltage generated on the secondary
side is higher than the level desired for operation of the
forward and synchronous MOSFETs. Consequently, the
LTC3766 contains a high voltage linear regulator controller
as well as a 15V VAUX bypass regulator with an internal
PMOS, either of which can be used to regulate the voltage on the VCC pin. The linear regulator controller is used
by tying the NDRV pin to the base or gate of an external
N-type pass device. The LTC3766 VIN pin provides bias to
the linear regulator controller as well as to internal standby
and monitoring circuitry. If adequate voltage is detected
on the VAUX pin, then the VAUX bypass regulator will be
activated and the high voltage linear regulator controller
will be shut down to reduce power loss. Alternatively, if
only the VAUX regulator is needed, then the NDRV pin can
be tied off to VCC, while VIN is tied to VAUX. This flexible
arrangement of two linear regulators allows for the convenient and efficient generation of VCC bias voltage for a
wide array of applications.
Using the MODE pin, the output voltage of both linear
regulators can be set to either 7V or 8.5V, depending on
the level needed to drive the gates of the forward and
synchronous MOSFETs. Note that the undervoltage lockout (UVLO) set points as well as VAUX switchover levels
are adjusted along with the VCC regulation levels. This
ensures that the MOSFETs are only switched when there
is adequate gate drive voltage.
Run Control and Soft-Start
The main on/off control for the LTC3766 is the RUN pin.
This pin features precision thresholds with both internal
and externally adjustable hysteresis. This pin can be used
to monitor the secondary-side bias voltage or main output
voltage, thereby controlling the point at which hand-off
from primary to secondary side occurs. Alternatively, it
can be driven directly with a control signal. In nonisolated
applications when the LTC3766 is used standalone, this pin
can be used as an undervoltage lockout by monitoring the
main power supply input voltage. See Nonisolated Applications in the Applications Information section for details.
3766f
12
LTC3766
OPERATION
The LTC3766 will begin a soft-start sequence when the
RUN pin is high, adequate voltage is present on both the
VIN and VCC pins, and switching is detected on the SW
pin. Note that the LTC3766 must see switching on the SW
pin prior to initiating a soft-start sequence to ensure that
the LTC3765 is ready for control hand-off. The soft-start
sequence begins by first measuring the voltage on the FB
pin and then rapidly pre-setting the soft-start capacitor
voltage to a level that corresponds to the output voltage,
VOUT. This is done to provide a smooth ramp on the output
voltage as control is transferred from primary to secondary,
as well as to avoid any unnecessary start-up delay. Once
the soft-start capacitor has been pre-set to the appropriate
level, the LTC3766 then sends a brief sequence of pulses
through the pulse transformer to establish a communication lock between the LTC3766 and the LTC3765. At this
point, the LTC3766 assumes control of the primary-side
MOSFETs, and the soft-start capacitor begins charging
with a constant current of 5μA, continuing the soft-start
of the main output voltage. Note that the soft-start voltage is used to limit the effective level of the reference into
the error amplifier. This technique maintains closed-loop
control of the output voltage during the secondary-side
soft-start interval.
Gate Drive Encoding
Since the LTC3766 controller normally resides on the
secondary side of an isolation barrier, communication to
the primary-side gate driver must be done through a small
pulse transformer. A common scheme for communicating
gate drive (PWM) information makes use of short pulses
and relies on receiver latches to “remember” whether
power MOSFETs should be either on or off. However,
this system is prone to get into the wrong state, and has
difficulty distinguishing a loss of signal from a legitimate
zero duty cycle signal. To alleviate these concerns, the
LTC3766 uses a proprietary gate drive encoding scheme
that reliably maintains constant contact across the isolation barrier without introducing any delay.
The LTC3766 encodes PWM information onto the PT+
and PT – outputs, which are in turn connected to a small
pulse transformer through a DC-blocking capacitor. These
outputs are driven in a complementary fashion, with a
constant 79% duty cycle. This results in a stable voltsecond balance, so that the signal amplitude transferred
across the pulse transformer is constant. As shown in
Figure 2, the beginning of the interval when (VPT+-VPT–) is
positive approximately coincides with the turn-on of the
main primary-side MOSFET. Likewise, the beginning of
the interval when (VPT+-VPT–) is negative coincides with
the maximum duty cycle (forced turn-off of main primaryside MOSFET). At the appropriate time during the positive
interval, the end of the “on” time (PWM going low) is
signaled by briefly applying a zero-volt differential across
the pulse transformer. In the event that a zero duty-cycle
signal needs to be sent, this is accomplished naturally
by placing the zero-voltage differential at the beginning
of the positive interval. In this manner, any duty cycle
from 0% to the maximum of 79% can be sent across
the pulse transformer without delay. Figure 2 illustrates
the operation of this encoding scheme.
On the primary side, the LTC3765 receives the signal from
the pulse transformer through a DC restoring capacitor.
After communication lock has been established between
the two parts, the LTC3765 extracts clock and duty cycle
information from the signal and uses it to control its
gate driver outputs. Note that, except for a tiny pulse,
150ns
150ns
+VCC
VPT+ – VPT –
–VCC
1 CLK PER
1 CLK PER
3766 F02
Figure 2: Gate Drive Encoding Scheme
(MODE = GND or MODE = VCC)
3766f
13
LTC3766
OPERATION
this scheme is constantly applying a differential voltage
across the pulse transformer. Therefore, the LTC3765 can
almost instantly detect a loss of signal and shut off the
power MOSFETs.
Forward Converter and Main Loop Operation
Once communication lock has been established between
the LTC3766 and the LTC3765, the LTC3766 will have
control over the switching of the primary-side MOSFETs.
During normal operation, the main primary-side MOSFET
(connected to PG on the LTC3765) is turned on somewhat
after the forward MOSFET on the secondary side. This
applies the input voltage across the transformer, causing
the SW node on the secondary side to rise. Since the SW
node voltage is greater than the output voltage, the inductor
current ramps upward. When the current in the inductor
has ramped up to the peak value as commanded by the
voltage on the ITH pin, the current sense comparator trips,
turning off the primary-side MOSFET. After a short delay,
the forward MOSFET is turned off and the synchronous
MOSFET is turned back on, causing the inductor current
to ramp back downwards. At the next rising edge of the
LTC3766 internal clock, the cycle repeats as the synchronous MOSFET is turned off and the forward and main
primary-side MOSFETs are again turned on. The LTC3766
error amplifier senses the main output voltage, and adjusts
the ITH voltage to obtain the peak inductor current needed
to keep the output voltage at the desired regulation level.
In some applications, there can be considerable resistive
voltage drops between the main output voltage and the
load. To address this, the LTC3766 contains a precision
differential amplifier, which can be used to remotely sense
a load voltage as high as 15V.
Current Sensing, Slope Compensation and Blanking
The LTC3766 supports current sensing either with a current
sense resistor or with an isolated current transformer. When
using a current sense resistor, the IS+ and IS– pins operate
differentially, and the maximum peak current threshold is
approximately 75mV. Normally, the current sense resistor
is placed in the source of the forward MOSFET to minimize
power loss. If a current transformer is used to sense the
primary-side switch current, then the IS– input should be
tied to VCC and the IS+ pin to the output of the current
transformer. This causes the gain of the internal current
sense amplifier to be reduced, so that the maximum peak
current threshold is increased to approximately 1V.
As with any PWM controller that uses constant-frequency
peak current control, slope compensation is needed to
provide current-loop stability and improve noise margin.
The LTC3766 has fixed internal slope compensation. The
amount of slope has been chosen to be adequate for a
wide range of applications. Normally, the use of slope compensation would have a negative impact on the accuracy
of the current limit, but the LTC3766 uses a proprietary
circuit to nullify the effect of slope compensation on the
current limit performance.
Since the LTC3766 current loop is sensing switch current, leading edge blanking is needed to avoid a current
comparator false trip due to the MOSFET turn-on current
spike. The LTC3766 uses the voltage on the SW pin (tied
to the drain of the synchronous MOSFET) to implement an
adaptive leading-edge blanking of approximately 180ns.
The blanking of the current comparator begins only after
the voltage on SW has risen above 1.4V. This adaptive
blanking is essential because of the potentially long delay
from the time that PT+ rises to the time that the SW node
rises, and current begins ramping up in the output inductor.
This blanking also minimizes the need for external filtering.
Gate Driver Delay Adjustment
As in all forward converters, the main transformer core
must be properly reset so as to maintain a balanced voltsecond product and prevent saturation. This job is handled
on the primary side by the LTC3765, which features an
active clamp gate driver. The active clamp MOSFET works
together with a capacitor to generate an optimal reset voltage for the main transformer. This optimal reset voltage
minimizes voltage stress on the main primary-side MOSFET
and maximizes the utilization of the power transformer
core by reducing the magnetic flux density excursion.
3766f
14
LTC3766
OPERATION
In general, the active clamp MOSFET is switched in a
complimentary fashion to the main primary-side MOSFET.
Since the active clamp MOSFET is a PMOS, the active clamp
gate driver (AG) and the main primary-side gate driver (PG)
voltages are therefore “in-phase,” with a programmable
overlap time set by the LTC3765 DELAY pin.
The delay time between the active clamp PMOS turn-off
and the primary switch NMOS turn-on is critical for optimizing efficiency. When the active clamp is on, the drain
of the primary NMOS, or primary switch node (SWP), is
driven to a voltage of approximately VIN/(1–D) by the main
transformer. When the active clamp turns off, the current
in the magnetizing inductance of the transformer ramps
this voltage linearly down to VIN. Power loss is minimized
by turning on the primary switch when the SWP voltage
is at a minimum. A resistor from the LTC3765 DELAY pin
to ground sets a fixed time for the PG turn-on delay.
The delay time between the primary switch turn-off and
the active clamp turn-on is substantially less critical.
When the primary switch turns off, the main transformer
leakage inductance is biased with the peak current of the
inductor reflected through the transformer. This current
drives the voltage across the active clamp PMOS quickly
to 0V. Turning on the PMOS after this transition results in
minimal switching power loss. The LTC3765 active clamp
turn on delay is internally fixed to 180ns, which normally
achieves zero voltage switching on the active clamp PMOS.
On the secondary side, the turn-on delay of the forward gate
(FG) and synchronous gate (SG) MOSFETs are adjusted by
the FGD and SGD pins respectively. These delays are set
using resistors to GND so as to minimize the dead time
(when the load current is being carried by MOSFET body
diodes) while avoiding shoot-through with the primary-side
MOSFETs. A shoot-through condition exists if either the
PG and SG gates, or the AG and FG gates are high at the
same time. Note that the SG MOSFET turn-on delay has
a minimum limit that is established by the falling edge of
the SW node. The SG pin will not go high until SW has
falling below 0.5V. Refer to Delay Resistor Selection in
the Applications Information Section for more detailed
information. In standalone mode (100k or 50k resistor on
MODE) the dead time between PG and SG is set adaptively
to prevent shoot-through.
Frequency Setting and Synchronization
The LTC3766 uses a single pin to set the operating frequency
or to synchronize the internal oscillator to a reference
clock using and on-chip phase-locked loop (PLL). The
FS/SYNC pin sources a 20μA current, and it may be tied
to VCC for fixed 275kHz operation or have a single resistor
to GND to set the switching frequency to fSW = 4RFS. If a
clock signal (>2V) is detected at the FS pin, the LTC3766
will automatically synchronize to the falling edge of this
signal using an internal PLL.
Current Limit and Inductor Ripple Cancellation
Since the LTC3766 utilizes peak current control, the peak
inductor current is limited when the load current demand
increases above the current limit set point. The peak current
limit is established by an internal clamp on the maximum
level of the ITH voltage. The average current, however,
will be less than the peak current by an amount equal to
one-half of the inductor ripple current. During current limit,
this ripple current will change significantly with variations
in VIN, VOUT and switching frequency. Without inductor
ripple cancellation, this variation in ripple current would
also result in an average output current that changes
significantly, even though the peak current is held at a
constant value.
In order to keep the average current approximately constant
during current limit, the LTC3766 cancels the effect of the
ripple current by adjusting the value of the peak current
limit (or ITH clamp level) in proportion to the amount of
inductor ripple current. This is achieved by generating an
internal ramp that mimics the inductor current ramp, and
3766f
15
LTC3766
OPERATION
then adding the amplitude of this internal ramp to the ITH
clamp voltage on a cycle-by cycle basis. During the on
time, the slope of the inductor current is given by:
dIL VSW – VS+
=
L
dt
The LTC3766 establishes a voltage on the IPK pin of (VSW
– VS+)/15, which is one-fifteenth of the voltage across the
output inductor during the on-time when SW is high. By
choosing a resistor RIPK that is proportional to the value of
the output inductor (RIPK = KL), the current flowing in RIPK
becomes proportional to the slope of the inductor current:
VSW – VS+ VSW – VS+
IRIPK =
=
15RIPK
15KL
During the time when SW is high, the LTC3766 uses the
RIPK current to create an internal ramp by charging an
on-chip capacitor CRIP. The slope of this internal ramp
voltage is given by:
dVRAMP IRIPK VSW – VS+
=
=
CRIP 15KLCRIP
dt
The amplitude of this internal ramp is then added to the
ITH clamp level dynamically. By choosing the appropriate value of RIPK, therefore, the average current during
current limit will be essentially independent of changes
in ripple current.
As is the case with all DC/DC converters that maintain
constant frequency operation, a cycle by cycle current
limit is only effective at duty cycles where the on time is
greater than the minimum controllable on-time. Under
short-circuit conditions, for example, the LTC3766 limits
the current using a separate overcurrent comparator. When
this overcurrent comparator is tripped, the LTC3766 generates a fault followed by a soft-start retry. This hiccup mode
overcurrent protection is highly effective at minimizing
power losses under short-circuit conditions.
Direct Flux Limit
In active clamp forward converters, it is essential to establish an accurate limit to the transformer flux density
in order to avoid core saturation during load transients or
when starting up into a pre-biased output. Although the
active clamp technique provides a suitable reset voltage
during steady-state operation, the sudden increase in duty
cycle caused in response to a load step can cause the
transformer flux to accumulate or “walk,” potentially leading to saturation. This occurs because the reset voltage on
the active clamp capacitor cannot keep up with the rapidly
changing duty cycle. This effect is most pronounced at low
input voltage, where the voltage loop demands a greater
increase in duty cycle due to the lower voltage available
to ramp up the current in the output inductor.
Traditionally, transformer core saturation has been avoided
either by limiting the maximum duty cycle of the converter
or by slowing down the loop to limit the rate at which the
duty cycle changes. Limiting the maximum duty cycle does
help the converter avoid saturation for a load step at low
input voltage, since the duty cycle maximum is clamped;
however, transformer saturation can also easily occur at
higher input voltage where the maximum duty cycle clamp
is ineffective. Limiting the rate of duty cycle change such
that the active clamp capacitor can sufficiently track the
duty cycle change also helps to prevent saturation in many
situations, but results in a very poor transient response.
Neither of these traditional techniques is guaranteed to
prevent the transformer from saturating in all situations.
For example, saturation can easily occur using these
traditional techniques when starting up into a pre-biased
output, where the duty cycle can quickly change from 0%
to 75%. Moreover, neither of these traditional techniques is
able to prevent saturation in the negative direction, which
can result from sudden decreases in duty cycle.
The LTC3765 and LTC3766 implement a new unique system
for monitoring and directly limiting the flux accumulation in the transformer core. During a reset cycle, when
the active clamp PMOS is on, the magnetizing current is
3766f
16
LTC3766
OPERATION
directly measured and limited through a sense resistor
in series with the PMOS source. This prevents saturation
in the negative direction. When the PMOS turns off and
the main NMOS switch turns on, the LTC3765 generates
an accurate internal estimate of the magnetizing current
based on the sensed input voltage on the LTC3765 RUN
pin and transformer core parameters customized to the
particular core by a resistor from the LTC3765 RCORE pin
to ground. The magnetizing current is then limited during
the on-time by this accurate internal approximation. Unlike
previous methods, the direct flux limit directly measures
and monitors flux accumulation and guarantees that the
transformer will not saturate in either direction, even
when starting into a pre-biased output. This technique
also provides the best possible transient response, as it
will temporarily allow very high duty cycles, only limiting
the duty cycle when absolutely necessary. Moreover, this
technique prevents overcurrent damage to the active clamp
PMOS, which is a potentially significant weakness in many
active clamp forward converter designs.
Additional Protection Features
The LTC3766 contains a wide array of protection features,
which protect the DC/DC converter in the event that abnormal conditions persist. In general, protections features
are either classified as a fault or a limit. When a fault is
detected, all switching stops and the LTC3766 initiates a
soft-start retry. Faults of this nature include overcurrent,
overtemperature, differential amplifier miswire and
communication-lock fault.
An overcurrent fault occurs if the peak current exceeds
approximately 133% of its normal value during current
limit. Note that when inductor ripple cancellation is used,
the value of the peak current during current limit will vary
with inductor current ripple. The overtemperature fault is
set at 165°C, with 20°C of hysteresis. This is helpful for
limiting the temperature of the DC/DC converter in the
event of some external device failure or other abnormal
condition. The differential amplifier wiring fault is generated if the inputs on the differential amplifier are reversed,
or if there is not enough voltage on the VIN pin to support
the voltage needed on VSOUT. This is important to avoid
an overvoltage condition on the output. Finally, since it is
essential that the LTC3766 be in constant communication
with the LTC3765, a loss of communication lock will also
generate a fault. A lock condition is detected by monitoring
the SW node voltage, and ensuring that it is both rising
and falling as it should in response to the PWM signal
being sent to the primary side. If the SW node voltage
is not rising and falling in an appropriate manner, than a
lock fault is generated.
In addition to the four protection features that generate
faults, there are also four protection features that establish a
clamp or limit, without generating a fault. First, the LTC3766
contains a precision volt-second clamp. This feature is not
needed when the LTC3766 is used in conjunction with the
LTC3765, which incorporates the direct flux limit feature. If
the LTC3766 is used standalone, however, the volt-second
limit can be used by placing a resistor from the SW node to
the VSEC pin and a capacitor from VSEC to GND. When the
SW node is low, the capacitor is discharged by an on-chip
NMOS. When the SW node is high, the capacitor on VSEC
is charged. If the capacitor voltage exceeds an internally
generated threshold, then the main primary switch will be
turned off, thereby limiting the volt-second product applied
to the main transformer. To compensate for the exponential
nature of the RC charging circuit, the LTC3766 adjusts the
threshold of the volt-second comparator according to:
VSEC(TH) = 0.6 –
0.16
VSW(HI)
where VSW(HI) is the voltage on the SW pin during the
on-time of the primary switch. This keeps the volt-second
limit essentially constant for SW node voltages in the
range of 2V to 40V.
Second, in the event that the main output voltage exceeds its
regulation target by more than 17%, the LTC3766 will detect
an overvoltage condition. If this happens, the LTC3766
will immediately turn off the main primary MOSFET and
3766f
17
LTC3766
OPERATION
turn on the synchronous MOSFET. This has the effect of
pulling down the output voltage to protect the load from
potential damage. Overvoltage protection is not latched,
and normal operation is restored when the output voltage
has been reduced to within 15% of its regulation level.
Third, the LTC3766 contains an adjustable synchronous
MOSFET reverse overcurrent. This is accomplished by
monitoring the SW voltage when the synchronous MOSFET
is on (SG pin is high). If the voltage on SW exceeds a
pre-determined threshold, then the synchronous MOSFET
will be turned off, protecting it from potentially damaging
current levels. This SW threshold for reverse overcurrent
detection can be reduced by placing a resistor in series
with the SW pin, which sources a current when the SG
pin is high. Note that the SG reverse overcurrent threshold and the SW pin source current are adjusted based on
the state of the MODE pin. This is done to accommodate
the use of either high voltage or low voltage MOSFETs,
which normally have significantly different on resistances.
In an overvoltage condition, the SG reverse overcurrent
will override the overvoltage protection and force SG low,
essentially regulating the reverse SG MOSFET current
at a high level while the overvoltage condition persists.
However, the SG reverse overcurrent is only active after
the LTC3766 has achieved communication lock.
Finally, the REGSD pin can be used to limit the amount
of time that the high voltage linear regulator controller
is active. This is particularly useful when the LTC3766 is
used standalone in a nonisolated forward converter. In
this application, the pass device of the linear regulator
controller may be dissipating considerable power. When
the linear regulator controller is active, the REGSD pin
sources a 13μA current. If a capacitor from REGSD to
GND charges to a voltage greater than 1.21V, then linear
regulator controller is disabled.
Gate Driver Mode Control
In addition to being used in conjunction with the LTC3765,
the LTC3766 can also be used standalone in a nonisolated
forward converter application. In this case, the MODE pin
can be used to disable gate drive encoding by tying MODE
to GND through either a 100k (for VCC = 7V operation)
or 50k (for VCC = 8.5V operation) resistor. This causes
a normal PWM signal to appear on PT+ and a reference
clock to appear on PT–.
3766f
18
LTC3766
APPLICATIONS INFORMATION
Secondary-Side Bias and Start-Up
In most applications, the LTC3766 will receive its bias
voltage from a supply that is generated on the secondary
side. The manner in which the secondary bias is generated
depends upon the output voltage as well as the variation in
the input voltage of the DC/DC converter. In all applications,
however, the secondary bias must always come up before
the output reaches the regulation level. This is essential
to avoid an overvoltage condition on the output, since the
initial start-up is performed from the primary side in an
open-loop fashion. See Generating the Secondary-Side
Bias for more information.
Note that the LTC3766 will not begin a soft-start sequence
and initiate switching until the RUN pin is high, adequate
voltage is present on both the VIN and V CC pins, and
switching is detected on the SW pin. The LTC3766 looks
for switching on the SW pin to ensure that the LTC3765 is
active and ready for control hand-off. For switching to be
detected, the SW node waveform must have at least eight
consecutive pulses in the range of 50kHz to 700kHz. The
SW node waveform must also have a peak that is greater
than 1.4V and a valley that is less than 0.5V. In standalone
mode, the LTC3766 begins the soft-start sequence without
waiting for a switching waveform to be detected on the
SW pin.
Linear Regulator Operation
The LTC3766 contains two linear regulators that are used to
regulate the available bias voltage down to a level suitable
for driving MOSFETs. If the bias supply voltage is greater
than 15V, then the high voltage linear regulator controller
may be used. This makes use of an external N-type pass
device. Place a capacitor of 0.22μF or greater on VIN and
1μF or greater on VCC. If the bias supply connected to the
VIN pin has a relatively high output impedance, it may be
necessary to use a larger capacitor on VIN to prevent the
VIN pin voltage from dropping when the VCC capacitor is
being charged. The VCC charge rate during linear regulator
start-up is set by the LTC3766 to approximately 0.5V/μs,
which will create at charging current of (0.5 • 106) CVCC.
Care should be taken to ensure that this charging current
does not exceed the SOA of the N-type pass device, particularly when operating at higher VIN voltages. The VCC
regulation level can be set to either 7V or 8.5V as desired
using the MODE pin. See the section on VCC and Drive
Mode Selection for details.
The LTC3766 also contains a 15V internal bypass LDO. If
the voltage on the VAUX pin exceeds the VAUX switchover
threshold, then the high voltage linear regulator is disabled,
and an internal PMOS-pass LDO uses the VAUX voltage to
supply power to VCC. This allows the high voltage linear
regulator to be used for initial start-up and the higher efficiency bypass LDO to be used during normal operation.
Figure 3 illustrates such a configuration that uses both
linear regulators.
If the voltage on the VAUX pin is below the switchover
threshold, then the VAUX pin is internally loaded with a
resistance of approximately 920Ω. This internal load is
removed after the VAUX regulator is enabled, and is used
to ensure that the VAUX supply is reasonably stiff before
the bypass regulator is activated.
In some cases, it is desirable to use the high voltage linear
regulator only briefly during start-up, so as to limit the
temperature rise in the external pass device. To accomplish
this, place a capacitor on the REGSD pin to ground (see
Figure 3) such that:
CRSD =
tHVREG (13µA )
1.21V
where tHVREG is the time that the high voltage regulator
will operate. When the high voltage regulator is operating, a 13μA current is sourced from the REGSD pin, and
when it is shut down (e.g., the bypass regulator is active), a 3μA current is sinked into the REGSD pin. If the
REGSD voltage exceeds 1.21V, the high voltage regulator
is disabled. Choose a time tHVREG that is greater than the
normal start-up time. After start-up, if the voltage on the
VAUX pin drops, the high-voltage linear regulator will be
re-energized, but only for a limited time.
VIN
CVIN
NDRV
HV BIAS
SUPPLY
6V TO 32V
LTC3766
VCC
OPTIONAL
REGSD
CRSD
VAUX
LV BIAS
CVAUX SUPPLY
5V TO 15V
CVCC
3766 F03
Figure 3. Typical Linear Regulator Connections
3766f
19
LTC3766
APPLICATIONS INFORMATION
When used with a bias supply that is between 5V and 10V,
the VCC pin can be directly connected to the bias supply as
shown in Figure 4a. Note that the VIN and NDRV pins must
also be connected to the bias supply for proper operation
of internal circuitry. When a bias supply between 6V and
15V is available, the VAUX bypass linear regulator can
be used standalone as shown in Figure 4b. In this case,
proper start-up is assured by connecting the NDRV pin
to VCC. Since there is no external pass device on NDRV,
however, the effective UVLO levels will be dictated by
the VAUX switchover thresholds instead of the VCC UVLO
thresholds. Rather than relying on the VAUX thresholds, the
start-up and shutdown levels are normally set by using the
RUN pin to monitor the bias supply voltage as shown in
Figure 4b. See the RUN Pin Operation section for details.
For applications where the available bias supply is greater
than 30V, the LTC3766 also contains a current-limited 30V
clamp on the VIN pin. This clamp can sink up to 3.5mA
to allow the VIN pin to be used as a shunt regulator. This
is especially useful in nonisolated applications where the
LTC3766 is used standalone. See the Nonisolated Applications section for more information.
LTC3766
VIN
NDRV
CVCC
VCC
LV BIAS
SUPPLY
5V TO 10V
Figure 4a. No Linear Regulator Used
VIN
LV BIAS
SUPPLY
6V TO 15V
VAUX
R1
CVAUX
RUN
NDRV
Normal operation is enabled when the voltage on RUN
rises above its 1.22V threshold. As shown in Figure 5,
the RUN pin can be used with an external resistor divider
to enable the LTC3766 operation based on a sensed voltage VX. In self-starting applications, VX is normally either
the converter output voltage (VOUT) or a bias voltage. In
nonisolated applications, VX is normally the converter
input voltage (VIN). See Nonisolated Applications for more
information on the use of the RUN pin in nonisolated
applications.
VX
R1
RUN
R2
VCC
CVCC
3766 F04b
Figure 4b. VAUX Regulator Used Standalone
R2
LTC3766
GND
3766 F05
Figure 5. Using the RUN Pin to Determine Start-Up
A 3µA current is pulled into the RUN pin when it is below
its threshold that, when combined with the value chosen
for R1, increases the hysteresis beyond the internal amount
of 4%. When used in this manner, the values for R1 and
R2 can be calculated from the desired rising and falling
VX thresholds by the following equations:
R1=
3766 F04a
LTC3766
RUN Pin Operation
R2 =
VX(RISING) – 1.043 • VX(FALLING)
3µA
1.17 •R1
VX(FALLING) – 1.17
In self-starting applications where the LTC3765 performs
an open-loop soft-start, the voltage VX can be tied to VOUT
of the converter (VX = VOUT) to inhibit the LTC3766 startup until the output voltage is above a given level. This
sets the exact output voltage at which soft-start control
is handed off from primary to secondary. This hand-off
output voltage should be set high enough so as to avoid
pulse-skipping operation when the LTC3766 initially takes
3766f
20
LTC3766
APPLICATIONS INFORMATION
control. If excessive pulse skipping occurs in applications
that use a peak charge circuit to generate bias voltage, this
can cause the bias supply to fall, preventing proper startup. To preclude this possibility, use the RUN pin to inhibit
the LTC3766 start-up until the output voltage is at least:
VOUT(ON) > 300ns
NS fSW VIN(MAX)
NP
In PolyPhase applications, synchronization can be achieved
by tying the PT – pin of the master to the FS/SYNC pin of
each slave. The relative phase delay of each slave is set
using the PHASE pin. Any one of five preset values can be
selected as shown in Table 2. Note that the phase delay
is relative to the falling edge of the incoming reference
clock on the FS/SYNC pin, since the falling edge of PT –
corresponds to the beginning of the PWM cycle.
Note that in self-starting applications, direct RUN/STOP
control should be handled only on the primary side using
the LTC3765. If the LTC3765 gets disabled, the LTC3766
will sense that the primary side is no longer switching
and automatically shut down. To avoid a possible output
overvoltage, do not manually disable the LTC3766 unless
the LTC3765 is also manually disabled.
Table 2
If the RUN pin function is not needed, it can be tied directly
to the VIN pin.
In some applications, it is desirable to start switching at a
given frequency, and then synchronize to a clock reference
signal at a later time. This can be accomplished by using
the circuit shown in Figure 6.
Setting the Switching Frequency and Synchronization
The switching frequency of the LTC3766 is set using the
FS/SYNC pin. This pin sources a 20μA current, and a resistor to ground on this pin sets the switching frequency
to a value equal to:
fSW = 4RFS
PHASE PIN
PHASE DELAY
APPLICATION
GND
180°
2-Phase and 4-Phase
25k to GND
240°
3-Phase
50k to GND
120°
3-Phase
100k to GND
90°
4-Phase
100k to VCC
270°
4-Phase
2N2222A
CLK
50k
BAT54
FS/SYNC
10k
Alternatively, the FS/SYNC pin can be tied to VCC, which
sets the switching frequency to a fixed value of 275kHz.
In general, a higher switching frequency will result in a
smaller size for inductors and transformers, but at the cost
of reduced efficiency. Although the LTC3766 can operate
from 75kHz to 500kHz, the best balance between efficiency
and size for a forward converter is found when operating
between 150kHz and 350kHz.
If a clock signal (>2V) is detected at the FS pin, the LTC3766
will automatically synchronize to the falling edge of this signal. Table 1 summarizes the operation of the FS/SYNC pin.
Table 1
FS/SYNC PIN
SWITCHING FREQUENCY
VCC
275kHz
RFS to GND
fSW = 4RFS
Reference Clock
fSW = fREF (100kHz to 500kHz)
10nF
RFS
LTC3766
GND
3766 F06
Figure 6. Synchronization After Free Running
Once the LTC3766 has been synchronized, do not remove
the external synchronizing clock unless the LTC3766
is also shut down. Removal of the external clock after
synchronization will result in operation at low frequencies
for a period of time, which can lead to very high currents
in external power components.
Setting the Output Voltage
The LTC3766 output voltage is set by an external feedback
resistor divider placed across the output as shown in
Figure 7. The regulated output voltage is determined by:
 R 
VOUT = 0.6V •  1+ B 
 RA 
3766f
21
LTC3766
APPLICATIONS INFORMATION
Be careful to keep these divider resistors very close to the
FB pin to minimize the trace length and noise pick-up on
the sensitive FB signal. Using a low resistance (<2k) for
the output voltage divider also minimizes noise on the FB
pin. If the remote sense amplifier is used, then the divider
should be placed between the VSOUT pin and GND. See
the Remote Sensing section for details.
VOUT
LTC3766
RB
VFB
RA
3766 F07
Figure 7. Setting the Output Voltage
Selecting the Main Transformer
The job of the transformer in a forward converter is to
step the voltage either up or down while providing isolation between the primary and secondary grounds. Ideally,
this transformer would not store any energy (it would have
infinite magnetizing inductance). Note that this objective
is very different from that of the transformer used in a
flyback converter. The transformer used in a flyback converter is really a coupled inductor, the purpose of which is
to store energy during the primary-side on time and then
deliver it to the secondary during the off-time. In a forward
converter, by contrast, the power is transferred during the
primary-side on-time, and the off-time is used to recover
the small amount of energy that was inadvertently stored
in the core of the transformer.
For nearly all applications, an off-the-shelf transformer can
be selected. Transformers using planar winding technology
are widely available and are a good choice for minimizing
leakage inductance as well as component height. There
are two basic items to consider in selecting an appropriate family of off-the-shelf transformers: 1) the isolation
requirements and 2) the power level requirements. If the
application circuit has specific isolation requirements,
choose a family of transformers whose isolation level
satisfies that requirement. In addition to an isolation voltage rating, the application may require a transformer with
certification from a particular agency, or it may require a
specific type of isolation (e.g., basic or functional). In terms
of power level, choose a family of transformers whose
rated power level exceeds that of the required amount of
output power. Be careful to allow for room to “grow,” as
the power requirements of many electronic systems tend
to increase throughout development.
Once a family of transformers has been selected, the
next step is to choose a suitable transformer from within
that family. This mainly consists of choosing the correct
number of primary and secondary turns (NP and NS). The
value of NS can be calculated from:
NS =
108 VOUT
fSW A CBM
where AC is the cross-sectional area of the core in cm2 (as
normally given in the transformer data sheet) and BM is the
maximum AC flux density desired. For the Pulse PA08xx
series power transformers used in the Typical Applications
section, AC = 0.59cm2. For the Pulse PA09xx series power
transformers, AC = 0.81cm2. Most high frequency transformers use a ferrite core material. Consequently, selecting
a maximum AC flux density of 2000 gauss is normally a
good starting point, provided that the switching frequency
is between 150kHz and 350kHz. This value of BM leaves
headroom during transients and avoids excessive core
losses. Note that the choice of BM together with switching frequency will determine the amount of core loss for
a given transformer. Consult the transformer data sheet to
evaluate the resulting core loss and temperature rise. In
some cases, it may be necessary to increase NS somewhat
in order to reduce BM and the associated temperature rise.
In all cases, be sure to stay well below the saturation flux
density of the transformer core.
Once the value of has NS been selected, the required
transformer turns ratio can be calculated from
NP DMAX VIN(MIN)
=
NS
VOUT
where VIN(MIN) is the minimum input voltage and DMAX
is the maximum duty cycle. Although the LTC3766 has a
maximum duty cycle of 79% (DMAX = 0.79), normally a
lower value of DMAX is chosen in the above equation so
that there is duty cycle headroom to accommodate load
3766f
22
LTC3766
APPLICATIONS INFORMATION
transients when operating at minimum input voltage. A
value for DMAX of 0.65 to 0.70 is appropriate for most
applications.
Having selected a particular transformer, calculate the
copper losses associated with the transformer winding.
These losses are highest when operating at maximum
duty cycle and full load. However, it is better to evaluate
copper losses at the nominal operating point of 50% duty
cycle, where the losses are approximately:
PCU
2
IMAX ) 
(
R
=
2
2

 NS 
RPRI 
SEC + 


 NP 
where RPRI and RSEC are the primary and secondary
winding resistances respectively, and IMAX is the maximum output current. An optimal transformer design has
a reasonable balance between copper and core losses. If
they are significantly different, then adjust the number of
secondary turns (and recalculate the needed turns ratio)
to achieve such a balance.
Inductor Value Calculation
The selection of an output inductor is essentially the same
as for a buck converter. For a given input and output voltage, the inductor value and operating frequency determine
the ripple current. The ripple current ∆IL increases with
higher VIN and decreases with higher inductance:
∆IL =
VOUT  VOUT NP 
1–
•
fSWL 
VIN NS 
Accepting larger values of ∆IL allows the use of low inductances, but results in higher output voltage ripple and
greater core losses. A reasonable starting point for setting
the ripple current is ∆IL = 0.3(IOUT(MAX)) for nominal VIN.
The maximum ∆IL occurs at the maximum input voltage.
Inductor Core Selection
Once the value for L is known, the type of inductor must
be selected. High efficiency converters generally cannot
afford the core loss found in low cost powdered iron cores,
forcing the use of the more expensive ferrite cores. Actual
core loss is essentially independent of core size for a fixed
inductor value but it is very dependent on the inductance
selected. As the inductance increases, core losses decrease.
Unfortunately, increased inductance requires more turns
of wire and therefore copper losses will increase.
Ferrite designs have very low core losses and are preferred at high switching frequencies, so design goals can
concentrate on copper loss and preventing saturation.
Ferrite core material saturates “hard,” which means that
inductance collapses abruptly when the peak design current
is exceeded. This results in an abrupt increase in inductor
ripple current and consequent output voltage ripple. Do
not allow the core to saturate!
Active Clamp Capacitor
The active clamp capacitor, CCL, stores the average reset
voltage of the transformer over many cycles. The voltage
on the clamp capacitor is generated by the transformer
core reset current, and will intrinsically adjust to the optimal
reset voltage regardless of other parameters. The voltage
across the capacitor at full load is approximately given by:
VCL =
VIN2

N 
VIN – 1.15  VOUT • P 
N 

S
NP/NS is the main transformer turns ratio. The factor of
1.15 accounts for typical losses and delays. When PG and
AG on the LTC3765 are low, the bottom side of the clamp
capacitor is grounded, placing the reset voltage, VCL, on
the SWP node. When PG and AG are high, the top side of
the capacitor is grounded, and the voltage on the bottom
side of the capacitor is –VCL. Therefore the voltage seen
on the capacitor is also the voltage seen at the drains of
the PG and AG MOSFETs.
As shown in Figure 8, the VCL voltage has a minimum when
the converter is operating at 50%. For a given range on
VIN, therefore, the maximum clamp voltage (VCL(MAX)) will
occur either at the minimum or maximum VIN, depending
on which input voltage causes the converter to operate
furthest from 50% duty cycle. The maximum VCL voltage
can be determined by substituting the maximum and
minimum values of VIN into this equation and selecting
the larger of the two. In order to leave room for overshoot,
3766f
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LTC3766
APPLICATIONS INFORMATION
cause oscillations under certain conditions. To avoid the
problems associated with this resonance, always use
an RC snubber in parallel with the clamp capacitor as
shown in Figure 9. The values for this RC snubber can
then be calculated using:
ACTIVE CLAMP VOLTAGE
NORMALIZED TO 50% DUTY CYCLE
1.6
1.5
1.4
1.3
1.2
RCS =
1.1
1.0
0.9
20
30
40
50
60
DUTY CYCLE (%)
70
80
3766 F08
Figure 8. VCL Voltage vs Duty Cycle
choose a capacitor whose voltage rating is greater than
this maximum VCL voltage by 50% or more. Typically, a
good quality (X7R) ceramic capacitor is a good choice for
CCL. Also, be sure to account for the voltage coefficient of
the capacitor. Many ceramic capacitors will lose as much
as 50% of their value at their rated voltage.
The value of the clamp capacitor should be high enough
to minimize the capacitor ripple voltage, thereby reducing
the voltage stress seen by the MOSFETs. However, a larger
clamp capacitor will ultimately result a slower transient
response to avoid transformer saturation during load
transients. While Direct Flux Limit will automatically limit
the PWM on-time only as needed to prevent saturation, a
larger clamp capacitor will require a longer time to charge
or discharge in response to a load transient. Consequently,
the value of the clamp capacitor represents a compromise
between transient response and MOSFET voltage stress. A
reasonable value for the clamp capacitor can be calculated
using the following:
1  4 
CCL =
•
2LM  2πfSW 
2
An additional design constraint on CCL occurs because of
the resonance between the magnetizing inductance LM of
the main transformer and the clamp capacitor CCL. If the
Q of this resonance is too high, it will result in increased
voltage stress on the primary-side MOSFET during load
transients. Also, a high Q resonance between LM and CCL
complicates the compensation of the voltage loop, and can
1
 V
N 
O
1– 
• P
 VIN(MIN) NS 
LM
CCL
and
CCS = 6CCL
Figure 9 shows a typical arrangement of the active clamp
capacitor with an RC snubber. Be careful to account for
the effect of voltage coefficient for both CCS and CCL to
ensure that the above relationship between CCS and CCL
is maintained.
LM
VIN
SWP
CCL
RCS
CCS
SNUBBER
ACTIVE
CLAMP
PMOS
3766 F09
Figure 9. Active Clamp Capacitor and Snubber
Direct Flux Limit
In active clamp forward converters, it is essential to establish an accurate limit to the transformer flux density
in order to avoid core saturation during load transients or
when starting up into a pre-biased output. The LTC3765
and LTC3766 implement a new unique system for monitoring and directly limiting the flux accumulation in the
transformer core. Unlike previous methods, the direct flux
limit directly measures and monitors flux accumulation and
guarantees that the transformer will not saturate in either
direction, even when starting into a pre-biased output.
This technique also provides the best possible transient
response, as it will temporarily allow very high duty cycles,
only limiting the duty cycle when absolutely necessary.
Moreover, this technique prevents overcurrent damage to
3766f
24
LTC3766
APPLICATIONS INFORMATION
the active clamp PMOS, which is a potentially significant
weakness in many active clamp forward converter designs.
Since the direct flux limit functionality is implemented
in the LTC3765 on the primary side, there is nothing to
adjust on the secondary side. See the LTC3765 data sheet
for details on using this feature. Note that if the LTC3765
terminates the PG MOSFET on-time prematurely to limit
flux accumulation, the LTC3766 will sense a premature
falling on the SW node. In response, the LTC3766 will
automatically terminate the FG on-time, thereby allowing
the transformer core to reset. A premature falling on the
SW node will also occur whenever the LTC3765 has shut
down for any reason. Consequently, if the LTC3766 detects
19 consecutive premature SW node falling edges on the
SW pin, it will generate a lock fault and shut down.
Primary-Side Power MOSFET Selection
On the primary side, the peak-to-peak drive levels for
both the N-channel main switch and the P-channel active
clamp switch are determined by the voltage on the VCC
pin of the LTC3765. This voltage is normally provided
through the pulse transformer, and is typically set in the
range of 8.5V to 12V. Note that even in applications where
a logic-level MOSFET may be used on the primary side,
the VCC voltage on the LTC3765 must still be in this range
for proper operation.
Selection of the N-channel MOSFET involves careful
consideration of the requirements for breakdown voltage
(BVDSS) and maximum drain current, while balancing the
losses associated with the on-resistance and parasitic
capacitances. In an active clamp topology, the maximum
drain voltage seen by this MOSFET is approximately:
VDS(PG) = 1.2 • VCL(MAX)
where VCL(MAX) is the maximum active clamp voltage given
above in the Active Clamp Capacitor section. The factor
of 1.2 has been added to allow margin for ringing and
ripple on the clamp capacitor. It is important to select the
lowest possible voltage rating for this MOSFET in order
to maximize efficiency. Note that the RC snubber on the
active clamp capacitor (see Figure 10) reduces the peak
voltage stress on the primary-side MOSFET without adding
to operating losses. Also, the leakage inductance of the
main transformer at full load can cause considerable ripple
on the active clamp capacitor, pushing up the peak voltage
stress seen by the primary-side MOSFET. This ripple can
be reduced by using a larger active clamp capacitor and
a proportionally larger RC snubber capacitor. See Active
Clamp Capacitor section for more information.
Once the required BVDSS of the N-channel MOSFET
is known, choose a MOSFET with the lowest available
on-resistance (RDS,ON) that has been optimized for
switching applications (low QG). In most applications,
the MOSFET will be used at a drain current that is a fraction of the maximum rated current, so this rating is not
normally a consideration. The total losses associated with
the N-channel MOSFET at maximum output current can
be estimated using:
 N  V (I
)
PPG =  P  OUT MAX (1+ δ )RDS(ON)
V
N 
2
S
IN
N  V I R Q f
+  S  CL MAX DR GD SW + QGTOT VCC fSW
2VMILLER
 NP 
where δ is the temperature dependence of the on-resistance
and VCL is the active clamp voltage (see Active Clamp Capacitor section). RDR (approximately 1.7Ω for the LTC3765)
is the gate drive output resistance at the MOSFET’s miller
plateau voltage, VMILLER. The values of QDG, QGTOT and
VMILLER can be taken from the VGS versus QG curve that
is typically provided in a MOSFET data sheet. QGD is the
change in gate charge (QG) during the region where the
VGS voltage is approximately constant and equal to miller
voltage, VMILLER. The total gate charge (QGTOT) is the
gate charge when VGS = VCC. The three parts in the above
equation represent conduction losses, transition losses
and gate drive losses respectively. Highest efficiency is
obtained by selecting a MOSFET that achieves a balance
between conduction losses and the sum of transition and
gate drive losses. Note that the above equation for PPG
is an approximation that includes assumptions. First, it
is assumed that the turn-on transition losses are relatively small because of the leakage inductance in the main
transformer. Also, it is assumed that the energy stored
in this leakage inductance at primary-switch turn-off is
3766f
25
LTC3766
APPLICATIONS INFORMATION
completely recovered by the active clamp capacitor. For
most applications, these assumptions are valid and the
above equation is a good approximation.
The active clamp P-channel MOSFET has the same BVDSS
requirement as that of the N-channel MOSFET. Since the
P-channel MOSFET only handles the magnetizing current,
it is normally much smaller (typically a SOT package).
To accommodate abnormal transients, use a P-channel
MOSFET that has a pulsed drain current rating of 2A or
higher. Also, note that when the N-channel MOSFET turns
off, the leakage inductance will momentarily force the reflected load current into the body diode of the P-channel
MOSFET. Consequently, the body diode should be rated
to handle a pulsed forward current of:
N 
ID(MAX) =  S  IMAX
N 
The first step in selecting the secondary-side MOSFETs is
to determine the needed breakdown voltage. The maximum
voltage seen by the synchronous MOSFET is approximately:
N 
VDS(SG) = 1.2 •  S  VIN(MAX)
 NP 
where the factor of 1.2 has been added to allow for ringing
and overshoot. This assumes that a snubber has been used
on the secondary side of the main transformer (see the RC
Snubbers section). If no snubber is used, the ringing and
peak overshoot will be considerably higher. The maximum
voltage seen by the forward MOSFET is approximately:
1.2 • VOUT
VDS(FG) =
1–
P
In some cases, it may be more practical to add a separate
diode in parallel with the body diode of the P-channel
MOSFET.
The primary-side P-channel MOSFET may be driven by a
simple level-shift circuit that shifts down the drive voltage
on the LTC3765 AG pin. Alternatively, the level-shift circuit
can be omitted if the source of the P-channel MOSFET
is returned to the VCC pin of the LTC3765. Refer to the
LTC3765 data sheet for details.
In nonisolated applications where the LTC3766 is used
standalone, it is necessary to use a resonant reset technique instead of the active clamp reset. As a result, there
are special considerations in selecting the primary-side
MOSFET. See the Nonisolated Applications section for
additional information.
Secondary-Side Power MOSFET Selection
On the secondary side, the peak-to-peak drive level for the
N-channel MOSFETs is determined by the VCC pin on the
LTC3766. Assuming that one or both of the linear regulators in the LTC3766 are used, the VCC regulation voltage
can be set to either 7V or 8.5V as needed for driving the
gates of the MOSFETs.
VOUT  NP 
VIN(MIN)  N S 
where the factor of 1.2 has again been added to allow for
ringing and overshoot.
Having determined the BVDSS requirement for the forward
and synchronous MOSFETs, the next step is to choose the
on-resistance. Since both secondary-side MOSFETs are
zero-voltage switched, choose MOSFETs that have a low
RDS(ON) and have been optimized for use as synchronous
rectifiers, including a body diode with a fast reverse recovery if possible. In most applications, the nominal input
voltage will correspond to approximately 50% duty cycle,
so the forward and synchronous MOSFETs will be selected
to have the same RDS(ON). The power loss associated with
the forward MOSFET can be approximated by:
 N  V (I
)
PFG =  P  OUT MAX (1+ δ )RDS(ON)
V
N 
2
S
IN
+QGTOT VBIAS fSW
where δ is the temperature dependence of the on-resistance
and VBIAS is the input to the LTC3766 linear regulator (if
used). The value for QGTOT can be taken from the VGS
versus QG curve given in the MOSFET data sheet. QGTOT
is the value of QG when VGS = VCC, where VCC is the
3766f
26
LTC3766
APPLICATIONS INFORMATION
voltage on the VCC pin of the LTC3766. For the synchronous
MOSFET, the power loss is approximately:
 N V 
2
PSG =  1– P OUT  (IMAX ) (1+ δ )RDS(ON)
 NS VIN 
+QGTOT VBIAS fSW
The power losses for the synchronous and forward MOSFET
are generally dominated by conduction losses. For both
of the above power loss equations, it is assumed that the
dead time (when the MOSFET body diode is conducting)
has been minimized. See Setting the Gate Drive Delays
section for details on minimizing the dead time.
VCC and Drive Mode Selection
In order to accommodate various operating gate voltages
that may be required by the secondary-side MOSFETs, the
MODE pin can be used to set the LTC3766 for either LV
mode or HV mode operation. In LV mode, the VCC regulation point for both linear regulators is set to 7V, while
the VCC UVLO and VAUX switchover rising thresholds are
adjusted to 4.7V. In HV mode, the VCC regulation point is
set to 8.5V, while the VCC UVLO and the VAUX switchover
rising thresholds are set to 7.9V and 8V respectively. Use
LV mode for MOSFETs that are rated for 4V to 5V operation, and use HV mode for those rated with 7V to 10V
operation. The VCC regulation levels, as well as the UVLO
and switchover voltages have been optimized to ensure
that both types of MOSFETs are operated safely and efficiently. In general, MOSFETs with a higher VDS rating also
have a higher operating gate voltage rating. As a result,
applications with output voltages of approximately 12V
and higher will generally use MOSFETs that are rated for
7V to 10V gate operation.
In addition to changing the VCC regulation, UVLO and VAUX
switchover levels, the selection of HV mode or LV mode
also changes the behavior of the SG reverse overcurrent.
In LV mode, the reverse overcurrent threshold on the
SW pin is 73mV and the adjust current is 103μA. In HV
mode, these levels are changed to 148mV and 42μA to
account for the fact that high voltage MOSFETs have larger
on-resistance than low voltage MOSFETs. For details, see
the Setting the SG Reverse Overcurrent.
In applications where the LTC3766 is used in conjunction
with the LTC3765, the signals on the PT+ and PT – pins
contain encoded PWM information with amplitude equal to
the VCC voltage. This encoded gate drive signal is received
by the LTC3765 and decoded into PWM and clock information that drives the primary-side MOSFETs. However,
the LTC3766 can also be used standalone in nonisolated
forward converter applications. In such applications, the
MODE pin can be used to disable the PWM encoding
on the PT+ and PT – pins. As a result, the LTC3766 will
generate a normal PWM gate drive signal on the PT+ pin
and a reference clock on the PT – pin. Also, in standalone
mode the FGD pin is ignored and the dead time between
SG falling and PT+ rising is set adaptively.
The MODE pin has four possible states. Tying MODE to
GND or VCC will provide encoded gate drive signals with
either LV mode or HV mode operation respectively. Tying
MODE to GND through either a 100k or a 50k resistor will
provided standard PWM gate drive signals with either LV
mode or HV mode operation respectively. Table 3 Summarizes the use of the MODE pin for setting the operating voltage and gate drive encoding modes, and Table 4
summarizes the effect of low voltage and high voltage
gate drive operating modes.
Table 3
MODE PIN
DRIVE LEVEL PT+/PT– MODE INTENDED APPLICATIONS
GND
LV
Encoded PWM Low VOUT Isolated Apps
with LTC3765
VCC
HV
Encoded PWM High VOUT Isolated Apps
with LTC3765
100k to GND
LV
Standard PWM Low VOUT, Nonisolated
Apps, Standalone
50k to GND
HV
Standard PWM High VOUT, Nonisolated
Apps, Standalone
Table 4
DRIVE
LEVEL
VCC
VCC UVLO
THRESHOLD
(RISE/FALL)
VAUX
SWITCHOVER
THRESHOLD
(RISE/FALL)
SG
OVERCURRENT
VTH
ISW
LV
7.0V
4.7V/3.9V
4.7V/4.5V
73mV
103μA
HV
8.5V
7.9V/6.9V
8.0V/7.7V
148mV
42μA
3766f
27
LTC3766
APPLICATIONS INFORMATION
Input Capacitor/Filter Selection
In applications with a low impedance source, or where there
the input voltage is relatively low, a simple capacitive input
filter is generally suitable. This capacitor needs to have a
very low ESR and must be rated to handle a worst-case
RMS input current of:
 N  IOUT(MAX)
IC(RMS) =  S 
2
 NP 
Note that capacitor manufacturers’ ripple current ratings
are often based on only 2000 hours of life. This makes
it advisable to further derate the capacitor, or to choose
a capacitor rated at a higher temperature than required.
Several capacitors may be paralleled to meet size or height
requirements in the design. Due to the high operating
frequency of the LTC3766, ceramic capacitors can also
be used for CIN. Always consult the manufacturer if there
is any question.
For higher input voltage applications, however, it can be
very costly to use bulk capacitance that is rated to handle
the required RMS current. Also, if a simple capacitor is
used as an input filter, it is hard to know exactly where
the AC input current will flow when a power supply is
placed into a larger system. To avoid these issues, an LC
filter can be used on the power supply input as shown in
Figure 10. This keeps the large AC currents contained in
relatively small and inexpensive capacitors whose RMS
current rating is known to be adequate. Choosing an LC
filter such that:
 N  V

R
LF
< 2.9 •  S  RIPPLE + ESR 
2 
CF
 NP  IOUT(MAX)
where VRIPPLE is the desired ripple voltage at the output
of the input filter and RESR is the ESR of capacitor CF. A
reasonable target for VRIPPLE 3% of nominal VIN.
When using an LC input filter, the output impedance of
the LC filter must never be greater in magnitude than
the input impedance looking into the power stage of the
DC/DC converter. This is necessary to avoid loop instabilities. In most applications, this condition is naturally
satisfied because the ESR of the bulk input capacitance,
CBULK, is high enough to lower the Q of the LC input filter,
thereby reducing the peaking in its output impedance to a
safe level. Also, using a larger value for CF reduces the Q,
although this can be expensive in high VIN applications.
In some situations, a series damping network must be
added as shown in Figure 10.
LD
VIN+
RD
OPTIONAL
MAIN
TRANSFORMER
LF
ZOUT
CBULK
VIN–
f
1
< SW
5
2π LF CF
ZIN
•
•
CF
3766 F10
Figure 10. Input Filter with Optional Damping Network
will attenuate the AC content of the RMS input current by
a factor of approximately 5×. This greatly alleviates the
RMS current requirements of the bulk input capacitor. The
filter inductor should have a saturation current of at least:
ISAT(LF) ≥ 1.3 •
In order to keep the ripple voltage at the filter output to
a reasonable level, choose a value of LF and CF that also
satisfies:
VOUT IOUT(MAX)
In order to provide critical damping, choose LD and RD
according to:
LD =
LF
L
and RD = 0.8 F
5
CF
VIN(MIN)
3766f
28
LTC3766
APPLICATIONS INFORMATION
The damping inductor LD does not carry the DC input
current. However, to ensure adequate attenuation during
large transients, choose an inductor whose saturation
current is at least:
 VOUT IOUT(MAX) 
ISAT(LD ) ≥ 0.6 

 VIN(MIN) 
Output Capacitor Selection
The selection of COUT is driven by the effective series
resistance (ESR) and the resulting output voltage ripple.
Typically, once the ESR requirement is satisfied, the
capacitance is adequate for filtering. The output ripple
(∆VOUT) is approximated by:


1
∆VOUT ≈ ∆IL  ESR +
8fSW COUT 

This is because the current loop does not see the magnetizing current, and will not provide its own safeguard
against saturation. Note that in nonisolated applications,
however, the current sense resistor is placed in series
with the primary-side switch, so the current loop will be
monitoring magnetizing current.
When using a current sense resistor, the IS+ and IS– pins
operate differentially and the maximum peak current threshold is approximately 75mV. Normally, the current sense
resistor is placed in the source of the forward MOSFET,
as shown in Figure 11. Depending on PCB layout and the
shielding of the traces going to the IS+ and IS– pins, it is
sometimes necessary to add a small amount of filtering
as shown in Figure 11. Typically, values of RFL = 100Ω
and CFL = 200pF to 1nF will provide adequate filtering of
noise pickup without substantially affecting the current
loop response.
FORWARD
MOSFET
where fSW is the operating frequency, COUT is the output
capacitance and ∆IL is the ripple current in the inductor.
The output ripple is highest at maximum input voltage
since ∆IL increases with input voltage.
Compared to a current transformer, a current sense resistor
is less expensive and somewhat simpler to apply than a
current transformer. When current sensing on the secondary side of an active clamp forward converter, direct
flux limit is required to prevent transformer saturation
and possible damage of the primary-side MOSFET.
LTC3766
RFL
RSENSE
RFL
Current Sensing and Average Current Limit
The LTC3766 supports current sensing either with a current sense resistor or with an isolated current transformer.
A current transformer is generally more efficient and has
the advantage of sensing current on the primary side in
isolated applications. This can be important because it
provides an additional safeguard against saturating the
main transformer during load transients. In addition, a
current transformer can generate a much larger current
sense signal than a sense resistor, resulting in a vastly
superior signal to noise ratio. This eases board layout
concerns for noise pickup and reduces jitter as well. Also,
the accuracy of LTC3766 current limit is significantly better
in current transformer mode than in current sense mode.
FG
IS +
CFL
IS –
3766 F11
Figure 11. Using a Current Sense Resistor
This filter is also helpful in correcting for the effect of the
ESL (parasitic inductance) of the sense resistor, which can
be important for RSENSE values less than 2mΩ. The effect
of the ESL is cancelled if the RC filter is chosen so that:
RFLCFL =
ESL
RSENSE
Since the LTC3766 implements an average current limit
architecture, choose the value of RSENSE based upon the
desired average current limit:
RSENSE =
55mV
ILIM(AVG)
Alternatively, if a current transformer is used to sense
the primary-side switch current, then the IS– pin should
be tied to VCC and the IS+ pin to the output of the current
3766f
29
LTC3766
APPLICATIONS INFORMATION
transformer. This causes the gain of the internal current
sense amplifier to be reduced, so that the maximum peak
current voltage is increased to approximately 1V. The
current transformer connections are shown in Figure 12.
CURRENT
TRANSFORMER
+
VIN
•
•
SF =
DCT
IS+
RCAL
1k
RSENSE
CFL
•
•
VCC
LTC3766
GND
NP
IS–
3766 F12
NS
voltage and comparing it to the output inductor current.
Figure 13 shows an example of a well-calibrated current
sense transformer, where the RSENSE voltage has been
scaled by a factor of:
MAIN
TRANSFORMER
NP
RSENSE K CT NS
Because of the magnetizing current, the slope of the scaled
RSENSE voltage will not exactly match that of the inductor
current. Choose RCAL so that the scaled RSENSE voltage
and the inductor current are identical at the peak.
PG
VIN–
Figure 12. Using a Current Sense Transformer
Typically, the current transformer is placed in series with
the power supply feed to the main transformer. This reduces
common mode noise, and is generally convenient for the
PCB layout. Use a small filter capacitor, CFL, between 1nF
and 3.3nF, or a time constant for RSENSE • CFL of less than
75ns, to eliminate high frequency noise. The diode DCT
is needed to allow the core of the current transformer to
properly reset.
When using a current transformer, set the value of RSENSE
using:
RSENSE =
N
0.73V
• P
K CT ILIM(AVG) NS
where NP/NS is the turns ratio of the main transformer,
KCT is the current gain of the transformer, and ILIM(AVG) is
the average current limit desired. For most applications,
a current transformer turns ratio of 1:100 is suitable
(KCT = 0.01).
The resistor RCAL is added to compensate for the effects of the magnetizing current in the main and current
sense transformers, both of which cause the voltage on
RSENSE to be somewhat higher than expected (2% to
8%). Typically, RCAL is in the range of 1.5k to 5k. For the
highest possible accuracy, the value of RCAL should be
adjusted to calibrate the current sensing at full load and
nominal input voltage by carefully measuring the RSENSE
20A
INDUCTOR
CURRENT
2A/DIV
SF • VRSENSE
2A/DIV
500ns/DIV
3766 F13
Figure 13. Properly Calibrated Current Transformer
In order to maintain a constant average current while
in current limit, the LTC3766 automatically adjusts the
value of the peak current limit to cancel the effect of the
inductor ripple current. This is accomplished by creating
an internal ramp that mimics the inductor current ripple.
The amplitude of this ramp is determined by the resistor
on the IPK pin, which must be set to be proportional to
the output inductor. The LTC3766 establishes a voltage
on the IPK pin of (VSW – VS+)/15, which is one-fifteenth
of the voltage across the output inductor during the ontime when SW is high. Therefore, it is imperative that the
SW and VS+ pins be connected as shown in Figure 14
or Figure 15 so that the LTC3766 can properly sense the
inductor voltage. If the differential amplifier is not needed,
tie VS– and VS+ together to VOUT as shown in Figure 14b.
For high VOUT applications where the SW node plateau
voltage is greater than 40V, it is necessary to add a resistor divider on both the SW and VS+ pins, as shown in
Figure 15. This divider will limit the voltage at the SW pin
and also impact the SG reverse overcurrent trip threshold.
See Setting the SG Reverse Overcurrent for details on
selecting the resistor divider on the SW pin.
3766f
30
LTC3766
APPLICATIONS INFORMATION
•
For resistor sense mode, place a resistor on the IPK pin
that is chosen using:
VOUT
VSW
•
LTC3766
VS+
MAIN
XFMR
SW
VS–
IPK
VSOUT
RLOAD
VFB
RA
3766 F14a
Figure 14a. Setting the Average Current Limit (RIPK)
•
LTC3766
MAIN
XFMR
VS+
SW
VS–
IPK
VSOUT
RIPK
3766 F14
Figure 14b. Setting RIPK with No Differential Amplifier
VOUT
VSW
•
•
MAIN
XFMR
R1
LTC3766
VSOUT
SW
R2
160k VS–
IPK
RIPK
RIPK =
VOUT
VSW
•
120k VS+
KRLIPK
(17.6nF )RSENSE
where LIPK is the inductance of the output inductor at I =
ILIM(AVG). For low VOUT applications where no SW node
divider is needed, KR = 1. For current transformer mode,
use:
RB
RIPK
RIPK =
R3
R4
GND
KRLIPK
N
• P
(1.32nF )KCT RSENSE NS
When the LTC3766 is in current limit and the output voltage is very low, the control of the output current will be
limited by the minimum on-time of the converter. Once this
minimum on-time has been reached, further decreases in
output voltage during current limit will result in an inductor
current that continues to rise, until the overcurrent limit
is reached. This will cause the LTC3766 to shut down and
attempt a restart, resulting in a hiccup mode of operation.
Typical average current limit performance is illustrated
in Figure 16. Note that the average current delivered to
the load is held substantially constant as the output voltage is decreased down to a low level, at which point the
converter will enter hiccup mode. Depending upon the
particular application, hiccup mode is entered either due
to the loss of secondary-side bias voltage (UVLO) or due
to an overcurrent fault.
3766 F15
6
Figure 15. Setting RIPK for High VOUT Applications
R2
69k •R4
KR =
=
R1+R2 69k •R4 +R3 ( 69k +R4)
where the 69k accounts for the internal resistance on the
VS+ and VS– pins.
OUTPUT VOLTAGE (V)
Note that the ratios of the resistor dividers on the SW
and VS+ pins must be the same for ripple cancellation to
operate properly. This requires that:
5
4
3
2
1
0
VIN = 72V
VIN = 36V
0
5
10
15
20
LOAD CURRENT (A)
25
30
3766 F16
Figure 16. Typical Current Limit Performance
3766f
31
LTC3766
APPLICATIONS INFORMATION
Estimating the Average Current Limit Accuracy
The accuracy of the average current limit depends on the
LTC3766 specifications together with a number of application circuit parameters as well as parasitics. Consequently,
it is very difficult to precisely calculate the average current
limit accuracy. This accuracy can be estimated, however,
by carefully considering the three primary sources of error:
1. The accuracy of the current sense resistor and/or current sense transformer. For resistor sensing, the accuracy of the current sense resistor is normally 1%. For
sense resistors less than 2mΩ, however, the parasitic
inductance can cause a significant error in the sensed
current. This error can be eliminated by adding an RC
filter as shown in Figure 11.
When using a current transformer, the accuracy of the
sense resistor on the current transformer secondary and
the turns ratio of the transformers (both KCT and NP/
NS) are generally 1% or better. Depending on where the
current sense transformer is placed, however, there can
be an additional 1% to 4% error due to the magnetizing
current of both the main and current sense transformers. Generally, this error is in the form of a relatively
constant offset, and it can be adjusted out for a particular
design for nominal input voltage and maximum load
current. The resulting tolerance due to the variation in
magnetizing current effects is generally less than 2%,
resulting in an overall accuracy of approximately 3%
for current transformer sensing.
2. The accuracy of the average current sense threshold
VIS(AVG). The accuracy of the LTC3766 current sense
threshold is given in the Electrical Characteristics table
and depends on the current sense mode chosen. Current
transformer mode provides an accuracy of 10% and is
more accurate than the resistor sense mode accuracy
of 15%.
3. The accuracy of the compensation for inductor ripple
current. The accuracy of the inductor ripple compensation depends both on the internal adjustment of VITH
as well as the tolerance of the output inductor itself.
For most application circuits, the ripple compensation
accuracy will be 25% or better for current transformer
mode, and 35% or better for resistor sense mode. Note
that the inductor current ripple is typically 30% to 60%
of the average current limit, and only one-half of this
peak-to-peak ripple is being compensated. As a result,
the effect of the ripple compensation accuracy on the
average current limit is attenuated by a factor of:
FR =
R
R+2
where R is the ratio of the peak-to-peak inductor ripple
current to the average current limit. For 30% to 60%
ripple, for example, the value of FR varies from 0.13 to
0.23.
Considering each of the above factors, the worst-case
tolerance of the average current limit can be estimated as:
∆IAVG = 3% + 10% + 0.23 (25%) = 18.5%
for current transformer mode and:
∆IAVG = 1% + 15% + 0.23 (35%) = 24%
for resistor sense mode. Since the three sources of error
are statistically independent, the current limit tolerance for
current transformer and resistance sense modes can be
calculated using the RSS method as approximately 12%
and 17% respectively.
Setting the Gate Drive Delays
The forward switch gate driver (FG) and the synchronous
switch gate driver (SG) operate with make-before-break
timing on the FG rising edge, and with simultaneous timing on the SG rising edge. The delays for these transitions
relative to the switching of the primary-side MOSFETs are
critical for optimizing efficiency, and can be configured
independently using the SGD and FGD pins.
The SG rising delay should be adjusted to minimize the
switch node (SW) body diode conduction. At full load, the
power loss in the body diode is significant, and the SG
rising delay can have a substantial impact on efficiency.
By minimizing the dead time between PG falling and SG
rising (while avoiding shoot-through), this power loss
is also minimized. Similarly, the dead time between SG
falling (set by the FG rising delay) and PG rising should
also be minimized.
3766f
32
LTC3766
APPLICATIONS INFORMATION
In addition to being set to minimize the dead time between
SG falling and PG rising, the FG rising delay should also
be adjusted to ensure that the drain of the forward switch
(SWB) is close to 0V when the switch is turned on, which
minimizes switching loss. When the LTC3765 active clamp
switch turns off, the drain voltage of the primary switch
(SWP) decreases linearly from VIN/(1 – D) to VIN, where D
is the duty cycle. On the secondary side of the transformer,
SWB ramps from VOUT/(1 – D) to 0V. Switching power
loss is minimized when FG and PG MOSFETs are switched
with minimal drain-to-source voltage across them. The FG
and PG rising delays should be adjusted to ensure that
the SWB and SWP nodes are at their minimums when the
switches are turned on.
Keep in mind the following set of relationships when setting the delays (refer to the Timing Diagram and Figure 1):
1. The forward gate (FG) always turns on with makebefore-break timing relative to the synchronous gate
(SG). This ensures that negative inductor current does
not create excessive voltage on the synchronous switch
drain.
2. Shoot-through is caused when the synchronous gate
(SG) and the LTC3765 primary gate (PG) are simultaneously high, or when the forward gate (FG) is high
and the LTC3765 active gate (AG) is low. The leakage
inductance of the main transformer will prevent significant power loss due to shoot-through for a few tens
of nanoseconds; however, if the PG and SG or FG and
AG gates are on simultaneously for a longer period of
time, the shoot-through will cause power loss, excessive heat, and potentially rapid part displacement.
3. The primary side turn-off of either AG or PG should
occur before FG and SG switch, and the primary-side
turn-on should occur after FG and SG switch. For example, on a particular cycle, AG goes high first (turning
the PMOS off), then FG goes high, then SG goes low,
then PG goes high. On the PG turn-off edge, PG goes
low first, then FG goes low and SG goes high, then AG
goes low (turning the PMOS on).
Delay Resistor Selection: PG Turn-Off Transition
In general, the PG turn-off delays are relatively simpler
to set and less critical than the PG turn-on delays. At the
end of the PWM on-time, the LTC3766 will assert a falling
edge on the PT+ pin, which in turn causes the LTC3765 to
immediately turn off the PG MOSFET. After a fixed 180ns
delay, the LTC3765 will then turn on the AG MOSFET.
Consequently, the only delay adjustment to be made for
this transition is on the secondary side using the SGD pin
of the LTC3766. This pin is used to set the delay from PT+
falling to FG falling/SG rising, which must occur after PG
turn-off and before AG turn-on.
The first consideration in setting the SGD delay is to
reduce the dead time between PG and SG, during which
the body diode of the synchronous MOSFET is carrying
the load current. After PG turn-off, the SW node on the
secondary side will rapidly fall until being clamped by the
body diode of the SG MOSFET. The objective is to turn on
the SG MOSFET as the SW node crosses through 0V. The
LTC3766 makes this easy to achieve by directly sensing
the SW node and inhibiting SG turn-on until SW has fallen
through 0.5V. In other words, minimum dead time between
PG and SG can be achieved by setting the SGD delay to any
value less than or equal to the delay time from PT+ falling to
SW falling through 0V. In general, this delay time is in the
range of 50ns to 100ns. The resistor from SGD to ground
that gives a particular delay tSGD can be computed using:
RSGD = ( t SGD – 12ns ) •
1kΩ
4.3ns
A 10k resistor from SGD to ground sets the FG falling/SG
rising delay to approximately 50ns, which is generally a
good starting point. To prevent damaging cross conduction between the FG and AG MOSFETs, do not set the
SGD delay to be longer than the 180ns fixed turn-on
delay of the AG MOSFET. Always start low when setting
the SGD delay. This is safe because of the adaptive limit
that inhibits premature SG turn-on.
3766f
33
LTC3766
APPLICATIONS INFORMATION
Another important consideration in setting the SGD delay
is the prevention of SWP collapse due to excessive FG
turn-off delay. After PG turn-off, the SWP node is quickly
driven high by the transformer leakage to a level of approximately VIN/(1 – D). Ideally, it should remain at this
voltage as FG turns off, SG turns on, and then AG turns
on. However, if the delay to FG turn-off is too long, the
SWP voltage will momentarily fall towards VIN, and it will
not rise again until being forced high by AG turn-on. This
collapse of the SWP node is illustrated in Figure 17, and
is more prominent at lighter loads.
It can significantly degrade efficiency as the SWP node
is discharged and recharged every cycle, but it is easily
avoided by further shortening the SGD delay. Although
the LTC3766 inhibits the SG turn-on until SW < 0.5V, this
is not true of the delay to FG turn-off. The delay from PT+
falling to FG turn-off can be decreased beyond the adaptive
~
VIN
1–D
SWP NODE VIN
0V
AG
PT +
FG
tSGD TOO LONG
~
VIN
1–D
SWP NODE VIN
0V
AG
PT +
FG
tSGD OK
3766 F17
Figure 17. Avoiding SWP Collapse from Long Delay
limit of SG turn-on, so that the FG and SG edges can be
separated with a small dead time between them. This is
important to allow the FG turn-off to be separately optimized based upon circuit parasitics. In most applications,
a peak in full load efficiency is normally found with the
SGD delay set so that there is no SWP collapse and there
is a small dead time between FG turn-off and SG turn-on.
In applications where efficiency is less critical, this delay
can be set adaptively by tying SGD to GND. In this case,
FG falling and SG rising will both be inhibited until SW <
0.5V. For fixed delay mode, always use a resistor of 8k or
greater on the SGD pin to avoid activating the adaptive
delay mode.
Delay Resistor Selection: PG Turn-On Transition
The delays associated with the PG turn-on transition are
set by the DELAY pin on the LTC3765 and the FGD pin on
the LTC3766. At the beginning of the PWM on-time, the
LTC3766 will assert the PT+ pin high, and will then turn FG
on and SG off after a delay set by the resistor on the FGD
pin. On the primary side, the LTC3765 will immediately
turn off the AG MOSFET in response to PT+ rising, and it
will then turn on the PG MOSFET after a delay determined
by the resistor on the LTC3765 DELAY pin. The FGD delay
resistor on the secondary side must be selected in careful
coordination with the delay on the primary side; therefore,
the following procedure outlines how to choose components for both the LTC3765 and LTC3766.
The first objective in setting the PG turn-on delays is to
minimize switching loss by turning on the PG and FG
MOSFETs at minimum drain voltage. After the AG MOSFET
has turned off, the PG and FG drain voltages (SWP and
SWB) will naturally ramp down to approximately VIN and
0V respectively. These voltages take 100ns to 500ns or
longer to fall, depending on the main transformer magnetizing inductance and the parasitic capacitance on the
MOSFET drains. Choosing the delay settings correctly
can significantly impact the power loss due to switching
the MOSFETs.
For a particular design, the most effective procedure is to
set the PG and FG delays based on the resulting waveform
on SWP and SWB. In order to evaluate these waveforms,
3766f
34
LTC3766
APPLICATIONS INFORMATION
the delays should initially be selected so that they are
long, while keeping in mind that the FG delay must be less
than the PG delay to prevent potentially damaging PG/SG
cross-conduction. As a first pass, use a 75k resistor from
FGD to ground for a 415ns delay and 60k resistor from
DELAY to ground for a 622ns delay. The SWP and SWB
waveforms should appear as shown in Figure 18.
The ramp rate on SWB and SWP is to a first order independent of duty cycle; however, the starting point of the
ramp is a function of the duty cycle. Therefore, the longest
delay time will be at high duty cycle when VIN is at a minimum. For the lowest switching losses over the range of
input voltage, the delays should be chosen based on the
waveforms when VIN is at its minimum operating voltage.
The resistor value from the FGD pin to ground should be
selected first. This should be chosen to give a delay equal
to the time from PT+ rising until SWB ramps down to approximately 0V. The FGD resistor value can be determined
from the following equation:
RFGD = ( tFGD – 18ns) •
1kΩ
5.1ns
Note that if the FG turns on before the SWP and SWB
voltages have naturally fallen to their minimums, they will
be instantly pulled to their minimum by the FG MOSFET
PT+
0V
~
VIN
1–D
SWP NODE
VIN
0V
V
~ OUT
1–D
SWB NODE
0V
3766 F18
tFGD
Figure 18. SWP and SWB Waveforms
turning on. This can give the appearance that FG is turning on after SWB has ramped to 0V, although it is actually
premature. Turning on FG prematurely will slightly degrade
efficiency due to increased switching loss; however, if the
fall time of SWP and SWB exceed a maximum FGD delay
of 600ns, it is acceptable to have premature FG turn-on
at low input voltage. Generally, the delay will be adequate
at higher VIN to allow a complete ramp down.
In rare cases, the LTC3765 and LTC3766 will be in delay
phase-out mode when operating at minimum VIN voltage.
This will be apparent because the measured delay will be
smaller than the programmed delay on either or both chips.
This feature allows the LTC3765 and LTC3766 to operate
at duty cycles up to a maximum of 79% by reducing the
programmed delays when they would otherwise limit the
maximum duty cycle. If this mode is evident, increase VIN
until delay phase-out is no longer active, and then set the
FGD delay as described above.
Having set the FGD delay to optimize for low voltage
switching, the PG delay is next chosen to minimize the
dead time between SG turn-off and PG turn-on. The delay
for the primary gate can be determined by taking the delay set tolerance and rise/fall times into account. The FG
delay setting on the LTC3766 and the PG delay setting on
the LTC3765 are both accurate to within 15% for a range
of resistance values. Given this accuracy, a reasonable
choice for the LTC3765 delay time is to set the PG delay
time to 1.22 • tFGD.
Be aware that the fall time of SG and the rise time of PG
cannot be neglected. For example, if SG is driving a MOSFET
with high input capacitance, and PG is driving a MOSFET
with low input capacitance, then SG will fall slowly and
PG will rise quickly. This increases the potential for shootthrough. Moreover, since SG will not turn off until FG turns
on (make before break), the rise time of FG is also a factor.
A final consideration is that the LTC3765 experiences a
delay in PT+ rising due to the pulse transformer. All of these
considerations can be accounted for in the delay resistor
selection by the following equation, in which tD(PT) is the
delay time from PT+ rising to IN+ rising on the LTC3765,
tR(FG) is the rise time of FG to 2V, tF(SG) is the fall time of
3766f
35
LTC3766
APPLICATIONS INFORMATION
SG to 1V and tR(PG) is the rise time of PG to 1V. The delay
time can then be chosen such that:
tPGD = 1.22 • tFGD + tR(FG) + tF(SG) – tR(PG) – tD(PT)
The resistor from the LTC3765 DELAY pin to ground can be
selected to give this delay by using the following equation:
RDELAY = ( tPGD – 45ns ) •
1kΩ
9.5ns
In practice, the LTC3765 PG turn-on delay should be
optimized by monitoring the PG and SG waveforms. A
conservative approach is to set the PG delay to create a
dead time between SG falling and PG rising that accounts
for the delay set tolerances (typically 22% of the total delay).
A more aggressive approach takes into account the fact
that transformer leakage inductance will delay the effect
of PG turn on (i.e., SW node rising) by 75ns to 150ns or
more at full load. Also, transformer leakage inductance
mitigates the effect of a small amount of shoot-through
by slowing the rise time of the transformer current. Higher
full-load efficiency can be achieved by setting the PG turnon closer to SG turn-off. In addition, a shorter dead time
at PG turn-on can reduce the overshoot and ringing on
the switch node, thereby reducing the size of the required
RC snubber and its associated power loss.
While a shorter dead time at PG turn on can improve full-load
performance, care must be taken to ensure that the worst
case shoot-through at no load is well within safe limits.
Maximum Duty Cycle and Delay Phase-Out
While the PG turn-on delay time is important for reducing
turn-on switching losses, no power is transferred from the
input supply to the output load during this delay time. In
most forward converter systems, the maximum available
duty cycle is artificially limited by this delay, which then
forces a trade-off between the optimal delay time and the
maximum available duty cycle. The LTC3765 and LTC3766
implement a unique delay phase-out feature in which the
PG and FG turn-on delays are gradually reduced as the
demanded duty cycle approaches the maximum value of
79%. This feature allows a forward converter to be designed
with an optimal delay at nominal input voltage, but still
approach the maximum duty cycle at low input voltage,
thereby making better utilization of the power transformer.
Generating Secondary-Side Bias
There are five items to consider when determining the
best way to generate bias for the LTC3766 in an isolated
application:
1. The required operating current. This includes the gate
drive current for both primary and secondary MOSFETs
as well as the operating supply currents of both the
LTC3765 and the LTC3766.
2. The operating voltage needed for the MOSFET gates.
Depending on whether logic-level or standard threshold MOSFETs are used, the VCC operating voltage and
undervoltage lockout (UVLO) levels can be set accordingly using the MODE pin. The bias supply must provide
adequate voltage to keep the LTC3766 VCC pin above
its UVLO level and keep the overall supply operating at
peak efficiency.
3. Current limit operation at low output voltage. The
minimum required VOUT during current limit relative to
the normal operating VOUT has a major impact on the
design of the bias supply. The bias supply must provide
adequate voltage over this range of VOUT voltages.
4. The variation in input voltage. At minimum input voltage,
the bias supply must still provide enough voltage for
proper operation. At maximum voltage, the bias supply
must not generate a voltage that exceeds maximum
ratings or dissipates excessive power.
5. The potential need for a rapid hand-off from primary
to secondary control. In PolyPhase applications, it is
important to quickly transfer control to the secondary
side during start-up so that current sharing and proper
phasing can be established before the full load current
is seen at the output. By contrast, some applications
may not need to have control handed off to the secondary until just prior to the output reaching its regulation
value. In all applications, however, the secondary bias
must always come up and control must be transferred
before the output reaches the regulation level.
The current that must be supplied by the secondary bias
supply can be estimated using
IVCC ≈ (QGPRIfSW + 3mA)NPT + QGSECfSW + 18mA
3766f
36
LTC3766
APPLICATIONS INFORMATION
where QGPRI is the total gate charge of all primary-side
MOSFETs, QGSEC is the total gate charge of all secondaryside MOSFETs, and NPT is the turns ratio of the pulse
transformer. Note that the primary-side current is scaled
by the turns ratio of the pulse transformer. The 18mA
constant in the above equation includes typical gate drive
switching current as well as losses associated with the
pulse transformer.
Using VOUT Directly for Secondary-Side Bias
The simplest method of generating secondary-side bias
is to directly use the output voltage of the converter. This
is only practical when VOUT is in the range of 5V to 15V.
When VOUT is in the range of 5V to 10V, it can be directly
connected to VCC as shown in Figure 4a. When VOUT is in
the range of 6V to 15V, it can be used as a bias input to the
VAUX regulator as shown in Figure 4b. For output voltages
higher than 15V, this method is generally not practical
due to high power dissipation. This simple method also
does not provide constant current limit operation at lower
output voltage. It also does not provide a quick hand-off
to the secondary and is not recommended for PolyPhase
applications.
Using a Peak Charge Circuit for Secondary-Side Bias
A common way to generate a bias voltage on the secondary side is by using a peak charge circuit connected to the
transformer secondary, as shown in Figure 19. This circuit
is useful for generating an unregulated bias voltage that
can be directly tied to the VIN pin of the chip and used as
an input to the high voltage linear regulator.
The peak charge circuit is capable of providing bias even at
low output voltages, so it is a good choice when constant
current limit operation is needed over a wide VOUT range.
FROM
TRANSFORMER
SECONDARY
LTC3766
VIN
NDRV
VBIAS = 6V TO 32V
DPK
RPK
CPK
Q1
VCC
Since it provides a bias voltage even when the converter
is operating at tiny duty cycles, the peak charge is also
a good choice for PolyPhase applications where a quick
hand-off to secondary is important. However, since the
output of a peak charge circuit directly follows changes
in the converter input voltage, it is should only be used in
applications where the input voltage varies by 2:1 or less.
Note that for bias voltages on the VIN pin of 28V or greater,
the internal 30V clamp will draw between 3.5mA and 7mA.
This will result in 100mW to 200mW of additional power
dissipation in the LTC3766. To limit the initial charging
current out of the peak charge circuit, use a series resistor RPK in the range of 1Ω to 4Ω. A schottky diode DPK
with a peak surge current rating of 5A or higher should
also be used, and the pass transistor Q1 should have a
minimum beta of at least 200. Capacitor CPK should be a
ceramic capacitor with a value of at least 2.2μF or greater.
During open-loop start-up, it is imperative that the peak
charge bias come up and control is transferred to the
secondary before an output overvoltage can occur. Since
a peak charge circuit is not directly coupled to the output
voltage of the converter, care must be taken to ensure
that the primary-side soft-start is not too fast relative to
the rise time of the peak charge bias on the secondary
side. The time required for the peak charge bias voltage
to rise to a level that allows control to be handed off to
the secondary can be approximated using:
tBIAS ≈ 103 • REQCPK CSSP + 150µs
where REQ is the sum of RPK and the series resistance of
diode DPK, and CSSP is the LTC3765 soft-start capacitor.
During open-loop soft-start, the time required for the
converter output voltage to reach a given level VHO can
be approximated using




2
2 ( V ) LC
f
C


OUT
SW
SSP
HO
tOUT ≈ 10 4 • 

2

NS 


 VIN(MIN) • N 


P
1/3
CVCC
3766 F19
Figure 19. Peak Charge Circuit for Secondary Bias
The above equation assumes that there is no load current,
which is the worst-case condition for output voltage rise.
3766f
37
LTC3766
APPLICATIONS INFORMATION
When calculating tOUT, use a value for VHO that corresponds to the target output voltage for control hand-off,
typically one-half the normal regulation level or less. If tOUT
is less than tBIAS, then the LTC3765 soft-start capacitor
value should be increased. Note that these equations are
approximations and the actual times will vary somewhat
with circuit parameters.
Peak Charge Bias Configurations
When the peak voltage on the SW node is in the range of
7V to 32V, the peak charge can be taken directly from the
SW node as shown in Figure 20. In practice, this condition only holds when the output voltage of the converter
is approximately 5V.
In most applications, it is necessary to add an additional
auxiliary winding on the secondary for use in generating an
SW
•
•
NP
NS
DPK
MAIN
XFMR
RPK
LTC3766
VIN
NDRV
VBIAS = 6V TO 32V
CPK
Q1
VCC
CVCC
adequate bias voltage. For low VOUT applications (VOUT <
5V), this winding can be configured as shown in Figure 21
to provide a higher voltage for bias generation.
This configuration is advantageous because it achieves
a higher voltage on the transformer secondary with a
minimum number of additional turns. The number of turns
on the auxiliary winding for this configuration should be
approximately:
 VB(MIN)DMAX 
NAUX ≈NS 
– 1
VOUT


where DMAX is the maximum operating duty cycle (typically
0.65 to 0.70) and VB(MIN) is either 7V for low voltage or
10V for high voltage drive mode operation. These values
for VB(MIN) are approximately 2V higher than the UVLO
levels on the LTC3766 to allow for drops in the peak charge
circuit. As an example, for VOUT = 1.5V, DMAX = 0.65V and
NS = 1 turn, use NAUX = 2 turns, assuming low voltage
drive mode.
For high VOUT applications (VOUT > 6V), this winding can
be configured as shown in Figure 22 to provide a reduced
voltage for generating bias. In this case, choose an auxiliary
winding with turns
 VB(MIN)DMAX 
NAUX ≈NS 

VOUT


3766 F20
Figure 20. Peak Charge Directly from SW for VOUT ≈ 5V
•
NAUX
•
NAUX
MAIN
XFMR
SW
•
•
•
NP
NS
NP
SW
•
NS
DPK
DPK
MAIN
XFMR
RPK
LTC3766
VIN
NDRV
VBIAS = 6V TO 32V
VIN
CPK
Q1
RPK
LTC3766
NDRV
VBIAS = 6V TO 32V
CPK
Q1
VCC
VCC
CVCC
CVCC
3766 F22
3766 F21
Figure 21. Peak Charge for Low VOUT Applications
Figure 22. Peak Charge for High VOUT Applications
3766f
38
LTC3766
APPLICATIONS INFORMATION
At maximum VIN, there may be considerable power dissipation in the linear regulator pass device Q1. This power
can be calculated using
For Figure 24 the output is given by:
VBUCK = VOUT
PQ1 = (VBIAS – VCC)IVCC
NAUX
– 0.5
NS
In applications where the peak charge and high voltage
linear regulator must operate continuously, transistor
Q1 must be capable of dissipating this power without
excessive temperature rise. In such applications, use a
transistor with a suitable package (SOT89) and connect
the thermal tab of the transistor to an adequately large
island of copper on the PCB.
For a buck bias supply, inductor LBK must be rated to
carry the required VCC bias current and should have an
inductance value that will provide continuous current
operation at one-fourth of the required bias current load
or less. Choose and inductor LBK to according to:
High Efficiency Secondary-Side Bias Techniques
A value of 1mH for LBK is adequate for most applications.
A high-efficiency alternative to using a peak-charge circuit
to generate secondary-side bias is to connect a buck output
to the transformer secondary. This buck output is normally
combined with a peak charge circuit as shown in Figures 23
and 24. The bias voltage from this buck output can be fed
directly into the VAUX pin. This arrangement combines
the quick start-up and flexibility of a peak charge circuit
with the higher operating efficiency of a buck bias supply.
The output voltage of the buck bias supply (VBUCK) should
be set to optimize efficiency during normal operation.
This will typically require a somewhat higher number of
auxiliary turns than is ideal for a peak charge output. As
a result, the buck supply and the peak charge circuit are
sometimes driven from separate auxiliary windings. Also,
note that the output voltage of the peak charge circuit will
increase somewhat when the VAUX bypass regulator is
activated and the high voltage linear regulator is disabled.
Care must be taken not to exceed the maximum voltage
rating on the VIN pin of the LTC3766.
For Figure 23, the output voltage of the buck bias supply
is given by:
 N

VBUCK = VOUT  1+ AUX  – 0.5
NS 

LBK >
VCC
ICC fSW
•
NAUX
•
DBK
NAUX
LBK
SW
•
•
DBK
NS
NP
MAIN
XFMR
MAIN
XFMR
VBUCK
•
CBK
DPK
NP
•
NS
OPTION TO
LIMIT Q1 POWER
VAUX
VIN
NDRV
REGSD
CPK
Q1
VCC
CVCC
3766 F23
Figure 23. Buck Bias Supply for Low VOUT Applications
CBK
DPK
LTC3766
CRSD
VBIAS = 6V TO 32V
DBK
RPK
RPK
REGSD
VBUCK
SW
LTC3766
CRSD
DBK
LBK
OPTION TO
LIMIT Q1 POWER
VAUX
VIN
NDRV
VBIAS = 6V TO 32V
CPK
Q1
VCC
CVCC
3766 F24
Figure 24. Buck Bias Supply for High VOUT Applications
3766f
39
LTC3766
APPLICATIONS INFORMATION
The buck bias winding can also be used standalone
without the peak charge supply, as shown in Figure 25.
This is sometimes done in applications where the peak
charge circuit is impractical, such when the VIN voltage
has a wide range.
When using the buck bias supply standalone, particular
care must be taken to ensure that the bias output comes
up more quickly than the main output, and that there is
adequate bias voltage immediately after control handoff. This is made more difficult by the presence of some
load on the VCC pin during start-up whereas there may
be no load on the main output. In general, a clean startup with a standalone buck bias supply can be achieved
by observing the following guidelines: 1) set the turns
ratio of the auxiliary winding so that the operating VAUX
will be at least 3V above the rising VCC UVLO voltage,
2) use a smaller value for LBK, typically one-half of that
calculated in the above equation, but always large enough
for continuous current in LBK during normal operation
3) use the high-voltage linear regulator to minimize the
load on VCC during start-up, 4) use the RUN pin to monitor
the bias voltage and set the start-up voltage to 2V above
the rising VCC UVLO voltage with a hysteresis of 1.5V, 5)
use a shorter soft-start time, less than 10ms if possible,
6) use a small VCC capacitor (typically CVCC = 0.22μF) and
a capacitor CBK given by:
CBK =
20 (QGPRIfSW + 3mA )NPT + 18mA 
fSW VHYST
where VHYST is the hysteresis set by the RUN pin (1.5V).
Note that this value for CBK is as small as possible so that
VBUCK rises quickly, but large enough to support the bias
current until control is handed off to the secondary and
the duty cycle increases. Once control is handed off, both
the buck supply and the main converter will be operating
in continuous current mode, so their outputs will track.
Another high efficiency option for generating bias is to make
use of an inductor overwinding, as shown in Figure 26.
This supply is created by adding a second winding on the
main output inductor.
During the on-time of the synchronous MOSFET, the VOUT
voltage is scaled and coupled through diode DOW to capacitor COW, so that the resulting bias voltage is:
VOW = VOUT
NL2
– 0.5
NL1
This is similar to the buck supply in that it is highly efficient
and fairly well regulated. However, it is simpler in that it
does not require the use of an additional inductor to generate the bias voltage. Another advantage of this technique
is that the bias voltage always tracks VOUT, so there is
no concern about the bias voltage potentially lagging the
output voltage during start-up. Like the buck bias supply,
the inductor overwinding can be used either stand alone
(as shown in Figure 26) or together with a peak charge
bias supply. Use a schottky diode DOW with a peak surge
current rating of 5A or higher. Capacitor COW should be a
ceramic capacitor with a value of 2.2μF or greater.
NL1
SW
•
NP
DBK
•
LBK
VBUCK
NAUX
DBK
NP
CBK
MAIN
XFMR
MAIN
XFMR
RR1
RR2
VOUT
NS
NL2
DOW
VOW
COUT
COW
LTC3766
LTC3766
RUN
•
•
VAUX
VIN
NDRV
VIN
Q1
NDRV
VCC
CVCC
3766 F25
Figure 25. Using the Buck Bias Supply Standalone
VCC
CVCC
3766 F26
Figure 26. Inductor Overwinding Bias Supply
3766f
40
LTC3766
APPLICATIONS INFORMATION
A useful variant of the inductor over-winding bias supply
is shown in Figure 27, where a discrete transformer TOW
has been used instead of an additional winding on the
main inductor LF . This is often more convenient because
standard parts can readily be used.
in Figures 23 and 24). This enables a low power pass
transistor to be used. See Linear Regulator Operation for
more information on using the REGSD feature.
In the circuit of Figure 27, a second diode DOW2 has been
added to prevent DC bias current from being carried in
the transformer TOW. This transformer can be either a
gate-drive or flyback-style transformer, which are widely
available in a range of turns ratios. Note that transformer
TOW requires only functional isolation and can be physically
very small. This circuit produces a bias voltage given by:
The soft-start ramp time on the LTC3766 is set by placing a
capacitor between the SS pin and GND. This secondary-side
soft-start capacitor only controls the output voltage ramp
after control hand-off has taken place. Consequently, its
effect on the overall output voltage start-up will depend on
the primary to secondary hand-off voltage in the particular
application. Choose a soft-start capacitor using:
VOW = ( VOUT – 0.5)
NL2
– 0.5
NL1
C SS =
During an output overload condition, the voltage generated
by a either a buck supply or inductor overwinding supply will drop as the converter output voltage decreases.
If this happens and there is no peak charge bias supply,
then the LTC3766 will have a UVLO fault that will cause
both the LTC3765 and LTC3766 to shut down and attempt
a restart. If a peak charge supply is used together with a
buck or inductor overwinding supply, then the LTC3766 will
automatically re-energize the high voltage linear regulator
when the VAUX pin gets too low. If continuous operation of
the peak charge and high voltage regulator is not needed,
then the REGSD pin can be used to limit the total time that
this regulator is allowed to operate (shown as an option
LF
SW
VOUT
NL1
NP
MAIN
XFMR
NS
DOW2
•
•
NL2
DOW1
Soft-Start Ramp Time and Control Hand-Off
VOW
COUT
COW
LTC3766
VAUX
VIN
( 5µA ) t SS
(
1.83 0.6 – VFB(HO)
)
where tSS is the soft-start time after control hand-off to
the secondary and VFB(HO) is the voltage on the FB pin at
control hand-off. The total soft-start time will be the sum
of tSS and the open-loop soft-start time prior to control
hand-off set by the LTC3765. Note that during the openloop soft-start time, the output voltage ramp will vary
significantly with load, since the synchronous MOSFET is
not enabled and the converter may operate in discontinuous current mode. If precise control over the soft-start
time is desired, use a secondary-side bias scheme that
provides control hand-off at the lowest possible output
voltage. See above sections on generating secondary-side
bias for details.
Just prior to control hand-off, the LTC3766 rapidly presets the soft-start capacitor so that the internal soft-start
voltage is equal to VFB(HO), ensuring a smooth transition
from primary to secondary control. Due to the dielectric
absorption of the soft-start capacitor, however, the voltage
on the soft-start capacitor may droop somewhat following
the initial preset. This can result in a small step down in the
output voltage ramp after control hand-off, and an associated negative current transient in the output inductor. To
minimize this effect, use a soft-start capacitor with a low
dielectric absorption, such as an NPO ceramic capacitor.
NDRV
VCC
CVCC
Pulse Transformer Selection
3766 F27
Figure 27. Inductor Overwinding Using Standard Parts
The pulse transformer that connects the LTC3766
PT+/PT− outputs to the LTC3765 IN+/IN− inputs functions
3766f
41
LTC3766
APPLICATIONS INFORMATION
as the communication link between the secondary-side
controller and the primary-side gate driver, as shown in
Figure 28. In addition, LTC3765 contains a bridge rectifier that extracts bias power from the pulse transformer,
which it then uses to drive the gates of the primary-side
MOSFETs.
The designs have been coordinated so that the transformer
turns ratio should be set to:
NPT = NLTC3765: NLTC3766 = 2:1
for low voltage mode operation on the LTC3766 (VCC =
7V), and:
NPT = NLTC3765: NLTC3766 = 1.5:1
for high voltage mode operation on the LTC3766 (VCC
= 8.5V). The resulting VCC voltage on the LTC3765 is
approximately:
VCC(3765) = VCC(3766)NPT – 1.3
Using the above turns ratios will provide a primary-side
VCC voltage of approximately 12V for the LTC3765 to
drive the gates of the primary-side MOSFET. Note that the
primary-side VCC voltage provided by the pulse transformer
must also be greater than the LTC3765 UVLO threshold for
proper operation. Care must also be taken not to exceed
the maximum voltage rating on the LTC3765 VCC pin.
The pulse transformer must also have a minimum voltsecond rating as required by the 79% duty cycle signal
on PT+/PT − and the lowest frequency of operation. The
required volt-seconds rating can be calculated from the
minimum frequency as:
Volt-Sec = 0.33 •
VCC
fSW(MIN)
Since the pulse transformer is used for transmitting
PWM information as well as bias power, choose a pulse
1µF
0.1µF
IN+
PT+
100Ω
LTC3765
•
•
LTC3766
220pF
IN–
NLTC3765:NLTC3766
PT–
3766 F28
Figure 28. Pulse Transformer Connection
transformer with a leakage inductance of 1μH or less. This
reduces ringing and distortion of the PWM information
so that a solid communication link is always maintained.
For low voltage (7V) mode on the LTC3766, transformers
that meet the above requirements include the PA2008 from
Pulse Engineering and the DA2320 from Coilcraft. For high
voltage (8.5V) mode on the LTC3766, transformers that
meet the above requirements include the PA3290 from
Pulse Engineering.
The 1µF and 0.1µF capacitors in series with the pulse
transformer of Figure 28 are for blocking and restoring
the DC level of the signal. The 220pF/100Ω RC snubber
shown at the IN+/IN– inputs of the LTC3765 is required
to minimize ringing due to the leakage inductance of the
pulse transformer. The values shown for each of these
four components are appropriate in nearly all LTC3765/
LTC3766 applications.
Voltage Loop Compensation
The voltage loop of the LTC3766 is compensated in much
the same way as a standard buck converter, by placing a
compensation network on the ITH pin. It is important to
note, however, that the speed and stability of the voltage
loop is heavily dependent upon several factors apart from
the design of the ITH compensation. Common PCB layout
errors, for example, often appear as stability problems.
Examples include the distant placement of the input decoupling capacitor, connecting the ITH compensation to a
ground track carrying significant switch current, and routing the FB signal over a long distance such that noise pick
occurs. Refer to the PCB Checklist section for additional
information. Another factor that affects the voltage loop
is the choice of output capacitor. If the value is too low, or
the ESR is too high, then it will not be possible to achieve
optimum loop performance. A third factor that can impair
loop response is the presence of underdamped resonances
in the power stage. Examples include an underdamped
LC input filter or an active clamp capacitor resonating
with the main transformer magnetizing inductance. Refer
to the Input Capacitor/Filter Selection and Active Clamp
Capacitor sections for details on how to properly damp
these LC resonances. Before attempting to optimize the
loop response, carefully consider the above factors,
3766f
42
LTC3766
APPLICATIONS INFORMATION
because no amount of tweaking to the ITH components can
cancel their effect. Also, any theoretical analysis of loop
response only considers first order non-ideal component
behavior. Consequently, it is important that a final stability
check be made with production layout and components.
Stabilizing the voltage loop of the LTC3766 is accomplished
by using the error amp to provide a gain from VOUT to
ITH that compensates for the control to output gain from
ITH to VOUT. The DC component of the ITH to VOUT gain
is approximately:
ADC1 =
2LfSWROUT
1
•
29.3RSENSE 2LfSW +ROUT
for resistor sense mode, and:
2LfSWROUT
NP
ADC1 =
•
2.2K CT NSRSENSE 2LfSW +ROUT
for current transformer mode. Since the LTC3766 utilizes
current mode control, the ITH to VOUT transfer function
can be basically characterized by one pole and one zero.
The pole is given approximately by:
fP =
1
1
+
2πROUTC πfSWLC
and the zero is given by:
fZ =
1
2πRESRC
where RESR is the ESR of the output capacitance C. Note
that the frequency of this zero will vary substantially depending on the type of capacitor chosen.
The LTC3766 uses internal slope compensation to stabilize
the current loop. The amount of slope that is effectively
seen at the current sense (IS+) input is:
be on the order of the down slope of the inductor, which
provides adequate current-loop stability without introducing excessive phase shift at the crossover frequency. For
phase margin calculations, assume that two poles exist
at one-half of the switching frequency. Use of an abnormally high valued inductor will produce additional phase
shift due to slope compensation, thereby forcing a lower
voltage loop crossover frequency to ensure stability. In
order to avoid having either too little or too much slope
compensation, make sure that the inductor satisfies the
following inequalities:
2VOUTRSENSE
3V R
<L < OUT SENSE
3SR @K=2
SR @K=1
for resistor sense mode and:
2VOUTRSENSE K CTNS
K N
3V R
<L < OUT SENSE CT S
3SR @K=2NP
SR @K=1NP
for current transformer mode.
In some cases, the LTC3766 and LTC3765 will be in delay
phase-out mode at low input voltages. This cycle-by-cycle
reduction of the PG and FG turn-on delays has the effect
of reducing the amount of slope compensation by approximately 20% to 40%. Consequently, a higher value
of inductance may be required to maintain current-loop
stability during operation in delay phase-out mode.
The compensation network is typically configured as shown
in Figure 29. The objective of this network is to add DC
gain for excellent load regulation while providing good
phase margin in the voltage loop at the highest possible
crossover frequency. Normally this is achieved by adding
a dominant pole at very low frequency and a zero well before the crossover frequency to remove most of the phase
VOUT
LTC3766
SR = KfSW(26mV)
for RSENSE mode and:
SR = KfSW(0.35V)
for current transformer mode, where K = 1 for duty cycles
less than 50% and K = 2 for duty cycles greater than 50%.
For most applications, this internal slope compensation will
C3
(OPT)
R3
FB
0.6V
–
EA
+
gm = 2.7mS
R2
ITH
R1
C2
C1
3766 F29
Figure 29. ITH Compensation Network
3766f
43
LTC3766
APPLICATIONS INFORMATION
associated with the dominant pole. A high frequency pole
is also added to reduce noise and provide attenuation of
the output voltage ripple. Note that significant gain at the
switching frequency in this compensation network can
cause instabilities.
The network of Figure 29 has a DC gain of:
ADC2 =
R2
g R
R2 +R3 m EA
where REA = 5MΩ is the output resistance of the error
amplifier and gm = 2.7mS is the transconductance. The
low frequency pole and zero are given by:
fP1 =
1
1
and fZ1 =
2πREA C3
2πR1C1
and the high frequency pole is given by:
fP2 =
1
2πR1C2
A good target for the 0dB crossover frequency of the
voltage loop is between one-tenth and one-fifth of the
switching frequency and a phase margin of 60° or more.
Note that the zero produced by the ESR of the output
capacitor helps to stabilize the loop by providing positive
phase shift at frequencies near crossover. This tends to
cancel the negative phase shift associated with the high
frequency current loop poles. However, if the output
capacitor is purely ceramic, the ESR zero may be at too
high a frequency to contribute phase lead to the overall
loop response. In this case, it can be helpful to add an
optional phase lead capacitor C3 as shown in Figure 29,
which generates a zero at a frequency of:
fZ2 =
1
2πR3C3
This zero should be placed near the crossover frequency
to provide additional phase boost.
When optimizing the voltage loop, bear in mind that the
large signal step response may be limited by factors other
than the crossover frequency. At low input voltage, for
example, the maximum duty cycle limit of 79% will impair
the ability of the loop to respond to a sudden increase in
load. Also, in responding to a very large load step (e.g.,
zero to full load) the loop may demand duty cycles that
cause the main transformer to saturate. Hard saturation
is prevented if current in sensed on the primary side or if
the volt-second clamp is used, but the large signal step
response will be limited by the available excess voltseconds in the main transformer.
Setting the SG Reverse Overcurrent
The LTC3766 has been carefully designed to turn off the
SG MOSFET as needed to prevent an overcurrent during
start-up, shutdown and normal operation. Nevertheless,
the LTC3766 also contains a user-adjustable SG reverseovercurrent protection circuit as an added protection
feature. This feature is also useful in special applications
where it may be advantageous to limit the SG reverse
current to a particular value. SG reverse overcurrent is
implemented by monitoring the voltage on the SW pin
when SG is high, and terminating the SG on-time for the
duration of the switching cycle if the SW voltage exceeds
an internal threshold. If the LTC3766 is operating at zero
duty cycle when the SG overcurrent occurs, then the FG
MOSFET is forced on prior to SG turn-off to re-route current to the primary and prevent avalanche from occurring.
If not adjusted, the internal SG overcurrent threshold has
been set high enough so that it should not interfere with
the operation of normal applications. Be careful to make
Kelvin connections from SW and GND to the drain and
source of the SG MOSFET.
In addition to a fixed internal threshold on the SW pin, a
current is sourced from the SW pin so that a resistor can be
added to decrease the overcurrent threshold if desired. Both
the SW pin threshold and the adjust current are changed
depending on whether the LTC3766 is operating in HV or
LV mode, so as to account for the higher on-resistance
of high voltage MOSFETs. In applications where the SW
node plateau voltage is 40V or less (VIN • NS/NP ≤ 40),
a single resistor can be used to set the SG overcurrent
threshold (Figure 30). The resulting overcurrent VDS on
the SG MOSFET is given by:
VOC = VREV – IREVRSW
3766f
44
LTC3766
APPLICATIONS INFORMATION
The SG overcurrent trip should normally be targeted at
twice the maximum VDS of the SG MOSFET during normal
operation. This can be estimated using:
PG
0V
VSW(PK)
RDS(MAX) VOUT 
VOUT NP 
VOC =
1–
• 

fSWL
 VIN(MAX) NS 
SW NODE
where RDS(MAX) is the maximum RDS(ON) of the SG
MOSFET over temperature. This equation allows for twice
the reverse SG current that would normally occur due to
the inductor current ripple at no load. The % error in the
SG overcurrent trip can be estimated using:
2
100  IREVRSW   VREV 
+
∆VOC =
VOC  15   15 
2
If the above error is greater than 30%, then the VOC threshold may need to be increased accordingly. To ensure that
the inductor doesn’t saturate prior to the SG overcurrent
trip, the inductor should have a saturation current such that:
ILSAT >
NS
V
NP IN
0V
3766 F31
Figure 31. Typical SW Node Waveform
The overshoot and ringing on the SW node is due to the
leakage inductance of main transformer, and it is worse
at full load and maximum VIN. The peak SW node voltage
(VSW(PK)) also depends heavily on the gate drive timing
as well as the RC snubber that is typically used on the SW
node. See Delay Resistor Selection: PG Turn-On Transition
and RC Snubber sections for details. Make sure that the
peak SW node voltage does not cause more than 0.2A to
flow into the SW pin:
VOC(MAX)
VSW(PK) – 50V
RDS(MIN)
RSW
< 0.2A
where VOC(MAX) is the maximum overcurrent trip based
on the above error and RDS(MIN) is the minimum RDS(ON)
of the SG MOSFET over temperature.
The above condition is normally satisfied with reasonable
values for RSW and the use of an RC snubber to limit
VSW(PK).
While the circuit of Figure 30 can be used whenever the
SW node plateau voltage is 40V or less, care must be
taken to limit the current into the 50V clamp on the SW
pin due to overshoot and ringing. Figure 31 illustrates a
typical SW node waveform.
In applications where the SW node plateau voltage is
greater than 40V, it is necessary to add a divider as shown
in Figure 32.
VSW
•
VOUT
•
RSW
MAIN
XFMR
+
–
VOC
SG
MOSFET
50V
SG
GND
•
IREV =
LV: 103µA
HV: 42µA
SW
+
+
C
–
LTC3766
VSW
LTC3766
VOUT
•
R1
SGOC
MAIN
XFMR
+
VDS(OC)
–
VREV =
LV: 73mV
HV: 148mV
3766 F30
Figure 30. SG Overcurrent for Low VOUT Applications
R3
SW
50V
R2
SG
MOSFET
IREV =
LV: 103µA
HV: 42µA
+
SG
+
C
–
SGOC
VREV =
LV: 73mV
HV: 148mV
GND
3766 F32
Figure 32. SG Overcurrent for High VOUT Applications
3766f
45
LTC3766
APPLICATIONS INFORMATION
For the circuit of Figure 32, the overcurrent VDS on the
SG MOSFET is given by:

 R1+R2 
 R1+R2  
VOC = VREV 
–IREV R1+R3 

 R2 
 R2  

In addition to producing the desired VOC threshold, there
are three constraints on the selection of resistors R1, R2
and R3 that must be simultaneously met: 1) R1 and R2
must divide the maximum VSW plateau voltage down to
40V or less, 2) the impedance at the SW pin must be kept
as low as possible to reduce the delay in sensing the VSW
voltage, and 3) the power dissipation in R1 and R2 must
be kept reasonably low. The last two constraints can be
met by choosing a maximum power (PR) to be dissipated
in the sum of R1 and R2. Typically, setting PR = 0.25W is a
reasonable compromise that keeps the time constant low
while not greatly impacting converter efficiency.
The selection of R1, R2 and R3 is made using the following procedure:
1. Calculate R1 and R2 based on a maximum power (PR
= 0.25W) and a divider ratio that will produce exactly
40V maximum on the SW pin:
N  VOUT VIN(MAX)  40VOUT
R1= S 
– P
NP 
PR

R
40 • R1
NS
V – 40
NP IN
2. If the value for VOC calculated using R1 and R2 from step
1) is greater than the target VOC value, then choose R3
such that IREV • R3(R1+ R2)/R2 equals the difference
between the calculated and target VOC values.
R2 =
3. If the value for VOC calculated using R1 and R2 from
step 1) is less than the target value, then R3 = 0. Recalculate R1 and R2 based on maximum power (PR =
0.25W) and the desired target VOC value:
R1=
BIREV – AVOC +
For the circuit of Figure 32, the % error in the SG overcurrent
trip can be estimated using:
2
100  IREV (R1+K •R3)   VREV 
+
K
  14 
6
VOC 


2
∆VOC =
where K = (R1 + R2)/R2.
RC Snubbers
Most applications will make use of an RC snubber to
reduce the overshoot and ringing on the SW and SWB
pins, as shown in Figure 33. The snubber capacitor is
chosen to limit the peak voltage overshoot on SW or SWB
by absorbing the energy in the leakage inductance of the
main transformer. The snubber resistor is then chosen to
provide optimum damping so as to minimize ringing. A
larger snubber capacitor reduces the overshoot, but at the
expense of increased power dissipation in the snubber
resistor. In general, the snubber on the SWB node has far
less energy to absorb and can therefore be smaller than
that on the SW node. In some cases, the snubber on SWB
can be eliminated entirely.
The precise values needed for the RC snubbers will depend
upon the specifics of each application, and should be
optimized in the lab. Typical values for CS1 and CS2 range
from 1nF to 4.7nF, and RS1 and RS2 are typically 1Ω to
50Ω. Always use a high quality ceramic (X7R) capacitor
and resistors with a high power rating (1/4W to 1/2W) for
and an RC snubber.
VSW
•
NP
VOUT
CS1
•
NS
CS2
RS2
RS1
MAIN VSWB
XFMR
3766 F33
Figure 33. Using RC Snubbers
( AVOC +BIREV )2 – 4ABVREVIREV
2AIREV
B – AR1
A
where A = PR(NP/NS) and B = VOUTVIN(MAX).
R2 =
46
3766f
LTC3766
APPLICATIONS INFORMATION
Remote Sensing
the input stage of the differential amplifier. If the input
stage is saturated, the LTC3766 forces the VSOUT pin to
0V. In applications where the differential amplifier is not
needed, connect the inputs as shown in either Figure 14b
or Figure 15.
The LTC3766 contains a precision differential amplifier for
use in remote sensing applications. As shown in Figure 14a,
this is useful in eliminating the voltage drops associated
with bussing the power supply output voltage to a remote
load. Be aware that the differential amplifier is powered
from the VIN pin of the LTC3766, and requires 1.5V of
overhead on VIN above the output voltage (VSOUT). If the
voltage on the VIN pin is not adequate to support the VSOUT
voltage, the LTC3766 will generate a fault. This is necessary to avoid a potential overvoltage on the main output
of the converter. In addition, the LTC3766 will generate a
fault if the polarity of the VS+ and VS– pins are reversed
by approximately 0.3V or more.
Self-Starting PolyPhase Applications
Figure 34 shows the PolyPhase connections for the
LTC3765 and LTC3766. On the primary side, the design
of one phase of the LTC3765 can be optimized and then
replicated up to four times by simply tying the SSFLT pins
together. The common SSFLT pins are held low until all
phases have adequate voltage on their VCC supplies and
RUN pins. This prevents any of the phases from switching
until every phase has satisfied the requirements for startup. When start-up conditions have been met, the SSFLT
pin is released and quickly charged until all phases have
In rare applications, it may be useful to raise the common
mode voltage of the VS+ and VS– inputs. When doing so,
always ensure that VS+ < 2(VIN – 2V) to prevent saturating
VIN+
VOUT+
VBIAS
PHASE 1 (MASTER)
VIN NDRV VCC
R1
NDRV
IN+
LTC3765
R2
RUN
VCC
CVCC
FB
PT+
LTC3766
(MASTER)
PT–
SS
•
IN–
ITH
SSFLT
CSSP
•
FS/UV
GND
RFSP
CSSS
FS/SYNC
GND
RFSS
VOUT–
VIN–
VBIAS
PHASE 2 (SLAVE)
VIN NDRV VCC
VIN+
R1
NDRV
IN+
LTC3765
R2
RUN
VCC
CVCC
CSSP
•
•
FS/SYNC
FB
LTC3766
(SLAVE)
PT+
VS–
VS+
PT–
IN–
VSOUT
ITH
SSFLT
FS/UV
GND
RFSP
SS
PHASE
GND
CSSS
VOUT–
VIN–
3766 F34
Figure 34. PolyPhase Connections
3766f
47
LTC3766
APPLICATIONS INFORMATION
switched once. The SSFLT pin currents then decrease to
their nominal values. This ensures that all phases begin their
asynchronous, open-loop start-up at nearly the same time.
On the secondary side, the SS pins from all phases are
interconnected as well. This prevents any one phase from
starting until all phases have adequate bias voltage and
have detected switching on their respective SW pins.
Once this condition is met, the master will advance the
soft-start voltage to match the VOUT of the converter, and
switching begins on the secondary side on all phases. After
a brief lock sequence, all phases will transfer control to
the secondary. The ITH pins are interconnected between
the phases so that current is shared evenly between the
master (which controls the ITH pin to regulate VOUT) and
the slaves.
The LTC3765 SSFLT connection is also used to communicate faults. If one phase has a primary-side fault
(undervoltage, overcurrent, overtemperature, or communication loss), it immediately stops switching and
rapidly pulls SSFLT to 6V. The other phases will detect
that SSFLT is above 5V and will also stop switching. On
the secondary side, the LTC3766s detect that switching
has stopped and also fault, which is communicated to all
phases through the common SS connection. The voltage
on the primary-side SSFLT node then slowly decreases
and a restart begins. Likewise, if a fault originates on the
secondary side on a give phase, this fault is communicated
to the other LTC3766s so that all phases stop switching.
This will cause a communication fault on the primary side
followed by a restart attempt.
regulator pass device will be dissipating more power
and may require a larger and more thermally conductive package. The design and PCB layout are generally
simplified if each phase uses its own linear regulator.
The secondary side follows a similar procedure; however,
there is more differentiation between the master phase
and the slave phases. For the master, choose components
based on the above design equations. Be aware that each
phase should have its own linear regulator pass device to
distribute the power dissipation. Duplicate the components
for each slave, with the following exceptions:
1. Connect all of the SS pins together. Instead of having
multiple capacitors from the SS node to ground, the
capacitors can be consolidated into one capacitor. Note
that only the master charges and discharges the softstart capacitor.
2. Connect the FB pin of the slaves to VCC. This connection
puts the LTC3766 into slave mode. In this mode, the ITH
pin becomes a high impedance input and the SS pin is
only used for fault communication. An LTC3766 slave
will not perform a pre-set of the soft-start capacitor, nor
will it charge or discharge it. A slave can only force the
SS pin high to indicate a fault, and it also monitors the
SS pin to respond to a fault in another phase.
3. For each slave, the integrated unity-gain differential
amplifier is used to sense the voltage on the ITH pin
of the master. Connect the VS+/VS– inputs of each slave
between the ITH and signal GND pins of the master.
Connect the VSOUT pin on each slave to its own ITH pin.
For the LTC3765 on the primary side, choose components
based on a single-phase design. Duplicate the single phase
to the desired number of phases, up to the maximum of
four, with the following modifications:
4. Connect the FS/SYNC pins of each slave to the PT – pin
of the master. The PT – pin of the master contains the
clock signal used to synchronize the slaves and master
together.
1. Connect the SSFLT pins together. Instead of having
multiple capacitors from the SSFLT node to ground,
the capacitors can be consolidated into one capacitor
with a value equal to N • CSSFLT, where N is the number
of phases.
For each slave, set the relative phase using the PHASE pin.
Note that ripple current in the input capacitor is minimized
by operating the controllers out of phase. For a 2-phase
system, set the slave at 180°. For a 3-phase system, set
the slaves at 120° and 240°. For a 4-phase system, set
the slaves at 90°, 180°, and 270°. Refer to Setting the
Switching Frequency and Synchronization for details on
setting the PHASE pin.
2. If desired, the phases can share the linear regulator of
one phase by shorting their VCC and NDRV pins to the
linear regulator output; however, be aware that the linear
3766f
48
LTC3766
APPLICATIONS INFORMATION
Volt-Second Clamp
When used in applications with the LTC3765, direct flux
limit will guarantee that no saturation occurs on the main
transformer. Consequently, there is no need to use a voltsecond clamp in applications that have the direct flux
limit feature. In applications where the LTC3766 is used
standalone, however, the volt-second clamp can be used
as a failsafe to prevent excessive volt-seconds from being
applied to the main transformer during the PWM on-time.
Figure 35 illustrates the use of the volt-second clamp. As
shown in Figure 35, the SW voltage is used to monitor
the voltage applied to the main transformer. During the
PWM on-time, the CVS capacitor is charged by the SW
node through the RVS resistor.
For capacitor CVS, use a 5% or better NPO-type ceramic
capacitor, since accuracy is important. Typically a value
of 1nF is suitable. Likewise, use a 1% resistor for RVS.
In high output voltage applications where the SW node
must be divided down, use the circuit of Figure 36 to set
the volt-second clamp.
SW
•
R1
•
NP
NS
LTC3766
SW
MAIN
XFMR
RVS
R2
VSEC
CVS
3766 F36
SW
•
Figure 36. Volt-Second Clamp in High VOUT Application
•
NP
NS
LTC3766
MAIN
XFMR
SW
RVS
VSEC
CVS
3766 F35
Figure 35. Using the Volt-Second Clamp
The PWM on-time is terminated when a pre-determined
threshold is reached. This will limit the applied volt-second
product to:
(V • S)LIM = 0.605RVSCVS
The above equation is accurate even when the peak voltage on the SW node is relatively low and the charging is
nonlinear, such as in low VOUT applications. This is possible
because the LTC3766 senses the voltage on the SW pin
and adjusts the internal volt-second comparator reference
so that constant volt-seconds are maintained regardless
of the voltage on SW. Consequently, it is important that
the LTC3766 SW pin be connected to the secondary SW
node for proper sensing of this voltage to occur.
The volt-second limit should normally be set approximately
10% above the operational volt-second requirement. To
accomplish this, calculate RVS using:
R VS = 1.10
VOUT
0.605fSW C VS
In this case, assuming RVS >> R1||R2, RVS can be calculated using:
R VS = 1.10
VOUT
 R2 
0.605fSW C VS  R1+R2 
Nonisolated Applications
In addition to being used with the LTC3765 in isolated
applications, the LTC3766 can also be used standalone to
make a nonisolated resonant-reset forward converter as
shown in Figure 37. In this application, the primary-side
MOSFET is driven directly by the PT+ pin, and the MODE
VIN
SW
•
MAIN
XFMR
SWB
FG
SWP
PG
CRST
VOUT
•
LTC3766
PT+
SG
VIN
RVIN
(FOR VIN > 30V)
QP
NDRV
REGSD
MODE
CRSD
VCC
VAUX
5V TO 15V
LV BIAS
SUPPLY
CVAUX
CVIN
CVCC
3766 F37
Figure 37. Nonisolated Resonant-Reset Application
3766f
49
LTC3766
APPLICATIONS INFORMATION
pin is tied to GND through either a 100k or 50k resistor
to select LV or HV operating mode.
The bias for the VIN pin is normally taken directly from
the input voltage of the converter. The LTC3766 contains a
current-limited internal 30V shunt to simplify applications
where VIN > 30V. In such applications, place a current
limiting resistor in series with the VIN pin calculated using:
R VIN =
VIN(MAX) – 30V
3.5mA
Note that at low VIN, there will be a maximum drop across
RVIN equal to (1.2mA) • (RVIN) that is due to the VIN pin
operating current. For proper operation, the voltage on
the VIN pin at low input voltage must be greater than the
rising VCC UVLO by at least the threshold voltage of QP.
Using a MOSFET for QP instead of an NPN eliminates the
base current that would otherwise add to the VIN operating
current. If more margin is needed at low VIN operation, a
Darlington transistor is another option for QP.
To reduce power dissipation in QP, a low voltage bias supply should be fed into the VAUX pin to power the bypass
LDO. This bias supply can be generated off of either the
primary or secondary of the main transformer using an
auxiliary buck or an inductor overwinding supply. During
an output overload condition, the low voltage bias supply
will collapse, causing the high voltage linear regulator
controller to be re-energized. To prevent excessive power
dissipation under this condition, place a capacitor on the
REGSD pin to limit the operating time of the high voltage
linear regulator.
The RUN pin can be used as an undervoltage lockout
(UVLO) on the converter input voltage. Direct RUN/STOP
control can be achieved by using a small NMOS on the
RUN pin as shown in Figure 38.
VIN
R1
RUN
R2
LTC3766
RUN/STOP
CONTROL
GND
3766 F38
Figure 38. RUN/STOP Control for Standalone Applications
The resonant reset capacitor, CRST, serves to generate
a voltage on the SWP node during the off-time of the
primary MOSFET that resets the transformer flux on a
cycle-by-cycle basis. This capacitor is normally sized so
that the SWP voltage exactly resonates back to VIN at the
end of the off time with minimum VIN:
2
1
CRST ≈
LM
 1 
VOUT NP  

 1–
  – CPAR
 πfSW  VIN(MIN) NS  
where LM is the main transformer magnetizing inductance
and CPAR is the total parasitic capacitance on SWP:
N 
CPAR = COSS(PG) +  S 
N 
P
2
(C
OSS(FG) + CSNUB
)
CPAR includes the drain capacitance of both the PG and
FG MOSFETs as well as any snubber capacitance on the
SWB node. In reality, the presence of leakage inductance
makes the SWP node rise much faster than it otherwise
would. As a result, the optimum value for CRST can be 40%
to 60% higher than that calculated by the above equation.
The steady-state peak voltage on the primary and forward
MOSFETs is given by:
VDS(PG) = VIN(MAX) +
VDS(FG) =
VOUT
2fSW
VOUT NP
2fSW NS
1
LM (CRST + CPAR )
1
LM (CRST + CPAR )
If a larger value of CRST is used, the peak voltage stresses
can be decreased, possibly allowing the use of a MOSFET
with lower BVDSS rating. However, with a larger CRST the
SWP voltage at low VIN will not have time to resonate back
down to VIN, thereby increasing the turn-on switching
losses. In practice, some truncation of the low VIN reset
waveform is often tolerated to maximize the overall efficiency of the converter. Note also that the peak MOSFET
voltage stress during transients can be considerably higher,
so allow at least 30% margin above these calculated voltages. The volt-second clamp can be used to reduce the
peak voltage stress due to load transients.
3766f
50
LTC3766
APPLICATIONS INFORMATION
The setting of the gate drive timing for a resonant reset
converter is simplified by the adaptive delays featured in
the LTC3766. When standalone mode is active (100k or
50k on MODE), the FGD pin is ignored, and the associated
dead time between SG turn-off and PG turn-on is controlled
adaptively. In this mode, LTC3766 delays the PG turn-on
until after the SG pin has fallen below approximately 0.5V.
For the PG turn-off transition, the SGD resistor is chosen
to minimize the dead time and also prevent collapse of
the SWP node (i.e., catch the SWP voltage at its peak if
possible). Note that setting the FG turn-off so as to catch
the SWP voltage near its peak will improve efficiency
and allow for the use of a larger resonant reset capacitor,
thereby reducing the peak voltage stresses on the MOSFETs.
Adaptive delay limiting on this edge ensures that SG will
not go high until SW has fallen, so shoot-through is not
a concern.
In nonisolated applications, the inductor current is normally
sensed on the input side of the power transformer, typically using a sense resistor. Note that in this situation, the
values for the sense resistor (RSENSE) and the IPK resistor
(RIPK) should be calculated using the above equations,
but then scaled by a factor of NP/NS. For applications
where the transformer is configured to step up the voltage, however, it may be more efficient to sense current
on the output side of the power transformer. In this case,
be careful to avoid transformer saturation by keeping the
resonant reset capacitor as small as possible and making
use of the volt-second clamp.
Common Mode Noise
Common mode noise arises in isolated converter applications due to the parasitic capacitance between the primary
and secondary windings of the main transformer. When
rapid voltage changes occur on the primary-side MOSFET
drain, this will inject current through the inter-winding
capacitance. This causes the ground reference of the
secondary to suddenly jump with respect to the primary
ground. As a result, current is injected across the inter-
winding capacitance of the pulse transformer back to the
primary, and a resulting common mode voltage can appear
at the IN+ and IN– inputs of the LTC3765. While the LTC3765
has been carefully designed to reject this common mode
voltage, always use a common mode filter capacitor that
is directly connected between the primary and secondary
grounds. This capacitor shunts away the common mode
noise. Typically, a value of 2.2nF is adequate. Use a high
quality ceramic Y capacitor rated for 250VAC operation, or
other voltage rating as needed for the isolation and safety
requirements of the particular application.
Thermal Considerations
When designing a forward converter with an output power
of 50W or more, particular attention must be paid to the
thermal aspects of the design and layout. In general, it is
better to use multiple elements in parallel to spread out the
power dissipation and reduce temperature rise. Beneath all
power MOSFETS, use thermal vias and copper islands on
multiple layers to provide cooling. If excessive temperature
rise occurs, both the LTC3765 and the LTC3766 contain
overtemperature shutdown circuits that will help to prevent
thermal damage. Both overtemperature shutdowns are set
at approximately 165°C rising with 20°C of hysteresis.
PCB Checklist
The LTC3766 requires proper bypassing on the VCC supply
due to its high speed switching (nanoseconds) and large
AC currents (Amperes). Careless component placement
and PCB trace routing may cause excessive ringing and
undershoot/overshoot.
To obtain optimum performance from the LTC3766:
1. Use a low inductance, low impedance ground planes
to reduce any ground drop and stray capacitance.
Remember that the LTC3766 switches at greater than
2A peak currents and the power MOSFETs can carry
50A or more. Any significant ground drop will degrade
signal integrity.
3766f
51
LTC3766
APPLICATIONS INFORMATION
2. Plan the power/ground routing carefully. Know where
the large load switching current is coming from and
going to. Maintain three separate planes if possible:
signal ground (GND pin), power ground (PGND pin) and
power stage ground. The power ground plane should
be connected with a single via to the source of the SG
MOSFET. The signal ground plane should be connected
with a single via to the source of the SG MOSFET for
accurate VDS sensing. If resistor current sensing is used
for IS+ and IS–, be careful to minimize the inductance
of the plane between the sense resistor and the source
of the SG MOSFET.
3. Mount a bypass capacitor as close as possible between
the VCC pin and the power ground plane.
6. If resistor sense mode is used, the IS+ and IS– pins
must be Kelvin connected to the sense resistor. The
traces to the sense resistor must run side-by-side and
be shielded with signal ground on all sides.
7. Keep the switching nodes (SW, PT+, PT –, FG, SG) away
from noise sensitive nodes, especially FB, ITH, IS+ and
IS–.
8. The voltage divider on the output should be connected
as close as possible to the load at the output terminal
of the power supply. The bottom of the voltage divider
should be tied to the signal ground plane. Use the differential amplifier to sense the load voltage and eliminate
distribution voltage drops.
4. Keep the copper traces between the driver output pins
and the MOSFET short and wide.
5. Keep the high current switching path on both the primary
and secondary as short as possible, using multiple layers in parallel to further reduce parasitic inductance.
3766f
52
LTC3766
TYPICAL APPLICATIONS
+VIN
36V TO 72V
•
2.2µF
100V
×3
T1
6:2
L1
1.4µH
•
1nF
100V
FDMS86201
BSC0901NS
33nF
200V
1µF
10V
220µF
6.3V
×2
L1: PULSE PA1392.152
T1: PULSE PA0810
T2: PULSE PA0297
SiR414DP
100nF
200V
10Ω
1/4W
3mΩ
2W
15mΩ 168Ω
1/2W
+VOUT
5V
15A
–VIN
–VOUT
Si3440DV
Si3437DV
(SOT23)
200k
100Ω
2.2nF
250V
330pF
1Ω
365k
I S+ I S–
NDRV PG
15.0k
AG
0.1µF
ISMAG
VCC
220pF
LTC3765
4.7µF
SSFLT
RCORE
33nF
DELAY
10.5k
FG SW SG RUN VIN NDRV VCC FS/SYNC VS+ VS–
4.42k
I S–
IN+
RUN
100Ω
•
T2
2:1
1.0µF
•
100Ω
IN–
FS/UV
SGND PGND
IS
+
FB
PT+
ITH
LTC3766
604Ω
PT–
SS
GND PGND IPK
33nF
NPO
SGD
26.1k
FGD
15k
470pF
MODE VSEC
22.1k
47pF
17.8k
18.2k
14k
3766 TA02
Figure 39. 36V-72V to 5V/15A Active Clamp Isolated Forward Converter
Efficiency vs Load Current
Pre-Biased Start-Up
Load Step
96
VOUT
1V/DIV
VOUT
200mV/DIV
EFFICIENCY (%)
94
IOUT
5A/DIV
92
IL1
5A/DIV
90
88
86
VIN = 48V
200µs/DIV
VPREBIAS = 4.6V
VIN = 36V
VIN = 48V
VIN = 72V
3
5
7
9
11
LOAD CURRENT (A)
13
3766 F39c
VIN = 48V
20µs/DIV
VOUT = 5V
LOAD STEP = 5A TO 15A
3766 F39d
15
3766 F39b
3766f
53
LTC3766
TYPICAL APPLICATIONS
9V-36V to 24V/4.2A Active Clamp Isolated Forward Converter
L1
0.47µH
+VIN
9V TO 36V
• T3
10µF
50V
×3
10µF
50V
•
•
D3
L2
58µH
•
2T
1.2k
1/8W
IS+
T1
24Ω
1W
8T
•
4T
150pF
250V
D4
15Ω
1/8W
1µF
100V
Q1
4mΩ
1W
ES1PD
0.33Ω
1/8W
100Ω
100Ω
L3
680µH
Si7309DN
2.2µF
3.65Ω
2.2nF
100Ω
D1
IS–
100k
2N7002
1µF 1nF
IS+
1nF
AG
VCC
0.1µF
IN+
DELAY
0.1µF
1µF
T2
2.5:2
•
•
NDRV
4.7µF
IS+
VCC
SS
IS–
REGSD MODE
274Ω
FB
10.7k
60.4k
81.6k
1nF
FGD
RUN
SGD
VS+
15k
SSFLT
3.3nF
FS/SYNC VS–
IPK
Q1: BSC057N08NS3
Q2: Si7430DP
Q3: BSC320N20NS3G
T1: PULSE PA0806.004NL
T2: PULSE PA0510NL
T3: ICE CT102-100 (1:100)
7.5k
+VOUT
PHASE
15k
ITH
100µF 35V: SUNCON 35HVH100M
D1-D2: ZHCS506
D3-D6: BAS21
L1: VISHAY IHLP2525CZERR47M01
L2: PULSE PA2729.583
L3: COOPER SD25-681
FCX491A
16.9k
2.2nF
250VAC
SGND PGND
28.7k
VAUX
+VOUT
PT–
33nF
RUN
SG
VIN
PT+
27.4k
147k
SW
FG
100Ω
RCORE FS/UV
+VIN
33nF NPO
D2
IN–
14.3k
Q3
LTC3766
10k
220pF
LTC3765
6.19k
IS+
0.1µF
NDRV
2.8k
1/8W
3.3nF
ISMAG
PG
10µF
50V
+VOUT
24V
100µF 4.2A
35V
–VOUT
–VIN
+VIN
7.5k
1/2W
Q2
D5
220nF
100V
D6
+
68pF
GND
VSEC
PGND
2.94k
3766 TA03a
3766f
54
LTC3766
TYPICAL APPLICATIONS
18V-75V to 12V/12.5A Active Clamp Isolated Forward Converter
L1
1.8µH
+VIN
18V TO 75V
2.2µF
100V
• T3
2.2µF
100V
×3
•
•
D3
L2
11µH
•
4T
1.2k
1/8W
IS+
T1
51Ω
1/2W
4T
1.82k
1/4W
ES1PD
Q2
Q1
ES1PD
0.75Ω
1/8W
5.11Ω
1/8W
1nF
100Ω
IS–
D1
200k
FDC2512
1µF 1nF
IS+
1nF
NDRV
AG
VCC
0.1µF
IN+
DELAY
33nF NPO
•
SS
IS–
PT+
•
604Ω
FB
11.5k
PT–
27.4k
16.9k
2.2nF
250VAC
33nF
FGD
RUN
SGD
VS+
15k
SSFLT
60.4k
SGND PGND
FS/SYNC VS–
REGSD
IPK
PHASE
ITH
VSEC
75k
10nF
10nF
Q2: BSC057N08NS3
Q3: BSC190N15NS3
T1: PULSE PA0801
T2: PULSE PA0510NL
T3: ICE CT102-100 (1:100)
10k
GND
47pF
PGND
1.82k
+VOUT
1.87k
3766 TA04a
Efficiency vs Load Current
96
VIN = 24V
94
EFFICIENCY (%)
68µF 16V: SANYO 16TQC68M
D1-D2: ZHCS506
D3: BAS21
L1: VISHAY IHLP4040DZER1R8M11
L2: PULSE PA2729.113NL
Q1: FDMS86201
VCC
100Ω
61.9k
4.99k
FMMT491
MODE
IN–
RCORE FS/UV
RUN
+VOUT
10µF
IS+
1µF
T2
2.5:2
220pF
13.3k
+VIN
LTC3766
10k
D2
SG
VIN
NDRV
3.3nF
0.1µF
LTC3767
6.19k
IS+
ISMAG
PG
68µF
16V
×2
–VOUT
SW
FG
100Ω
+
1nF
200V
Q3
IRF6217
–VIN
+VIN
22µF
16V
×2
75Ω
1/8W
0.22µF
250V
33nF
200V
100Ω
33k
1/2W
1.82k
1/4W
100pF
200V
4mΩ
1W
+VOUT
12V
12.5A
VIN = 48V
92
90
88
86
0
3
9
6
LOAD CURRENT (A)
12
15
3766 TA04b
3766f
55
LTC3766
TYPICAL APPLICATIONS
36V-60V to 32V at 10A 320W Isolated P/A Power Supply
L1
1.8µH
+VIN
36V TO 60V
• T3
2.2µF
100V
×3
2.2µF
100V
•
•
D6
L2
10µH
•
4T
330Ω
1/8W
IS+
T1
•
2T
D4
165Ω
1/8W
0.22µF
250V
33nF
200V
4mΩ
1W
ES1PD
0.56Ω
1/8W
100Ω
100Ω
4.7µF
I +
4.22Ω S
1.5nF
IS–
D1
200k
FDC2512
1µF 1nF
IS+
VCC
0.1µF
IN+
DELAY
0.1µF
•
RUN
IS–
1k
FGD
RUN
SGD
VS+
15.0k
60.4k
2.2nF
IPK
8.66k
+VOUT
PHASE
47k
ITH
GND
100pF
Q1-Q6: BSC190N15NS3
T1: PULSE PA0905NL
T2: PULSE PA0510NL
T3: ICE CT102-100 (1:100)
1.54M
FS/SYNC VS–
33.2k
10nF
31.6k
205k
SSFLT
56µF 50V: SUNCON 50HV56M
D1-D2: ZHCS506
D3-D6: BAS21
L1: VISHAY IHLP6060DZER1R8M11
L2: COILCRAFT SER2814H-103
L3: COOPER SD25-681
604Ω
FB
27.4k
2.2nF
250VAC
SGND PGND
2.43k
SS
330pF
27.4k
66.5k
VCC
PT–
33nF
FCX491A
1µF
IS+
100Ω
RCORE FS/UV
+VIN
NDRV
PT+
IN–
8.25k
VAUX
REGSD MODE
1µF
T2
2.5:2
•
220pF
LTC3765
13k
33nF NPO
D2
0.1µF
AG
SG
VIN
0.1µF
50V
3.9V +VOUT
LTC3766
10k
1nF
NDRV
SW
FG
3.3nF
ISMAG
PG
Q5
Q6
L3
680µH
IRF6217
100Ω
+VOUT
32V
56µF 10A
50V
×2
–VOUT
–VIN
+VIN
+
2.94k
Q3
Q4
D5
Q1
Q2
8.66k
1/8W
D3
6T
4.7µF
50V
×4
VSEC
PGND
3.09k
3766 TA05a
Efficiency vs Load Current
96
VIN = 48V
EFFICIENCY (%)
95
94
93
92
91
2
4
6
LOAD CURRENT (A)
8
10
3766 TA05b
3766f
56
LTC3766
TYPICAL APPLICATIONS
36V-60V to 14V at 25A 350W Isolated Bus Converter
L1
1.8µH
+VIN
36V TO 60V
• T3
2.2µF
100V
×3
2.2µF
100V
•
•
T1
L2
4.7µH
•
5T
1.00k
1/8W
3T
IS+
165Ω
1/8W
0.22µF
250V
33nF
200V
Q1
Q2
Q3
4mΩ
1W
ES1PD
0.68Ω
1/8W
100Ω
100Ω
Q4
Q5
–VOUT
SW
FG
1/8W
SG
VIN
NDRV
–VIN
D1
200k
FDC2512
1µF 1nF
IS–
IS+
10k
1nF
NDRV
AG
VCC
0.1µF
IN+
LTC3767
DELAY
0.1µF
RCORE FS/UV
IS–
MODE
604Ω
FB
13.7k
2.2nF
250VAC
33nF
PT–
RUN
FGD
VS+
SGD
VS–
27.4k
15.0k
SSFLT
FS/SYNC REGSD
150k
10nF
4.7nF
IPK
PHASE
10k
ITH
Q1-Q3: BSC190N15NS3
Q4-Q7: BSC057N08NS3
T1: PULSE PA0956NL
T2: PULSE PA0510NL
T3: ICE CT102-100 (1:100)
VSEC
GND
100pF
PGND
3766 TA06a
Efficiency vs Load Current
96
VIN = 48V
95
EFFICIENCY (%)
68µF 16V: SANYO 16TQC68M
D1-D2: ZHCS506
D5: BAS21
L1: VISHAY IHLP4040DZER1R8M11
L2: COILCRAFT SER2814L-472KL
+VOUT
60.4k
SGND PGND
2.43k
SS
100Ω
27.4k
RUN
VCC
PT+
•
IN–
66.5k
FCX491A
4.7µF
IS+
1µF
T2
2.5:2
•
220pF
11k
+VIN
33nF NPO
D2
ISMAG
PG
14k
LTC3766
3.3nF
100Ω
+VOUT
D5
4.22Ω
1nF
+VIN
+VOUT
14V
68µF 25A
16V
×4
10nF
200V
Q6
Q7
+
432Ω IS
IRF6217
5.1k
1W
ES1PD
22µF +
16V
×4
94
93
92
91
0
5
10
15
20
LOAD CURRENT (A)
25
30
3766 TA06b
3766f
57
LTC3766
PACKAGE DESCRIPTION
GN Package
28-Lead Plastic SSOP (Narrow .150 Inch)
(Reference LTC DWG # 05-08-1641)
.386 – .393*
(9.804 – 9.982)
.045 .005
28 27 26 25 24 23 22 21 20 19 18 17 1615
.254 MIN
.033
(0.838)
REF
.150 – .165
.229 – .244
(5.817 – 6.198)
.0165 .0015
.150 – .157**
(3.810 – 3.988)
.0250 BSC
1
RECOMMENDED SOLDER PAD LAYOUT
.015 .004
¥ 45∞
(0.38 0.10)
.0075 – .0098
(0.19 – 0.25)
2 3
4
5 6
7
8
.0532 – .0688
(1.35 – 1.75)
9 10 11 12 13 14
.004 – .0098
(0.102 – 0.249)
0 – 8 TYP
.016 – .050
(0.406 – 1.270)
NOTE:
1. CONTROLLING DIMENSION: INCHES
INCHES
2. DIMENSIONS ARE IN
(MILLIMETERS)
.008 – .012
(0.203 – 0.305)
TYP
.0250
(0.635)
BSC
GN28 (SSOP) 0204
3. DRAWING NOT TO SCALE
*DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
**DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
3766f
58
LTC3766
PACKAGE DESCRIPTION
UFD Package
28-Lead Plastic QFN (4mm × 5mm)
(Reference LTC DWG # 05-08-1712 Rev B)
0.70 ±0.05
4.50 ± 0.05
3.10 ± 0.05
2.50 REF
2.65 ± 0.05
3.65 ± 0.05
PACKAGE OUTLINE
0.25 ±0.05
0.50 BSC
3.50 REF
4.10 ± 0.05
5.50 ± 0.05
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
4.00 ± 0.10
(2 SIDES)
0.75 ± 0.05
PIN 1 NOTCH
R = 0.20 OR 0.35
× 45° CHAMFER
2.50 REF
R = 0.115
TYP
R = 0.05
TYP
27
28
0.40 ± 0.10
PIN 1
TOP MARK
(NOTE 6)
1
2
5.00 ± 0.10
(2 SIDES)
3.50 REF
3.65 ± 0.10
2.65 ± 0.10
(UFD28) QFN 0506 REV B
0.25 ± 0.05
0.200 REF
0.50 BSC
0.00 – 0.05
BOTTOM VIEW—EXPOSED PAD
NOTE:
1. DRAWING PROPOSED TO BE MADE A JEDEC PACKAGE OUTLINE MO-220 VARIATION (WXXX-X).
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
3766f
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
59
LTC3766
TYPICAL APPLICATION
36V-72V to 3.3V/20A Nonisolated Resonant-Reset Forward Converter
L1
0.85µH
VIN
36V TO 72V
VOUT
3.3V
20A
T1
•
L1: PULSE PA1294.910NL
L2: COOPER SD25-102
T1: PULSE PA0810.006NL
2.2µF
100V
×3
• 2T
12T
1.5nF
200V
NPO
BSC320N20NS3
BAT54
15mΩ
1W
100Ω
100Ω
6T
100µF +
6.3V
×2
•
220µF
6.3V
BSC0901NS
L2
1mH
1µF
1nF
50V
2.4Ω
1/4W
BSC0901NS
BAT54
330pF
210k
16.5k
1/4W
IS–
IS+ PT+
VAUX
FG
VS–
VIN
Si2328DS
(SOT23)
NDRV
0.1µF
50V
1nF
1µF
16V
VCC
FB
FS/SYNC
ITH
7.87k
REGSD
33nF
GND PGND VSEC SGD
0.22µF
+SENSE
–SENSE
8.62k
VSOUT
LTC3766
SS
100Ω
SW SG
VS+
RUN
IPK
MODE
16.2k
49.9k
20.5k
100Ω
2.2nF
47pF
6.2k
1.82k
3766 TA07
Efficiency vs Load Current
Start-Up
Load Step
94
VIN = 36V
EFFICIENCY (%)
92
VIN = 48V
VIN = 72V
90
VOUT
200mV/DIV
IL
5A/DIV
IOUT
5A/DIV
VIN = 48V
VOUT = 3.3V
RLOAD = 0.22Ω
88
86
VOUT
1V/DIV
6
8
16
10
12
14
LOAD CURRENT (A)
18
1ms/DIV
3766 TA07c
20µs/DIV
VIN = 48V
VOUT = 3.3V
LOAD STEP = 10A TO 20A
3766 TA07d
20
3766 TA07b
RELATED PARTS
PART NUMBER
LTC3765
DESCRIPTION
Active Clamp Forward Controller and Gate Driver
LTC3705/LTC3726
2-Switch Synchronous Forward No Opto Isolated
Controller Chip Set
Isolated Synchronous Forward Active Clamp
LT®1952/LT1952-1
Contollers
LTC3723/LTC3723-2
Synchronous Push-Pull and Full-Bridge
Controllers
LTC3721-1/LTC3721-2 Nonsynchronous Push-Pull and Full-Bridge
Controllers
LTC3722/LTC3722-2
Synchronous Isolated Full-Bridge Controllers
COMMENTS
Direct Flux Limit, Supports Self-Starting Secondary Forward Control, Works
in Conjuction with LTC3766
Self-Starting Architecture Eliminates Need for Bias Voltage on Primary Side
Suitable for Medium Power 12V, 24V and 48V Input Applications, Adjustable
Synchronous Rectification Timing
High Efficiency with On-Chip MOSFET Drivers, Adjustable Synchronous
Rectification Timing
Minimizes External Components, On-Chip MOSFET Drivers
Adaptive or Manual Delay Control for Zero Voltage Switching, Adjustable
Synchronous Rectification Timing
3766f
60 Linear Technology Corporation
LT 0711 • PRINTED IN USA
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 ● FAX: (408) 434-0507
●
www.linear.com
 LINEAR TECHNOLOGY CORPORATION 2011
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