Download datasheet for ESDA19SC6 by STMicroelectronics

Download datasheet for ESDA19SC6 by STMicroelectronics
ESDAxxSCx
Quad Transil™ array for ESD protection
Features
■
4 unidirectional Transil Functions
■
Low leakage current: IR max. < 20 µA at VRM
■
400 W peak pulse power (8/20 µs)
Benefits
■
High ESD protection level: up to 25 kV
■
High integration
■
Suitable for high density boards
Complies with the following standards:
■
■
SOT23-5L (SC-59)
ESDAxxSC5
Figure 1.
IEC 61000-4-2 level 4:
– 15 kV (air discharge)
– 8 kV (contact discharge)
SOT23-6L (SC-59)
ESDAxxSC6
ESDAxxSC5 functional diagram
1
5
2
MIL STD 883E- Method 3015-7: class3B
– human body model
3
4
Applications
Where transient overvoltage protection in ESD
sensitive equipment is required, such as :
■
Computers
■
Printers
■
Communication systems
■
Cellular phone handsets and accessories
■
Other telephone set
■
Set top boxes
Figure 2.
ESDAxxSC6 functional diagram
1
6
2
5
3
4
Description
The ESDAxxSC5 and ESDAxxSC6 are monolithic
voltage suppressors designed to protect
components which are connected to data and
transmission lines against ESD.
They clamp the voltage just above the logic level
supply for positive transients, and to a diode drop
below ground for negative transient.
November 2007
TM: Transil is a trademark of STMicroelectronics.
Rev 9
1/11
www.st.com
11
Characteristics
ESDAxxSCx
1
Characteristics
Table 1.
Absolute ratings (Tamb = 25 °C)
Symbol
VPP
PPP
Tj
Parameter
ESD discharge
Peak pulse power (8/20µs)
Value
Unit
MIL STD 883E - Method 3015-7
IEC61000-4-2 air discharge
IEC61000-4-2 contact discharge
25
kV
ESDA5V3SCx
ESDA6V1SCx
500
400
W
ESDA14V2SCx
ESDA17SC6
ESDA19SC6
ESDA25SC6
300
W
150
°C
-55 to +150
°C
260
°C
-40 to +125
°C
Junction temperature
Tstg
Storage temperature range
TL
Maximum lead temperature for soldering during 10 s at 5mm for case
Top
Operating temperature range
Table 2.
Electrical characteristics - definitions (Tamb = 25 °C)
Symbol
Parameter
I
VRM
Stand-off voltage
VBR
Breakdown voltage
VCL
Clamping voltage
IRM
Leakage current @ VRM
IPP
Peak pulse current
αT
Voltage temperature coefficient
C
Capacitance
Rd
Dynamic resistance
VF
Forward voltage dropt
2/11
IF
VBR
V RM
VCL
VF
I RM
Rd
I PP
V
ESDAxxSCx
Table 3.
Characteristics
Electrical characteristics - values (Tamb = 25 °C)
VBR @ IR
Rd
αT
typ.(1)
max.(2)
IRM @ VRM
[email protected] IF
typ.
min.
max.
V
V
mA
µA
V
mΩ
10-4/C
pF
V
mA
ESDA5V3SC5
ESDA5V3SC6
5.3
5.9
1
2
3
230
5
280
1.25
200
ESDA6V1SC5
ESDA6V1SC6
6.1
7.2
1
20
5.25
350
6
190
1.25
200
ESDA14V2SC5
ESDA14V2SC6
14.2
15.8
1
5
12
650
10
100
1.25
200
ESDA17SC6
ESDA19SC6
17
19
19
21
1
1
0.075
0.1
14
15
700
800
10
8.5
85
80
1.2
1.2
10
10
ESDA25SC6
25
30
1
1
24
1000
10
60
1.2
10
Order codes
max.
C
0 V bias
max.
1. Square pulse, Ipp = 15 A, tp=2.5 µs.
2. Δ VBR = αT* (Tamb -25 °C) * VBR (25 °C)
Figure 3.
Peak power dissipation versus
initial junction temperature
Figure 4.
Peak pulse power versus
exponential pulse duration
(Tj initial = 25 °C)
PPP(W)
PPP[Tj initial] / PPP[Tj initial=25°C]
5000
1.1
1.0
0.9
ESDA5V3SC5/SC6
&
ESDA6V1SC5/SC6
0.8
0.7
1000
0.6
0.5
ESDA14V2SC5/SC6
ESDA17SC6
ESDA19SC6
ESDA25SC6
0.4
0.3
0.2
0.1
tp(µs)
Tj initial (°C)
100
0.0
0
25
Figure 5.
50
75
100
125
1
150
Clamping voltage versus peak
pulse current (Tj initial = 25 °C).
Rectangular waveform tp = 2.5 µs
Figure 6.
IPP(A)
10
100
Capacitance versus reverse applied
voltage (typical values)
C(pF)
50.0
500
F=1MHz
VOSC=30mVRMS
ESDA25SC6
ESDA19SC6
10.0
ESDA17SC6
ESDA5V3SC5/SC6
ESDA14V2SC5/SC6
100
ESDA6V1SC5/SC6
ESDA6V1SC5/SC6
1.0
ESDA5V3SC5/SC6
ESDA14V2SC5/SC6
ESDA17SC6
ESDA19SC6
tp=2.5µs
VCL(V)
0.1
0
5
10
15
20
25
30
35
40
45
50
55
60
65
70
75
80
ESDA25SC6
VR(V)
10
1
2
5
10
20
50
3/11
Application information
Figure 7.
ESDAxxSCx
Relative variation of leakage
current versus junction
temperature (typical values)
Figure 8.
IR[Tj] / IR[Tj=25°C]
5.00
500
IFM(A)
ESDA5V3SC5/SC6
ESDA17SC6
&
ESDA19SC6
ESDA14V2SC5/SC6
&
ESDA6V1SC5/SC6
ESDA14V2SC5/SC6
&
ESDA6V1SC5/SC6
100
Peak forward voltage drop versus
peak forward current
(typical values)
ESDA19SC6
ESDA17SC6
1.00
ESDA25SC6
ESDA25SC6
0.10
10
Tj(°C)
Tj = 25°C
ESDA5V3SC5/SC6
VFM(V)
0.01
1
25
50
75
100
0.5
125
1.0
1.5
2.0
2.5
3.0
3.5
2
Application information
2.1
Calculation of the clamping voltage use of the dynamic
resistance
4.0
The ESDA family has been designed to clamp fast spikes like ESD. Generally the PCB
designers need to calculate easily the clamping voltage VCL. This is why we give the
dynamic resistance in addition to the classical parameters. The voltage across the
protection cell can be calculated with the following formula:
VCL = VBR + Rd IPP
Where IPP is the peak current through the ESDA cell.
As the value of the dynamic resistance remains stable for a surge duration lower than 20 µs,
the 2.5 µs rectangular surge is well adapted. In addition both rise and fall times are
optimized to avoid any parasitic phenomenon during the measurement of Rd.
2.2
Dynamic resistance measurement
The short duration of the ESD has led us to prefer a more adapted test wave, as below
defined, to the classical 8/20µs and 10/1000 µs surges.
Figure 9.
2.5 µs duration measurement wave
I
Ipp
2µs
tp = 2.5µs
4/11
t
ESDAxxSCx
2.3
Application information
ESD protection with ESDAxxSCx
Electrostatic discharge (ESD) is a major cause of failure in electronic systems.
Transient Voltage Suppressors (TVS) are an ideal choice for ESD protection. They are
capable of clamping the incoming transient overvoltage to a low enough level such that
damage to the protected semiconductor is prevented.
Surface mount TVS arrays offer the best choice for minimal lead inductance.
They serve as parallel protection elements, connected between the signal line and ground.
As the transient rises above the operating voltage of the device, the TVS array becomes a
low impedance path diverting the transient current to ground.
Figure 10. ESDAxxSCx array protection against ESD
I/ O LINES
ESD
sensitive
device
GND
ESDAxxxSC6 (1connection to GND for ESDAxxSC5)
The ESDAxxSCx array is the ideal board level protection of ESD sensitive semiconductor
components.
The tiny SOT23-5L and SOT23-6L packages allow design flexibility in the high density
boards where the space saving is at a premium. This enables to shorten the routing and
contributes to hardening against ESD.
2.4
Advice for optimizing circuit board layout
Circuit board layout is a critical design step in the suppression of ESD induced transients.
The following guidelines are recommended:
●
The ESDAxxSC5/6 should be placed as close as possible to the input terminals or
connectors.
●
The path length between the ESD suppressor and the protected line should be
minimized
●
All conductive loops, including power and ground loops should be minimized
●
The ESD transient return path to ground should be kept as short as possible
●
Ground planes should be used whenever possible
5/11
Technical information
ESDAxxSCx
3
Technical information
3.1
ESD protection
The ESDA19SC6 is particularly optimized to perform ESD protection. ESD protection is
achieved by clamping the unwanted overvoltage. The clamping voltage is given by the
following formula :
VCL = VBR + Rd . IPP
As shown in Figure 11., the ESD strikes are clamped by the transient voltage suppressor.
Figure 11. ESD clamping behavior (example)
Rg
Rd
Voutput
Vg
Rload
VBR
ESD Surge
ESDA19SC6
Device
to be
protected
To have a good approximation of the remaining voltages at both VI/O side, we provide the
typical dynamical resistance value Rd. By taking into account the following hypothesis :
Rg > Rd and Rload > Rd
we have:
Vg
V output = V BR + R d × ------Rg
The results of the calculation done for Vg = 8 kV, Rg = 330 Ω (IEC61000-4-2 standard),
VBR = 19 V (typ.) and Rd = 0.80 Ω (typ.) give:
Vouput = 38.4 V
This confirms the very low remaining voltage across the device to be protected. It is also
important to note that in this approximation the parasitic inductance effect was not taken into
account. This could be a few tenths of volts during a few nanoseconds at the output side.
6/11
ESDAxxSCx
4
Ordering information
Ordering information
Figure 12. Ordering information scheme
ESDA
xx
SCx
ESD Array
Breakdown Voltage (min)
5V3 = 5.3 Volt
6V1 = 6.1 Volt
14V2 = 14.2 Volt
17 = 17 Volt
19 = 19 Volt
25 = 25 Volt
Package
SC5 = SOT23-5L
SC6 = SOT23-6L
7/11
Package information
5
ESDAxxSCx
Package information
Epoxy meets UL94, V0 standard
●
In order to meet environmental requirements, ST (also) offers these devices in ECOPACK®
packages. ECOPACK® packages are Lead-free. The category of second level Interconnect
is marked on the inner box label, in compliance with JEDEC Standard JESD97. The
maximum ratings related to soldering conditions are also marked on the inner box label.
ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com.
Table 4.
SOT23-5L dimensions
Dimensions
Ref.
Millimeters
Inches
A
Min. Typ. Max.
E
e
B
D
e
A2
Typ.
Max.
A
0.90
A1
0
A2
0.90
1.30 0.035
0.051
b
0.35
0.50 0.014
0.020
c
0.09
0.20 0.004
0.008
D
2.80
3.05
0.11
0.118
E
1.50
1.75 0.059
0.069
e
c
Min.
1.45 0.035
0.057
0.10
0.004
0
0.95
0.037
A1
θ
L
H
2.60
3.00 0.102
0.118
L
0.10
0.60 0.004
0.024
M
0°
H
10°
Figure 13. SOT23-5L footprint (dimensions in mm)
0.60
1.20
0.95
3.50
8/11
2.30
1.10
0°
10°
ESDAxxSCx
Package information
Table 5.
SOT23-6L dimensions
Dimensions
Ref.
Millimeters
Inches
A
Min. Typ. Max.
E
e
b
D
e
A2
Typ.
Max.
A
0.90
A1
0
A2
0.90
1.30 0.035
0.051
b
0.35
0.50 0.014
0.020
c
0.09
0.20 0.004
0.008
D
2.80
3.05
0.11
0.118
E
1.50
1.75 0.059
0.069
e
c
Min.
1.45 0.035
0.057
0.10
0.004
0
0.95
0.037
A1
θ
L
H
2.60
3.00 0.102
0.118
L
0.10
0.60 0.004
0.024
θ
0°
H
10°
0°
10°
Figure 14. SOT23-6L footprint (dimensions in mm)
0.60
1.20
0.95
3.50
2.30
1.10
9/11
Ordering information
6
ESDAxxSCx
Ordering information
Table 6.
Ordering information
Order codes
7
ESDA5V3SC5
EC53
ESDA6V1SC5
EC61
ESDA14V2SC5
EC15
ESDA5V3SC6
ES53
ESDA6V1SC6
ES61
ESDA14V2SC6
ES15
ESDA17SC6
ES17
ESDA19SC6
ES19
ESDA25SC6
ES25
Package
Weight
Base qty
Delivery mode
16.7 mg
3000
Tape and reel
SOT23-5L
SOT23-6L
Revision history
Table 7.
10/11
Marking
Document revision history
Date
Revision
Description of changes
Nov-2003
7F
Previous issue.
4-Nov-2004
8
SOT23-6L package dimensions change for reference “D” from
3.0 millimeters (0.118 inches) to 3.05 millimeters (0.120
inches).
22-Nov-2007
9
Reformatted to current standard. Units for IRM MAX inTable 3
corrected to µA. Ordering information scheme expanded to
cover all devices. Package information for SOT23-5L updated.
ESDAxxSCx
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11/11
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