Download datasheet for ESDA6V1M6 by STMicroelectronics

Download datasheet for ESDA6V1M6 by STMicroelectronics
ESDA6V1M6, ESDA6V1-5M6
4- and 5-line Transil™ arrays for ESD protection
Features
■
High ESD protection level
■
High integration
■
Suitable for high density boards
■
4 unidirectional Transil diodes
(ESDA6V1M6)
■
5 unidirectional Transil diodes
(ESDA6V1-5M6)
■
Breakdown Voltage VBR = 6.1 V min
■
High peak power dissipation:
100 Watts 8/20 µs
■
Low leakage current < 500 nA
■
Low diode capacitance (70 pF typ at 0 V)
■
Very small PCB area: 1.45 mm²
■
500 microns pitch
■
Lead-free package
Micro QFN package
Figure 1.
ESDA6V1M6
■
I/O1 1
6 I/O5
GND 2
5 GND
I/O2
4 I/O3
3
ESDA6V1-5M6
Complies with the following standards:
■
Functional diagram
IEC 61000-4-2
– 15 kV (air discharge)
– 8 kV (contact discharge)
I/O1 1
6 I/O5
GND 2
5 I/O4
I/O2
4 I/O3
3
MIL STD 883G- Method 3015-7: class 3B
– > 8 kV (human body model)
Description
Applications
Where transient overvoltage protection in ESD
sensitive equipment is required, such as:
■
Computers
■
Printers
■
Communication systems
■
Cellular phone handsets and accessories
■
Video equipment
The ESDA6V1xxM6 are monolithic arrays
designed to protect up to 4 or 5 lines against ESD
transients.
The device is ideal for applications where both
reduced print circuit board space and power
absorption capability are required.
TM: Transil is a trademark of STMicroelectronics
February 2008
Rev 4
1/11
www.st.com
11
Characteristics
1
ESDA6V1M6, ESDA6V1-5M6
Characteristics
Table 1.
Absolute maximum ratings (Tamb = 25 °C)
Symbol
Parameter
Value
Unit
VPP
ESD IEC 61000-4-2, air discharge
ESD IEC 61000-4-2, contact discharge
MIL STD 883G- Method 3015-7: class 3B, (human body model)
±15
±11
25
kV
PPP
Peak pulse power dissipation (8/20 µs)(1)
100
W
Ipp
Repetitive peak pulse current typical value (8/20 µs)
8
A
Tj
Junction temperature
125
°C
-55 to +150
°C
260
°C
-40 to +125
°C
Tstg
TL
TOP
Tj initial = Tamb
Storage temperature range
Maximum lead temperature for soldering during 10 s at 5 mm for
case
Operating temperature range
1. For a surge greater than the maximum values, the diode will fail in short-circuit.
Table 2.
Electrical characteristics (Tamb = 25 °C)
Symbol
Parameter
VRM
Stand-off voltage
VBR
Breakdown voltage
VCL
Clamping voltage
I
IF
VF
VCL VBR VRM
IRM
Leakage current @ VRM
IPP
Peak pulse current
αT
Voltage temperature coefficient
VF
Forward voltage drop
V
I RM
IR
Slope= 1/ Rd
Symbol
Test Condition
Min
Typ
Max
Unit
7.2
V
VBR
IR = 1 mA
IRM
VRM = 3 V
500
nA
VF
IF = 10 mA
1
V
Rd
αT(1)
C
6.1
1
IR = 1 mA
VR =0 V DC, F = 1 MHz, Vosc = 30 mVRMS
1. ΔVBR = αT * (Tamb - 25 °C) * VBR (25 °C)
2/11
I PP
Ω
5
70
10-4/ °C
pF
ESDA6V1M6, ESDA6V1-5M6
Figure 2.
Characteristics
Relative variation of peak pulse
power versus initial junction
temperature
Figure 3.
Peak pulse power versus
exponential pulse duration
PP P(W )
PPP [Tj i n iti al ] /PPP [Tj i n iti al = 2 5 °C]
1000
1.1
Tj initial = 25°C
1.0
0.9
0.8
0.7
0.6
100
0.5
0.4
0.3
0.2
0.1
t P (µs)
T j (°C)
10
0.0
0
25
Figure 4.
50
75
100
125
1
150
Clamping voltage versus peak
pulse current (typical values,
8/20 µs waveform)
10
Figure 5.
100
Forward voltage drop versus peak
forward current (typical values)
IF M(A)
IP P(A)
100.0
1.E+00
8/20µs
Tj initial =25°C
10.0
1.E-01
Tj =125°C
Tj =25°C
1.0
1.E-02
V CL (V)
V FM (V)
0.1
1.E-03
0
10
Figure 6.
20
30
40
50
60
70
Junction capacitance versus
reverse voltage applied (typical
values)
0.0
0.2
Figure 7.
C (p F )
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
Relative variation of leakage
current versus junction
temperature (typical values)
IR [Tj] / IR [Tj= 2 5 °C ]
80
100
F=1MHz
VOSC=30mVRMS
Tj=25°C
70
60
VR =3V
50
40
10
30
20
10
V R (V)
T j (°C)
1
0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
25
50
75
100
125
3/11
Ordering information scheme
Figure 8.
ESDA6V1M6, ESDA6V1-5M6
S21 attenuation measurement
results of each channel
Figure 9.
dB
dB
0.00
0.00
-10.00
-30.00
-20.00
-60.00
-30.00
-90.00
f/Hz
f/Hz
-40.00
100.0k
1.0M
10.0M
100.0M
1.0G
Figure 10. ESD response to IEC 6100-4-2
(+15 kV air discharge) on each
channel
2
Analog crosstalk measurements
between channels
-120.00
100.0k
1.0M
10.0M
100.0M
Figure 11. ESD response to IEC 6100-4-2
(-15 kV air discharge) on each
channel
Ordering information scheme
Figure 12. Ordering information scheme
ESDA
ESD array
Breakdown voltage
6V1 = 6.1 Volts min
Number of lines
blank = 4 line
-5 = 5 line protection
Package
M6 = Micro QFN 6 leads
4/11
1.0G
6V1
xx
M6
ESDA6V1M6, ESDA6V1-5M6
3
Package information
Package information
●
Epoxy meets UL94, V0
In order to meet environmental requirements, ST offers these devices in ECOPACK®
packages. These packages have a lead-free second level interconnect. The category of
second level interconnect is marked on the inner box label, in compliance with JEDEC
Standard JESD97. The maximum ratings related to soldering conditions are also marked on
the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at
www.st.com.
Table 3.
Package dimensions
Dimensions
D
Ref
N
Millimeters
E
1
2
A
A1
1
Inches
Min
Typ
Max
Min
Typ
Max
A
0.50
0.55
0.60
0.020
0.022
0.024
A1
0.00
0.02
0.05
0.000
0.001
0.002
b
0.18
0.25
0.30
0.007
0.010
0.012
D(1)
1.45
0.057
E(1)
1.00
0.039
e(2)
0.50
0.020
2
L
k
b
e
k
0.20
L
0.30
0.008
0.35
0.40
0.012
0.014
0.016
1. ± 0.1 mm
2. ± 0.05 mm
Figure 13. Footprint dimensions in mm [inches]
0.50
[0.020]
0.25
[0.010]
0.65
[0.026]
0.30
1.60
[0.012] [0.063]
5/11
Package information
ESDA6V1M6, ESDA6V1-5M6
Figure 14. Tape and reel specification
Dot identifying Pin A1 location
X
X
1.20
X: Marking
6/11
φ 1.5 +/- 0.1
3.5 +/- 0.03
1.65
8.0 +/- 0.3
0.75
Note:
4.00+/-0.1
1.75 +/- 0.1
2.0+/-0.05
X
4.00
User direction of unreeling
Product marking may be rotated by 90° for assembly plant differentiation. In no case should
this product marking be used to orient the component for its placement on a PCB. Only pin 1
mark is to be used for this purpose.
ESDA6V1M6, ESDA6V1-5M6
Recommendation on PCB assembly
4
Recommendation on PCB assembly
4.1
Stencil opening design
1.
General recommendation on stencil opening design
a)
Stencil opening dimensions: L (Length), W (Width), T (Thickness).
Figure 15. Stencil opening dimensions
L
T
b)
W
General design rule
Stencil thickness (T) = 75 ~ 125 µm
W
Aspect Ratio = ----- ≥ 1.5
T
L× W
Aspect Area = ---------------------------- ≥ 0.66
2T ( L + W )
2.
Reference design
a)
Stencil opening thickness: 100 µm
b)
Stencil opening for leads: Opening to footprint ratio is 90%.
Figure 16. Recommended stencil window position
7 µm
7 µm
620 µm
650 µm
15 µm
236 µm
15 µm
250 µm
Footprint
Stencil window
Footprint
7/11
Recommendation on PCB assembly
4.2
4.3
4.4
8/11
ESDA6V1M6, ESDA6V1-5M6
Solder paste
1.
Halide-free flux qualification ROL0 according to ANSI/J-STD-004.
2.
“No clean” solder paste is recommended.
3.
Offers a high tack force to resist component movement during high speed.
4.
Solder paste with fine particles: powder particle size is 20-45 µm.
Placement
1.
Manual positioning is not recommended.
2.
It is recommended to use the lead recognition capabilities of the placement system, not
the outline centering.
3.
Standard tolerance of ± 0.05 mm is recommended.
4.
3.5 N placement force is recommended. Too much placement force can lead to
squeezed out solder paste and cause solder joints to short. Too low placement force
can lead to insufficient contact between package and solder paste that could cause
open solder joints or badly centered packages.
5.
To improve the package placement accuracy, a bottom side optical control should be
performed with a high resolution tool.
6.
For assembly, a perfect supporting of the PCB (all the more on flexible PCB) is
recommended during solder paste printing, pick and place and reflow soldering by
using optimized tools.
PCB design preference
1.
To control the solder paste amount, the closed via is recommended instead of open
vias.
2.
The position of tracks and open vias in the solder area should be well balanced. The
symmetrical layout is recommended, in case any tilt phenomena caused by
asymmetrical solder paste amount due to the solder flow away.
ESDA6V1M6, ESDA6V1-5M6
4.5
Recommendation on PCB assembly
Reflow profile
Figure 17. ST ECOPACK® recommended soldering reflow profile for PCB mounting
Temperature (°C)
260°C max
255°C
220°C
180°C
125 °C
2°C/s recommended
2°C/s recommended
6°C/s max
6°C/s max
3°C/s max
3°C/s max
0
0
1
2
3
4
5
10-30 sec
90 to 150 sec
Note:
6
7
Time (min)
90 sec max
Minimize air convection currents in the reflow oven to avoid component movement.
9/11
Ordering information
5
ESDA6V1M6, ESDA6V1-5M6
Ordering information
Table 4.
Ordering information
Order code
Marking
Package
Weight
Base qty
Delivery mode
ESDA6V1M6
I(1)
Micro QFN
2.2 mg
3000
Tape and reel
ESDA6V1-5M6
J(1)
Micro QFN
2.2 mg
3000
Tape and reel
1. The marking can be rotated by 90° to differentiate assembly location
6
Revision history
Table 5.
10/11
Document revision history
Date
Revision
Changes
19-Sep-2005
1
Initial release.
10-Oct-2005
2
Package title changed from DFN to QFN. No technical changes.
01-Feb-2007
3
Reformatted to current standard.
Added note on marking rotation in section 3. Package information.
18-Feb-2008
4
Reformatted to current standards. Corrected inch measurements in
Table 3 on page 5. Added Section 4: Recommendation on PCB
assembly.
ESDA6V1M6, ESDA6V1-5M6
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11/11
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