Download datasheet for Am29F160D by Spansion

Download datasheet for Am29F160D by Spansion
Am29F160D
Data Sheet
Am29F160D Cover Sheet
The following document contains information on Spansion memory products.
Continuity of Specifications
There is no change to this data sheet as a result of offering the device as a Spansion product. Any changes that have been
made are the result of normal data sheet improvement and are noted in the document revision summary.
For More Information
Please contact your local sales office for additional information about Spansion memory solutions.
Publication Number Am29F160D_00
Revision D
Amendment 10
Issue Date April 23, 2010
D at a
S hee t
This page left intentionally blank.
2
Am29F160D
Am29F160D_00_D10 April 23, 2010
DATA SHEET
Am29F160D
16 Megabit (2 M x 8-Bit/1 M x 16-Bit)
CMOS 5.0 Volt-only, Boot Sector Flash Memory
DISTINCTIVE CHARACTERISTICS
■ 5.0 Volt single power supply operation
— Minimizes system-level power requirements
■ High performance
— Access times as fast as 70 ns
■ Manufactured on 0.23 µm process technology
■ CFI (Common Flash Interface) compliant
— Provides device-specific information to the
system, allowing host software to easily
reconfigure for different Flash devices
■ Ultra low power consumption (typical values at
5 MHz)
— 15 mA typical active read current
— 35 mA typical erase/program current
— 300 nA typical standby mode current
■ Flexible sector architecture
— One 16 Kbyte, two 8 Kbyte, one 32 Kbyte, and
thirty-one 64 Kbyte sectors (byte mode)
— One 8 Kword, two 4 Kword, one 16 Kword, and
thirty-one 32 Kword sectors (word mode)
— Supports full chip erase
— Sector Protection features:
— Hardware method of locking a sector to prevent
program or erase operations within that sector
— Sectors can be locked in-system or via
programming equipment
— Temporary Sector Unprotect feature allows code
changes in previously locked sectors
■ Top boot or bottom boot configurations
available
■ Minimum 1,000,000 write cycle guarantee
per sector
■ 20-year data retention at 125° C
— Reliable operation for the life of the system
■ Package options
— 48-pin TSOP
■ Compatible with JEDEC standards
— Pinout and software compatible with singlepower supply Flash
— Superior inadvertent write protection
■ Embedded Algorithms
— Embedded Erase algorithm automatically
preprograms and erases the entire chip or any
combination of designated sectors
— Embedded Program algorithm automatically
writes and verifies data at specified addresses
■ Erase Suspend/Erase Resume
— Suspends an erase operation to read data from,
or program data to, a sector that is not being
erased, then resumes the erase operation
■ Data# Polling and toggle bits
— Provides a software method of detecting
program or erase operation completion
■ Unlock Bypass Program command
— Reduces overall programming time when
issuing multiple program command sequences
■ Ready/Busy# pin (RY/BY#)
— Provides a hardware method of detecting
program or erase cycle completion
■ Hardware reset pin (RESET#)
— Hardware method to reset the device for reading
array data
■ WP# input pin
— At VIL, protects the 16 Kbyte boot sector from
erasure regardless of sector protect/unprotect
status
— At VIH, allows removal of boot sector protection
■ Program and Erase Performance
— Sector erase time: 1 s typical for each 64 Kbyte
sector
— Byte program time: 7 µs typical
This Data Sheet states AMD’s current technical specifications regarding the Product described herein. This Data
Sheet may be revised by subsequent versions or modifications due to changes in technical specifications.
Publication# Am29F160D_00 Revision: D
Amendment: 10 Issue Date: April 23, 2010
DATA SHEET
GENERAL DESCRIPTION
The Am29F160D is a 16 Mbit, 5.0 Volt-only Flash
memory device organized as 2,097,152 bytes or
1,048,576 words. Data appears on DQ0-DQ7 or DQ0DQ15 depending on the data width selected. The
device is designed to be programmed in-system with
the standard system 5.0 volt VCC supply. A 12.0 volt
VPP is not required for program or erase operations.
The device can also be programmed in standard
EPROM programmers.
The device offers access times of 70 and 90 ns, allowing
high speed microprocessors to operate without wait
states. The device is offered in a 48-pin TSOP
package. To eliminate bus contention each device has
separate chip enable (CE#), write enable (WE#) and
output enable (OE#) controls.
Each device requires only a single 5.0 volt power
supply for both read and write functions. Internally
generated and regulated voltages are provided for the
program and erase operations.
The device is entirely command set compatible with the
JEDEC single-power-supply Flash standard. Commands are written to the command register using standard microprocessor write timing. Register contents
serve as inputs to an internal state-machine that controls the erase and programming circuitry. Write cycles
also internally latch addresses and data needed for the
programming and erase operations. Reading data out
of the device is similar to reading from other Flash or
EPROM devices.
Device programming occurs by executing the program
command sequence. This initiates the Embedded
Program algorithm—an internal algorithm that automatically times the program pulse widths and verifies
proper cell margin. The Unlock Bypass mode facilitates faster programming times by requiring only two
write cycles to program data instead of four.
Device erasure occurs by executing the erase
command sequence. This initiates the Embedded
Erase algorithm—an internal algorithm that automatically preprograms the array (if it is not already programmed) before executing the erase operation.
During erase, the device automatically times the erase
pulse widths and verifies proper cell margin.
2
The host system can detect whether a program or
erase operation is complete by observing the RY/BY#
pin, by reading the DQ7 (Data# Polling), or DQ6
(toggle) status bits. After a program or erase cycle is
completed, the device is ready to read array data or
accept another command.
The sector erase architecture allows memory sectors
to be erased and reprogrammed without affecting the
data contents of other sectors. The device is fully
erased when shipped from the factory.
Hardware data protection measures include a low
VCC detector that automatically inhibits write operations
during power transitions. The hardware sector protection feature disables both program and erase operations
in any combination of sectors of memory. This can be
achieved in-system or via programming equipment.
The Write Protect (WP#) feature protects the 16
Kbyte boot sector from erasure, by asserting a logic
low on the WP# pin, whether or not the sector had
been previously protected.
The Erase Suspend/Erase Resume feature enables
the user to put erase on hold for any period of time to
read data from, or program data to, any sector that is
not selected for erasure. True background erase can
thus be achieved.
The hardware RESET# pin terminates any operation
in progress and resets the internal state machine to
reading array data. The RESET# pin may be tied to the
system reset circuitry. A system reset would thus also
reset the device, enabling the system microprocessor
to read boot-up firmware from the Flash memory device.
The device offers a standby mode as a power-saving
feature. Once the system places the device into the
standby mode power consumption is greatly reduced.
AMD’s Flash technology combines years of Flash
memory manufacturing experience to produce the
highest levels of quality, reliability and cost effectiveness. The device electrically erases all bits within a
sector simultaneously via Fowler-Nordheim tunnelling.
The data is programmed using hot electron injection.
Am29F160D
Am29F160D_00_D10 April 23, 2010
DATA SHEET
TABLE OF CONTENTS
Product Selector Guide . . . . . . . . . . . . . . . . . . . . . 4
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . 5
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . 7
Device Bus Operations . . . . . . . . . . . . . . . . . . . . . 8
Table 1. Am29F160D Device Bus Operations . . . . . 8
Word/Byte Configuration . . . . . . . . . . . . . . . . . . . . . 8
Requirements for Reading Array Data . . . . . . . . . . . 8
Writing Commands/Command Sequences . . . . . . . 9
Program and Erase Operation Status . . . . . . . . . . . 9
Standby Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Automatic Sleep Mode . . . . . . . . . . . . . . . . . . . . . . . 9
RESET#: Hardware Reset Pin . . . . . . . . . . . . . . . . . 9
Output Disable Mode . . . . . . . . . . . . . . . . . . . . . . . . 9
Table 2. Am29F160DT Sector Address Table (Top
Boot) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Table 3. Am29F160DB Sector Address Table (Bottom
Boot) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Autoselect Mode . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Table 4. Am29F160D Autoselect Codes (High Voltage
Method) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Sector Protection/Unprotection . . . . . . . . . . . . . . . 12
Write Protect (WP#) . . . . . . . . . . . . . . . . . . . . . . . . 13
Temporary Sector Unprotect . . . . . . . . . . . . . . . . . 13
Figure 1. Temporary Sector Unprotect Operation . 13
In-System Sector Protect/Unprotect Algorithms. . . 14
Common Flash Memory Interface (CFI) . . . . . . . 15
Table 5. CFI Query Identification String . . . . . . . . . 15
Table 6. System Interface String . . . . . . . . . . . . . . 16
Table 7. Device Geometry Definition . . . . . . . . . . . 16
Table 8. Primary Vendor-Specific Extended Query 17
Hardware Data Protection . . . . . . . . . . . . . . . . . . . 18
Reading Array Data . . . . . . . . . . . . . . . . . . . . . . . . 18
Reset Command . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Autoselect Command Sequence . . . . . . . . . . . . . . 19
Word/Byte Program Command Sequence. . . . . . . 19
Figure 3. Program Operation . . . . . . . . . . . . . . . . . 20
Chip Erase Command Sequence . . . . . . . . . . . . . 20
Sector Erase Command Sequence . . . . . . . . . . . . 20
Erase Suspend/Erase Resume Commands . . . . . 21
Figure 4. Erase Operation . . . . . . . . . . . . . . . . . . . 21
Command Definitions. . . . . . . . . . . . . . . . . . . . . . . 22
Table 9. Am29F160D Command Definitions . . . . . 22
Write Operation Status . . . . . . . . . . . . . . . . . . . . 23
April 23, 2010 Am29F160D_00_D10
DQ7: Data# Polling . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 5. Data# Polling Algorithm . . . . . . . . . . . . . . 23
RY/BY#: Ready/Busy# . . . . . . . . . . . . . . . . . . . . . . 24
DQ6: Toggle Bit I . . . . . . . . . . . . . . . . . . . . . . . . . . 24
DQ2: Toggle Bit II . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Reading Toggle Bits DQ6/DQ2. . . . . . . . . . . . . . . . 24
DQ5: Exceeded Timing Limits . . . . . . . . . . . . . . . . 25
DQ3: Sector Erase Timer . . . . . . . . . . . . . . . . . . . . 25
Figure 6. Toggle Bit Algorithm . . . . . . . . . . . . . . . . 25
Table 10. Write Operation Status . . . . . . . . . . . . . . 26
Absolute Maximum Ratings. . . . . . . . . . . . . . . . . 27
Figure 7. Maximum Negative Overshoot Waveform 27
Figure 8. Maximum Positive Overshoot Waveform. 27
Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . 27
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 28
TTL/NMOS Compatible. . . . . . . . . . . . . . . . . . . . . . 28
CMOS Compatible . . . . . . . . . . . . . . . . . . . . . . . . . 29
Test Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Figure 9. Test Setup . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 11. Test Specifications . . . . . . . . . . . . . . . . . 30
Key to Switching Waveforms. . . . . . . . . . . . . . . . 30
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 31
Figure 10. Read Operations Timings . . . . . . . . . . . 31
Figure 11. RESET# Timings . . . . . . . . . . . . . . . . . . 32
Figure 12. BYTE# Timings for Read Operations . . 33
Figure 13. BYTE# Timings for Write Operations. . . 33
Figure 14. Program Operation Timings. . . . . . . . . . 35
Figure 15. Chip/Sector Erase Operation Timings . . 36
Figure 16. Data# Polling Timings (During Embedded
Algorithms) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Figure 17. Toggle Bit Timings (During Embedded Algorithms) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Figure 18. DQ2 vs. DQ6 . . . . . . . . . . . . . . . . . . . . . 38
Figure 19. Temporary Sector Unprotect Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Figure 20. Sector Protect/Unprotect
Timing Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Figure 21. Alternate CE# Controlled Write Operation
Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Erase and Programming Performance . . . . . . . . 42
Latchup Characteristics . . . . . . . . . . . . . . . . . . . . 42
TSOP and SO Pin Capacitance . . . . . . . . . . . . . . 42
Data Retention. . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . 43
Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . 44
Am29F160D
3
DATA SHEET
PRODUCT SELECTOR GUIDE
Family Part Number
Am29F160D
75
VCC = 5.0 V ± 5%
Speed Option
VCC = 5.0 V ± 10%
70
90
Max access time, ns (tACC)
70
70
90
Max CE# access time, ns (tCE)
70
70
90
Max OE# access time, ns (tOE)
30
30
35
Note:
See “AC Characteristics” for full specifications.
BLOCK DIAGRAM
DQ0–DQ15 (A-1)
RY/BY#
VCC
Sector Switches
VSS
Erase Voltage
Generator
RESET#
WE#
WP#
BYTE#
Input/Output
Buffers
State
Control
Command
Register
PGM Voltage
Generator
Chip Enable
Output Enable
Logic
CE#
OE#
VCC Detector
Address Latch
STB
Timer
A0–A19
4
Am29F160D
STB
Data
Latch
Y-Decoder
Y-Gating
X-Decoder
Cell Matrix
Am29F160D_00_D10 April 23, 2010
DATA SHEET
CONNECTION DIAGRAMS
A15
A14
A13
A12
A11
A10
A9
A8
A19
NC
WE#
RESET#
NC
WP#
RY/BY#
A18
A17
A7
A6
A5
A4
A3
A2
A1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
April 23, 2010 Am29F160D_00_D10
48-Pin TSOP
Standard Pinout
Am29F160D
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
A16
BYTE#
VSS
DQ15/A-1
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
VCC
DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
OE#
VSS
CE#
A0
5
DATA SHEET
PIN CONFIGURATION
A0–A19
LOGIC SYMBOL
= 20 address inputs
20
DQ0–DQ14 = 15 data inputs/outputs
DQ15/A-1
= DQ15 (data input/output, word mode),
A-1 (LSB address input, byte mode)
A0–A19
DQ0–DQ15
(A-1)
BYTE#
= Select input for 8-bit or 16-bit mode
CE#
= Chip Enable input
CE#
OE#
= Output Enable input
OE#
WE#
= Write Enable input
WE#
WP#
= Write Protect input
WP#
RESET#
= Hardware reset input
RY/BY#
= Ready/Busy# output
VCC
= +5.0 V single power supply
(see Product Selector Guide for
device speed ratings and voltage
supply tolerances)
VSS
= Device ground
NC
= Pin not connected internally
6
16 or 8
RESET#
RY/BY#
BYTE#
Am29F160D
Am29F160D_00_D10 April 23, 2010
DATA SHEET
ORDERING INFORMATION
Standard Products
AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is formed
by a combination of the elements below.
Am29F160D
T
75
E
F
TEMPERATURE RANGE
I
= Industrial (–40° C to +85° C)
F
= Industrial (–40° C to +85° C) with Pb-free Package
E
= Extended (–40° C to +110° C)
K
= Extended (–40° C to +110° C) with Pb-free Package
PACKAGE TYPE
E
= 48-Pin Thin Small Outline Package (TSOP)
Standard Pinout (TS 048)
SPEED OPTION
See Product Selector Guide and Valid Combinations
BOOT CODE SECTOR ARCHITECTURE
T
= Top sector
B
= Bottom sector
DEVICE NUMBER/DESCRIPTION
Am29F160D
16 Megabit (2 M x 8-Bit/1 M x 16-Bit) CMOS Boot Sector Flash Memory
5.0 Volt-only Read, Program and Erase
Valid Combinations
Valid Combinations
Order Number
EI,
Speed
(ns)
Voltage
Range
70
5.0 V
± 5%
AM29F160DT75,
AM29F160DB75
EF
AM29F160DT70,
AM29F160DB70
EF
AM29F160DT90,
AM29F160DB90
EI,
EF
90
Am29F160DT75,
Am29F160DB75
EE,
EK
70
5.0 V
± 5%
Am29F160DT90,
Am29F160DB90
EE,
EK
90
5.0 V
± 10%
EI
April 23, 2010 Am29F160D_00_D10
Valid Combinations list configurations planned to be supported in volume for this device. Consult the local AMD sales
office to confirm availability of specific valid combinations and
to check on newly released combinations.
70
5.0 V
± 10%
Am29F160D
7
DATA SHEET
DEVICE BUS OPERATIONS
This section describes the requirements and use of the
device bus operations, which are initiated through the
internal command register. The command register itself does not occupy any addressable memory location. The register is composed of latches that store the
commands, along with the address and data information needed to execute the command. The contents of
the register serve as inputs to the internal state machine. The state machine outputs dictate the function of
the device. The appropriate device bus operations
table lists the inputs and control levels required, and the
resulting output. The following subsections describe
each of these operations in further detail.
Table 1. Am29F160D Device Bus Operations
DQ8–DQ15
Operation
CE#
OE#
WE#
WP#
RESET#
Addresses
(Note 1)
DQ0–
DQ7
BYTE#
= VIH
BYTE#
= VIL
Read
L
L
H
X
H
AIN
DOUT
DOUT
Write
L
H
L
(Note 3)
H
AIN
DIN
DIN
DQ8–DQ14 = High-Z,
DQ15 = A-1
VCC ±
0.5 V
X
X
(Note 4)
VCC ±
0.5 V
X
High-Z
High-Z
High-Z
Output Disable
L
H
H
X
H
X
High-Z
High-Z
High-Z
Reset
X
X
X
X
L
X
High-Z
High-Z
High-Z
DIN
X
X
Standby
Sector Protect
(Note 2)
L
H
L
X
VID
Sector Address,
A6 = L, A1 = H,
A0 = L
Sector Unprotect
(Note 2)
L
H
L
X
VID
Sector Address,
A6 = H, A1 = H,
A0 = L
DIN
X
X
Temporary Sector
Unprotect
X
X
X
(Note 3)
VID
AIN
DIN
DIN
High-Z
Legend:
L = Logic Low = VIL, H = Logic High = VIH, VID = 12.0 ± 0.5 V, X = Don’t Care, AIN = Address In, DIN = Data In, DOUT = Data Out
Notes:
1. Addresses are A19:A0 in word mode (BYTE# = VIH), A19:A-1 in byte mode (BYTE# = VIL).
2. The sector protect and sector unprotect functions may also be implemented via programming equipment. See the “Sector
Protection/Unprotection” section.
3. The 16 Kbyte boot sector is protected from erasure when WP# = VIL.
4. In CMOS mode, WP# must be at VCC±0.5 V or left floating.
Word/Byte Configuration
The BYTE# pin controls whether the device data I/O
pins DQ15–DQ0 operate in the byte or word configuration. If the BYTE# pin is set at logic ‘1’, the device is in
word configuration, DQ15–DQ0 are active and controlled by CE# and OE#.
If the BYTE# pin is set at logic ‘0’, the device is in byte
configuration, and only data I/O pins DQ0–DQ7 are active and controlled by CE# and OE#. The data I/O pins
DQ8–DQ14 are tri-stated, and the DQ15 pin is used as
an input for the LSB (A-1) address function.
Requirements for Reading Array Data
To read array data from the outputs, the system must
drive the CE# and OE# pins to VIL. CE# is the power
control and selects the device. OE# is the output control
8
and gates array data to the output pins. WE# should remain at VIH.
The internal state machine is set for reading array
data upon device power-up, or after a hardware reset.
This ensures that no spurious alteration of the memory content occurs during the power transition. No
command is necessary in this mode to obtain array
data. Standard microprocessor read cycles that assert valid addresses on the device address inputs
produce valid data on the device data outputs. The
device remains enabled for read access until the
command register contents are altered.
See Reading Array Data‚ on page 18 for more information. Refer to the AC Read Operations table for timing
specifications and to the Read Operations Timings diagram for the timing waveforms. ICC1 in the DC Char-
Am29F160D
Am29F160D_00_D10 April 23, 2010
DATA SHEET
acteristics table represents the active current specification for reading array data.
Writing Commands/Command Sequences
To write a command or command sequence (which includes programming data to the device and erasing
sectors of memory), the system must drive WE# and
CE# to VIL, and OE# to VIH.
An erase operation can erase one sector, multiple sectors, or the entire device. The Sector Address Tables indicate the address space that each sector occupies. A
“sector address” consists of the address bits required
to uniquely select a sector. See the Command Definitions‚ on page 18 section for details on erasing a sector
or the entire chip, or suspending/resuming the erase
operation.
After the system writes the autoselect command sequence, the device enters the autoselect mode. The
system can then read autoselect codes from the internal register (which is separate from the memory array)
on DQ7–DQ0. Standard read cycle timings apply in this
mode. Refer to the Autoselect Mode‚ on page 12 and
Autoselect Command Sequence‚ on page 19 sections
for more information.
ICC2 in the DC Characteristics table represents the active current specification for the write mode. The “AC
Characteristics” section contains timing specification
tables and timing diagrams for write operations.
Program and Erase Operation Status
During an erase or program operation, the system may
check the status of the operation by reading the status
bits on DQ7–DQ0. Standard read cycle timings and ICC
read specifications apply. Refer to Write Operation
Status‚ on page 23 for more information, and to each
AC Characteristics section for timing diagrams.
Standby Mode
When the system is not reading or writing to the device,
it can place the device in the standby mode. In this
mode, current consumption is greatly reduced, and the
outputs are placed in the high impedance state, independent of the OE# input.
The device enters the CMOS standby mode when the
CE# and RESET# are held at VCC ± 0.5 V. (Note that
this is a more restricted voltage range than VIH.) WP#
must also either be held at VCC ± 0.5 V or left floating.
The device enters the TTL standby mode when CE#
and RESET# pins are both held at VIH. The device requires standard access time (tCE) for read access when
the device is in either of these standby modes, before it
is ready to read data.
April 23, 2010 Am29F160D_00_D10
The device also enters the standby mode when the RESET# pin is driven low. Refer to the next section,
RESET#: Hardware Reset Pin‚ on page 9.
If the device is deselected during erasure or programming, the device draws active current until the
operation is completed.
In the DC Characteristics tables, ICC3 represents the
standby current specification.
Automatic Sleep Mode
The automatic sleep mode minimizes flash device
energy consumption. The device automatically enables
this mode when addresses remain stable for tACC + 30
ns. The automatic sleep mode is independent of the
CE#, WE#, and OE# control signals. Standard address
access timings provide new data when addresses are
changed. While in sleep mode, output data is latched
and always available to the system.
RESET#: Hardware Reset Pin
The RESET# pin provides a hardware method of resetting the device to reading array data. When the system
drives the RESET# pin low for at least a period of tRP,
the device immediately terminates any operation in
progress, tristates all data output pins, and ignores all
read/write attempts for the duration of the RESET#
pulse. The device also resets the internal state machine to reading array data. The operation that was interrupted should be reinitiated once the device is ready
to accept another command sequence, to ensure data
integrity. Current is reduced for the duration of the RESET# pulse.
The RESET# pin may be tied to the system reset circuitry. A system reset would thus also reset the Flash
memory, enabling the system to read the boot-up firmware from the Flash memory.
If RESET# is asserted during a program or erase operation, the RY/BY# pin remains a “0” (busy) until the internal reset operation is complete, which requires a
time of tREADY (during Embedded Algorithms). The
system can thus monitor RY/BY# to determine whether
the reset operation is complete. If RESET# is asserted
when a program or erase operation is not executing
(RY/BY# pin is “1”), the reset operation is completed
within a time of tREADY (not during Embedded Algorithms). The system can read data tRH after the RESET# pin returns to VIH.
Refer to the AC Characteristics tables for RESET# parameters and timing diagram.
Output Disable Mode
When the OE# input is at VIH, output from the device is
disabled. The output pins are placed in the high impedance state.
Am29F160D
9
DATA SHEET
Table 2.
Am29F160DT Sector Address Table (Top Boot)
Address Range (in hexadecimal)
Sector
A19
A18
A17
A16
A15
A14
A13
A12
Sector Size
(Kbytes/
Kwords)
SA0
0
0
0
0
0
X
X
X
64/32
000000–00FFFF
00000–07FFF
SA1
0
0
0
0
1
X
X
X
64/32
010000–01FFFF
08000–0FFFF
SA2
0
0
0
1
0
X
X
X
64/32
020000–02FFFF
10000–17FFF
SA3
0
0
0
1
1
X
X
X
64/32
030000–03FFFF
18000–1FFFF
SA4
0
0
1
0
0
X
X
X
64/32
040000–04FFFF
20000–27FFF
SA5
0
0
1
0
1
X
X
X
64/32
050000–05FFFF
28000–2FFFF
SA6
0
0
1
1
0
X
X
X
64/32
060000–06FFFF
30000–37FFF
SA7
0
0
1
1
1
X
X
X
64/32
070000–07FFFF
38000–3FFFF
SA8
0
1
0
0
0
X
X
X
64/32
080000–08FFFF
40000–47FFF
SA9
0
1
0
0
1
X
X
X
64/32
090000–09FFFF
48000–4FFFF
SA10
0
1
0
1
0
X
X
X
64/32
0A0000–0AFFFF
50000–57FFF
SA11
0
1
0
1
1
X
X
X
64/32
0B0000–0BFFFF
58000–5FFFF
SA12
0
1
1
0
0
X
X
X
64/32
0C0000–0CFFFF
60000–67FFF
SA13
0
1
1
0
1
X
X
X
64/32
0D0000–0DFFFF
68000–6FFFF
SA14
0
1
1
1
0
X
X
X
64/32
0E0000–0EFFFF
70000–77FFF
SA15
0
1
1
1
1
X
X
X
64/32
0F0000–0FFFFF
78000–7FFFF
SA16
1
0
0
0
0
X
X
X
64/32
100000–10FFFF
80000–87FFF
SA17
1
0
0
0
1
X
X
X
64/32
110000–11FFFF
88000–8FFFF
SA18
1
0
0
1
0
X
X
X
64/32
120000–12FFFF
90000–97FFF
SA19
1
0
0
1
1
X
X
X
64/32
130000–13FFFF
98000–9FFFF
SA20
1
0
1
0
0
X
X
X
64/32
140000–14FFFF
A0000–A7FFF
SA21
1
0
1
0
1
X
X
X
64/32
150000–15FFFF
A8000–AFFFF
SA22
1
0
1
1
0
X
X
X
64/32
160000–16FFFF
B0000–B7FFF
SA23
1
0
1
1
1
X
X
X
64/32
170000–17FFFF
B8000–BFFFF
SA24
1
1
0
0
0
X
X
X
64/32
180000–18FFFF
C0000–C7FFF
SA25
1
1
0
0
1
X
X
X
64/32
190000–19FFFF
C8000–CFFFF
SA26
1
1
0
1
0
X
X
X
64/32
1A0000–1AFFFF
D0000–D7FFF
SA27
1
1
0
1
1
X
X
X
64/32
1B0000–1BFFFF
D8000–DFFFF
SA28
1
1
1
0
0
X
X
X
64/32
1C0000–1CFFFF
E0000–E7FFF
SA29
1
1
1
0
1
X
X
X
64/32
1D0000–1DFFFF
E8000–EFFFF
SA30
1
1
1
1
0
X
X
X
64/32
1E0000–1EFFFF
F0000–F7FFF
SA31
1
1
1
1
1
0
X
X
32/16
1F0000–1F7FFF
F8000–FBFFF
SA32
1
1
1
1
1
1
0
0
8/4
1F8000–1F9FFF
FC000–FCFFF
SA33
1
1
1
1
1
1
0
1
8/4
1FA000–1FBFFF
FD000–FDFFF
SA34
1
1
1
1
1
1
1
X
16/8
1FC000–1FFFFF
FE000–FFFFF
Byte Mode (x8)
Word Mode (x16)
Note: Address range is A19:A-1 in byte mode and A19:A0 in
word mode. See “Word/Byte Configuration” section.
10
Am29F160D
Am29F160D_00_D10 April 23, 2010
DATA SHEET
Table 3.
Am29F160DB Sector Address Table (Bottom Boot)
Address Range (in hexadecimal)
Sector
A19
A18
A17
A16
A15
A14
A13
A12
Sector Size
(Kbytes/
Kwords)
SA0
0
0
0
0
0
0
0
X
16/8
000000–003FFF
00000–01FFF
SA1
0
0
0
0
0
0
1
0
8/4
004000–005FFF
02000–02FFF
SA2
0
0
0
0
0
0
1
1
8/4
006000–007FFF
03000–03FFF
SA3
0
0
0
0
0
1
X
X
32/16
008000–00FFFF
04000–07FFF
SA4
0
0
0
0
1
X
X
X
64/32
010000–01FFFF
08000–0FFFF
SA5
0
0
0
1
0
X
X
X
64/32
020000–02FFFF
10000–17FFF
SA6
0
0
0
1
1
X
X
X
64/32
030000–03FFFF
18000–1FFFF
SA7
0
0
1
0
0
X
X
X
64/32
040000–04FFFF
20000–27FFF
SA8
0
0
1
0
1
X
X
X
64/32
050000–05FFFF
28000–2FFFF
SA9
0
0
1
1
0
X
X
X
64/32
060000–06FFFF
30000–37FFF
SA10
0
0
1
1
1
X
X
X
64/32
070000–07FFFF
38000–3FFFF
SA11
0
1
0
0
0
X
X
X
64/32
080000–08FFFF
40000–47FFF
SA12
0
1
0
0
1
X
X
X
64/32
090000–09FFFF
48000–4FFFF
SA13
0
1
0
1
0
X
X
X
64/32
0A0000–0AFFFF
50000–57FFF
SA14
0
1
0
1
1
X
X
X
64/32
0B0000–0BFFFF
58000–5FFFF
SA15
0
1
1
0
0
X
X
X
64/32
0C0000–0CFFFF
60000–67FFF
SA16
0
1
1
0
1
X
X
X
64/32
0D0000–0DFFFF
68000–6FFFF
SA17
0
1
1
1
0
X
X
X
64/32
0E0000–0EFFFF
70000–77FFF
SA18
0
1
1
1
1
X
X
X
64/32
0F0000–0FFFFF
78000–7FFFF
SA19
1
0
0
0
0
X
X
X
64/32
100000–10FFFF
80000–87FFF
SA20
1
0
0
0
1
X
X
X
64/32
110000–11FFFF
88000–8FFFF
SA21
1
0
0
1
0
X
X
X
64/32
120000–12FFFF
90000–97FFF
SA22
1
0
0
1
1
X
X
X
64/32
130000–13FFFF
98000–9FFFF
SA23
1
0
1
0
0
X
X
X
64/32
140000–14FFFF
A0000–A7FFF
SA24
1
0
1
0
1
X
X
X
64/32
150000–15FFFF
A8000–AFFFF
SA25
1
0
1
1
0
X
X
X
64/32
160000–16FFFF
B0000–B7FFF
SA26
1
0
1
1
1
X
X
X
64/32
170000–17FFFF
B8000–BFFFF
SA27
1
1
0
0
0
X
X
X
64/32
180000–18FFFF
C0000–C7FFF
SA28
1
1
0
0
1
X
X
X
64/32
190000–19FFFF
C8000–CFFFF
SA29
1
1
0
1
0
X
X
X
64/32
1A0000–1AFFFF
D0000–D7FFF
SA30
1
1
0
1
1
X
X
X
64/32
1B0000–1BFFFF
D8000–DFFFF
SA31
1
1
1
0
0
X
X
X
64/32
1C0000–1CFFFF
E0000–E7FFF
SA32
1
1
1
0
1
X
X
X
64/32
1D0000–1DFFFF
E8000–EFFFF
SA33
1
1
1
1
0
X
X
X
64/32
1E0000–1EFFFF
F0000–F7FFF
SA34
1
1
1
1
1
X
X
X
64/32
1F0000–1FFFFF
F8000–FFFFF
Byte Mode (x8)
Word Mode (x16)
Note: Address range is A19:A-1 in byte mode and A19:A0 in
word mode. See the Word/Byte Configuration‚ on page 8.
.
April 23, 2010 Am29F160D_00_D10
Am29F160D
11
DATA SHEET
Autoselect Mode
The autoselect mode provides manufacturer and device identification, and sector protection verification,
through identifier codes output on DQ7–DQ0. This
mode is primarily intended for programming equipment
to automatically match a device to be programmed with
its corresponding programming algorithm. However,
the autoselect codes can also be accessed in-system
through the command register.
dress must appear on the appropriate highest order
address bits. Refer to the corresponding Sector Address Tables. The Command Definitions table shows
the remaining address bits that are don’t care. When all
necessary bits are set as required, the programming
equipment may then read the corresponding identifier
code on DQ7–DQ0.
To access the autoselect codes in-system, the host
system can issue the autoselect command via the
command register, as shown in the Command Definitions table. This method does not require VID. See
Command Definitions‚ on page 18 for details on using
the autoselect mode.
When using programming equipment, the autoselect
mode requires VID (11.5 V to 12.5 V) on address pin
A9. Address pins A6, A1, and A0 must be as shown in
Autoselect Codes (High Voltage Method) table. In addition, when verifying sector protection, the sector ad-
Table 4.
Description
Mode
Manufacturer ID: AMD
Am29F160D Autoselect Codes (High Voltage Method)
A11
to
A10
A1
A0
DQ8
to
DQ15
DQ7
to
DQ0
X
01h
22h
D2h
X
D2h
22h
D8h
X
D8h
X
01h (protected)
X
00h
(unprotected)
OE#
WE#
L
L
H
X
X
VID
X
L
X
L
L
L
L
H
X
X
VID
X
L
X
L
H
VID
X
VID
X
Word
Byte
L
L
H
Device ID:
Am29F160D
(Bottom Boot Block)
Word
L
L
H
X
Sector Protection Verification
A6
A5
to
A2
CE#
Device ID:
Am29F160D
(Top Boot Block)
Byte
A9
A8
to
A7
A19
to
A12
L
L
H
L
L
H
X
SA
X
L
L
X
X
L
H
H
L
L = Logic Low = VIL, H = Logic High = VIH, SA = Sector Address, X = Don’t care.
Sector Protection/Unprotection
The hardware sector protection feature disables both
program and erase operations in any sector. The hardware sector unprotection feature re-enables both program and erase operations in previously protected
sectors.
The device is shipped with all sectors unprotected.
AMD offers the option of programming and protecting
sectors at its factory prior to shipping the device
through AMD’s ExpressFlash™ Service. Contact an
AMD representative for details.
It is possible to determine whether a sector is protected
or unprotected. See Autoselect Mode‚ on page 12 for
details.
The primary method requires VID on the RESET# pin
only, and can be implemented either in-system or via
programming equipment. Figure 2, on page 14 shows
the algorithms and Figure 20, on page 39 shows the
timing diagram. This method uses standard microprocessor bus cycle timing. For sector unprotect, all unprotected sectors must first be protected prior to the first
sector unprotect write cycle.
The alternate method intended only for programming
equipment requires VID on address pin A9 and OE#.
This method is compatible with programmer routines
written for earlier 5.0 volt-only AMD flash devices. Details on this method are provided in a supplement, publication number 22289. Contact an AMD representative
to request a copy.
Sector protection/unprotection can be implemented via
two methods.
12
Am29F160D
Am29F160D_00_D10 April 23, 2010
DATA SHEET
Write Protect (WP#)
The Write Protect function provides a hardware
method of protecting the 16 Kbyte boot sector from
erasure without using VID.
START
If the system asserts VIL on the WP# pin, the device
disables erase functions for the 16 Kbyte boot sector
(SA34 for top boot device and SA0 for bottom boot device) independently of whether those sectors were
protected or unprotected using the method described
in Sector Protection/Unprotection‚ on page 12.
RESET# = VID
(Note 1)
Perform Erase or
Program Operations
If the system asserts VIH on the WP# pin, the device
reverts to whether the 16 Kbyte boot sector was previously set to be protected or unprotected using the
method described in Sector Protection/Unprotection‚
on page 12.
RESET# = VIH
Temporary Sector
Unprotect Completed
(Note 2)
Temporary Sector Unprotect
This feature allows temporary unprotection of previously protected sectors to change data in-system. The
Sector Unprotect mode is activated by setting the RESET# pin to VID. During this mode, formerly protected
sectors can be programmed or erased by selecting the
sector addresses. However, note that the boot sector is
still protected from erasure only if WP# is asserted low.
Once VID is removed from the RESET# pin, all the previously protected sectors are protected again. Figure 2,
on page 14 shows the algorithm, and Figure 19, on
page 38 shows the timing diagrams, for this feature.
April 23, 2010 Am29F160D_00_D10
Notes:
1. All protected sectors unprotected. However, boot sector
remains protected from erasure only if WP# is low.
2. All previously protected sectors are protected once
again.
Figure 1.
Am29F160D
Temporary Sector Unprotect Operation
13
DATA SHEET
START
START
Protect all sectors:
The indicated portion
of the sector protect
algorithm must be
performed for all
unprotected sectors
prior to issuing the
first sector
unprotect address
PLSCNT = 1
RESET# = VID
Wait 1 µs
Temporary Sector
Unprotect Mode
No
PLSCNT = 1
RESET# = VID
Wait 1 µs
No
First Write
Cycle = 60h?
First Write
Cycle = 60h?
Yes
Yes
Set up sector
address
No
All sectors
protected?
Sector Protect:
Write 60h to sector
address with
A6 = 0, A1 = 1,
A0 = 0
Yes
Set up first sector
address
Sector Unprotect:
Write 60h to sector
address with
A6 = 1, A1 = 1,
A0 = 0
Wait 150 µs
Increment
PLSCNT
Temporary Sector
Unprotect Mode
Verify Sector
Protect: Write 40h
to sector address
with A6 = 0,
A1 = 1, A0 = 0
Reset
PLSCNT = 1
Wait 15 ms
Read from
sector address
with A6 = 0,
A1 = 1, A0 = 0
Verify Sector
Unprotect: Write
40h to sector
address with
A6 = 1, A1 = 1,
A0 = 0
Increment
PLSCNT
No
No
PLSCNT
= 25?
Yes
Yes
No
Yes
Device failed
Read from
sector address
with A6 = 1,
A1 = 1, A0 = 0
Data = 01h?
PLSCNT
= 1000?
Protect another
sector?
No
Data = 00h?
Yes
Yes
Remove VID
from RESET#
Device failed
Last sector
verified?
Write reset
command
Sector Protect
Algorithm
Sector Protect
complete
Set up
next sector
address
No
No
Yes
Sector Unprotect
Algorithm
Remove VID
from RESET#
Write reset
command
Sector Unprotect
complete
Figure 2.
14
In-System Sector Protect/Unprotect Algorithms
Am29F160D
Am29F160D_00_D10 April 23, 2010
DATA SHEET
COMMON FLASH MEMORY INTERFACE
(CFI)
The Common Flash Interface (CFI) specification outlines device and host system software interrogation
handshake, which allows specific vendor-specified
software algorithms to be used for entire families of
devices. Software support can then be device-independent, JEDEC ID-independent, and forward- and backward-compatible for the specified flash device families.
Flash vendors can standardize their existing interfaces
for long-term compatibility.
This device enters the CFI Query mode when the
system writes the CFI Query command, 98h, to
address 55h in word mode (or address AAh in byte
mode), any time the device is ready to read array data.
The system can read CFI information at the addresses
given in Table 5 on page 15, Table 6 on page 16,
Table 5.
Table 7 on page 16, and –Table 8 on page 17. In word
mode, the upper address bits (A7–MSB) must be all
zeros. To terminate reading CFI data, the system must
write the reset command.
The system can also write the CFI query command
when the device is in the autoselect mode. The device
enters the CFI query mode, and the system can read
CFI data at the addresses given in Table 5 on page 15,
Table 6 on page 16, Table 7 on page 16, and –Table 8
on page 17. The system must write the reset command
to return the device to the autoselect mode.
For further information, please refer to the CFI Specification and CFI Publication 100, available via the World
Wide Web at http://www.amd.com/products/nvd/overview/cfi.html. Alternatively, contact an AMD representative for copies of these documents.
CFI Query Identification String
Addresses
(Word Mode)
Addresses
(Byte Mode)
Data
10h
11h
12h
20h
22h
24h
0051h
0052h
0059h
Query Unique ASCII string “QRY”
13h
14h
26h
28h
0002h
0000h
Primary OEM Command Set
15h
16h
2Ah
2Ch
0040h
0000h
Address for Primary Extended Table
17h
18h
2Eh
30h
0000h
0000h
Alternate OEM Command Set (00h = none exists)
19h
1Ah
32h
34h
0000h
0000h
Address for Alternate OEM Extended Table (00h = none exists)
April 23, 2010 Am29F160D_00_D10
Description
Am29F160D
15
DATA SHEET
Table 6.
Addresses
(Word Mode)
Addresses
(Byte Mode)
Data
1Bh
36h
0045h
VCC Min. (write/erase)
D7–D4: volt, D3–D0: 100 millivolt
1Ch
38h
0055h
VCC Max. (write/erase)
D7–D4: volt, D3–D0: 100 millivolt
1Dh
3Ah
0000h
VPP Min. voltage (00h = no VPP pin present)
1Eh
3Ch
0000h
VPP Max. voltage (00h = no VPP pin present)
1Fh
3Eh
0004h
Typical timeout per single byte/word write 2N µs
20h
40h
0000h
Typical timeout for Min. size buffer write 2N µs (00h = not supported)
21h
42h
000Ah
Typical timeout per individual block erase 2N ms
22h
44h
0000h
Typical timeout for full chip erase 2N ms (00h = not supported)
23h
46h
0005h
Max. timeout for byte/word write 2N times typical
24h
48h
0000h
Max. timeout for buffer write 2N times typical
25h
4Ah
0004h
Max. timeout per individual block erase 2N times typical
26h
4Ch
0000h
Max. timeout for full chip erase 2N times typical (00h = not supported)
Table 7.
16
System Interface String
Description
Device Geometry Definition
Addresses
(Word Mode)
Addresses
(Byte Mode)
Data
27h
4Eh
0015h
Device Size = 2N byte
28h
29h
50h
52h
0002h
0000h
Flash Device Interface description (refer to CFI publication 100)
2Ah
2Bh
54h
56h
0000h
0000h
Max. number of byte in multi-byte write = 2N
(00h = not supported)
2Ch
58h
0004h
Number of Erase Block Regions within device
2Dh
2Eh
2Fh
30h
5Ah
5Ch
5Eh
60h
0000h
0000h
0040h
0000h
Erase Block Region 1 Information
(refer to the CFI specification or CFI publication 100)
31h
32h
33h
34h
62h
64h
66h
68h
0001h
0000h
0020h
0000h
Erase Block Region 2 Information
35h
36h
37h
38h
6Ah
6Ch
6Eh
70h
0000h
0000h
0080h
0000h
Erase Block Region 3 Information
39h
3Ah
3Bh
3Ch
72h
74h
76h
78h
001Eh
0000h
0000h
0001h
Erase Block Region 4 Information
Description
Am29F160D
Am29F160D_00_D10 April 23, 2010
DATA SHEET
Table 8.
Primary Vendor-Specific Extended Query
Addresses
(Word Mode)
Addresses
(Byte Mode)
Data
40h
41h
42h
80h
82h
84h
0050h
0052h
0049h
Query-unique ASCII string “PRI”
43h
86h
0031h
Major version number, ASCII
44h
88h
0031h
Minor version number, ASCII
45h
8Ah
0000h
Address Sensitive Unlock
0 = Required, 1 = Not Required
46h
8Ch
0002h
Erase Suspend
0 = Not Supported, 1 = To Read Only, 2 = To Read & Write
47h
8Eh
0001h
Sector Protect
0 = Not Supported, X = Number of sectors per group
48h
90h
0001h
Sector Temporary Unprotect
00 = Not Supported, 01 = Supported
49h
92h
0004h
Sector Protect/Unprotect scheme
01 = 29F040 mode, 02 = 29F016 mode,
03 = 29F400 mode, 04 = 29LV800A mode
4Ah
94h
0000h
Simultaneous Operation
00 = Not Supported, 01 = Supported
4Bh
96h
0000h
Burst Mode Type
00 = Not Supported, 01 = Supported
4Ch
98h
0000h
Page Mode Type
00 = Not Supported, 01 = 4 Word Page, 02 = 8 Word Page
4Dh
9Ah
0000h
ACC Supply Minimum
4Eh
9Ch
0000h
ACC Supply Maximum
4Fh
9Eh
0002h,
0003h
Top/Bottom Boot Sector Flag
April 23, 2010 Am29F160D_00_D10
Description
02 = bottom, 03 = top
Am29F160D
17
DATA SHEET
Hardware Data Protection
The command sequence requirement of unlock cycles
for programming or erasing provides data protection
against inadvertent writes (refer to the Command Definitions table). In addition, the following hardware data
protection measures prevent accidental erasure or programming, which might otherwise be caused by spurious system level signals during VCC power-up and
power-down transitions, or from system noise.
Low VCC Write Inhibit
When VCC is less than VLKO, the device does not accept any write cycles. This protects data during VCC
power-up and power-down. The command register and
all internal program/erase circuits are disabled, and the
device resets. Subsequent writes are ignored until VCC
is greater than V LKO. The system must provide the
proper signals to the control pins to prevent unintentional writes when VCC is greater than VLKO.
Write Pulse “Glitch” Protection
Noise pulses of less than 5 ns (typical) on OE#, CE# or
WE# do not initiate a write cycle.
Logical Inhibit
Write cycles are inhibited by holding any one of OE# =
VIL, CE# = VIH or WE# = VIH. To initiate a write cycle,
CE# and WE# must be a logical zero while OE# is a
logical one.
Power-Up Write Inhibit
If WE# = CE# = VIL and OE# = VIH during power up, the
device does not accept commands on the rising edge
of WE#. The internal state machine is automatically
reset to reading array data on power-up.
COMMAND DEFINITIONS
Writing specific address and data commands or sequences into the command register initiates device operations. The Command Definitions table defines the
valid register command sequences. Writing incorrect
address and data values or writing them in the improper sequence resets the device to reading array
data.
All addresses are latched on the falling edge of WE# or
CE#, whichever happens later. All data is latched on
the rising edge of WE# or CE#, whichever happens
first. Refer to the appropriate timing diagrams in the
“AC Characteristics” section.
Reading Array Data
The device is automatically set to reading array data
after device power-up. No commands are required to
retrieve data. The device is also ready to read array
data after completing an Embedded Program or Embedded Erase algorithm.
After the device accepts an Erase Suspend command,
the device enters the Erase Suspend mode. The system can read array data using the standard read timings, except that if it reads at an address within erasesuspended sectors, the device outputs status data.
After completing a programming operation in the Erase
Suspend mode, the system may once again read array
data with the same exception. See Erase Suspend/Erase Resume Commands‚ on page 21 for more
information on this mode.
The system must issue the reset command to re-enable the device for reading array data if DQ5 goes high,
18
or while in the autoselect mode. See the Reset Command‚ on page 18 section, next.
See also Requirements for Reading Array Data‚ on
page 8 for more information. The Read Operations
table provides the read parameters, and Read Operation Timings diagram shows the timing diagram.
Reset Command
Writing the reset command to the device resets the device to reading array data. Address bits are don’t care
for this command.
The reset command may be written between the sequence cycles in an erase command sequence before
erasing begins. This resets the device to reading array
data. Once erasure begins, however, the device ignores reset commands until the operation is complete.
The reset command may be written between the sequence cycles in a program command sequence before programming begins. This resets the device to
reading array data (also applies to programming in
Erase Suspend mode). Once programming begins,
however, the device ignores reset commands until the
operation is complete.
The reset command may be written between the sequence cycles in an autoselect command sequence.
Once in the autoselect mode, the reset command must
be written to return to reading array data (also applies
to autoselect during Erase Suspend).
If DQ5 goes high during a program or erase operation,
writing the reset command returns the device to reading array data (also applies during Erase Suspend).
Am29F160D
Am29F160D_00_D10 April 23, 2010
DATA SHEET
Autoselect Command Sequence
The autoselect command sequence allows the host
system to access the manufacturer and devices codes,
and determine whether or not a sector is protected.
The Command Definitions table shows the address
and data requirements. This method is an alternative to
that shown in the Autoselect Codes (High Voltage
Method) table, which is intended for PROM programmers and requires VID on address bit A9.
The autoselect command sequence is initiated by
writing two unlock cycles, followed by the autoselect
command. The device then enters the autoselect
mode, and the system may read at any address any
number of times, without initiating another command
sequence.
A read cycle at address XX00h retrieves the manufacturer code. A read cycle at address XX01h in word
mode (or 02h in byte mode) returns the device code.
A read cycle containing a sector address (SA) and the
address 02h in word mode (or 04h in byte mode) returns 01h if that sector is protected, or 00h if it is unprotected. Refer to the Sector Address tables for valid
sector addresses. When a read occurs at an address
within the 16 Kbyte boot sector (SA34 for top boot devices and SA0 for bottom boot devices), the input on
WP# may determine what code is returned.
16Kb Sector
Protection
WP#
input
Autoselect
Code
protected
VIH
01 (protected)
protected
VIL
01 (protected)
unprotected
VIH
00 (unprotected)
unprotected
VIL
01 (protected)1
1
Sector is protected from erasure. Programing operations within sector is still permitted.
The system must write the reset command to exit the
autoselect mode and return to reading array data.
Word/Byte Program Command Sequence
The system may program the device by byte or word,
on depending on the state of the BYTE# pin. Programming is a four-bus-cycle operation. The program command sequence is initiated by writing two unlock write
cycles, followed by the program set-up command. The
program address and data are written next, which in
turn initiate the Embedded Program algorithm. The
system is not required to provide further controls or timings. The device automatically provides internally gen-
April 23, 2010 Am29F160D_00_D10
erated program pulses and verify the programmed cell
margin. The Command Definitions take shows the address and data requirements for the byte program command sequence.
When the Embedded Program algorithm is complete,
the device then returns to reading array data and addresses are no longer latched. The system can determine the status of the program operation by using DQ7,
DQ6, or RY/BY#. See “Write Operation Status” for information on these status bits.
Any commands written to the device during the Embedded Program Algorithm are ignored. Note that a
hardware reset immediately terminates the programming operation. The program command sequence
should be reinitiated once the device resets to reading
array data, to ensure data integrity.
Programming is allowed in any sequence and across
sector boundaries. A bit cannot be programmed
from a “0” back to a “1”. Attempting to do so may halt
the operation and set DQ5 to “1”, or cause the Data#
Polling algorithm to indicate the operation was successful. However, a succeeding read shows that the
data is still “0”. Only erase operations can convert a “0”
to a “1”.
Unlock Bypass Command Sequence
The unlock bypass feature allows the system to program words to the device faster than using the standard program command sequence. The unlock bypass
command sequence is initiated by first writing two unlock cycles. This is followed by a third write cycle containing the unlock bypass command, 20h. The device
then enters the unlock bypass mode. A two-cycle unlock bypass program command sequence is all that is
required to program in this mode. The first cycle in this
sequence contains the unlock bypass program command, A0h; the second cycle contains the program
address and data. Additional data is programmed in
the same manner. This mode dispenses with the initial
two unlock cycles required in the standard program
command sequence, resulting in faster total programming time. Table 9 on page 22 shows the requirements for the command sequence.
During the unlock bypass mode, only the Unlock Bypass Program and Unlock Bypass Reset commands
are valid. To exit the unlock bypass mode, the system
must issue the two-cycle unlock bypass reset command sequence. The first cycle must contain the data
90h. The second cycle must contain the data 00h. The
device then returns to the read mode.
Am29F160D
19
DATA SHEET
The system can determine the status of the erase
operation by using DQ7, DQ6, DQ2, or RY/BY#. See
Write Operation Status‚ on page 23 for information
on these status bits. When the Embedded Erase algorithm is complete, the device returns to reading
array data and addresses are no longer latched.
START
Write Program
Command Sequence
Figure 4, on page 21 illustrates the algorithm for the
erase operation. See the Erase/Program Operations
tables in “AC Characteristics” for parameters, and to
the Chip/Sector Erase Operation Timings for timing
waveforms.
Data Poll
from System
Embedded
Program
algorithm
in progress
Sector Erase Command Sequence
Verify Data?
No
Yes
Increment Address
No
Last Address?
The device does not require the system to preprogram
the memory prior to erase. The Embedded Erase algorithm automatically programs and verifies the sector for
an all zero data pattern prior to electrical erase. The
system is not required to provide any controls or timings during these operations.
Yes
Programming
Completed
Note: See the appropriate Command Definitions table for
program command sequence.
Figure 3.
Program Operation
Chip Erase Command Sequence
Chip erase is a six-bus-cycle operation. The chip erase
command sequence is initiated by writing two unlock
cycles, followed by a set-up command. Two additional
unlock write cycles are then followed by the chip erase
command, which in turn invokes the Embedded Erase
algorithm. The device does not require the system to
preprogram prior to erase. The Embedded Erase algorithm automatically preprograms and verifies the entire
memory for an all zero data pattern prior to electrical
erase. The system is not required to provide any controls or timings during these operations. The Command
Definitions table shows the address and data requirements for the chip erase command sequence.
Any commands written to the chip during the Embedded Erase algorithm are ignored. Note that a hardware
reset during the chip erase operation immediately terminates the operation. The Chip Erase command sequence should be reinitiated once the device returns to
reading array data, to ensure data integrity.
20
Sector erase is a six bus cycle operation. The sector
erase command sequence is initiated by writing two unlock cycles, followed by a set-up command. Two additional unlock write cycles are then followed by the
address of the sector to be erased, and the sector
erase command. The Command Definitions table
shows the address and data requirements for the sector erase command sequence.
After the command sequence is written, a sector erase
time-out of 50 µs begins. During the time-out period,
additional sector addresses and sector erase commands may be written. Loading the sector erase buffer
may be done in any sequence, and the number of sectors may be from one sector to all sectors. The time between these additional cycles must be less than 50 µs,
otherwise the last address and command might not be
accepted, and erasure may begin. It is recommended
that processor interrupts be disabled during this time to
ensure all commands are accepted. The interrupts can
be re-enabled after the last Sector Erase command is
written. If the time between additional sector erase
commands can be assumed to be less than 50 µs, the
system need not monitor DQ3. Any command other
than Sector Erase or Erase Suspend during the
time-out period resets the device to reading array
data. The system must rewrite the command sequence
and any additional sector addresses and commands.
The system can monitor DQ3 to determine if the sector
erase timer has timed out. (See the DQ3: Sector Erase
Timer‚ on page 25 section.) The time-out begins from
the rising edge of the final WE# pulse in the command
sequence.
Once the sector erase operation begins, only the Erase
Suspend command is valid. All other commands are ignored. Note that a hardware reset during the sector
erase operation immediately terminates the operation.
Am29F160D
Am29F160D_00_D10 April 23, 2010
DATA SHEET
The Sector Erase command sequence should be reinitiated once the device returns to reading array data, to
ensure data integrity.
When the Embedded Erase algorithm is complete, the
device returns to reading array data and addresses are
no longer latched. The system can determine the status of the erase operation by using DQ7, DQ6, DQ2, or
RY/BY#. Refer to Write Operation Status‚ on page 23
for information on these status bits.
Figure 4, on page 21 illustrates the algorithm for the
erase operation. Refer to the Erase/Program Operations tables in the AC Characteristics‚ on page 31 for
parameters, and to the Sector Erase Operations Timing diagram for timing waveforms.
Erase Suspend/Erase Resume Commands
The Erase Suspend command allows the system to interrupt a sector erase operation and then read data
from, or program data to, any sector not selected for
erasure. This command is valid only during the sector
erase operation, including the 50 µs time-out period
during the sector erase command sequence. The
Erase Suspend command is ignored if written during
the chip erase operation or Embedded Program algorithm. Writing the Erase Suspend command during the
Sector Erase time-out immediately terminates the
time-out period and suspends the erase operation. Addresses are “don’t-cares” when writing the Erase Suspend command.
the status of the program operation using the DQ7 or
DQ6 status bits, just as in the standard program operation. See Write Operation Status‚ on page 23 for
more information.
The system may also write the autoselect command
sequence when the device is in the Erase Suspend
mode. The device allows reading autoselect codes
even at addresses within erasing sectors, since the
codes are not stored in the memory array. When the
device exits the autoselect mode, the device reverts to
the Erase Suspend mode, and is ready for another
valid operation. See Autoselect Command Sequence‚
on page 19 for more information.
The system must write the Erase Resume command
(address bits are “don’t care”) to exit the erase suspend
mode and continue the sector erase operation. Further
writes of the Resume command are ignored. Another
Erase Suspend command can be written after the device resumes erasing.
START
Write Erase
Command Sequence
When the Erase Suspend command is written during a
sector erase operation, the device requires a maximum
of 20 µs to suspend the erase operation. However,
when the Erase Suspend command is written during
the sector erase time-out, the device immediately terminates the time-out period and suspends the erase
operation.
After the erase operation is suspended, the system can
read array data from or program data to any sector not
selected for erasure. (The device “erase suspends” all
sectors selected for erasure.) Normal read and write
timings and command definitions apply. Reading at any
address within erase-suspended sectors produces status data on DQ7–DQ0. The system can use DQ7, or
DQ6 and DQ2 together, to determine if a sector is actively erasing or is erase-suspended. See Write Operation Status‚ on page 23 for information on these status
bits.
After an erase-suspended program operation is complete, the system can once again read array data within
non-suspended sectors. The system can determine
April 23, 2010 Am29F160D_00_D10
Data Poll
from System
No
Embedded
Erase
algorithm
in progress
Data = FFh?
Yes
Erasure Completed
1. See the appropriate Command Definitions table for erase
command sequence.
2. See DQ3: Sector Erase Timer‚ on page 25 for more information.
Am29F160D
Figure 4.
Erase Operation
21
DATA SHEET
Command Definitions
Table 9.
Cycles
Command
Sequence
(Note 1)
Read (Note 6)
Reset (Note 7)
Autoselect (Note 8)
Manufacturer ID
Device ID,
Top Boot Block
Device ID,
Bottom Boot Block
Sector Protect Verify
(Note 9)
1
1
Word
Byte
Word
Byte
Word
Byte
4
4
4
Word
First
Addr Data
Second
Addr Data
Bus Cycles (Notes 2–5)
Third
Fourth
Addr
Data Addr Data
RA
XXX
555
AAA
555
AAA
555
AAA
2AA
555
2AA
555
2AA
555
555
AAA
555
AAA
555
AAA
4
Word
Byte
Word
Program
Byte
Word
Unlock Bypass
Byte
Unlock Bypass Program (Note 11)
Unlock Bypass Reset (Note 12)
Word
Chip Erase
Byte
Word
Sector Erase
Byte
Erase Suspend (Note 13)
Erase Resume (Note 14)
AA
AA
AA
AA
4
3
2
2
6
6
1
1
555
AAA
555
AAA
555
AAA
XXX
XXX
555
AAA
555
AAA
XXX
XXX
55
55
55
2AA
AAA
1
Fifth
Addr Data
Sixth
Addr Data
2AA
555
2AA
555
55
555
AAA
10
55
SA
30
RD
F0
555
Byte
CFI Query (Note 10)
Am29F160D Command Definitions
90
90
90
555
55
90
555
AAA
X00
01
X01
X02
X01
X02
(SA)
X04
22D2
D2
22D8
D8
XX00
XX01
00
01
PA
PD
(SA)
X02
98
AA
AA
A0
90
AA
AA
2AA
555
2AA
555
PA
XXX
2AA
555
2AA
555
555
AAA
555
AAA
55
55
A0
20
PD
00
555
AAA
555
AAA
55
55
80
80
555
AAA
555
AAA
AA
AA
B0
30
Legend:
PD = Data to be programmed at location PA. Data latches on the
rising edge of WE# or CE# pulse, whichever happens first.
X = Don’t care
RA = Address of the memory location to be read.
RD = Data read from location RA during read operation.
PA = Address of the memory location to be programmed. Addresses
latch on the falling edge of the WE# or CE# pulse, whichever
happens later.
SA = Address of the sector to be verified (in autoselect mode) or
erased. Address bits A19–A12 uniquely select any sector.
Notes:
1. See Table 1 on page 8 for description of bus operations.
2. All values are in hexadecimal.
3. Except when reading array or autoselect data, all bus cycles are
write operations.
4. Data bits DQ15–DQ8 are don’t cares for unlock and command
cycles.
5. Address bits A19–A11 are don’t cares for unlock and command
cycles, unless SA or PA required.
6. No unlock or command cycles required when reading array data.
7. The Reset command is required to return to reading array data
when device is in the autoselect mode, CFI query mode, or if
DQ5 goes high (while the device is providing status data).
8. The fourth cycle of the autoselect command sequence is a read
cycle.
22
9. The data is 00h for an unprotected sector and 01h for a protected
sector. See Autoselect Command Sequence‚ on page 19 for
more information.
10. Command is valid when device is ready to read array data or
when device is in autoselect mode.
11. The Unlock Bypass command is required prior to the Unlock
Bypass Program command.
12. The Unlock Bypass Reset command is required to return to
reading array data when the device is in the unlock bypass mode.
13. The system may read and program in non-erasing sectors, or
enter the autoselect mode, when in the Erase Suspend mode.
The Erase Suspend command is valid only during a sector erase
operation.
14. The Erase Resume command is valid only during the
Erase Suspend mode.
Am29F160D
Am29F160D_00_D10 April 23, 2010
DATA SHEET
WRITE OPERATION STATUS
The device provides several bits to determine the status of a write operation: DQ2, DQ3, DQ5, DQ6, DQ7,
and RY/BY#. Table 10 on page 26 and the following
subsections describe the functions of these bits. DQ7,
RY/BY#, and DQ6 each offer a method for determining
whether a program or erase operation is complete or in
progress. These three bits are discussed first.
Table 10 on page 26 shows the outputs for Data# Polling on DQ7. Figure 5 shows the Data# Polling algorithm.
START
DQ7: Data# Polling
The Data# Polling bit, DQ7, indicates to the host
system whether an Embedded Algor ithm is in
progress or completed, or whether the device is in
Erase Suspend. Data# Polling is valid after the rising
edge of the final WE# pulse in the program or erase
command sequence.
During the Embedded Program algorithm, the device
outputs on DQ7 the complement of the datum programmed to DQ7. This DQ7 status also applies to programming during Erase Suspend. When the
Embedded Program algorithm is complete, the device
outputs the datum programmed to DQ7. The system
must provide the program address to read valid status
information on DQ7. If a program address falls within a
protected sector, Data# Polling on DQ7 is active for approximately 2 µs, then the device returns to reading
array data.
Read DQ7–DQ0
Addr = VA
DQ7 = Data?
No
No
When the system detects DQ7 changes from the complement to true data, it can read valid data at DQ7–
DQ0 on the following read cycles. This is because DQ7
may change asynchronously with DQ0–DQ6 while
Output Enable (OE#) is asserted low. The Data# Polling Timings (During Embedded Algorithms) figure in
the “AC Characteristics” section illustrates this.
April 23, 2010 Am29F160D_00_D10
DQ5 = 1?
Yes
Read DQ7–DQ0
Addr = VA
During the Embedded Erase algorithm, Data# Polling
produces a “0” on DQ7. When the Embedded Erase algorithm is complete, or if the device enters the Erase
Suspend mode, Data# Polling produces a “1” on DQ7.
This is analogous to the complement/true datum output
described for the Embedded Program algorithm: the
erase function changes all the bits in a sector to “1”;
prior to this, the device outputs the “complement,” or
“0.” The system must provide an address within any of
the sectors selected for erasure to read valid status information on DQ7.
After an erase command sequence is written, if all sectors selected for erasing are protected, Data# Polling
on DQ7 is active for approximately 100 µs, then the device returns to reading array data. If not all selected
sectors are protected, the Embedded Erase algorithm
erases the unprotected sectors, and ignores the selected sectors that are protected.
Yes
DQ7 = Data?
Yes
No
FAIL
PASS
Notes:
1. VA = Valid address for programming. During a sector
erase operation, a valid address is an address within any
sector selected for erasure. During chip erase, a valid
address is any non-protected sector address.
2. DQ7 should be rechecked even if DQ5 = “1” because
DQ7 may change simultaneously with DQ5.
Am29F160D
Figure 5.
Data# Polling Algorithm
23
DATA SHEET
RY/BY#: Ready/Busy#
The RY/BY# is a dedicated, open-drain output pin that
indicates whether an Embedded Algorithm is in
progress or complete. The RY/BY# status is valid after
the rising edge of the final WE# pulse in the command
sequence. Since RY/BY# is an open-drain output, several RY/BY# pins can be tied together in parallel with a
pull-up resistor to VCC.
If the output is low (Busy), the device is actively erasing
or programming. (This includes programming in the
Erase Suspend mode.) If the output is high (Ready),
the device is ready to read array data (including during
the Erase Suspend mode), or is in the standby mode.
Table 10 on page 26 shows the outputs for RY/BY#.
The timing diagrams for read, reset, program, and
erase shows the relationship of RY/BY# to other signals.
DQ6: Toggle Bit I
Toggle Bit I on DQ6 indicates whether an Embedded
Program or Erase algorithm is in progress or complete,
or whether the device entered the Erase Suspend
mode. Toggle Bit I may be read at any address, and is
valid after the rising edge of the final WE# pulse in the
command sequence (prior to the program or erase operation), and during the sector erase time-out.
During an Embedded Program or Erase algorithm operation, successive read cycles to any address cause
DQ6 to toggle. (The system may use either OE# or
CE# to control the read cycles.) When the operation is
complete, DQ6 stops toggling.
After an erase command sequence is written, if all
sectors selected for erasing are protected, DQ6 toggles for approximately 100 µs, then returns to reading
array data. If not all selected sectors are protected,
the Embedded Erase algorithm erases the unprotected sectors, and ignores the selected sectors that
are protected.
The system can use DQ6 and DQ2 together to determine whether a sector is actively erasing or is erasesuspended. When the device is actively erasing (that is,
the Embedded Erase algorithm is in progress), DQ6
toggles. When the device enters the Erase Suspend
mode, DQ6 stops toggling. However, the system must
also use DQ2 to determine which sectors are erasing
or erase-suspended. Alternatively, the system can use
DQ7 (see the subsection on DQ7: Data# Polling‚ on
page 23).
If a program address falls within a protected sector,
DQ6 toggles for approximately 2 µs after the program
command sequence is written, then returns to reading
array data.
24
DQ6 also toggles during the erase-suspend-program
mode, and stops toggling once the Embedded Program algorithm is complete.
The Write Operation Status table shows the outputs for
Toggle Bit I on DQ6. Refer to Figure 6, on page 25 for
the toggle bit algorithm, and to the Toggle Bit Timings
figure in the “AC Characteristics” section for the timing
diagram. The DQ2 vs. DQ6 figure shows the differences between DQ2 and DQ6 in graphical form. See
also the subsection on DQ2: Toggle Bit II‚ on page 24.
DQ2: Toggle Bit II
The “Toggle Bit II” on DQ2, when used with DQ6, indicates whether a particular sector is actively erasing
(that is, the Embedded Erase algorithm is in progress),
or whether that sector is erase-suspended. Toggle Bit
II is valid after the rising edge of the final WE# pulse in
the command sequence.
DQ2 toggles when the system reads at addresses
within those sectors that were selected for erasure.
(The system may use either OE# or CE# to control the
read cycles.) But DQ2 cannot distinguish whether the
sector is actively erasing or is erase-suspended. DQ6,
by comparison, indicates whether the device is actively
erasing, or is in Erase Suspend, but cannot distinguish
which sectors are selected for erasure. Thus, both status bits are required for sector and mode information.
Refer to Table 10 on page 26 to compare outputs for
DQ2 and DQ6.
Figure 6, on page 25 shows the toggle bit algorithm in
flowchart form, and the section “DQ2: Toggle Bit II” explains the algorithm. See also the “DQ6: Toggle Bit I”
subsection. Refer to the Toggle Bit Timings figure for
the toggle bit timing diagram. The DQ2 vs. DQ6 figure
shows the differences between DQ2 and DQ6 in graphical form.
Reading Toggle Bits DQ6/DQ2
Refer to Figure 6, on page 25 for the following discussion. Whenever the system initially begins reading
toggle bit status, it must read DQ7–DQ0 at least twice
in a row to determine whether a toggle bit is toggling.
Typically, a system would note and store the value of
the toggle bit after the first read. After the second
read, the system would compare the new value of the
toggle bit with the first. If the toggle bit is not toggling,
the device completed the program or erase operation.
The system can read array data on DQ7–DQ0 on the
following read cycle.
However, if after the initial two read cycles, the system
determines that the toggle bit is still toggling, the
system also should note whether the value of DQ5 is
high (see the section on DQ5). If it is, the system
should then determine again whether the toggle bit is
toggling, since the toggle bit may have stopped toggling just as DQ5 went high. If the toggle bit is no longer
Am29F160D
Am29F160D_00_D10 April 23, 2010
DATA SHEET
toggling, the device successfully completed the
program or erase operation. If it is still toggling, the
device did not complete the operation successfully, and
the system must write the reset command to return to
reading array data.
The remaining scenario is that the system initially determines that the toggle bit is toggling and DQ5 has not
gone high. The system may continue to monitor the
toggle bit and DQ5 through successive read cycles, determining the status as described in the previous paragraph. Alternatively, it may choose to perform other
system tasks. In this case, the system must start at the
beginning of the algorithm when it returns to determine
the status of the operation (top of Figure 6).
mands. To ensure the command is accepted, the system software should check the status of DQ3 prior to
and following each subsequent sector erase command.
If DQ3 is high on the second status check, the last command might not have been accepted. Table 10 on
page 26 shows the outputs for DQ3.
START
Read DQ7–DQ0
DQ5: Exceeded Timing Limits
DQ5 indicates whether the program or erase time exceeded a specified internal pulse count limit. Under
these conditions DQ5 produces a “1.” This is a failure
condition that indicates the program or erase cycle was
not successfully completed.
The DQ5 failure condition may appear if the system
tries to program a “1” to a location that is previously programmed to “0.” Only an erase operation can change
a “0” back to a “1.” Under this condition, the device
halts the operation, and when the operation exceeds
the timing limits, DQ5 produces a “1.”
No
Toggle Bit
= Toggle?
No
DQ5 = 1?
Yes
DQ3: Sector Erase Timer
Read DQ7–DQ0
Twice
After writing a sector erase command sequence, the
system may read DQ3 to determine whether or not an
erase operation begun. (The sector erase timer does
not apply to the chip erase command.) If additional
sectors are selected for erasure, the entire time-out
also applies after each additional sector erase command. When the time-out is complete, DQ3 switches
from “0” to “1.” The system may ignore DQ3 if the system can guarantee that the time between additional
sector erase commands is always less than 50 µs.
See also the Sector Erase Command Sequence‚ on
page 20 section.
April 23, 2010 Am29F160D_00_D10
(Note 1)
Yes
Under both these conditions, the system must issue the
reset command to return the device to reading array
data.
After the sector erase command sequence is written,
the system should read the status on DQ7 (Data# Polling) or DQ6 (Toggle Bit I) to ensure the device accepted
the command sequence, and then read DQ3. If DQ3 is
“1”, the internally controlled erase cycle started; all further commands (other than Erase Suspend) are ignored until the erase operation is complete. If DQ3 is
“0”, the device accepts additional sector erase com-
Read DQ7–DQ0
Toggle Bit
= Toggle?
(Notes
1, 2)
No
Yes
Program/Erase
Operation Not
Complete, Write
Reset Command
Program/Erase
Operation Complete
Notes:
1. Read toggle bit twice to determine whether or not it is
toggling. See text.
2. Recheck toggle bit because it may stop toggling as DQ5
changes to “1”. See text.
Am29F160D
Figure 6. Toggle Bit Algorithm
25
DATA SHEET
Table 10.
DQ7
(Note 1)
DQ6
DQ5
(Note 2)
DQ3
DQ2
(Note 1)
RY/BY#
DQ7#
Toggle
0
N/A
No toggle
0
0
Toggle
0
1
Toggle
0
1
No toggle
0
N/A
Toggle
1
Reading within Non-Erase
Suspended Sector
Data
Data
Data
Data
Data
1
Erase-Suspend-Program
DQ7#
Toggle
0
N/A
N/A
0
Operation
Standard
Mode
Erase
Suspend
Mode
Write Operation Status
Embedded Program Algorithm
Embedded Erase Algorithm
Reading within Erase
Suspended Sector
Notes:
1. DQ7 and DQ2 require a valid address when reading status information. Refer to the appropriate subsection for further details.
2. DQ5 switches to ‘1’ when an Embedded Program or Embedded Erase operation exceeds the maximum timing limits. See
DQ5: Exceeded Timing Limits‚ on page 25 for more information.
26
Am29F160D
Am29F160D_00_D10 April 23, 2010
DATA SHEET
ABSOLUTE MAXIMUM RATINGS
Storage Temperature
Plastic Packages . . . . . . . . . . . . . . .–65° C to +150° C
Ambient Temperature
with Power Applied. . . . . . . . . . . . . .–55° C to +125° C
20 ns
20 ns
+0.8 V
Voltage with Respect to Ground
VCC (Note 1) . . . . . . . . . . . . . . . . –2.0 V to +7.0 V
–0.5 V
A9, OE#, and
RESET# (Note 2). . . . . . . . . . . .–2.0 V to +12.5 V
–2.0 V
All other pins (Note 1) . . . . . . . . . –0.5 V to +7.0 V
20 ns
Output Short Circuit Current (Note 3) . . . . . . 200 mA
Figure 7. Maximum Negative
Overshoot Waveform
Notes:
1. Minimum DC voltage on input or I/O pins is –0.5 V. During
voltage transitions, input or I/O pins may undershoot VSS
to –2.0 V for periods of up to 20 ns. See Figure 7.
Maximum DC voltage on input or I/O pins is VCC +0.5 V.
During voltage transitions, input or I/O pins may overshoot
to VCC +2.0 V for periods up to 20 ns. See Figure 8.
2. Minimum DC input voltage on pins A9, OE#, and RESET#
is –0.5 V. During voltage transitions, A9, OE#, and
RESET# may undershoot VSS to –2.0 V for periods of up
to 20 ns. See Figure 7. Maximum DC input voltage on pin
A9 is +12.5 V which may overshoot to +13.5 V for periods
up to 20 ns.
3. No more than one output may be shorted to ground at a
time. Duration of the short circuit should not be greater
than one second.
20 ns
VCC
+2.0 V
VCC
+0.5 V
2.0 V
Note: Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device. This is
a stress rating only; functional operation of the device at
these or any other conditions above those indicated in the
operational sections of this data sheet is not implied.
Exposure of the device to absolute maximum rating
conditions for extended periods may affect device reliability.
20 ns
20 ns
Figure 8. Maximum Positive
Overshoot Waveform
OPERATING RANGES
Industrial (I) Devices
Ambient Temperature (TA) . . . . . . . . . –40°C to +85°C
Extended (E) Devices
Ambient Temperature (TA) . . . . . . . . . –40°C to +110°C
VCC Supply Voltages
VCC for ±5% devices . . . . . . . . . . .+4.75 V to +5.25 V
VCC for ±10% devices . . . . . . . . . . . .+4.5 V to +5.5 V
Note: Operating ranges define those limits between which
the functionality of the device is guaranteed.
April 23, 2010 Am29F160D_00_D10
Am29F160D
27
DATA SHEET
DC CHARACTERISTICS
TTL/NMOS Compatible
Parameter
Description
Test Conditions
ILI
Input Load Current
VIN = VSS to VCC, VCC = VCC max
ILIT
A9, OE#, RESET Input Load Current
VCC = VCC max;
A9 = OE# = RESET# = 12.5 V
ILO
Output Leakage Current
VOUT = VSS to VCC
ICC1
VCC Active Read Current
(Notes 1, 2)
Min
CE# = VIL, OE# = VIH,
f = 5 MHz, Byte Mode
CE# = VIL, OE# = VIH,
f = 5 MHz, Word Mode
Typ
Max
Unit
±1.0
µA
35
µA
±1.0
µA
15
40
mA
15
50
mA
ICC2
VCC Active Write Current
(Notes 2, 3 and 4)
CE# = VIL, OE# = VIH
35
50
mA
ICC3
VCC Standby Current (Notes 2, 5)
CE#, OE#, and RESET# = VIH
0.4
1
mA
VIL
Input Low Voltage
–0.5
0.8
V
VIH
Input High Voltage
2.0
VCC
+ 0.5
V
VID
Voltage for Autoselect and Temporary
Sector Unprotect
VCC = 5.0 V
11.5
12.5
V
VOL
Output Low Voltage
IOL = 5.8 mA, VCC = VCC min
0.45
V
VOH
Output High Voltage
IOH = –2.5 mA, VCC = VCC min
VLKO
Low VCC Lock-Out Voltage (Note 4)
2.4
3.2
V
4.2
V
Notes:
1. The ICC current listed is typically less than 2 mA/MHz, with OE# at VIH.
2. Maximum ICC specifications are tested with VCC = VCCmax
3. ICC active while Embedded Erase or Embedded Program is in progress.
4. Not 100% tested.
5. ICC3 = 20 µA max at extended temperature (>+85°C)
28
Am29F160D
Am29F160D_00_D10 April 23, 2010
DATA SHEET
DC CHARACTERISTICS
CMOS Compatible
Parameter
Description
Test Conditions
ILI
Input Load Current
VIN = VSS to VCC,
VCC = VCC max
ILIT
A9, OE#, RESET Input Load Current
VCC = VCC max,
A9 = OE# = RESET = 12.5 V
ILO
Output Leakage Current
VOUT = VSS to VCC,
VCC = VCC max
ICC1
VCC Active Read Current
(Note 2)
Min
Typ
Max
Unit
±1.0
µA
35
µA
±1.0
µA
CE# = VIL, OE# = VIH,
f = 5 MHz
Byte Mode
15
40
mA
CE# = VIL, OE# = VIH,
f = 5 MHz
Word Mode
15
50
mA
ICC2
VCC Active Write Current
(Notes 1, 2, 3)
CE# = VIL, OE# = VIH
35
50
mA
ICC3
VCC Standby Current (Note 2)
CE# and RESET# = VCC±0.5 V, WP#
= VCC±0.5 V or floating, OE# = VIH
0.3
5
µA
VIL
Input Low Voltage
–0.5
0.8
V
VIH
Input High Voltage
0.7 x VCC
VCC + 0.3
V
VID
Voltage for Autoselect and
Temporary Sector Unprotect
VCC = 5.0 V
11.5
12.5
V
VOL
Output Low Voltage
IOL = 5.8 mA, VCC = VCC min
0.45
V
VOH1
Output High Voltage
VOH2
VLKO
IOH = –2.5 mA, VCC = VCC min
0.85 VCC
V
IOH = –100 µA, VCC = VCC min
VCC–0.4
V
Low VCC Lock-Out Voltage (Note 3)
3.2
4.2
V
Notes:
1. ICC active while Embedded Erase or Embedded Program is in progress.
2. Maximum ICC specifications are tested with VCC = VCCmax
3. Not 100% tested.
April 23, 2010 Am29F160D_00_D10
Am29F160D
29
DATA SHEET
TEST CONDITIONS
Table 11.
Test Specifications
5.0 V
Test Condition
2.7 kΩ
Device
Under
Test
CL
6.2 kΩ
Output Load
Figure 9.
90
Unit
1 TTL gate
Output Load Capacitance, CL
(including jig capacitance)
30
100
pF
Input Rise and Fall Times
5
20
ns
0.0–3.0
0.45–2.4
V
Input timing measurement
reference levels
1.5
0.8, 2.0
V
Output timing measurement
reference levels
1.5
0.8, 2.0
V
Input Pulse Levels
Note:
Diodes are IN3064 or equivalents.
70, 75
Test Setup
KEY TO SWITCHING WAVEFORMS
WAVEFORM
INPUTS
OUTPUTS
Steady
Changing from H to L
Changing from L to H
30
Don’t Care, Any Change Permitted
Changing, State Unknown
Does Not Apply
Center Line is High Impedance State (High Z)
Am29F160D
Am29F160D_00_D10 April 23, 2010
DATA SHEET
AC CHARACTERISTICS
Read Operations
Parameter
Speed Option
JEDEC
Std.
Description
tAVAV
tRC
Read Cycle Time (Note 1)
tAVQV
tACC
Address to Output Delay
tELQV
tCE
Chip Enable to Output Delay
tGLQV
tOE
tEHQZ
tGHQZ
tAXQX
Test Setup
70, 75
90
Unit
Min
70
90
ns
CE# = VIL
OE# = VIL
Max
70
90
ns
OE# = VIL
Max
70
90
ns
Output Enable to Output Delay
Max
30
35
ns
tDF
Chip Enable to Output High Z (Note 1)
Max
20
20
ns
tDF
Output Enable to Output High Z
(Note 1)
Max
20
20
ns
Read
Min
0
ns
Toggle and
Data# Polling
Min
10
ns
Min
0
ns
tOEH
Output Enable
Hold Time
(Note 1)
tOH
Output Hold Time From Addresses, CE# or OE#,
Whichever Occurs First (Note 1)
Notes:
1. Not 100% tested.
2. See Figure 9, on page 30 and Table 11 on page 30 for test specifications.
tRC
Addresses Stable
Addresses
tACC
CE#
tDF
tOE
OE#
tOEH
WE#
tCE
tOH
HIGH Z
HIGH Z
Output Valid
Outputs
RESET#
RY/BY#
0V
Figure 10.
April 23, 2010 Am29F160D_00_D10
Read Operations Timings
Am29F160D
31
DATA SHEET
AC CHARACTERISTICS
Hardware Reset (RESET#)
Parameter
JEDEC
Std
Description
Test Setup
All Speed Options
Unit
tREADY
RESET# Pin Low (During Embedded Algorithms)
to Read or Write (See Note)
Max
20
µs
tREADY
RESET# Pin Low (NOT During Embedded
Algorithms) to Read or Write (See Note)
Max
500
ns
tRP
RESET# Pulse Width
Min
500
ns
tRH
RESET# High Time Before Read (See Note)
Min
50
ns
tRB
RY/BY# Recovery Time
Min
0
ns
Note: Not 100% tested.
RY/BY#
CE#, OE#
tRH
RESET#
tRP
tReady
Reset Timings NOT during Embedded Algorithms
Reset Timings during Embedded Algorithms
tReady
RY/BY#
tRB
CE#, OE#
RESET#
tRP
Figure 11.
32
RESET# Timings
Am29F160D
Am29F160D_00_D10 April 23, 2010
DATA SHEET
AC CHARACTERISTICS
Word/Byte Configuration (BYTE#)
Parameter
JEDEC
Std.
tELFL/tELFH
Speed Options
Description
70, 75
90
5
Unit
CE# to BYTE# Switching Low or High
Max
ns
tFLQZ
BYTE# Switching Low to Output HIGH Z
Max
20
20
ns
tFHQV
BYTE# Switching High to Output Active
Min
70
90
ns
CE#
OE#
BYTE#
tELFL
BYTE#
Switching
from word
to byte
mode
Data Output
(DQ0–DQ7)
Data Output
(DQ0–DQ14)
DQ0–DQ14
Address
Input
DQ15
Output
DQ15/A-1
tFLQZ
tELFH
BYTE#
BYTE#
Switching
from byte to
word mode
Data Output
(DQ0–DQ7)
DQ0–DQ14
Address
Input
DQ15/A-1
Data Output
(DQ0–DQ14)
DQ15
Output
tFHQV
Figure 12.
BYTE# Timings for Read Operations
CE#
The falling edge of the last WE# signal
WE#
BYTE#
tSET
(tAS)
tHOLD (tAH)
Note: Refer to the Erase/Program Operations table for tAS and tAH specifications.
Figure 13.
April 23, 2010 Am29F160D_00_D10
BYTE# Timings for Write Operations
Am29F160D
33
DATA SHEET
AC CHARACTERISTICS
Erase/Program Operations
Parameter
Speed Options
JEDEC
Std.
Description
tAVAV
tWC
Write Cycle Time (Note 1)
Min
tAVWL
tAS
Address Setup Time
Min
tWLAX
tAH
Address Hold Time
Min
45
45
ns
tDVWH
tDS
Data Setup Time
Min
30
45
ns
tWHDX
tDH
Data Hold Time
Min
0
ns
tOES
Output Enable Setup Time
Min
0
ns
Read Recovery Time Before Write
(OE# High to WE# Low)
Min
0
ns
70, 75
90
Unit
70
90
ns
0
ns
tGHWL
tGHWL
tELWL
tCS
CE# Setup Time
Min
0
ns
tWHEH
tCH
CE# Hold Time
Min
0
ns
tWLWH
tWP
Write Pulse Width
Min
tWHWL
tWPH
Write Pulse Width High
Min
20
Byte
Typ
7
tWHWH1
tWHWH1
Programming Operation (Note 2)
Word
Typ
12
tWHWH2
tWHWH2
Sector Erase Operation (Note 2)
Typ
1
sec
tVCS
VCC Setup Time (Note 1)
Min
50
µs
tRB
Recovery Time from RY/BY#
Min
0
ns
Program/Erase Valid to RY/BY# Delay
Max
tBUSY
35
45
ns
ns
µs
30
35
ns
Notes:
1. Not 100% tested.
2. See Erase and Programming Performance‚ on page 42 for more information.
34
Am29F160D
Am29F160D_00_D10 April 23, 2010
DATA SHEET
AC CHARACTERISTICS
Program Command Sequence (last two cycles)
tAS
tWC
Addresses
555h
Read Status Data (last two cycles)
PA
PA
PA
tAH
CE#
tCH
OE#
tWHWH1
tWP
WE#
tWPH
tCS
tDS
tDH
A0h
Data
PD
Status
tBUSY
DOUT
tRB
RY/BY#
tVCS
VCC
Notes:
1. PA = program address, PD = program data, DOUT is the true data at the program address.
2. Illustration shows device in word mode.
Figure 14.
April 23, 2010 Am29F160D_00_D10
Program Operation Timings
Am29F160D
35
DATA SHEET
AC CHARACTERISTICS
Erase Command Sequence (last two cycles)
tAS
tWC
Addresses
Read Status Data
2AAh
VA
SA
555h for chip erase
VA
tAH
CE#
tCH
OE#
tWP
WE#
tWPH
tCS
tWHWH2
tDS
tDH
Data
55h
In
Progress
30h
Complete
10 for Chip Erase
tBUSY
tRB
RY/BY#
tVCS
VCC
Notes:
1. SA = sector address (for Sector Erase), VA = Valid Address for reading status data (see Write Operation Status‚ on page 23).
2. Illustration shows device in word mode.
Figure 15.
36
Chip/Sector Erase Operation Timings
Am29F160D
Am29F160D_00_D10 April 23, 2010
DATA SHEET
AC CHARACTERISTICS
tRC
Addresses
VA
VA
VA
tACC
tCE
CE#
tCH
tOE
OE#
tOEH
tDF
WE#
tOH
DQ7
Complement
Complement
DQ0–DQ6
Status Data
Status Data
Valid Data
True
Valid Data
True
High Z
High Z
tBUSY
RY/BY#
Note:
VA = Valid address. Illustration shows first status cycle after command sequence, last status read cycle, and array data read cycle.
Figure 16.
Data# Polling Timings (During Embedded Algorithms)
tRC
Addresses
VA
VA
VA
VA
tACC
tCE
CE#
tCH
tOE
OE#
tOEH
tDF
WE#
tOH
High Z
DQ6/DQ2
tBUSY
Valid Status
Valid Status
(first read)
(second read)
Valid Status
Valid Data
(stops toggling)
RY/BY#
Note:
VA = Valid address; not required for DQ6. Illustration shows first two status cycle after command sequence, last status read cycle,
and array data read cycle.
Figure 17.
April 23, 2010 Am29F160D_00_D10
Toggle Bit Timings (During Embedded Algorithms)
Am29F160D
37
DATA SHEET
AC CHARACTERISTICS
Enter
Embedded
Erasing
Erase
Suspend
Erase
WE#
Enter Erase
Suspend Program
Erase
Resume
Erase
Suspend
Program
Erase Suspend
Read
Erase
Complete
Erase
Erase Suspend
Read
DQ6
DQ2
Note: The system may use OE# or CE# to toggle DQ2 and DQ6. DQ2 toggles only when read at an address within the
erase-suspended sector.
Figure 18. DQ2 vs. DQ6
Temporary Sector Unprotect
Parameter
JEDEC
Std.
Description
tVIDR
VID Rise and Fall Time (See Note)
tRSP
RESET# Setup Time for Temporary Sector
Unprotect
All Speed Options
Unit
Min
500
ns
Min
4
µs
Note: Not 100% tested.
12 V
RESET#
0 or 5 V
0 or 5 V
tVIDR
tVIDR
Program or Erase Command Sequence
CE#
WE#
tRSP
RY/BY#
Figure 19.
38
Temporary Sector Unprotect Timing Diagram
Am29F160D
Am29F160D_00_D10 April 23, 2010
DATA SHEET
AC CHARACTERISTICS
VID
VIH
RESET#
SA, A6,
A1, A0
Valid*
Valid*
Sector Protect/Unprotect
Data
60h
Valid*
Verify
60h
40h
Status
Sector Protect: 150 µs
Sector Unprotect: 15 ms
1 µs
CE#
WE#
OE#
Note: For sector protect, A6 = 0, A1 = 1, A0 = 0. For sector unprotect, A6 = 1, A1 = 1, A0 = 0.
Figure 20.
April 23, 2010 Am29F160D_00_D10
Sector Protect/Unprotect
Timing Diagram
Am29F160D
39
DATA SHEET
AC CHARACTERISTICS
Alternate CE# Controlled Erase/Program Operations
Parameter
Speed Options
JEDEC
Std.
Description
tAVAV
tWC
Write Cycle Time (Note 1)
Min
tAVEL
tAS
Address Setup Time
Min
tELAX
tAH
Address Hold Time
Min
45
45
ns
tDVEH
tDS
Data Setup Time
Min
30
45
ns
tEHDX
tDH
Data Hold Time
Min
0
ns
tOES
Output Enable Setup Time
Min
0
ns
tGHEL
tGHEL
Read Recovery Time Before Write
(OE# High to WE# Low)
Min
0
ns
tWLEL
tWS
WE# Setup Time
Min
0
ns
tEHWH
tWH
WE# Hold Time
Min
0
ns
tELEH
tCP
CE# Pulse Width
Min
tEHEL
tCPH
CE# Pulse Width High
Min
20
Typ
7
tWHWH1
Programming Operation
(Note 2)
Byte
tWHWH1
Word
Typ
12
tWHWH2
tWHWH2
Sector Erase Operation (Note 2)
Typ
1
70, 75
90
Unit
70
90
ns
0
35
ns
45
ns
ns
µs
sec
Notes:
1. Not 100% tested.
2. See Erase and Programming Performance‚ on page 42 for more information.
40
Am29F160D
Am29F160D_00_D10 April 23, 2010
DATA SHEET
AC CHARACTERISTICS
555 for program
2AA for erase
PA for program
SA for sector erase
555 for chip erase
Data# Polling
Addresses
PA
tWC
tAS
tAH
tWH
WE#
tGHEL
OE#
tWHWH1 or 2
tCP
CE#
tWS
tCPH
tBUSY
tDS
tDH
DQ7#
Data
tRH
A0 for program
55 for erase
DOUT
PD for program
30 for sector erase
10 for chip erase
RESET#
RY/BY#
Notes:
1. PA = Program Address, PD = Program Data, SA = Sector Address, DQ7# = Complement of Data Input, DOUT = Array Data.
2. Figure indicates the last two bus cycles of the command sequence, with the device in word mode.
Figure 21.
April 23, 2010 Am29F160D_00_D10
Alternate CE# Controlled Write Operation Timings
Am29F160D
41
DATA SHEET
ERASE AND PROGRAMMING PERFORMANCE
Parameter
Typ (Note 1)
Max (Note 3)
Unit
Comments
Sector Erase Time
1.0
8
s
Chip Erase Time (Note 2)
25
Excludes 00h programming prior
to erasure (Note 4)
Byte Programming Time
7
300
µs
Word Programming Time
11
360
µs
Chip Programming Time
Byte Mode
15
45
s
(Note 2)
Word Mode
12
35
s
s
Excludes system level overhead
(Note 5)
Notes:
1. Typical program and erase times assume the following conditions: 25° C, 5.0 V VCC, 1,000,000 cycles. Additionally,
programming typicals assume checkerboard pattern.
2. Under worst case conditions of 90°C, VCC = 4.5 V, 1,000,000 cycles.
3. The typical chip programming time is considerably less than the maximum chip programming time listed, since most bytes
program faster than the maximum program times listed.
4. In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h before erasure.
5. System-level overhead is the time required to execute the four-bus-cycle sequence for the program command. See Table 9
for further information on command definitions.
6. The device has a guaranteed minimum erase and
program cycle endurance of 1,000,000 cycles.
LATCHUP CHARACTERISTICS
Description
Min
Max
Input voltage with respect to VSS on all pins except I/O pins
(including A9, OE#, and RESET#)
–1.0 V
12.5 V
Input voltage with respect to VSS on all I/O pins
–1.0 V
VCC + 1.0 V
–100 mA
+100 mA
VCC Current
Includes all pins except VCC. Test conditions: VCC = 5.0 V, one pin at a time.
TSOP AND SO PIN CAPACITANCE
Parameter Symbol
Parameter Description
Test Setup
Typ
Max
Unit
CIN
Input Capacitance
VIN = 0
6
7.5
pF
COUT
Output Capacitance
VOUT = 0
8.5
12
pF
CIN2
Control Pin Capacitance
VIN = 0
7.5
9
pF
Notes:
1. Sampled, not 100% tested.
2. Test conditions TA = 25°C, f = 1.0 MHz.
DATA RETENTION
Parameter
Test Conditions
Min
Unit
150° C
10
Years
125° C
20
Years
Minimum Pattern Data Retention Time
42
Am29F160D
Am29F160D_00_D10 April 23, 2010
DATA SHEET
PHYSICAL DIMENSIONS
TS 048—48-Pin Standard Thin Small Outline Package
Dwg rev AA; 10/99
April 23, 2010 Am29F160D_00_D10
Am29F160D
43
DATA SHEET
REVISION SUMMARY
Revision C (November 16, 1999)
Revision A (January 1999)
AC Characteristics—Figure 14. Program
Operations Timing and Figure 15. Chip/Sector
Erase Operations
Initial release.
Deleted tGHWL and changed OE# waveform to start at
high.
Revision B (June 14, 1999)
Global
Physical Dimensions
Expanded data sheet into document with full specifications.
Replaced figures with more detailed illustrations.
Deleted the 55 ns speed options.
Revision D (December 4, 2000)
Distinctive Characteristics
Removed Advance Information status from document.
In the Ultra Low Power Consumption bullets, changed
the typical current to match the DC specifications
(CMOS Compatible) table.
Ordering Information
Deleted optional processing.
Table 9, Command Definitions
Revision B+1 (July 7, 1999)
In Note 5, changed the lower address bit in don’t care
range to A11.
Connection Diagrams
Corrected the signals on pins 39 and 40 of the reverse
TSOP package.
Revision B+2 (July 14, 1999)
Table 11, Test Specifications
Changed capacitive loading on 70 ns speed option to
30 pF.
Revision D+1 (November 18, 2003)
Global
Changed the VCC operating range of the 70 ns speed
option to 5.0 V ± 5%. Deleted all references to uniform
sector.
Global
Added “70” speed option (70 ns, VCC = 5.0 V ± 10%).
Command Definitions table
Revision D+2 (October 29, 2004)
In Note 7, added a reference to CFI query mode.
Added Pb-Free option.
Revision B+3 (July 30, 1999)
Revision D+3 (April 4, 2005)
Global
Distinctive Characteristics
Changed the part number designator for the 70 ns
speed option to 75 (with VCC rated at 5.0 V ± 5%).
Changed µm process technology number.
DC Characteristics
Global
TTL/NMOS Compatible table: Changed the maximum
current specification for ICC2 to 50 mA.
Changed WP# terminology throughout the data sheet.
Changed terminology in WP# input pin description.
Revision D4 (December 23, 2005)
Revision B+4 (September 10, 1999)
Global
Device Bus Operations
Deleted reverse TSOP package option and 120 ns
speed option.
Write Protect (WP#): Clarified explanatory text.
Command Definitions
Autoselect Command Sequence: Added text and table
explaining effect of WP# input on autoselect code
output for 16 Kbyte boot sector.
Revision D5 (May 19, 2006)
Added “Not recommended for new designs” note.
AC Characteristics
Changed tBUSY specification to maximium value.
Revision D6 (November 2, 2006)
Deleted “Not recommended for new designs” note.
44
Am29F160D
Am29F160D_00_D10 April 23, 2010
DATA SHEET
Revision D7 (March 5, 2009)
Revision D10 (April 23, 2010)
Global
Global
Added obsolescence information.
Added Extended Temperature Range option.
Revision D8 (August 3, 2009)
Global
Removed obsolescence information.
Revision D9 (November 17, 2009)
Global
Removed all commercial temperature range options.
Colophon
The products described in this document are designed, developed and manufactured as contemplated for general use, including without
limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as
contemplated (1) for any use that includes fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the
public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility,
aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for
any use where chance of failure is intolerable (i.e., submersible repeater and artificial satellite). Please note that Spansion will not be liable to
you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor
devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design
measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal
operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under
the Foreign Exchange and Foreign Trade Law of Japan, the US Export Administration Regulations or the applicable laws of any other country,
the prior authorization by the respective government entity will be required for export of those products.
Trademarks and Notice
The contents of this document are subject to change without notice. This document may contain information on a Spansion product under
development by Spansion. Spansion reserves the right to change or discontinue work on any product without notice. The information in this
document is provided as is without warranty or guarantee of any kind as to its accuracy, completeness, operability, fitness for particular purpose,
merchantability, non-infringement of third-party rights, or any other warranty, express, implied, or statutory. Spansion assumes no liability for any
damages of any kind arising out of the use of the information in this document.
Copyright © 1999–2005 Advanced Micro Devices, Inc. All rights reserved. AMD, the AMD logo, and combinations thereof are registered
trademarks of Advanced Micro Devices, Inc. Product names used in this publication are for identification purposes only and may be trademarks
of their respective companies.
Copyright © 2006-2010 Spansion Inc. All rights reserved. Spansion®, the Spansion logo, MirrorBit®, MirrorBit® Eclipse™, ORNAND™,
EcoRAM™ and combinations thereof, are trademarks and registered trademarks of Spansion LLC in the United States and other countries.
Other names used are for informational purposes only and may be trademarks of their respective owners.
April 23, 2010 Am29F160D_00_D10
Am29F160D
45
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