PIC16CR7X.pdf

PIC16CR7X.pdf
PIC16CR7X
Data Sheet
28/40-Pin, 8-Bit CMOS ROM
Microcontrollers
© 2006 Microchip Technology Inc.
DS21993A
Note the following details of the code protection feature on Microchip devices:
•
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•
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
•
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•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
•
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
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Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
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Information contained in this publication regarding device
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Trademarks
The Microchip name and logo, the Microchip logo, Accuron,
dsPIC, KEELOQ, microID, MPLAB, PIC, PICmicro, PICSTART,
PRO MATE, PowerSmart, rfPIC and SmartShunt are
registered trademarks of Microchip Technology Incorporated
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SEEVAL, SmartSensor and The Embedded Control Solutions
Company are registered trademarks of Microchip Technology
Incorporated in the U.S.A.
Analog-for-the-Digital Age, Application Maestro, dsPICDEM,
dsPICDEM.net, dsPICworks, ECAN, ECONOMONITOR,
FanSense, FlexROM, fuzzyLAB, In-Circuit Serial
Programming, ICSP, ICEPIC, Linear Active Thermistor,
MPASM, MPLIB, MPLINK, MPSIM, PICkit, PICDEM,
PICDEM.net, PICLAB, PICtail, PowerCal, PowerInfo,
PowerMate, PowerTool, REAL ICE, rfLAB, rfPICDEM, Select
Mode, Smart Serial, SmartTel, Total Endurance, UNI/O,
WiperLock and Zena are trademarks of Microchip Technology
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SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
© 2006, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.
Microchip received ISO/TS-16949:2002 quality system certification for
its worldwide headquarters, design and wafer fabrication facilities in
Chandler and Tempe, Arizona and Mountain View, California in
October 2003. The Company’s quality system processes and
procedures are for its PICmicro® 8-bit MCUs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
DS21993A-page ii
© 2006 Microchip Technology Inc.
PIC16CR7X
28/40-Pin, 8-Bit CMOS ROM Microcontrollers
Devices Included in this Data Sheet:
Peripheral Features:
• High-performance RISC CPU
• Only 35 single-word instructions to learn
• All single-cycle instructions except for program
branches which are two-cycle
• Operating speed: DC – 20 MHz clock input
DC – 200 ns instruction cycle
• Up to 8K x 14 words of ROM Program Memory,
Up to 368 x 8 bytes of Data Memory (RAM)
• Function compatible to the PIC16F73/74/76/77
• Pinout compatible to the PIC16F873/874/876/877
• Interrupt capability (up to 12 sources)
• Eight-level deep hardware stack
• Direct, Indirect and Relative Addressing modes
• Processor read access to program memory
• Timer0: 8-bit timer/counter with 8-bit prescaler
• Timer1: 16-bit timer/counter with prescaler,
can be incremented during Sleep via external
crystal/clock
• Timer2: 8-bit timer/counter with 8-bit period
register, prescaler and postscaler
• Two Capture, Compare, PWM modules:
- Capture is 16-bit, max. resolution is 12.5 ns
- Compare is 16-bit, max. resolution is 200 ns
- PWM max. resolution is 10-bit
• 8-bit, up to 8-channel Analog-to-Digital converter
• Synchronous Serial Port (SSP) with SPI (Master
mode) and I2C™ (Slave)
• Universal Synchronous Asynchronous Receiver
Transmitter (USART/SCI)
• Parallel Slave Port (PSP), 8-bits wide with
external RD, WR and CS controls (40/44-pin only)
• Brown-out detection circuitry for
Brown-out Reset (BOR)
Special Microcontroller Features:
CMOS Technology:
• Power-on Reset (POR)
• Power-up Timer (PWRT) and
Oscillator Start-up Timer (OST)
• Watchdog Timer (WDT) with its own on-chip RC
oscillator for reliable operation
• Power-saving Sleep mode
• Selectable oscillator options
•
•
•
•
•
•
• PIC16CR73
• PIC16CR74
• PIC16CR76
• PIC16CR77
High-Performance RISC CPU:
Device
Program
Data
Memory
SRAM I/O
(# Single Word
(Bytes)
Instructions)
Low-power, high-speed CMOS ROM technology
Fully static design
Wide operating voltage range: 2.0V to 5.5V
High Sink/Source Current: 25 mA
Industrial temperature range
Low power consumption:
- < 2 mA typical @ 5V, 4 MHz – TBD
- 20 μA typical @ 3V, 32 kHz – TBD
- < 1 μA typical standby current – TBD
SSP
8-bit
CCP
Interrupts
A/D (ch) (PWM)
Timers
SPI
I2C™ USART 8/16-bit
(Master) (Slave)
PIC16CR73
4096
192
22
11
5
2
Yes
Yes
Yes
2/1
PIC16CR74
4096
192
33
12
8
2
Yes
Yes
Yes
2/1
PIC16CR76
8192
368
22
11
5
2
Yes
Yes
Yes
2/1
PIC16CR77
8192
368
33
12
8
2
Yes
Yes
Yes
2/1
© 2006 Microchip Technology Inc.
DS21993A-page 1
PIC16CR7X
Pin Diagrams
PDIP, SOIC, SSOP
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
PIC16CR76/73
MCLR
RA0/AN0
RA1/AN1
RA2/AN2
RA3/AN3/VREF
RA4/T0CKI
RA5/AN4/SS
VSS
OSC1/CLKIN
OSC2/CLKOUT
RC0/T1OSO/T1CKI
RC1/T1OSI/CCP2
RC2/CCP1
RC3/SCK/SCL
RB7
RB6
RB5
RB4
RB3
RB2
RB1
RB0/INT
VDD
VSS
RC7/RX/DT
RC6/TX/CK
RC5/SDO
RC4/SDI/SDA
1
2
3
4
5
6
7
28 27 26 25 24 23 22
21
20
PIC16CR73 19
18
PIC16CR76 17
16
15
8 9 10 11 12 13 14
RB3
RB2
RB1
RB0/INT
VDD
VSS
RC7/RX/DT
RC0/T1OSO/T1CKI
RC1/T1OSI/CCP2
RC2/CCP1
RC3/SCK/SCL
RC4/SDI/SDA
RC5/SDO
RC6/TX/CK
RA2/AN2
RA3/AN3/VREF
RA4/T0CKI
RA5/AN4/SS
VSS
OSC1/CLKIN
OSC2/CLKOUT
RA1/AN1
RA0/AN0
MCLR
RB7
RB6
RB5
RB4
QFN
MCLR
RA0/AN0
RA1/AN1
RA2/AN2
RA3/AN3/VREF
RA4/T0CKI
RA5/AN4/SS
RE0/AN5/RD
RE1/AN6/WR
RE2/AN7/CS
VDD
VSS
OSC1/CLKIN
OSC2/CLKOUT
RC0/T1OSO/T1CKI
RC1/T1OSI/CCP2
RC2/CCP1
RC3/SCK/SCL
RD0/PSP0
RD1/PSP1
DS21993A-page 2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
PIC16CR77/74
PDIP
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
RB7
RB6
RB5
RB4
RB3
RB2
RB1
RB0/INT
VDD
VSS
RD7/PSP7
RD6/PSP6
RD5/PSP5
RD4/PSP4
RC7/RX/DT
RC6/TX/CK
RC5/SDO
RC4/SDI/SDA
RD3/PSP3
RD2/PSP2
© 2006 Microchip Technology Inc.
PIC16CR7X
Pin Diagrams (Continued)
PIC16CR77
PIC16CR74
39
38
37
36
35
34
33
32
31
30
9
18
19
20
21
22
23
24
25
26
27
282
7
8
9
10
11
12
13
14
15
16
17
RB3
RB2
RB1
RB0/INT
VDD
VSS
RD7/PSP7
RD6/PSP6
RD5/PSP5
RD4/PSP4
RC7/RX/DT
RC1/T1OSI/CCP2
RC2/CCP1
RC3/SCK/SCL
RD0/PSP0
RD1/PSP1
RD2/PSP2
RD3/PSP3
RC4/SDI/SDA
RC5/SDO
RC6/TX/CK
NC
RA4/T0CKI
RA5/AN4/SS
RE0/AN5/RD
RE1/AN6/WR
RE2/AN7/CS
VDD
VSS
OSC1/CLKIN
OSC2/CLKOUT
RC0/T1OSO/T1CK1
NC
6
5
4
3
2
1
44
43
42
41
40
RA3/AN3/VREF
RA2/AN2
RA1/AN1
RA0/AN0
MCLR
NC
RB7
RB6
RB5
RB4
NC
PLCC
44
43
42
41
40
39
38
37
36
35
34
RC6/TX/CK
RC5/SDO
RC4/SDI/SDA
RD3/PSP3
RD2/PSP2
RD1/PSP1
RD0/PSP0
RC3/SCK/SCL
RC2/CCP1
RC1/T1OSI/CCP2
NC
TQFP
PIC16CR77
PIC16CR74
33
32
31
30
29
28
27
26
25
24
23
12
13
14
15
16
17
18
19
20
21
22
1
2
3
4
5
6
7
8
9
10
11
NC
RC0/T1OSO/T1CKI
OSC2/CLKOUT
OSC1/CLKIN
VSS
VDD
RE2/AN7/CS
RE1/AN6/WR
RE0/AN5/RD
RA5/AN4/SS
RA4/T0CKI
NC
NC
RB4
RB5
RB6
RB7
MCLR
RA0/AN0
RA1/AN1
RA2/AN2
RA3/AN3/VREF
RC7/RX/DT
RD4/PSP4
RD5/PSP5
RD6/PSP6
RD7/PSP7
VSS
VDD
RB0/INT
RB1
RB2
RB3
© 2006 Microchip Technology Inc.
DS21993A-page 3
PIC16CR7X
Table of Contents
Device Overview ................................................................................................................................................................................... 5
Memory Organization .......................................................................................................................................................................... 13
Reading Program Memory .................................................................................................................................................................. 29
I/O Ports .............................................................................................................................................................................................. 31
Timer0 Module .................................................................................................................................................................................... 43
Timer1 Module .................................................................................................................................................................................... 47
Timer2 Module .................................................................................................................................................................................... 51
Capture/Compare/PWM Modules ....................................................................................................................................................... 53
Synchronous Serial Port (SSP) Module .............................................................................................................................................. 59
Universal Synchronous Asynchronous Receiver Transmitter (USART) ............................................................................................. 69
Analog-to-Digital Converter (A/D) Module ........................................................................................................................................... 83
Special Features of the CPU ............................................................................................................................................................... 89
Instruction Set Summary ................................................................................................................................................................... 105
Development Support ....................................................................................................................................................................... 113
Electrical Characteristics ................................................................................................................................................................... 117
DC and AC Characteristics Graphs and Tables ................................................................................................................................ 139
Packaging Information ...................................................................................................................................................................... 149
Appendix A: Revision History ........................................................................................................................................................... 159
Appendix B: Device Differences ........................................................................................................................................................ 159
Appendix C: Conversion Considerations .......................................................................................................................................... 160
The Microchip Web Site .................................................................................................................................................................... 167
Customer Change Notification Service ............................................................................................................................................. 167
Customer Support ............................................................................................................................................................................. 167
Reader Response ............................................................................................................................................................................. 168
Product Identification System ............................................................................................................................................................ 169
TO OUR VALUED CUSTOMERS
It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip
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DS21993A-page 4
© 2006 Microchip Technology Inc.
PIC16CR7X
1.0
DEVICE OVERVIEW
This document contains device specific information
about the following devices:
•
•
•
•
PIC16CR73
PIC16CR74
PIC16CR76
PIC16CR77
PIC16CR73/76 devices are available only in 28-pin
packages, while PIC16CR74/77 devices are available
in 40-pin and 44-pin packages. All devices in the
PIC16CR7X family share common architecture, with
the following differences:
The available features are summarized in Table 1-1.
Block diagrams of the PIC16CR73/76 and
PIC16CR74/77 devices are provided in Figure 1-1 and
Figure 1-2, respectively. The pinouts for these device
families are listed in Table 1-2 and Table 1-3.
Additional information may be found in the “PICmicro®
Mid-Range MCU Family Reference Manual”
(DS33023), which may be obtained from your local
Microchip Sales Representative or downloaded from
the Microchip web site. The Reference Manual should
be considered a complementary document to this data
sheet, and is highly recommended reading for a better
understanding of the device architecture and operation
of the peripheral modules.
• The PIC16CR73 and PIC16CR76 have one-half
of the total on-chip memory of the PIC16CR74
and PIC16CR77
• The 28-pin devices have 3 I/O ports, while the
40/44-pin devices have 5
• The 28-pin devices have 11 interrupts, while the
40/44-pin devices have 12
• The 28-pin devices have 5 A/D input channels,
while the 40/44-pin devices have 8
• The Parallel Slave Port is implemented only on
the 40/44-pin devices
TABLE 1-1:
PIC16CR7X DEVICE FEATURES
Key Features
PIC16CR73
PIC16CR74
PIC16CR76
PIC16CR77
Operating Frequency
DC – 20 MHz
DC – 20 MHz
DC – 20 MHz
DC – 20 MHz
Resets (and Delays)
POR, BOR
(PWRT, OST)
POR, BOR
(PWRT, OST)
POR, BOR
(PWRT, OST)
POR, BOR
(PWRT, OST)
ROM Program Memory
(14-bit words)
4K
4K
8K
8K
Data Memory (bytes)
192
192
368
368
Interrupts
11
12
11
12
I/O Ports
Ports A,B,C
Ports A,B,C,D,E
Ports A,B,C
Ports A,B,C,D,E
Timers
3
3
3
3
Capture/Compare/PWM Modules
2
2
2
2
SSP, USART
SSP, USART
SSP, USART
SSP, USART
—
PSP
—
PSP
Serial Communications
Parallel Communications
8-bit Analog-to-Digital Module
Instruction Set
Packaging
© 2006 Microchip Technology Inc.
5 Input Channels 8 Input Channels 5 Input Channels 8 Input Channels
35 Instructions
35 Instructions
35 Instructions
35 Instructions
28-pin DIP
28-pin SOIC
28-pin SSOP
28-pin MLF
40-pin PDIP
44-pin PLCC
44-pin TQFP
28-pin DIP
28-pin SOIC
28-pin SSOP
28-pin MLF
40-pin PDIP
44-pin PLCC
44-pin TQFP
DS21993A-page 5
PIC16CR7X
FIGURE 1-1:
PIC16CR73 AND PIC16CR76 BLOCK DIAGRAM
13
ROM
Program
Memory
PORTA
RA0/AN0
RA1/AN1
RA2/AN2
RA3/AN3/VREF
RA4/T0CKI
RA5/AN4/SS
RAM
File
Registers
8-Level Stack
(13-bit)
Program
Bus
8
Data Bus
Program Counter
14
RAM Addr(1)
9
PORTB
Addr MUX
Instruction Reg
Direct Addr
7
8
Indirect
Addr
FSR Reg
STATUS Reg
8
RB0/INT
RB1
RB2
RB3
RB4
RB5
RB6
RB7
PORTC
3
Power-up
Timer
Instruction
Decode &
Control
Timing
Generation
OSC1/CLKIN
OSC2/CLKOUT
Oscillator
Start-up Timer
Note
ALU
Power-on
Reset
8
Watchdog
Timer
Brown-out
Reset
MCLR
W Reg
VDD, VSS
Timer0
Timer1
Timer2
8-bit A/D
CCP1
CCP2
Synchronous
Serial Port
USART
1:
RC0/T1OSO/T1CKI
RC1/T1OSI/CCP2
RC2/CCP1
RC3/SCK/SCL
RC4/SDI/SDA
RC5/SDO
RC6/TX/CK
RC7/RX/DT
MUX
Device
Program ROM
Data Memory
PIC16CR73
4K
192 Bytes
PIC16CR76
8K
368 Bytes
Higher order bits are from the STATUS register.
DS21993A-page 6
© 2006 Microchip Technology Inc.
PIC16CR7X
FIGURE 1-2:
PIC16CR74 AND PIC16CR77 BLOCK DIAGRAM
13
ROM
Program
Memory
PORTA
RA0/AN0
RA1/AN1
RA2/AN2
RA3/AN3/VREF
RA4/T0CKI
RA5/AN4/SS
RAM
File
Registers
8-Level Stack
(13-bit)
Program
Bus
8
Data Bus
Program Counter
14
RAM Addr(1)
PORTB
9
RB0/INT
RB1
RB2
RB3
RB4
RB5
RB6
RB7
Addr MUX
Instruction Reg
Direct Addr
7
8
Indirect
Addr
FSR Reg
STATUS Reg
8
PORTC
3
Power-up
Timer
Instruction
Decode &
Control
Oscillator
Start-up Timer
Timing
Generation
Watchdog
Timer
Brown-out
Reset
OSC1/CLKIN
OSC2/CLKOUT
MUX
ALU
Power-on
Reset
MCLR
RC0/T1OSO/T1CKI
RC1/T1OSI/CCP2
RC2/CCP1
RC3/SCK/SCL
RC4/SDI/SDA
RC5/SDO
RC6/TX/CK
RC7/RX/DT
8
PORTD
W Reg
RD0/PSP0
RD1/PSP1
RD2/PSP2
RD3/PSP3
RD4/PSP4
RD5/PSP5
RD6/PSP6
RD7/PSP7
VDD, VSS
PORTE
RE0/AN5/RD
RE1/AN6/WR
RE2/AN7/CS
Note
Timer0
Timer1
Timer2
8-bit A/D
CCP1
CCP2
Synchronous
Serial Port
USART
1:
Parallel Slave Port
Device
Program ROM
Data Memory
PIC16CR74
4K
192 Bytes
PIC16CR77
8K
368 Bytes
Higher order bits are from the STATUS register.
© 2006 Microchip Technology Inc.
DS21993A-page 7
PIC16CR7X
TABLE 1-2:
Pin Name
OSC1/CLKIN
OSC1
PIC16CR73 AND PIC16CR76 PINOUT DESCRIPTION
PDIP
SSOP
SOIC
Pin#
MLF
Pin#
9
6
I/O/P
Type
I
CLKIN
I
OSC2/CLKOUT
OSC2
10
7
Buffer
Type
ST/CMOS(3) Oscillator crystal or external clock input.
Oscillator crystal input or external clock source input. ST
buffer when configured in RC mode. Otherwise CMOS.
External clock source input. Always associated with pin
function OSC1 (see OSC1/CLKIN, OSC2/CLKOUT pins).
—
Oscillator crystal or clock output.
Oscillator crystal output.
Connects to crystal or resonator in Crystal Oscillator
mode.
In RC mode, OSC2 pin outputs CLKOUT, which has 1/4
the frequency of OSC1 and denotes the instruction cycle
rate.
ST
Master Clear (Reset) input. This pin is an active low
Reset to the device.
O
CLKOUT
O
MCLR
1
26
RA0/AN0
RA0
AN0
2
27
RA1/AN1
RA1
AN1
3
RA2/AN2
RA2
AN2
4
RA3/AN3/VREF
RA3
AN3
VREF
5
RA4/T0CKI
RA4
T0CKI
6
RA5/AN4/SS
RA5
AN4
SS
7
I
Description
PORTA is a bidirectional I/O port.
TTL
I/O
I
28
Digital I/O.
Analog input 0.
TTL
I/O
I
1
Digital I/O.
Analog input 1.
TTL
I/O
I
2
Digital I/O.
Analog input 2.
TTL
I/O
I
I
3
Digital I/O.
Analog input 3.
A/D reference voltage input.
ST
I/O
I
4
Digital I/O – Open drain when configured as output.
Timer0 external clock input.
TTL
I/O
I
I
Digital I/O.
Analog input 4.
SPI slave select input.
PORTB is a bidirectional I/O port. PORTB can be software
programmed for internal weak pull-up on all inputs.
TTL/ST(1)
RB0/INT
RB0
INT
21
RB1
22
19
I/O
TTL
Digital I/O.
RB2
23
20
I/O
TTL
Digital I/O.
RB3
24
21
I/O
TTL
Digital I/O.
RB4
25
22
I/O
TTL
Digital I/O.
RB5
26
23
I/O
TTL
Digital I/O.
RB6
27
24
I/O
TTL
Digital I/O.
RB7
28
25
I/O
TTL
Digital I/O.
Legend:
Note 1:
2:
3:
18
Digital I/O.
External interrupt.
I/O
I
I = input
O = output
I/O = input/output
P = power
— = Not used
TTL = TTL input
ST = Schmitt Trigger input
This buffer is a Schmitt Trigger input when configured as the external interrupt.
This buffer is a Schmitt Trigger input when used in Serial Verify mode.
This buffer is a Schmitt Trigger input when configured in RC Oscillator mode and a CMOS input otherwise.
DS21993A-page 8
© 2006 Microchip Technology Inc.
PIC16CR7X
TABLE 1-2:
PIC16CR73 AND PIC16CR76 PINOUT DESCRIPTION (CONTINUED)
PDIP
SSOP
SOIC
Pin#
MLF
Pin#
RC0/T1OSO/T1CKI
RC0
T1OSO
T1CKI
11
8
RC1/T1OSI/CCP2
RC1
T1OSI
CCP2
12
RC2/CCP1
RC2
CCP1
13
RC3/SCK/SCL
RC3
SCK
SCL
14
RC4/SDI/SDA
RC4
SDI
SDA
15
RC5/SDO
RC5
SDO
16
RC6/TX/CK
RC6
TX
CK
17
RC7/RX/DT
RC7
RX
DT
18
Pin Name
I/O/P
Type
Buffer
Type
Description
PORTC is a bidirectional I/O port.
ST
I/O
O
I
9
Digital I/O.
Timer1 oscillator output.
Timer1 external clock input.
ST
I/O
I
I/O
10
Digital I/O.
Timer1 oscillator input.
Capture2 input, Compare2 output, PWM2 output.
ST
I/O
I/O
11
Digital I/O.
Capture1 input/Compare1 output/PWM1 output.
ST
I/O
I/O
I/O
12
Digital I/O.
Synchronous serial clock input/output for SPI mode.
Synchronous serial clock input/output for I2C™ mode.
ST
I/O
I
I/O
13
Digital I/O.
SPI data in.
I2C™ data I/O.
ST
I/O
O
14
Digital I/O.
SPI data out.
ST
I/O
O
I/O
15
Digital I/O.
USART asynchronous transmit.
USART 1 synchronous clock.
ST
I/O
I
I/O
Digital I/O.
USART asynchronous receive.
USART synchronous data.
VSS
8, 19
5, 16
P
—
Ground reference for logic and I/O pins.
VDD
20
17
P
—
Positive supply for logic and I/O pins.
Legend:
Note 1:
2:
3:
I = input
O = output
I/O = input/output
P = power
— = Not used
TTL = TTL input
ST = Schmitt Trigger input
This buffer is a Schmitt Trigger input when configured as the external interrupt.
This buffer is a Schmitt Trigger input when used in Serial Verify mode.
This buffer is a Schmitt Trigger input when configured in RC Oscillator mode and a CMOS input otherwise.
© 2006 Microchip Technology Inc.
DS21993A-page 9
PIC16CR7X
TABLE 1-3:
Pin Name
OSC1/CLKIN
OSC1
PIC16CR74 AND PIC16CR77 PINOUT DESCRIPTION
PDIP
Pin#
PLCC
Pin#
QFP
Pin#
13
14
30
I/O/P
Type
I
CLKIN
I
OSC2/CLKOUT
OSC2
14
15
31
Buffer
Type
ST/CMOS(4) Oscillator crystal or external clock input.
Oscillator crystal input or external clock source input.
ST buffer when configured in RC mode. Otherwise
CMOS.
External clock source input. Always associated with pin
function OSC1 (see OSC1/CLKIN, OSC2/CLKOUT
pins).
—
Oscillator crystal or clock output.
Oscillator crystal output.
Connects to crystal or resonator in Crystal Oscillator
mode.
In RC mode, OSC2 pin outputs CLKOUT, which has 1/4
the frequency of OSC1 and denotes the instruction
cycle rate.
ST
Master Clear (Reset) input. This pin is an active low
Reset to the device.
O
CLKOUT
O
MCLR
1
2
18
RA0/AN0
RA0
AN0
2
3
19
RA1/AN1
RA1
AN1
3
RA2/AN2
RA2
AN2
4
RA3/AN3/VREF
RA3
AN3
VREF
5
RA4/T0CKI
RA4
T0CKI
6
RA5/AN4/SS
RA5
AN4
SS
7
I
Description
PORTA is a bidirectional I/O port.
Legend:
Note 1:
2:
3:
4:
TTL
I/O
I
4
20
Digital I/O.
Analog input 0.
TTL
I/O
I
5
21
Digital I/O.
Analog input 1.
TTL
I/O
I
6
22
Digital I/O.
Analog input 2.
TTL
I/O
I
I
7
23
Digital I/O.
Analog input 3.
A/D reference voltage input.
ST
I/O
I
8
24
Digital I/O – Open drain when configured as output.
Timer0 external clock input.
TTL
I/O
I
I
Digital I/O.
Analog input 4.
SPI slave select input.
I = input
O = output
I/O = input/output
P = power
— = Not used
TTL = TTL input ST = Schmitt Trigger input
This buffer is a Schmitt Trigger input when configured as an external interrupt.
This buffer is a Schmitt Trigger input when used in Serial Verify mode.
This buffer is a Schmitt Trigger input when configured as general purpose I/O and a TTL input when used in the Parallel
Slave Port mode (for interfacing to a microprocessor bus).
This buffer is a Schmitt Trigger input when configured in RC Oscillator mode and a CMOS input otherwise.
DS21993A-page 10
© 2006 Microchip Technology Inc.
PIC16CR7X
TABLE 1-3:
Pin Name
PIC16CR74 AND PIC16CR77 PINOUT DESCRIPTION (CONTINUED)
PDIP
Pin#
PLCC
Pin#
QFP
Pin#
I/O/P
Type
Buffer
Type
Description
PORTB is a bidirectional I/O port. PORTB can be software
programmed for internal weak pull-up on all inputs.
RB0/INT
RB0
INT
33
36
TTL/ST(1)
8
I/O
I
Digital I/O.
External interrupt.
RB1
34
37
9
I/O
TTL
Digital I/O.
RB2
35
38
10
I/O
TTL
Digital I/O.
RB3
36
39
11
I/O
TTL
Digital I/O.
RB4
37
41
14
I/O
TTL
Digital I/O.
RB5
38
42
15
I/O
TTL
Digital I/O.
RB6
39
43
16
I/O
TTL
Digital I/O.
RB7
40
44
17
I/O
TTL
Digital I/O.
PORTC is a bidirectional I/O port.
RC0/T1OSO/
T1CKI
RC0
T1OSO
T1CKI
15
RC1/T1OSI/CCP2
RC1
T1OSI
CCP2
16
RC2/CCP1
RC2
CCP1
17
RC3/SCK/SCL
RC3
SCK
SCL
18
RC4/SDI/SDA
RC4
SDI
SDA
23
RC5/SDO
RC5
SDO
24
RC6/TX/CK
RC6
TX
CK
25
RC7/RX/DT
RC7
RX
DT
26
Legend:
Note 1:
2:
3:
4:
16
32
ST
I/O
O
I
18
35
Digital I/O.
Timer1 oscillator output.
Timer1 external clock input.
ST
I/O
I
I/O
19
36
Digital I/O.
Timer1 oscillator input.
Capture2 input, Compare2 output, PWM2 output.
ST
I/O
I/O
20
Digital I/O.
Capture1 input/Compare1 output/PWM1 output.
ST
37
I/O
I/O
I/O
25
42
Digital I/O.
Synchronous serial clock input/output for SPI mode.
Synchronous serial clock input/output for I2C™ mode.
ST
I/O
I
I/O
26
43
Digital I/O.
SPI data in.
I2C™ data I/O.
ST
I/O
O
27
44
Digital I/O.
SPI data out.
ST
I/O
O
I/O
29
1
Digital I/O.
USART asynchronous transmit.
USART 1 synchronous clock.
ST
I/O
I
I/O
Digital I/O.
USART asynchronous receive.
USART synchronous data.
I = input
O = output
I/O = input/output
P = power
— = Not used
TTL = TTL input ST = Schmitt Trigger input
This buffer is a Schmitt Trigger input when configured as an external interrupt.
This buffer is a Schmitt Trigger input when used in Serial Verify mode.
This buffer is a Schmitt Trigger input when configured as general purpose I/O and a TTL input when used in the Parallel
Slave Port mode (for interfacing to a microprocessor bus).
This buffer is a Schmitt Trigger input when configured in RC Oscillator mode and a CMOS input otherwise.
© 2006 Microchip Technology Inc.
DS21993A-page 11
PIC16CR7X
TABLE 1-3:
Pin Name
PIC16CR74 AND PIC16CR77 PINOUT DESCRIPTION (CONTINUED)
PDIP
Pin#
PLCC
Pin#
QFP
Pin#
I/O/P
Type
Buffer
Type
Description
PORTD is a bidirectional I/O port or parallel slave port
when interfacing to a microprocessor bus.
RD0/PSP0
RD0
PSP0
19
RD1/PSP1
RD1
PSP1
20
RD2/PSP2
RD2
PSP2
21
RD3/PSP3
RD3
PSP3
22
RD4/PSP4
RD4
PSP4
27
RD5/PSP5
RD5
PSP5
28
RD6/PSP6
RD6
PSP6
29
RD7/PSP7
RD7
PSP7
30
RE0/AN5/RD/
RE0
AN5
RD
8
RE1/AN6/WR/
RE1
AN6
WR
9
RE2/AN7/CS
RE2
AN7
CS
10
21
ST/TTL(3)
38
Digital I/O.
Parallel Slave Port data.
I/O
I/O
22
23
24
39
40
I
I/O
I/O
ST/TTL(3)
I
I/O
I/O
ST/TTL(3)
Digital I/O.
Parallel Slave Port data.
Digital I/O.
Parallel Slave Port data.
ST/TTL(3)
41
Digital I/O.
Parallel Slave Port data.
I/O
I/O
30
ST/TTL(3)
2
Digital I/O.
Parallel Slave Port data.
I/O
I/O
31
ST/TTL(3)
3
Digital I/O.
Parallel Slave Port data.
I/O
I/O
32
ST/TTL(3)
4
Digital I/O.
Parallel Slave Port data.
I/O
I/O
33
ST/TTL(3)
5
Digital I/O.
Parallel Slave Port data.
I/O
I/O
PORTE is a bidirectional I/O port.
9
ST/TTL(3)
25
Digital I/O.
Analog input 5.
Read control for parallel slave port .
I/O
I
I
10
ST/TTL(3)
26
Digital I/O.
Analog input 6.
Write control for parallel slave port .
I/O
I
I
11
ST/TTL(3)
27
Digital I/O.
Analog input 7.
Chip Select control for parallel slave port .
I/O
I
I
VSS
12,31
13,34
6,29
P
—
Ground reference for logic and I/O pins.
VDD
11,32
12,35
7,28
P
—
Positive supply for logic and I/O pins.
NC
—
1,17,
28, 40
12,13,
33, 34
—
These pins are not internally connected. These pins should
be left unconnected.
Legend:
Note 1:
2:
3:
4:
I = input
O = output
I/O = input/output
P = power
— = Not used
TTL = TTL input ST = Schmitt Trigger input
This buffer is a Schmitt Trigger input when configured as an external interrupt.
This buffer is a Schmitt Trigger input when used in Serial Verify mode.
This buffer is a Schmitt Trigger input when configured as general purpose I/O and a TTL input when used in the Parallel
Slave Port mode (for interfacing to a microprocessor bus).
This buffer is a Schmitt Trigger input when configured in RC Oscillator mode and a CMOS input otherwise.
DS21993A-page 12
© 2006 Microchip Technology Inc.
PIC16CR7X
2.0
MEMORY ORGANIZATION
There are two memory blocks in each of these
PICmicro® MCUs. The Program Memory and Data
Memory have separate buses so that concurrent
access can occur and is detailed in this section. The
Program Memory can be read internally by user code
(see Section 3.0 “Reading Program Memory”).
2.2
The Data Memory is partitioned into multiple banks,
which contain the General Purpose Registers (GPR)
and the Special Function Registers (SFR). Bits RP1
(STATUS<6>) and RP0 (STATUS<5>) are the bank
select bits:
Additional information on device memory may be found
in the “PICmicro® Mid-Range MCU Family Reference
Manual” (DS33023).
2.1
Data Memory Organization
Program Memory Organization
RP1:RP0
Bank
00
0
01
1
10
2
11
3
The PIC16CR7X devices have a 13-bit program
counter capable of addressing an 8K word x 14-bit program memory space. The PIC16CR77/76 devices
have 8K words of ROM program memory and the
PIC16CR73/74 devices have 4K words. The program
memory maps for PIC16CR7X devices are shown in
Figure 2-1. Accessing a location above the physically
implemented address will cause a wraparound.
Each bank extends up to 7Fh (128 bytes). The lower
locations of each bank are reserved for the Special
Function Registers. Above the Special Function Registers are General Purpose Registers, implemented as
static RAM. All implemented banks contain Special
Function Registers. Some frequently used Special
Function Registers from one bank may be mirrored in
another bank for code reduction and quicker access.
The Reset vector is at 0000h and the interrupt vector is
at 0004h.
2.2.1
GENERAL PURPOSE REGISTER
FILE
The register file (shown in Figure 2-2 and Figure 2-3)
can be accessed either directly, or indirectly, through
the File Select Register (FSR).
FIGURE 2-1:
PROGRAM MEMORY MAPS AND STACKS FOR PIC16CR7X DEVICES
PIC16CR76/77
PIC16CR73/74
PC<12:0>
PC<12:0>
13
CALL, RETURN
RETFIE, RETLW
Stack Level 1
Stack Level 2
Stack Level 1
Stack Level 2
Stack Level 8
Stack Level 8
Reset Vector
0000h
Reset Vector
0000h
Interrupt Vector
0004h
0005h
Interrupt Vector
0004h
0005h
Page 0
07FFh
0800h
On-Chip
Program
Memory
13
CALL, RETURN
RETFIE, RETLW
Page 1
On-Chip
Program
Memory
Page 0
07FFh
0800h
Page 1
0FFFh
1000h
0FFFh
1000h
Page 2
17FFh
1800h
Unimplemented
Read as ‘0’
Page 3
1FFFh
© 2006 Microchip Technology Inc.
1FFFh
DS21993A-page 13
PIC16CR7X
FIGURE 2-2:
PIC16CR77/76 REGISTER FILE MAP
Indirect addr.(*)
TMR0
PCL
STATUS
FSR
PORTA
PORTB
PORTC
PORTD(1)
PORTE(1)
PCLATH
INTCON
PIR1
PIR2
TMR1L
TMR1H
T1CON
TMR2
T2CON
SSPBUF
SSPCON
CCPR1L
CCPR1H
CCP1CON
RCSTA
TXREG
RCREG
CCPR2L
CCPR2H
CCP2CON
ADRES
ADCON0
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
1Bh
1Ch
1Dh
1Eh
1Fh
20h
Indirect addr.(*) 80h
OPTION_REG 81h
PCL
82h
STATUS
83h
FSR
84h
TRISA
85h
TRISB
86h
TRISC
87h
TRISD(1)
88h
TRISE(1)
89h
PCLATH
8Ah
INTCON
8Bh
PIE1
8Ch
PIE2
8Dh
PCON
8Eh
8Fh
90h
91h
PR2
92h
SSPADD
93h
SSPSTAT
94h
95h
96h
97h
98h
TXSTA
99h
SPBRG
9Ah
9Bh
9Ch
9Dh
9Eh
9Fh
ADCON1
A0h
General
Purpose
Register
80 Bytes
General
Purpose
Register
96 Bytes
accesses
70h-7Fh
7Fh
Bank 0
EFh
F0h
Indirect addr.(*) 100h
101h
TMR0
102h
PCL
103h
STATUS
104h
FSR
105h
106h
PORTB
107h
108h
109h
10Ah
PCLATH
10Bh
INTCON
10Ch
PMDATA
PMADR
10Dh
10Eh
PMDATH
10Fh
PMADRH
110h
111h
112h
113h
114h
115h
116h
General
117h
Purpose
118h
Register
119h
16 Bytes
11Ah
11Bh
11Ch
11Dh
11Eh
11Fh
120h
General
Purpose
Register
80 Bytes
accesses
70h-7Fh
16Fh
170h
Indirect addr.(*)
OPTION_REG
PCL
STATUS
FSR
TRISB
PCLATH
INTCON
PMCON1
General
Purpose
Register
16 Bytes
Bank 2
180h
181h
182h
183h
184h
185h
186h
187h
188h
189h
18Ah
18Bh
18Ch
18Dh
18Eh
18Fh
190h
191h
192h
193h
194h
195h
196h
197h
198h
199h
19Ah
19Bh
19Ch
19Dh
19Eh
19Fh
1A0h
General
Purpose
Register
80 Bytes
accesses
70h-7Fh
17Fh
FFh
Bank 1
File
Address
File
Address
File
Address
File
Address
1EFh
1F0h
1FFh
Bank 3
Unimplemented data memory locations, read as ‘0’.
* Not a physical register.
Note 1: These registers are not implemented on 28-pin devices.
DS21993A-page 14
© 2006 Microchip Technology Inc.
PIC16CR7X
FIGURE 2-3:
PIC16CR74/73 REGISTER FILE MAP
File
Address
Indirect addr.(*)
TMR0
PCL
STATUS
FSR
PORTA
PORTB
PORTC
PORTD(1)
PORTE(1)
PCLATH
INTCON
PIR1
PIR2
TMR1L
TMR1H
T1CON
TMR2
T2CON
SSPBUF
SSPCON
CCPR1L
CCPR1H
CCP1CON
RCSTA
TXREG
RCREG
CCPR2L
CCPR2H
CCP2CON
ADRES
ADCON0
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
1Bh
1Ch
1Dh
1Eh
1Fh
20h
File
Address
Indirect addr.(*) 80h
OPTION_REG 81h
PCL
82h
STATUS
83h
FSR
84h
TRISA
85h
TRISB
86h
TRISC
87h
TRISD(1)
88h
TRISE(1)
89h
PCLATH
8Ah
INTCON
8Bh
PIE1
8Ch
PIE2
8Dh
PCON
8Eh
8Fh
90h
91h
PR2
92h
SSPADD
93h
SSPSTAT
94h
95h
96h
97h
98h
TXSTA
99h
SPBRG
9Ah
9Bh
9Ch
9Dh
9Eh
9Fh
ADCON1
Indirect addr.(*) 100h
101h
TMR0
102h
PCL
103h
STATUS
104h
FSR
105h
106h
PORTB
107h
108h
109h
10Ah
PCLATH
10Bh
INTCON
10Ch
PMDATA
PMADR
10Dh
10Eh
PMDATH
10Fh
PMADRH
110h
Indirect addr.(*)
OPTION_REG
PCL
STATUS
FSR
TRISB
PCLATH
INTCON
PMCON1
180h
181h
182h
183h
184h
185h
186h
187h
188h
189h
18Ah
18Bh
18Ch
18Dh
18Eh
18Fh
190h
1A0h
120h
A0h
General
Purpose
Register
General
Purpose
Register
96 Bytes
96 Bytes
7Fh
Bank 0
File
Address
File
Address
accesses
20h-7Fh
1EFh
1F0h
16Fh
170h
17Fh
FFh
Bank 1
accesses
A0h-FFh
Bank 2
1FFh
Bank 3
Unimplemented data memory locations, read as ‘0’.
* Not a physical register.
Note 1: These registers are not implemented on 28-pin devices.
© 2006 Microchip Technology Inc.
DS21993A-page 15
PIC16CR7X
2.2.2
SPECIAL FUNCTION REGISTERS
The Special Function Registers can be classified into
two sets: core (CPU) and peripheral. Those registers
associated with the core functions are described in
detail in this section. Those related to the operation of
the peripheral features are described in detail in the
peripheral feature section.
The Special Function Registers are registers used by
the CPU and peripheral modules for controlling the
desired operation of the device. These registers are
implemented as static RAM. A list of these registers is
given in Table 2-1.
TABLE 2-1:
Address
Name
SPECIAL FUNCTION REGISTER SUMMARY
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on:
POR,
BOR
Details
on page
Bank 0
00h(4)
INDF
Addressing this location uses contents of FSR to address data memory (not a physical register)
0000 0000
27, 96
01h
TMR0
Timer0 Module Register
xxxx xxxx
45, 96
02h(4)
PCL
Program Counter (PC) Least Significant Byte
0000 0000
26, 96
0001 1xxx
19, 96
xxxx xxxx
27, 96
--0x 0000
32, 96
03h(4)
STATUS
04h(4)
FSR
05h
PORTA
06h
PORTB
PORTB Data Latch when written: PORTB pins when read
xxxx xxxx
34, 96
07h
PORTC
PORTC Data Latch when written: PORTC pins when read
xxxx xxxx
35, 96
08h(5)
PORTD
PORTD Data Latch when written: PORTD pins when read
xxxx xxxx
36, 96
09h(5)
PORTE
---- -xxx
39, 96
0Ah(1,4)
PCLATH
—
—
—
---0 0000
26, 96
0Bh(4)
INTCON
GIE
PEIE
TMR0IE
INTE
RBIE
TMR0IF
INTF
RBIF
0000 000x
21, 96
ADIF
RCIF
TXIF
SSPIF
CCP1IF
TMR2IF
TMR1IF
0000 0000
23, 96
—
—
—
—
—
—
CCP2IF
---- ---0
24, 96
IRP
RP1
RP0
TO
PD
Z
DC
C(2)
Indirect Data Memory Address Pointer
—
—
—
PORTA Data Latch when written: PORTA pins when read
—
(3)
—
—
—
RE2
RE1
RE0
Write Buffer for the upper 5 bits of the Program Counter
0Ch
PIR1
0Dh
PIR2
0Eh
TMR1L
Holding Register for the Least Significant Byte of the 16-bit TMR1 Register
xxxx xxxx
50, 96
0Fh
TMR1H
Holding Register for the Most Significant Byte of the 16-bit TMR1 Register
xxxx xxxx
50, 96
10h
T1CON
TMR1ON --00 0000
47, 96
11h
TMR2
0000 0000
52, 96
12h
T2CON
TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000
52, 96
13h
SSPBUF
PSPIF
—
—
—
T1CKPS1
T1CKPS0
T1OSCEN
T1SYNC
TMR1CS
Timer2 Module Register
—
TOUTPS3 TOUTPS2
TOUTPS1
Synchronous Serial Port Receive Buffer/Transmit Register
WCOL
SSPOV
SSPEN
CKP
SSPM3
xxxx xxxx 64, 68, 96
14h
SSPCON
0000 0000
61, 96
15h
CCPR1L
Capture/Compare/PWM Register 1 (LSB)
SSPM2
SSPM1
xxxx xxxx
56, 96
16h
CCPR1H
Capture/Compare/PWM Register 1 (MSB)
xxxx xxxx
56, 96
17h
CCP1CON
CCP1M0 --00 0000
54, 96
18h
RCSTA
19h
TXREG
1Ah
—
—
CCP1X
CCP1Y
CCP1M3
CCP1M2
CCP1M1
SPEN
RX9
SREN
CREN
—
FERR
OERR
SSPM0
RX9D
0000 -00x
70, 96
USART Transmit Data Register
0000 0000
75, 96
RCREG
USART Receive Data Register
0000 0000
77, 96
1Bh
CCPR2L
Capture/Compare/PWM Register 2 (LSB)
xxxx xxxx
58, 96
1Ch
CCPR2H
Capture/Compare/PWM Register 2 (MSB)
xxxx xxxx
58, 96
1Dh
CCP2CON
CCP2M0 --00 0000
54, 96
1Eh
ADRES
xxxx xxxx
88, 96
0000 00-0
83, 96
1Fh
ADCON0
Legend:
Note 1:
2:
3:
4:
5:
6:
—
—
CCP2X
CCP2Y
CCP2M3
CCP2M2
CCP2M1
A/D Result Register Byte
ADCS1
ADCS0
CHS2
CHS1
CHS0
GO/
DONE
—
ADON
x = unknown, u = unchanged, q = value depends on condition, – = unimplemented, read as ‘0’, r = reserved.
Shaded locations are unimplemented, read as ‘0’.
The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8>, whose
contents are transferred to the upper byte of the program counter during branches (CALL or GOTO).
Other (non Power-up) Resets include external Reset through MCLR and Watchdog Timer Reset.
Bits PSPIE and PSPIF are reserved on the 28-pin devices; always maintain these bits clear.
These registers can be addressed from any bank.
PORTD, PORTE, TRISD and TRISE are not physically implemented on the 28-pin devices, read as ‘0’.
This bit always reads as a ‘1’.
DS21993A-page 16
© 2006 Microchip Technology Inc.
PIC16CR7X
TABLE 2-1:
Address
SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on:
POR,
BOR
Details
on page
0000 0000
27, 96
Bank 1
80h(4)
INDF
81h
OPTION_REG
82h(4)
PCL
83h(4)
STATUS
Addressing this location uses contents of FSR to address data memory (not a physical register)
RBPU
INTEDG
T0CS
T0SE
PSA
PS2
PS1
PS0
PD
Z
DC
C(2)
1111 1111 20, 44, 96
Program Counter (PC) Least Significant Byte
IRP
RP1
RP0
TO
0000 0000
26, 96
0001 1xxx
19, 96
xxxx xxxx
27, 96
--11 1111
32, 96
84h(4)
FSR
85h
TRISA
86h
TRISB
PORTB Data Direction Register
1111 1111
34, 96
87h
TRISC
PORTC Data Direction Register
1111 1111
35, 96
88h(5)
TRISD
PORTD Data Direction Register
1111 1111
36, 96
89h(5)
TRISE
IBF
OBF
IBOV
0000 -111
38, 96
8Ah(1,4)
PCLATH
—
—
—
---0 0000
26, 96
8Bh
INTCON
GIE
8Ch
PIE1
8Dh
PIE2
8Eh
PCON
8Fh
—
90h
(4)
Indirect data memory address pointer
—
—
PORTA Data Direction Register
PSPMODE
—
PORTE Data Direction Bits
Write Buffer for the upper 5 bits of the Program Counter
PEIE
TMR0IE
INTE
RBIE
TMR0IF
INTF
RBIF
0000 000x
21, 96
ADIE
RCIE
TXIE
SSPIE
CCP1IE
TMR2IE
TMR1IE
0000 0000
22, 97
—
—
—
—
—
—
—
CCP2IE
---- ---0
24, 97
—
—
—
—
—
—
POR
BOR
---- --qq
22, 97
Unimplemented
—
—
—
Unimplemented
—
—
91h
—
Unimplemented
—
—
92h
PR2
Timer2 Module Period Register
1111 1111
52, 97
93h
SSPADD
Synchronous Serial Port (I2C™ mode) Address Register
0000 0000
68, 97
94h
SSPSTAT
0000 0000
60, 97
95h
—
Unimplemented
—
—
96h
—
Unimplemented
—
—
97h
—
Unimplemented
—
—
98h
TXSTA
0000 -010
69, 97
99h
SPBRG
Baud Rate Generator Register
0000 0000
71, 97
9Ah
—
Unimplemented
—
9Bh
—
Unimplemented
—
9Ch
—
Unimplemented
—
9Dh
—
Unimplemented
—
9Eh
—
Unimplemented
9Fh
ADCON1
Legend:
Note 1:
2:
3:
4:
5:
6:
(3)
PSPIE
SMP
CSRC
—
CKE
TX9
—
D/A
TXEN
P
SYNC
S
—
R/W
BRGH
UA
TRMT
BF
TX9D
—
—
—
—
PCFG2
PCFG1
PCFG0
---- -000
84, 97
x = unknown, u = unchanged, q = value depends on condition, – = unimplemented, read as ‘0’, r = reserved.
Shaded locations are unimplemented, read as ‘0’.
The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8>, whose
contents are transferred to the upper byte of the program counter during branches (CALL or GOTO).
Other (non Power-up) Resets include external Reset through MCLR and Watchdog Timer Reset.
Bits PSPIE and PSPIF are reserved on the 28-pin devices; always maintain these bits clear.
These registers can be addressed from any bank.
PORTD, PORTE, TRISD and TRISE are not physically implemented on the 28-pin devices, read as ‘0’.
This bit always reads as a ‘1’.
© 2006 Microchip Technology Inc.
DS21993A-page 17
PIC16CR7X
TABLE 2-1:
Address
SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on:
POR,
BOR
Details
on page
Bank 2
100h(4)
INDF
Addressing this location uses contents of FSR to address data memory (not a physical register)
0000 0000
27, 96
101h
TMR0
Timer0 Module Register
xxxx xxxx
45, 96
102h(4)
PCL
Program Counter (PC) Least Significant Byte
0000 0000
26, 96
103h(4)
STATUS
0001 1xxx
19, 96
104h(4)
FSR
Indirect Data Memory Address Pointer
xxxx xxxx
27, 96
105h
—
Unimplemented
106h
PORTB
PORTB Data Latch when written: PORTB pins when read
107h
—
108h
—
109h
—
10Ah(1,4)
PCLATH
10Bh(4)
INTCON
10Ch
PMDATA
Data Register Low Byte
10Dh
PMADR
Address Register Low Byte
10Eh
PMDATH
—
—
10Fh
PMADRH
—
—
IRP
RP1
RP0
TO
PD
Z
DC
C
—
—
xxxx xxxx
34, 96
Unimplemented
—
—
Unimplemented
—
—
Unimplemented
—
—
---0 0000
26, 96
0000 000x
21, 96
xxxx xxxx
29, 97
xxxx xxxx
29, 97
xxxx xxxx
29, 97
xxxx xxxx
29, 97
0000 0000
27, 96
—
—
—
GIE
PEIE
TMR0IE
Write Buffer for the upper 5 bits of the Program Counter
INTE
RBIE
TMR0IF
INTF
RBIF
Data Register High Byte
—
Address Register High Byte
Bank 3
180h(4)
INDF
181h
OPTION_REG
182h(4)
PCL
183h(4)
STATUS
184h(4)
FSR
Addressing this location uses contents of FSR to address data memory (not a physical register)
RBPU
INTEDG
T0CS
T0SE
PSA
PS2
PS1
PS0
PD
Z
DC
C
Program Counter (PC) Least Significant Byte
IRP
RP1
RP0
TO
Indirect Data Memory Address Pointer
185h
—
Unimplemented
186h
TRISB
PORTB Data Direction Register
187h
—
188h
—
189h
—
18Ah(1,4)
PCLATH
1111 1111 20, 44, 96
0000 0000
26, 96
0001 1xxx
19, 96
xxxx xxxx
27, 96
—
—
1111 1111
34, 96
Unimplemented
—
—
Unimplemented
—
—
Unimplemented
—
—
---0 0000
26, 96
—
—
—
Write Buffer for the upper 5 bits of the Program Counter
18Bh(4)
INTCON
GIE
PEIE
TMR0IE
INTE
RBIE
TMR0IF
INTF
RBIF
0000 000x
21, 96
18Ch
PMCON1
— (6)
—
—
—
—
—
—
RD
1--- ---0
29, 97
18Dh
—
Unimplemented
18Eh
—
Reserved maintain clear
0000 0000
18Fh
—
Reserved maintain clear
0000 0000
Legend:
Note 1:
2:
3:
4:
5:
6:
—
x = unknown, u = unchanged, q = value depends on condition, – = unimplemented, read as ‘0’, r = reserved.
Shaded locations are unimplemented, read as ‘0’.
The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8>, whose
contents are transferred to the upper byte of the program counter during branches (CALL or GOTO).
Other (non Power-up) Resets include external Reset through MCLR and Watchdog Timer Reset.
Bits PSPIE and PSPIF are reserved on the 28-pin devices; always maintain these bits clear.
These registers can be addressed from any bank.
PORTD, PORTE, TRISD and TRISE are not physically implemented on the 28-pin devices, read as ‘0’.
This bit always reads as a ‘1’.
DS21993A-page 18
© 2006 Microchip Technology Inc.
PIC16CR7X
2.2.2.1
STATUS Register
The STATUS register contains the arithmetic status of
the ALU, the Reset status and the bank select bits for
data memory.
The STATUS register can be the destination for any
instruction, as with any other register. If the STATUS
register is the destination for an instruction that affects
the Z, DC or C bits, then the write to these three bits is
disabled. These bits are set or cleared according to the
device logic. Furthermore, the TO and PD bits are not
writable, therefore, the result of an instruction with the
STATUS register as destination may be different than
intended.
REGISTER 2-1:
For example, CLRF STATUS will clear the upper three
bits and set the Z bit. This leaves the STATUS register
as ‘000u u1uu’ (where u = unchanged).
It is recommended, therefore, that only BCF, BSF,
SWAPF and MOVWF instructions are used to alter the
STATUS register, because these instructions do not
affect the Z, C or DC bits from the STATUS register. For
other instructions not affecting any Status bits, see the
“Instruction Set Summary.”
Note 1: The C and DC bits operate as a borrow
and digit borrow bit, respectively, in subtraction. See the SUBLW and SUBWF
instructions for examples.
STATUS: (ADDRESS 03h, 83h, 103h, 183h)
R/W-0
R/W-0
R/W-0
R-1
R-1
R/W-x
R/W-x
R/W-x
IRP
RP1
RP0
TO
PD
Z
DC
C
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
IRP: Register Bank Select bit (used for indirect addressing)
1 = Bank 2, 3 (100h-1FFh)
0 = Bank 0, 1 (00h-FFh)
bit 6-5
RP1:RP0: Register Bank Select bits (used for direct addressing)
11 = Bank 3 (180h-1FFh)
10 = Bank 2 (100h-17Fh)
01 = Bank 1 (80h-FFh)
00 = Bank 0 (00h-7Fh)
Each bank is 128 bytes
bit 4
TO: Time-out bit
1 = After power-up, CLRWDT instruction or SLEEP instruction
0 = A WDT time-out occurred
bit 3
PD: Power-down bit
1 = After power-up or by the CLRWDT instruction
0 = By execution of the SLEEP instruction
bit 2
Z:
Zero bit
1 = The result of an arithmetic or logic operation is zero
0 = The result of an arithmetic or logic operation is not zero
bit 1
DC: Digit carry/borrow bit (ADDWF, ADDLW, SUBLW, SUBWF instructions)
1 = A carry-out from the 4th low order bit of the result occurred
0 = No carry-out from the 4th low order bit of the result
bit 0
C: Carry/borrow bit (ADDWF, ADDLW, SUBLW, SUBWF instructions)
1 = A carry-out from the Most Significant bit of the result occurred
0 = No carry-out from the Most Significant bit of the result occurred
Note:
For borrow, the polarity is reversed. A subtraction is executed by adding the two’s complement of the
second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high or low order bit
of the source register.
© 2006 Microchip Technology Inc.
DS21993A-page 19
PIC16CR7X
2.2.2.2
OPTION_REG Register
Note:
The OPTION_REG register is a readable and writable
register, which contains various control bits to configure
the TMR0 prescaler/WDT postscaler (single assignable register known also as the prescaler), the External
INT Interrupt, TMR0 and the weak pull-ups on PORTB.
REGISTER 2-2:
To achieve a 1:1 prescaler assignment for
the TMR0 register, assign the prescaler to
the Watchdog Timer.
OPTION_REG: (ADDRESS 81h, 181h)
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
RBPU
INTEDG
T0CS
T0SE
PSA
PS2
PS1
PS0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7
RBPU: PORTB Pull-up Enable bit
1 = PORTB pull-ups are disabled
0 = PORTB pull-ups are enabled by individual PORT latch values
bit 6
INTEDG: Interrupt Edge Select bit
1 = Interrupt on rising edge of RB0/INT pin
0 = Interrupt on falling edge of RB0/INT pin
bit 5
T0CS: TMR0 Clock Source Select bit
1 = Transition on RA4/T0CKI pin
0 = Internal instruction cycle clock (CLKOUT)
bit 4
T0SE: TMR0 Source Edge Select bit
1 = Increment on high-to-low transition on RA4/T0CKI pin
0 = Increment on low-to-high transition on RA4/T0CKI pin
bit 3
PSA: Prescaler Assignment bit
1 = Prescaler is assigned to the WDT
0 = Prescaler is assigned to the Timer0 module
bit 2-0
PS2:PS0: Prescaler Rate Select bits
Bit Value
000
001
010
011
100
101
110
111
DS21993A-page 20
x = Bit is unknown
TMR0 Rate WDT Rate
1:2
1:4
1:8
1 : 16
1 : 32
1 : 64
1 : 128
1 : 256
1:1
1:2
1:4
1:8
1 : 16
1 : 32
1 : 64
1 : 128
© 2006 Microchip Technology Inc.
PIC16CR7X
2.2.2.3
INTCON Register
Note:
The INTCON register is a readable and writable register, which contains various enable and flag bits for the
TMR0 register overflow, RB port change and external
RB0/INT pin interrupts.
REGISTER 2-3:
Interrupt flag bits are set when an interrupt
condition occurs, regardless of the state of
its corresponding enable bit or the global
enable bit, GIE (INTCON<7>). User software should ensure the appropriate interrupt flag bits are clear prior to enabling an
interrupt.
INTCON: (ADDRESS 0Bh, 8Bh, 10Bh, 18Bh)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-x
GIE
PEIE
TMR0IE
INTE
RBIE
TMR0IF
INTF
RBIF
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
GIE: Global Interrupt Enable bit
1 = Enables all unmasked interrupts
0 = Disables all interrupts
bit 6
PEIE: Peripheral Interrupt Enable bit
1 = Enables all unmasked peripheral interrupts
0 = Disables all peripheral interrupts
bit 5
TMR0IE: TMR0 Overflow Interrupt Enable bit
1 = Enables the TMR0 interrupt
0 = Disables the TMR0 interrupt
bit 4
INTE: RB0/INT External Interrupt Enable bit
1 = Enables the RB0/INT external interrupt
0 = Disables the RB0/INT external interrupt
bit 3
RBIE: RB Port Change Interrupt Enable bit
1 = Enables the RB port change interrupt
0 = Disables the RB port change interrupt
bit 2
TMR0IF: TMR0 Overflow Interrupt Flag bit
1 = TMR0 register has overflowed (must be cleared in software)
0 = TMR0 register did not overflow
bit 1
INTF: RB0/INT External Interrupt Flag bit
1 = The RB0/INT external interrupt occurred (must be cleared in software)
0 = The RB0/INT external interrupt did not occur
bit 0
RBIF: RB Port Change Interrupt Flag bit
A mismatch condition will continue to set flag bit RBIF. Reading PORTB will end the mismatch
condition and allow flag bit RBIF to be cleared.
1 = At least one of the RB7:RB4 pins changed state (must be cleared in software)
0 = None of the RB7:RB4 pins have changed state
© 2006 Microchip Technology Inc.
DS21993A-page 21
PIC16CR7X
2.2.2.4
PIE1 Register
Note:
The PIE1 register contains the individual enable bits for
the peripheral interrupts.
REGISTER 2-4:
Bit PEIE (INTCON<6>) must be set to
enable any peripheral interrupt.
PIE1: (ADDRESS 8Ch)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
PSPIE(1)
ADIE
RCIE
TXIE
SSPIE
CCP1IE
TMR2IE
TMR1IE
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7
PSPIE(1): Parallel Slave Port Read/Write Interrupt Enable bit
1 = Enables the PSP read/write interrupt
0 = Disables the PSP read/write interrupt
bit 6
ADIE: A/D Converter Interrupt Enable bit
1 = Enables the A/D converter interrupt
0 = Disables the A/D converter interrupt
bit 5
RCIE: USART Receive Interrupt Enable bit
1 = Enables the USART receive interrupt
0 = Disables the USART receive interrupt
bit 4
TXIE: USART Transmit Interrupt Enable bit
1 = Enables the USART transmit interrupt
0 = Disables the USART transmit interrupt
bit 3
SSPIE: Synchronous Serial Port Interrupt Enable bit
1 = Enables the SSP interrupt
0 = Disables the SSP interrupt
bit 2
CCP1IE: CCP1 Interrupt Enable bit
1 = Enables the CCP1 interrupt
0 = Disables the CCP1 interrupt
bit 1
TMR2IE: TMR2 to PR2 Match Interrupt Enable bit
1 = Enables the TMR2 to PR2 match interrupt
0 = Disables the TMR2 to PR2 match interrupt
bit 0
TMR1IE: TMR1 Overflow Interrupt Enable bit
1 = Enables the TMR1 overflow interrupt
0 = Disables the TMR1 overflow interrupt
Note 1:
x = Bit is unknown
PSPIE is reserved on 28-pin devices; always maintain this bit clear.
DS21993A-page 22
© 2006 Microchip Technology Inc.
PIC16CR7X
2.2.2.5
PIR1 Register
Note:
The PIR1 register contains the individual flag bits for
the peripheral interrupts.
REGISTER 2-5:
Interrupt flag bits are set when an interrupt
condition occurs, regardless of the state of
its corresponding enable bit or the global
enable bit, GIE (INTCON<7>). User software should ensure the appropriate interrupt
bits are clear prior to enabling an interrupt.
PIR1: (ADDRESS 0Ch)
R/W-0
R/W-0
R-0
R-0
R/W-0
R/W-0
R/W-0
R/W-0
PSPIF(1)
ADIF
RCIF
TXIF
SSPIF
CCP1IF
TMR2IF
TMR1IF
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
PSPIF(1): Parallel Slave Port Read/Write Interrupt Flag bit
1 = A read or a write operation has taken place (must be cleared in software)
0 = No read or write has occurred
bit 6
ADIF: A/D Converter Interrupt Flag bit
1 = An A/D conversion is completed (must be cleared in software)
0 = The A/D conversion is not complete
bit 5
RCIF: USART Receive Interrupt Flag bit
1 = The USART receive buffer is full
0 = The USART receive buffer is empty
bit 4
TXIF: USART Transmit Interrupt Flag bit
1 = The USART transmit buffer is empty
0 = The USART transmit buffer is full
bit 3
SSPIF: Synchronous Serial Port (SSP) Interrupt Flag
1 = The SSP interrupt condition has occurred, and must be cleared in software before
returning from the Interrupt Service Routine. The conditions that will set this bit are:
SPI
A transmission/reception has taken place.
I2 C Slave
A transmission/reception has taken place.
I2 C Master
A transmission/reception has taken place.
The initiated Start condition was completed by the SSP module.
The initiated Stop condition was completed by the SSP module.
The initiated Restart condition was completed by the SSP module.
The initiated Acknowledge condition was completed by the SSP module.
A Start condition occurred while the SSP module was Idle (multi-master system).
A Stop condition occurred while the SSP module was Idle (multi-master system).
0 = No SSP interrupt condition has occurred
bit 2
CCP1IF: CCP1 Interrupt Flag bit
Capture mode:
1 = A TMR1 register capture occurred (must be cleared in software)
0 = No TMR1 register capture occurred
Compare mode:
1 = A TMR1 register compare match occurred (must be cleared in software)
0 = No TMR1 register compare match occurred
PWM mode:
Unused in this mode
bit 1
TMR2IF: TMR2 to PR2 Match Interrupt Flag bit
1 = TMR2 to PR2 match occurred (must be cleared in software)
0 = No TMR2 to PR2 match occurred
bit 0
TMR1IF: TMR1 Overflow Interrupt Flag bit
1 = TMR1 register overflowed (must be cleared in software)
0 = TMR1 register did not overflow
Note 1:
PSPIF is reserved on 28-pin devices; always maintain this bit clear.
© 2006 Microchip Technology Inc.
DS21993A-page 23
PIC16CR7X
2.2.2.6
PIE2 Register
The PIE2 register contains the individual enable bits for
the CCP2 peripheral interrupt.
REGISTER 2-6:
PIE2: (ADDRESS 8Dh)
U-0
U-0
U-0
U-0
U-0
U-0
U-0
R/W-0
—
—
—
—
—
—
—
CCP2IE
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-1
Unimplemented: Read as ‘0’
bit 0
CCP2IE: CCP2 Interrupt Enable bit
1 = Enables the CCP2 interrupt
0 = Disables the CCP2 interrupt
2.2.2.7
x = Bit is unknown
PIR2 Register
The PIR2 register contains the flag bits for the CCP2
interrupt.
REGISTER 2-7:
U-0
Note:
Interrupt flag bits are set when an interrupt
condition occurs, regardless of the state of
its corresponding enable bit or the global
enable bit, GIE (INTCON<7>). User software should ensure the appropriate interrupt flag bits are clear prior to enabling an
interrupt.
PIR2: (ADDRESS 0Dh)
U-0
U-0
U-0
U-0
U-0
U-0
R/W-0
CCP2IF
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7-1
Unimplemented: Read as ‘0’
bit 0
CCP2IF: CCP2 Interrupt Flag bit
Capture mode:
1 = A TMR1 register capture occurred (must be cleared in software)
0 = No TMR1 register capture occurred
Compare mode:
1 = A TMR1 register compare match occurred (must be cleared in software)
0 = No TMR1 register compare match occurred
PWM mode:
Unused
DS21993A-page 24
© 2006 Microchip Technology Inc.
PIC16CR7X
2.2.2.8
PCON Register
Note:
The Power Control (PCON) register contains flag bits
to allow differentiation between a Power-on Reset
(POR), a Brown-out Reset (BOR), a Watchdog Reset
(WDT) and an external MCLR Reset.
REGISTER 2-8:
BOR is unknown on POR. It must be set by
the user and checked on subsequent
Resets to see if BOR is clear, indicating a
brown-out has occurred. The BOR Status
bit is not predictable if the brown-out circuit
is disabled (by clearing the BOREN bit in
the Configuration Word).
PCON: (ADDRESS 8Eh)
U-0
U-0
U-0
U-0
U-0
U-0
R/W-0
R/W-1
—
—
—
—
—
—
POR
BOR
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7-2
Unimplemented: Read as ‘0’
bit 1
POR: Power-on Reset Status bit
1 = No Power-on Reset occurred
0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs)
bit 0
BOR: Brown-out Reset Status bit
1 = No Brown-out Reset occurred
0 = A Brown-out Reset occurred (must be set in software after a Brown-out Reset occurs)
© 2006 Microchip Technology Inc.
DS21993A-page 25
PIC16CR7X
2.3
PCL and PCLATH
The program counter (PC) is 13 bits wide. The low byte
comes from the PCL register, which is a readable and
writable register. The upper bits (PC<12:8>) are not
readable, but are indirectly writable through the
PCLATH register. On any Reset, the upper bits of the
PC will be cleared. Figure 2-1 shows the two situations
for the loading of the PC. The upper example in the
figure shows how the PC is loaded on a write to PCL
(PCLATH<4:0> → PCH). The lower example in the
figure shows how the PC is loaded during a CALL or
GOTO instruction (PCLATH<4:3> → PCH).
FIGURE 2-4:
LOADING OF PC IN
DIFFERENT SITUATIONS
PCH
PCL
12
8
7
0
PC
8
PCLATH<4:0>
5
Instruction with
PCL as
Destination
ALU
PCLATH
PCH
12
11 10
PCL
8
0
7
PC
GOTO,CALL
2
PCLATH<4:3>
11
Opcode <10:0>
PCLATH
2.3.1
Note 1: There are no Status bits to indicate stack
overflow or stack underflow conditions.
2: There are no instructions/mnemonics
called PUSH or POP. These are actions
that occur from the execution of the
CALL, RETURN, RETLW and RETFIE
instructions, or the vectoring to an interrupt address.
2.4
Program Memory Paging
PIC16CR7X devices are capable of addressing a continuous 8K word block of program memory. The CALL
and GOTO instructions provide only 11 bits of address to
allow branching within any 2K program memory page.
When doing a CALL or GOTO instruction, the upper 2
bits of the address are provided by PCLATH<4:3>.
When doing a CALL or GOTO instruction, the user must
ensure that the page select bits are programmed so
that the desired program memory page is addressed. If
a return from a CALL instruction (or interrupt) is executed, the entire 13-bit PC is popped off the stack.
Therefore, manipulation of the PCLATH<4:3> bits are
not required for the RETURN instructions (which POPs
the address from the stack).
Note:
The contents of the PCLATH are
unchanged after a RETURN or RETFIE
instruction is executed. The user must
setup the PCLATH for any subsequent
CALLS or GOTOS.
COMPUTED GOTO
A computed GOTO is accomplished by adding an offset
to the program counter (ADDWF PCL). When doing a
table read using a computed GOTO method, care
should be exercised if the table location crosses a PCL
memory boundary (each 256 byte block). Refer to the
Application Note, “Implementing a Table Read”
(AN556).
2.3.2
The stack operates as a circular buffer. This means that
after the stack has been PUSHed eight times, the ninth
push overwrites the value that was stored from the first
push. The tenth push overwrites the second push (and
so on).
Example 2-1 shows the calling of a subroutine in
page 1 of the program memory. This example assumes
that PCLATH is saved and restored by the Interrupt
Service Routine (if interrupts are used).
EXAMPLE 2-1:
STACK
The PIC16CR7X family has an 8-level deep x 13-bit
wide hardware stack. The stack space is not part of
either program or data space and the Stack Pointer is
not readable or writable. The PC is PUSHed onto the
stack when a CALL instruction is executed, or an interrupt causes a branch. The stack is POPed in the event
of a RETURN, RETLW or a RETFIE instruction execution. PCLATH is not affected by a PUSH or POP
operation.
ORG
BCF
BSF
0x500
PCLATH,4
PCLATH,3 ;Select page 1
;(800h-FFFh)
CALL SUB1_P1 ;Call subroutine in
:
;page 1 (800h-FFFh)
:
ORG
0x900
;page 1 (800h-FFFh)
SUB1_P1
:
:
:
RETURN
DS21993A-page 26
CALL OF A SUBROUTINE
IN PAGE 1 FROM PAGE 0
;called subroutine
;page 1 (800h-FFFh)
;return to Call
;subroutine in page 0
;(000h-7FFh)
© 2006 Microchip Technology Inc.
PIC16CR7X
2.5
EXAMPLE 2-2:
Indirect Addressing, INDF and FSR
Registers
MOVLW
MOVWF
NEXT
CLRF
INCF
BTFSS
GOTO
CONTINUE
:
The INDF register is not a physical register. Addressing
the INDF register will cause indirect addressing.
Indirect addressing is possible by using the INDF register. Any instruction using the INDF register actually
accesses the register pointed to by the File Select Register (FSR). Reading the INDF register itself indirectly
(FSR = 0) will read 00h. Writing to the INDF register
indirectly results in a no operation (although Status bits
may be affected). An effective 9-bit address is obtained
by concatenating the 8-bit FSR register and the IRP bit
(STATUS<7>), as shown in Figure 2-2.
INDIRECT ADDRESSING
0x20
FSR
INDF
FSR,F
FSR,4
NEXT
;initialize pointer
;to RAM
;clear INDF register
;inc pointer
;all done?
;no clear next
;yes continue
A simple program to clear RAM locations 20h-2Fh
using indirect addressing is shown in Example 2-2.
FIGURE 2-5:
DIRECT/INDIRECT ADDRESSING
Direct Addressing
RP1:RP0
Bank Select
6
Indirect Addressing
From Opcode
0
IRP
7
Bank Select
Location Select
00
01
10
FSR Register
0
Location Select
11
00h
80h
100h
180h
7Fh
FFh
17Fh
1FFh
Data
Memory(1)
Bank 0
Note 1:
Bank 1
Bank 2
Bank 3
For register file map detail, see Figure 2-2.
© 2006 Microchip Technology Inc.
DS21993A-page 27
PIC16CR7X
NOTES:
DS21993A-page 28
© 2006 Microchip Technology Inc.
PIC16CR7X
3.0
READING PROGRAM MEMORY
The ROM Program Memory is readable during normal
operation over the entire VDD range. It is indirectly
addressed through Special Function Registers (SFR).
Up to 14-bit numbers can be stored in memory for use
as calibration parameters, serial numbers, packed 7-bit
ASCII, etc. Executing a program memory location
containing data that forms an invalid instruction results
in a NOP.
When interfacing to the program memory block, the
PMDATH:PMDATA registers form a two-byte word,
which holds the 14-bit data for reads. The
PMADRH:PMADR registers form a two-byte word,
which holds the 13-bit address of the ROM location
being accessed. These devices can have up to 8K
words of program ROM, with an address range from 0h
to 3FFFh. The unused upper bits in both the PMDATH
and PMADRH registers are not implemented and read
as ‘0’s.
There are five SFRs used to read the program and
memory. These registers are:
3.1
•
•
•
•
•
PMADR
The address registers can address up to a maximum of
8K words of program ROM.
PMCON1
PMDATA
PMDATH
PMADR
PMADRH
The program memory allows word reads. Program
memory access allows for checksum calculation and
reading calibration tables.
When selecting a program address value, the MSByte
of the address is written to the PMADRH register and
the LSByte is written to the PMADR register. The upper
MSbits of PMADRH must always be clear.
3.2
PMCON1 Register
PMCON1 is the control register for memory accesses.
The control bit RD initiates read operations. This bit
cannot be cleared, only set, in software. It is cleared in
hardware at the completion of the read operation.
REGISTER 3-1:
PMCON1: (ADDRESS 18Ch)
R-1
U-0
U-0
U-0
U-x
U-0
U-0
R/S-0
reserved
—
—
—
—
—
—
RD
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
Reserved: Read as ‘1’
bit 6-1
Unimplemented: Read as ‘0’
bit 0
RD: Read Control bit
1 = Initiates a ROM read, RD is cleared in hardware. The RD bit can only be set (not cleared) in
software.
0 = ROM read completed
© 2006 Microchip Technology Inc.
DS21993A-page 29
PIC16CR7X
3.3
Reading the ROM Program
Memory
3.4
ROM program memory has its own code-protect mechanism. External Read operations by programmers are
disabled if this mechanism is enabled.
A program memory location may be read by writing two
bytes of the address to the PMADR and PMADRH registers and then setting control bit RD (PMCON1<0>).
Once the read control bit is set, the microcontroller will
use the next two instruction cycles to read the data. The
data is available in the PMDATA and PMDATH registers after the second NOP instruction. Therefore, it can
be read as two bytes in the following instructions. The
PMDATA and PMDATH registers will hold this value
until the next read operation.
EXAMPLE 3-1:
Required
Sequence
10Dh
The microcontroller can read and execute instructions
out of the internal ROM program memory, regardless of
the state of the code-protect Configuration bits.
ROM PROGRAM READ
BSF
BCF
MOVF
MOVWF
MOVF
MOVWF
BSF
STATUS, RP1
STATUS, RP0
ADDRH, W
PMADRH
ADDRL, W
PMADR
STATUS, RP0
;
;
;
;
;
;
;
BSF
NOP
NOP
PMCON1, RD
; ROM Read Sequence
; memory is read in the next two cycles after BSF PMCON1,RD
;
BCF
MOVF
MOVF
STATUS, RP0
PMDATA, W
PMDATH, W
; Bank 2
; W = LSByte of Program PMDATA
; W = MSByte of Program PMDATA
TABLE 3-1:
Address
Operation During Code-Protect
Bank 2
MSByte of Program Address to read
LSByte of Program Address to read
Bank 3 Required
REGISTERS ASSOCIATED WITH PROGRAM ROM
Name
PMADR
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Address Register Low Byte
Value on:
POR,
BOR
Value on
all other
Resets
xxxx xxxx uuuu uuuu
10Fh
PMADRH
10Ch
PMDATA Data Register Low Byte
xxxx xxxx uuuu uuuu
10Eh
PMDATH
—
—
xxxx xxxx uuuu uuuu
PMCON1
—(1)
—
18Ch
Legend:
Note 1:
—
—
—
Address Register High Byte
xxxx xxxx uuuu uuuu
Data Register High Byte
—
—
—
—
—
RD
1--- ---0 1--- ---0
x = unknown, u = unchanged, r = reserved, - = unimplemented read as ‘0’. Shaded cells are not used during ROM
access.
This bit always reads as a ‘1’.
DS21993A-page 30
© 2006 Microchip Technology Inc.
PIC16CR7X
4.0
I/O PORTS
FIGURE 4-1:
Some pins for these I/O ports are multiplexed with an
alternate function for the peripheral features on the
device. In general, when a peripheral is enabled, that
pin may not be used as a general purpose I/O pin.
Additional information on I/O ports may be found in the
“PICmicro® Mid-Range MCU Family Reference
Manual” (DS33023).
Data Bus
BLOCK DIAGRAM OF
RA3:RA0 AND RA5 PINS
D
Q
VDD
WR Port
CK
Q
P
Data Latch
I/O pin(1)
N
4.1
PORTA and the TRISA Register
PORTA is a 6-bit wide, bidirectional port. The corresponding data direction register is TRISA. Setting a
TRISA bit (= 1) will make the corresponding PORTA pin
an input (i.e., put the corresponding output driver in a
High-Impendance mode). Clearing a TRISA bit (= 0)
will make the corresponding PORTA pin an output (i.e.,
put the contents of the output latch on the selected pin).
Reading the PORTA register reads the status of the
pins, whereas writing to it will write to the PORT latch.
All write operations are read-modify-write operations.
Therefore, a write to a port implies that the port pins are
read, the value is modified and then written to the
PORT data latch.
Pin RA4 is multiplexed with the Timer0 module clock
input to become the RA4/T0CKI pin. The RA4/T0CKI
pin is a Schmitt Trigger input and an open drain output.
All other PORTA pins have TTL input levels and full
CMOS output drivers.
Other PORTA pins are multiplexed with analog inputs
and analog VREF input. The operation of each pin is
selected by clearing/setting the control bits in the
ADCON1 register (A/D Control Register1).
Note:
On a Power-on Reset, these pins are
configured as analog inputs and read as
‘0’.
The TRISA register controls the direction of the RA
pins, even when they are being used as analog inputs.
The user must ensure the bits in the TRISA register are
maintained set, when using them as analog inputs.
WR TRIS
D
Q
CK
Q
VSS
Analog
Input
Mode
TRIS Latch
TTL
Input
Buffer
RD TRIS
Q
ENEN
RD PORT
To A/D Converter
Note
1:
I/O pins have protection diodes to VDD and VSS.
FIGURE 4-2:
Data Bus
WR PORT
BLOCK DIAGRAM OF
RA4/T0CKI PIN
D
Q
CK
Q
N
Data Latch
WR TRIS
D
Q
VSS
CK
Q
Schmitt
Trigger
Input
Buffer
TRIS Latch
EXAMPLE 4-1:
BCF
BCF
CLRF
INITIALIZING PORTA
STATUS, RP0
STATUS, RP1
PORTA
BSF
MOVLW
MOVWF
MOVLW
STATUS, RP0
0x06
ADCON1
0xCF
MOVWF
TRISA
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
Bank0
Initialize PORTA by
clearing output
data latches
Select Bank 1
Configure all pins
as digital inputs
Value used to
initialize data
direction
Set RA<3:0> as inputs
RA<5:4> as outputs
TRISA<7:6>are always
read as ‘0’.
© 2006 Microchip Technology Inc.
D
I/O pin(1)
RD TRIS
Q
D
ENEN
RD PORT
TMR0 Clock Input
Note
1:
I/O pin has protection diodes to VSS only.
DS21993A-page 31
PIC16CR7X
TABLE 4-1:
PORTA FUNCTIONS
Name
Bit#
Buffer
Function
RA0/AN0
bit 0
TTL
Input/output or analog input.
RA1/AN1
bit 1
TTL
Input/output or analog input.
RA2/AN2
bit 2
TTL
Input/output or analog input.
RA3/AN3/VREF
bit 3
TTL
Input/output or analog input or VREF.
RA4/T0CKI
bit 4
ST
Input/output or external clock input for Timer0. Output is open drain type.
RA5/AN4/SS
bit 5
TTL
Input/output or slave select input for synchronous serial port or analog input.
Legend: TTL = TTL input, ST = Schmitt Trigger input
TABLE 4-2:
Address
SUMMARY OF REGISTERS ASSOCIATED WITH PORTA
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on: Value on all
POR,
other
BOR
Resets
RA5
RA4
RA3
RA2
RA1
RA0
--0x 0000
--0u 0000
--11 1111
--11 1111
PCFG2 PCFG1 PCFG0 ---- -000
---- -000
05h
PORTA
—
—
85h
TRISA
—
—
9Fh
ADCON1
—
—
PORTA Data Direction Register
—
—
—
Legend: x = unknown, u = unchanged, – = unimplemented locations read as ‘0’. Shaded cells are not used by
PORTA.
Note:
When using the SSP module in SPI Slave mode and SS enabled, the A/D converter must be set to one of
the following modes where PCFG2:PCFG0 = 100, 101, 11x.
DS21993A-page 32
© 2006 Microchip Technology Inc.
PIC16CR7X
4.2
PORTB and the TRISB Register
PORTB is an 8-bit wide, bidirectional port. The corresponding data direction register is TRISB. Setting a
TRISB bit (= 1) will make the corresponding PORTB
pin an input (i.e., put the corresponding output driver in
a High-Impendance mode). Clearing a TRISB bit (= 0)
will make the corresponding PORTB pin an output (i.e.,
put the contents of the output latch on the selected pin).
Each of the PORTB pins has a weak internal pull-up. A
single control bit can turn on all the pull-ups. This is performed by clearing bit RBPU (OPTION_REG<7>). The
weak pull-up is automatically turned off when the port
pin is configured as an output. The pull-ups are
disabled on a Power-on Reset.
FIGURE 4-3:
BLOCK DIAGRAM OF
RB3:RB0 PINS
VDD
RBPU(2)
Data Bus
WR Port
Weak
P Pull-up
Data Latch
D
Q
I/O
pin(1)
CK
TRIS Latch
D
Q
WR TRIS
TTL
Input
Buffer
CK
This interrupt can wake the device from Sleep. The
user, in the Interrupt Service Routine, can clear the
interrupt in the following manner:
a)
b)
Any read or write of PORTB. This will end the
mismatch condition.
Clear flag bit RBIF.
A mismatch condition will continue to set flag bit RBIF.
Reading PORTB will end the mismatch condition and
allow flag bit RBIF to be cleared.
The interrupt-on-change feature is recommended for
wake-up on key depression operation and operations
where PORTB is only used for the interrupt-on-change
feature. Polling of PORTB is not recommended while
using the interrupt-on-change feature.
This interrupt on mismatch feature, together with software configureable pull-ups on these four pins, allow
easy interface to a keypad and make it possible for
wake-up on key depression. Refer to the Embedded
Control Handbook, “Implementing Wake-up on Key
Stroke” (AN552).
RB0/INT is an external interrupt input pin and is
configured using the INTEDG bit (OPTION_REG<6>).
RB0/INT is discussed in detail in Section 12.11.1 “INT
Interrupt”.
FIGURE 4-4:
BLOCK DIAGRAM OF
RB7:RB4 PINS
VDD
RBPU(2)
RD TRIS
Q
D
Data Bus
RD Port
Weak
P Pull-up
Data Latch
D
Q
EN
WR Port
TRIS Latch
D
Q
RB0/INT
Schmitt Trigger
Buffer
I/O
pin(1)
CK
RD Port
WR TRIS
TTL
Input
Buffer
CK
Note 1: I/O pins have diode protection to VDD and VSS.
2: To enable weak pull-ups, set the appropriate TRIS
bit(s) and clear the RBPU bit (OPTION_REG<7>).
RD TRIS
Latch
Four of the PORTB pins (RB7:RB4) have an interrupton-change feature. Only pins configured as inputs can
cause this interrupt to occur (i.e., any RB7:RB4 pin
configured as an output is excluded from the interrupton-change comparison). The input pins (of RB7:RB4)
are compared with the old value latched on the last
read of PORTB. The “mismatch” outputs of RB7:RB4
are ORed together to generate the RB Port Change
Interrupt with flag bit RBIF (INTCON<0>).
Q
EN
Q1
Set RBIF
Q
From other
RB7:RB4 pins
Note
© 2006 Microchip Technology Inc.
D
RD Port
1:
2:
D
RD Port
EN
Q3
I/O pins have diode protection to VDD and VSS.
To enable weak pull-ups, set the appropriate TRIS
bit(s) and clear the RBPU bit (OPTION_REG<7>).
DS21993A-page 33
PIC16CR7X
TABLE 4-3:
Name
PORTB FUNCTIONS
Bit#
Buffer
(1)
Function
RB0/INT
bit 0
TTL/ST
Input/output pin or external interrupt input. Internal software
programmable weak pull-up.
RB1
bit 1
TTL
Input/output pin. Internal software programmable weak pull-up.
RB2
bit 2
TTL
Input/output pin. Internal software programmable weak pull-up.
RB3
bit 3
TTL
Input/output pin. Internal software programmable weak pull-up.
RB4
bit 4
TTL
Input/output pin (with interrupt-on-change). Internal software programmable
weak pull-up.
RB5
bit 5
TTL
Input/output pin (with interrupt-on-change). Internal software programmable
weak pull-up.
RB6
bit 6
TTL
Input/output pin (with interrupt-on-change). Internal software programmable
weak pull-up.
RB7
bit 7
TTL
Input/output pin (with interrupt-on-change). Internal software programmable
weak pull-up.
Legend: TTL = TTL input, ST = Schmitt Trigger input
Note 1: This buffer is a Schmitt Trigger input when configured as the external interrupt.
TABLE 4-4:
Address
06h, 106h
SUMMARY OF REGISTERS ASSOCIATED WITH PORTB
Name
PORTB
86h, 186h
TRISB
81h, 181h
OPTION_REG
Legend:
Value on:
POR,
BOR
Value on
all other
Resets
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RB7
RB6
RB5
RB4
RB3
RB2
RB1
RB0
xxxx xxxx uuuu uuuu
T0SE
PSA
PS2
PS1
PS0
1111 1111 1111 1111
PORTB Data Direction Register
RBPU
INTEDG
T0CS
1111 1111 1111 1111
x = unknown, u = unchanged. Shaded cells are not used by PORTB.
DS21993A-page 34
© 2006 Microchip Technology Inc.
PIC16CR7X
4.3
FIGURE 4-5:
PORTC and the TRISC Register
PORTC is an 8-bit wide, bidirectional port. The corresponding data direction register is TRISC. Setting a
TRISC bit (= 1) will make the corresponding PORTC
pin an input (i.e., put the corresponding output driver in
a High-Impendance mode). Clearing a TRISC bit (= 0)
will make the corresponding PORTC pin an output (i.e.,
put the contents of the output latch on the selected pin).
Port/Peripheral Select(2)
Peripheral Data Out
VDD
0
Data Bus
D
Q
P
1
WR Port
PORTC is multiplexed with several peripheral functions
(Table 4-5). PORTC pins have Schmitt Trigger input
buffers.
CK
Q
Data Latch
D
WR TRIS
When enabling peripheral functions, care should be
taken in defining TRIS bits for each PORTC pin. Some
peripherals override the TRIS bit to make a pin an
output, while other peripherals override the TRIS bit to
make a pin an input. Since the TRIS bit override is
in effect while the peripheral is enabled, read-modifywrite instructions (BSF, BCF, XORWF) with TRISC as
destination should be avoided. The user should refer to
the corresponding peripheral section for the correct
TRIS bit settings, and to Section 13.1 “READ-MODIFY-WRITE OPERATIONS” for additional information
on read-modify-write operations.
CK
I/O
pin(1)
Q
Q
N
TRIS Latch
VSS
RD TRIS
Schmitt
Trigger
Peripheral
OE(3)
Q
D
EN
RD Port
Peripheral Input
Note
1:
2:
3:
TABLE 4-5:
PORTC BLOCK DIAGRAM
(PERIPHERAL OUTPUT
OVERRIDE)
I/O pins have diode protection to VDD and VSS.
Port/Peripheral select signal selects between PORT
data and peripheral output.
Peripheral OE (output enable) is only activated if
peripheral select is active.
PORTC FUNCTIONS
Name
Bit#
Buffer Type
Function
RC0/T1OSO/T1CKI
bit 0
ST
Input/output port pin or Timer1 oscillator output/Timer1 clock input.
RC1/T1OSI/CCP2
bit 1
ST
Input/output port pin or Timer1 oscillator input or Capture2 input/
Compare2 output/PWM2 output.
RC2/CCP1
bit 2
ST
Input/output port pin or Capture1 input/Compare1 output/PWM1 output.
RC3/SCK/SCL
bit 3
ST
RC3 can also be the synchronous serial clock for both SPI and I2C™
modes.
RC4/SDI/SDA
bit 4
ST
RC4 can also be the SPI Data In (SPI mode) or Data I/O (I2C™ mode).
RC5/SDO
bit 5
ST
Input/output port pin or Synchronous Serial Port data output.
RC6/TX/CK
bit 6
ST
Input/output port pin or USART Asynchronous Transmit or
Synchronous Clock.
RC7/RX/DT
bit 7
ST
Input/output port pin or USART Asynchronous Receive or
Synchronous Data.
Legend: ST = Schmitt Trigger input
TABLE 4-6:
Address
SUMMARY OF REGISTERS ASSOCIATED WITH PORTC
Name
07h
PORTC
87h
TRISC
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RC7
RC6
RC5
RC4
RC3
RC2
RC1
RC0
PORTC Data Direction Register
Value on:
POR,
BOR
Value on
all other
Resets
xxxx xxxx uuuu uuuu
1111 1111 1111 1111
Legend: x = unknown, u = unchanged
© 2006 Microchip Technology Inc.
DS21993A-page 35
PIC16CR7X
4.4
FIGURE 4-6:
PORTD and TRISD Registers
This section is not applicable to the PIC16CR73 or
PIC16CR76.
PORTD is an 8-bit port with Schmitt Trigger input buffers. Each pin is individually configureable as an input or
output.
PORTD BLOCK DIAGRAM
(IN I/O PORT MODE)
Data Bus
D
WR Port
CK
Q
I/O pin(1)
Data Latch
PORTD can be configured as an 8-bit wide microprocessor port (parallel slave port) by setting control bit
PSPMODE (TRISE<4>). In this mode, the input buffers
are TTL.
D
WR TRIS
Q
Schmitt
Trigger
Input
Buffer
CK
TRIS Latch
RD TRIS
Q
D
ENEN
RD Port
Note 1: I/O pins have protection diodes to VDD and VSS.
TABLE 4-7:
Name
PORTD FUNCTIONS
Bit#
Buffer Type
Function
RD0/PSP0
bit 0
ST/TTL(1)
Input/output port pin or parallel slave port bit 0
RD1/PSP1
bit 1
ST/TTL(1)
Input/output port pin or parallel slave port bit 1
RD2/PSP2
bit 2
ST/TTL(1)
Input/output port pin or parallel slave port bit 2
RD3/PSP3
bit 3
ST/TTL(1)
Input/output port pin or parallel slave port bit 3
RD4/PSP4
bit 4
ST/TTL(1)
Input/output port pin or parallel slave port bit 4
RD5/PSP5
bit 5
ST/TTL
(1)
Input/output port pin or parallel slave port bit 5
RD6/PSP6
bit 6
ST/TTL(1)
Input/output port pin or parallel slave port bit 6
RD7/PSP7
bit 7
ST/TTL(1)
Input/output port pin or parallel slave port bit
Legend: ST = Schmitt Trigger input, TTL = TTL input
Note 1: Input buffers are Schmitt Triggers when in I/O mode and TTL buffers when in Parallel Slave Port mode.
TABLE 4-8:
SUMMARY OF REGISTERS ASSOCIATED WITH PORTD
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on:
POR,
BOR
Value on
all other
Resets
08h
PORTD
RD7
RD6
RD5
RD4
RD3
RD2
RD1
RD0
xxxx xxxx
uuuu uuuu
88h
TRISD
89h
TRISE
Legend:
x = unknown, u = unchanged, - = unimplemented read as ‘0’. Shaded cells are not used by PORTD.
Address
DS21993A-page 36
PORTD Data Direction Register
IBF
OBF
IBOV
PSPMODE
—
PORTE Data Direction bits
1111 1111
1111 1111
0000 -111
0000 -111
© 2006 Microchip Technology Inc.
PIC16CR7X
4.5
PORTE and TRISE Register
This section is not applicable to the PIC16CR73 or
PIC16CR76.
PORTE has three pins, RE0/RD/AN5, RE1/WR/AN6
and RE2/CS/AN7, which are individually configureable
as inputs or outputs. These pins have Schmitt Trigger
input buffers.
I/O PORTE becomes control inputs for the microprocessor port when bit PSPMODE (TRISE<4>) is set.
In this mode, the user must make sure that the
TRISE<2:0> bits are set (pins are configured as digital
inputs). Ensure ADCON1 is configured for digital I/O. In
this mode, the input buffers are TTL.
Register 4-1 shows the TRISE register, which also
controls the parallel slave port operation.
FIGURE 4-7:
Data Bus
D
WR Port
CK
Note:
Q
I/O pin(1)
Data Latch
D
WR TRIS
Q
Schmitt
Trigger
Input
Buffer
CK
TRIS Latch
RD TRIS
Q
PORTE pins are multiplexed with analog inputs. When
selected as an analog input, these pins will read as ‘0’s.
TRISE controls the direction of the RE pins, even when
they are being used as analog inputs. The user must
make sure to keep the pins configured as inputs when
using them as analog inputs.
PORTE BLOCK DIAGRAM
(IN I/O PORT MODE)
D
ENEN
RD Port
Note 1: I/O pins have protection diodes to VDD and VSS.
On a Power-on Reset, these pins are
configured as analog inputs and read as
‘0’.
© 2006 Microchip Technology Inc.
DS21993A-page 37
PIC16CR7X
REGISTER 4-1:
TRISE: (ADDRESS 89h)
R-0
R-0
R/W-0
R/W-0
U-0
R/W-1
R/W-1
R/W-1
IBF
OBF
IBOV
PSPMODE
—
Bit 2
Bit 1
Bit 0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7
Parallel Slave Port Status/Control bits:
IBF: Input Buffer Full Status bit
1 = A word has been received and is waiting to be read by the CPU
0 = No word has been received
bit 6
OBF: Output Buffer Full Status bit
1 = The output buffer still holds a previously written word
0 = The output buffer has been read
bit 5
IBOV: Input Buffer Overflow Detect bit (in Microprocessor mode)
1 = A write occurred when a previously input word has not been read
(must be cleared in software)
0 = No overflow occurred
bit 4
PSPMODE: Parallel Slave Port Mode Select bit
1 = Parallel Slave Port mode
0 = General Purpose I/O mode
bit 3
Unimplemented: Read as ‘0’
bit 2
PORTE Data Direction bits:
Bit 2: Direction Control bit for pin RE2/CS/AN7
1 = Input
0 = Output
bit 1
Bit 1: Direction Control bit for pin RE1/WR/AN6
1 = Input
0 = Output
bit 0
Bit 0: Direction Control bit for pin RE0/RD/AN5
1 = Input
0 = Output
DS21993A-page 38
x = Bit is unknown
© 2006 Microchip Technology Inc.
PIC16CR7X
TABLE 4-9:
Name
PORTE FUNCTIONS
Bit#
Buffer Type
Function
RE0/RD/AN5
bit 0
ST/TTL(1)
Input/output port pin or read control input in Parallel Slave Port mode or
analog input.
For RD (PSP mode):
1 = Idle
0 = Read operation. Contents of PORTD register output to PORTD I/O
pins (if chip selected).
RE1/WR/AN6
bit 1
ST/TTL(1)
Input/output port pin or write control input in Parallel Slave Port mode
or analog input.
For WR (PSP mode):
1 = Idle
0 = Write operation. Value of PORTD I/O pins latched into PORTD
register (if chip selected).
RE2/CS/AN7
bit 2
ST/TTL(1)
Input/output port pin or Chip Select control input in Parallel Slave Port
mode or analog input.
For CS (PSP mode):
1 = Device is not selected
0 = Device is selected
Legend: ST = Schmitt Trigger input, TTL = TTL input
Note 1: Input buffers are Schmitt Triggers when in I/O mode and TTL buffers when in Parallel Slave Port mode.
TABLE 4-10:
Addr
Name
SUMMARY OF REGISTERS ASSOCIATED WITH PORTE
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
09h
PORTE
—
—
—
—
—
89h
TRISE
IBF
OBF
IBOV
PSPMODE
—
9Fh
ADCON1
—
—
—
—
—
Bit 2
Bit 1
Bit 0
Value on:
POR,
BOR
Value on all
other Resets
RE2
RE1
RE0
---- -xxx
---- -uuu
0000 -111
0000 -111
---- -000
---- -000
PORTE Data Direction bits
PCFG2
PCFG1
PCFG0
Legend: x = unknown, u = unchanged, - = unimplemented, read as ‘0’. Shaded cells are not used by PORTE.
© 2006 Microchip Technology Inc.
DS21993A-page 39
PIC16CR7X
4.6
Parallel Slave Port
The Parallel Slave Port (PSP) is not implemented on
the PIC16CR73 or PIC16CR76.
PORTD operates as an 8-bit wide Parallel Slave Port,
or Microprocessor Port, when control bit PSPMODE
(TRISE<4>) is set. In Slave mode, it is asynchronously
readable and writable by an external system using the
read control input pin RE0/RD, the write control input
pin RE1/WR, and the Chip Select control input pin RE2/
CS.
The PSP can directly interface to an 8-bit microprocessor data bus. The external microprocessor can
read or write the PORTD latch as an 8-bit latch. Setting
bit PSPMODE enables port pin RE0/RD to be the RD
input, RE1/WR to be the WR input and RE2/CS to be
the CS (Chip Select) input. For this functionality, the
corresponding data direction bits of the TRISE register
(TRISE<2:0>) must be configured as inputs (i.e., set).
The A/D port Configuration bits PCFG3:PCFG0
(ADCON1<3:0>) must be set to configure pins
RE2:RE0 as digital I/O.
There are actually two 8-bit latches, one for data output
(external reads) and one for data input (external
writes). The firmware writes 8-bit data to the PORTD
output data latch and reads data from the PORTD input
data latch (note that they have the same address). In
this mode, the TRISD register is ignored, since the
external device is controlling the direction of data flow.
An external write to the PSP occurs when the CS and
WR lines are both detected low. Firmware can read the
actual data on the PORTD pins during this time. When
either the CS or WR lines become high (level triggered), the data on the PORTD pins is latched, and the
Input Buffer Full (IBF) status flag bit (TRISE<7>) and
interrupt flag bit PSPIF (PIR1<7>) are set on the Q4
clock cycle, following the next Q2 cycle to signal the
write is complete (Figure 4-9). Firmware clears the IBF
flag by reading the latched PORTD data and clears the
PSPIF bit.
When either the CS or RD pins are detected high, the
PORTD outputs are disabled, and the interrupt flag bit
PSPIF is set on the Q4 clock cycle following the next
Q2 cycle, indicating that the read is complete. OBF
remains low until firmware writes new data to PORTD.
When not in PSP mode, the IBF and OBF bits are held
clear. Flag bit IBOV remains unchanged. The PSPIF bit
must be cleared by the user in firmware; the interrupt
can be disabled by clearing the interrupt enable bit
PSPIE (PIE1<7>).
FIGURE 4-8:
PORTD AND PORTE
BLOCK DIAGRAM
(PARALLEL SLAVE PORT)
Data Bus
D
WR
Port
Q
RDx
pin
CK
TTL
Q
RD
Port
D
ENEN
One bit of PORTD
Set Interrupt Flag
PSPIF (PIR1<7>)
Read
TTL
RD
Chip Select
TTL
CS
Write
TTL
WR
Note: I/O pin has protection diodes to VDD and VSS.
The Input Buffer Overflow (IBOV) status flag bit
(TRISE<5>) is set if an external write to the PSP occurs
while the IBF flag is set from a previous external write.
The previous PORTD data is overwritten with the new
data. IBOV is cleared by reading PORTD and clearing
IBOV.
A read from the PSP occurs when both the CS and RD
lines are detected low. The data in the PORTD output
latch is output to the PORTD pins. The Output Buffer
Full (OBF) status flag bit (TRISE<6>) is cleared immediately (Figure 4-10), indicating that the PORTD latch is
being read, or has been read by the external bus. If
firmware writes new data to the output latch during this
time, it is immediately output to the PORTD pins, but
OBF will remain cleared.
DS21993A-page 40
© 2006 Microchip Technology Inc.
PIC16CR7X
FIGURE 4-9:
PARALLEL SLAVE PORT WRITE WAVEFORMS
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q4
Q1
Q2
Q3
Q4
CS
WR
RD
PORTD<7:0>
IBF
OBF
PSPIF
FIGURE 4-10:
PARALLEL SLAVE PORT READ WAVEFORMS
Q1
Q2
Q3
Q4
Q1
Q2
Q3
CS
WR
RD
PORTD<7:0>
IBF
OBF
PSPIF
TABLE 4-11:
Address
REGISTERS ASSOCIATED WITH PARALLEL SLAVE PORT
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 1
Bit 0
Value on:
POR,
BOR
xxxx xxxx
uuuu uuuu
RE1
RE0
---- -xxx
---- -uuu
PORTE Data Direction Bits
0000 -111
0000 -111
0000 0000
0000 0000
Bit 2
PORT data latch when written: Port pins when read
Value on
all other
Resets
08h
PORTD
09h
PORTE
—
—
89h
TRISE
IBF
OBF
IBOV PSPMODE
0Ch
PIR1
PSPIF(1)
ADIF
RCIF
TXIF
SSPIF
CCP1IF TMR2IF TMR1IF
PSPIE(1)
ADIE
RCIE
TXIE
SSPIE
CCP1IE TMR2IE TMR1IE
0000 0000
0000 0000
—
—
—
—
—
PCFG2
---- -000
---- -000
—
—
—
—
RE2
8Ch
PIE1
9Fh
ADCON1
Legend:
Note 1:
x = unknown, u = unchanged, - = unimplemented, read as ‘0’. Shaded cells are not used by the Parallel Slave Port.
Bits PSPIE and PSPIF are reserved on the PIC16CR73/76; always maintain these bits clear.
© 2006 Microchip Technology Inc.
PCFG1
PCFG0
DS21993A-page 41
PIC16CR7X
NOTES:
DS21993A-page 42
© 2006 Microchip Technology Inc.
PIC16CR7X
5.0
TIMER0 MODULE
Counter mode is selected by setting bit T0CS
(OPTION_REG<5>). In Counter mode, Timer0 will
increment, either on every rising or falling edge of pin
RA4/T0CKI. The incrementing edge is determined by
the Timer0 Source Edge Select bit T0SE
(OPTION_REG<4>). Clearing bit T0SE selects the rising edge. Restrictions on the external clock input are
discussed in detail in Section 5.2 “Using Timer0 with
an External Clock”.
The Timer0 module timer/counter has the following
features:
•
•
•
•
•
•
8-bit timer/counter
Readable and writable
8-bit software programmable prescaler
Internal or external clock select
Interrupt on overflow from FFh to 00h
Edge select for external clock
The prescaler is mutually exclusively shared between
the Timer0 module and the Watchdog Timer. The
prescaler is not readable or writable. Section 5.3
“Prescaler” details the operation of the prescaler.
Additional information on the Timer0 module is
available in the “PICmicro® Mid-Range MCU Family
Reference Manual” (DS33023).
5.1
Figure 5-1 is a block diagram of the Timer0 module and
the prescaler shared with the WDT.
The TMR0 interrupt is generated when the TMR0 register overflows from FFh to 00h. This overflow sets bit
TMR0IF (INTCON<2>). The interrupt can be masked
by clearing bit TMR0IE (INTCON<5>). Bit TMR0IF
must be cleared in software by the Timer0 module
Interrupt Service Routine, before re-enabling this interrupt. The TMR0 interrupt cannot awaken the processor
from Sleep, since the timer is shut-off during Sleep.
Timer0 operation is controlled through the
OPTION_REG register (Register 5-1 on the following
page). Timer mode is selected by clearing bit T0CS
(OPTION_REG<5>). In Timer mode, the Timer0 module will increment every instruction cycle (without prescaler). If the TMR0 register is written, the increment is
inhibited for the following two instruction cycles. The
user can work around this by writing an adjusted value
to the TMR0 register.
FIGURE 5-1:
Timer0 Interrupt
BLOCK DIAGRAM OF THE TIMER0 MODULE AND PRESCALER
Data Bus
CLKOUT (= FOSC/4)
0
RA4/T0CKI
pin
8
M
U
X
1
M
U
X
0
1
SYNC
2
Cycles
TMR0 Reg
T0SE
T0CS
Set Flag bit TMR0IF
on Overflow
PSA
PRESCALER
0
Watchdog
Timer
M
U
X
1
8-bit Prescaler
8
8-to-1 MUX
PS2:PS0
PSA
WDT Enable bit
1
0
MUX
PSA
WDT
Time-out
Note: T0CS, T0SE, PSA, PS2:PS0 are (OPTION_REG<5:0>).
© 2006 Microchip Technology Inc.
DS21993A-page 43
PIC16CR7X
5.2
Using Timer0 with an External
Clock
Q4 cycles of the internal phase clocks. Therefore, it is
necessary for T0CKI to be high for at least 2Tosc (and
a small RC delay of 20 ns) and low for at least 2Tosc
(and a small RC delay of 20 ns). Refer to the electrical
specification of the desired device.
When no prescaler is used, the external clock input is
the same as the prescaler output. The synchronization
of T0CKI, with the internal phase clocks, is accomplished by sampling the prescaler output on the Q2 and
REGISTER 5-1:
OPTION_REG:
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
RBPU
INTEDG
T0CS
T0SE
PSA
PS2
PS1
PS0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
RBPU: PORTB Pull-up Enable bit (see Section 2.2.2.2 “OPTION_REG Register”)
bit 6
INTEDG: Interrupt Edge Select bit (see Section 2.2.2.2 “OPTION_REG Register”)
bit 5
T0CS: TMR0 Clock Source Select bit
1 = Transition on T0CKI pin
0 = Internal instruction cycle clock (CLKOUT)
bit 4
T0SE: TMR0 Source Edge Select bit
1 = Increment on high-to-low transition on T0CKI pin
0 = Increment on low-to-high transition on T0CKI pin
bit 3
PSA: Prescaler Assignment bit
1 = Prescaler is assigned to the WDT
0 = Prescaler is assigned to the Timer0 module
bit 2-0
PS2:PS0: Prescaler Rate Select bits
Note:
Bit Value
TMR0 Rate
WDT Rate
000
001
010
011
100
101
110
111
1:2
1:4
1:8
1 : 16
1 : 32
1 : 64
1 : 128
1 : 256
1:1
1:2
1:4
1:8
1 : 16
1 : 32
1 : 64
1 : 128
To avoid an unintended device Reset, the instruction sequences shown in Example 5-1 and Example 5-2
must be executed when changing the prescaler assignment between Timer0 and the WDT. This sequence
must be followed even if the WDT is disabled.
DS21993A-page 44
© 2006 Microchip Technology Inc.
PIC16CR7X
5.3
Prescaler
value. The final 1:1 value is then set in lines 10 and 11
(highlighted). (Line numbers are included in the
example for illustrative purposes only, and are not part
of the actual code.)
There is only one prescaler available on the microcontroller; it is shared exclusively between the Timer0 module and the Watchdog Timer. The usage of the prescaler
is also mutually exclusive: that is, a prescaler assignment for the Timer0 module means that there is no prescaler for the Watchdog Timer, and vice versa. This
prescaler is not readable or writable (see Figure 5-1).
When assigned to the Timer0 module, all instructions
writing to the TMR0 register (e.g. CLRF 1, MOVWF 1,
BSF 1,x....etc.) will clear the prescaler. When assigned
to WDT, a CLRWDT instruction will clear the prescaler
along with the Watchdog Timer.
The PSA and PS2:PS0 bits (OPTION_REG<3:0>)
determine the prescaler assignment and prescale ratio.
Examples of code for assigning the prescaler assignment are shown in Example 5-1 and Example 5-2.
Note that when the prescaler is being assigned to the
WDT with ratios other than 1:1, lines 2 and 3 (highlighted) are optional. If a prescale ratio of 1:1 is used,
however, these lines must be used to set a temporary
EXAMPLE 5-1:
1)
2)
3)
4)
5)
6)
7)
8)
9)
10)
11)
12)
BSF
MOVLW
MOVWF
BCF
CLRF
BSF
MOVLW
MOVWF
CLRWDT
MOVLW
MOVWF
BCF
Address
01h,101h
Legend:
Bank1
Select clock source and prescale value of
other than 1:1
Bank0
Clear TMR0 and prescaler
Bank1
Select WDT, do not change prescale value
; Clears WDT and prescaler
; Select new prescale value and WDT
; Bank0
CHANGING THE PRESCALER ASSIGNMENT FROM WDT TO TIMER0
;
;
;
;
;
Clear WDT and prescaler
Bank1
Select TMR0, new prescale
value and clock source
Bank0
REGISTERS ASSOCIATED WITH TIMER0
Name
TMR0
0Bh,8Bh,
INTCON
10Bh,18Bh
81h,181h
;
;
;
;
;
;
;
b’xxxx1xxx’
OPTION_REG
STATUS, RP0
STATUS, RP0
b’xxxx0xxx’
OPTION_REG
STATUS, RP0
TABLE 5-1:
Writing to TMR0 when the prescaler is
assigned to Timer0 will clear the prescaler
count, but will not change the prescaler
assignment.
CHANGING THE PRESCALER ASSIGNMENT FROM TIMER0 TO WDT
STATUS, RP0
b’xx0x0xxx’
OPTION_REG
STATUS, RP0
TMR0
STATUS, RP1
b’xxxx1xxx’
OPTION_REG
EXAMPLE 5-2:
CLRWDT
BSF
MOVLW
MOVWF
BCF
Note:
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Timer0 Module Register
GIE
PEIE
OPTION_REG RBPU INTEDG
Value on:
POR,
BOR
Value on
all other
Resets
xxxx xxxx
uuuu uuuu
TMR0IE
INTE
RBIE
TMR0IF
INTF
RBIF
0000 000x
0000 000u
T0CS
T0SE
PSA
PS2
PS1
PS0
1111 1111
1111 1111
x = unknown, u = unchanged, - = unimplemented locations read as ‘0’. Shaded cells are not used by Timer0.
© 2006 Microchip Technology Inc.
DS21993A-page 45
PIC16CR7X
NOTES:
DS21993A-page 46
© 2006 Microchip Technology Inc.
PIC16CR7X
6.0
TIMER1 MODULE
The Timer1 module is a 16-bit timer/counter consisting
of two 8-bit registers (TMR1H and TMR1L), which are
readable and writable. The TMR1 Register pair
(TMR1H:TMR1L) increments from 0000h to FFFFh
and rolls over to 0000h. The TMR1 Interrupt, if enabled,
is generated on overflow, which is latched in interrupt
flag bit TMR1IF (PIR1<0>). This interrupt can be
enabled/disabled by setting/clearing TMR1 interrupt
enable bit TMR1IE (PIE1<0>).
Timer1 can operate in one of two modes:
• As a timer
• As a counter
The operating mode is determined by the clock select
bit, TMR1CS (T1CON<1>).
REGISTER 6-1:
In Timer mode, Timer1 increments every instruction
cycle. In Counter mode, it increments on every rising
edge of the external clock input.
Timer1 can be enabled/disabled by setting/clearing
control bit TMR1ON (T1CON<0>).
Timer1 also has an internal “Reset input”. This Reset
can be generated by either of the two CCP modules as
the special event trigger (see Sections 8.1 and 8.2).
Register 6-1 shows the Timer1 Control register.
When the Timer1 oscillator is enabled (T1OSCEN is
set), the RC1/T1OSI/CCP2 and RC0/T1OSO/T1CKI
pins become inputs. That is, the TRISC<1:0> value is
ignored and these pins read as ‘0’.
Additional information on timer modules is available in
the “PICmicro® Mid-Range MCU Family Reference
Manual” (DS33023).
T1CON: TIMER1 CONTROL (ADDRESS 10h)
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
T1CKPS1
T1CKPS0
T1OSCEN
T1SYNC
TMR1CS
TMR1ON
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7-6
Unimplemented: Read as ‘0’
bit 5-4
T1CKPS1:T1CKPS0: Timer1 Input Clock Prescale Select bits
11 = 1:8 Prescale value
10 = 1:4 Prescale value
01 = 1:2 Prescale value
00 = 1:1 Prescale value
bit 3
T1OSCEN: Timer1 Oscillator Enable Control bit
1 = Oscillator is enabled
0 = Oscillator is shut-off (the oscillator inverter is turned off to eliminate power drain)
bit 2
T1SYNC: Timer1 External Clock Input Synchronization Control bit
TMR1CS = 1:
1 = Do not synchronize external clock input
0 = Synchronize external clock input
TMR1CS = 0:
This bit is ignored. Timer1 uses the internal clock when TMR1CS = 0.
bit 1
TMR1CS: Timer1 Clock Source Select bit
1 = External clock from pin RC0/T1OSO/T1CKI (on the rising edge)
0 = Internal clock (FOSC/4)
bit 0
TMR1ON: Timer1 On bit
1 = Enables Timer1
0 = Stops Timer1
© 2006 Microchip Technology Inc.
DS21993A-page 47
PIC16CR7X
6.1
Timer1 Operation in Timer Mode
6.2
Timer mode is selected by clearing the TMR1CS
(T1CON<1>) bit. In this mode, the input clock to the
timer is FOSC/4. The synchronize control bit T1SYNC
(T1CON<2>) has no effect, since the internal clock is
always in sync.
FIGURE 6-1:
Timer1 Counter Operation
Timer1 may operate in Asynchronous or Synchronous
mode, depending on the setting of the TMR1CS bit.
When Timer1 is being incremented via an external
source, increments occur on a rising edge. After Timer1
is enabled in Counter mode, the module must first have
a falling edge before the counter begins to increment.
TIMER1 INCREMENTING EDGE
T1CKI
(Default high)
T1CKI
(Default low)
Note: Arrows indicate counter increments.
6.3
Timer1 Operation in Synchronized
Counter Mode
If T1SYNC is cleared, then the external clock input is
synchronized with internal phase clocks. The synchronization is done after the prescaler stage. The prescaler stage is an asynchronous ripple counter.
Counter mode is selected by setting bit TMR1CS. In
this mode, the timer increments on every rising edge of
clock input on pin RC1/T1OSI/CCP2, when bit
T1OSCEN is set, or on pin RC0/T1OSO/T1CKI, when
bit T1OSCEN is cleared.
FIGURE 6-2:
In this configuration, during Sleep mode, Timer1 will not
increment even if the external clock is present, since
the synchronization circuit is shut-off. The prescaler,
however, will continue to increment.
TIMER1 BLOCK DIAGRAM
Set Flag bit
TMR1IF on
Overflow
TMR1H
Synchronized
Clock Input
0
TMR1
TMR1L
1
TMR1ON
On/Off
T1OSC
RC0/T1OSO/T1CKI
RC1/T1OSI/CCP2
(2)
T1SYNC
(2)
1
T1OSCEN FOSC/4
Enable
Internal
Oscillator(1) Clock
Synchronize
Prescaler
1, 2, 4, 8
det
0
2
T1CKPS1:T1CKPS0
TMR1CS
Q Clock
Note 1: When the T1OSCEN bit is cleared, the inverter is turned off. This eliminates power drain.
2: For the PIC16CR73/76, the Schmitt Trigger is not implemented in External Clock mode.
DS21993A-page 48
© 2006 Microchip Technology Inc.
PIC16CR7X
6.4
Timer1 Operation in
Asynchronous Counter Mode
If control bit T1SYNC (T1CON<2>) is set, the external
clock input is not synchronized. The timer continues to
increment asynchronous to the internal phase clocks.
The timer will continue to run during Sleep and can
generate an interrupt on overflow, which will wake-up
the processor. However, special precautions in software are needed to read/write the timer (Section 6.4.1
“Reading and writing Timer1 in asynchronous
counter mode”).
In Asynchronous Counter mode, Timer1 cannot be
used as a time base for capture or compare operations.
6.4.1
READING AND WRITING TIMER1 IN
ASYNCHRONOUS COUNTER
MODE
Reading TMR1H or TMR1L, while the timer is running
from an external asynchronous clock, will ensure a
valid read (taken care of in hardware). However, the
user should keep in mind that reading the 16-bit timer
in two 8-bit values itself, poses certain problems, since
the timer may overflow between the reads.
For writes, it is recommended that the user simply stop
the timer and write the desired values. A write contention may occur by writing to the timer registers, while
the register is incrementing. This may produce an
unpredictable value in the timer register.
Reading the 16-bit value requires some care. The
example code provided in Example 6-1 and
Example 6-2 demonstrates how to write to and read
Timer1 while it is running in Asynchronous mode.
EXAMPLE 6-1:
WRITING A 16-BIT FREE-RUNNING TIMER
; All interrupts are disabled
CLRF
TMR1L
; Clear Low byte, Ensures no rollover into TMR1H
MOVLW
HI_BYTE
; Value to load into TMR1H
MOVWF
TMR1H, F
; Write High byte
MOVLW
LO_BYTE
; Value to load into TMR1L
MOVWF
TMR1H, F
; Write Low byte
; Re-enable the Interrupt (if required)
CONTINUE
; Continue with your code
EXAMPLE 6-2:
READING A 16-BIT FREE-RUNNING TIMER
; All interrupts are disabled
MOVF
TMR1H, W
; Read high byte
MOVWF
TMPH
MOVF
TMR1L, W
; Read low byte
MOVWF
TMPL
MOVF
TMR1H, W
; Read high byte
SUBWF
TMPH, W
; Sub 1st read with 2nd read
BTFSC
STATUS,Z
; Is result = 0
GOTO
CONTINUE
; Good 16-bit read
; TMR1L may have rolled over between the read of the high and low bytes.
; Reading the high and low bytes now will read a good value.
MOVF
TMR1H, W
; Read high byte
MOVWF
TMPH
MOVF
TMR1L, W
; Read low byte
MOVWF
TMPL
; Re-enable the Interrupt (if required)
CONTINUE
; Continue with your code
© 2006 Microchip Technology Inc.
DS21993A-page 49
PIC16CR7X
6.5
TABLE 6-1:
Timer1 Oscillator
A crystal oscillator circuit is built-in between pins T1OSI
(input) and T1OSO (amplifier output). It is enabled by
setting control bit T1OSCEN (T1CON<3>). The oscillator is a low-power oscillator rated up to 200 kHz. It will
continue to run during Sleep. It is primarily intended for
use with a 32 kHz crystal. Table 6-1 shows the capacitor selection for the Timer1 oscillator.
Capacitors Used:
Osc Type
32 kHz
47 pF
47 pF
100 kHz
33 pF
33 pF
200 kHz
15 pF
15 pF
Capacitor values are for design guidance only.
These capacitors were tested with the crystals listed
below for basic start-up and operation. These values
were not optimized.
Resetting Timer1 using a CCP
Trigger Output
Different capacitor values may be required to produce
acceptable oscillator operation. The user should test
the performance of the oscillator over the expected
VDD and temperature range for the application.
See the notes (below) table for additional information.
Commonly Used Crystals:
The special event triggers from the CCP1
and CCP2 modules will not set interrupt
flag bit TMR1IF (PIR1<0>).
32.768 kHz
Epson C-001R32.768K-A
100 kHz
Epson C-2 100.00 KC-P
200 kHz
STD XTL 200.000 kHz
Note 1: Higher capacitance increases the stability
of the oscillator, but also increases the
start-up time.
2: Since each resonator/crystal has its own
characteristics, the user should consult
the resonator/crystal manufacturer for
appropriate values of external components.
Timer1 must be configured for either Timer or Synchronized Counter mode, to take advantage of this feature.
If Timer1 is running in Asynchronous Counter mode,
this Reset operation may not work.
In the event that a write to Timer1 coincides with a special event trigger from CCP1 or CCP2, the write will
take precedence.
In this mode of operation, the CCPRxH:CCPRxL register pair effectively becomes the period register for
Timer1.
6.7
T1CON register is reset to 00h on a Power-on Reset or
a Brown-out Reset, which shuts off the timer and
leaves a 1:1 prescale. In all other Resets, the register
is unaffected.
Resetting of Timer1 Register Pair
(TMR1H, TMR1L)
6.8
TMR1H and TMR1L registers are not reset to 00h on a
POR, or any other Reset, except by the CCP1 and
CCP2 special event triggers.
TABLE 6-2:
OSC2
LP
If the CCP1 or CCP2 module is configured in Compare
mode to generate a “special event trigger”
(CCP1M3:CCP1M0 = 1011), this signal will reset
Timer1.
Note:
Frequency
OSC1
The Timer1 oscillator is identical to the LP oscillator.
The user must provide a software time delay to ensure
proper oscillator start-up.
6.6
CAPACITOR SELECTION FOR
THE TIMER1 OSCILLATOR
Timer1 Prescaler
The prescaler counter is cleared on writes to the
TMR1H or TMR1L registers.
REGISTERS ASSOCIATED WITH TIMER1 AS A TIMER/COUNTER
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on:
POR,
BOR
Value on
all other
Resets
GIE
PEIE
TMR0IE
INTE
RBIE
TMR0IF
INTF
RBIF
0000 000x
0000 000u
PIR1
PSPIF(1)
ADIF
RCIF
TXIF
SSPIF
CCP1IF
TMR2IF
TMR1IF
0000 0000
0000 0000
8Ch
PIE1
PSPIE(1)
ADIE
RCIE
TXIE
SSPIE
CCP1IE
TMR2IE
TMR1IE
0000 0000
0000 0000
0Eh
TMR1L
Holding Register for the Least Significant Byte of the 16-bit TMR1 Register
xxxx xxxx
uuuu uuuu
0Fh
TMR1H
Holding Register for the Most Significant Byte of the 16-bit TMR1 Register
10h
T1CON
Address
Name
0Bh,8Bh,
INTCON
10Bh,18Bh
0Ch
Legend:
Note 1:
—
—
T1CKPS1
T1CKPS0
T1OSCEN
T1SYNC
TMR1CS
TMR1ON
xxxx xxxx
uuuu uuuu
--00 0000
--uu uuuu
x = unknown, u = unchanged, - = unimplemented, read as ‘0’. Shaded cells are not used by the Timer1 module.
Bits PSPIE and PSPIF are reserved on the PIC16CR73/76; always maintain these bits clear.
DS21993A-page 50
© 2006 Microchip Technology Inc.
PIC16CR7X
7.0
TIMER2 MODULE
Timer2 is an 8-bit timer with a prescaler and a
postscaler. It can be used as the PWM time base for the
PWM mode of the CCP module(s). The TMR2 register
is readable and writable, and is cleared on any device
Reset.
The input clock (FOSC/4) has a prescale option of 1:1,
1:4
or
1:16,
selected
by
control
bits
T2CKPS1:T2CKPS0 (T2CON<1:0>).
The Timer2 module has an 8-bit period register, PR2.
Timer2 increments from 00h until it matches PR2 and
then resets to 00h on the next increment cycle. PR2 is
a readable and writable register. The PR2 register is
initialized to FFh upon Reset.
The match output of TMR2 goes through a 4-bit
postscaler (which gives a 1:1 to 1:16 scaling inclusive)
to generate a TMR2 interrupt (latched in flag bit
TMR2IF, (PIR1<1>)).
7.1
Timer2 Prescaler and Postscaler
The prescaler and postscaler counters are cleared
when any of the following occurs:
• a write to the TMR2 register
• a write to the T2CON register
• any device Reset (POR, MCLR Reset, WDT
Reset or BOR)
TMR2 is not cleared when T2CON is written.
7.2
Output of TMR2
The output of TMR2 (before the postscaler) is fed to the
SSP module, which optionally uses it to generate shift
clock.
FIGURE 7-1:
Sets Flag
bit TMR2IF
TIMER2 BLOCK DIAGRAM
TMR2
Output(1)
Timer2 can be shut-off by clearing control bit TMR2ON
(T2CON<2>) to minimize power consumption.
Reset
Register 7-1 shows the Timer2 control register.
Additional information on timer modules is available in
the “PICmicro® Mid-Range MCU Family Reference
Manual” (DS33023).
Postscaler
1:1 to 1:16
4
EQ
TMR2 Reg
Comparator
PR2 Reg
Prescaler
1:1, 1:4, 1:16
FOSC/4
2
T2CKPS1:
T2CKPS0
T2OUTPS3:
T2OUTPS0
Note
© 2006 Microchip Technology Inc.
1:
TMR2 register output can be software selected by
the SSP module as a baud clock.
DS21993A-page 51
PIC16CR7X
REGISTER 7-1:
T2CON: TIMER2 CONTROL (ADDRESS 12h)
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
TOUTPS3
TOUTPS2
TOUTPS1
TOUTPS0
TMR2ON
T2CKPS1
T2CKPS0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7
Unimplemented: Read as ‘0’
bit 6-3
TOUTPS3:TOUTPS0: Timer2 Output Postscale Select bits
0000 = 1:1 Postscale
0001 = 1:2 Postscale
0010 = 1:3 Postscale
•
•
•
1111 = 1:16 Postscale
bit 2
TMR2ON: Timer2 On bit
1 = Timer2 is on
0 = Timer2 is off
bit 1-0
T2CKPS1:T2CKPS0: Timer2 Clock Prescale Select bits
00 = Prescaler is 1
01 = Prescaler is 4
1x = Prescaler is 16
TABLE 7-1:
Address
Name
0Bh,8Bh,
INTCON
10Bh, 18Bh
x = Bit is unknown
REGISTERS ASSOCIATED WITH TIMER2 AS A TIMER/COUNTER
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on:
POR,
BOR
Value on
all other
Resets
GIE
PEIE
TMR0IE
INTE
RBIE
TMR0IF
INTF
RBIF
0000 000x
0000 000u
0Ch
PIR1
PSPIF(1)
ADIF
RCIF
TXIF
SSPIF
CCP1IF
TMR2IF
TMR1IF
0000 0000
0000 0000
8Ch
PIE1
PSPIE(1)
ADIE
RCIE
TXIE
SSPIE
CCP1IE
TMR2IE
TMR1IE
0000 0000
0000 0000
0000 0000
0000 0000
-000 0000
-000 0000
1111 1111
1111 1111
11h
TMR2
12h
T2CON
92h
Legend:
Note 1:
PR2
Timer2 Module Register
—
TOUTPS3
Timer2 Period Register
TOUTPS2
TOUTPS1
TOUTPS0
TMR2ON
T2CKPS1
T2CKPS0
x = unknown, u = unchanged, - = unimplemented, read as ‘0’. Shaded cells are not used by the Timer2 module.
Bits PSPIE and PSPIF are reserved on the PIC16CR73/76; always maintain these bits clear.
DS21993A-page 52
© 2006 Microchip Technology Inc.
PIC16CR7X
8.0
CAPTURE/COMPARE/PWM
MODULES
Each Capture/Compare/PWM (CCP) module contains
a 16-bit register which can operate as a:
• 16-bit Capture register
• 16-bit Compare register
• PWM Master/Slave Duty Cycle register
Both the CCP1 and CCP2 modules are identical in
operation, with the exception being the operation of the
special event trigger. Table 8-1 and Table 8-2 show the
resources and interactions of the CCP module(s). In
the following sections, the operation of a CCP module
is described with respect to CCP1. CCP2 operates the
same as CCP1, except where noted.
8.1
8.2
Capture/Compare/PWM Register1 (CCPR1) is comprised of two 8-bit registers: CCPR1L (low byte) and
CCPR1H (high byte). The CCP2CON register controls
the operation of CCP2. The special event trigger is
generated by a compare match; it will clear both
TMR1H and TMR1L registers, and start an A/D conversion (if the A/D module is enabled).
Additional information on CCP modules is available in
the “PICmicro® Mid-Range MCU Family Reference
Manual” (DS33023) and in Application Note AN594,
“Using the CCP Modules” (DS00594).
TABLE 8-1:
CCP1 Module
Capture/Compare/PWM Register1 (CCPR1) is comprised of two 8-bit registers: CCPR1L (low byte) and
CCPR1H (high byte). The CCP1CON register controls
the operation of CCP1. The special event trigger is
generated by a compare match and will clear both
TMR1H and TMR1L registers.
TABLE 8-2:
CCP2 Module
CCP MODE – TIMER
RESOURCES REQUIRED
CCP Mode
Timer Resource
Capture
Compare
PWM
Timer1
Timer1
Timer2
INTERACTION OF TWO CCP MODULES
CCPx Mode CCPy Mode
Interaction
Capture
Capture
Same TMR1 time base.
Capture
Compare
Same TMR1 time base.
Compare
Compare
Same TMR1 time base.
PWM
PWM
The PWMs will have the same frequency and update rate (TMR2 interrupt).
The rising edges are aligned.
PWM
Capture
None.
PWM
Compare
None.
© 2006 Microchip Technology Inc.
DS21993A-page 53
PIC16CR7X
REGISTER 8-1:
CCP1CON/CCP2CON: (ADDRESS 17h/1Dh)
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
CCPxX
CCPxY
CCPxM3
CCPxM2
CCPxM1
CCPxM0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7-6
Unimplemented: Read as ‘0’
bit 5-4
CCPxX:CCPxY: PWM Least Significant bits
Capture mode:
Unused
Compare mode:
Unused
PWM mode:
These bits are the two LSbs of the PWM duty cycle. The eight MSbs are found in CCPRxL.
bit 3-0
CCPxM3:CCPxM0: CCPx Mode Select bits
0000 = Capture/Compare/PWM disabled (resets CCPx module)
0100 = Capture mode, every falling edge
0101 = Capture mode, every rising edge
0110 = Capture mode, every 4th rising edge
0111 = Capture mode, every 16th rising edge
1000 = Compare mode, set output on match (CCPxIF bit is set)
1001 = Compare mode, clear output on match (CCPxIF bit is set)
1010 = Compare mode, generate software interrupt on match (CCPxIF bit is set, CCPx pin is
unaffected)
1011 = Compare mode, trigger special event (CCPxIF bit is set, CCPx pin is unaffected);
CCP1 clears Timer1; CCP2 clears Timer1 and starts an A/D conversion (if A/D module
is enabled)
11xx = PWM mode
DS21993A-page 54
© 2006 Microchip Technology Inc.
PIC16CR7X
8.3
8.3.4
Capture Mode
In Capture mode, CCPR1H:CCPR1L captures the
16-bit value of the TMR1 register when an event occurs
on pin RC2/CCP1. An event is defined as one of the
following and is configured by CCPxCON<3:0>:
•
•
•
•
Every falling edge
Every rising edge
Every 4th rising edge
Every 16th rising edge
An event is selected by control bits CCP1M3:CCP1M0
(CCP1CON<3:0>). When a capture is made, the interrupt request flag bit CCP1IF (PIR1<2>) is set. The
interrupt flag must be cleared in software. If another
capture occurs before the value in register CCPR1 is
read, the old captured value is overwritten by the new
captured value.
8.3.1
There are four prescaler settings, specified by bits
CCP1M3:CCP1M0. Whenever the CCP module is
turned off, or the CCP module is not in Capture mode,
the prescaler counter is cleared. Any Reset will clear
the prescaler counter.
Switching from one capture prescaler to another may
generate an interrupt. Also, the prescaler counter will
not be cleared, therefore, the first capture may be from
a non-zero prescaler. Example 8-1 shows the recommended method for switching between capture
prescalers. This example also clears the prescaler
counter and will not generate the “false” interrupt.
EXAMPLE 8-1:
CLRF
MOVLW
If the RC2/CCP1 pin is configured as an
output, a write to the port can cause a
capture condition.
FIGURE 8-1:
CAPTURE MODE
OPERATION BLOCK
DIAGRAM
Prescaler
÷ 1, 4, 16
Set Flag bit CCP1IF
(PIR1<2>)
RC2/CCP1
pin
CCPR1H
and
Edge Detect
CCPR1L
Capture
Enable
TMR1H
TMR1L
MOVWF
8.4
CHANGING BETWEEN
CAPTURE PRESCALERS
CCP1CON
;Turn CCP module off
NEW_CAPT_PS ;Load the W reg with
;the new prescaler
;move value and CCP ON
CCP1CON
;Load CCP1CON with this
;value
CCP PIN CONFIGURATION
In Capture mode, the RC2/CCP1 pin should be
configured as an input by setting the TRISC<2> bit.
Note:
CCP PRESCALER
Compare Mode
In Compare mode, the 16-bit CCPR1 register value is
constantly compared against the TMR1 register pair
value. When a match occurs, the RC2/CCP1 pin is:
• Driven high
• Driven low
• Remains unchanged
The action on the pin is based on the value of control
bits CCP1M3:CCP1M0 (CCP1CON<3:0>). At the
same time, interrupt flag bit CCP1IF is set.
FIGURE 8-2:
COMPARE MODE
OPERATION BLOCK
DIAGRAM
CCP1CON<3:0>
Q’s
8.3.2
CCP1CON<3:0>
Mode Select
TIMER1 MODE SELECTION
Timer1 must be running in Timer mode or Synchronized Counter mode for the CCP module to use the
capture feature. In Asynchronous Counter mode, the
capture operation may not work.
8.3.3
SOFTWARE INTERRUPT
When the Capture mode is changed, a false capture
interrupt may be generated. The user should keep bit
CCP1IE (PIE1<2>) clear to avoid false interrupts and
should clear the flag bit CCP1IF following any such
change in operating mode.
Set Flag bit CCP1IF
(PIR1<2>)
CCPR1H CCPR1L
Q
S
RC2/CCP1
Pin
R
Output
Logic
Match
TRISC<2>
Output Enable
Comparator
TMR1H
TMR1L
Special Event Trigger
Special Event Trigger will:
• clear TMR1H and TMR1L registers
• NOT set interrupt flag bit TMR1F (PIR1<0>)
• (for CCP2 only) set the GO/DONE bit (ADCON0<2>)
© 2006 Microchip Technology Inc.
DS21993A-page 55
PIC16CR7X
8.4.1
CCP PIN CONFIGURATION
8.4.4
The user must configure the RC2/CCP1 pin as an output by clearing the TRISC<2> bit.
Note:
8.4.2
In this mode, an internal hardware trigger is generated,
which may be used to initiate an action.
Clearing the CCP1CON register will force
the RC2/CCP1 compare output latch to
the default low level. This is not the
PORTC I/O data latch.
The special event trigger output of CCP1 resets the
TMR1 register pair. This allows the CCPR1 register to
effectively be a 16-bit programmable period register for
Timer1.
TIMER1 MODE SELECTION
The special event trigger output of CCP2 resets the
TMR1 register pair and starts an A/D conversion (if the
A/D module is enabled).
Timer1 must be running in Timer mode or Synchronized Counter mode if the CCP module is using the
compare feature. In Asynchronous Counter mode, the
compare operation may not work.
8.4.3
SPECIAL EVENT TRIGGER
Note:
The special event trigger from the CCP1
and CCP2 modules will not set interrupt
flag bit TMR1IF (PIR1<0>).
SOFTWARE INTERRUPT MODE
When Generate Software Interrupt mode is chosen, the
CCP1 pin is not affected. The CCP1IF or CCP2IF bit is
set, causing a CCP interrupt (if enabled).
TABLE 8-3:
Address
REGISTERS ASSOCIATED WITH CAPTURE, COMPARE AND TIMER1
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0Bh,8Bh, INTCON
10Bh,18Bh
GIE
PEIE
TMR0IE
INTE
RBIE
TMR0IF
INTF
RBIF
Value on:
POR,
BOR
Value on
all other
Resets
0000 000x 0000 000u
0Ch
PIR1
PSPIF(1)
ADIF
RCIF
TXIF
SSPIF
CCP1IF
TMR2IF
TMR1IF 0000 0000 0000 0000
0Dh
PIR2
—
—
—
—
—
—
—
CCP2IF ---- ---0 ---- ---0
ADIE
RCIE
TXIE
SSPIE
CCP1IE
—
—
—
—
—
(1)
PSPIE
TMR2IE TMR1IE 0000 0000 0000 0000
8Ch
PIE1
8Dh
PIE2
87h
TRISC
PORTC Data Direction Register
1111 1111 1111 1111
0Eh
TMR1L
Holding Register for the Least Significant Byte of the 16-bit TMR1 Register
xxxx xxxx uuuu uuuu
0Fh
TMR1H
Holding Register for the Most Significant Byte of the 16-bit TMR1 Register
xxxx xxxx uuuu uuuu
10h
T1CON
15h
CCPR1L
Capture/Compare/PWM Register 1 (LSB)
xxxx xxxx uuuu uuuu
16h
CCPR1H
Capture/Compare/PWM Register 1 (MSB)
xxxx xxxx uuuu uuuu
17h
CCP1CON
1Bh
CCPR2L
Capture/Compare/PWM Register 2 (LSB)
xxxx xxxx uuuu uuuu
1Ch
CCPR2H
Capture/Compare/PWM Register 2 (MSB)
xxxx xxxx uuuu uuuu
1Dh
CCP2CON
Legend:
Note 1:
x = unknown, u = unchanged, - = unimplemented, read as ‘0’. Shaded cells are not used by Capture and Timer1.
The PSP is not implemented on the PIC16CR73/76; always maintain these bits clear.
DS21993A-page 56
—
—
—
—
—
—
—
—
CCP2IE ---- ---0 ---- ---0
T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON --00 0000 --uu uuuu
CCP1X
CCP2X
CCP1Y
CCP2Y
CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 --00 0000
CCP2M3 CCP2M2 CCP2M1 CCP2M0 --00 0000 --00 0000
© 2006 Microchip Technology Inc.
PIC16CR7X
8.5
8.5.1
PWM Mode (PWM)
In Pulse Width Modulation mode, the CCPx pin
produces up to a 10-bit resolution PWM output. Since
the CCP1 pin is multiplexed with the PORTC data latch,
the TRISC<2> bit must be cleared to make the CCP1
pin an output.
Note:
Clearing the CCP1CON register will force
the CCP1 PWM output latch to the default
low level. This is not the PORTC I/O data
latch.
Figure 8-3 shows a simplified block diagram of the
CCP module in PWM mode.
For a step-by-step procedure on how to set up the CCP
module for PWM operation, see Section 8.5.3 “SetUp
for PWM Operation”.
FIGURE 8-3:
SIMPLIFIED PWM BLOCK
DIAGRAM
Duty Cycle Registers
PWM PERIOD
The PWM period is specified by writing to the PR2
register. The PWM period can be calculated using the
following formula:
PWM period = [(PR2) + 1] • 4 • TOSC •
(TMR2 prescale value)
PWM frequency is defined as 1 / [PWM period].
When TMR2 is equal to PR2, the following three events
occur on the next increment cycle:
• TMR2 is cleared
• The CCP1 pin is set (exception: if PWM duty
cycle = 0%, the CCP1 pin will not be set)
• The PWM duty cycle is latched from CCPR1L into
CCPR1H
Note:
CCP1CON<5:4>
CCPR1L
8.5.2
CCPR1H (Slave)
R
Comparator
Q
RC2/CCP1
(1)
TMR2
S
(Note 1)
TRISC<2>
Comparator
Clear Timer,
CCP1 pin and
latch D.C.
PR2
Note 1: The 8-bit timer is concatenated with the 2-bit internal Q clock or the 2 bits of the prescaler to create the
10-bit time base.
A PWM output (Figure 8-4) has a time base (period)
and a time that the output stays high (duty cycle). The
frequency of the PWM is the inverse of the period
(1/period).
FIGURE 8-4:
PWM OUTPUT
TMR2
Reset
TMR2
Reset
Period
The Timer2 postscaler (see Section 8.3
“Capture Mode”) is not used in the determination of the PWM frequency. The
postscaler could be used to have a servo
update rate at a different frequency than
the PWM output.
PWM DUTY CYCLE
The PWM duty cycle is specified by writing to the
CCPR1L register and to the CCP1CON<5:4> bits. Up
to 10-bit resolution is available. The CCPR1L contains
the eight MSbs and the CCP1CON<5:4> contains the
two LSbs. This 10-bit value is represented by
CCPR1L:CCP1CON<5:4>. The following equation is
used to calculate the PWM duty cycle in time:
PWM duty cycle = (CCPR1L:CCP1CON<5:4>) •
TOSC • (TMR2 prescale value)
CCPR1L and CCP1CON<5:4> can be written to at any
time, but the duty cycle value is not latched into
CCPR1H until after a match between PR2 and TMR2
occurs (i.e., the period is complete). In PWM mode,
CCPR1H is a read-only register.
The CCPR1H register and a 2-bit internal latch are
used to double buffer the PWM duty cycle. This double
buffering is essential for glitchless PWM operation.
When the CCPR1H and 2-bit latch match TMR2,
concatenated with an internal 2-bit Q clock or 2 bits of
the TMR2 prescaler, the CCP1 pin is cleared.
The maximum PWM resolution (bits) for a given PWM
frequency is given by the formula:
FOSC
log FPWM
Resolution =
bits
log(2)
(
Duty Cycle
TMR2 = PR2
TMR2 = Duty Cycle
TMR2 = PR2
© 2006 Microchip Technology Inc.
Note:
)
If the PWM duty cycle value is longer than
the PWM period, the CCP1 pin will not be
cleared.
DS21993A-page 57
PIC16CR7X
8.5.3
SETUP FOR PWM OPERATION
3.
The following steps should be taken when configuring
the CCP module for PWM operation:
1.
2.
4.
Set the PWM period by writing to the PR2 register.
Set the PWM duty cycle by writing to the
CCPR1L register and CCP1CON<5:4> bits.
TABLE 8-4:
EXAMPLE PWM FREQUENCIES AND RESOLUTIONS (FOSC = 20 MHz)
PWM Frequency
1.22 kHz
Timer Prescale (1, 4, 16)
PR2 Value
Address
4.88 kHz
19.53 kHz
78.12 kHz
156.3 kHz
208.3 kHz
16
4
1
1
1
1
0xFF
0xFF
0xFF
0x3F
0x1F
0x17
10
10
10
8
7
5.5
Maximum Resolution (bits)
TABLE 8-5:
5.
Make the CCP1 pin an output by clearing the
TRISC<2> bit.
Set the TMR2 prescale value and enable Timer2
by writing to T2CON.
Configure the CCP1 module for PWM operation.
REGISTERS ASSOCIATED WITH PWM AND TIMER2
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0Bh,8Bh, INTCON
10Bh,18Bh
GIE
PEIE
TMR0IE
INTE
RBIE
TMR0IF
INTF
RBIF
Value on:
POR,
BOR
Value on
all other
Resets
0000 000x 0000 000u
0Ch
PIR1
PSPIF(1)
ADIF
RCIF
TXIF
SSPIF
CCP1IF
TMR2IF
TMR1IF 0000 0000 0000 0000
0Dh
PIR2
—
—
—
—
—
—
—
CCP2IF ---- ---0 ---- ---0
ADIE
RCIE
TXIE
SSPIE
—
—
—
—
(1)
8Ch
PIE1
8Dh
PIE2
87h
TRISC
PORTC Data Direction Register
1111 1111 1111 1111
11h
TMR2
Timer2 Module Register
0000 0000 0000 0000
92h
PR2
Timer2 Module Period Register
1111 1111 1111 1111
12h
T2CON
PSPIE
—
—
CCP1IE TMR2IE
—
—
TMR1IE 0000 0000 0000 0000
CCP2IE ---- ---0 ---- ---0
TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000
15h
CCPR1L
Capture/Compare/PWM Register 1 (LSB)
xxxx xxxx uuuu uuuu
16h
CCPR1H
Capture/Compare/PWM Register 1 (MSB)
xxxx xxxx uuuu uuuu
17h
CCP1CON
CCP1Y
CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 --00 0000
1Bh
CCPR2L
Capture/Compare/PWM Register 2 (LSB)
xxxx xxxx uuuu uuuu
1Ch
CCPR2H
Capture/Compare/PWM Register 2 (MSB)
1Dh
CCP2CON
Legend:
Note 1:
x = unknown, u = unchanged, - = unimplemented, read as ‘0’. Shaded cells are not used by PWM and Timer2.
Bits PSPIE and PSPIF are reserved on the PIC16CR73/76; always maintain these bits clear.
DS21993A-page 58
—
—
—
—
CCP1X
CCP2X
CCP2Y
xxxx xxxx uuuu uuuu
CCP2M3 CCP2M2 CCP2M1 CCP2M0 --00 0000 --00 0000
© 2006 Microchip Technology Inc.
PIC16CR7X
9.0
9.1
SYNCHRONOUS SERIAL PORT
(SSP) MODULE
SSP Module Overview
The Synchronous Serial Port (SSP) module is a serial
interface useful for communicating with other peripheral or microcontroller devices. These peripheral
devices may be Serial EEPROMs, shift registers,
display drivers, A/D converters, etc. The SSP module
can operate in one of two modes:
• Serial Peripheral Interface (SPI)
• Inter-Integrated Circuit (I2C)
An overview of I2C operations and additional information on the SSP module can be found in the “PICmicro®
Mid-Range MCU Family Reference Manual”
(DS33023).
Refer to Application Note AN578, “Use of the SSP
Module in the I 2C™ Multi-Master Environment”
(DS00578).
9.2
SPI Mode
This section contains register definitions and operational characteristics of the SPI module. Additional
information on the SPI module can be found in the
“PICmicro® Mid-Range MCU Family Reference
Manual” (DS33023).
SPI mode allows 8 bits of data to be synchronously
transmitted and received simultaneously. To
accomplish communication, typically three pins are
used:
• Serial Data Out (SDO) RC5/SDO
• Serial Data In (SDI) RC4/SDI/SDA
• Serial Clock (SCK) RC3/SCK/SCL
Additionally, a fourth pin may be used when in a Slave
mode of operation:
• Slave Select (SS) RA5/SS/AN4
When initializing the SPI, several options need to be
specified. This is done by programming the appropriate
control bits in the SSPCON register (SSPCON<5:0>)
and SSPSTAT<7:6>. These control bits allow the
following to be specified:
•
•
•
•
Master mode (SCK is the clock output)
Slave mode (SCK is the clock input)
Clock Polarity (Idle state of SCK)
Clock edge (output data on rising/falling edge of
SCK)
• Clock Rate (Master mode only)
• Slave Select mode (Slave mode only)
© 2006 Microchip Technology Inc.
DS21993A-page 59
PIC16CR7X
REGISTER 9-1:
SSPSTAT: SYNC SERIAL PORT STATUS (ADDRESS 94h)
R/W-0
R/W-0
R-0
R-0
R-0
R-0
R-0
R-0
SMP
CKE
D/A
P
S
R/W
UA
BF
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
SMP: SPI Data Input Sample Phase bit
SPI Master mode:
1 = Input data sampled at end of data output time
0 = Input data sampled at middle of data output time (Microwire)
SPI Slave mode:
SMP must be cleared when SPI is used in Slave mode
I2 C mode:
This bit must be maintained clear
bit 6
CKE: SPI Clock Edge Select bit (Figure 9-2, Figure 9-3, and Figure 9-4)
SPI mode, CKP = 0:
1 = Data transmitted on rising edge of SCK (Microwire alternate)
0 = Data transmitted on falling edge of SCK
SPI mode, CKP = 1:
1 = Data transmitted on falling edge of SCK (Microwire default)
0 = Data transmitted on rising edge of SCK
I2 C mode:
This bit must be maintained clear
bit 5
D/A: Data/Address bit (I2C™ mode only)
1 = Indicates that the last byte received or transmitted was data
0 = Indicates that the last byte received or transmitted was address
bit 4
P: Stop bit (I2C™ mode only)
This bit is cleared when the SSP module is disabled, or when the Start bit is detected last.
SSPEN is cleared.
1 = Indicates that a Stop bit has been detected last (this bit is ‘0’ on Reset)
0 = Stop bit was not detected last
bit 3
S: Start bit (I2C™ mode only)
This bit is cleared when the SSP module is disabled, or when the Stop bit is detected last.
SSPEN is cleared.
1 = Indicates that a Start bit has been detected last (this bit is ‘0’ on Reset)
0 = Start bit was not detected last
bit 2
R/W: Read/Write bit Information (I2C™ mode only)
This bit holds the R/W bit information following the last address match. This bit is only valid from the address match
to the next Start bit, Stop bit, or ACK bit.
1 = Read
0 = Write
bit 1
UA: Update Address bit (10-bit I2C™ mode only)
1 = Indicates that the user needs to update the address in the SSPADD register
0 = Address does not need to be updated
bit 0
BF: Buffer Full Status bit
Receive (SPI and I2 C modes):
1 = Receive complete, SSPBUF is full
0 = Receive not complete, SSPBUF is empty
Transmit (I2 C mode only):
1 = Transmit in progress, SSPBUF is full
0 = Transmit complete, SSPBUF is empty
DS21993A-page 60
© 2006 Microchip Technology Inc.
PIC16CR7X
REGISTER 9-2:
SSPCON: SYNC SERIAL PORT CONTROL (ADDRESS 14h)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
WCOL
SSPOV
SSPEN
CKP
SSPM3
SSPM2
SSPM1
SSPM0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
WCOL: Write Collision Detect bit
1 = The SSPBUF register is written while it is still transmitting the previous word
(must be cleared in software)
0 = No collision
bit 6
SSPOV: Receive Overflow Indicator bit
In SPI mode:
1 = A new byte is received while the SSPBUF register is still holding the previous data. In case
of overflow, the data in SSPSR is lost. Overflow can only occur in Slave mode. The user
must read the SSPBUF, even if only transmitting data, to avoid setting overflow. In
Master mode, the overflow bit is not set since each new reception (and transmission) is
initiated by writing to the SSPBUF register.
0 = No overflow
In I2 C mode:
1 = A byte is received while the SSPBUF register is still holding the previous byte. SSPOV
is a “don’t care” in Transmit mode. SSPOV must be cleared in software in either mode.
0 = No overflow
bit 5
SSPEN: Synchronous Serial Port Enable bit
In SPI mode:
1 = Enables serial port and configures SCK, SDO and SDI as serial port pins
0 = Disables serial port and configures these pins as I/O port pins
In I2 C mode:
1 = Enables the serial port and configures the SDA and SCL pins as serial port pins
0 = Disables serial port and configures these pins as I/O port pins
In both modes, when enabled, these pins must be properly configured as input or output.
bit 4
CKP: Clock Polarity Select bit
In SPI mode:
1 = Idle state for clock is a high level (Microwire default)
0 = Idle state for clock is a low level (Microwire alternate)
In I2 C mode:
SCK release control
1 = Enable clock
0 = Holds clock low (clock stretch). (Used to ensure data setup time.)
bit 3-0
SSPM3:SSPM0: Synchronous Serial Port Mode Select bits
0000 = SPI Master mode, clock = FOSC/4
0001 = SPI Master mode, clock = FOSC/16
0010 = SPI Master mode, clock = FOSC/64
0011 = SPI Master mode, clock = TMR2 output/2
0100 = SPI Slave mode, clock = SCK pin. SS pin control enabled.
0101 = SPI Slave mode, clock = SCK pin. SS pin control disabled. SS can be used as I/O pin.
0110 = I2C™ Slave mode, 7-bit address
0111 = I2C™ Slave mode, 10-bit address
1011 = I2C™ Firmware Controlled Master mode (slave Idle)
1110 = I2C™ Slave mode, 7-bit address with Start and Stop bit interrupts enabled
1111 = I2C™ Slave mode, 10-bit address with Start and Stop bit interrupts enabled
© 2006 Microchip Technology Inc.
DS21993A-page 61
PIC16CR7X
FIGURE 9-1:
SSP BLOCK DIAGRAM
(SPI MODE)
Internal
Data Bus
Read
Write
SSPBUF Reg
SSPSR Reg
RC4/SDI/SDA
RC5/SDO
Shift
Clock
bit 0
Peripheral OE
SS Control
Enable
RA5/SS/AN4
Edge
Select
2: If the SPI is used in Slave mode with
CKE = ‘1’, then the SS pin control must
be enabled.
SSPM3:SSPM0
4
Edge
Select
DS21993A-page 62
• SDI must have TRISC<4> set
• SDO must have TRISC<5> cleared
• SCK (Master mode) must have TRISC<3>
cleared
• SCK (Slave mode) must have TRISC<3> set
• SS must have TRISA<5> set and ADCON must
be configured such that RA5 is a digital I/O
Note 1: When the SPI is in Slave mode with SS
pin control enabled (SSPCON<3:0> =
0100), the SPI module will reset if the SS
pin is set to VDD.
2
Clock Select
RC3/SCK/
SCL
To enable the serial port, SSP enable bit, SSPEN
(SSPCON<5>) must be set. To reset or reconfigure SPI
mode, clear bit SSPEN, re-initialize the SSPCON
register, and then set bit SSPEN. This configures the
SDI, SDO, SCK and SS pins as serial port pins. For the
pins to behave as the serial port function, they must
have their data direction bits (in the TRISC register)
appropriately programmed. That is:
TRISC<3>
TMR2 Output
2
Prescaler TCY
4, 16, 64
3: When the SPI is in Slave mode with SS
pin control enabled (SSPCON<3:0> =
‘0100’), the state of the SS pin can affect
the state read back from the TRISC<5>
bit. The Peripheral OE signal from the
SSP module into PORTC controls the
state that is read back from the
TRISC<5> bit (see Section 4.3 “PORTC
and the TRISC Register” for information
on PORTC). If Read-Modify-Write
instructions, such as BSF are performed
on the TRISC register while the SS pin is
high, this will cause the TRISC<5> bit to
be set, thus disabling the SDO output.
© 2006 Microchip Technology Inc.
PIC16CR7X
FIGURE 9-2:
SPI MODE TIMING, MASTER MODE
SCK (CKP = 0,
CKE = 0)
SCK (CKP = 0,
CKE = 1)
SCK (CKP = 1,
CKE = 0)
SCK (CKP = 1,
CKE = 1)
bit 7
SDO
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
SDI (SMP = 0)
bit 7
bit 0
SDI (SMP = 1)
bit 7
bit 0
SSPIF
FIGURE 9-3:
SPI MODE TIMING (SLAVE MODE WITH CKE = 0)
SS (optional)
SCK (CKP = 0)
SCK (CKP = 1)
bit 7
SDO
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
SDI (SMP = 0)
bit 7
bit 0
SSPIF
© 2006 Microchip Technology Inc.
DS21993A-page 63
PIC16CR7X
FIGURE 9-4:
SPI MODE TIMING (SLAVE MODE WITH CKE = 1)
SS
SCK (CKP = 0)
SCK (CKP = 1)
SDO
bit 7
bit 6
bit 5
bit 3
bit 4
bit 2
bit 1
bit 0
SDI (SMP = 0)
bit 7
bit 0
SSPIF
TABLE 9-1:
Address
REGISTERS ASSOCIATED WITH SPI OPERATION
Name
Bit 7
Bit 6
0Bh,8Bh.
INTCON
10Bh,18Bh
GIE
PEIE
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
TMR0IE INTE
RBIE
TMR0IF
INTF
RBIF
Value on:
POR,
BOR
Value on
all other
Resets
0000 000x 0000 000u
PIR1
PSPIF(1)
ADIF
RCIF
TXIF
SSPIF
CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
8Ch
PIE1
(1)
ADIE
RCIE
TXIE
SSPIE
CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
87h
TRISC
PORTC Data Direction Register
13h
SSPBUF
Synchronous Serial Port Receive Buffer/Transmit Register
14h
SSPCON WCOL
85h
TRISA
0Ch
94h
Legend:
Note 1:
SSPSTAT
PSPIE
SSPOV SSPEN
—
—
SMP
CKE
1111 1111 1111 1111
CKP
SSPM3 SSPM2
xxxx xxxx uuuu uuuu
SSPM1
SSPM0
PORTA Data Direction Register
D/A
P
S
R/W
0000 0000 0000 0000
--11 1111 --11 1111
UA
BF
0000 0000 0000 0000
x = unknown, u = unchanged, - = unimplemented, read as ‘0’. Shaded cells are not used by the SSP in SPI mode.
Bits PSPIE and PSPIF are reserved on the PIC16CR73/76; always maintain these bits clear.
DS21993A-page 64
© 2006 Microchip Technology Inc.
PIC16CR7X
9.3
SSP I2 C™ Operation
The SSP module in I2C mode fully implements all slave
functions except general call support, and provides
interrupts on Start and Stop bits in hardware to facilitate
firmware implementations of the master functions. The
SSP module implements the standard mode specifications as well as 7-bit and 10-bit addressing.
Two pins are used for data transfer. These are the RC3/
SCK/SCL pin, which is the clock (SCL), and the RC4/
SDI/SDA pin, which is the data (SDA). The user must
configure these pins as inputs or outputs through the
TRISC<4:3> bits.
The SSP module functions are enabled by setting SSP
enable bit SSPEN (SSPCON<5>).
FIGURE 9-5:
SSP BLOCK DIAGRAM
(I2C™ MODE)
Internal
Data Bus
Read
Write
SSPBUF Reg
RC3/SCK/SCL
LSb
Match Detect
Addr Match
SSPADD Reg
Start and
Stop bit Detect
Selection of any I 2C mode with the SSPEN bit set,
forces the SCL and SDA pins to be open drain, provided these pins are programmed to inputs by setting
the appropriate TRISC bits. Pull-up resistors must be
provided externally to the SCL and SDA pins for proper
operation of the I2C module.
Additional information on SSP I 2C operation can be
found in the “PICmicro® Mid-Range MCU Family
Reference Manual” (DS33023).
Set, Reset
S, P bits
(SSPSTAT Reg)
When an address is matched, or the data transfer after
an address match is received, the hardware automatically will generate the Acknowledge (ACK) pulse, and
then load the SSPBUF register with the received value
currently in the SSPSR register.
There are certain conditions that will cause the SSP
module not to give this ACK pulse. They include (either
or both):
a)
The SSP module has five registers for
These are the:
•
•
•
•
SLAVE MODE
In Slave mode, the SCL and SDA pins must be configured as inputs (TRISC<4:3> set). The SSP module will
override the input state with the output data when
required (slave-transmitter).
SSPSR Reg
MSb
• I 2C Slave mode (7-bit address)
• I 2C Slave mode (10-bit address)
• I 2C Slave mode (7-bit address), with Start and
Stop bit interrupts enabled to support Firmware
Master mode
• I 2C Slave mode (10-bit address), with Start and
Stop bit interrupts enabled to support Firmware
Master mode
• I 2C Start and Stop bit interrupts enabled to support Firmware Master mode, Slave is Idle
9.3.1
Shift
Clock
RC4/
SDI/
SDA
The SSPCON register allows control of the I 2C operation. Four mode selection bits (SSPCON<3:0>) allow
one of the following I 2C modes to be selected:
I2C
operation.
SSP Control Register (SSPCON)
SSP Status Register (SSPSTAT)
Serial Receive/Transmit Buffer (SSPBUF)
SSP Shift Register (SSPSR) – Not directly
accessible
• SSP Address Register (SSPADD)
b)
The Buffer Full bit BF (SSPSTAT<0>) was set
before the transfer was received.
The overflow bit SSPOV (SSPCON<6>) was set
before the transfer was received.
In this case, the SSPSR register value is not loaded
into the SSPBUF, but bit SSPIF (PIR1<3>) is set.
Table 9-2 shows what happens when a data transfer
byte is received, given the status of bits BF and
SSPOV. The shaded cells show the condition where
user software did not properly clear the overflow condition. Flag bit BF is cleared by reading the SSPBUF
register, while bit SSPOV is cleared through software.
The SCL clock input must have a minimum high and
low for proper operation. The high and low times of the
I2C specification, as well as the requirements of the
SSP module, are shown in timing parameter #100 and
parameter #101.
© 2006 Microchip Technology Inc.
DS21993A-page 65
PIC16CR7X
9.3.1.1
Addressing
Once the SSP module has been enabled, it waits for a
Start condition to occur. Following the Start condition,
the 8-bits are shifted into the SSPSR register. All
incoming bits are sampled with the rising edge of the
clock (SCL) line. The value of register SSPSR<7:1> is
compared to the value of the SSPADD register. The
address is compared on the falling edge of the eighth
clock (SCL) pulse. If the addresses match, and the BF
and SSPOV bits are clear, the following events occur:
a)
b)
c)
d)
The SSPSR register value is loaded into the
SSPBUF register.
The Buffer Full bit, BF is set.
An ACK pulse is generated.
SSP Interrupt Flag bit, SSPIF (PIR1<3>) is set
(interrupt is generated if enabled) – on the falling
edge of the ninth SCL pulse.
In 10-bit Address mode, two address bytes need to be
received by the slave (Figure 9-7). The five Most Significant bits (MSbs) of the first address byte specify if
this is a 10-bit address. Bit R/W (SSPSTAT<2>) must
specify a write so the slave device will receive the second address byte. For a 10-bit address, the first byte
would equal ‘1111 0 A9 A8 0’, where A9 and A8 are
the two MSbs of the address.
TABLE 9-2:
The sequence of events for 10-bit address is as
follows, with steps 7-9 for slave-transmitter:
1.
2.
3.
4.
5.
6.
7.
8.
9.
Receive first (high) byte of address (bits SSPIF,
BF, and bit UA (SSPSTAT<1>) are set).
Update the SSPADD register with second (low)
byte of address (clears bit UA and releases the
SCL line).
Read the SSPBUF register (clears bit BF) and
clear flag bit SSPIF.
Receive second (low) byte of address (bits
SSPIF, BF and UA are set).
Update the SSPADD register with the first (high)
byte of address, if match releases SCL line, this
will clear bit UA.
Read the SSPBUF register (clears bit BF) and
clear flag bit SSPIF.
Receive Repeated Start condition.
Receive first (high) byte of address (bits SSPIF
and BF are set).
Read the SSPBUF register (clears bit BF) and
clear flag bit SSPIF.
DATA TRANSFER RECEIVED BYTE ACTIONS
Status Bits as Data
Transfer is Received
SSPSR → SSPBUF
Generate ACK
Pulse
Set bit SSPIF
(SSP Interrupt occurs
if enabled)
BF
SSPOV
0
0
Yes
Yes
Yes
1
0
No
No
Yes
1
1
No
No
Yes
0
Note:
9.3.1.2
1
No
No
Yes
Shaded cells show the conditions where the user software did not properly clear the overflow condition.
Reception
When the R/W bit of the address byte is clear and an
address match occurs, the R/W bit of the SSPSTAT
register is cleared. The received address is loaded into
the SSPBUF register.
When the address byte overflow condition exists, then
no Acknowledge (ACK) pulse is given. An overflow
condition is defined as either bit BF (SSPSTAT<0>) is
set, or bit SSPOV (SSPCON<6>) is set. This is an error
condition due to the user’s firmware.
An SSP interrupt is generated for each data transfer
byte. Flag bit SSPIF (PIR1<3>) must be cleared in software. The SSPSTAT register is used to determine the
status of the byte.
DS21993A-page 66
© 2006 Microchip Technology Inc.
PIC16CR7X
I 2C™ WAVEFORMS FOR RECEPTION (7-BIT ADDRESS)
FIGURE 9-6:
Receiving Address
SCL
R/W=0
A7 A6 A5 A4 A3 A2 A1
SDA
1
S
2
3
4
5
6
7
ACK
Receiving Data
Receiving Data
ACK
ACK
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
9
1
8
2
SSPIF (PIR1<3>)
3
4
5
6
7
8
9
1
2
3
5
4
8
7
6
9
Cleared in software
BF (SSPSTAT<0>)
P
Bus Master
terminates
transfer
SSPBUF register is read
SSPOV (SSPCON<6>)
Bit SSPOV is set because the SSPBUF register is still full.
ACK is not sent.
9.3.1.3
Transmission
An SSP interrupt is generated for each data transfer
byte. Flag bit SSPIF must be cleared in software and
the SSPSTAT register is used to determine the status
of the byte. Flag bit SSPIF is set on the falling edge of
the ninth clock pulse.
When the R/W bit of the incoming address byte is set
and an address match occurs, the R/W bit of the
SSPSTAT register is set. The received address is
loaded into the SSPBUF register. The ACK pulse will
be sent on the ninth bit, and pin RC3/SCK/SCL is held
low. The transmit data must be loaded into the
SSPBUF register, which also loads the SSPSR register. Then, pin RC3/SCK/SCL should be enabled by setting bit CKP (SSPCON<4>). The master must monitor
the SCL pin prior to asserting another clock pulse. The
slave devices may be holding off the master by stretching the clock. The eight data bits are shifted out on the
falling edge of the SCL input. This ensures that the
SDA signal is valid during the SCL high time (Figure 9-7).
I 2C™ WAVEFORMS FOR TRANSMISSION (7-BIT ADDRESS)
FIGURE 9-7:
Receiving Address
SDA
SCL
A7
S
As a slave-transmitter, the ACK pulse from the masterreceiver is latched on the rising edge of the ninth SCL
input pulse. If the SDA line was high (not ACK), then
the data transfer is complete. When the ACK is latched
by the slave, the slave logic is reset (resets SSPSTAT
register) and the slave then monitors for another occurrence of the Start bit. If the SDA line was low (ACK), the
transmit data must be loaded into the SSPBUF register,
which also loads the SSPSR register. Then pin RC3/
SCK/SCL should be enabled by setting bit CKP.
A6
1
2
Data in
sampled
R/W = 1
A5
A4
A3
A2
A1
3
4
5
6
7
SSPIF (PIR1<3>)
8
9
ACK
Transmitting Data
ACK
D7
1
SCL held low
while CPU
responds to SSPIF
D6
D5
D4
D3
D2
D1
D0
2
3
4
5
6
7
8
9
P
Cleared in software
BF (SSPSTAT<0>)
SSPBUF is written in software
From SSP Interrupt
Service Routine
CKP (SSPCON<4>)
Set bit after writing to SSPBUF
(the SSPBUF must be written to
before the CKP bit can be set)
© 2006 Microchip Technology Inc.
DS21993A-page 67
PIC16CR7X
9.3.2
MASTER MODE
9.3.3
Master mode of operation is supported in firmware
using interrupt generation on the detection of the Start
and Stop conditions. The Stop (P) and Start (S) bits are
cleared from a Reset or when the SSP module is disabled. The Stop (P) and Start (S) bits will toggle based
on the Start and Stop conditions. Control of the I 2C bus
may be taken when the P bit is set, or the bus is Idle
and both the S and P bits are clear.
MULTI-MASTER MODE
In Multi-Master mode, the interrupt generation on the
detection of the Start and Stop conditions, allows the
determination of when the bus is free. The Stop (P) and
Start (S) bits are cleared from a Reset or when the SSP
module is disabled. The Stop (P) and Start (S) bits will
toggle based on the Start and Stop conditions. Control
of the I 2C bus may be taken when bit P (SSPSTAT<4>)
is set, or the bus is Idle and both the S and P bits clear.
When the bus is busy, enabling the SSP Interrupt will
generate the interrupt when the Stop condition occurs.
In Master mode, the SCL and SDA lines are manipulated by clearing the corresponding TRISC<4:3> bit(s).
The output level is always low, irrespective of the
value(s) in PORTC<4:3>. So when transmitting data, a
‘1’ data bit must have the TRISC<4> bit set (input) and
a ‘0’ data bit must have the TRISC<4> bit cleared (output). The same scenario is true for the SCL line with the
TRISC<3> bit. Pull-up resistors must be provided
externally to the SCL and SDA pins for proper
operation of the I2C module.
In Multi-Master operation, the SDA line must be monitored to see if the signal level is the expected output
level. This check only needs to be done when a high
level is output. If a high level is expected and a low level
is present, the device needs to release the SDA and
SCL lines (set TRISC<4:3>). There are two stages
where this arbitration can be lost, these are:
• Address Transfer
• Data Transfer
The following events will cause SSP Interrupt Flag bit,
SSPIF, to be set (SSP Interrupt will occur if enabled):
When the slave logic is enabled, the slave continues to
receive. If arbitration was lost during the address transfer stage, communication to the device may be in
progress. If addressed, an ACK pulse will be generated. If arbitration was lost during the data transfer
stage, the device will need to retransfer the data at a
later time.
• Start condition
• Stop condition
• Data transfer byte transmitted/received
Master mode of operation can be done with either the
Slave mode Idle (SSPM3:SSPM0 = 1011), or with the
Slave active. When both Master and Slave modes are
enabled, the software needs to differentiate the
source(s) of the interrupt.
REGISTERS ASSOCIATED WITH I2C™ OPERATION
TABLE 9-3:
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on:
POR,
BOR
Value on
all other
Resets
0Bh, 8Bh, INTCON
10Bh,18Bh
GIE
PEIE
TMR0IE
INTE
RBIE
TMR0IF
INTF
RBIF
0000 000x
0000 000u
Address
0Ch
PIR1
PSPIF(1)
ADIF
RCIF
TXIF
SSPIF CCP1IF TMR2IF TMR1IF
0000 0000
0000 0000
8Ch
PIE1
PSPIE(1)
ADIE
RCIE
TXIE
SSPIE CCP1IE TMR2IE TMR1IE
0000 0000
0000 0000
13h
SSPBUF Synchronous Serial Port Receive Buffer/Transmit Register
xxxx xxxx
uuuu uuuu
93h
SSPADD Synchronous Serial Port (I2C™ mode) Address Register
0000 0000
0000 0000
14h
SSPCON
WCOL
SSPOV SSPEN
0000 0000
0000 0000
94h
SSPSTAT
SMP(2)
CKE(2)
0000 0000
0000 0000
87h
TRISC
1111 1111
1111 1111
Legend:
x = unknown, u = unchanged, - = unimplemented locations read as ‘0’. Shaded cells are not used by SSP module in
I2C™ mode.
PSPIF and PSPIE are reserved on the PIC16CR73/76; always maintain these bits clear.
Maintain these bits clear in I2C mode.
Note 1:
2:
DS21993A-page 68
CKP
D/A
PORTC Data Direction Register
P
SSPM3 SSPM2 SSPM1 SSPM0
S
R/W
UA
BF
© 2006 Microchip Technology Inc.
PIC16CR7X
10.0
UNIVERSAL SYNCHRONOUS
ASYNCHRONOUS RECEIVER
TRANSMITTER (USART)
The Universal Synchronous Asynchronous Receiver
Transmitter (USART) module is one of the two serial
I/O modules. (USART is also known as a Serial
Communications Interface or SCI.) The USART can be
configured as a full duplex asynchronous system that
can communicate with peripheral devices, such as
CRT terminals and personal computers, or it can be
configured as a half duplex synchronous system that
can communicate with peripheral devices, such as A/D
or D/A integrated circuits, serial EEPROMs, etc.
REGISTER 10-1:
The USART can be configured in the following modes:
• Asynchronous (full duplex)
• Synchronous – Master (half duplex)
• Synchronous – Slave (half duplex)
Bit SPEN (RCSTA<7>) and bits TRISC<7:6> have to be
set in order to configure pins RC6/TX/CK and
RC7/
RX/DT as the Universal Synchronous Asynchronous
Receiver Transmitter.
TXSTA: TRANSMIT STATUS AND CONTROL (ADDRESS 98h)
R/W-0
R/W-0
R/W-0
R/W-0
U-0
R/W-0
R-1
R/W-0
CSRC
TX9
TXEN
SYNC
—
BRGH
TRMT
TX9D
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7
CSRC: Clock Source Select bit
Asynchronous mode:
Don’t care
Synchronous mode:
1 = Master mode (clock generated internally from BRG)
0 = Slave mode (clock from external source)
bit 6
TX9: 9-bit Transmit Enable bit
1 = Selects 9-bit transmission
0 = Selects 8-bit transmission
bit 5
TXEN: Transmit Enable bit
1 = Transmit enabled
0 = Transmit disabled
bit 4
SYNC: USART Mode Select bit
1 = Synchronous mode
0 = Asynchronous mode
bit 3
Unimplemented: Read as ‘0’
bit 2
BRGH: High Baud Rate Select bit
Asynchronous mode:
1 = High speed
0 = Low speed
Synchronous mode:
Unused in this mode
bit 1
TRMT: Transmit Shift Register Status bit
1 = TSR empty
0 = TSR full
bit 0
TX9D: 9th bit of Transmit Data
Can be parity bit
Note:
x = Bit is unknown
SREN/CREN overrides TXEN in Sync mode
© 2006 Microchip Technology Inc.
DS21993A-page 69
PIC16CR7X
REGISTER 10-2:
RCSTA: RECEIVE STATUS AND CONTROL (ADDRESS 18h)
R/W-0
R/W-0
R/W-0
R/W-0
U-0
R-0
R-0
R-x
SPEN
RX9
SREN
CREN
—
FERR
OERR
RX9D
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
SPEN: Serial Port Enable bit
1 = Serial port enabled (configures RC7/RX/DT and RC6/TX/CK pins as serial port pins)
0 = Serial port disabled
bit 6
RX9: 9-bit Receive Enable bit
1 = Selects 9-bit reception
0 = Selects 8-bit reception
bit 5
SREN: Single Receive Enable bit
Asynchronous mode:
Don’t care
Synchronous mode – Master:
1 = Enables single receive
0 = Disables single receive
This bit is cleared after reception is complete.
Synchronous mode – Slave:
Don’t care
bit 4
CREN: Continuous Receive Enable bit
Asynchronous mode:
1 = Enables continuous receive
0 = Disables continuous receive
Synchronous mode:
1 = Enables continuous receive until enable bit CREN is cleared (CREN overrides SREN)
0 = Disables continuous receive
bit 3
Unimplemented: Read as ‘0’
bit 2
FERR: Framing Error bit
1 = Framing error (can be updated by reading RCREG register and receive next valid byte)
0 = No framing error
bit 1
OERR: Overrun Error bit
1 = Overrun error (can be cleared by clearing bit CREN)
0 = No overrun error
bit 0
RX9D: 9th bit of Received Data
Can be parity bit (parity to be calculated by firmware)
DS21993A-page 70
© 2006 Microchip Technology Inc.
PIC16CR7X
10.1
USART Baud Rate Generator
(BRG)
It may be advantageous to use the high baud rate
(BRGH = 1), even for slower baud clocks. This is
because the FOSC/(16(X + 1)) equation can reduce the
baud rate error in some cases.
The BRG supports both the Asynchronous and Synchronous modes of the USART. It is a dedicated 8-bit
baud rate generator. The SPBRG register controls the
period of a free running 8-bit timer. In Asynchronous
mode, bit BRGH (TXSTA<2>) also controls the baud
rate. In Synchronous mode, bit BRGH is ignored.
Table 10-1 shows the formula for computation of the
baud rate for different USART modes which only apply
in Master mode (internal clock).
Writing a new value to the SPBRG register causes the
BRG timer to be reset (or cleared). This ensures the
BRG does not wait for a timer overflow before outputting
the new baud rate.
10.1.1
The data on the RC7/RX/DT pin is sampled three times
by a majority detect circuit to determine if a high or a
low level is present at the RX pin.
Given the desired baud rate and FOSC, the nearest
integer value for the SPBRG register can be calculated
using the formula in Table 10-1. From this, the error in
baud rate can be determined.
TABLE 10-1:
SAMPLING
BAUD RATE FORMULA
SYNC
BRGH = 0 (Low Speed)
BRGH = 1 (High Speed)
0
1
(Asynchronous) Baud Rate = FOSC/(64(X+1))
(Synchronous) Baud Rate = FOSC/(4(X+1))
Baud Rate = FOSC/(16(X+1))
N/A
X = value in SPBRG (0 to 255)
TABLE 10-2:
REGISTERS ASSOCIATED WITH BAUD RATE GENERATOR
Bit 0
Value on:
POR,
BOR
Value on
all other
Resets
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
98h
TXSTA
CSRC
TX9
TXEN
SYNC
—
BRGH
TRMT
TX9D 0000 -010
0000 -010
18h
RCSTA
SPEN
RX9
SREN CREN
—
FERR
OERR RX9D 0000 -00x
0000 -00x
99h
SPBRG Baud Rate Generator Register
0000 0000
0000 0000
Legend: x = unknown, - = unimplemented, read as ‘0’. Shaded cells are not used by the BRG.
© 2006 Microchip Technology Inc.
DS21993A-page 71
PIC16CR7X
TABLE 10-3:
BAUD RATES FOR ASYNCHRONOUS MODE (BRGH = 0)
FOSC = 20 MHz
BAUD
RATE
FOSC = 16 MHz
BAUD
%
ERROR
SPBRG
VALUE
(DECIMAL)
1200
1,221
1.73%
2400
2,404
0.16%
9600
9,470
19,200
FOSC = 10 MHz
BAUD
%
ERROR
SPBRG
VALUE
(DECIMAL)
BAUD
%
ERROR
SPBRG
VALUE
(DECIMAL)
255
1,202
0.16%
129
2,404
0.16%
207
1,202
0.16%
129
103
2,404
0.16%
-1.36%
32
9,615
64
0.16%
25
9,766
1.73%
19,531
1.73%
15
15
19,231
0.16%
12
19,531
1.73%
38,400
39,063
1.73%
7
7
35,714
-6.99%
6
39,063
1.73%
3
57,600
62,500
8.51%
4
62,500
8.51%
76,800
78,125
1.73%
3
83,333
8.51%
3
52,083
-9.58%
2
2
78,125
1.73%
1
96,000
104,167
8.51%
2
83,333
-13.19%
2
78,125
-18.62%
1
115,200
104,167
-9.58%
2
125,000
8.51%
1
78,125
-32.18%
1
250,000
312,500
25.00%
0
250,000
0.00%
0
156,250
-37.50%
0
FOSC = 4 MHz
BAUD
RATE
BAUD
FOSC = 3.6864 MHz
%
ERROR
SPBRG
VALUE
(DECIMAL)
BAUD
FOSC = 3.579545 MHz
%
ERROR
SPBRG
VALUE
(DECIMAL)
BAUD
%
ERROR
SPBRG
VALUE
(DECIMAL)
300
300
0.16%
207
300
0.00%
191
301
0.23%
185
1200
1,202
0.16%
51
1,200
0.00%
47
1,190
-0.83%
46
2400
2,404
0.16%
25
2,400
0.00%
23
2,432
1.32%
22
9600
8,929
-6.99%
6
9,600
0.00%
5
9,322
-2.90%
5
19,200
20,833
8.51%
2
19,200
0.00%
2
18,643
-2.90%
2
38,400
31,250
-18.62%
1
28,800
-25.00%
1
27,965
-27.17%
1
57,600
62,500
8.51%
0
76,800
62,500
-18.62%
0
57,600
—
0.00%
—
0
—
55,930
—
-2.90%
—
0
—
TABLE 10-4:
BAUD RATES FOR ASYNCHRONOUS MODE (BRGH = 1)
FOSC = 20 MHz
BAUD
RATE
BAUD
%
ERROR
FOSC = 16 MHz
SPBRG
VALUE
(DECIMAL)
BAUD
%
ERROR
FOSC = 10 MHz
SPBRG
VALUE
(DECIMAL)
BAUD
%
ERROR
SPBRG
VALUE
(DECIMAL)
255
2400
—
—
—
—
—
—
2,441
1.73%
9600
9,615
0.16%
129
9,615
0.16%
103
9,615
0.16%
64
19,200
19,231
0.16%
64
19,231
0.16%
51
18,939
-1.36%
32
38,400
37,879
-1.36%
32
38,462
0.16%
25
39,063
1.73%
15
57,600
56,818
-1.36%
21
58,824
2.12%
16
56,818
-1.36%
10
76,800
78,125
1.73%
15
76,923
0.16%
12
78,125
1.73%
7
96,000
96,154
0.16%
12
100,000
4.17%
9
89,286
-6.99%
6
115,200
113,636
-1.36%
10
111,111
-3.55%
8
125,000
8.51%
4
250,000
250,000
0.00%
4
250,000
0.00%
3
208,333
-16.67%
2
300,000
312,500
4.17%
3
333,333
11.11%
2
312,500
4.17%
1
FOSC = 4 MHz
BAUD
RATE
(K)
BAUD
%
ERROR
FOSC = 3.6864 MHz
SPBRG
VALUE
(DECIMAL)
BAUD
FOSC = 3.579545 MHz
%
ERROR
SPBRG
VALUE
(DECIMAL)
BAUD
%
ERROR
SPBRG
VALUE
(DECIMAL)
185
1200
2400
1,202
0.16%
207
1,200
0.00%
191
1,203
0.23%
2,404
0.16%
103
2,400
0.00%
95
2,406
0.23%
92
9600
9,615
0.16%
25
9,600
0.00%
23
9,727
1.32%
22
19,200
19,231
0.16%
12
19,200
0.00%
11
18,643
-2.90%
11
38,400
35,714
-6.99%
6
38,400
0.00%
5
37,287
-2.90%
5
57,600
62,500
8.51%
3
57,600
0.00%
3
55,930
-2.90%
3
76,800
83,333
8.51%
2
76,800
0.00%
2
74,574
-2.90%
2
96,000
83,333
-13.19%
2
115,200
20.00%
1
111,861
16.52%
1
115,200
125,000
8.51%
1
115,200
0.00%
1
111,861
-2.90%
1
250,000
250,000
0.00%
0
230,400
-7.84%
0
223,722
-10.51%
0
DS21993A-page 72
© 2006 Microchip Technology Inc.
PIC16CR7X
10.2
USART Asynchronous Mode
In this mode, the USART uses standard non-return-tozero (NRZ) format (one Start bit, eight or nine data bits,
and one Stop bit). The most common data format is 8bits. An on-chip, dedicated, 8-bit baud rate generator
can be used to derive standard baud rate frequencies
from the oscillator. The USART transmits and receives
the LSb first. The USART’s transmitter and receiver are
functionally independent, but use the same data format
and baud rate. The baud rate generator produces a
clock, either x16 or x64 of the bit shift rate, depending
on bit BRGH (TXSTA<2>). Parity is not supported by
the hardware, but can be implemented in software (and
stored as the ninth data bit). Asynchronous mode is
stopped during Sleep.
Asynchronous mode is selected by clearing bit SYNC
(TXSTA<4>).
The USART Asynchronous module consists of the
following important elements:
•
•
•
•
Baud Rate Generator
Sampling Circuit
Asynchronous Transmitter
Asynchronous Receiver
10.2.1
USART ASYNCHRONOUS
TRANSMITTER
The USART transmitter block diagram is shown in
Figure 10-1. The heart of the transmitter is the Transmit
(serial) Shift Register (TSR). The shift register obtains its
data from the read/write transmit buffer, TXREG. The
TXREG register is loaded with data by firmware. The
TSR register is not loaded until the Stop bit has been
transmitted from the previous load. As soon as the Stop
bit is transmitted, the TSR is loaded with new data from
the TXREG register (if available). Once the TXREG
register transfers the data to the TSR register, the
TXREG register is empty. One instruction cycle later,
flag bit TXIF (PIR1<4>) and flag bit TRMT (TXSTA<1>)
are set. The TXIF interrupt can be enabled/disabled by
setting/clearing enable bit TXIE (PIE1<4>). Flag bit TXIF
will be set, regardless of the state of enable bit TXIE and
cannot be cleared in software. It will reset only when new
data is loaded into the TXREG register. While flag bit
TXIF indicates the status of the TXREG register, another
bit TRMT (TXSTA<1>) shows the status of the TSR
register. Status bit TRMT is a read-only bit, which is set
one instruction cycle after the TSR register becomes
empty, and is cleared one instruction cycle after the TSR
register is loaded. No interrupt logic is tied to this bit, so
the user has to poll this bit in order to determine if the
TSR register is empty.
© 2006 Microchip Technology Inc.
Note 1: The TSR register is not mapped in data
memory, so it is not available to the user.
2: Flag bit TXIF is set when enable bit TXEN
is set. TXIF is cleared by loading TXREG.
Transmission is enabled by setting enable bit TXEN
(TXSTA<5>). The actual transmission will not occur
until the TXREG register has been loaded with data
and the baud rate generator (BRG) has produced a
shift clock (Figure 10-2). The transmission can also be
started by first loading the TXREG register and then
setting enable bit TXEN. Normally, when transmission
is first started, the TSR register is empty. At that point,
transfer to the TXREG register will result in an immediate transfer to TSR, resulting in an empty TXREG. A
back-to-back transfer is thus possible (Figure 10-3).
Clearing enable bit TXEN during a transmission will
cause the transmission to be aborted and will reset the
transmitter. As a result, the RC6/TX/CK pin will revert
to high-impendance.
In order to select 9-bit transmission, transmit bit TX9
(TXSTA<6>) should be set and the ninth bit should be
written to TX9D (TXSTA<0>). The ninth bit must be
written before writing the 8-bit data to the TXREG
register. This is because a data write to the TXREG
register can result in an immediate transfer of the data
to the TSR register (if the TSR is empty). In such a
case, an incorrect ninth data bit may be loaded in the
TSR register.
DS21993A-page 73
PIC16CR7X
FIGURE 10-1:
USART TRANSMIT BLOCK DIAGRAM
Data Bus
TXIF
TXREG Register
TXIE
8
MSb
(8)
LSb
0
• • •
Pin Buffer
and Control
TSR Register
RC6/TX/CK pin
Interrupt
TXEN
Baud Rate CLK
TRMT
SPEN
SPBRG
Baud Rate Generator
TX9
TX9D
Steps to follow when setting up an Asynchronous
Transmission:
5.
1.
6.
2.
3.
4.
Initialize the SPBRG register for the appropriate
baud rate. If a high speed baud rate is desired,
set bit BRGH (Section 10.1 “USART Baud
Rate Generator (BRG)”).
Enable the asynchronous serial port by clearing
bit SYNC and setting bit SPEN.
If interrupts are desired, then set enable bit
TXIE.
If 9-bit transmission is desired, then set transmit
bit TX9.
FIGURE 10-2:
7.
8.
Enable the transmission by setting bit TXEN,
which will also set bit TXIF.
If 9-bit transmission is selected, the ninth bit
should be loaded in bit TX9D.
Load data to the TXREG register (starts
transmission).
If using interrupts, ensure that GIE and PEIE in
the INTCON register are set.
ASYNCHRONOUS MASTER TRANSMISSION
Write to TXREG
BRG Output
(Shift Clock)
RC6/TX/CK (pin)
Word 1
Start bit
TXIF bit
(Transmit Buffer
Reg. Empty Flag)
TRMT bit
(Transmit Shift
Reg. Empty Flag)
DS21993A-page 74
bit 0
bit 1
Word 1
bit 7/8
Stop bit
Word 1
Transmit Shift Reg
© 2006 Microchip Technology Inc.
PIC16CR7X
FIGURE 10-3:
ASYNCHRONOUS MASTER TRANSMISSION (BACK-TO-BACK)
Write to TXREG
RC6/TX/CK (pin)
TXIF bit
(Interrupt Reg. Flag)
TRMT bit
(Transmit Shift
Reg. Empty Flag)
Word 2
Word 1
BRG Output
(Shift Clock)
Start bit
bit 0
bit 1
Word 1
bit 7/8
Word 1
Transmit Shift Reg.
Stop bit
Start bit
Word 2
bit 0
Word 2
Transmit Shift Reg.
Note: This timing diagram shows two consecutive transmissions.
TABLE 10-5:
Address
REGISTERS ASSOCIATED WITH ASYNCHRONOUS TRANSMISSION
Name
0Bh, 8Bh, INTCON
10Bh,18Bh
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on:
POR,
BOR
Value on
all other
Resets
GIE
PEIE
TMR0IE
INTE
RBIE
TMR0IF
INTF
RBIF
0000 000x
0000 000u
PSPIF(1)
ADIF
RCIF
TXIF
SSPIF
CCP1IF
TMR2IF
TMR1IF
0000 0000
0000 0000
SPEN
RX9
SREN
CREN
—
FERR
OERR
RX9D
0000 -00x
0000 -00x
0000 0000
0000 0000
TMR2IE
TMR1IE
0000 0000
0000 0000
TRMT
TX9D
0000 -010
0000 -010
0000 0000
0000 0000
0Ch
PIR1
18h
RCSTA
19h
TXREG
8Ch
PIE1
98h
TXSTA
99h
SPBRG Baud Rate Generator Register
Legend:
Note 1:
x = unknown, - = unimplemented locations read as ‘0’. Shaded cells are not used for asynchronous transmission.
Bits PSPIE and PSPIF are reserved on the PIC16CR73/76; always maintain these bits clear.
10.2.2
USART ASYNCHRONOUS
RECEIVER
USART Transmit Data Register
PSPIE(1)
ADIE
RCIE
TXIE
CSRC
TX9
TXEN
SYNC
The receiver block diagram is shown in Figure 10-4.
The data is received on the RC7/RX/DT pin and drives
the data recovery block. The data recovery block is
actually a high-speed shifter operating at x16 times the
baud rate, whereas the main receive serial shifter
operates at the bit rate, or at FOSC.
Once Asynchronous mode is selected, reception is
enabled by setting bit CREN (RCSTA<4>).
The heart of the receiver is the Receive (serial) Shift
Register (RSR). After sampling the Stop bit, the
received data in the RSR is transferred to the RCREG
register (if it is empty). If the transfer is complete, flag
bit RCIF (PIR1<5>) is set. The actual interrupt can be
enabled/disabled by setting/clearing enable bit RCIE
(PIE1<5>). Flag bit RCIF is a read-only bit which is
cleared by the hardware. It is cleared when the RCREG
register has been read and is empty. The RCREG is a
double buffered register (i.e., it is a two-deep FIFO). It
is possible for two bytes of data to be received and
transferred to the RCREG FIFO and a third byte to
begin shifting to the RSR register. On the detection of
the Stop bit of the third byte, if the RCREG register is
still full, the overrun error bit OERR (RCSTA<1>) will be
set. The word in the RSR will be lost. The RCREG
register can be read twice to retrieve the two bytes in
© 2006 Microchip Technology Inc.
SSPIE CCP1IE
—
BRGH
the FIFO. Overrun bit OERR has to be cleared in software. This is done by resetting the receive logic (CREN
is cleared and then set). If bit OERR is set, transfers
from the RSR register to the RCREG register are inhibited and no further data will be received, therefore, it is
essential to clear error bit OERR if it is set. Framing
error bit FERR (RCSTA<2>) is set if a Stop bit is
detected as clear. Bit FERR and the 9th receive bit are
buffered the same way as the receive data. Reading
the RCREG will load bits RX9D and FERR with new
values, therefore, it is essential for the user to read the
RCSTA register before reading RCREG register, in
order not to lose the old FERR and RX9D information.
DS21993A-page 75
PIC16CR7X
FIGURE 10-4:
USART RECEIVE BLOCK DIAGRAM
x64 Baud Rate CLK
FERR
OERR
CREN
FOSC
SPBRG
Baud Rate Generator
RSR Register
MSb
÷64
or
÷16
Stop
(8)
• • •
7
1
LSb
0 Start
RC7/RX/DT
Pin Buffer
and Control
Data
Recovery
RX9
RX9D
SPEN
RCREG Register
FIFO
8
RCIF
Interrupt
Data Bus
RCIE
FIGURE 10-5:
ASYNCHRONOUS RECEPTION
Start
bit
RX (pin)
bit 0
bit 1
bit 7/8 Stop
bit
Rcv Shift
Reg
Rcv Buffer Reg
Read Rcv
Buffer reg
RCREG
Start
bit
bit 0
bit 7/8
Stop
bit
Start
bit
bit 7/8
Stop
bit
Word 2
RCREG
Word 1
RCREG
RCIF
(Interrupt Flag)
OERR bit
CREN
Note:
This timing diagram shows three words appearing on the RX input. The RCREG (receive buffer) is read after the third word,
causing the OERR (overrun) bit to be set. An overrun error indicates an error in user firmware.
Steps to follow when setting up an Asynchronous
Reception:
1.
2.
3.
4.
5.
6.
7.
Initialize the SPBRG register for the appropriate
baud rate. If a high speed baud rate is desired,
set bit BRGH (Section 10.1 “USART Baud
Rate Generator (BRG)”).
Enable the asynchronous serial port by clearing
bit SYNC and setting bit SPEN.
If interrupts are desired, then set enable bit
RCIE.
If 9-bit reception is desired, then set bit RX9.
Enable the reception by setting bit CREN.
Flag bit RCIF will be set when reception is complete and an interrupt will be generated if enable
bit RCIE is set.
Read the RCSTA register to get the ninth bit (if
enabled) and determine if any error occurred
during reception.
DS21993A-page 76
8.
Read the 8-bit received data by reading the
RCREG register.
9. If any error occurred, clear the error by clearing
enable bit CREN.
10. If using interrupts, ensure that GIE and PEIE in
the INTCON register are set.
© 2006 Microchip Technology Inc.
PIC16CR7X
TABLE 10-6:
Address
REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION
Name
0Bh, 8Bh, INTCON
10Bh,18Bh
0Ch
PIR1
18h
RCSTA
1Ah
RCREG
8Ch
PIE1
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on:
POR,
BOR
Value on
all other
Resets
GIE
PEIE
TMR0IE
INTE
RBIE
TMR0IF
INTF
RBIF
0000 000x
0000 000u
PSPIF(1)
ADIF
RCIF
TXIF
SSPIF
CCP1IF
TMR2IF
TMR1IF
0000 0000
0000 0000
SPEN
RX9
SREN
CREN
—
FERR
OERR
RX9D
0000 -00x
0000 -00x
0000 0000
0000 0000
USART Receive Register
PSPIE(1)
ADIE
RCIE
TXIE
SSPIE
CCP1IE
TMR2IE
TMR1IE
0000 0000
0000 0000
CSRC
TX9
TXEN
SYNC
—
BRGH
TRMT
TX9D
0000 -010
0000 -010
0000 0000
0000 0000
98h
TXSTA
99h
SPBRG
Legend:
Note 1:
x = unknown, - = unimplemented locations read as ‘0’. Shaded cells are not used for asynchronous reception.
Bits PSPIE and PSPIF are reserved on the PIC16CR73/76 devices; always maintain these bits clear.
Baud Rate Generator Register
© 2006 Microchip Technology Inc.
DS21993A-page 77
PIC16CR7X
10.3
USART Synchronous Master
Mode
In Synchronous Master mode, the data is transmitted in
a half-duplex manner (i.e., transmission and reception
do not occur at the same time). When transmitting data,
the reception is inhibited and vice versa. Synchronous
mode is entered by setting bit SYNC (TXSTA<4>). In
addition, enable bit SPEN (RCSTA<7>) is set in order
to configure the RC6/TX/CK and RC7/RX/DT I/O pins
to CK (clock) and DT (data) lines, respectively. The
Master mode indicates that the processor transmits the
master clock on the CK line. The Master mode is
entered by setting bit CSRC (TXSTA<7>).
10.3.1
USART SYNCHRONOUS MASTER
TRANSMISSION
The USART transmitter block diagram is shown in
Figure 10-1. The heart of the transmitter is the Transmit
(serial) Shift Register (TSR). The shift register obtains
its data from the read/write transmit buffer register
TXREG. The TXREG register is loaded with data in
software. The TSR register is not loaded until the last
bit has been transmitted from the previous load. As
soon as the last bit is transmitted, the TSR is loaded
with new data from the TXREG (if available). Once the
TXREG register transfers the data to the TSR register
(occurs in one TCYCLE), the TXREG is empty and interrupt bit TXIF (PIR1<4>) is set. The interrupt can be
enabled/disabled by setting/clearing enable bit TXIE
(PIE1<4>). Flag bit TXIF will be set, regardless of the
state of enable bit TXIE and cannot be cleared in software. It will reset only when new data is loaded into the
TXREG register. While flag bit TXIF indicates the status
of the TXREG register, another bit TRMT (TXSTA<1>)
shows the status of the TSR register. TRMT is a readonly bit, which is set when the TSR is empty. No
interrupt logic is tied to this bit, so the user has to poll
this bit in order to determine if the TSR register is
empty. The TSR is not mapped in data memory, so it is
not available to the user.
Transmission is enabled by setting enable bit TXEN
(TXSTA<5>). The actual transmission will not occur
until the TXREG register has been loaded with data.
The first data bit will be shifted out on the next available
rising edge of the clock on the CK line. Data out is
stable around the falling edge of the synchronous clock
(Figure 10-6). The transmission can also be started by
first loading the TXREG register and then setting bit
TXEN (Figure 10-7). This is advantageous when slow
baud rates are selected, since the BRG is kept in Reset
when bits TXEN, CREN and SREN are clear. Setting
enable bit TXEN will start the BRG, creating a shift
clock immediately. Normally, when transmission is first
started, the TSR register is empty, so a transfer to the
TXREG register will result in an immediate transfer to
TSR, resulting in an empty TXREG. Back-to-back
transfers are possible.
DS21993A-page 78
Clearing enable bit TXEN during a transmission will
cause the transmission to be aborted and will reset the
transmitter. The DT and CK pins will revert to highimpendance. If either bit CREN or bit SREN is set
during a transmission, the transmission is aborted and
the DT pin reverts to a high-impendance state (for a
reception). The CK pin will remain an output if bit CSRC
is set (internal clock). The transmitter logic, however, is
not reset, although it is disconnected from the pins. In
order to reset the transmitter, the user has to clear bit
TXEN. If bit SREN is set (to interrupt an on-going transmission and receive a single word), then after the
single word is received, bit SREN will be cleared and
the serial port will revert back to transmitting, since bit
TXEN is still set. The DT line will immediately switch
from High-Impendance Receive mode to transmit and
start driving. To avoid this, bit TXEN should be cleared.
In order to select 9-bit transmission, the TX9
(TXSTA<6>) bit should be set and the ninth bit should
be written to bit TX9D (TXSTA<0>). The ninth bit must
be written before writing the 8-bit data to the TXREG
register. This is because a data write to the TXREG can
result in an immediate transfer of the data to the TSR
register (if the TSR is empty). If the TSR was empty and
the TXREG was written before writing the “new” TX9D,
the “present” value of bit TX9D is loaded.
Steps to follow when setting up a Synchronous Master
Transmission:
1.
2.
3.
4.
5.
6.
7.
8.
Initialize the SPBRG register for the appropriate
baud rate (Section 10.1 “USART Baud Rate
Generator (BRG)”).
Enable the synchronous master serial port by
setting bits SYNC, SPEN and CSRC.
If interrupts are desired, set enable bit TXIE.
If 9-bit transmission is desired, set bit TX9.
Enable the transmission by setting bit TXEN.
If 9-bit transmission is selected, the ninth bit
should be loaded in bit TX9D.
Start transmission by loading data to the TXREG
register.
If using interrupts, ensure that GIE and PEIE in
the INTCON register are set.
© 2006 Microchip Technology Inc.
PIC16CR7X
FIGURE 10-6:
SYNCHRONOUS TRANSMISSION
Q1Q2 Q3Q4 Q1 Q2Q3 Q4Q1 Q2Q3 Q4Q1 Q2Q3 Q4Q1 Q2 Q3Q4
RC7/RX/DT
pin
bit 0
bit 1
Word 1
Q3Q4 Q1Q2 Q3Q4 Q1Q2 Q3Q4 Q1Q2 Q3 Q4Q1 Q2Q3 Q4Q1 Q2Q3 Q4Q1 Q2Q3 Q4
bit 2
bit 7
bit 0
bit 1
Word 2
bit 7
RC6/TX/CK
pin
Write to
TXREG reg
Write Word 1
Write Word 2
TXIF bit
(Interrupt Flag)
TRMTTRMT
bit
TXEN bit
‘1’
‘1’
Note: Sync Master mode; SPBRG = 0. Continuous transmission of two 8-bit words.
FIGURE 10-7:
SYNCHRONOUS TRANSMISSION (THROUGH TXEN)
RC7/RX/DT pin
bit 0
bit 1
bit 2
bit 6
bit 7
RC6/TX/CK pin
Write to
TXREG Reg
TXIF bit
TRMT bit
TXEN bit
TABLE 10-7:
Address
REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER TRANSMISSION
Name
0Bh, 8Bh, INTCON
10Bh,18Bh
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on:
POR,
BOR
Value on
all other
Resets
GIE
PEIE
TMR0IE
INTE
RBIE
TMR0IF
INTF
RBIF
0000 000x
0000 000u
PSPIF(1)
ADIF
RCIF
TXIF
SSPIF CCP1IF TMR2IF
SPEN
RX9
SREN
CREN
0Ch
PIR1
18h
RCSTA
19h
TXREG
USART Transmit Data Register
8Ch
PIE1
PSPIE(1)
ADIE
RCIE
TXIE
CSRC
TX9
TXEN
SYNC
98h
TXSTA
99h
SPBRG
Legend:
Note 1:
Baud Rate Generator Register
—
FERR
OERR
TMR1IF
0000 0000
0000 0000
RX9D
0000 -00x
0000 -00x
0000 0000
0000 0000
0000 0000
0000 0000
0000 -010
0000 -010
0000 0000
0000 0000
SSPIE CCP1IE TMR2IE TMR1IE
—
BRGH
TRMT
TX9D
x = unknown, - = unimplemented, read as ‘0’. Shaded cells are not used for synchronous master transmission.
Bits PSPIE and PSPIF are reserved on the PIC16CR73/76 devices; always maintain these bits clear.
© 2006 Microchip Technology Inc.
DS21993A-page 79
PIC16CR7X
10.3.2
USART SYNCHRONOUS MASTER
RECEPTION
data. Reading the RCREG register will load bit RX9D
with a new value, therefore, it is essential for the user
to read the RCSTA register before reading RCREG, in
order not to lose the old RX9D information.
Once Synchronous mode is selected, reception is
enabled by setting either enable bit SREN
(RCSTA<5>), or enable bit CREN (RCSTA<4>). Data is
sampled on the RC7/RX/DT pin on the falling edge of
the clock. If enable bit SREN is set, then only a single
word is received. If enable bit CREN is set, the reception is continuous until CREN is cleared. If both bits are
set, CREN takes precedence. After clocking the last bit,
the received data in the Receive Shift Register (RSR)
is transferred to the RCREG register (if it is empty).
When the transfer is complete, interrupt flag bit RCIF
(PIR1<5>) is set. The actual interrupt can be enabled/
disabled by setting/clearing enable bit RCIE
(PIE1<5>). Flag bit RCIF is a read-only bit, which is
reset by the hardware. In this case, it is reset when the
RCREG register has been read and is empty. The
RCREG is a double buffered register (i.e., it is a twodeep FIFO). It is possible for two bytes of data to be
received and transferred to the RCREG FIFO and a
third byte to begin shifting into the RSR register. On the
clocking of the last bit of the third byte, if the RCREG
register is still full, then overrun error bit OERR
(RCSTA<1>) is set. The word in the RSR will be lost.
The RCREG register can be read twice to retrieve the
two bytes in the FIFO. Bit OERR has to be cleared in
software (by clearing bit CREN). If bit OERR is set,
transfers from the RSR to the RCREG are inhibited, so
it is essential to clear bit OERR if it is set. The ninth
receive bit is buffered the same way as the receive
FIGURE 10-8:
Steps to follow when setting up a Synchronous Master
Reception:
1.
Initialize the SPBRG register for the appropriate
baud rate (Section 10.1 “USART Baud Rate
Generator (BRG)”).
2. Enable the synchronous master serial port by
setting bits SYNC, SPEN and CSRC.
3. Ensure bits CREN and SREN are clear.
4. If interrupts are desired, then set enable bit
RCIE.
5. If 9-bit reception is desired, then set bit RX9.
6. If a single reception is required, set bit SREN.
For continuous reception set bit CREN.
7. Interrupt flag bit RCIF will be set when reception
is complete and an interrupt will be generated if
enable bit RCIE was set.
8. Read the RCSTA register to get the ninth bit (if
enabled) and determine if any error occurred
during reception.
9. Read the 8-bit received data by reading the
RCREG register.
10. If any error occurred, clear the error by clearing
bit CREN.
11. If using interrupts, ensure that GIE and PEIE in
the INTCON register are set.
SYNCHRONOUS RECEPTION (MASTER MODE, SREN)
Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
RC7/RX/DT pin
bit 0
bit 1
bit 2
bit 3
bit 4
bit 5
bit 6
bit 7
RC6/TX/CK pin
Write to
bit SREN
SREN bit
CREN bit
‘0’
‘0’
RCIF bit
(Interrupt)
Read
RXREG
Note: Timing diagram demonstrates Sync Master mode with bit SREN = 1 and bit BRG = 0.
DS21993A-page 80
© 2006 Microchip Technology Inc.
PIC16CR7X
TABLE 10-8:
Address
REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER RECEPTION
Name
0Bh, 8Bh, INTCON
10Bh,18Bh
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on:
POR, BOR
Value on
all other
Resets
GIE
PEIE
TMR0IE
INTE
RBIE
TMR0IF
INTF
RBIF
0000 000x
0000 000u
PSPIF(1)
ADIF
RCIF
TXIF
SSPIF
CCP1IF
TMR2IF
SPEN
RX9
SREN
CREN
—
FERR
OERR
0Ch
PIR1
18h
RCSTA
1Ah
RCREG
USART Receive Data Register
8Ch
PIE1
PSPIE(1)
ADIE
RCIE
TXIE
98h
TXSTA
CSRC
TX9
TXEN
SYNC
99h
SPBRG
Legend:
Note 1:
x = unknown, - = unimplemented, read as ‘0’. Shaded cells are not used for synchronous master reception.
Bits PSPIE and PSPIF are reserved on the PIC16CR73/76 devices; always maintain these bits clear.
10.4
Synchronous Slave mode differs from the Master
mode, in that the shift clock is supplied externally at the
RC6/TX/CK pin (instead of being supplied internally in
Master mode). This allows the device to transfer or
receive data while in Sleep mode. Slave mode is
entered by clearing bit CSRC (TXSTA<7>).
10.4.1
USART SYNCHRONOUS SLAVE
TRANSMIT
The operation of the Synchronous Master and Slave
modes are identical except in the case of the Sleep
mode.
0000 0000
0000 0000
SSPIE CCP1IE TMR2IE TMR1IE 0000 0000
0000 0000
—
BRGH
1.
2.
3.
4.
5.
6.
a)
8.
e)
© 2006 Microchip Technology Inc.
TRMT
TX9D
0000 -010
0000 -010
0000 0000
0000 0000
Follow these steps when setting up a Synchronous
Slave Transmission:
7.
b)
c)
d)
0000 0000
0000 -00x
If two words are written to the TXREG and then the
SLEEP instruction is executed, the following will occur:
The first word will immediately transfer to the
TSR register and transmit when the master
device drives the CK line.
The second word will remain in TXREG register.
Flag bit TXIF will not be set.
When the first word has been shifted out of TSR,
the TXREG register will transfer the second
word to the TSR and flag bit TXIF will now be
set.
If enable bit TXIE is set, the interrupt will wake
the chip from Sleep and if the global interrupt is
enabled, the program will branch to the interrupt
vector (0004h).
RX9D
0000 -00x
Baud Rate Generator Register
USART Synchronous Slave Mode
TMR1IF 0000 0000
Enable the synchronous slave serial port by setting bits SYNC and SPEN and clearing bit
CSRC.
Clear bits CREN and SREN.
If interrupts are desired, then set enable bit
TXIE.
If 9-bit transmission is desired, then set bit TX9.
Enable the transmission by setting enable bit
TXEN.
If 9-bit transmission is selected, the ninth bit
should be loaded in bit TX9D.
Start transmission by loading data to the TXREG
register.
If using interrupts, ensure that GIE and PEIE in
the INTCON register are set.
DS21993A-page 81
PIC16CR7X
TABLE 10-9:
Address
REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE TRANSMISSION
Name
0Bh, 8Bh, INTCON
10Bh,18Bh
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on:
POR,
BOR
Value on
all other
Resets
GIE
PEIE
TMR0IE
INTE
RBIE
TMR0IF
INTF
RBIF
0000 000x
0000 000u
PSPIF(1)
ADIF
RCIF
TXIF
SSPIF
CCP1IF TMR2IF TMR1IF
0000 0000
0000 0000
SPEN
RX9
SREN
CREN
—
0Ch
PIR1
18h
RCSTA
19h
TXREG USART Transmit Data Register
8Ch
PIE1
98h
TXSTA
99h
SPBRG Baud Rate Generator Register
Legend:
Note 1:
x = unknown, - = unimplemented, read as ‘0’. Shaded cells are not used for synchronous slave transmission.
Bits PSPIE and PSPIF are reserved on the PIC16CR73/76 devices; always maintain these bits clear.
10.4.2
USART SYNCHRONOUS SLAVE
RECEPTION
PSPIE(1)
ADIE
RCIE
TXIE
SSPIE
CSRC
TX9
TXEN
SYNC
—
FERR
OERR
RX9D
0000 000x
0000 000x
0000 0000
0000 0000
CCP1IE TMR2IE TMR1IE 0000 0000
0000 0000
BRGH
TRMT
TX9D
0000 -010
0000 -010
0000 0000
0000 0000
Follow these steps when setting up a Synchronous
Slave Reception:
The operation of the Synchronous Master and Slave
modes is identical, except in the case of the Sleep
mode. Bit SREN is a “don’t care” in Slave mode.
1.
If receive is enabled by setting bit CREN prior to the
SLEEP instruction, then a word may be received during
Sleep. On completely receiving the word, the RSR register will transfer the data to the RCREG register and if
enable bit RCIE bit is set, the interrupt generated will
wake the chip from Sleep. If the global interrupt is
enabled, the program will branch to the interrupt vector
(0004h).
2.
3.
4.
5.
6.
7.
8.
9.
Enable the synchronous master serial port by
setting bits SYNC and SPEN and clearing bit
CSRC.
If interrupts are desired, set enable bit RCIE.
If 9-bit reception is desired, set bit RX9.
To enable reception, set enable bit CREN.
Flag bit RCIF will be set when reception is
complete and an interrupt will be generated, if
enable bit RCIE was set.
Read the RCSTA register to get the ninth bit (if
enabled) and determine if any error occurred
during reception.
Read the 8-bit received data by reading the
RCREG register.
If any error occurred, clear the error by clearing
bit CREN.
If using interrupts, ensure that GIE and PEIE in
the INTCON register are set.
TABLE 10-10: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE RECEPTION
Address
Name
0Bh, 8Bh, INTCON
10Bh,18Bh
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on:
POR,
BOR
Value on
all other
Resets
GIE
PEIE
TMR0IE
INTE
RBIE
TMR0IF
INTF
RBIF
0000 000x
0000 000u
PSPIF(1)
ADIF
RCIF
TXIF
SSPIF
CCP1IF
TMR2IF
TMR1IF
0000 0000
0000 0000
SPEN
RX9
SREN
CREN
—
FERR
OERR
RX9D
0000 000x
0000 000x
0Ch
PIR1
18h
RCSTA
1Ah
RCREG
USART Receive Data Register
8Ch
PIE1
PSPIE(1)
ADIE
RCIE
TXIE
SSPIE
98h
TXSTA
CSRC
TX9
TXEN
SYNC
—
99h
SPBRG
Legend:
Note 1:
x = unknown, - = unimplemented, read as ‘0’. Shaded cells are not used for synchronous slave reception.
Bits PSPIE and PSPIF are reserved on the PIC16CR73/76 devices, always maintain these bits clear.
DS21993A-page 82
Baud Rate Generator Register
0000 0000
0000 0000
CCP1IE TMR2IE TMR1IE 0000 0000
0000 0000
BRGH
TRMT
TX9D
0000 -010
0000 -010
0000 0000
0000 0000
© 2006 Microchip Technology Inc.
PIC16CR7X
11.0
ANALOG-TO-DIGITAL
CONVERTER (A/D) MODULE
The 8-bit Analog-to-Digital (A/D) converter module has
five inputs for the PIC16CR73/76 and eight for the
PIC16CR74/77.
The A/D allows conversion of an analog input signal to
a corresponding 8-bit digital number. The output of the
sample and hold is the input into the converter, which
generates the result via successive approximation. The
analog reference voltage is software selectable to
either the device’s positive supply voltage (VDD), or the
voltage level on the RA3/AN3/VREF pin.
The A/D converter has a unique feature of being able
to operate while the device is in Sleep mode. To operate in Sleep, the A/D conversion clock must be derived
from the A/D’s internal RC oscillator.
REGISTER 11-1:
The A/D module has three registers. These registers
are:
• A/D Result Register ((ADRES)
• A/D Control Register 0 (ADCON0)
• A/D Control Register 1 ((ADCON1)
The ADCON0 register, shown in Register 11-1,
controls the operation of the A/D module. The
ADCON1 register, shown in Register 11-2, configures
the functions of the port pins. The port pins can be
configured as analog inputs (RA3 can also be a voltage
reference), or as digital I/O.
Additional information on using the A/D module can be
found in the “PICmicro® Mid-Range MCU Family
Reference Manual” (DS33023) and in Application Note
AN546, “Using The Analog-to-Digital Converter”
(DS00546).
ADCON0: (ADDRESS 1Fh)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
U-0
R/W-0
ADCS1
ADCS0
CHS2
CHS1
CHS0
GO/DONE
—
ADON
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7-6
ADCS1:ADCS0: A/D Conversion Clock Select bits
00 = FOSC/2
01 = FOSC/8
10 = FOSC/32
11 = FRC (clock derived from the internal A/D module RC oscillator)
bit 5-3
CHS2:CHS0: Analog Channel Select bits
000 = Channel 0 (RA0/AN0)
001 = Channel 1 (RA1/AN1)
010 = Channel 2 (RA2/AN2)
011 = Channel 3 (RA3/AN3)
100 = Channel 4 (RA5/AN4)
101 = Channel 5 (RE0/AN5)(1)
110 = Channel 6 (RE1/AN6)(1)
111 = Channel 7 (RE2/AN7)(1)
bit 2
GO/DONE: A/D Conversion Status bit
If ADON = 1:
1 = A/D conversion in progress (setting this bit starts the A/D conversion)
0 =A/D conversion not in progress (this bit is automatically cleared by hardware when the
A/D conversion is complete)
bit 1
Unimplemented: Read as ‘0’
bit 0
ADON: A/D On bit
1 = A/D converter module is operating
0 = A/D converter module is shut-off and consumes no operating current
Note:
A/D channels 5, 6 and 7 are implemented on the PIC16CR74/77 only.
© 2006 Microchip Technology Inc.
DS21993A-page 83
PIC16CR7X
REGISTER 11-2:
ADCON1: (ADDRESS 1Fh)
U-0
U-0
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
—
—
—
—
—
PCFG2
PCFG1
PCFG0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-3
Unimplemented: Read as ‘0’
bit 2-0
PCFG2:PCFG0: A/D Port Configuration Control bits
PCFG2:PCFG0
RA0
RA1
RA2
RA5
RA3
000
001
010
011
100
101
11x
A
A
A
A
A
A
D
A
A
A
A
A
A
D
A
A
A
A
D
D
D
A
A
A
A
D
D
D
A
x = Bit is unknown
RE0(1) RE1(1) RE2(1)
VREF
A
VREF
A
VREF
D
A
A
D
D
D
D
D
A
A
D
D
D
D
D
A
A
D
D
D
D
D
VREF
VDD
RA3
VDD
RA3
VDD
RA3
VDD
A = Analog input
D = Digital I/O
Note 1:
RE0, RE1 and RE2 are implemented on the PIC16CR74/77 only.
DS21993A-page 84
© 2006 Microchip Technology Inc.
PIC16CR7X
The following steps should be followed for doing an
A/D conversion:
4.
1.
5.
2.
3.
Configure the A/D module:
• Configure analog pins, voltage reference and
digital I/O (ADCON1)
• Select A/D conversion clock (ADCON0)
• Turn on A/D module (ADCON0)
Configure the A/D interrupt (if desired):
• Clear ADIF bit
• Set ADIE bit
• Set PEIE bit
• Set GIE bit
Select an A/D input channel (ADCON0).
FIGURE 11-1:
6.
Wait for at least an appropriate acquisition
period.
Start conversion:
• Set GO/DONE bit (ADCON0)
Wait for the A/D conversion to complete, by
either:
• Polling for the GO/DONE bit to be cleared
(interrupts disabled)
OR
7.
8.
• Waiting for the A/D interrupt
Read A/D Result register (ADRES) and clear bit
ADIF if required.
For next conversion, go to step 3 or step 4, as
required.
A/D BLOCK DIAGRAM
CHS2:CHS0
111
110
101
RE2/AN7(1)
RE1/AN6(1)
RE0/AN5(1)
100
RA5/AN4
VIN
011
(Input Voltage)
RA3/AN3/VREF
010
RA2/AN2
A/D
Converter
001
RA1/AN1
VDD
000 or
010 or
100 or
11x
VREF
(Reference
Voltage)
000
RA0/AN0
001 or
011 or
101
PCFG2:PCFG0
Note 1: Not available on PIC16CR73/76.
© 2006 Microchip Technology Inc.
DS21993A-page 85
PIC16CR7X
11.1
A/D Acquisition Requirements
The maximum recommended impedance for analog
sources is 10 kΩ. After the analog input channel is
selected (changed), the acquisition period must pass
before the conversion can be started.
For the A/D converter to meet its specified accuracy,
the charge holding capacitor (CHOLD) must be allowed
to fully charge to the input channel voltage level. The
analog input model is shown in Figure 11-2. The source
impedance (RS) and the internal sampling switch (RSS)
impedance directly affect the time required to charge
the capacitor CHOLD. The sampling switch (RSS)
impedance varies over the device voltage (VDD), see
Figure 11-2. The source impedance affects the offset
voltage at the analog input (due to pin leakage current).
FIGURE 11-2:
To calculate the minimum acquisition time, TACQ, see
the “PICmicro® Mid-Range MCU Family Reference
Manual” (DS33023). In general, however, given a
maximum source impedance of 10 kΩ and at a
temperature of 100°C, TACQ will be no more than 16
μsec.
ANALOG INPUT MODEL
VDD
ANx
RS
CPIN
5 pF
VA
Sampling
Switch
VT = 0.6V
VT = 0.6V
RIC ≤ 1k
SS
RSS
CHOLD
= DAC Capacitance
= 51.2 pF
I leakage
± 500 nA
VSS
Legend: CPIN
VT
= input capacitance
= threshold voltage
I leakage = leakage current at the pin due to
various junctions
RIC
= interconnect resistance
SS
CHOLD
= sampling switch
= sample/hold capacitance (from DAC)
VDD
6V
5V
4V
3V
2V
5 6 7 8 9 10 11
Sampling Switch
(kΩ)
TAD vs. MAXIMUM DEVICE OPERATING FREQUENCIES (STANDARD DEVICES (C))
TABLE 11-1:
AD Clock Source (TAD)
Maximum Device Frequency
Operation
ADCS1:ADCS0
Max.
2TOSC
00
1.25 MHz
8TOSC
01
5 MHz
32TOSC
10
20 MHz
RC(1, 2, 3)
11
(Note 1)
Note 1: The RC source has a typical TAD time of 4 μs but can vary between 2-6 μs.
2: When the device frequencies are greater than 1 MHz, the RC A/D conversion clock source is only
recommended for Sleep operation.
3: For extended voltage devices (LC), please refer to the Electrical Specifications section.
DS21993A-page 86
© 2006 Microchip Technology Inc.
PIC16CR7X
11.2
Selecting the A/D Conversion
Clock
The A/D conversion time per bit is defined as TAD. The
A/D conversion requires 9.0 TAD per 8-bit conversion.
The source of the A/D conversion clock is software
selectable. The four possible options for TAD are:
•
•
•
•
2 TOSC (FOSC/2)
8 TOSC (FOSC/8)
32 TOSC (FOSC/32)
Internal RC oscillator (2-6 μs)
For correct A/D conversions, the A/D conversion clock
(TAD) must be selected to ensure a minimum TAD time
as small as possible, but no less than 1.6 μs.
11.3
Configuring Analog Port Pins
The ADCON1, TRISA and TRISE registers control the
operation of the A/D port pins. The port pins that are
desired as analog inputs must have their corresponding TRIS bits set (input). If the TRIS bit is cleared (output), the digital output level (VOH or VOL) will be
converted.
The A/D operation is independent of the state of the
CHS2:CHS0 bits and the TRIS bits.
Note 1: When reading the PORT register, all pins
configured as analog input channels will
read as cleared (a low level). Pins configured as digital inputs will convert an analog input. Analog levels on a digitally
configured input will not affect the conversion accuracy.
2: Analog levels on any pin that is defined as
a digital input, but not as an analog input,
may cause the digital input buffer to consume current that is out of the device’s
specification.
11.4
Note:
A/D Conversions
The GO/DONE bit should NOT be set in
the same instruction that turns on the A/D.
Setting the GO/DONE bit begins an A/D conversion.
When the conversion completes, the 8-bit result is
placed in the ADRES register, the GO/DONE bit is
cleared, and the ADIF flag (PIR<6>) is set.
Clearing the GO/DONE bit during a conversion will
abort the current conversion. The ADRES register will
NOT be changed and the ADIF flag will not be set.
After the GO/DONE bit is cleared at either the end of a
conversion, or by firmware, another conversion can be
initiated by setting the GO/DONE bit. Users must still
take into account the appropriate acquisition time for
the application.
11.5
A/D Operation During Sleep
The A/D module can operate during Sleep mode. This
requires that the A/D clock source be set to RC
(ADCS1:ADCS0 = 11). When the RC clock source is
selected, the A/D module waits one instruction cycle
before starting the conversion. This allows the SLEEP
instruction to be executed, which eliminates all digital
switching noise from the conversion. When the conversion is completed, the GO/DONE bit will be cleared,
and the result loaded into the ADRES register. If the
A/D interrupt is enabled, the device will wake-up from
Sleep. If the A/D interrupt is not enabled, the A/D module will then be turned off, although the ADON bit will
remain set.
When the A/D clock source is another clock option (not
RC), a SLEEP instruction will cause the present conversion to be aborted and the A/D module to be turned off,
though the ADON bit will remain set.
Turning off the A/D places the A/D module in its lowest
current consumption state.
Note:
11.6
For the A/D module to operate in Sleep,
the A/D clock source must be set to RC
(ADCS1:ADCS0 = 11). To perform an A/D
conversion in Sleep, ensure the SLEEP
instruction immediately follows the instruction that sets the GO/DONE bit.
Effects of a Reset
A device Reset forces all registers to their Reset state.
The A/D module is disabled and any conversion in
progress is aborted. All A/D input pins are configured
as analog inputs.
The ADRES register will contain unknown data after a
Power-on Reset.
If both the A/D interrupt bit ADIE (PIE1<6>) and the
peripheral interrupt enable bit PEIE (INTCON<6>) are
set, the device will wake from Sleep whenever ADIF is
set by hardware. In addition, an interrupt will also occur
if the Global Interrupt bit GIE (INTCON<7>) is set.
© 2006 Microchip Technology Inc.
DS21993A-page 87
PIC16CR7X
11.7
Use of the CCP Trigger
with minimal software overhead (moving the ADRES to
the desired location). The appropriate analog input
channel must be selected and an appropriate acquisition time should pass before the “special event trigger”
sets the GO/DONE bit (starts a conversion).
An A/D conversion can be started by the “special event
trigger” of the CCP2 module. This requires that the
CCP2M3:CCP2M0 bits (CCP2CON<3:0>) be programmed as 1011 and that the A/D module is enabled
(ADON bit is set). When the trigger occurs, the
GO/DONE bit will be set, starting the A/D conversion,
and the Timer1 counter will be reset to zero. Timer1 is
reset to automatically repeat the A/D acquisition period
TABLE 11-2:
Address
If the A/D module is not enabled (ADON is cleared),
then the “special event trigger” will be ignored by the
A/D module, but will still reset the Timer1 counter.
SUMMARY OF A/D REGISTERS
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0Bh,8Bh,
INTCON
10Bh, 18Bh
GIE
PEIE
TMR0IE
INTE
RBIE
TMR0IF
INTF
RBIF
0Ch
PIR1
PSPIF(1)
ADIF
RCIF
TXIF
SSPIF
CCP1IF
0Dh
PIR2
—
—
—
—
—
—
ADIE
RCIE
TXIE
SSPIE
CCP1IE
—
—
—
—
—
(1)
Value on:
POR,
BOR
Value on
all other
Resets
0000 000x 0000 000u
TMR2IF TMR1IF 0000 0000 0000 0000
—
CCP2IF ---- ---0 ---- ---0
8Ch
PIE1
8Dh
PIE2
1Eh
ADRES
A/D Result Register Byte
1Fh
ADCON0
ADCS1
ADCS0
9Fh
ADCON1
—
—
—
—
—
05h
PORTA
—
—
RA5
RA4
RA3
85h
TRISA
—
—
09h
PORTE(2)
—
—
—
—
—
89h
TRISE(2)
IBF
OBF
IBOV
PSPMODE
—
Legend:
x = unknown, u = unchanged, - = unimplemented, read as ‘0’. Shaded cells are not used for A/D conversion.
PSPIE
—
CHS2
TMR2IE TMR1IE 0000 0000 0000 0000
—
CCP2IE ---- ---0 ---- ---0
—
ADON 0000 00-0 0000 00-0
PCFG2
PCFG1
PCFG0 ---- -000 ---- -000
RA2
RA1
xxxx xxxx uuuu uuuu
CHS1
CHS0 GO/DONE
RA0
PORTA Data Direction Register
--0x 0000 --0u 0000
--11 1111 --11 1111
RE2
RE1
RE0
PORTE Data Direction Bits
---- -xxx ---- -uuu
0000 -111 0000 -111
Note 1: Bits PSPIE and PSPIF are reserved on the PIC16CR73/76; always maintain these bits clear.
2: These registers are reserved on the PIC16CR73/76.
DS21993A-page 88
© 2006 Microchip Technology Inc.
PIC16CR7X
12.0
SPECIAL FEATURES OF THE
CPU
These devices have a host of features intended to maximize system reliability, minimize cost through elimination of external components, provide power saving
operating modes and offer code protection. These are:
• Oscillator Selection
• Reset
- Power-on Reset (POR)
- Power-up Timer (PWRT)
- Oscillator Start-up Timer (OST)
- Brown-out Reset (BOR)
• Interrupts
• Watchdog Timer (WDT)
• Sleep
• Code Protection
• ID Locations
• In-Circuit Serial Programming™
These devices have a Watchdog Timer, which can be
enabled or disabled, using a Configuration bit. It runs
off its own RC oscillator for added reliability.
Sleep mode is designed to offer a very low-current
power-down mode. The user can wake-up from Sleep
through external Reset, Watchdog Timer Wake-up or
through an interrupt.
Several oscillator options are also made available to
allow the part to fit the application. The RC oscillator
option saves system cost while the LP crystal option
saves power. Configuration bits are used to select the
desired oscillator mode.
Additional information on special features is available
in the “PICmicro® Mid-Range MCU Family Reference
Manual” (DS33023).
12.1
Configuration Bits
The Configuration bits can be programmed (read as
‘0’), or left unprogrammed (read as ‘1’), to select
various device configurations. These bits are mapped
in program memory location 2007h.
The user will note that address 2007h is beyond the
user program memory space, which can be accessed
only during programming.
There are two timers that offer necessary delays on
power-up. One is the Oscillator Start-up Timer (OST),
intended to keep the chip in Reset until the crystal oscillator is stable. The other is the Power-up Timer
(PWRT), which provides a fixed delay of 72 ms (nominal) on power-up only. It is designed to keep the part in
Reset while the power supply stabilizes, and is enabled
or disabled, using a Configuration bit. With these two
timers on-chip, most applications need no external
Reset circuitry.
© 2006 Microchip Technology Inc.
DS21993A-page 89
PIC16CR7X
REGISTER 12-1:
CONFIGURATION WORD: (ADDRESS 2007h(1))
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
bit 13
bit 7
R/P-1
U-0
R/P-1
R/P-1
R/P-1
R/P-1
R/P-1
BOREN
—
CP0
PWRTEN
WDTEN
FOSC1
FOSC0
bit 6
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 13-7
Unimplemented: Read as ‘1’
bit 6
BOREN: Brown-out Reset Enable bit
1 = BOR enabled
0 = BOR disabled
bit 5
Unimplemented: Read as ‘1’
bit 4
CP0: ROM Program Memory Code Protection bit
1 = Code protection off
0 = All memory locations code protected
bit 3
PWRTEN: Power-up Timer Enable bit
1 = PWRT disabled
0 = PWRT enabled
bit 2
WDTEN: Watchdog Timer Enable bit
1 = WDT enabled
0 = WDT disabled
bit 1-0
FOSC1:FOSC0: Oscillator Selection bits
11 = RC oscillator
10 = HS oscillator
01 = XT oscillator
00 = LP oscillator
Note 1:
x = Bit is
unknown
The erased (unprogrammed) value of the Configuration Word is 3FFFh.
DS21993A-page 90
© 2006 Microchip Technology Inc.
PIC16CR7X
12.2
FIGURE 12-2:
Oscillator Configurations
12.2.1
OSCILLATOR TYPES
The PIC16CR7X can be operated in four different oscillator modes. The user can program two Configuration
bits (FOSC1 and FOSC0) to select one of these four
modes:
•
•
•
•
EXTERNAL CLOCK INPUT
OPERATION (HS OSC
CONFIGURATION)
LP
XT
HS
RC
Low-Power Crystal
Crystal/Resonator
High-Speed Crystal/Resonator
Resistor/Capacitor
12.2.2
In XT, LP or HS modes, a crystal or ceramic resonator is
connected to the OSC1/CLKIN and OSC2/CLKOUT
pins to establish oscillation (Figure 12-1). The
PIC16CR7X oscillator design requires the use of a
parallel cut crystal. Use of a series cut crystal may give
a frequency out of the crystal manufacturers specifications. When in HS mode, the device can accept an
external clock source to drive the OSC1/CLKIN pin
(Figure 12-2). See Figure 15-1 or Figure 15-2
(depending on the part number and VDD range) for valid
external clock frequencies.
C1(1)
CRYSTAL/CERAMIC
RESONATOR OPERATION
(HS, XT OR LP
OSC CONFIGURATION)
OSC1
XTAL
OSC2
RS(2)
See Table 12-1 and Table 12-2
recommended values of C1 and C2.
OSC2
CERAMIC RESONATORS
(FOR DESIGN GUIDANCE
ONLY)
Typical Capacitor Values Used:
Mode
Freq.
OSC1
OSC2
XT
455 kHz
2.0 MHz
4.0 MHz
56 pF
47 pF
33 pF
56 pF
47 pF
33 pF
HS
8.0 MHz
16.0 MHz
27 pF
22 pF
27 pF
22 pF
Capacitor values are for design guidance only.
These capacitors were tested with the resonators
listed below for basic start-up and operation. These
values were not optimized.
Different capacitor values may be required to produce
acceptable oscillator operation. The user should test
the performance of the oscillator over the expected
VDD and temperature range for the application.
See the notes at the bottom of page 92 for additional
information.
Resonators Used:
for
2:
A series resistor (RS) may be required for
AT strip cut crystals.
3:
RF varies with the crystal chosen.
© 2006 Microchip Technology Inc.
TABLE 12-1:
SLEEP
PIC16CR7X
C2(1)
Note 1:
To
Internal
Logic
RF(3)
PIC16CR7X
(HS Mode)
Open
CRYSTAL OSCILLATOR/CERAMIC
RESONATORS
FIGURE 12-1:
OSC1
Clock from
Ext. System
455 kHz
Panasonic EFO-A455K04B
2.0 MHz
Murata Erie CSA2.00MG
4.0 MHz
Murata Erie CSA4.00MG
8.0 MHz
Murata Erie CSA8.00MT
16.0 MHz
Murata Erie CSA16.00MX
DS21993A-page 91
PIC16CR7X
TABLE 12-2:
Osc Type
LP
XT
HS
CAPACITOR SELECTION FOR
CRYSTAL OSCILLATOR
(FOR DESIGN GUIDANCE
ONLY)
Crystal
Freq.
Typical Capacitor Values
Tested:
C1
C2
32 kHz
33 pF
33 pF
200 kHz
15 pF
15 pF
200 kHz
56 pF
56 pF
1 MHz
15 pF
15 pF
4 MHz
15 pF
15 pF
4 MHz
15 pF
15 pF
8 MHz
15 pF
15 pF
20 MHz
15 pF
15 pF
Capacitor values are for design guidance only.
These capacitors were tested with the crystals listed
below for basic start-up and operation. These values
were not optimized.
Different capacitor values may be required to produce
acceptable oscillator operation. The user should test
the performance of the oscillator over the expected
VDD and temperature range for the application.
See the notes following this table for additional
information.
12.2.3
RC OSCILLATOR
For timing insensitive applications, the “RC” device
option offers additional cost savings. The RC oscillator
frequency is a function of the supply voltage, the resistor (REXT) and capacitor (CEXT) values, and the operating temperature. In addition to this, the oscillator
frequency will vary from unit to unit due to normal
process parameter variation. Furthermore, the difference in lead frame capacitance between package
types will also affect the oscillation frequency,
especially for low CEXT values. The user also needs to
take into account variation due to tolerance of external
R and C components used. Figure 12-3 shows how the
R/C combination is connected to the PIC16CR7X.
FIGURE 12-3:
RC OSCILLATOR MODE
VDD
REXT
OSC1
CEXT
Internal
Clock
PIC16CR7X
VSS
FOSC/4
Recommended values:
OSC2/CLKOUT
3 kΩ ≤ REXT ≤ 100 kΩ
CEXT > 20pF
Crystals Used:
32 kHz
Epson C-001R32.768K-A
200 kHz
STD XTL 200.000KHz
1 MHz
ECS ECS-10-13-1
4 MHz
ECS ECS-40-20-1
8 MHz
EPSON CA-301 8.000M-C
20 MHz
EPSON CA-301 20.000M-C
Note 1: Higher capacitance increases the stability
of oscillator, but also increases the startup time.
2: Since each resonator/crystal has its own
characteristics, the user should consult
the resonator/crystal manufacturer for
appropriate values of external components.
3: Rs may be required in HS mode, as well
as XT mode, to avoid overdriving crystals
with low drive level specification.
4: Always verify oscillator performance over
the VDD and temperature range that is
expected for the application.
DS21993A-page 92
© 2006 Microchip Technology Inc.
PIC16CR7X
12.3
Reset
The PIC16CR7X differentiates between various kinds
of Reset:
•
•
•
•
•
•
Power-on Reset (POR)
MCLR Reset during normal operation
MCLR Reset during Sleep
WDT Reset (during normal operation)
WDT Wake-up (during Sleep)
Brown-out Reset (BOR)
Some registers are not affected in any Reset condition.
Their status is unknown on POR and unchanged in any
other Reset. Most other registers are reset to a “Reset
state” on Power-on Reset (POR), on the MCLR and
WDT Reset, on MCLR Reset during Sleep, and Brownout Reset (BOR). They are not affected by a WDT
Wake-up, which is viewed as the resumption of normal
operation. The TO and PD bits are set or cleared differently in different Reset situations, as indicated in
Table 12-4. These bits are used in software to
determine the nature of the Reset. See Table 12-6 for
a full description of Reset states of all registers.
A simplified block diagram of the on-chip Reset circuit
is shown in Figure 12-4.
FIGURE 12-4:
SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT
External
Reset
MCLR
Sleep
WDT
WDT
Module
Time-out
Reset
VDD Rise
Detect
VDD
Power-on Reset
Brown-out
Reset
BODEN
S
OST/PWRT
OST
10-bit Ripple Counter
Chip_Reset
R
Q
OSC1
(1)
On-chip
RC OSC
PWRT
10-bit Ripple Counter
Enable PWRT
Enable OST
Note
1:
This is a separate oscillator from the RC oscillator of the CLKIN pin.
© 2006 Microchip Technology Inc.
DS21993A-page 93
PIC16CR7X
12.4
MCLR
12.6
PIC16CR7X devices have a noise filter in the MCLR
Reset path. The filter will detect and ignore small
pulses.
It should be noted that a WDT Reset does not drive
MCLR pin low.
The behavior of the ESD protection on the MCLR pin
has been altered from previous devices of this family.
Voltages applied to the pin that exceed its specification
can result in both MCLR Resets and excessive current
beyond the device specification during the ESD event.
For this reason, Microchip recommends that the MCLR
pin no longer be tied directly to VDD. The use of an RC
network, as shown in Figure 12-5, is suggested.
FIGURE 12-5:
RECOMMENDED MCLR
CIRCUIT
VDD
PIC16CR7X
R1
1 kΩ (or greater)
MCLR
C1
0.1 μF
(optional, not critical)
12.5
Power-on Reset (POR)
A Power-on Reset pulse is generated on-chip when
VDD rise is detected (in the range of 1.2V-1.7V). To take
advantage of the POR, tie the MCLR pin to VDD as
described in Section 12.4 “MCLR”. A maximum rise
time for VDD is specified. See the Electrical Specifications for details.
When the device starts normal operation (exits the
Reset condition), device operating parameters (voltage, frequency, temperature,...) must be met to ensure
operation. If these conditions are not met, the device
must be held in Reset until the operating conditions are
met. For additional information, refer to Application
Note AN607, “Power-up Trouble Shooting” (DS00607).
Power-up Timer (PWRT)
The Power-up Timer provides a fixed 72 ms nominal
time-out on power-up only from the POR. The Powerup Timer operates on an internal RC oscillator. The
chip is kept in Reset as long as the PWRT is active. The
PWRT’s time delay allows VDD to rise to an acceptable
level. A Configuration bit is provided to enable/disable
the PWRT.
The power-up time delay will vary from chip-to-chip,
due to VDD, temperature and process variation. See
DC parameters for details (TPWRT, parameter #33).
12.7
Oscillator Start-up Timer (OST)
The Oscillator Start-up Timer (OST) provides 1024 oscillator cycles (from OSC1 input) delay after the PWRT
delay is over (if enabled). This helps to ensure that the
crystal oscillator or resonator has started and stabilized.
The OST time-out is invoked only for XT, LP and HS
modes and only on Power-on Reset, or wake-up from
Sleep.
12.8
Brown-out Reset (BOR)
The Configuration bit, BODEN, can enable or disable
the Brown-out Reset circuit. If VDD falls below VBOR
(parameter D005, about 4V) for longer than TBOR
(parameter #35, about 100 μS), the brown-out situation
will reset the device. If VDD falls below VBOR for less
than TBOR, a Reset may not occur.
Once the brown-out occurs, the device will remain in
Brown-out Reset until VDD rises above VBOR. The
Power-up Timer then keeps the device in Reset for
TPWRT (parameter #33, about 72 mS). If VDD should fall
below VBOR during TPWRT, the Brown-out Reset process will restart when VDD rises above VBOR, with the
Power-up Timer Reset. The Power-up Timer is always
enabled when the Brown-out Reset circuit is enabled,
regardless of the state of the PWRT Configuration bit.
12.9
Time-out Sequence
On power-up, the time-out sequence is as follows: the
PWRT delay starts (if enabled) when a POR Reset
occurs. Then, OST starts counting 1024 oscillator
cycles when PWRT ends (LP, XT, HS). When the OST
ends, the device comes out of Reset.
If MCLR is kept low long enough, all delays will expire.
Bringing MCLR high will begin execution immediately.
This is useful for testing purposes or to synchronize
more than one PIC16CR7X device operating in
parallel.
Table 12-5 shows the Reset conditions for the
STATUS, PCON and PC registers, while Table 12-6
shows the Reset conditions for all the registers.
DS21993A-page 94
© 2006 Microchip Technology Inc.
PIC16CR7X
12.10 Power Control/Status Register
(PCON)
bit BOR cleared, indicating a Brown-out Reset
occurred. When the Brown-out Reset is disabled, the
state of the BOR bit is unpredictable.
The Power Control/Status Register, PCON, has two
bits to indicate the type of Reset that last occurred.
Bit 1 is POR (Power-on Reset Status bit). It is cleared
on a Power-on Reset and unaffected otherwise. The
user must set this bit following a Power-on Reset.
Bit 0 is Brown-out Reset Status bit, BOR. Bit BOR is
unknown on a Power-on Reset. It must then be set by
the user and checked on subsequent Resets to see if
TABLE 12-3:
TIME-OUT IN VARIOUS SITUATIONS
Power-up
Oscillator Configuration
Brown-out
Wake-up from
Sleep
PWRTE = 0
PWRTE = 1
XT, HS, LP
72 ms + 1024 TOSC
1024 TOSC
72 ms + 1024 TOSC
1024 TOSC
RC
72 ms
—
72 ms
—
TABLE 12-4:
STATUS BITS AND THEIR SIGNIFICANCE
POR
BOR
TO
PD
(PCON<1>) (PCON<0>) (STATUS<4>) (STATUS<3>)
Significance
0
x
1
1
Power-on Reset
0
x
0
x
Illegal, TO is set on POR
0
x
x
0
Illegal, PD is set on POR
1
0
1
1
Brown-out Reset
1
1
0
1
WDT Reset
1
1
0
0
WDT Wake-up
1
1
u
u
MCLR Reset during normal operation
1
1
1
0
MCLR Reset during Sleep or interrupt wake-up from
Sleep
TABLE 12-5:
RESET CONDITION FOR SPECIAL REGISTERS
Program
Counter
STATUS
Register
PCON
Register
Power-on Reset
000h
0001 1xxx
---- --0x
MCLR Reset during normal operation
000h
000u uuuu
---- --uu
0001
0000
uuu0
0001
-------------
Condition
MCLR Reset during Sleep
WDT Reset
WDT Wake-up
Brown-out Reset
000h
000h
PC + 1
000h
0uuu
1uuu
0uuu
1uuu
--uu
--uu
--uu
--u0
Interrupt wake-up from Sleep
PC + 1(1)
uuu1 0uuu
---- --uu
Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’
Note 1: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector
(0004h).
© 2006 Microchip Technology Inc.
DS21993A-page 95
PIC16CR7X
TABLE 12-6:
INITIALIZATION CONDITIONS FOR ALL REGISTERS
Register
Devices
Power-on Reset,
Brown-out Reset
MCLR Reset,
WDT Reset
Wake-up via WDT or
Interrupt
W
INDF
TMR0
73
73
73
74
74
74
76
76
76
77
77
77
xxxx xxxx
N/A
xxxx xxxx
uuuu uuuu
N/A
uuuu uuuu
uuuu uuuu
N/A
uuuu uuuu
PCL
73
74
76
77
0000h
0000h
PC + 1(2)
STATUS
FSR
PORTA
PORTB
PORTC
PORTD
PORTE
PCLATH
73
73
73
73
73
73
73
73
74
74
74
74
74
74
74
74
76
76
76
76
76
76
76
76
77
77
77
77
77
77
77
77
0001
xxxx
--0x
xxxx
xxxx
xxxx
------0
INTCON
73
74
76
77
0000 000x
0000 000u
uuuu uuuu(1)
PIR1
73
74
76
77
r000 0000
r000 0000
ruuu uuuu(1)
73
74
76
77
0000 0000
0000 0000
uuuu uuuu(1)
1xxx
xxxx
0000
xxxx
xxxx
xxxx
-xxx
0000
000q
uuuu
--0u
uuuu
uuuu
uuuu
------0
quuu(3)
uuuu
0000
uuuu
uuuu
uuuu
-uuu
0000
uuuq
uuuu
--uu
uuuu
uuuu
uuuu
------u
quuu(3)
uuuu
uuuu
uuuu
uuuu
uuuu
-uuu
uuuu
PIR2
73
74
76
77
---- ---0
---- ---0
---- ---u(1)
TMR1L
73
74
76
77
xxxx xxxx
uuuu uuuu
uuuu uuuu
TMR1H
73
74
76
77
xxxx xxxx
uuuu uuuu
uuuu uuuu
T1CON
73
74
76
77
--00 0000
--uu uuuu
--uu uuuu
TMR2
73
74
76
77
0000 0000
0000 0000
uuuu uuuu
T2CON
73
74
76
77
-000 0000
-000 0000
-uuu uuuu
SSPBUF
73
74
76
77
xxxx xxxx
uuuu uuuu
uuuu uuuu
SSPCON
73
74
76
77
0000 0000
0000 0000
uuuu uuuu
CCPR1L
73
74
76
77
xxxx xxxx
uuuu uuuu
uuuu uuuu
CCPR1H
73
74
76
77
xxxx xxxx
uuuu uuuu
uuuu uuuu
CCP1CON
73
74
76
77
--00 0000
--00 0000
--uu uuuu
RCSTA
73
74
76
77
0000 -00x
0000 -00x
uuuu -uuu
TXREG
73
74
76
77
0000 0000
0000 0000
uuuu uuuu
RCREG
73
74
76
77
0000 0000
0000 0000
uuuu uuuu
CCPR2L
73
74
76
77
xxxx xxxx
uuuu uuuu
uuuu uuuu
CCPR2H
73
74
76
77
xxxx xxxx
uuuu uuuu
uuuu uuuu
CCP2CON
73
74
76
77
0000 0000
0000 0000
uuuu uuuu
ADRES
73
74
76
77
xxxx xxxx
uuuu uuuu
uuuu uuuu
ADCON0
73
74
76
77
0000 00-0
0000 00-0
uuuu uu-u
OPTION_REG
73
74
76
77
1111 1111
1111 1111
uuuu uuuu
TRISA
73
74
76
77
--11 1111
--11 1111
--uu uuuu
TRISB
73
74
76
77
1111 1111
1111 1111
uuuu uuuu
TRISC
73
74
76
77
1111 1111
1111 1111
uuuu uuuu
TRISD
73
74
76
77
1111 1111
1111 1111
uuuu uuuu
TRISE
73
74
76
77
0000 -111
0000 -111
uuuu -uuu
Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition,
r = reserved, maintain clear
Note 1: One or more bits in INTCON, PIR1 and/or PIR2 will be affected (to cause wake-up).
2: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector
(0004h).
3: See Table 12-5 for Reset value for specific condition.
DS21993A-page 96
© 2006 Microchip Technology Inc.
PIC16CR7X
TABLE 12-6:
INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)
Register
Devices
PIE1
73
73
74
74
76
76
77
77
MCLR Reset,
WDT Reset
r000 0000
0000 0000
Power-on Reset,
Brown-out Reset
r000 0000
0000 0000
Wake-up via WDT or
Interrupt
ruuu uuuu
uuuu uuuu
PIE2
73
74
76
77
---- ---0
---- ---0
---- ---u
PCON
73
74
76
77
---- --qq
---- --uu
---- --uu
PR2
73
74
76
77
1111 1111
1111 1111
1111 1111
SSPSTAT
73
74
76
77
--00 0000
--00 0000
--uu uuuu
SSPADD
73
74
76
77
0000 0000
0000 0000
uuuu uuuu
TXSTA
73
74
76
77
0000 -010
0000 -010
uuuu -uuu
SPBRG
73
74
76
77
0000 0000
0000 0000
uuuu uuuu
ADCON1
73
74
76
77
---- -000
---- -000
---- -uuu
PMDATA
73
74
76
77
0--- 0000
0--- 0000
u--- uuuu
PMADR
73
74
76
77
xxxx xxxx
uuuu uuuu
uuuu uuuu
PMDATH
73
74
76
77
xxxx xxxx
uuuu uuuu
uuuu uuuu
PMADRH
73
74
76
77
xxxx xxxx
uuuu uuuu
uuuu uuuu
PMCON1
73
74
76
77
1--- ---0
1--- ---0
1--- ---u
Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition,
r = reserved, maintain clear
Note 1: One or more bits in INTCON, PIR1 and/or PIR2 will be affected (to cause wake-up).
2: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector
(0004h).
3: See Table 12-5 for Reset value for specific condition.
FIGURE 12-6:
TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD THROUGH
RC NETWORK)
VDD
MCLR
INTERNAL POR
TPWRT
PWRT TIME-OUT
TOST
OST TIME-OUT
INTERNAL RESET
© 2006 Microchip Technology Inc.
DS21993A-page 97
PIC16CR7X
FIGURE 12-7:
TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 1
VDD
MCLR
INTERNAL POR
TPWRT
PWRT TIME-OUT
TOST
OST TIME-OUT
INTERNAL RESET
TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 2
FIGURE 12-8:
VDD
MCLR
INTERNAL POR
TPWRT
PWRT TIME-OUT
TOST
OST TIME-OUT
INTERNAL RESET
FIGURE 12-9:
SLOW RISE TIME (MCLR TIED TO VDD THROUGH RC NETWORK)
5V
VDD
1V
0V
MCLR
INTERNAL POR
TPWRT
PWRT TIME-OUT
TOST
OST TIME-OUT
INTERNAL RESET
DS21993A-page 98
© 2006 Microchip Technology Inc.
PIC16CR7X
12.11 Interrupts
The RB0/INT pin interrupt, the RB port change interrupt
and the TMR0 overflow interrupt flags are contained in
the INTCON register.
The PIC16CR7X family has up to 12 sources of
interrupt. The Interrupt Control register (INTCON)
records individual interrupt requests in flag bits. It also
has individual and global interrupt enable bits.
Note:
The peripheral interrupt flags are contained in the
Special Function Registers, PIR1 and PIR2. The corresponding interrupt enable bits are contained in Special
Function Registers, PIE1 and PIE2, and the peripheral
interrupt enable bit is contained in Special Function
Register, INTCON.
Individual interrupt flag bits are set,
regardless of the status of their corresponding mask bit or the GIE bit.
A Global Interrupt Enable bit, GIE (INTCON<7>)
enables (if set) all unmasked interrupts, or disables (if
cleared) all interrupts. When bit GIE is enabled and an
interrupt’s flag bit and mask bit are set, the interrupt will
vector immediately. Individual interrupts can be disabled through their corresponding enable bits in various registers. Individual interrupt bits are set,
regardless of the status of the GIE bit. The GIE bit is
cleared on Reset.
When an interrupt is responded to, the GIE bit is
cleared to disable any further interrupt, the return
address is pushed onto the stack and the PC is loaded
with 0004h. Once in the Interrupt Service Routine, the
source(s) of the interrupt can be determined by polling
the interrupt flag bits. The interrupt flag bit(s) must be
cleared in software before re-enabling interrupts to
avoid recursive interrupts.
For external interrupt events, such as the INT pin or
PORTB change interrupt, the interrupt latency will be
three or four instruction cycles. The exact latency
depends when the interrupt event occurs, relative to
the current Q cycle. The latency is the same for one or
two-cycle instructions. Individual interrupt flag bits are
set, regardless of the status of their corresponding
mask bit, PEIE bit or the GIE bit.
The “return from interrupt” instruction, RETFIE, exits
the interrupt routine, as well as sets the GIE bit, which
re-enables interrupts.
FIGURE 12-10:
INTERRUPT LOGIC
PSPIF(1)
PSPIE(1)
ADIF
ADIE
TMR0IF
TMR0IE
RCIF
RCIE
INTF
INTE
TXIF
TXIE
SSPIF
SSPIE
CCP1IF
CCP1IE
Wake-up (If in Sleep mode)
Interrupt to CPU
RBIF
RBIE
PEIE
GIE
TMR2IF
TMR2IE
TMR1IF
TMR1IE
CCP2IF
CCP2IE
Note 1:
PSP interrupt is implemented only on PIC16CR74/77 devices.
© 2006 Microchip Technology Inc.
DS21993A-page 99
PIC16CR7X
12.11.1
INT INTERRUPT
12.12 Context Saving During Interrupts
External interrupt on the RB0/INT pin is edge triggered,
either rising, if bit INTEDG (OPTION_REG<6>) is set,
or falling, if the INTEDG bit is clear. When a valid edge
appears on the RB0/INT pin, flag bit INTF
(INTCON<1>) is set. This interrupt can be disabled by
clearing enable bit INTE (INTCON<4>). Flag bit INTF
must be cleared in software in the Interrupt Service
Routine before re-enabling this interrupt. The INT interrupt can wake-up the processor from Sleep, if bit INTE
was set prior to going into Sleep. The status of global
interrupt enable bit GIE decides whether or not the
processor branches to the interrupt vector following
wake-up. See Section 12.14 “Power-down Mode
(Sleep)” for details on Sleep mode.
12.11.2
TMR0 INTERRUPT
An overflow (FFh → 00h) in the TMR0 register will set
flag bit TMR0IF (INTCON<2>). The interrupt can be
enabled/disabled by setting/clearing enable bit TMR0IE
(INTCON<5>). (Section 5.0 “Timer0 Module”)
12.11.3
During an interrupt, only the return PC value is saved
on the stack. Typically, users may wish to save key
registers during an interrupt (i.e., W, PCLATH and
STATUS registers). This will have to be implemented in
software, as shown in Example 12-1.
For the PIC16CR73/74 devices, the register W_TEMP
must be defined in both banks 0 and 1 and must be
defined at the same offset from the bank base address
(i.e., If W_TEMP is defined at 20h in bank 0, it must
also be defined at A0h in bank 1.). The registers,
PCLATH_TEMP and STATUS_TEMP, are only defined
in bank 0.
Since the upper 16 bytes of each bank are common in
the PIC16CR76/77 devices, temporary holding registers W_TEMP, STATUS_TEMP and PCLATH_TEMP
should be placed in here. These 16 locations don’t
require banking and, therefore, make it easier for
context save and restore. The same code shown in
Example 12-1 can be used.
PORTB INTCON CHANGE
An input change on PORTB<7:4> sets flag bit RBIF
(INTCON<0>). The interrupt can be enabled/disabled
by setting/clearing enable bit RBIE (INTCON<3>), see
Section 4.2 “PORTB and the TRISB Register”.
EXAMPLE 12-1:
SAVING STATUS, W AND PCLATH REGISTERS IN RAM
MOVWF
SWAPF
CLRF
MOVWF
MOVF
MOVWF
CLRF
:
:(ISR)
:
MOVF
MOVWF
SWAPF
W_TEMP
STATUS,W
STATUS
STATUS_TEMP
PCLATH, W
PCLATH_TEMP
PCLATH
MOVWF
SWAPF
SWAPF
STATUS
W_TEMP,F
W_TEMP,W
;Copy
;Swap
;bank
;Save
;Only
;Save
;Page
W to TEMP register
status to be saved into W
0, regardless of current bank, Clears IRP,RP1,RP0
status to bank zero STATUS_TEMP register
required if using pages 1, 2 and/or 3
PCLATH into W
zero, regardless of current page
;Insert user code here
PCLATH_TEMP, W
PCLATH
STATUS_TEMP,W
DS21993A-page 100
;Restore PCLATH
;Move W into PCLATH
;Swap STATUS_TEMP register into W
;(sets bank to original state)
;Move W into STATUS register
;Swap W_TEMP
;Swap W_TEMP into W
© 2006 Microchip Technology Inc.
PIC16CR7X
12.13 Watchdog Timer (WDT)
The Watchdog Timer is a free running on-chip RC
oscillator, which does not require any external components. This RC oscillator is separate from the RC
oscillator of the OSC1/CLKIN pin. That means that the
WDT will run, even if the clock on the OSC1/CLKIN and
OSC2/CLKOUT pins of the device has been stopped,
for example, by execution of a SLEEP instruction.
WDT time-out period values may be found in the
Electrical Specifications section under parameter #31.
Values for the WDT prescaler (actually a postscaler, but
shared with the Timer0 prescaler), may be assigned
using the OPTION_REG register.
Note 1: The CLRWDT and SLEEP instructions
clear the WDT and the postscaler, if
assigned to the WDT, and prevent it from
timing out and generating a device Reset
condition.
During normal operation, a WDT time-out generates a
device Reset (Watchdog Timer Reset). If the device is
in Sleep mode, a WDT time-out causes the device to
wake-up and continue with normal operation (Watchdog Timer Wake-up). The TO bit in the STATUS register will be cleared upon a Watchdog Timer time-out.
2: When a CLRWDT instruction is executed
and the prescaler is assigned to the WDT,
the prescaler count will be cleared, but
the prescaler assignment is not changed.
The WDT can be permanently disabled by clearing
Configuration bit, WDTE (Section 12.1 “Configuration
Bits”).
FIGURE 12-11:
WATCHDOG TIMER BLOCK DIAGRAM
From TMR0 Clock Source
(Figure 5-1)
0
1
WDT Timer
Postscaler
M
U
X
8
8-to-1 MUX
PS2:PS0
PSA
WDT
Enable Bit
To TMR0 (Figure 5-1)
0
1
MUX
PSA
WDT
Time-out
Note: PSA and PS2:PS0 are bits in the OPTION_REG register.
TABLE 12-7:
Address
2007h
SUMMARY OF WATCHDOG TIMER REGISTERS
Name
Bit 7
Bit 6
Bit 5
Bit 4
(1)
BOREN(1)
—
CP0
RBPU
INTEDG
T0CS
T0SE
Config. bits
81h,181h OPTION_REG
Bit 3
Bit 2
PWRTEN(1) WDTEN
PSA
PS2
Bit 1
Bit 0
FOSC1
FOSC0
PS1
PS0
Legend: Shaded cells are not used by the Watchdog Timer.
Note 1: See Register 12-1 for operation of these bits.
© 2006 Microchip Technology Inc.
DS21993A-page 101
PIC16CR7X
12.14 Power-down Mode (Sleep)
Power-down mode is entered by executing a SLEEP
instruction.
If enabled, the Watchdog Timer will be cleared but
keeps running, the PD bit (STATUS<3>) is cleared, the
TO (STATUS<4>) bit is set, and the oscillator driver is
turned off. The I/O ports maintain the status they had
before the SLEEP instruction was executed (driving
high, low, or high-impendance).
For lowest current consumption in this mode, place all
I/O pins at either VDD or VSS, ensure no external circuitry is drawing current from the I/O pin, power-down
the A/D and disable external clocks. Pull all I/O pins
that are high-impendance inputs, high or low externally,
to avoid switching currents caused by floating inputs.
The T0CKI input should also be at VDD or VSS for lowest current consumption. The contribution from on-chip
pull-ups on PORTB should also be considered.
The MCLR pin must be at a logic high level (VIHMC).
12.14.1
WAKE-UP FROM SLEEP
The device can wake-up from Sleep through one of the
following events:
1.
2.
3.
External Reset input on MCLR pin.
Watchdog Timer wake-up (if WDT was
enabled).
Interrupt from INT pin, RB port change or a
Peripheral Interrupt.
External MCLR Reset will cause a device Reset. All
other events are considered a continuation of program
execution and cause a “wake-up”. The TO and PD bits
in the STATUS register can be used to determine the
cause of device Reset. The PD bit, which is set on
power-up, is cleared when Sleep is invoked. The TO bit
is cleared if a WDT time-out occurred and caused
wake-up.
When the SLEEP instruction is being executed, the next
instruction (PC + 1) is pre-fetched. For the device to
wake-up through an interrupt event, the corresponding
interrupt enable bit must be set (enabled). Wake-up
occurs, regardless of the state of the GIE bit. If the GIE
bit is clear (disabled), the device continues execution at
the instruction after the SLEEP instruction. If the GIE bit
is set (enabled), the device executes the instruction
after the SLEEP instruction and then branches to the
interrupt address (0004h). In cases where the execution of the instruction following SLEEP is not desirable,
the user should have a NOP after the SLEEP instruction.
12.14.2
WAKE-UP USING INTERRUPTS
When global interrupts are disabled (GIE cleared) and
any interrupt source has both its interrupt enable bit
and interrupt flag bit set, one of the following will occur:
• If the interrupt occurs before the execution of a
SLEEP instruction, the SLEEP instruction will
complete as a NOP. Therefore, the WDT and WDT
postscaler will not be cleared, the TO bit will not
be set and PD bits will not be cleared.
• If the interrupt occurs during or after the execution of a SLEEP instruction, the device will immediately wake-up from Sleep. The SLEEP
instruction will be completely executed before the
wake-up. Therefore, the WDT and WDT
postscaler will be cleared, the TO bit will be set
and the PD bit will be cleared.
Even if the flag bits were checked before executing a
SLEEP instruction, it may be possible for flag bits to
become set before the SLEEP instruction completes. To
determine whether a SLEEP instruction executed, test
the PD bit. If the PD bit is set, the SLEEP instruction
was executed as a NOP.
To ensure that the WDT is cleared, a CLRWDT instruction
should be executed before a SLEEP instruction.
The following peripheral interrupts can wake the device
from Sleep:
1.
2.
3.
4.
5.
6.
7.
8.
PSP read or write (PIC16CR74/77 only).
TMR1 interrupt. Timer1 must be operating as an
asynchronous counter.
CCP Capture mode interrupt.
Special event trigger (Timer1 in Asynchronous
mode, using an external clock).
SSP (Start/Stop) bit detect interrupt.
SSP transmit or receive in Slave mode
(SPI/I2C).
USART RX or TX (Synchronous Slave mode).
A/D conversion (when A/D clock source is RC).
Other peripherals cannot generate interrupts, since
during Sleep, no on-chip clocks are present.
DS21993A-page 102
© 2006 Microchip Technology Inc.
PIC16CR7X
FIGURE 12-12:
WAKE-UP FROM SLEEP THROUGH INTERRUPT
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
OSC1
TOST(2)
CLKOUT(4)
INT pin
INTF Flag
(INTCON<1>)
Interrupt Latency
(Note 2)
GIE bit
(INTCON<7>)
Processor in
Sleep
INSTRUCTION FLOW
PC
Instruction
Fetched
Instruction
Executed
Note
1:
2:
3:
4:
PC
Inst(PC) = Sleep
Inst(PC - 1)
PC + 1
PC + 2
PC + 2
Inst(PC + 1)
Inst(PC + 2)
Sleep
Inst(PC + 1)
PC + 2
Dummy cycle
0004h
0005h
Inst(0004h)
Inst(0005h)
Dummy cycle
Inst(0004h)
XT, HS or LP oscillator mode assumed.
TOST = 1024 TOSC (drawing not to scale) This delay will not be there for RC osc mode.
GIE = ‘1’ assumed. In this case, after wake-up, the processor jumps to the interrupt routine.
If GIE = ‘0’, execution will continue in-line.
CLKOUT is not available in these osc modes, but shown here for timing reference.
12.15 Program Verification/Code
Protection
If the code protection bit(s) have not been enabled, the
on-chip program memory can be read out for verification
purposes.
12.16 ID Locations
Four memory locations (2000h-2002h) are designated
as ID locations, where the user can store checksum or
other code identification numbers. These locations are
not accessible during normal execution, but are readable for program verification. It is recommended that
only the 4 Least Significant bits of the ID location are
used.
12.17 User Code
PIC16CR7X microcontrollers are ROM-based, thus
user programming is not possible. Please contact your
Microchip sales representitive for details on how to
submit your final code. This information can also be
found in Application Note AN1010, “PIC16CR ROM
Code Submission Process”.
© 2006 Microchip Technology Inc.
DS21993A-page 103
PIC16CR7X
NOTES:
DS21993A-page 104
© 2006 Microchip Technology Inc.
PIC16CR7X
13.0
INSTRUCTION SET SUMMARY
The PIC16 instruction set is highly orthogonal and is
comprised of three basic categories:
• Byte-oriented operations
• Bit-oriented operations
• Literal and control operations
Each PIC16 instruction is a 14-bit word divided into an
opcode, which specifies the instruction type and one or
more operands, which further specify the operation of
the instruction. The formats for each of the categories
are presented in Figure 13-1, while the various opcode
fields are summarized in Table 13-1.
Table 13-2 lists the instructions recognized by the
MPASMTM Assembler. A complete description of each
instruction is also available in the “PICmicro® MidRange MCU Family Reference Manual” (DS33023).
For byte-oriented instructions, ‘f’ represents a file
register designator and ‘d’ represents a destination
designator. The file register designator specifies which
file register is to be used by the instruction.
The destination designator specifies where the result of
the operation is to be placed. If ‘d’ is zero, the result is
placed in the W register. If ‘d’ is one, the result is placed
in the file register specified in the instruction.
For bit-oriented instructions, ‘b’ represents a bit field
designator, which selects the bit affected by the operation, while ‘f’ represents the address of the file in which
the bit is located.
For literal and control operations, ‘k’ represents an
eight- or eleven-bit constant or literal value.
One instruction cycle consists of four oscillator periods;
for an oscillator frequency of 4 MHz, this gives a normal
instruction execution time of 1 μs. All instructions are
executed within a single instruction cycle, unless a
conditional test is true, or the program counter is
changed as a result of an instruction. When this occurs,
the execution takes two instruction cycles, with the
second cycle executed as a NOP.
Note:
To maintain upward compatibility with
future PIC16CR7X products, do not use
the OPTION and TRIS instructions.
All instruction examples use the format ‘0xhh’ to
represent a hexadecimal number, where ‘h’ signifies a
hexadecimal digit.
13.1
For example, a “CLRF PORTB” instruction will read
PORTB, clear all the data bits, then write the result
back to PORTB. This example would have the unintended result that the condition that sets the RBIF flag
would be cleared for pins configured as inputs and
using the PORTB interrupt-on-change feature.
TABLE 13-1:
Field
Description
f
Register file address (0x00 to 0x7F)
W
Working register (accumulator)
b
Bit address within an 8-bit file register
k
Literal field, constant data or label
x
Don’t care location (= 0 or 1).
The assembler will generate code with x = 0.
It is the recommended form of use for
compatibility with all Microchip software tools.
d
Destination select; d = 0: store result in W,
d = 1: store result in file register f.
Default is d = 1.
PC
Program Counter
TO
Time-out bit
PD
Power-down bit
FIGURE 13-1:
© 2006 Microchip Technology Inc.
GENERAL FORMAT FOR
INSTRUCTIONS
Byte-oriented file register operations
13
8 7 6
OPCODE
d
f (FILE #)
0
d = 0 for destination W
d = 1 for destination f
f = 7-bit file register address
Bit-oriented file register operations
13
10 9
7 6
OPCODE
b (BIT #)
f (FILE #)
0
b = 3-bit bit address
f = 7-bit file register address
Literal and control operations
General
13
8
7
OPCODE
0
k (literal)
k = 8-bit immediate value
Read-Modify-Write operations
Any instruction that specifies a file register as part of
the instruction performs a Read-Modify-Write (R-M-W)
operation. The register is read, the data is modified,
and the result is stored according to either the instruction, or the destination designator ‘d’. A read operation
is performed on a register even if the instruction writes
to that register.
OPCODE FIELD
DESCRIPTIONS
CALL and GOTO instructions only
13
11
OPCODE
10
0
k (literal)
k = 11-bit immediate value
DS21993A-page 105
PIC16CR7X
TABLE 13-2:
PIC16CR7X INSTRUCTION SET
Mnemonic,
Operands
14-Bit Opcode
Description
Cycles
MSb
LSb
Status
Affected
Notes
BYTE-ORIENTED FILE REGISTER OPERATIONS
ADDWF
ANDWF
CLRF
CLRW
COMF
DECF
DECFSZ
INCF
INCFSZ
IORWF
MOVF
MOVWF
NOP
RLF
RRF
SUBWF
SWAPF
XORWF
f, d
f, d
f
—
f, d
f, d
f, d
f, d
f, d
f, d
f, d
f
—
f, d
f, d
f, d
f, d
f, d
Add W and f
AND W with f
Clear f
Clear W
Complement f
Decrement f
Decrement f, Skip if 0
Increment f
Increment f, Skip if 0
Inclusive OR W with f
Move f
Move W to f
No Operation
Rotate Left f through Carry
Rotate Right f through Carry
Subtract W from f
Swap nibbles in f
Exclusive OR W with f
BCF
BSF
BTFSC
BTFSS
f, b
f, b
f, b
f, b
Bit Clear f
Bit Set f
Bit Test f, Skip if Clear
Bit Test f, Skip if Set
ADDLW
ANDLW
CALL
CLRWDT
GOTO
IORLW
MOVLW
RETFIE
RETLW
RETURN
SLEEP
SUBLW
XORLW
k
k
k
—
k
k
k
—
k
—
—
k
k
Add literal and W
AND literal with W
Call subroutine
Clear Watchdog Timer
Go to address
Inclusive OR literal with W
Move literal to W
Return from interrupt
Return with literal in W
Return from Subroutine
Go into Standby mode
Subtract W from literal
Exclusive OR literal with W
1
1
1
1
1
1
1(2)
1
1(2)
1
1
1
1
1
1
1
1
1
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
dfff
dfff
lfff
0xxx
dfff
dfff
dfff
dfff
dfff
dfff
dfff
lfff
0xx0
dfff
dfff
dfff
dfff
dfff
ffff
ffff
ffff
xxxx
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
0000
ffff
ffff
ffff
ffff
ffff
00bb
01bb
10bb
11bb
bfff
bfff
bfff
bfff
ffff
ffff
ffff
ffff
111x
1001
0kkk
0000
1kkk
1000
00xx
0000
01xx
0000
0000
110x
1010
kkkk
kkkk
kkkk
0110
kkkk
kkkk
kkkk
0000
kkkk
0000
0110
kkkk
kkkk
kkkk
kkkk
kkkk
0100
kkkk
kkkk
kkkk
1001
kkkk
1000
0011
kkkk
kkkk
0111
0101
0001
0001
1001
0011
1011
1010
1111
0100
1000
0000
0000
1101
1100
0010
1110
0110
C,DC,Z
Z
Z
Z
Z
Z
Z
Z
Z
C
C
C,DC,Z
Z
1,2
1,2
2
1,2
1,2
1,2,3
1,2
1,2,3
1,2
1,2
1,2
1,2
1,2
1,2
1,2
BIT-ORIENTED FILE REGISTER OPERATIONS
1
1
1 (2)
1 (2)
01
01
01
01
1,2
1,2
3
3
LITERAL AND CONTROL OPERATIONS
1
1
2
1
2
1
1
2
2
2
1
1
1
11
11
10
00
10
11
11
00
11
00
00
11
11
C,DC,Z
Z
TO,PD
Z
TO,PD
C,DC,Z
Z
Note 1: When an I/O register is modified as a function of itself ( e.g., MOVF PORTB, 1), the value used will be that value present
on the pins themselves. For example, if the data latch is ‘1’ for a pin configured as input and is driven low by an external
device, the data will be written back with a ‘0’.
2: If this instruction is executed on the TMR0 register (and, where applicable, d = 1), the prescaler will be cleared if
assigned to the Timer0 module.
3: If Program Counter (PC) is modified, or a conditional test is true, the instruction requires two cycles. The second cycle is
executed as a NOP.
Note:
Additional information on the mid-range instruction set is available in the “PICmicro® Mid-Range MCU
Family Reference Manual” (DS33023).
DS21993A-page 106
© 2006 Microchip Technology Inc.
PIC16CR7X
13.2
Instruction Descriptions
ADDLW
Add Literal and W
BCF
Bit Clear f
Syntax:
[ label ] ADDLW
Syntax:
[ label ] BCF
Operands:
0 ≤ k ≤ 255
Operands:
0 ≤ f ≤ 127
0≤b≤7
Operation:
(W) + k → (W)
Status Affected:
C, DC, Z
Operation:
0 → (f<b>)
Description:
The contents of the W register
are added to the eight-bit literal ‘k’
and the result is placed in the W
register.
Status Affected:
None
Description:
Bit ‘b’ in register ‘f’ is cleared.
ADDWF
Add W and f
BSF
Bit Set f
Syntax:
[ label ] ADDWF
Syntax:
[ label ] BSF
Operands:
0 ≤ f ≤ 127
d ∈ [0,1]
Operands:
0 ≤ f ≤ 127
0≤b≤7
Operation:
(W) + (f) → (destination)
Operation:
1 → (f<b>)
Status Affected:
C, DC, Z
Status Affected:
None
Description:
Add the contents of the W register
with register ‘f’. If ‘d’ is ‘0’, the
result is stored in the W register. If
‘d’ is 1, the result is stored back in
register ‘f’.
Description:
Bit ‘b’ in register ‘f’ is set.
ANDLW
AND Literal with W
BTFSS
Bit Test f, Skip if Set
Syntax:
[ label ] ANDLW
Syntax:
[ label ] BTFSS f,b
Operands:
0 ≤ k ≤ 255
Operands:
Operation:
(W) .AND. (k) → (W)
0 ≤ f ≤ 127
0≤b<7
Status Affected:
Z
Operation:
skip if (f<b>) = 1
Description:
The contents of W register are
AND’ed with the eight-bit literal
‘k’. The result is placed in the W
register.
Status Affected:
None
Description:
If bit ‘b’ in register ‘f’ is ‘0’, the next
instruction is executed.
If bit ‘b’ is ‘1’, then the next instruction is discarded and a NOP is
executed instead, making this a
2TCY instruction.
BTFSC
Bit Test f, Skip if Clear
Syntax:
[ label ] BTFSC f,b
k
f,d
k
f,b
f,b
ANDWF
AND W with f
Syntax:
[ label ] ANDWF
Operands:
0 ≤ f ≤ 127
d ∈ [0,1]
Operands:
0 ≤ f ≤ 127
0≤b≤7
Operation:
(W) .AND. (f) → (destination)
Operation:
skip if (f<b>) = 0
Status Affected:
Z
Status Affected:
None
Description:
AND the W register with register
‘f’. If ‘d’ is ‘0’, the result is stored in
the W register. If ‘d’ is ‘1’, the
result is stored back in register ‘f’.
Description:
If bit ‘b’ in register ‘f’ is ‘1’, the next
instruction is executed.
If bit ‘b’ in register ‘f’ is ‘0’, the next
instruction is discarded and a NOP
is executed instead, making this a
2TCY instruction.
© 2006 Microchip Technology Inc.
f,d
DS21993A-page 107
PIC16CR7X
CALL
Call Subroutine
CLRWDT
Clear Watchdog Timer
Syntax:
[ label ] CALL k
Syntax:
[ label ] CLRWDT
Operands:
0 ≤ k ≤ 2047
Operands:
None
Operation:
(PC)+ 1→ TOS,
k → PC<10:0>,
(PCLATH<4:3>) → PC<12:11>
Operation:
Status Affected:
None
00h → WDT
0 → WDT prescaler,
1 → TO
1 → PD
Description:
Call Subroutine. First, return
address (PC + 1) is pushed onto
the stack. The eleven-bit immediate address is loaded into PC bits
<10:0>. The upper bits of the PC
are loaded from PCLATH. CALL is
a two-cycle instruction.
Status Affected:
TO, PD
Description:
CLRWDT instruction resets the
Watchdog Timer. It also resets the
prescaler of the WDT. Status bits
TO and PD are set.
Clear f
COMF
Complement f
CLRF
Syntax:
[ label ] CLRF
Syntax:
[ label ] COMF
Operands:
0 ≤ f ≤ 127
Operands:
Operation:
00h → (f)
1→Z
0 ≤ f ≤ 127
d ∈ [0,1]
Operation:
(f) → (destination)
Status Affected:
Z
Status Affected:
Z
Description:
The contents of register ‘f’ are
cleared and the Z bit is set.
Description:
The contents of register ‘f’ are
complemented. If ‘d’ is ‘0’, the
result is stored in W. If ‘d’ is ‘1’,
the result is stored back in
register ‘f’.
CLRW
Clear W
Syntax:
[ label ] CLRW
DECF
Decrement f
Operands:
None
Syntax:
[ label ] DECF f,d
Operation:
00h → (W)
1→Z
Operands:
0 ≤ f ≤ 127
d ∈ [0,1]
Status Affected:
Z
Operation:
(f) - 1 → (destination)
W register is cleared. Zero bit (Z)
is set.
Status Affected:
Z
Description:
Decrement register ‘f’. If ‘d’ is ‘0’,
the result is stored in the W
register. If ‘d’ is ‘1’, the result is
stored back in register ‘f’.
Description:
DS21993A-page 108
f
f,d
© 2006 Microchip Technology Inc.
PIC16CR7X
DECFSZ
Decrement f, Skip if 0
INCFSZ
Increment f, Skip if 0
Syntax:
[ label ] DECFSZ f,d
Syntax:
[ label ]
Operands:
0 ≤ f ≤ 127
d ∈ [0,1]
Operands:
0 ≤ f ≤ 127
d ∈ [0,1]
Operation:
(f) - 1 → (destination);
skip if result = 0
Operation:
(f) + 1 → (destination),
skip if result = 0
Status Affected:
None
Status Affected:
None
Description:
The contents of register ‘f’ are
decremented. If ‘d’ is ‘0’, the result
is placed in the W register. If ‘d’ is
‘1’, the result is placed back in
register ‘f’.
If the result is ‘1’, the next instruction is executed. If the result is ‘0’,
then a NOP is executed instead,
making it a 2TCY instruction.
Description:
The contents of register ‘f’ are
incremented. If ‘d’ is ‘0’, the result
is placed in the W register. If ‘d’ is
‘1’, the result is placed back in
register ‘f’.
If the result is ‘1’, the next instruction is executed. If the result is ‘0’,
a NOP is executed instead, making
it a 2TCY instruction.
GOTO
Unconditional Branch
IORLW
Inclusive OR Literal with W
Syntax:
[ label ]
Syntax:
[ label ]
Operands:
0 ≤ k ≤ 2047
Operands:
0 ≤ k ≤ 255
Operation:
k → PC<10:0>
PCLATH<4:3> → PC<12:11>
Operation:
(W) .OR. k → (W)
Status Affected:
Z
Status Affected:
None
Description:
Description:
GOTO is an unconditional branch.
The eleven-bit immediate value is
loaded into PC bits <10:0>. The
upper bits of PC are loaded from
PCLATH<4:3>. GOTO is a twocycle instruction.
The contents of the W register are
OR’ed with the eight-bit literal ‘k’.
The result is placed in the W
register.
INCF
Increment f
IORWF
Inclusive OR W with f
Syntax:
[ label ]
Syntax:
[ label ]
Operands:
0 ≤ f ≤ 127
d ∈ [0,1]
Operands:
0 ≤ f ≤ 127
d ∈ [0,1]
Operation:
(f) + 1 → (destination)
Operation:
(W) .OR. (f) → (destination)
Status Affected:
Z
Status Affected:
Z
Description:
The contents of register ‘f’ are
incremented. If ‘d’ is ‘0’, the result
is placed in the W register. If ‘d’ is
‘1’, the result is placed back in
register ‘f’.
Description:
Inclusive OR the W register with
register ‘f’. If ‘d’ is ‘0’, the result is
placed in the W register. If ‘d’ is
‘1’, the result is placed back in
register ‘f’.
GOTO k
INCF f,d
© 2006 Microchip Technology Inc.
INCFSZ f,d
IORLW k
IORWF
f,d
DS21993A-page 109
PIC16CR7X
MOVF
Move f
Syntax:
[ label ]
Operands:
0 ≤ f ≤ 127
d ∈ [0,1]
Operation:
(f) → (destination)
Status Affected: None
Status Affected:
Z
Description:
No operation.
Description:
The contents of register ‘f’ are
moved to a destination dependant
upon the status of ‘d’. If ‘d’ = 0,
destination is W register. If ‘d’ = 1,
the destination is file register ‘f’
itself. ‘d’ = 1 is useful to test a file
register, since status flag Z is
affected.
MOVLW
Move Literal to W
RETFIE
Return from Interrupt
Syntax:
[ label ]
Syntax:
[ label ] RETFIE
Operands:
0 ≤ k ≤ 255
Operands:
None
Operation:
k → (W)
Operation:
TOS → PC,
1 → GIE
MOVF f,d
MOVLW k
Status Affected:
None
Description:
The eight-bit literal ‘k’ is loaded
into W register. The “don’t cares”
will assemble as ‘0’s.
NOP
No Operation
Syntax:
[ label ] NOP
Operands:
None
Operation:
No operation
Status Affected: None
MOVWF
Move W to f
RETLW
Return with Literal in W
Syntax:
[ label ] MOVWF f
Syntax:
[ label ] RETLW k
Operands:
0 ≤ f ≤ 127
Operands:
0 ≤ k ≤ 255
Operation:
(W) → (f)
Operation:
Status Affected:
None
k → (W);
TOS → PC
Description:
Move data from W register to
register ‘f’.
DS21993A-page 110
Status Affected: None
Description:
Subtract (2’s complement method)
W register from register ‘f’. If ‘d’ is
‘0’, the result is stored in the W
register. If ‘d’ is ‘1’, the result is
stored back in register ‘f’.
© 2006 Microchip Technology Inc.
PIC16CR7X
RLF
Rotate Left f through Carry
SLEEP
Syntax:
[ label ] RLF
Syntax:
[ label ] SLEEP
Operands:
0 ≤ f ≤ 127
d ∈ [0,1]
Operands:
None
Operation:
Operation:
See description below
Status Affected:
C
Description:
The contents of register ‘f’ are rotated
one bit to the left through the Carry
Flag. If ‘d’ is ‘0’, the result is placed in
the W register. If ‘d’ is ‘1’, the result is
stored back in register ‘f’.
00h → WDT,
0 → WDT prescaler,
1 → TO,
0 → PD
Status Affected:
TO, PD
Description:
The power-down Status bit PD is
cleared. Time-out Status bit TO is
set. Watchdog Timer and its
prescaler are cleared.
The processor is put into Sleep
mode with the oscillator stopped.
C
f,d
Register f
RETURN
Return from Subroutine
SUBLW
Subtract W from Literal
Syntax:
[ label ]
Syntax:
[ label ] SUBLW k
Operands:
None
Operands:
0 ≤ k ≤ 255
Operation:
TOS → PC
Operation:
k - (W) → (W)
Status Affected:
None
Status Affected: C, DC, Z
Description:
Return from subroutine. The stack
is POPed and the top of the stack
(TOS) is loaded into the program
counter. This is a two-cycle
instruction.
Description:
The W register is subtracted (2’s
complement method) from the
eight-bit literal ‘k’. The result is
placed in the W register.
RRF
Rotate Right f through Carry
SUBWF
Subtract W from f
Syntax:
[ label ]
Syntax:
[ label ] SUBWF f,d
Operands:
0 ≤ f ≤ 127
d ∈ [0,1]
Operands:
0 ≤ f ≤ 127
d ∈ [0,1]
Operation:
See description below
Operation:
(f) - (W) → (destination)
Status Affected:
C
Status Affected: C, DC, Z
Description:
The contents of register ‘f’ are
rotated one bit to the right through
the Carry Flag. If ‘d’ is ‘0’, the
result is placed in the W register.
If ‘d’ is ‘1’, the result is placed
back in register ‘f’.
Description:
RETURN
RRF f,d
C
© 2006 Microchip Technology Inc.
Subtract (2’s complement method)
W register from register ‘f’. If ‘d’ is
‘0’, the result is stored in the W
register. If ‘d’ is ‘1’, the result is
stored back in register ‘f’.
Register f
DS21993A-page 111
PIC16CR7X
SWAPF
Swap Nibbles in f
XORWF
Exclusive OR W with f
Syntax:
[ label ] SWAPF f,d
Syntax:
[ label ] XORWF
Operands:
0 ≤ f ≤ 127
d ∈ [0,1]
Operands:
0 ≤ f ≤ 127
d ∈ [0,1]
Operation:
(f<3:0>) → (destination<7:4>),
(f<7:4>) → (destination<3:0>)
Operation:
(W) .XOR. (f) → (destination)
Status Affected:
Z
Status Affected:
None
Description:
Description:
The upper and lower nibbles of
register ‘f’ are exchanged. If ‘d’ is
‘0’, the result is placed in the W
register. If ‘d’ is ‘1’, the result is
placed in register ‘f’.
Exclusive OR the contents of the
W register with register ‘f’. If ‘d’ is
‘0’, the result is stored in the W
register. If ‘d’ is ‘1’, the result is
stored back in register ‘f’.
XORLW
Exclusive OR Literal with W
Syntax:
[ label ] XORLW k
Operands:
0 ≤ k ≤ 255
Operation:
(W) .XOR. k → (W)
Status Affected:
Z
Description:
The contents of the W register
are XOR’ed with the eight-bit
literal ‘k’. The result is placed in
the W register.
DS21993A-page 112
f,d
© 2006 Microchip Technology Inc.
PIC16CR7X
14.0
DEVELOPMENT SUPPORT
The PICmicro® microcontrollers are supported with a
full range of hardware and software development tools:
• Integrated Development Environment
- MPLAB® IDE Software
• Assemblers/Compilers/Linkers
- MPASMTM Assembler
- MPLAB C18 and MPLAB C30 C Compilers
- MPLINKTM Object Linker/
MPLIBTM Object Librarian
- MPLAB ASM30 Assembler/Linker/Library
• Simulators
- MPLAB SIM Software Simulator
• Emulators
- MPLAB ICE 2000 In-Circuit Emulator
- MPLAB ICE 4000 In-Circuit Emulator
• In-Circuit Debugger
- MPLAB ICD 2
• Device Programmers
- PICSTART® Plus Development Programmer
- MPLAB PM3 Device Programmer
- PICkit™ 2 Development Programmer
• Low-Cost Demonstration and Development
Boards and Evaluation Kits
14.1
MPLAB Integrated Development
Environment Software
The MPLAB IDE software brings an ease of software
development previously unseen in the 8/16-bit microcontroller market. The MPLAB IDE is a Windows®
operating system-based application that contains:
• A single graphical interface to all debugging tools
- Simulator
- Programmer (sold separately)
- Emulator (sold separately)
- In-Circuit Debugger (sold separately)
• A full-featured editor with color-coded context
• A multiple project manager
• Customizable data windows with direct edit of
contents
• High-level source code debugging
• Visual device initializer for easy register
initialization
• Mouse over variable inspection
• Drag and drop variables from source to watch
windows
• Extensive on-line help
• Integration of select third party tools, such as
HI-TECH Software C Compilers and IAR
C Compilers
The MPLAB IDE allows you to:
• Edit your source files (either assembly or C)
• One touch assemble (or compile) and download
to PICmicro MCU emulator and simulator tools
(automatically updates all project information)
• Debug using:
- Source files (assembly or C)
- Mixed assembly and C
- Machine code
MPLAB IDE supports multiple debugging tools in a
single development paradigm, from the cost-effective
simulators, through low-cost in-circuit debuggers, to
full-featured emulators. This eliminates the learning
curve when upgrading to tools with increased flexibility
and power.
© 2006 Microchip Technology Inc.
DS21993A-page 113
PIC16CR7X
14.2
MPASM Assembler
The MPASM Assembler is a full-featured, universal
macro assembler for all PICmicro MCUs.
The MPASM Assembler generates relocatable object
files for the MPLINK Object Linker, Intel® standard HEX
files, MAP files to detail memory usage and symbol
reference, absolute LST files that contain source lines
and generated machine code and COFF files for
debugging.
The MPASM Assembler features include:
• Integration into MPLAB IDE projects
• User-defined macros to streamline
assembly code
• Conditional assembly for multi-purpose
source files
• Directives that allow complete control over the
assembly process
14.5
MPLAB ASM30 Assembler produces relocatable
machine code from symbolic assembly language for
dsPIC30F devices. MPLAB C30 C Compiler uses the
assembler to produce its object file. The assembler
generates relocatable object files that can then be
archived or linked with other relocatable object files and
archives to create an executable file. Notable features
of the assembler include:
•
•
•
•
•
•
Support for the entire dsPIC30F instruction set
Support for fixed-point and floating-point data
Command line interface
Rich directive set
Flexible macro language
MPLAB IDE compatibility
14.6
14.3
MPLAB C18 and MPLAB C30
C Compilers
The MPLAB C18 and MPLAB C30 Code Development
Systems are complete ANSI C compilers for
Microchip’s PIC18 family of microcontrollers and the
dsPIC30, dsPIC33 and PIC24 family of digital signal
controllers. These compilers provide powerful integration capabilities, superior code optimization and ease
of use not found with other compilers.
For easy source level debugging, the compilers provide
symbol information that is optimized to the MPLAB IDE
debugger.
14.4
MPLINK Object Linker/
MPLIB Object Librarian
The MPLINK Object Linker combines relocatable
objects created by the MPASM Assembler and the
MPLAB C18 C Compiler. It can link relocatable objects
from precompiled libraries, using directives from a
linker script.
MPLAB ASM30 Assembler, Linker
and Librarian
MPLAB SIM Software Simulator
The MPLAB SIM Software Simulator allows code
development in a PC-hosted environment by simulating the PICmicro MCUs and dsPIC® DSCs on an
instruction level. On any given instruction, the data
areas can be examined or modified and stimuli can be
applied from a comprehensive stimulus controller.
Registers can be logged to files for further run-time
analysis. The trace buffer and logic analyzer display
extend the power of the simulator to record and track
program execution, actions on I/O, most peripherals
and internal registers.
The MPLAB SIM Software Simulator fully supports
symbolic debugging using the MPLAB C18 and
MPLAB C30 C Compilers, and the MPASM and
MPLAB ASM30 Assemblers. The software simulator
offers the flexibility to develop and debug code outside
of the hardware laboratory environment, making it an
excellent, economical software development tool.
The MPLIB Object Librarian manages the creation and
modification of library files of precompiled code. When
a routine from a library is called from a source file, only
the modules that contain that routine will be linked in
with the application. This allows large libraries to be
used efficiently in many different applications.
The object linker/library features include:
• Efficient linking of single libraries instead of many
smaller files
• Enhanced code maintainability by grouping
related modules together
• Flexible creation of libraries with easy module
listing, replacement, deletion and extraction
DS21993A-page 114
© 2006 Microchip Technology Inc.
PIC16CR7X
14.7
MPLAB ICE 2000
High-Performance
In-Circuit Emulator
The MPLAB ICE 2000 In-Circuit Emulator is intended
to provide the product development engineer with a
complete microcontroller design tool set for PICmicro
microcontrollers. Software control of the MPLAB ICE
2000 In-Circuit Emulator is advanced by the MPLAB
Integrated Development Environment, which allows
editing, building, downloading and source debugging
from a single environment.
The MPLAB ICE 2000 is a full-featured emulator
system with enhanced trace, trigger and data monitoring features. Interchangeable processor modules allow
the system to be easily reconfigured for emulation of
different processors. The architecture of the MPLAB
ICE 2000 In-Circuit Emulator allows expansion to
support new PICmicro microcontrollers.
The MPLAB ICE 2000 In-Circuit Emulator system has
been designed as a real-time emulation system with
advanced features that are typically found on more
expensive development tools. The PC platform and
Microsoft® Windows® 32-bit operating system were
chosen to best make these features available in a
simple, unified application.
14.8
MPLAB ICE 4000
High-Performance
In-Circuit Emulator
The MPLAB ICE 4000 In-Circuit Emulator is intended to
provide the product development engineer with a
complete microcontroller design tool set for high-end
PICmicro MCUs and dsPIC DSCs. Software control of
the MPLAB ICE 4000 In-Circuit Emulator is provided by
the MPLAB Integrated Development Environment,
which allows editing, building, downloading and source
debugging from a single environment.
14.9
MPLAB ICD 2 In-Circuit Debugger
Microchip’s In-Circuit Debugger, MPLAB ICD 2, is a
powerful, low-cost, run-time development tool,
connecting to the host PC via an RS-232 or high-speed
USB interface. This tool is based on the Flash PICmicro
MCUs and can be used to develop for these and other
PICmicro MCUs and dsPIC DSCs. The MPLAB ICD 2
utilizes the in-circuit debugging capability built into
the Flash devices. This feature, along with Microchip’s
In-Circuit Serial ProgrammingTM (ICSPTM) protocol,
offers cost-effective, in-circuit Flash debugging from the
graphical user interface of the MPLAB Integrated
Development Environment. This enables a designer to
develop and debug source code by setting breakpoints,
single stepping and watching variables, and CPU
status and peripheral registers. Running at full speed
enables testing hardware and applications in real
time. MPLAB ICD 2 also serves as a development
programmer for selected PICmicro devices.
14.10 MPLAB PM3 Device Programmer
The MPLAB PM3 Device Programmer is a universal,
CE compliant device programmer with programmable
voltage verification at VDDMIN and VDDMAX for
maximum reliability. It features a large LCD display
(128 x 64) for menus and error messages and a modular, detachable socket assembly to support various
package types. The ICSP™ cable assembly is included
as a standard item. In Stand-Alone mode, the MPLAB
PM3 Device Programmer can read, verify and program
PICmicro devices without a PC connection. It can also
set code protection in this mode. The MPLAB PM3
connects to the host PC via an RS-232 or USB cable.
The MPLAB PM3 has high-speed communications and
optimized algorithms for quick programming of large
memory devices and incorporates an SD/MMC card for
file storage and secure data applications.
The MPLAB ICE 4000 is a premium emulator system,
providing the features of MPLAB ICE 2000, but with
increased emulation memory and high-speed performance for dsPIC30F and PIC18XXXX devices. Its
advanced emulator features include complex triggering
and timing, and up to 2 Mb of emulation memory.
The MPLAB ICE 4000 In-Circuit Emulator system has
been designed as a real-time emulation system with
advanced features that are typically found on more
expensive development tools. The PC platform and
Microsoft Windows 32-bit operating system were
chosen to best make these features available in a
simple, unified application.
© 2006 Microchip Technology Inc.
DS21993A-page 115
PIC16CR7X
14.11 PICSTART Plus Development
Programmer
14.13 Demonstration, Development and
Evaluation Boards
The PICSTART Plus Development Programmer is an
easy-to-use, low-cost, prototype programmer. It
connects to the PC via a COM (RS-232) port. MPLAB
Integrated Development Environment software makes
using the programmer simple and efficient. The
PICSTART Plus Development Programmer supports
most PICmicro devices in DIP packages up to 40 pins.
Larger pin count devices, such as the PIC16C92X and
PIC17C76X, may be supported with an adapter socket.
The PICSTART Plus Development Programmer is CE
compliant.
A wide variety of demonstration, development and
evaluation boards for various PICmicro MCUs and dsPIC
DSCs allows quick application development on fully functional systems. Most boards include prototyping areas for
adding custom circuitry and provide application firmware
and source code for examination and modification.
14.12 PICkit 2 Development Programmer
The PICkit™ 2 Development Programmer is a low-cost
programmer with an easy-to-use interface for programming many of Microchip’s baseline, mid-range
and PIC18F families of Flash memory microcontrollers.
The PICkit 2 Starter Kit includes a prototyping development board, twelve sequential lessons, software and
HI-TECH’s PICC Lite C compiler, and is designed to
help get up to speed quickly using PIC® microcontrollers. The kit provides everything needed to
program, evaluate and develop applications using
Microchip’s powerful, mid-range Flash memory family
of microcontrollers.
DS21993A-page 116
The boards support a variety of features, including LEDs,
temperature sensors, switches, speakers, RS-232
interfaces, LCD displays, potentiometers and additional
EEPROM memory.
The demonstration and development boards can be
used in teaching environments, for prototyping custom
circuits and for learning about various microcontroller
applications.
In addition to the PICDEM™ and dsPICDEM™ demonstration/development board series of circuits, Microchip
has a line of evaluation kits and demonstration software
for analog filter design, KEELOQ® security ICs, CAN,
IrDA®, PowerSmart® battery management, SEEVAL®
evaluation system, Sigma-Delta ADC, flow rate
sensing, plus many more.
Check the Microchip web page (www.microchip.com)
and the latest “Product Selector Guide” (DS00148) for
the complete list of demonstration, development and
evaluation kits.
© 2006 Microchip Technology Inc.
PIC16CR7X
15.0
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings †
Ambient temperature under bias................................................................................................................ .-55 to +125°C
Storage temperature .............................................................................................................................. -65°C to +150°C
Voltage on any pin with respect to VSS ........................................................................................... -0.3V to (VDD + 0.3V)
Voltage on VDD with respect to VSS ............................................................................................................. -0.3 to +6.5V
Voltage on MCLR with respect to VSS...............................................................................................................0 to +5.5V
Voltage on RA4 with respect to Vss ..................................................................................................................0 to +5.5V
Total power dissipation (Note 1) ...............................................................................................................................1.0W
Maximum current out of VSS pin ...........................................................................................................................300 mA
Maximum current into VDD pin ..............................................................................................................................250 mA
Input clamp current, IIK (VI < 0 or VI > VDD)..................................................................................................................... ± 20 mA
Output clamp current, IOK (VO < 0 or VO > VDD) ............................................................................................................. ± 20 mA
Maximum output current sunk by any I/O pin..........................................................................................................25 mA
Maximum output current sourced by any I/O pin ....................................................................................................25 mA
Maximum current sunk by PORTA, PORTB, and PORTE (combined) (Note 3) ...................................................200 mA
Maximum current sourced by PORTA, PORTB, and PORTE (combined) (Note 3)..............................................200 mA
Maximum current sunk by PORTC and PORTD (combined) (Note 3) .................................................................200 mA
Maximum current sourced by PORTC and PORTD (combined) (Note 3) ............................................................200 mA
Note 1: Power dissipation is calculated as follows: Pdis = VDD x {IDD - ∑ IOH} + ∑ {(VDD - VOH) x IOH} + ∑(VOl x IOL)
2: Voltage spikes at the MCLR pin may cause latch-up. A series resistor of greater than 1 kΩ should be used
to pull MCLR to VDD, rather than tying the pin directly to VDD.
3: PORTD and PORTE are not implemented on the PIC16CR73/76 devices.
† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at those or any other conditions above those
indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability.
© 2006 Microchip Technology Inc.
DS21993A-page 117
PIC16CR7X
FIGURE 15-1:
PIC16CR7X VOLTAGE-FREQUENCY GRAPH
6.0V
5.5V
5.0V
Voltage
4.5V
4.0V
3.5V
3.0V
2.5V
2.0V
16 MHz
20 MHz
Frequency
DS21993A-page 118
© 2006 Microchip Technology Inc.
PIC16CR7X
15.1
DC Characteristics: PIC16CR73/74/76/77 (Industrial, Extended)
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for industrial
-40°C ≤ TA ≤ +125°C for extended
PIC16CR73/74/76/77
(Industrial, Extended)
Param
No.
Sym
VDD
Characteristic
Min
Typ† Max Units
Conditions
Supply Voltage
D001
PIC16CR7X
2.5
2.2
2.0
—
—
—
5.5
5.5
5.5
V
V
V
A/D in use, -40°C to +85°C
A/D in use, 0°C to +85°C
A/D not used, -40°C to +85°C
D001
D001A
PIC16CR7X
4.0
VBOR*
—
—
5.5
5.5
V
V
All configurations
BOR enabled (Note 7)
D002*
VDR
RAM Data Retention
Voltage (Note 1)
—
1.5
—
V
D003
VPOR
VDD Start Voltage to
ensure internal Power-on
Reset signal
—
VSS
—
V
D004*
SVDD
VDD Rise Rate to ensure
internal Power-on Reset
signal
0.05
-
—
D005
VBOR
Brown-out Reset Voltage
TBD
TBD TBD
See section on Power-on Reset for details
V/ms See section on Power-on Reset for details
V
BOREN bit in Configuration Word enabled
Legend: Shading of rows is to assist in readability of of the table.
* These parameters are characterized but not tested.
† Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance
only and are not tested.
Note 1:
2:
3:
4:
5:
6:
7:
This is the limit to which VDD can be lowered without losing RAM data.
The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O
pin loading and switching rate, oscillator type, internal code execution pattern and temperature also have
an impact on the current consumption.
The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD
MCLR = VDD; WDT enabled/disabled as specified.
The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is
measured with the part in Sleep mode, with all I/O pins in high-impendance state and tied to VDD and VSS.
For RC osc configuration, current through REXT is not included. The current through the resistor can be
estimated by the formula Ir = VDD/2REXT (mA) with REXT in kOhm.
Timer1 oscillator (when enabled) adds approximately 20 μA to the specification. This value is from
characterization and is for design guidance only. This is not tested.
The Δ current is the additional current consumed when this peripheral is enabled. This current should be
added to the base IDD or IPD measurement.
When BOR is enabled, the device will operate correctly until the VBOR voltage trip point is reached.
© 2006 Microchip Technology Inc.
DS21993A-page 119
PIC16CR7X
15.1
DC Characteristics: PIC16CR73/74/76/77 (Industrial, Extended) (Continued)
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for industrial
-40°C ≤ TA ≤ +125°C for extended
PIC16CR73/74/76/77
(Industrial, Extended)
Param
No.
Sym
IDD
Characteristic
Typ† Max Units
Conditions
Supply Current (Notes 2, 5)
D010
PIC16CR7X
D010A
D010
PIC16CR7X
D013
D015*
ΔIBOR Brown-out
Reset Current (Note 6)
D020
IPD
—
0.5
2
mA
XT, RC osc configuration
FOSC = 4 MHz, VDD = 3.0V (Note 4)
LP osc configuration
FOSC = 32 kHz, VDD = 3.0V, WDT disabled
—
20
48
μA
—
1.1
4
mA
—
6.3
15
mA
—
30
200
μA
BOR enabled, VDD = 5.0V
XT, RC osc configuration
FOSC = 4 MHz, VDD = 5.5V (Note 4)
HS osc configuration
FOSC = 20 MHz, VDD = 5.5V
Power-down Current (Notes 3, 5)
PIC16CR7X
—
—
TBD TBD
TBD TBD
μA
μA
VDD = 3.0V, WDT enabled, -40°C to +85°C
VDD = 3.0V, WDT disabled, -40°C to +85°C
PIC16CR7X
—
—
—
—
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
μA
μA
μA
μA
VDD = 4.0V, WDT enabled, -40°C to +85°C
VDD = 4.0V, WDT disabled, -40°C to +85°C
VDD = 4.0V, WDT enabled, -40°C to
+125°C
VDD = 4.0V, WDT disabled, -40°C to
+125°C
—
30
200
μA
BOR enabled, VDD = 5.0V
D021
D020
D021
D021A
ΔIBOR Brown-out
Reset Current (Note 6)
D023*
Min
Legend: Shading of rows is to assist in readability of of the table.
* These parameters are characterized but not tested.
† Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance
only and are not tested.
Note 1:
2:
3:
4:
5:
6:
7:
This is the limit to which VDD can be lowered without losing RAM data.
The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O
pin loading and switching rate, oscillator type, internal code execution pattern and temperature also have
an impact on the current consumption.
The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD
MCLR = VDD; WDT enabled/disabled as specified.
The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is
measured with the part in Sleep mode, with all I/O pins in high-impendance state and tied to VDD and VSS.
For RC osc configuration, current through REXT is not included. The current through the resistor can be
estimated by the formula Ir = VDD/2REXT (mA) with REXT in kOhm.
Timer1 oscillator (when enabled) adds approximately 20 μA to the specification. This value is from
characterization and is for design guidance only. This is not tested.
The Δ current is the additional current consumed when this peripheral is enabled. This current should be
added to the base IDD or IPD measurement.
When BOR is enabled, the device will operate correctly until the VBOR voltage trip point is reached.
DS21993A-page 120
© 2006 Microchip Technology Inc.
PIC16CR7X
15.2
DC Characteristics: PIC16CR73/74/76/77 (Industrial, Extended)
DC CHARACTERISTICS
Param
Sym
No.
VIL
Characteristic
Standard Operating Conditions (unless otherwise stated)
Operating temperature
-40°C ≤ TA ≤ +85°C for industrial
-40°C ≤ TA ≤ +125°C for extended
Operating voltage VDD range as described in DC Specification,
Section 15.1 “DC Characteristics: PIC16CR73/74/76/77
(Industrial, Extended)”.
Min
Typ†
Max
Units
Conditions
with TTL buffer
VSS
—
0.15VDD
V
For entire VDD range
VSS
—
0.8V
V
4.5V ≤ VDD ≤ 5.5V
with Schmitt Trigger buffer
VSS
—
0.2VDD
V
0.2VDD
V
Input Low Voltage
I/O ports:
D030
D030A
D031
D032
MCLR, OSC1 (in RC mode)
VSS
—
D033
OSC1 (in XT and LP mode)
VSS
—
0.3V
V
OSC1 (in HS mode)
VSS
—
0.3VDD
V
VIH
(Note 1)
Input High Voltage
I/O ports:
D040
with TTL buffer
D040A
D041
with Schmitt Trigger buffer
2.0
—
VDD
V
4.5V ≤ VDD ≤ 5.5V
0.25VDD
+ 0.8V
—
VDD
V
For entire VDD range
0.8VDD
—
VDD
V
For entire VDD range
0.8VDD
—
VDD
V
1.6V
—
VDD
V
V
D042
MCLR
D042A
OSC1 (in XT and LP mode)
OSC1 (in HS mode)
0.7VDD
—
VDD
D043
OSC1 (in RC mode)
0.9VDD
—
VDD
V
(Note 1)
TBD
TBD
TBD
μA
VDD = 5V, VPIN = VSS
D070
IPURB
PORTB Weak Pull-up Current
IIL
Input Leakage Current (Notes 2, 3)
D060
I/O ports
—
—
±1
μA
Vss ≤ VPIN ≤ VDD, pin at
high-impendance
D061
MCLR, RA4/T0CKI
—
—
±5
μA
Vss ≤ VPIN ≤ VDD
D063
OSC1
—
—
±5
μA
Vss ≤ VPIN ≤ VDD, XT, HS and LP
osc configuration
*
†
Note 1:
2:
3:
These parameters are characterized but not tested.
Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance
only and are not tested.
In RC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that
the PIC16CR7X be driven with external clock in RC mode.
The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified
levels represent normal operating conditions. Higher leakage current may be measured at different input
voltages.
Negative current is defined as current sourced by the pin.
© 2006 Microchip Technology Inc.
DS21993A-page 121
PIC16CR7X
15.2
DC Characteristics: PIC16CR73/74/76/77 (Industrial, Extended) (Continued)
DC CHARACTERISTICS
Param
Sym
No.
VOL
Characteristic
Standard Operating Conditions (unless otherwise stated)
Operating temperature
-40°C ≤ TA ≤ +85°C for industrial
-40°C ≤ TA ≤ +125°C for extended
Operating voltage VDD range as described in DC Specification,
Section 15.1 “DC Characteristics: PIC16CR73/74/76/77
(Industrial, Extended)”.
Min
Typ†
Max
Units
Conditions
Output Low Voltage
D080
I/O ports
—
—
0.6
V
IOL = 8.5 mA, VDD = 4.5V,
-40°C to +125°C
D083
OSC2/CLKOUT (RC osc config)
—
—
0.6
V
—
—
0.6
V
IOL = 1.6 mA, VDD = 4.5V,
-40°C to +125°C
IOL = 1.2 mA, VDD = 4.5V,
-40°C to +125°C
VOH
Output High Voltage
D090
I/O ports (Note 3)
VDD - 0.7
—
—
V
IOH = -3.0 mA, VDD = 4.5V,
-40°C to +125°C
D092
OSC2/CLKOUT (RC osc config) VDD - 0.7
—
—
V
VDD - 0.7
—
—
V
IOH = -1.3 mA, VDD = 4.5V,
-40°C to +125°C
IOH = -1.0 mA, VDD = 4.5V,
-40°C to +125°C
—
—
5.5
V
RA4 pin
In XT, HS and LP modes when
external clock is used to drive
OSC1
Open Drain High Voltage
D150*
VOD
D100
COSC2 OSC2 pin
—
—
15
pF
D101
CIO
All I/O pins and OSC2
(in RC mode)
—
—
50
pF
D102
CB
SCL, SDA in I2C™ mode
—
—
400
pF
Capacitive Loading Specs on Output Pins
*
†
Note 1:
2:
3:
These parameters are characterized but not tested.
Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance
only and are not tested.
In RC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that
the PIC16CR7X be driven with external clock in RC mode.
The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified
levels represent normal operating conditions. Higher leakage current may be measured at different input
voltages.
Negative current is defined as current sourced by the pin.
DS21993A-page 122
© 2006 Microchip Technology Inc.
PIC16CR7X
15.3
Timing Parameter Symbology
The timing parameter symbols have been created
using one of the following formats:
1. TppS2ppS
3. TCC:ST
(I2C™ specifications only)
2. TppS
4. Ts
(I2C™ specifications only)
T
F
Frequency
Lowercase letters (pp) and their meanings:
pp
cc
CCP1
ck
CLKOUT
cs
CS
di
SDI
do
SDO
dt
Data in
io
I/O port
mc
MCLR
Uppercase letters and their meanings:
S
F
Fall
H
High
I
Invalid (High-impendance)
L
Low
I2C™ only
AA
BUF
output access
Bus free
TCC:ST (I2C specifications only)
CC
HD
Hold
ST
DAT
DATA input hold
STA
Start condition
FIGURE 15-2:
T
Time
osc
rd
rw
sc
ss
t0
t1
wr
OSC1
RD
RD or WR
SCK
SS
T0CKI
T1CKI
WR
P
R
V
Z
Period
Rise
Valid
High-impendance
High
Low
High
Low
SU
Setup
STO
Stop condition
LOAD CONDITIONS
Load Condition 2
Load Condition 1
VDD/2
RL
CL
Pin
VSS
Legend:
CL
Pin
VSS
RL = 464Ω
CL = 50 pF
15 pF
for all pins except OSC2, but including PORTD and PORTE outputs as ports
for OSC2 output
Note: PORTD and PORTE are not implemented on the PIC16CR73/76 devices.
© 2006 Microchip Technology Inc.
DS21993A-page 123
PIC16CR7X
FIGURE 15-3:
EXTERNAL CLOCK TIMING
Q4
Q1
Q2
Q3
Q4
Q1
OSC1
1
3
3
4
4
2
CLKOUT
TABLE 15-1:
Parameter
No.
EXTERNAL CLOCK TIMING REQUIREMENTS
Symbol
FOSC
Characteristic
External CLKIN Frequency
(Note 1)
Oscillator Frequency
(Note 1)
1
TOSC
External CLKIN Period
(Note 1)
Oscillator Period
(Note 1)
2
TCY
3
TosL,
TosH
4
†
Note 1:
Instruction Cycle Time
(Note 1)
External Clock in (OSC1)
High or Low Time
Min
Typ†
Max
Units
DC
DC
DC
DC
0.1
4
5
1000
50
5
250
250
50
5
200
—
—
—
—
—
—
—
—
—
—
—
—
—
—
TCY
1
20
32
4
4
20
200
—
—
—
—
10,000
250
—
DC
MHz
MHz
kHz
MHz
MHz
MHz
kHz
ns
ns
ms
ns
ns
ns
ms
ns
Conditions
XT osc mode
HS osc mode
LP osc mode
RC osc mode
XT osc mode
HS osc mode
LP osc mode
XT osc mode
HS osc mode
LP osc mode
RC osc mode
XT osc mode
HS osc mode
LP osc mode
TCY = 4/FOSC
500
—
—
ns XT oscillator
2.5
—
—
ms LP oscillator
15
—
—
ns HS oscillator
TosR,
External Clock in (OSC1)
—
—
25
ns XT oscillator
TosF
Rise or Fall Time
—
—
50
ns LP oscillator
—
—
15
ns HS oscillator
Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance
only and are not tested.
Instruction cycle period (TCY) equals four times the input oscillator time base period. All specified values
are based on characterization data for that particular oscillator type under standard operating conditions,
with the device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. All devices are tested to operate at “min.” values
with an external clock applied to the OSC1/CLKIN pin. When an external clock input is used, the “max.”
cycle time limit is “DC” (no clock) for all devices.
DS21993A-page 124
© 2006 Microchip Technology Inc.
PIC16CR7X
FIGURE 15-4:
CLKOUT AND I/O TIMING
Q1
Q4
Q2
Q3
OSC1
11
10
CLKOUT
13
14
19
12
18
16
I/O Pin
(Input)
15
17
I/O Pin
(Output)
New Value
Old Value
20, 21
Note: Refer to Figure 15-2 for load conditions.
TABLE 15-2:
Param
No.
Symbol
10*
TosH2ckL
CLKOUT AND I/O TIMING REQUIREMENTS
Characteristic
Min
Typ†
Max
Units Conditions
OSC1↑ to CLKOUT↓
—
75
200
ns
(Note 1)
11*
TosH2ckH OSC1↑ to CLKOUT↑
—
75
200
ns
(Note 1)
12*
TckR
CLKOUT rise time
—
35
100
ns
(Note 1)
13*
TckF
CLKOUT fall time
—
35
100
ns
(Note 1)
14*
TckL2ioV
CLKOUT↓ to Port out valid
—
—
0.5TCY + 20
ns
(Note 1)
TOSC + 200
—
—
ns
(Note 1)
0
—
—
ns
(Note 1)
15*
TioV2ckH
Port in valid before CLKOUT↑
16*
TckH2ioI
Port in hold after CLKOUT↑
17*
TosH2ioV
OSC1↑ (Q1 cycle) to Port out valid
18*
TosH2ioI
OSC1↑ (Q2 cycle) to
Port input invalid (I/O in
hold time)
—
100
255
ns
Standard (5V)
100
—
—
ns
Extended (3V)
200
—
—
ns
19*
TioV2osH
Port input valid to OSC1↑ (I/O in setup time)
0
—
—
ns
20*
TioR
Port output rise time
Standard (5V)
—
10
40
ns
Extended (3V)
—
—
145
ns
21*
TioF
Port output fall time
Standard (5V)
—
10
40
ns
—
—
145
ns
22††*
Tinp
INT pin high or low time
TCY
—
—
ns
23††*
Trbp
RB7:RB4 change INT high or low time
TCY
—
—
ns
Extended (3V)
*
†
These parameters are characterized but not tested.
Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are
not tested.
†† These parameters are asynchronous events, not related to any internal clock edges.
Note 1: Measurements are taken in RC mode, where CLKOUT output is 4 x TOSC.
© 2006 Microchip Technology Inc.
DS21993A-page 125
PIC16CR7X
FIGURE 15-5:
RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND
POWER-UP TIMER TIMING
VDD
MCLR
30
Internal
POR
33
PWRT
Time-out
32
OSC
Time-out
Internal
RESET
Watchdog
Timer
Reset
31
34
34
I/O Pins
Note: Refer to Figure 15-2 for load conditions.
FIGURE 15-6:
BROWN-OUT RESET TIMING
VBOR
VDD
35
TABLE 15-3:
Parameter
No.
RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER
AND BROWN-OUT RESET REQUIREMENTS
Sym
Characteristic
30
TmcL
MCLR Pulse Width (low)
31*
TWDT
Watchdog Timer Time-out Period
(No Prescaler)
Min
Typ†
Max
Units
Conditions
TBD
—
—
μs
VDD = 5V, -40°C to +85°C
7
18
33
ms
VDD = 5V, -40°C to +85°C
32
TOST
Oscillation Start-up Timer Period
—
1024 TOSC
—
—
TOSC = OSC1 period
33*
TPWRT
Power-up Timer Period
28
72
132
ms
VDD = 5V, -40°C to +85°C
34
TIOZ
I/O High-impendance from MCLR
Low or Watchdog Timer Reset
—
—
2.1
μs
TBOR
Brown-out Reset Pulse Width
100
—
—
μs
35
*
†
VDD ≤ VBOR (D005)
These parameters are characterized but not tested.
Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance
only and are not tested.
DS21993A-page 126
© 2006 Microchip Technology Inc.
PIC16CR7X
FIGURE 15-7:
TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS
RA4/T0CKI
41
40
42
RC0/T1OSO/T1CKI
46
45
47
48
TMR0 or TMR1
Note: Refer to Figure 15-2 for load conditions.
TABLE 15-4:
Param
No.
40*
TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS
Symbol
Tt0H
Characteristic
T0CKI High Pulse Width
No Prescaler
With Prescaler
41*
Tt0L
T0CKI Low Pulse Width
No Prescaler
With Prescaler
42*
Tt0P
T0CKI Period
No Prescaler
With Prescaler
45*
Tt1H
T1CKI High Time Synchronous, Prescaler = 1
47*
Tt1L
Tt1P
T1CKI Low Time
T1CKI Input
Period
48
Units
0.5TCY + 20
—
—
ns
10
—
—
ns
0.5TCY + 20
—
—
ns
10
—
—
ns
—
—
ns
—
ns
N = prescale
value (2, 4, ...,
256)
0.5TCY + 20
—
—
ns
15
—
—
ns
Must also meet
parameter 47
—
—
ns
—
ns
50
—
—
ns
0.5TCY + 20
—
—
ns
15
—
—
ns
Synchronous,
Standard(5V)
Prescaler = 2,4,8 Extended(3V)
25
—
—
ns
Asynchronous
30
—
—
ns
Extended(3V)
50
—
—
ns
Standard(5V)
Greater of:
30 or TCY + 40
N
—
—
ns
Extended(3V)
Greater of:
50 or TCY + 40
N
Synchronous
Must also meet
parameter 47
N = prescale
value (1, 2, 4, 8)
N = prescale
value (1, 2, 4, 8)
Standard(5V)
60
—
—
ns
Extended(3V)
100
—
—
ns
DC
—
200
kHz
2 TOSC
—
7 TOSC
—
Timer1 Oscillator Input Frequency Range
(oscillator enabled by setting bit T1OSCEN)
Must also meet
parameter 42
—
—
Standard(5V)
Must also meet
parameter 42
TCY + 40
30
Synchronous, Prescaler = 1
Conditions
Greater of:
20 or TCY + 40
N
25
Standard(5V)
TCKEZtmr1 Delay from External Clock Edge to Timer Increment
*
†
Max
Asynchronous
Asynchronous
Ft1
Typ†
Synchronous,
Standard(5V)
Prescaler = 2,4,8 Extended(3V)
Extended(3V)
46*
Min
These parameters are characterized but not tested.
Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are
not tested.
© 2006 Microchip Technology Inc.
DS21993A-page 127
PIC16CR7X
FIGURE 15-8:
CAPTURE/COMPARE/PWM TIMINGS (CCP1 AND CCP2)
RC1/T1OSI/CCP2
and RC2/CCP1
(Capture Mode)
50
51
52
RC1/T1OSI/CCP2
and RC2/CCP1
(Compare or PWM Mode)
53
54
Note: Refer to Figure 15-2 for load conditions.
TABLE 15-5:
CAPTURE/COMPARE/PWM REQUIREMENTS (CCP1 AND CCP2)
Param
Symbol
No.
50*
TccL
Characteristic
Min
CCP1 and CCP2 No Prescaler
input low time
0.5TCY + 20
—
—
ns
10
—
—
ns
20
—
—
ns
CCP1 and CCP2 No Prescaler
input high time
0.5TCY + 20
—
—
ns
10
—
—
ns
20
—
—
ns
3TCY + 40
N
—
—
ns
Standard(5V)
With Prescaler Extended(3V)
51*
TccH
Typ† Max Units
Standard(5V)
With Prescaler Extended(3V)
52*
TccP
CCP1 and CCP2 input period
53*
TccR
CCP1 and CCP2 output rise time Standard(5V)
—
10
25
ns
Extended(3V)
—
25
50
ns
Standard(5V)
—
10
25
ns
Extended(3V)
—
25
45
ns
54*
TccF
*
†
CCP1 and CCP2 output fall time
Conditions
N = prescale
value (1,4 or 16)
These parameters are characterized but not tested.
Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only
and are not tested.
DS21993A-page 128
© 2006 Microchip Technology Inc.
PIC16CR7X
FIGURE 15-9:
PARALLEL SLAVE PORT TIMING (PIC16CR74/77 DEVICES ONLY)
RE2/CS
RE0/RD
RE1/WR
65
RD7:RD0
62
64
63
Note: Refer to Figure 15-2 for load conditions.
TABLE 15-6:
PARALLEL SLAVE PORT REQUIREMENTS (PIC16CR74/77 DEVICES ONLY)
Parameter
Symbol
No.
62
63*
64
65
*
†
Characteristic
Min Typ† Max Units
TdtV2wrH Data in valid before WR↑ or CS↑ (setup time)
TwrH2dtI
WR↑ or CS↑ to data in invalid
(hold time)
TrdL2dtV RD↓ and CS↓ to data out valid
TrdH2dtI
RD↑ or CS↓ to data out invalid
20
25
—
—
—
—
ns
ns
Standard(5V)
20
—
—
ns
Extended(3V)
35
—
—
ns
—
—
—
—
80
90
ns
ns
10
—
30
ns
Conditions
Extended range
only
Extended range
only
These parameters are characterized but not tested.
Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance
only and are not tested.
© 2006 Microchip Technology Inc.
DS21993A-page 129
PIC16CR7X
FIGURE 15-10:
SPI MASTER MODE TIMING (CKE = 0, SMP = 0)
SS
70
SCK
(CKP = 0)
71
72
78
79
79
78
SCK
(CKP = 1)
80
Bit 6 - - - - - -1
MSb
SDO
LSb
75, 76
SDI
MSb In
Bit 6 - - - -1
LSb In
74
73
Note: Refer to Figure 15-2 for load conditions.
FIGURE 15-11:
SPI MASTER MODE TIMING (CKE = 1, SMP = 1)
SS
81
SCK
(CKP = 0)
71
72
79
73
SCK
(CKP = 1)
80
78
SDO
MSb
Bit 6 - - - - - -1
LSb
Bit 6 - - - -1
LSb In
75, 76
SDI
MSb In
74
Note: Refer to Figure 15-2 for load conditions.
DS21993A-page 130
© 2006 Microchip Technology Inc.
PIC16CR7X
FIGURE 15-12:
SPI SLAVE MODE TIMING (CKE = 0)
SS
70
SCK
(CKP = 0)
83
71
72
78
79
79
78
SCK
(CKP = 1)
80
MSb
SDO
LSb
Bit 6 - - - - - -1
77
75, 76
SDI
MSb In
Bit 6 - - - -1
LSb In
74
73
Note: Refer to Figure 15-2 for load conditions.
FIGURE 15-13:
SPI SLAVE MODE TIMING (CKE = 1)
82
SS
SCK
(CKP = 0)
70
83
71
72
SCK
(CKP = 1)
80
MSb
SDO
Bit 6 - - - - - -1
LSb
75, 76
SDI
MSb In
77
Bit 6 - - - -1
LSb In
74
Note: Refer to Figure 15-2 for load conditions.
© 2006 Microchip Technology Inc.
DS21993A-page 131
PIC16CR7X
TABLE 15-7:
Param
No.
SPI MODE REQUIREMENTS
Symbol
Characteristic
Min
Typ†
Max Units Conditions
TCY
—
—
ns
70*
TssL2scH,
TssL2scL
SS↓ to SCK↓ or SCK↑ input
71*
TscH
SCK input high time (Slave mode)
TCY + 20
—
—
ns
72*
TscL
SCK input low time (Slave mode)
TCY + 20
—
—
ns
73*
TdiV2scH,
TdiV2scL
Setup time of SDI data input to SCK edge
100
—
—
ns
74*
TscH2diL,
TscL2diL
Hold time of SDI data input to SCK edge
100
—
—
ns
75*
TdoR
SDO data output rise time
—
—
10
25
25
50
ns
ns
76*
TdoF
SDO data output fall time
—
10
25
ns
77*
TssH2doZ
SS↑ to SDO output high-impendance
10
—
50
ns
78*
TscR
SCK output rise time
(Master mode)
—
—
10
25
25
50
ns
ns
79*
TscF
SCK output fall time (Master mode)
80*
TscH2doV, SDO data output valid after
TscL2doV SCK edge
81*
Standard(F)
Extended(LF)
Standard(5V)
Extended(3V)
—
10
25
ns
—
—
—
—
50
145
ns
ns
TdoV2scH, SDO data output setup to SCK edge
TdoV2scL
Tcy
—
—
ns
82*
TssL2doV
—
—
50
ns
83*
TscH2ssH, SS ↑ after SCK edge
TscL2ssH
1.5TCY + 40
—
—
ns
*
†
Standard(5V)
Extended(3V)
SDO data output valid after SS↓ edge
These parameters are characterized but not tested.
Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance
only and are not tested.
FIGURE 15-14:
I2C™ BUS START/STOP BITS TIMING
SCL
91
90
93
92
SDA
Start
Condition
Stop
Condition
Note: Refer to Figure 15-2 for load conditions.
DS21993A-page 132
© 2006 Microchip Technology Inc.
PIC16CR7X
TABLE 15-8:
Param
No.
I2C™ BUS START/STOP BITS REQUIREMENTS
Symbol
Characteristic
90*
TSU:STA
91*
THD:STA
92*
TSU:STO
93
THD:STO Stop condition
Start condition
Typ
4700
—
Max Units
—
Setup time
400 kHz mode
600
—
—
Start condition
100 kHz mode
4000
—
—
Hold time
400 kHz mode
600
—
—
Stop condition
100 kHz mode
4700
—
—
Setup time
Hold time
*
100 kHz mode
Min
400 kHz mode
600
—
—
100 kHz mode
4000
—
—
400 kHz mode
600
—
—
Conditions
ns
Only relevant for Repeated
Start condition
ns
After this period, the first
clock pulse is generated
ns
ns
These parameters are characterized but not tested.
FIGURE 15-15:
I2C™ BUS DATA TIMING
103
102
100
101
SCL
90
106
107
91
92
SDA
In
110
109
109
SDA
Out
Note: Refer to Figure 15-2 for load conditions.
© 2006 Microchip Technology Inc.
DS21993A-page 133
PIC16CR7X
TABLE 15-9:
Param.
No.
100*
I2C™ BUS DATA REQUIREMENTS
Symbol
THIGH
Characteristic
Clock high time
Min
Max
Units
100 kHz mode
4.0
—
μs
Device must operate at a
minimum of 1.5 MHz
400 kHz mode
0.6
—
μs
Device must operate at a
minimum of 10 MHz
1.5TCY
—
100 kHz mode
4.7
—
μs
Device must operate at a
minimum of 1.5 MHz
400 kHz mode
1.3
—
μs
Device must operate at a
minimum of 10 MHz
SSP Module
101*
TLOW
Clock low time
SSP Module
102*
103*
90*
91*
106*
107*
92*
109*
110*
TR
TF
TSU:STA
THD:STA
THD:DAT
TSU:DAT
TSU:STO
TAA
TBUF
CB
*
Note 1:
2:
Conditions
1.5TCY
—
—
1000
ns
300
ns
SDA and SCL rise
time
100 kHz mode
SDA and SCL fall
time
100 kHz mode
—
300
ns
400 kHz mode
20 + 0.1CB
300
ns
CB is specified to be from
10-400 pF
Only relevant for
Repeated Start
condition
400 kHz mode
20 +
0.1CB
CB is specified to be from
10-400 pF
100 kHz mode
4.7
—
μs
400 kHz mode
0.6
—
μs
Start condition hold 100 kHz mode
time
400 kHz mode
4.0
—
μs
0.6
—
μs
ns
Start condition
setup time
Data input hold time 100 kHz mode
0
—
400 kHz mode
0
0.9
μs
100 kHz mode
250
—
ns
400 kHz mode
100
—
ns
Data input setup
time
Stop condition
setup time
(Note 2)
100 kHz mode
4.7
—
μs
400 kHz mode
0.6
—
μs
Output valid from
clock
100 kHz mode
—
3500
ns
400 kHz mode
—
—
ns
Bus free time
100 kHz mode
4.7
—
μs
400 kHz mode
1.3
—
μs
—
400
pF
Bus capacitive loading
After this period the first
clock pulse is generated
(Note 1)
Time the bus must be free
before a new transmission
can start
These parameters are characterized but not tested.
As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region
(min. 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions.
A Fast mode (400 kHz) I2C bus device can be used in a Standard mode (100 kHz) I2C bus system, but the
requirement TSU:DAT ≥ 250 ns must then be met. This will automatically be the case if the device does not
stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal,
it must output the next data bit to the SDA line TR max. + TSU:DAT = 1000 + 250 = 1250 ns (according to the
Standard mode I2C bus specification), before the SCL line is released.
DS21993A-page 134
© 2006 Microchip Technology Inc.
PIC16CR7X
FIGURE 15-16:
USART SYNCHRONOUS TRANSMISSION (MASTER/SLAVE) TIMING
RC6/TX/CK
pin
121
121
RC7/RX/DT
pin
120
122
Note: Refer to Figure 15-2 for load conditions.
TABLE 15-10: USART SYNCHRONOUS TRANSMISSION REQUIREMENTS
Param
No.
Symbol
120
TckH2dtV
121
Tckrf
122
Tdtrf
†
Characteristic
Min
SYNC XMIT (MASTER &
Standard(5V)
SLAVE)
Clock high to data out valid Extended(3V)
Typ† Max
Units Conditions
—
—
80
ns
—
—
100
ns
Clock out rise time and fall Standard(5V)
time (Master mode)
Extended(3V)
—
—
45
ns
—
—
50
ns
Data out rise time and fall
time
Standard(5V)
—
—
45
ns
Extended(3V)
—
—
50
ns
Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance
only and are not tested.
FIGURE 15-17:
USART SYNCHRONOUS RECEIVE (MASTER/SLAVE) TIMING
RC6/TX/CK
pin
125
RC7/RX/DT
pin
126
Note: Refer to Figure 15-2 for load conditions.
TABLE 15-11: USART SYNCHRONOUS RECEIVE REQUIREMENTS
Parameter
No.
125
126
†
Symbol
TdtV2ckL
TckL2dtl
Characteristic
Min
Typ†
Max
Units
SYNC RCV (MASTER & SLAVE)
Data setup before CK↓ (DT setup time)
15
—
—
ns
Data hold after CK↓ (DT hold time)
15
—
—
ns
Conditions
Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only
and are not tested.
© 2006 Microchip Technology Inc.
DS21993A-page 135
PIC16CR7X
TABLE 15-12: A/D CONVERTER CHARACTERISTICS:PIC16CR7X (INDUSTRIAL, EXTENDED)
Param
No.
Sym
Characteristic
Min
Typ†
Max
Units
bit
Conditions
A01
NR
Resolution
—
—
8 bits
A02
EABS
Total absolute error
—
—
< ±1
LSb VREF = VDD = 5.12V,
VSS ≤ VAIN ≤ VREF
A03
EIL
Integral linearity error
—
—
< ±1
LSb VREF = VDD = 5.12V,
VSS ≤ VAIN ≤ VREF
A04
EDL
Differential linearity error
—
—
< ±1
LSb VREF = VDD = 5.12V,
VSS ≤ VAIN ≤ VREF
A05
EFS
Full scale error
—
—
< ±1
LSb VREF = VDD = 5.12V,
VSS ≤ VAIN ≤ VREF
A06
EOFF
Offset error
—
—
< ±1
LSb VREF = VDD = 5.12V,
VSS ≤ VAIN ≤ VREF
A10
—
Monotonicity (Note 3)
—
guaranteed
—
—
VSS ≤ VAIN ≤ VREF
A20
VREF
Reference voltage
2.5
2.2
—
—
5.5
5.5
V
V
-40°C to +125°C
0°C to +125°C
A25
VAIN
Analog input voltage
VSS - 0.3
—
VREF + 0.3
V
A30
ZAIN
Recommended impedance of
analog voltage source
—
—
10.0
kΩ
A40
IAD
A/D conversion current (VDD)
—
180
—
μA
Average current
consumption when A/D
is on (Note 1).
A50
IREF
VREF input current (Note 2)
N/A
—
—
—
±5
500
μA
μA
During VAIN acquisition.
During A/D Conversion
cycle.
*
†
Note 1:
2:
3:
VREF = VDD = 5.12V,
VSS ≤ VAIN ≤ VREF
These parameters are characterized but not tested.
Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance
only and are not tested.
When A/D is off, it will not consume any current other than minor leakage current. The power-down current
spec includes any such leakage from the A/D module.
VREF current is from the RA3 pin or the VDD pin, whichever is selected as a reference input.
The A/D conversion result never decreases with an increase in the input voltage and has no missing
codes.
DS21993A-page 136
© 2006 Microchip Technology Inc.
PIC16CR7X
FIGURE 15-18:
A/D CONVERSION TIMING
BSF ADCON0, GO
134
1 TCY
(TOSC/2)(1)
131
Q4
130
A/D CLK
132
7
A/D DATA
6
5
4
3
2
1
0
NEW_DATA
OLD_DATA
ADRES
ADIF
GO
DONE
Sampling Stopped
SAMPLE
Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the SLEEP instruction
to be executed.
TABLE 15-13: A/D CONVERSION REQUIREMENTS
Param
Sym
No.
130
TAD
Characteristic
A/D clock period
Min
Typ†
Max
Units
Conditions
PIC16CR7X
1.6
—
—
μs
TOSC based, VREF ≥ 3.0V
PIC16CR7X
2.0
—
—
μs
TOSC based,
2.0V ≤ VREF ≤ 5.5V
PIC16CR7X
2.0
4.0
6.0
μs
A/D RC mode
PIC16CR7X
3.0
6.0
9.0
μs
A/D RC mode
131
TCNV Conversion time (not including
S/H time) (Note 1)
9
—
9
TAD
132
TACQ Acquisition time
5*
—
—
μs
The minimum time is the
amplifier settling time. This
may be used if the “new” input
voltage has not changed by
more than 1 LSb (i.e.,
20.0 mV @ 5.12V) from the
last sampled voltage (as
stated on CHOLD).
134
TGO
—
TOSC/2
—
—
If the A/D clock source is
selected as RC, a time of TCY
is added before the A/D clock
starts. This allows the SLEEP
instruction to be executed.
*
†
Note 1:
2:
Q4 to A/D clock start
These parameters are characterized but not tested.
Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance
only and are not tested.
ADRES register may be read on the following TCY cycle.
See Section 11.1 “A/D Acquisition Requirements” for minimum conditions.
© 2006 Microchip Technology Inc.
DS21993A-page 137
PIC16CR7X
NOTES:
DS21993A-page 138
© 2006 Microchip Technology Inc.
PIC16CR7X
16.0
DC AND AC CHARACTERISTICS GRAPHS AND TABLES
Note:
The graphs and tables provided following this note are a statistical summary based on a limited number of
samples and are provided for informational purposes only. The performance characteristics listed herein
are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified
operating range (e.g., outside specified power supply range) and therefore, outside the warranted range.
“Typical” represents the mean of the distribution at 25°C. “Maximum” or “minimum” represents (mean + 3σ) or (mean - 3σ)
respectively, where σ is a standard deviation, over the whole temperature range.
FIGURE 16-1:
TYPICAL IDD vs. FOSC OVER VDD (HS MODE)
7
Typical: statistical mean @ 25°C
Maximum: mean + 3σ (-40°C to 125°C)
Minimum: mean – 3σ (-40°C to 125°C)
6
5.5V
5.0V
5
IDD(mA)
4.5V
4
4.0V
3
3.5V
2
3.0V
1
2.5V
2.0V
0
4
6
8
10
12
14
16
18
20
Fosc(MHz)
FIGURE 16-2:
MAXIMUM IDD vs. FOSC OVER VDD (HS MODE)
8
Typical: statistical mean @ 25°C
Maximum: mean + 3σ (-40°C to 125°C)
Minimum: mean – 3σ (-40°C to 125°C)
IDD(mA)
7
5.5V
6
5.0V
5
4.5V
4.0V
4
3
3.5V
3.0V
2
2.5V
1
2.0V
0
4
6
8
10
12
14
16
18
20
Fosc(MHz)
© 2006 Microchip Technology Inc.
DS21993A-page 139
PIC16CR7X
FIGURE 16-3:
TYPICAL IDD vs. FOSC OVER VDD (XT MODE)
1.2
Typical: statistical mean @ 25°C
Maximum: mean + 3σ (-40°C to 125°C)
Minimum: mean – 3σ (-40°C to 125°C)
5.5V
1
5.0V
IDD (mA)
0.8
4.5V
4.0V
0.6
3.5V
3.0V
0.4
2.5V
2.0V
0.2
0
0.5
1
1.5
2
2.5
3
3.5
4
Fosc (MHz)
FIGURE 16-4:
MAXIMUM IDD vs. FOSC OVER VDD (XT MODE)
1.4
Typical: statistical mean @ 25°C
Maximum: mean + 3σ (-40°C to 125°C)
Minimum: mean – 3σ (-40°C to 125°C)
1.2
5.5V
5.0V
1
IDD(mA)
4.5V
4.0V
0.8
3.5V
3.0V
0.6
2.5V
2.0V
0.4
0.2
0
0.5
1
1.5
2
2.5
3
3.5
4
Fosc (MHz)
DS21993A-page 140
© 2006 Microchip Technology Inc.
PIC16CR7X
FIGURE 16-5:
TYPICAL IDD VS. FOSC OVER VDD (LP MODE)
45
Typical: statistical mean @ 25°C
Maximum: mean + 3σ (-40°C to 125°C)
Minimum: mean – 3σ (-40°C to 125°C)
40
5.5V
35
5.0V
IDD (µA)
30
4.5V
25
4.0V
20
15
2.0V
10
5
0
30
40
50
60
70
80
90
100
Fosc (KHz)
FIGURE 16-6:
MAXIMUM IDD vs. FOSC OVER VDD (LP MODE)
85
5.5V
75
IDD (µA)
65
Typical: statistical mean @ 25°C
Maximum: mean + 3σ (-40°C to 125°C)
Minimum: mean – 3σ (-40°C to 125°C)
55
5.0V
4.5V
4.0V
45
35
2.0V
25
15
30
40
50
60
70
80
90
100
Fosc (KHz)
© 2006 Microchip Technology Inc.
DS21993A-page 141
PIC16CR7X
FIGURE 16-7:
AVERAGE FOSC vs. VDD FOR VARIOUS VALUES OF R
(RC MODE, C = 20 pF, 25°C)
5.0
4.5
Operation above 4 MHz is not recomended
4.0
3.5
Freq (MHz)
10KΩ (F7x)
3.0
10 kΩ
2.5
2.0
1.5
1.0
0.5
100 kΩ
0.0
2.5
3
3.5
4
4.5
5
5.5
5
5.5
VDD (V)
FIGURE 16-8:
AVERAGE FOSC vs. VDD FOR VARIOUS VALUES OF R
(RC MODE, C = 100 pF, 25°C)
2.5
Freq (MHz)
2
5.1 kΩ
1.5
1
10KΩ (F7x)
10 kΩ
0.5
100 kΩ
0
2.5
3
3.5
4
4.5
VDD (V)
DS21993A-page 142
© 2006 Microchip Technology Inc.
PIC16CR7X
FIGURE 16-9:
AVERAGE FOSC vs. VDD FOR VARIOUS VALUES OF R
(RC MODE, C = 300 pF, 25°C)
1
0.9
0.8
3.3KΩ
Freq (MHz)
0.7
0.6
5.1KΩ
0.5
0.4
10KΩ (F7x)
10KΩ
0.3
0.2
0.1
100KΩ
0
2.5
3
3.5
4
4.5
5
5.5
Vdd (V)
FIGURE 16-10:
IPD vs. VDD (SLEEP MODE, ALL PERIPHERALS DISABLED)
100
Max 125°C
10
IPD (uA)
Max 85°C
1
Typ 25°C
0.1
Typical: statistical mean @ 25°C
Maximum: mean + 3σ (-40°C to 125°C)
Minimum: mean – 3σ (-40°C to 125°C)
0.01
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VDD (V)
© 2006 Microchip Technology Inc.
DS21993A-page 143
PIC16CR7X
FIGURE 16-11:
ΔIBOR vs. VDD OVER TEMPERATURE
1,000
Max (125˚C)
Typ (25˚C)
Device in
SLEEP
Indeterminant
State
IDD (μA)
Device in
RESET
100
Note:
Device current in Reset
depends on Oscillator mode,
frequency and circuit.
Max (125˚C)
Typical: statistical mean @ 25°C
Maximum: mean + 3σ (-40°C to 125°C)
Minimum: mean – 3σ (-40°C to 125°C)
Typ (25˚C)
10
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
5.0
5.5
VDD (V)
FIGURE 16-12:
TYPICAL AND MAXIMUM ΔIWDT vs. VDD OVER TEMPERATURE
100
Typical: statistical mean @ 25°C
Maximum: mean + 3σ (-40°C to 125°C)
Minimum: mean – 3σ (-40°C to 125°C)
Max (125˚C)
ΔIWDT (μA)
10
Typ (25˚C)
1
0.1
2.0
2.5
3.0
3.5
4.0
4.5
VDD (V)
DS21993A-page 144
© 2006 Microchip Technology Inc.
PIC16CR7X
FIGURE 16-13:
TYPICAL, MINIMUM AND MAXIMUM WDT PERIOD vs. VDD (-40°C TO 125°C)
16F77
50
45
Typical: statistical mean @ 25°C
Maximum: mean + 3σ (-40°C to 125°C)
Minimum: mean – 3σ (-40°C to 125°C)
40
35
WDT Period (ms)
Max
(125°C)
30
25
Typ
(25°C)
20
Min
(-40°C)
15
10
5
0
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VDD (V)
FIGURE 16-14:
AVERAGE WDT PERIOD vs. VDD OVER TEMPERATURE (-40°C TO 125°C)
50
45
Typical: statistical mean @ 25°C
Maximum: mean + 3σ (-40°C to 125°C)
Minimum: mean – 3σ (-40°C to 125°C)
40
125°C
35
WDT Period (ms)
85°C
30
25°C
25
20
-40°C
15
10
5
0
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VDD (V)
© 2006 Microchip Technology Inc.
DS21993A-page 145
PIC16CR7X
FIGURE 16-15:
TYPICAL, MINIMUM AND MAXIMUM VOH vs. IOH (VDD = 5V, -40°C TO 125°C)
5.5
5.0
4.5
4.0
Max
3.5
VOH (V)
Typ (25°C)
3.0
2.5
Min
2.0
Typical: statistical mean @ 25°C
Maximum: mean + 3σ (-40°C to 125°C)
Minimum: mean – 3σ (-40°C to 125°C)
1.5
1.0
0.5
0.0
0
5
10
15
20
25
IOH (-mA)
FIGURE 16-16:
TYPICAL, MINIMUM AND MAXIMUM VOH vs. IOH (VDD = 3V, -40°C TO 125°C)
3.5
Typical: statistical mean @ 25°C
Maximum: mean + 3σ (-40°C to 125°C)
Minimum: mean – 3σ (-40°C to 125°C)
3.0
2.5
Max
VOH (V)
2.0
Typ (25°C)
1.5
Min
1.0
0.5
0.0
0
5
10
15
20
25
IOH (-mA)
DS21993A-page 146
© 2006 Microchip Technology Inc.
PIC16CR7X
FIGURE 16-17:
TYPICAL, MINIMUM AND MAXIMUM VOL vs. IOL (VDD = 5V, -40°C TO 125°C)
1.0
0.9
Max (125°C)
Typical: statistical mean @ 25°C
Maximum: mean + 3σ (-40°C to 125°C)
Minimum: mean – 3σ (-40°C to 125°C)
0.8
0.7
Max (85°C)
VOL (V)
0.6
0.5
Typ (25°C)
0.4
0.3
Min (-40°C)
0.2
0.1
0.0
0
5
10
15
20
25
IOL (-mA)
FIGURE 16-18:
TYPICAL, MINIMUM AND MAXIMUM VOL vs. IOL (VDD = 3V, -40°C TO 125°C)
3.0
Max (125°C)
Typical: statistical mean @ 25°C
Maximum: mean + 3σ (-40°C to 125°C)
Minimum: mean – 3σ (-40°C to 125°C)
2.5
VOL (V)
2.0
1.5
Max (85°C)
1.0
Typ (25°C)
0.5
Min (-40°C)
0.0
0
5
10
15
20
25
IOL (-mA)
© 2006 Microchip Technology Inc.
DS21993A-page 147
PIC16CR7X
FIGURE 16-19:
MINIMUM AND MAXIMUM VIN vs. VDD, (TTL INPUT, -40°C TO 125°C)
1.5
1.4
Typical: statistical mean @ 25°C
Maximum: mean + 3σ (-40°C to 125°C)
Minimum: mean – 3σ (-40°C to 125°C)
1.3
VTH Max (-40°C)
1.2
1.1
VIN (V)
VTH Typ (25°C)
1.0
VTH Min (125°C)
0.9
0.8
0.7
0.6
0.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VDD (V)
FIGURE 16-20:
MINIMUM AND MAXIMUM VIN vs. VDD (ST INPUT, -40°C TO 125°C)
4.0
Typical: statistical mean @ 25°C
Maximum: mean + 3σ (-40°C to 125°C)
Minimum: mean – 3σ (-40°C to 125°C)
3.5
VIH Max (125°C)
3.0
VIN (V)
2.5
VIH Min (-40°C)
2.0
VIL Max (-40°C)
1.5
1.0
VIL Min (125°C)
0.5
0.0
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VDD (V)
DS21993A-page 148
© 2006 Microchip Technology Inc.
PIC16CR7X
17.0
PACKAGING INFORMATION
17.1
Package Marking Information
28-Lead PDIP
Example
XXXXXXXXXXXXXXX
XXXXXXXXXXXXXXX
XXXXXXXXXXXXXXX
YYWWNNN
40-Lead PDIP
PICXXFXXXX-I/P
0510017
Example
XXXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXXX
YYWWNNN
44-Lead PLCC
Example
XXXXXXXXXX
XXXXXXXXXX
XXXXXXXXXX
YYWWNNN
Legend: XX...X
Y
YY
WW
NNN
e3
*
Note:
*
PICXXFXXXX-I/P
0510017
PICXXFXXX
/L
0510017
Customer-specific information
Year code (last digit of calendar year)
Year code (last 2 digits of calendar year)
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code
Pb-free JEDEC designator for Matte Tin (Sn)
This package is Pb-free. The Pb-free JEDEC designator ( e3 )
can be found on the outer packaging for this package.
In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
Standard PICmicro device marking consists of Microchip part number, year code, week code, and
traceability code. For PICmicro device marking beyond this, certain price adders apply. Please check
with your Microchip Sales Office. For QTP devices, any special marking adders are included in QTP
price.
© 2006 Microchip Technology Inc.
DS21993A-page 149
PIC16CR7X
17.1
Package Marking Information (continued)
28-Lead QFN
XXXXXXXX
XXXXXXXX
YYWWNNN
28-Lead SOIC (.300”)
XXXXXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXXXXX
YYWWNNN
28-Lead SSOP
XXXXXXXXXXXX
XXXXXXXXXXXX
YYWWNNN
44-Lead TQFP
XXXXXXXXXX
XXXXXXXXXX
XXXXXXXXXX
YYWWNNN
DS21993A-page 150
Example
XXFXXX
/ML
0510017
Example
PICXXFXXXX/SO
0510017
Example
PICXXFXXXX
-I/SS
0510017
Example
PICXXFXXXX
-I/PT
0510017
© 2006 Microchip Technology Inc.
PIC16CR7X
17.2
Package Details
The following sections give the technical details of the packages.
28-Lead Skinny Plastic Dual In-line (SP) – 300 mil Body (PDIP)
E1
D
2
n
1
α
E
A2
A
L
c
β
B1
A1
eB
Units
Number of Pins
Pitch
p
B
Dimension Limits
n
p
INCHES*
MIN
NOM
MILLIMETERS
MAX
MIN
28
NOM
MAX
28
.100
2.54
Top to Seating Plane
A
.140
.150
.160
3.56
3.81
4.06
Molded Package Thickness
A2
.125
.130
.135
3.18
3.30
3.43
8.26
Base to Seating Plane
A1
.015
Shoulder to Shoulder Width
E
.300
.310
.325
7.62
7.87
Molded Package Width
E1
.275
.285
.295
6.99
7.24
7.49
Overall Length
D
1.345
1.365
1.385
34.16
34.67
35.18
Tip to Seating Plane
L
c
.125
.130
.135
3.18
3.30
3.43
.008
.012
.015
0.20
0.29
0.38
B1
.040
.053
.065
1.02
1.33
1.65
Lead Thickness
Upper Lead Width
Lower Lead Width
Overall Row Spacing
Mold Draft Angle Top
§
0.38
B
.016
.019
.022
0.41
0.48
0.56
eB
α
.320
.350
.430
8.13
8.89
10.92
5
10
15
5
10
15
β
Mold Draft Angle Bottom
5
10
15
5
10
15
* Controlling Parameter
§ Significant Characteristic
Notes:
Dimension D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side.
JEDEC Equivalent: MO-095
Drawing No. C04-070
© 2006 Microchip Technology Inc.
DS21993A-page 151
PIC16CR7X
40-Lead Plastic Dual In-line (P) – 600 mil Body (PDIP)
E1
D
α
2
1
n
E
A2
A
L
c
β
B1
A1
eB
p
B
Units
Dimension Limits
n
p
INCHES*
NOM
40
.100
.175
.150
MAX
MILLIMETERS
NOM
40
2.54
4.06
4.45
3.56
3.81
0.38
15.11
15.24
13.46
13.84
51.94
52.26
3.05
3.30
0.20
0.29
0.76
1.27
0.36
0.46
15.75
16.51
5
10
5
10
MAX
Number of Pins
Pitch
Top to Seating Plane
A
.160
.190
4.83
Molded Package Thickness
A2
.140
.160
4.06
Base to Seating Plane
.015
A1
Shoulder to Shoulder Width
E
.595
.600
.625
15.88
Molded Package Width
E1
.530
.545
.560
14.22
Overall Length
D
2.045
2.058
2.065
52.45
Tip to Seating Plane
L
.120
.130
.135
3.43
c
Lead Thickness
.008
.012
.015
0.38
Upper Lead Width
B1
.030
.050
.070
1.78
Lower Lead Width
B
.014
.018
.022
0.56
Overall Row Spacing
§
eB
.620
.650
.680
17.27
α
Mold Draft Angle Top
5
10
15
15
β
Mold Draft Angle Bottom
5
10
15
15
* Controlling Parameter
§ Significant Characteristic
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side.
JEDEC Equivalent: MO-011
Drawing No. C04-016
DS21993A-page 152
MIN
MIN
© 2006 Microchip Technology Inc.
PIC16CR7X
44-Lead Plastic Leaded Chip Carrier (L) – Square (PLCC)
E
E1
#leads=n1
D1 D
n 1 2
CH2 x 45 °
CH1 x 45 °
α
A3
A2
35°
A
B1
B
c
β
E2
Units
Dimension Limits
n
p
A1
p
D2
INCHES*
NOM
44
.050
11
.165
.173
.145
.153
.028
.020
.024
.029
.040
.045
.000
.005
.685
.690
.685
.690
.650
.653
.650
.653
.590
.620
.590
.620
.008
.011
.026
.029
.013
.020
0
5
0
5
MAX
MILLIMETERS
NOM
44
1.27
11
4.19
4.39
3.68
3.87
0.71
0.51
0.61
0.74
1.02
1.14
0.00
0.13
17.40
17.53
17.40
17.53
16.51
16.59
16.51
16.59
14.99
15.75
14.99
15.75
0.20
0.27
0.66
0.74
0.33
0.51
0
5
0
5
MAX
Number of Pins
Pitch
Pins per Side
n1
Overall Height
A
.180
4.57
.160
4.06
Molded Package Thickness
A2
.035
0.89
Standoff
§
A1
A3
Side 1 Chamfer Height
.034
0.86
Corner Chamfer 1
CH1
.050
1.27
.010
0.25
Corner Chamfer (others)
CH2
Overall Width
E
.695
17.65
Overall Length
D
.695
17.65
Molded Package Width
E1
.656
16.66
Molded Package Length
D1
.656
16.66
Footprint Width
E2
.630
16.00
Footprint Length
.630
16.00
D2
c
Lead Thickness
.013
0.33
Upper Lead Width
B1
.032
0.81
B
.021
0.53
Lower Lead Width
α
Mold Draft Angle Top
10
10
β
Mold Draft Angle Bottom
10
10
* Controlling Parameter
§ Significant Characteristic
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side.
JEDEC Equivalent: MO-047
Drawing No. C04-048
© 2006 Microchip Technology Inc.
MIN
MIN
DS21993A-page 153
PIC16CR7X
28-Lead Plastic Quad Flat No Lead Package (ML) 6x6 mm Body (QFN) –
With 0.55 mm Contact Length (Saw Singulated)
E2
E
EXPOSED
METAL
PAD
(NOTE 2)
e
D
b
D2
2
1
K
n
OPTIONAL
INDEX
TOP VIEW
AREA
SEE DETAIL
ALTERNATE
INDEX
INDICATORS
L
BOTTOM VIEW
(NOTE 1)
A1
A
Units
Dimension Limits
n
MILLIMETERS*
INCHES
MIN
Number of Pins
DETAIL
ALTERNATE
PAD OUTLINE
MAX
NOM
MIN
NOM
28
MAX
28
Pitch
e
Overall Height
A
.031
.035
.039
0.80
0.90
1.00
Standoff
A1
.000
.001
.002
0.00
0.02
0.05
Contact Thickness
A3
Overall Width
Exposed Pad Width
Overall Length
Exposed Pad Length
0.65 BSC
.026 BSC
0.20 REF
.008 REF
E
.232
.236
.240
5.90
6.00
6.10
E2
.153
.167
.169
3.89
4.24
4.29
D
.232
.236
.240
5.90
6.00
6.10
D2
.153
.167
.169
3.89
4.24
4.29
Contact Width
β
.009
.011
.013
0.23
0.28
0.33
Contact Length §
L
.018
.022
.024
0.45
0.55
0.65
K
.008
–
–
0.20
–
–
Contact-to-Exposed Pad
§
* Controlling Parameter
§ Significant Characteristic
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. Exposed pad varies according to die attach paddle size.
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
See ASME Y14.5M
REF: Reference Dimension, usually without tolerance, for information purposes only.
See ASME Y14.5M
JEDEC equivalent: MO-220
Drawing No. C04-105
DS21993A-page 154
Revised 09-12-05
© 2006 Microchip Technology Inc.
PIC16CR7X
28-Lead Plastic Small Outline (SO) – Wide, 300 mil Body (SOIC)
E
E1
p
D
B
2
1
n
h
α
45°
c
A2
A
φ
β
L
Units
Dimension Limits
n
p
A1
INCHES*
NOM
28
.050
.099
.091
.008
.407
.295
.704
.020
.033
4
.011
.017
12
12
MAX
MILLIMETERS
NOM
28
1.27
2.36
2.50
2.24
2.31
0.10
0.20
10.01
10.34
7.32
7.49
17.65
17.87
0.25
0.50
0.41
0.84
0
4
0.23
0.28
0.36
0.42
0
12
0
12
MAX
Number of Pins
Pitch
Overall Height
A
.093
.104
2.64
Molded Package Thickness
A2
.088
.094
2.39
Standoff
§
A1
.004
.012
0.30
Overall Width
E
.394
.420
10.67
Molded Package Width
E1
.288
.299
7.59
Overall Length
D
.695
.712
18.08
Chamfer Distance
h
.010
.029
0.74
Foot Length
L
.016
.050
1.27
φ
Foot Angle Top
0
8
8
c
Lead Thickness
.009
.013
0.33
Lead Width
B
.014
.020
0.51
α
Mold Draft Angle Top
0
15
15
β
Mold Draft Angle Bottom
0
15
15
* Controlling Parameter
§ Significant Characteristic
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side.
JEDEC Equivalent: MS-013
Drawing No. C04-052
© 2006 Microchip Technology Inc.
MIN
MIN
DS21993A-page 155
PIC16CR7X
28-Lead Plastic Shrink Small Outline (SS) – 209 mil Body, 5.30 mm (SSOP)
E
E1
p
D
B
2
1
n
A
c
φ
A2
A1
L
Units
Number of Pins
Dimension Limits
n
p
Pitch
Overall Height
Molded Package Thickness
Standoff
Overall Width
Molded Package Width
Overall Length
Foot Length
Lead Thickness
Foot Angle
Lead Width
A
A2
A1
E
E1
D
L
c
φ
B
MIN
.065
.002
.295
.197
.390
.022
.004
0°
.009
INCHES
NOM
28
.026
.069
.307
.209
.402
.030
4°
-
MAX
.079
.073
.323
.220
.413
.037
.010
8°
.015
MIN
MILLIMETERS *
NOM
28
1.65
0.05
7.49
5.00
9.90
0.55
0.09
0°
0.22
0.65
1.75
7.80
5.30
10.20
0.75
4°
-
MAX
2.0
1.85
8.20
5.60
10.50
0.95
0.25
8°
0.38
* Controlling Parameter
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" (0.254mm) per side.
Drawing No. C04-073
DS21993A-page 156
Revised 1-12-06
© 2006 Microchip Technology Inc.
PIC16CR7X
44-Lead Plastic Thin-Quad Flatpack (PT) 10x10x1 mm Body, 1.0/0.10 mm Lead Form (TQFP)
E
E1
#leads=n1
p
D1
D
2
1
B
n
CH x 45°
α
A
c
φ
β
A1
L
Number of Pins
Units
Dimension Limits
n
p
Pitch
Pins per Side
Overall Height
Molded Package Thickness
Standoff
Foot Length
Footprint (Reference)
n1
A
A2
A1
L
F
φ
MIN
.039
.037
.002
.018
A2
F
INCHES
NOM
44
.031
11
.043
.039
.004
.024
.039 REF.
MAX
.047
.041
.006
.030
MIN
MILLIMETERS*
NOM
44
1.00
0.95
0.05
0.45
MAX
0.80
11
1.10
1.00
0.10
0.60
1.00 REF.
1.20
1.05
0.15
0.75
Foot Angle
0
3.5
7
0
3.5
7
Overall Width
E
.463
.472
.482
11.75
12.00
12.25
Overall Length
D
.463
.472
.482
11.75
12.00
12.25
Molded Package Width
E1
.390
.394
.398
9.90
10.00
10.10
Molded Package Length
D1
.390
.394
.398
9.90
10.00
10.10
c
Lead Thickness
.004
.006
.008
0.09
0.15
0.20
Lead Width
B
.012
.015
.017
0.30
0.38
0.44
CH
.025
.035
.045
0.64
0.89
1.14
Pin 1 Corner Chamfer
α
5
10
15
5
10
15
Mold Draft Angle Top
β
5
10
15
5
10
15
Mold Draft Angle Bottom
* Controlling Parameter
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" (0.254mm) per side.
REF: Reference Dimension, usually without tolerance, for information purposes only.
See ASME Y14.5M
JEDEC Equivalent: MS-026
Revised 07-22-05
Drawing No. C04-076
© 2006 Microchip Technology Inc.
DS21993A-page 157
PIC16CR7X
NOTES:
DS21993A-page 158
© 2006 Microchip Technology Inc.
PIC16CR7X
APPENDIX A:
REVISION HISTORY
Version
Date
Revision Description
A
2006
This is a new data sheet. However, these devices are similar to
the PIC16F7X devices found in
the PIC16F7X Data Sheet
(DS30325B).
TABLE B-1:
APPENDIX B:
DEVICE
DIFFERENCES
The differences between the devices in this data sheet
are listed in Table B-1.
DEVICE DIFFERENCES
Difference
PIC16CR73
PIC16CR74
PIC16CR76
PIC16CR77
ROM Program Memory
(14-bit words)
4K
4K
8K
8K
Data Memory (bytes)
192
192
368
368
3
5
3
5
5 channels,
8 bits
8 channels,
8 bits
5 channels,
8 bits
8 channels,
8 bits
Parallel Slave Port
no
yes
no
yes
Interrupt Sources
11
12
11
12
28-pin PDIP
28-pin SOIC
28-pin SSOP
28-pin QFN
40-pin PDIP
44-pin TQFP
44-pin PLCC
28-pin PDIP
28-pin SOIC
28-pin SSOP
28-pin MLF
40-pin PDIP
44-pin TQFP
44-pin PLCC
I/O Ports
A/D
Packages
© 2006 Microchip Technology Inc.
DS21993A-page 159
PIC16CR7X
APPENDIX C:
CONVERSION
CONSIDERATIONS
Considerations for converting from previous versions
of devices to the ones listed in this data sheet are listed
in Table C-1.
TABLE C-1:
CONVERSION CONSIDERATIONS
Characteristic
PIC16CR7X
PIC16F87X
PIC16F7X
28/40
28/40
28/40
3
3
3
11 or 12
13 or 14
11 or 12
PSP, USART, SSP
(SPI, I2C™ Slave)
PSP, USART, SSP
(SPI, I2C Master/Slave)
PSP, USART, SSP
(SPI, I2C Slave)
20 MHz
20 MHz
20 MHz
A/D
8-bit
10-bit
8-bit
CCP
2
2
2
4K, 8K ROM
4K, 8K FLASH
(1,000 E/W cycles)
4K, 8K FLASH
(100 E/W cycles, typical)
192, 368 bytes
192, 368 bytes
192, 368 bytes
None
128, 256 bytes
None
—
In-Circuit Debugger,
Low-Voltage Programming
—
Pins
Timers
Interrupts
Communication
Frequency
Program Memory
RAM
EEPROM Data
Other
DS21993A-page 160
© 2006 Microchip Technology Inc.
PIC16CR7X
INDEX
A
A/D
A/D Conversio Status (GO/DONE Bit) ........................ 83
Acquisition Requirements ........................................... 86
ADCON0 Register....................................................... 83
ADCON1 Register....................................................... 83
ADRES Register ......................................................... 83
Analog Port Pins ......................................... 8, 10, 12, 39
Analog-to-Digital Converter......................................... 83
Associated Registers .................................................. 88
Configuring Analog Port Pins...................................... 87
Configuring the Interrupt ............................................. 85
Configuring the Module............................................... 85
Conversion Clock........................................................ 87
Conversion Requirements ........................................ 137
Conversions ................................................................ 87
Converter Characteristics ......................................... 136
Effects of a RESET ..................................................... 87
Faster Conversion - Lower Resolution Trade-off ........ 87
Internal Sampling Switch (Rss) Impedance ................ 86
Operation During SLEEP ............................................ 87
Source Impedance...................................................... 86
Using the CCP Trigger................................................ 88
Absolute Maximum Ratings .............................................. 117
ACK pulse ..................................................................... 65, 66
ADCON0 Register............................................................... 83
GO/DONE Bit.............................................................. 83
ADCON1 Register............................................................... 83
ADRES Register ................................................................. 83
Analog Port Pins. See A/D
Application Notes
AN552 (Implementing Wake-up on Key Strokes
Using PIC16F7X) ............................................... 33
AN556 (Implementing a Table Read) ......................... 26
AN578 (Use of the SSP Module in the I2C
Multi-Master Environment).................................. 59
AN607 (Power-up Trouble Shooting).......................... 94
Assembler
MPASM Assembler................................................... 114
B
Banking, Data Memory ....................................................... 13
BF bit................................................................................... 60
Block Diagrams
A/D .............................................................................. 85
Analog Input Model ..................................................... 86
Capture Mode Operation ............................................ 55
Compare ..................................................................... 55
Crystal/Ceramic Resonator Operation (HS, XT
or LP Osc Configuration) .................................... 91
External Clock Input Operation
(HS Osc Configuration)....................................... 91
Interrupt Logic ............................................................. 99
PIC16CR73 and PIC16CR76........................................ 6
PIC16CR74 and PIC16CR77........................................ 7
PORTA
RA3:RA0 and RA5 Port Pins .............................. 31
RA4/T0CKI Pin ................................................... 31
PORTB
RB3:RB0 Port Pins ............................................. 33
RB7:RB4 Port Pins ............................................. 33
PORTC (Peripheral Output Override) ......................... 35
PORTD (In I/O Port Mode).......................................... 36
PORTD and PORTE (Parallel Slave Port) .................. 40
© 2006 Microchip Technology Inc.
PORTE (In I/O Port Mode) ......................................... 37
PWM Mode................................................................. 57
RC Oscillator Mode .................................................... 92
Recommended MCLR Circuit..................................... 94
Reset Circuit ............................................................... 93
SSP (I2C Mode).......................................................... 65
SSP (SPI Mode) ......................................................... 62
Timer0/WDT Prescaler ............................................... 43
Timer1 ........................................................................ 48
Timer2 ........................................................................ 51
USART
Receive .............................................................. 76
USART Transmit ........................................................ 74
Watchdog Timer (WDT)............................................ 101
BOR. See Brown-out Reset
BRGH bit ............................................................................ 71
Brown-out Reset (BOR).............................. 89, 93, 94, 95, 96
C
C Compilers
MPLAB C18.............................................................. 114
MPLAB C30.............................................................. 114
Capture/Compare/PWM (CCP)
Associated Registers............................................ 56, 58
Capture Mode............................................................. 55
Prescaler ............................................................ 55
CCP Pin Configuration ......................................... 55, 56
CCP1
RC2/CCP1 Pin................................................ 9, 11
CCP2
RC1/T1OSI/CCP2 Pin .................................... 9, 11
Compare Mode........................................................... 55
Software Interrupt Mode ..................................... 56
Special Trigger Output........................................ 56
Timer1 Mode Selection....................................... 56
Example PWM Frequencies and Resolutions ............ 58
Interaction of Two CCP Modules................................ 53
PWM Duty Cycle ........................................................ 57
PWM Mode................................................................. 57
PWM Period ............................................................... 57
Setup for PWM Operation .......................................... 58
Special Event Trigger and A/D Conversions .............. 56
Timer Resources ........................................................ 53
CCP1 Module ..................................................................... 53
CCP2 Module ..................................................................... 53
CCPR1H Register............................................................... 53
CCPR1L Register ............................................................... 53
CCPxM<3:0> bits................................................................ 54
CCPxX and CCPxY bits...................................................... 54
CKE bit ............................................................................... 60
CKP bit ............................................................................... 61
Code Examples
Call of a Subroutine in Page 1 from Page 0 ............... 26
Changing Between Capture Prescalers ..................... 55
Changing Prescaler Assignment to Timer0 ................ 45
Changing Prescaler Assignment to WDT ................... 45
Indirect Addressing..................................................... 27
Initializing PORTA ...................................................... 31
Reading a 16-bit Free-Running Timer ........................ 49
ROM Program Read................................................... 30
Saving STATUS, W, and PCLATH Registers
in RAM............................................................. 100
Writing a 16-bit Free-Running Timer .......................... 49
Code Protection .......................................................... 89, 103
DS21993A-page 161
PIC18FXXXX
Computed GOTO ................................................................ 26
Configuration Bits................................................................ 89
Continuous Receive Enable (CREN Bit) ............................. 70
Conversion Considerations ............................................... 160
Customer Change Notification Service ............................. 167
Customer Notification Service........................................... 167
Customer Support ............................................................. 167
D
D/A bit ................................................................................. 60
Data Memory....................................................................... 13
Bank Select (RP1:RP0 Bits) ....................................... 13
General Purpose Registers......................................... 13
Register File Map, PIC16CR74/73.............................. 15
Register File Map, PIC16CR77/76.............................. 14
Special Function Registers ......................................... 16
Data/Address bit (D/A) ........................................................ 60
DC and AC Characteristics
Graphs and Tables ................................................... 139
DC Characteristics ............................................................ 119
Development Support ....................................................... 113
Device Differences ............................................................ 159
Device Overview ................................................................... 5
Features ........................................................................ 5
Direct Addressing................................................................ 27
E
Electrical Characteristics................................................... 117
Errata .................................................................................... 4
External Clock Input (RA4/T0CKI). See Timer0
External Interrupt Input (RB0/INT). See Interrupt Sources
F
Firmware Instructions........................................................ 105
FSR Register....................................................................... 27
I
I/O Ports .............................................................................. 31
I2C Mode
Addressing .................................................................. 66
Associated Registers .................................................. 68
Master Mode ............................................................... 68
Mode Selection ........................................................... 65
Multi-Master Mode ...................................................... 68
Operation .................................................................... 65
Reception .................................................................... 66
Slave Mode
SCL and SDA pins .............................................. 65
Transmission............................................................... 67
ID Locations ...................................................................... 103
INDF Register ..................................................................... 27
Indirect Addressing ............................................................. 27
FSR Register .............................................................. 13
Instruction Format ............................................................. 105
Instruction Set ................................................................... 105
ADDLW ..................................................................... 107
ADDWF ..................................................................... 107
ANDLW ..................................................................... 107
ANDWF ..................................................................... 107
BCF ........................................................................... 107
BSF ........................................................................... 107
BTFSC ...................................................................... 107
BTFSS ...................................................................... 107
CALL ......................................................................... 108
CLRF......................................................................... 108
CLRW ....................................................................... 108
DS21993A-page 162
CLRWDT .................................................................. 108
COMF ....................................................................... 108
DECF ........................................................................ 108
DECFSZ ................................................................... 109
GOTO ....................................................................... 109
INCF ......................................................................... 109
INCFSZ..................................................................... 109
IORLW ...................................................................... 109
IORWF...................................................................... 109
RETURN........................................................... 110, 111
RLF ........................................................................... 111
RRF .................................................................. 110, 111
SLEEP .............................................................. 110, 111
SUBLW ............................................................. 110, 111
SUBWF............................................................. 110, 111
SWAPF ..................................................................... 112
XORLW .................................................................... 112
XORWF .................................................................... 112
Summary Table ........................................................ 106
INT Interrupt (RB0/INT). See Interrupt Sources
INTCON Register................................................................ 21
GIE Bit ........................................................................ 21
INTE Bit ...................................................................... 21
INTF Bit ...................................................................... 21
RBIF Bit ................................................................ 21, 33
TMR0IE Bit ................................................................. 21
Inter-Integrated Circuit (I2C). See I2C Mode
Internet Address ............................................................... 167
Interrupt Sources .......................................................... 89, 99
Interrupt-on-Change (RB7:RB4) ................................. 33
RB0/INT Pin, External..................................... 8, 11, 100
TMR0 Overflow......................................................... 100
USART Receive/Transmit Complete .......................... 69
Interrupts
Synchronous Serial Port Interrupt............................... 23
Interrupts, Context Saving During..................................... 100
Interrupts, Enable Bits
Global Interrupt Enable (GIE Bit) .......................... 21, 99
Interrupt-on-Change (RB7:RB4) Enable (RBIE Bit).. 100
RB0/INT Enable (INTE Bit) ......................................... 21
TMR0 Overflow Enable (TMR0IE Bit)......................... 21
Interrupts, Flag Bits
Interrupt-on Change (RB7:RB4) Flag (RBIF Bit) ........ 21
Interrupt-on-Change (RB7:RB4) Flag
(RBIF Bit)............................................. 21, 33, 100
RB0/INT Flag (INTF Bit) ............................................. 21
TMR0 Overflow Flag (TMR0IF Bit) ........................... 100
L
Load Conditions................................................................ 123
Loading of PC ..................................................................... 26
M
Master Clear (MCLR)............................................................ 8
MCLR Reset, Normal Operation..................... 93, 95, 96
MCLR Reset, SLEEP...................................... 93, 95, 96
Operation and ESD Protection ................................... 94
MCLR Pin ........................................................................... 10
MCLR/VPP Pin ...................................................................... 8
Memory Organization ......................................................... 13
Data Memory .............................................................. 13
Program Memory ........................................................ 13
Program Memory and Stack Maps ............................. 13
Microchip Internet Web Site.............................................. 167
MPLAB ASM30 Assembler, Linker, Librarian ................... 114
MPLAB ICD 2 In-Circuit Debugger ................................... 115
© 2006 Microchip Technology Inc.
PIC16CR7X
MPLAB ICE 2000 High-Performance Universal
In-Circuit Emulator .................................................... 115
MPLAB ICE 4000 High-Performance Universal
In-Circuit Emulator .................................................... 115
MPLAB Integrated Development Environment Software .. 113
MPLAB PM3 Device Programmer .................................... 115
MPLINK Object Linker/MPLIB Object Librarian ................ 114
O
OPCODE Field Descriptions ............................................. 105
OPTION_REG Register ...................................................... 20
INTEDG Bit ................................................................. 20
PS2:PS0 Bits .............................................................. 20
PSA Bit........................................................................ 20
RBPU Bit..................................................................... 20
T0CS Bit...................................................................... 20
T0SE Bit...................................................................... 20
OSC1/CLKI Pin ............................................................... 8, 10
OSC2/CLKO Pin ............................................................. 8, 10
Oscillator Configuration....................................................... 89
Oscillator Configurations ..................................................... 91
Crystal Oscillator/Ceramic Resonators ....................... 91
HS ......................................................................... 91, 95
LP.......................................................................... 91, 95
RC................................................................... 91, 92, 95
XT ......................................................................... 91, 95
Oscillator, WDT ................................................................. 101
P
P (STOP) bit........................................................................ 60
Packaging ......................................................................... 149
Marking ..................................................................... 149
PDIP Details.............................................................. 151
Paging, Program Memory ................................................... 26
Parallel Slave Port
Associated Registers .................................................. 41
Parallel Slave Port (PSP) .............................................. 36, 40
RE0/RD/AN5 Pin................................................... 12, 39
RE1/WR/AN6 Pin.................................................. 12, 39
RE2/CS/AN7 Pin................................................... 12, 39
Select (PSPMODE Bit) ......................................... 36, 37
PCFG0 bit ........................................................................... 84
PCFG1 bit ........................................................................... 84
PCFG2 bit ........................................................................... 84
PCL Register....................................................................... 26
PCLATH Register ............................................................... 26
PCON Register ............................................................. 25, 95
POR Bit ....................................................................... 25
PICSTART Plus Development Programmer ..................... 116
PIE1 Register ...................................................................... 22
PIE2 Register ...................................................................... 24
Pinout Descriptions
PIC16CR73/PIC16CR76........................................... 8–9
PIC16CR74/PIC16CR77....................................... 10–12
PIR1 Register...................................................................... 23
PIR2 Register...................................................................... 24
PMADR Register................................................................. 29
PMADRH Register .............................................................. 29
POP .................................................................................... 26
POR. See Power-on Reset
PORTA............................................................................ 8, 10
Analog Port Pins ..................................................... 8, 10
Associated Registers .................................................. 32
PORTA Register ......................................................... 31
RA4/T0CKI Pin........................................................ 8, 10
RA5/SS/AN4 Pin ..................................................... 8, 10
© 2006 Microchip Technology Inc.
TRISA Register........................................................... 31
PORTA Register ................................................................. 31
PORTB ........................................................................... 8, 11
Associated Registers.................................................. 34
PORTB Register......................................................... 33
Pull-up Enable (RBPU Bit).......................................... 20
RB0/INT Edge Select (INTEDG Bit) ........................... 20
RB0/INT Pin, External .................................... 8, 11, 100
RB7:RB4 Interrupt-on-Change ................................. 100
RB7:RB4 Interrupt-on-Change Enable (RBIE Bit) .... 100
RB7:RB4 Interrupt-on-Change Flag (RBIF Bit) ... 21, 33,
100
TRISB Register........................................................... 33
PORTB Register ................................................................. 33
PORTC ........................................................................... 9, 11
Associated Registers.................................................. 35
PORTC Register......................................................... 35
RC0/T1OSO/T1CKI Pin.......................................... 9, 11
RC1/T1OSI/CCP2 Pin ............................................ 9, 11
RC2/CCP1 Pin........................................................ 9, 11
RC3/SCK/SCL Pin.................................................. 9, 11
RC4/SDI/SDA Pin................................................... 9, 11
RC5/SDO Pin ......................................................... 9, 11
RC6/TX/CK Pin................................................. 9, 11, 70
RC7/RX/DT Pin .......................................... 9, 11, 70, 71
TRISC Register .......................................................... 35
PORTC Register................................................................. 35
PORTD ............................................................................... 12
Associated Registers.................................................. 36
Parallel Slave Port (PSP) Function............................. 36
PORTD Register......................................................... 36
TRISD Register .......................................................... 36
PORTD Register................................................................. 36
PORTE ............................................................................... 12
Analog Port Pins................................................... 12, 39
Associated Registers.................................................. 39
Input Buffer Full Status (IBF Bit)................................. 38
Input Buffer Overflow (IBOV Bit)................................. 38
PORTE Register......................................................... 37
PSP Mode Select (PSPMODE Bit)....................... 36, 37
RE0/RD/AN5 Pin .................................................. 12, 39
RE1/WR/AN6 Pin ................................................. 12, 39
RE2/CS/AN7 Pin .................................................. 12, 39
TRISE Register........................................................... 37
PORTE Register ................................................................. 37
Postscaler, WDT
Assignment (PSA Bit) ................................................. 20
Rate Select (PS2:PS0 Bits) ........................................ 20
Power-down Mode. See SLEEP
Power-on Reset (POR)..................................... 89, 93, 95, 96
Oscillator Start-up Timer (OST)............................ 89, 94
POR Status (POR Bit) ................................................ 25
Power Control (PCON) Register................................. 95
Power-down (PD Bit) .................................................. 93
Power-up Timer (PWRT) ...................................... 89, 94
Time-out (TO Bit).................................................. 19, 93
PR2 Register ...................................................................... 51
Prescaler, Timer0
Assignment (PSA Bit) ................................................. 20
Rate Select (PS2:PS0 Bits) ........................................ 20
Program Counter
RESET Conditions...................................................... 95
Program Memory ................................................................ 29
Associated Registers.................................................. 30
Interrupt Vector........................................................... 13
Memory and Stack Maps ............................................ 13
DS21993A-page 163
PIC18FXXXX
Operation During Code Protect................................... 30
Organization................................................................ 13
Paging ......................................................................... 26
PMADR Register......................................................... 29
PMADRH Register ...................................................... 29
Reading ROM ............................................................. 30
Reading, PMADR Register ......................................... 29
Reading, PMADRH Register....................................... 29
Reading, PMCON1 Register ....................................... 29
Reading, PMDATA Register ....................................... 29
Reading, PMDATH Register ....................................... 29
RESET Vector............................................................. 13
Program Verification.......................................................... 103
Programming, Device Instructions .................................... 105
PUSH .................................................................................. 26
R
R/W bit .................................................................... 60, 66, 67
RA0/AN0 Pin ................................................................... 8, 10
RA1/AN1 Pin ................................................................... 8, 10
RA2/AN2 Pin ................................................................... 8, 10
RA3/AN3/VREF Pin.......................................................... 8, 10
RA4/T0CKI Pin................................................................ 8, 10
RA5/SS/AN4 Pin ............................................................. 8, 10
RAM. See Data Memory
RB0/INT Pin .................................................................... 8, 11
RB1 Pin ........................................................................... 8, 11
RB2 Pin ........................................................................... 8, 11
RB3 Pin ........................................................................... 8, 11
RB4 Pin ........................................................................... 8, 11
RB5 Pin ........................................................................... 8, 11
RB6 Pin ........................................................................... 8, 11
RB7 Pin ........................................................................... 8, 11
RC0/T1OSO/T1CKI Pin .................................................. 9, 11
RC1/T1OSI/CCP2 Pin..................................................... 9, 11
RC2/CCP1 Pin ................................................................ 9, 11
RC3/SCK/SCL Pin .......................................................... 9, 11
RC4/SDI/SDA Pin ........................................................... 9, 11
RC5/SDO Pin .................................................................. 9, 11
RC6/TX/CK Pin ............................................................... 9, 11
RC7/RX/DT Pin ............................................................... 9, 11
RCSTA Register
CREN Bit..................................................................... 70
OERR Bit .................................................................... 70
SPEN Bit ..................................................................... 69
SREN Bit ..................................................................... 70
RD0/PSP0 Pin..................................................................... 12
RD1/PSP1 Pin..................................................................... 12
RD2/PSP2 Pin..................................................................... 12
RD3/PSP3 Pin..................................................................... 12
RD4/PSP4 Pin..................................................................... 12
RD5/PSP5 Pin..................................................................... 12
RD6/PSP6 Pin..................................................................... 12
RD7/PSP7 Pin..................................................................... 12
RE0/RD/AN5 Pin................................................................. 12
RE1/WR/AN6 Pin ................................................................ 12
RE2/CS/AN7 Pin ................................................................. 12
Reader Response ............................................................. 168
Read-Modify-Write Operations.......................................... 105
Receive Overflow Indicator bit (SSPOV)............................. 61
Register File ........................................................................ 13
Registers
ADCON0 (A/D Control 0) ............................................ 83
ADCON0 Register....................................................... 83
ADCON1 (A/D Control 1) ............................................ 83
ADCON1 Register....................................................... 84
DS21993A-page 164
ADRES (A/D Result)................................................... 83
CCP1CON/CCP2CON Register ................................. 54
Configuration Word Register ...................................... 90
Initialization Conditions (table).............................. 96–97
INTCON (Interrupt Control)......................................... 21
INTCON Register........................................................ 21
OPTION_REG ............................................................ 20
OPTION_REG Register........................................ 20, 44
PCON (Power Control) ............................................... 25
PCON Register ........................................................... 25
PIE1 (Peripheral Interrupt Enable 1)........................... 22
PIE1 Register ............................................................. 22
PIE2 (Peripheral Interrupt Enable 2)........................... 24
PIE2 Register ............................................................. 24
PIR1 (Peripheral Interrupt Request 1) ........................ 23
PIR1 Register ............................................................. 23
PIR2 (Peripheral Interrupt Request 2) ........................ 24
PIR2 Register ............................................................. 24
PMCON1 (Program Memory Control 1) Register ....... 29
RCSTA Register ......................................................... 70
Special Function, Summary.................................. 16–18
SSPCON Register ...................................................... 61
SSPSTAT Register ..................................................... 60
STATUS Register ....................................................... 19
T1CON Register ......................................................... 47
T2CON Register ......................................................... 52
TRISE Register........................................................... 38
TXSTA Register.......................................................... 69
RESET .......................................................................... 89, 93
Brown-out Reset (BOR). See Brown-out Reset (BOR)
MCLR Reset. See MCLR
Power-on Reset (POR). See Power-on Reset (POR)
RESET Conditions for All Registers ........................... 96
RESET Conditions for PCON Register....................... 95
RESET Conditions for Program Counter .................... 95
RESET Conditions for STATUS Register ................... 95
Reset
WDT Reset. See Watchdog Timer (WDT)
Revision History................................................................ 159
S
S (START) bit ..................................................................... 60
SCI. See USART
SCL..................................................................................... 65
Serial Communication Interface. See USART
SLEEP .................................................................. 89, 93, 102
SMP bit ............................................................................... 60
Software Simulator (MPLAB SIM) .................................... 114
Special Features of the CPU .............................................. 89
Special Function Registers ..................................... 16, 16–18
Speed, Operating.................................................................. 1
SPI Mode ............................................................................ 59
Associated Registers .................................................. 64
Serial Clock (SCK pin) ................................................ 59
Serial Data In (SDI pin)............................................... 59
Serial Data Out (SDO pin) .......................................... 59
Slave Select................................................................ 59
SSP
Overview
RA5/SS/AN4 Pin..................................................... 8, 10
RC3/SCK/SCL Pin .................................................. 9, 11
RC4/SDI/SDA Pin ................................................... 9, 11
RC5/SDO Pin.......................................................... 9, 11
SSP I2C Operation.............................................................. 65
Slave Mode................................................................. 65
SSPEN bit........................................................................... 61
© 2006 Microchip Technology Inc.
PIC16CR7X
SSPIF bit ............................................................................. 23
SSPM<3:0> bits .................................................................. 61
SSPOV bit ........................................................................... 61
Stack ................................................................................... 26
Overflows .................................................................... 26
Underflow.................................................................... 26
STATUS Register
DC Bit.......................................................................... 19
IRP Bit......................................................................... 19
PD Bit.......................................................................... 93
TO Bit.................................................................... 19, 93
Z Bit............................................................................. 19
Synchronous Serial Port Enable bit (SSPEN)..................... 61
Synchronous Serial Port Interrupt bit (SSPIF) .................... 23
Synchronous Serial Port Mode Select bits (SSPM<3:0>) ... 61
Synchronous Serial Port. See SSP
T
T1CKPS0 bit ....................................................................... 47
T1CKPS1 bit ....................................................................... 47
T1OSCEN bit ...................................................................... 47
T1SYNC bit ......................................................................... 47
T2CKPS0 bit ....................................................................... 52
T2CKPS1 bit ....................................................................... 52
TAD ....................................................................................... 87
Time-out Sequence............................................................. 94
Timer0 ................................................................................. 43
Associated Registers .................................................. 45
Clock Source Edge Select (T0SE Bit)......................... 20
Clock Source Select (T0CS Bit).................................. 20
External Clock............................................................. 44
Interrupt....................................................................... 43
Overflow Enable (TMR0IE Bit).................................... 21
Overflow Flag (TMR0IF Bit) ...................................... 100
Overflow Interrupt ..................................................... 100
Prescaler..................................................................... 45
RA4/T0CKI Pin, External Clock .............................. 8, 10
T0CKI.......................................................................... 44
Timer1 ................................................................................. 47
Associated Registers .................................................. 50
Asynchronous Counter Mode ..................................... 49
Capacitor Selection..................................................... 50
Counter Operation ...................................................... 48
Operation in Timer Mode ............................................ 48
Oscillator ..................................................................... 50
Prescaler..................................................................... 50
RC0/T1OSO/T1CKI Pin .......................................... 9, 11
RC1/T1OSI/CCP2 Pin............................................. 9, 11
Resetting of Timer1 Registers .................................... 50
Resetting Timer1 using a CCP Trigger Output ........... 50
Synchronized Counter Mode ...................................... 48
TMR1H Register ......................................................... 49
TMR1L Register.......................................................... 49
Timer2 ................................................................................. 51
Associated Registers .................................................. 52
Output ......................................................................... 51
Postscaler ................................................................... 51
Prescaler..................................................................... 51
Prescaler and Postscaler ............................................ 51
Timing Diagrams
A/D Conversion......................................................... 137
Brown-out Reset ....................................................... 126
Capture/Compare/PWM (CCP1 and CCP2) ............. 128
CLKOUT and I/O....................................................... 125
External Clock........................................................... 124
I2C Bus Data ............................................................. 133
© 2006 Microchip Technology Inc.
I2C Bus Start/Stop Bits ............................................. 132
I2C Reception (7-bit Address)..................................... 67
I2C Transmission (7-bit Address) ............................... 67
Parallel Slave Port .................................................... 129
Parallel Slave Port Read Waveforms ......................... 41
Parallel Slave Port Write Waveforms ......................... 41
Power-up Timer ........................................................ 126
PWM Output ............................................................... 57
RESET...................................................................... 126
Slow Rise Time (MCLR Tied to VDD
Through RC Network)......................................... 98
SPI Master Mode (CKE = 0, SMP = 0) ..................... 130
SPI Master Mode (CKE = 1, SMP = 1) ..................... 130
SPI Mode (Master Mode) ........................................... 63
SPI Mode (Slave Mode with CKE = 0)........................ 63
SPI Mode (Slave Mode with CKE = 1)........................ 64
SPI Slave Mode (CKE = 0) ....................................... 131
SPI Slave Mode (CKE = 1) ....................................... 131
Start-up Timer........................................................... 126
Time-out Sequence on Power-up
(MCLR Not Tied to VDD)
Case 1 ................................................................ 98
Case 2 ................................................................ 98
Time-out Sequence on Power-up
(MCLR Tied to VDD Through RC Network)......... 97
Timer0 ...................................................................... 127
Timer1 ...................................................................... 127
USART Asynchronous Master Transmission ............. 74
USART Asynchronous Master Transmission
(Back to Back) ................................................... 75
USART Asynchronous Reception .............................. 76
USART Synchronous Receive (Master/Slave) ......... 135
USART Synchronous Reception
(Master Mode, SREN) ........................................ 80
USART Synchronous Transmission ........................... 79
USART Synchronous Transmission
(Master/Slave) .................................................. 135
USART Synchronous Transmission
(Through TXEN) ................................................. 79
Wake-up from Sleep via Interrupt............................. 103
Watchdog Timer ....................................................... 126
Timing Parameter Symbology .......................................... 123
Timing Requirements
Capture/Compare/PWM (CCP1 and CCP2)............. 128
CLKOUT and I/O ...................................................... 125
External Clock .......................................................... 124
I2C Bus Data............................................................. 134
I2C Bus Start/Stop Bits............................................. 133
Parallel Slave Port .................................................... 129
Reset, Watchdog Timer, Oscillator Start-up
Timer, Power-up Timer and Brown-out Reset . 126
SPI Mode.................................................................. 132
Timer0 and Timer1 External Clock ........................... 127
USART Synchronous Receive ................................. 135
USART Synchronous Transmission ......................... 135
TMR1CS bit ........................................................................ 47
TMR1ON bit........................................................................ 47
TMR2ON bit........................................................................ 52
TOUTPS<3:0> bits ............................................................. 52
TRISA Register................................................................... 31
TRISB Register................................................................... 33
TRISC Register................................................................... 35
TRISD Register................................................................... 36
DS21993A-page 165
PIC18FXXXX
TRISE Register ................................................................... 37
IBF Bit ......................................................................... 38
IBOV Bit ...................................................................... 38
PSPMODE Bit ....................................................... 36, 37
TXSTA Register
SYNC Bit ..................................................................... 69
TRMT Bit ..................................................................... 69
TX9 Bit ........................................................................ 69
TX9D Bit...................................................................... 69
TXEN Bit ..................................................................... 69
U
UA ....................................................................................... 60
Universal Synchronous Asynchronous Receiver
Transmitter. See USART
Update Address bit, UA....................................................... 60
USART ................................................................................ 69
Asynchronous Mode ................................................... 73
Asynchronous Receiver .............................................. 75
Asynchronous Reception ............................................ 76
Associated Registers .......................................... 77
Asynchronous Transmission
Associated Registers .......................................... 75
Asynchronous Transmitter .......................................... 73
Baud Rate Generator (BRG)....................................... 71
Baud Rate Formula............................................. 71
Baud Rates, Asynchronous Mode (BRGH = 0) .. 72
Baud Rates, Asynchronous Mode (BRGH = 1) .. 72
Sampling ............................................................. 71
Mode Select (SYNC Bit) ............................................. 69
Overrun Error (OERR Bit) ........................................... 70
RC6/TX/CK Pin ....................................................... 9, 11
RC7/RX/DT Pin ....................................................... 9, 11
Serial Port Enable (SPEN Bit)..................................... 69
Single Receive Enable (SREN Bit) ............................. 70
Synchronous Master Mode ......................................... 78
Synchronous Master Reception .................................. 80
Associated Registers .......................................... 81
Synchronous Master Transmission............................. 78
Associated Registers .......................................... 79
Synchronous Slave Mode ........................................... 81
Synchronous Slave Reception .................................... 82
Associated Registers .......................................... 82
Synchronous Slave Transmission............................... 81
Associated Registers .......................................... 82
Transmit Data, 9th Bit (TX9D)..................................... 69
Transmit Enable (TXEN Bit)........................................ 69
Transmit Enable, Nine-bit (TX9 Bit) ............................ 69
Transmit Shift Register Status (TRMT Bit).................. 69
User Code ......................................................................... 103
DS21993A-page 166
W
Wake-up from SLEEP......................................................... 89
Interrupts .............................................................. 95, 96
MCLR Reset ............................................................... 96
WDT Reset ................................................................. 96
Wake-up from Sleep ......................................................... 102
Wake-up Using Interrupts ................................................. 102
Watchdog Timer (WDT).............................................. 89, 101
Associated Registers ................................................ 101
Enable (WDTE Bit) ................................................... 101
Postscaler. See Postscaler, WDT
Programming Considerations ................................... 101
RC Oscillator............................................................. 101
Time-out Period ........................................................ 101
WDT Reset, Normal Operation....................... 93, 95, 96
WDT Reset, SLEEP........................................ 93, 95, 96
WCOL bit ............................................................................ 61
Write Collision Detect bit (WCOL) ...................................... 61
WWW Address ................................................................. 167
WWW, On-Line Support ....................................................... 4
© 2006 Microchip Technology Inc.
PIC16CR7X
THE MICROCHIP WEB SITE
CUSTOMER SUPPORT
Microchip provides online support via our WWW site at
www.microchip.com. This web site is used as a means
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customers. Accessible by using your favorite Internet
browser, the web site contains the following
information:
Users of Microchip products can receive assistance
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Technical Support
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Technical support is available through the web site
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© 2006 Microchip Technology Inc.
DS21993A-page 167
PIC16CR7X
READER RESPONSE
It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip product. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation
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Literature Number: DS21993A
Questions:
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2. How does this document meet your hardware and software development needs?
3. Do you find the organization of this document easy to follow? If not, why?
4. What additions to the document do you think would enhance the structure and subject?
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DS21993A-page 168
© 2006 Microchip Technology Inc.
PIC16CR7X
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
PART NO.
X
/XX
XXX
Device
Temperature
Range
Package
Pattern
Examples:
a)
b)
Device:
PIC18F248/258(1), PIC18F448/458(1), PIC18F248/258T(2),
PIC18F448/458T(2);
VDD range 4.2V to 5.5V
PIC18LF248/258(1), PIC18LF448/458(1), PIC18LF248/258T(2),
PIC18LF448/458T(2);
VDD range 2.0V to 5.5V
Temperature
Range:
I
E
= -40°C to +85°C
= -40°C to +125°C
Package:
PT
L
SO
SP
P
=
=
=
=
=
Pattern:
c)
PIC18LF258 - I/L 301 = Industrial temp., PLCC
package, Extended VDD limits, QTP pattern
#301.
PIC18LF458 - I/PT = Industrial temp., TQFP
package, Extended VDD limits.
PIC18F258 - E/L = Extended temp., PLCC
package, normal VDD limits.
(Industrial)
(Extended)
TQFP (Thin Quad Flatpack)
PLCC
SOIC
Skinny Plastic DIP
PDIP
Note 1:
2:
F = Standard Voltage Range
LF = Wide Voltage Range
T = in tape and reel PLCC, and TQFP
packages only.
QTP, SQTP, Code or Special Requirements
(blank otherwise)
© 2006 Microchip Technology Inc.
DS21993A-page 169
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Fax: 86-757-2839-5571
China - Wuhan
Tel: 86-27-5980-5300
Fax: 86-27-5980-5118
China - Xian
Tel: 86-29-8833-7250
Fax: 86-29-8833-7256
Malaysia - Penang
Tel: 60-4-646-8870
Fax: 60-4-646-5086
Philippines - Manila
Tel: 63-2-634-9065
Fax: 63-2-634-9069
Italy - Milan
Tel: 39-0331-742611
Fax: 39-0331-466781
Netherlands - Drunen
Tel: 31-416-690399
Fax: 31-416-690340
Spain - Madrid
Tel: 34-91-708-08-90
Fax: 34-91-708-08-91
UK - Wokingham
Tel: 44-118-921-5869
Fax: 44-118-921-5820
Singapore
Tel: 65-6334-8870
Fax: 65-6334-8850
Taiwan - Hsin Chu
Tel: 886-3-572-9526
Fax: 886-3-572-6459
Taiwan - Kaohsiung
Tel: 886-7-536-4818
Fax: 886-7-536-4803
Taiwan - Taipei
Tel: 886-2-2500-6610
Fax: 886-2-2508-0102
Thailand - Bangkok
Tel: 66-2-694-1351
Fax: 66-2-694-1350
Toronto
Mississauga, Ontario,
Canada
Tel: 905-673-0699
Fax: 905-673-6509
02/16/06
DS21993A-page 170
© 2006 Microchip Technology Inc.
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