EVALUATION KIT AVAILABLE
MAX5134–MAX5137
Pin-/Software-Compatible,
16-/12-Bit, Voltage-Output DACs
The MAX5134–MAX5137 is a family of pin-compatible and software-compatible 16-bit and 12-bit DACs. The
MAX5134/MAX5135 are low-power, quad 16-/12-bit, buffered voltage-output, high-linearity DACs. The
MAX5136/MAX5137 are low-power, dual 16-/12-bit, buffered voltage-output, high-linearity DACs. They use a precision internal reference or a precision external reference for rail-to-rail operation. The MAX5134–MAX5137 accept a wide +2.7V to +5.25V supply-voltage range to accommodate most low-power and low-voltage applications. These devices accept a 3-wire SPI-/QSPI
TM
-/
MICROWIRE
®
-/DSP-compatible serial interface to save board space and reduce the complexity of optically isolated and transformer-isolated applications. The digital interface’s double-buffered hardware and software
LDAC provide simultaneous output updates. The serial interface features a
READY output for easy daisy-chaining of several MAX5134–MAX5137 devices and/or other compatible devices. The MAX5134–MAX5137 include a hardware input to reset the DAC outputs to zero or midscale upon power-up or reset, providing additional safety for applications that drive valves or other transducers that need to be off during power-up. The high linearity of the DACs makes these devices ideal for precision control and instrumentation applications. The MAX5134–
MAX5137 are available in an ultra-small (4mm x 4mm),
24-pin TQFN package or a 16-pin TSSOP package. Both packages are specified over the -40°C to +105°C extended industrial temperature range.
Automatic Test Equipment
Automatic Tuning
Communication Systems
Data Acquisition
Gain and Offset Adjustment
Portable Instrumentation
Power-Amplifier Control
Process Control and Servo Loops
Programmable Voltage and Current Sources o o
16-/12-Bit Resolution Available in a 4mm x 4mm,
24-Pin TQFN Package or 16-Pin TSSOP
Hardware-Selectable to Zero/Midscale DAC
Output on Power-Up or Reset
o o o o o
Double-Buffered Input Registers
LDAC
Asynchronously Updates DAC Outputs
Simultaneously
READY
Facilitates Daisy Chaining
High-Performance 10ppm/°C Internal Reference
o o o
Guaranteed Monotonic Over All Operating
Conditions
Wide +2.7V to +5.25V Supply Range
Rail-to-Rail Buffered Output Operation
Low Gain Error (Less Than ±0.5%FS) and Offset
(Less Than ±10mV)
o o o
30MHz 3-Wire SPI-/QSPI-/MICROWIRE-/
DSP-Compatible Serial Interface
CMOS-Compatible Inputs with Hysteresis
Low-Power Consumption (I
SHDN
= 2 µ A max)
PART
PIN-
PACKAGE
RESOLUTION
(BITS)
INL
(LSB)
MAX5134
AGTG+
MAX5134AGUE+
MAX5135
GTG+
MAX5135GUE+
24 TQFN-EP*
16 TSSOP
24 TQFN-EP*
16 TSSOP
16 Quad
16 Quad
12 Quad
12 Quad
±8
±8
±1
±1
MAX5136
AGTG+
MAX5136AGUE+
24 TQFN-EP*
16 TSSOP
16 Dual
16 Dual
±8
±8
MAX5137
GTG+ 24 TQFN-EP* 12 Dual ±1
MAX5137GUE+ 16 TSSOP 12 Dual ±1
+ Denotes a lead(Pb)-free/RoHS-compliant package.
* EP = Exposed pad.
Note:
All devices are specified over the -40°C to +105°C operating temperature range.
Functional Diagrams, Pin Configurations, and Typical
Operating Circuit appear at end of data sheet.
QSPI is a trademark of Motorola Inc.
MICROWIRE is a registered trademark of National
Semiconductor Corp.
19-4209; Rev 4; 11/13
2
MAX5134–MAX5137
Pin-/Software-Compatible,
16-/12-Bit, Voltage-Output DACs
AVDD to GND...........................................................-0.3V to +6V
DVDD to GND...........................................................-0.3V to +6V
OUT0–OUT3 to GND ....................................-0.3V to the lower of
(AVDD + 0.3V) and +6V
REFI, REFO, M/
Z to GND .............................-0.3V to the lower of
(AVDD + 0.3V) and +6V
SCLK, DIN,
CS to GND ................................-0.3V to the lower of
(DVDD + 0.3V) and +6V
LDAC
,
READY to GND .................................-0.3V to the lower of
(DVDD + 0.3V) and +6V
Continuous Power Dissipation (T
A
= +70°C)
24-Pin TQFN (derate at 27.8mW/°C above +70°C)....2222.2mW
16-Pin TSSOP (derate at 11.1mW/°C above +70°C)....888.9mW
Maximum Current into Any Input or Output with the Exception of M/
Z
Pin .......................................±50mA
Maximum Current into M/
Z
Pin ...........................................±5mA
Operating Temperature Range .........................-40°C to +105°C
Storage Temperature Range .............................-65°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
Soldering Temperature (reflow) .......................................+260°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
TQFN
Junction-to-Ambient Thermal Resistance (
θ
JA
) ............36°C/W
Junction-to-Case Thermal Resistance (
θ
JC
) ...................3°C/W
TSSOP
Junction-to-Ambient Thermal Resistance (
θ
JA
) ............90°C/W
Junction-to-Case Thermal Resistance (
θ
JC
) .................27°C/W
Note 1:
Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-
layer board. For detailed information on package thermal considerations, refer to
www.maximintegrated.com/thermal-tutorial
(V
AVDD
T
A
= T
= 2.7V to 5.25V, V
MIN to T
MAX
DVDD
= 2.7V to 5.25V, V
AVDD
≥
V
DVDD
, V
, unless otherwise noted. Typical values are at T
A
GND
= 0V, V
= +25°C.)
REFI
= V
AVDD
- 0.25V, C
OUT
= 200pF, R
OUT
= 10k
Ω
,
PARAMETER
Integral Nonlinearity
(MAX5135/MAX5137)
SYMBOL
STATIC ACCURACY (Notes 1, 2)
MAX5134/MAX5136 16
Resolution N Bits
MAX5135/MAX5137 12
Integral Nonlinearity
(MAX5134/MAX5136)
INL
V
V
REFI
= 5V,
AVDD
= 5.25V
(Note 3)
T
A
= +25°C
-8 ±2 +10
±6
LSB
INL V
REFI
= 5V, V
CONDITIONS
AVDD
= 5.25V
MIN
-1
TYP
+0.25
MAX
+1
UNITS
LSB
Differential Nonlinearity
Offset Error
Gain Error
DNL
OE
Guaranteed monotonic
(Note 4)
GE (Note 4)
-1.0
-10
-0.5
±1
±0.2
+1.0
+10
+0.5
LSB mV
Gain Temperature Coefficient ±2
% of FS ppm
FS/°C
REFERENCE INPUT
Reference-Input Voltage Range
Reference-Input Impedance
V
REFI
V
AVDD
= 3V to 5.25V
V
AVDD
= 2.7V to 3V
2
2
113
V
AVDD
V
AVDD
- 0.2 k
V
Maxim Integrated
MAX5134–MAX5137
Pin-/Software-Compatible,
16-/12-Bit, Voltage-Output DACs
(V
T
A
AVDD
= T
= 2.7V to 5.25V, V
MIN to T
MAX
DVDD
= 2.7V to 5.25V, V
AVDD
≥
V
DVDD
, V
GND
, unless otherwise noted. Typical values are at T
A
= 0V, V
REFI
= +25°C.)
= V
AVDD
- 0.25V, C
OUT
= 200pF, R
OUT
= 10k
Ω
,
PARAMETER
INTERNAL REFERENCE
Reference Voltage
Reference Temperature Coefficient
Reference Output Impedance
Line Regulation
Maximum Capacitive Load
DAC OUTPUT VOLTAGE (Note 2)
SYMBOL
V
REFO
C
R
T
A =
CONDITIONS MIN TYP MAX UNITS
+25°C 2.437
(Note 5) 10
1
100
0.1
25 ppm/°C ppm/V nF
Output Voltage Range No load 0.02
0.1
V
AVDD
- 0.02
V
DC Output Impedance
Maximum Capacitive Load
(Note 5)
C
L
Series resistance = 0
Series resistance = 500
Resistive Load
Short-Circuit Current
R
L
V
AVDD
= 5.25V
I
SC
V
AVDD
= 2.7V
Power-Up Time From power-down mode
DIGITAL INPUTS (SCLK, DIN,
CS
,
LDAC
) (Note 6)
Input High Voltage V
IH
2
-40
0.7 x
V
DVDD
±35
±20
25
+40 k mA
μs
V
Input Low Voltage
Input Leakage Current
Input Capacitance
DIGITAL OUTPUTS (
READY
)
Output High Voltage
Output Low Voltage
DYNAMIC PERFORMANCE
Voltage-Output Slew Rate
Voltage-Output Settling Time
V
IL
0.3 x
V
DVDD
V
I
IN
V
IN
= 0 or V
C
IN
DVDD
-1
10 pF
V
V
OH
OL
SR t
S
I
I
SOURCE
SINK
= 3mA
= 2mA
Positive and negative
1/4 scale to 3/4 scale V
REFI
= V
AVDD
= 5V settle to ±2 LSB (Note 5)
V
DVDD
- 0.5
V
1.25
0.4 V
V/μs
5 μs
Code 0, all digital inputs from 0 to V
DVDD
0.5 Digital Feedthrough
Major Code Transition Analog
Glitch Impulse
Output Noise
Integrated Output Noise
DAC-to-DAC Crosstalk
10kHz
1Hz to 10kHz
25 nV•s
120
18
25 nV/
Hz
μV nV•s
Maxim Integrated 3
4
MAX5134–MAX5137
Pin-/Software-Compatible,
16-/12-Bit, Voltage-Output DACs
(V
T
A
AVDD
= T
= 2.7V to 5.25V, V
MIN to T
MAX
DVDD
= 2.7V to 5.25V, V
AVDD
≥
V
DVDD
, V
GND
, unless otherwise noted. Typical values are at T
A
= 0V, V
REFI
= +25°C.)
= V
AVDD
- 0.25V, C
OUT
= 200pF, R
OUT
= 10k
Ω
,
PARAMETER
POWER REQUIREMENTS (Note 7)
SYMBOL CONDITIONS MIN TYP MAX UNITS
Analog Supply Voltage Range
Digital Supply Voltage Range
Supply Current
(MAX5134/MAX5135)
V
AVDD
V
DVDD
I
AVDD
I
DVDD
No load, all digital inputs at 0 or DVDD
2.7
2.7 V
5.25
AVDD
V
V
Supply Current
(MAX5136/MAX5137)
I
AVDD
I
DVDD
No load, all digital inputs at 0 or DVDD
Power-Down Supply Current
I
AVPD
I
DVPD
No load, all digital inputs at 0 or DVDD
2
0.1 2
μA
TIMING CHARACTERISTICS (Note 8) (Figure 1)
Serial-Clock Frequency
SCLK Pulse-Width High
SCLK Pulse-Width Low
CS
Fall-to-SCLK Fall Setup Time
SCLK Fall-to
CS
-Rise Hold Time
DIN-to-SCLK Fall Setup Time
DIN-to-SCLK Fall Hold Time
SCLK Fall to
READY
Transition
CS
Pulse-Width High
LDAC
Pulse Width f
SCLK t
CH t
CL t
CSS t
CSH t
DS t
DH t
SRL
(Note t
CSW t
LDACPWL
0
13
13
8 ns
5 ns
10
2 ns
33
33
30 MHz
30 ns ns ns ns ns ns
Note 1:
Note 2:
Note 3:
Note 4:
Note 5:
Note 6:
Note 7:
Note 8:
Note 9:
Static accuracy tested without load.
Linearity is tested within 20mV of GND and AVDD
, allowing for gain and offset error.
Codes above 2047 are guaranteed to be within ±8 LSB
.
Gain and offset tested within 100mV of GND and AVDD
.
Guaranteed by design.
Device draws current in excess of the specified supply current when a digital input is driven with a voltage of VI < V
DVDD
- 0.6V
or VI > 0.5V. At VI = 2.2V with V
DVDD
= 5.25V, this current can be as high as 2mA. The SPI inputs are CMOS-input level compatible. The 30MHz clock frequency cannot be guaranteed for a minimum signal swing.
Excess current from AVDD is 10mA when powered without DVDD. Excess current from DVDD is 1mA when powered without
AVDD.
All timing specifications are with respect to the digital input and output thresholds.
Maximum daisy-chain clock frequency is limited to 25MHz.
t
CSW
COMMAND EXECUTED ON
24TH FALLING EDGE OF SCLK
CS t
CSS t
CL t
CH t
CSH
SCLK
DIN X C7 C6 C5 D3 t
DS t
DH
D2 D1 t
SRL
D0
X
READY
X = DON'T CARE.
Figure 1. Serial-Interface Timing Diagram
Maxim Integrated
MAX5134–MAX5137
Pin-/Software-Compatible,
16-/12-Bit, Voltage-Output DACs
(T
A
= +25°C, unless otherwise noted.)
6
3
0
9
MAX5134/MAX5136 INTEGRAL
NONLINEARITY vs. DIGITAL INPUT CODE
-3
-6
-9
0 16384 32768 49152
DIGITAL INPUT CODE (LSB)
65536
-0.4
-0.6
-0.8
-1.0
0.4
0.2
0
-0.2
1.0
0.8
0.6
0
MAX5134/MAX5136 DIFFERENTIAL
NONLINEARITY vs. DIGITAL INPUT CODE
16384 32768 49152
DIGITAL INPUT CODE (LSB)
65536
10
8
6
4
2
0
-2
-4
-6
-8
-10
2.7
MAX5134/MAX5136 OFFSET ERROR vs. ANALOG SUPPLY VOLTAGE
3.2
3.7
4.2
AVDD ( V )
4.7
5.2
MAX5134/MAX5136 INTEGRAL
NONLINEARITY vs. ANALOG SUPPLY VOLTAGE
9
-1
-3
-5
-7
7
5
3
1
-9
2.7
3.2
3.7
4.2
AVDD ( V )
4.7
5.2
0.4
0.2
0
-0.2
MAX5134/MAX5136 DIFFERENTIAL
NONLINEARITY vs. ANALOG SUPPLY VOLTAGE
1.0
0.8
0.6
-0.4
-0.6
-0.8
-1.0
2.7
3.2
3.7
4.2
AVDD ( V )
4.7
5.2
0.10
0.08
0.06
0.04
0.02
0
-0.02
-0.04
-0.06
-0.08
-0.10
0
MAX5135/MAX5137 DIFFERENTIAL
NONLINEARITY vs. DIGITAL INPUT CODE
1024 2048 3072
DIGITAL INPUT CODE (LSB)
4096
9
7
5
3
1
-1
-3
-5
-7
-9
-40
MAX5134/MAX5136 INTEGRAL
NONLINEARITY vs. TEMPERATURE
-20 0 20 40 60
TEMPERATURE (
°
C)
80 100
0.4
0.2
0
-0.2
1.0
0.8
0.6
-0.4
-0.6
-0.8
-1.0
-40
MAX5134/MAX5136 DIFFERENTIAL
NONLINEARITY vs. TEMPERATURE
-20 0 20 40 60
TEMPERATURE (
°
C)
80 100
0
-0.25
-0.50
-0.75
-1.00
0
1.00
MAX5135/MAX5137 INTEGRAL
NONLINEARITY vs. DIGITAL INPUT CODE
0.75
0.50
0.25
1024 2048 3072
DIGITAL INPUT CODE (LSB)
4096
Maxim Integrated 5
6
MAX5134–MAX5137
Pin-/Software-Compatible,
16-/12-Bit, Voltage-Output DACs
(T
A
= +25°C, unless otherwise noted.)
OFFSET ERROR vs. TEMPERATURE
0
-0.1
-0.2
-0.3
V
V
AVDD
REFI
= 2.7V
= 2.5V
-0.4
-0.5
V
AVDD
= 5.25V
V
REFI
= 5V
-0.6
-40 -20 0 20 40 60
TEMPERATURE (
°
C)
80 100
ANALOG SUPPLY CURRENT vs. ANALOG SUPPLY VOLTAGE
2500
2300
2100
V
OUT_
= V
REFO
(MAX5134/MAX5135)
V
OUT_
= 0 (MAX5134/MAX5135)
1900
1700
1500
V
OUT_
= V
REFO
(MAX5136/MAX5137)
1300
1100
900
2.7
V
OUT_
= 0
(MAX5136/MAX5137)
3.2
3.7
4.2
SUPPLY VOLTAGE (V)
4.7
5.2
EXITING/ENTERING
POWER-DOWN MODE
MAX5134-MAX5137 toc16
0.2
0.1
0
-0.1
0.5
0.4
0.3
-0.2
-0.3
-0.4
-0.5
2.7
3.2
GAIN ERROR vs.
ANALOG SUPPLY VOLTAGE
3.7
4.2
AVDD ( V )
4.7
5.2
ANALOG SUPPLY CURRENT vs. TEMPERATURE
3000
I
AVDD
(MAX5134/MAX5135)
2500
2000
I
AVDD
(MAX5136/MAX5137)
1500
1000
500
I
DVDD
0
-40 -20 0 20 40 60
TEMPERATURE (
°
C)
80 100
GAIN ERROR vs. TEMPERATURE
0.086
0.084
0.082
0.080
0.078
0.076
0.074
0.072
0.070
-40 -20
V
AVDD
= 5.25V
0 20 40 60
TEMPERATURE (
°
C)
V
AVDD
= 2.7V
80 100
ANALOG SUPPLY CURRENT vs. SUPPLY VOLTAGE
(POWER-DOWN MODE)
0.50
0.45
0.40
0.35
0.30
0.25
0.20
0.15
0.10
0.05
0
2.7
T
A
= +105
°
C
3.2
T
T
A
A
= -40
= +25
3.7
4.2
SUPPLY VOLTAGE (V)
°
°
4.7
C
C
5.2
MAJOR CODE TRANSITION
MAX5134-MAX5137 toc17
SETTLING TIME UP
MAX5134-MAX5137 toc18
500mV/div
CH1
10mV/div 500mV/div
500mV/div
CH0
4
μ s/div 1
μ s/div 400ns/div
Maxim Integrated
(T
A
= +25°C, unless otherwise noted.)
MAX5134–MAX5137
Pin-/Software-Compatible,
16-/12-Bit, Voltage-Output DACs
SETTLING TIME DOWN
MAX5134-MAX5137 toc19
CROSSTALK
MAX5134-MAX5137 toc20
10mV/div SCLK
DIGITAL FEEDTHROUGH
MAX5134-MAX5137 toc21
5V/div
500mV/div
2V/div V
OUT_
50mV/div
400ns/div
DIGITAL SUPPLY CURRENT vs.
DIGITAL SUPPLY VOLTAGE
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
2.7
V
AVDD
= 5.25V, SCLK = 0Hz
3.2
3.7
4.2
SUPPLY VOLTAGE (V)
4.7
5.2
1500
1000
500
0
0
3000
DIGITAL SUPPLY CURRENT vs. DIGITAL INPUT VOLTAGE
V
AVDD
= V
DVDD
= 5.25V
2500
UP
2000
DOWN
1 2 3
DIGITAL INPUT VOLTAGE (V)
4 5
Maxim Integrated
4
μ s/div
REFERENCE VOLTAGE vs.
SUPPLY VOLTAGE
2.50
2.48
2.46
2.44
T
A
= +25
°
C
2.42
T
A
= -40
°
C
T
A
= +105
°
C
2.40
2.7
3.2
3.7
4.2
SUPPLY VOLTAGE (V)
4.7
5.2
2.51
2.50
2.49
2.48
2.47
2.46
2.45
2.44
2.43
-40 -20
FULL-SCALE OUTPUT vs. TEMPERATURE
EXTERNAL
REFERENCE
2.500V
INTERNAL
REFERENCE
0 20 40 60
TEMPERATURE (
°
C)
80 100
40ns/div
2.50
2.45
2.40
2.35
2.30
2.25
2.20
2.15
2.10
2.05
2.00
0
REFERENCE VOLTAGE vs. TEMPERATURE
2.4405
2.4400
2.4395
2.4390
2.4385
2.4380
2.4375
2.4370
-40 -20 0 20 40 60
TEMPERATURE (
°
C)
80 100
OUTPUT VOLTAGE vs. OUTPUT CURRENT
V
AVDD
= 5V
V
AVDD
= 3.3V
5 10 15 20
OUTPUT CURRENT (mA)
25 30
7
MAX5134–MAX5137
Pin-/Software-Compatible,
16-/12-Bit, Voltage-Output DACs
(T
A
= +25°C, unless otherwise noted.)
V
OUT_
REF
FULL-SCALE REFERENCE FEEDTHROUGH
MAX5134-MAX5137 toc28
500mV/div
500mV/div
V
REF
0V V
OUT
0V V
REF
V
OUT_
ZERO-SCALE REFERENCE FEEDTHROUGH
MAX5134-MAX5137 toc29
20
μ s/div
500mV/div
10mV/div
5
-10
-15
0
-5
-20
-25
-30
-35
-40
-45
1
REFERENCE INPUT RESPONSE vs. FREQUENCY
10 100 1000
INPUT FREQUENCY (kHz)
10,000
POWER-UP GLITCH, ZERO SCALE,
EXTERNAL REFERENCE
MAX5134-MAX5137 toc31
2V/div
POWER-UP GLITCH, ZERO SCALE,
INTERNAL REFERENCE
MAX5134-MAX5137 toc32
2V/div
POWER-UP GLITCH, MIDSCALE,
EXTERNAL REFERENCE
MAX5134-MAX5137 toc33
2V/div
V
AVDD V
AVDD
V
AVDD
1V/div
V
OUT_
1V/div
V
OUT_
1V/div
V
OUT_
V
AVDD
POWER-UP GLITCH, MIDSCALE,
INTERNAL REFERENCE
MAX5134-MAX5137 toc34
2V/div
1V/div
V
OUT_
DC NOISE SPECTRUM, FFT PLOT
MAX5134-MAX5137 toc35
-40dBm
10dB/div
2.5kHz/div 25kHz
8 Maxim Integrated
MAX5134–MAX5137
Pin-/Software-Compatible,
16-/12-Bit, Voltage-Output DACs
PIN
MAX5134
MAX5135
MAX5136
MAX5137
NAME FUNCTION
TQFN-EP
1
2, 5, 8,
11, 14, 17,
20, 23
3
TSSOP
3
—
TQFN-EP
1
2, 5, 6, 8,
11, 13, 14,
17, 20, 23
3
TSSOP
3
6, 11
4
OUT0
N.C.
Channel 0 Buffered DAC Output
No Connection. Not internally connected.
4 DVDD Digital Power Supply. Bypass DVDD with a 0.1μF capacitor to GND.
Active-Low Ready. Indicated configuration ready. Use
READY
as
CS
for consecutive part or as feedback to the μC.
6
7, 19
6
7, 15
—
7, 19
—
7, 15
OUT3
GND
Channel 3 Buffered DAC Output
Ground
DIN In
10 9 10 9
CS
Active-Low Chip-Select Input
13 —
16 13 16 13 M/
18
24
11
14
2
—
18
24
14
2
OUT2
Z
OUT1
Channel 2 Buffered DAC Output
Load DAC Input. Active-low hardware load DAC input.
Power-Up Reset Select. Connect M/
Z
to V
AVDD
to power up the DAC outputs to midscale. Connect M/
Z
to GND to power up the DAC outputs to zero.
Channel 1 Buffered DAC Output
Reference Output
Reference Voltage Input. Bypass REFI with a 0.1μF capacitor to GND
REFI when using external reference.
AVDD Analog Power Supply. Bypass AVDD with a 0.1μF capacitor to GND.
Exposed Pad. Not internally connected. Connect to a ground or leave unconnected. Not intended as an electrical connection point.
The MAX5134–MAX5137 is a family of pin-compatible and software-compatible 16-bit and 12-bit DACs. The
MAX5134/MAX5135 are low-power, quad 16-/12-bit, buffered voltage-output, high-linearity DACs. The
MAX5136/MAX5137 are low-power, dual 16-/12-bit, buffered voltage-output, high-linearity DACs. The
MAX5134–MAX5137 minimize the digital noise feedthrough from input to output by powering down the
SCLK and DIN input buffers after completion of each 24bit serial input. On power-up, the MAX5134–MAX5137 reset the DAC outputs to zero or midscale, depending on the state of the M/
Z input, providing additional safety for applications that drive valves or other transducers that need to be off on power-up. The MAX5134–MAX5137 contain a segmented resistor string-type DAC, a serial-in parallel-out shift register, a DAC register, power-on reset
(POR) circuit, and control logic. On the falling edge of the clock (SCLK) pulse, the serial input (DIN) data is shifted into the device, MSB first. During power-down, an internal 80k
Ω resistor pulls DAC outputs to GND.
The MAX5134–MAX5137 include internal buffers for all
DAC outputs. The internal buffers provide improved load regulation and transition glitch suppression for the DAC outputs. The output buffers slew at 1.25V/µs and drive up to 2k
Ω in parallel with 200pF. The analog supply voltage
(AVDD) determines the maximum output voltage range of the device as AVDD powers the output buffers.
Internal Reference
The MAX5134–MAX5137 feature an internal reference with a nominal output of +2.44V. Connect REFO to REFI
Maxim Integrated 9
MAX5134–MAX5137
Pin-/Software-Compatible,
16-/12-Bit, Voltage-Output DACs
when using the internal reference. Bypass REFO to
GND with a 47pF (maximum 100pF) capacitor.
Alternatively, if heavier decoupling is required, use a
1k
Ω resistor in series with a 1µF capacitor in parallel with the existing 100pF capacitor. REFO can deliver up to 100µA of current with no degradation in performance. Configure other reference voltages by applying a resistive potential divider with a total resistance greater than 33k
Ω from REFO to GND.
External Reference
The external reference input features a typical input impedance of 113k
Ω and accepts an input voltage from +2V to AVDD. Connect an external voltage supply between REFI and GND to apply an external reference. Leave REFO unconnected. Visit
www.maximintegrated.com/products/references
a list of available external voltage-reference devices.
for
AVDD as Reference
Connect AVDD to REFI to use AVDD as the reference voltage. Leave REFO unconnected.
The MAX5134–MAX5137 3-wire serial interface is compatible with MICROWIRE, SPI, QSPI, and DSPs (Figures
2, 3). The interface provides three inputs, SCLK,
CS
, and DIN and one output,
READY
. Use
READY to verify communication or to daisy-chain multiple devices (see the
READY section).
READY is capable of driving a
20pF load with a 30ns (max) delay from the falling edge of SCLK. The chip-select input (
CS
) frames the serial data loading at DIN. Following a chip-select input’s high-to-low transition, the data is shifted synchronously and latched into the input register on each falling edge of the serial-clock input (SCLK). Each serial word is 24 bits. The first 8 bits are the control word followed by 16 data bits (MSB first), as shown in Table 1. The serial input register transfers its contents to the input registers after loading 24 bits of data. To initiate a new data transfer, drive
CS high, keep
CS high for a minimum of
33ns before the next write sequence. The SCLK can be either high or low between
CS write pulses. Figure 1 shows the timing diagram for the complete 3-wire serialinterface transmission.
24-BIT WORD
CONTROL BITS
MSB
C7 C6 C5 C4 C3 C2
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
1
C1
0
0
1
1
0
DAC
3
DAC
2
DAC
1
DATA BITS
C0 D15 D14 D13 D12 D11 D10 D9
0
1
0
1
1
DAC
0
X
X
X
X
0
X
X
X
X
0
X
X
X
X
0
X
X
X
0
X
DAC
3
X
0
X X
DAC
2
DAC
1
X
0
X
LIN
D15 D14 D13 D12 D11 D10 D9
D8
X
DAC
0
X
D7
X
X
X
X
DAC
3
DAC
2
DAC
1
DAC
0
READY_EN
0
D8
0
D7
X
X
X
0
D6
DESC FUNCTION
LSB
D6–D0
X NOP
LDAC
No operation.
Move contents of input to DAC registers indicated by 1’s. No effect on registers indicated by 0’s.
CLR
Power
Control
Software clear.
Power down DACs indicated by 1’s.
Set READY_EN = 1 to enable
READY
.
Linearity Optimize DAC linearity.
Write
Write to selected input registers (DAC output not affected).
0
0
0
0
1
1
1
0
DAC DAC DAC
3 2 1
0 0 0
DAC
0
D15 D14 D13 D12 D11 D10 D9
0 X X X X X X X
D8
X
D7
X
D6
X
Writethrough
NOP
Write to selected input and DAC registers,
DAC outputs updated
(writethrough).
No operation.
* For the MAX5136/MAX5137, DAC2 and DAC3 do not exist. For the MAX5135/MAX5137, D0–D3 are don’t-care bits.
10 Maxim Integrated
MAX5134–MAX5137
Pin-/Software-Compatible,
16-/12-Bit, Voltage-Output DACs
The MAX5134–MAX5137 digital inputs are double buffered. Depending on the command issued through the serial interface, the input register(s) can be loaded without affecting the DAC register(s) using the write command. To update the DAC registers, either pulse the
LDAC input low to synchronously update all DAC outputs, or use the software
LDAC command. Use the writethrough commands
(see Table 1) to update the DAC outputs immediately after the data is received. Only use the writethrough command to update the DAC output immediately.
The MAX5134/MAX5136 DAC code is unipolar binary with V
OUT_
= (code/65,536) x V
REF
. The MAX5135/
MAX5137 DAC code is unipolar binary with V
OUT_
=
(code/4096) x V
REF
. See Table 1 for the serial interface commands.
Connect the MAX5134–MAX5137 DVDD supply to the supply of the host DSP or microprocessor. The AVDD supply may be set to any voltage within the operating range of 2.7V to 5.25V, but must be greater than or equal to the DVDD supply.
Write to the MAX5134–MAX5137 using the following sequence:
1) Drive
CS low, enabling the shift register.
2) Clock 24 bits of data into DIN (C7 first and D0 last), observing the specified setup and hold times. Bits
D15–D0 are the data bits that are written to the internal register.
3) After clocking in the last data bit, drive
CS high.
CS must remain high for 33ns before the next transmission is started.
Figure 1 shows a write operation for the transmission of
24 bits. If
CS is driven high at any point prior to receiving
24 bits, the transmission is discarded.
+5V
SCLK
MAX5134–
MAX5137
DIN
READY*
SK
SO
MICROWIRE
PORT
SI*
READY*
MAX5134–
MAX5137
DIN
MISO*
SS
MOSI
SPI/QSPI
PORT
SCK
SCLK
CS
I/O
CS
I/O
*THE READY-TO-SI CONNECTION IS NOT REQUIRED FOR WRITING TO THE DEVICES
* BUT MAY BE USED FOR TRANSMISSION VERIFICATION.
Figure 2. Connections for MICROWIRE
*THE READY-TO-MISO CONNECTION IS NOT REQUIRED FOR WRITING TO THE
DEVICES BUT MAY BE USED FOR TRANSMISSION VERIFICATION.
Figure 3. Connections for SPI/QSPI
CS
DIN
SCLK
1 2 3 4
READY 1
READY 2
READY 3
Figure 4.
READY
Timing
SLAVE 1 DATA SLAVE 2 DATA
20 21 22 23 24 1 2 3 4 5
SLAVE 3 DATA
21 22 23 24 1 2 3 4 5 21 22 23 24
Maxim Integrated 11
MAX5134–MAX5137
Pin-/Software-Compatible,
16-/12-Bit, Voltage-Output DACs
Connect
READY to a microcontroller (µC) input to monitor the serial interface for valid communications. The
READY pulse appears 24 clock cycles after the negative edge of
CS
(Figure 4). Since the MAX5134–
MAX5137 look at the first 24 bits of the transmission following the falling edge of
CS
, it is possible to daisy chain devices with different command word lengths.
READY goes high 16ns after
CS is driven high.
Daisy chain multiple MAX5134–MAX5137 devices by connecting the first device conventionally, then connect its
READY output to the
CS of the following device.
Repeat for any other devices in the chain, and drive the
SCLK and DIN lines in parallel (Figure 5). When sending commands to daisy-chained devices, the devices are accessed serially starting with the first device in the chain. The first 24 data bits are read by the first device, the second 24 data bits are read by the second device and so on (Figure 4). Figure 6 shows the configuration when
CS is not driven by the µC. These devices can be daisy chained with other compatible devices such as the
MAX15500 output conditioner.
To perform a daisy-chain write operation, drive
CS low and output the data serially to DIN. The propagation of the
READY signal then controls how the data is read by each device. As the data propagates through the daisy chain, each individual command in the chain is executed on the 24th falling clock edge following the falling edge of the respective
CS input. To update just one device in a daisy chain, send the no-op command to the other devices in the chain.
If
READY is not required, write command 0x03 (power control) and set READY_EN = 0 (see Table 1) to disable the
READY output.
The MAX5134–MAX5137 feature a software clear command (0x02). The software clear command acts as a software POR, erasing the contents of all registers. All outputs return to the state determined by the M/
Z input.
The MAX5134–MAX5137 feature a software-controlled individual power-down mode for each channel. The internal reference and biasing circuits power down to conserve power when all 4 channels are powered down. In power-down, the outputs disconnect from the buffers and are grounded with an internal 80k
Ω resistor. The DAC register holds the retained code so that the output is restored when the channel powers up. The serial interface remains active in power-down mode.
The MAX5134–MAX5137 feature an active-low
LDAC logic input that allows the outputs to update asynchronously. Keep
LDAC high during normal operation
(when the device is controlled only through the serial interface). Drive
LDAC low to simultaneously update all
DAC outputs with data from their respective input registers. Figure 7 shows the
LDAC
OUT_. Holding
LDAC timing with respect to low causes the input registers to become transparent and data written to the DAC registers to immediately update the DAC outputs. A software command can also activate the
LDAC operation. To activate
LDAC by software, set control word 0x01 and data bits A11–A8 to select which DAC to load, and all other data bits to don’t care. See Table 1 for the data format. This operation updates only the DAC outputs that are flagged with a 1. DAC outputs flagged with a 0 remain unchanged.
μ
C
MOSI
SCK
I/O
Figure 5. Daisy-Chain Configuration
12
DIN
SLAVE 1
MAX5134–
MAX5137
SCLK
CS
READY
DIN
SLAVE 2
MAX5134–
MAX5137
SCLK
CS
READY
DIN
SLAVE 3
MAX5134–
MAX5137
SCLK
CS
READY
Maxim Integrated
CSm
μ
C
CS1
CS
SCLK
DWRITE
DREAD
INT
MAX5134–MAX5137
Pin-/Software-Compatible,
16-/12-Bit, Voltage-Output DACs
TO OTHER CHIPS/CHAINS
SLAVE 1
CS
SCLK
DIN
MAX5134–
MAX5137
READY
SLAVE 2
CS
SCLK
DIN
MAX5134–
MAX5137
READY
SLAVE N
CS
SCLK
DIN
DOUT
ERROR
READY
MAX15500
Figure 6. Daisy Chain (
CS
Not Used)
Maxim Integrated 13
MAX5134–MAX5137
Pin-/Software-Compatible,
16-/12-Bit, Voltage-Output DACs
t
LDACPWL
LDAC t
S
±2 LSB
OUT_
Figure 7. Output Timing
On power-up, the input registers are set to zero, DAC outputs power up to zero or midscale, depending on the configuration of M/
Z
. Connect M/
Z to GND to power the outputs to GND. Connect M/
Z to AVDD to power the outputs to midscale.
To guarantee DAC linearity, wait until the supplies have settled. Set the LIN bit in the DAC linearity register; wait
10ms, and clear the LIN bit.
The MAX5134–MAX5137 unipolar output voltage range is 0 to V
REFI
. The output buffers each drive a load of
2k
Ω in parallel with 200pF.
Use the MAX5134–MAX5137 in bipolar applications with additional external components (see the
Typical
Operating Circuit).
For best performance, use a separate supply for the
MAX5134–MAX5137. Bypass both DVDD and AVDD with high-quality ceramic capacitors to a low-impedance ground as close as possible to the device.
Minimize lead lengths to reduce lead inductance.
Connect both MAX5134–MAX5137 GND inputs to the analog ground plane.
DAC LATCH CONTENTS
MSB LSB
1111 1111 1111 1111
1000 0000 0000 0000
0000 0000 0000 0001
0000 0000 0000 0000
ANALOG OUTPUT, V
OUT_
V
REF
x (65,535/65,536)
V
REF
x (32,768/65,536) = 1/2 V
REF
V
REF
x (1/65,536)
0
14
Digital and AC transient signals on GND inputs can create noise at the outputs. Connect both GND inputs to form the star ground for the DAC system. Refer remote
DAC loads to this system ground for the best possible performance. Use proper grounding techniques, such as a multilayer board with a low-inductance ground plane, or star connect all ground return paths back to the MAX5134–MAX5137 GND. Carefully lay out the traces between channels to reduce AC crosscoupling and crosstalk. Do not use wire-wrapped boards and sockets. Use shielding to improve noise immunity. Do not run analog and digital signals parallel to one another (especially clock signals) and avoid routing digital lines underneath the MAX5134–MAX5137 package.
INL is the deviation of the measured transfer function from a best fit straight line drawn between two codes.
For the MAX5134/MAX5136, this best fit line is a line drawn between codes 3072 and 64,512 of the transfer function, once offset and gain errors have been nullified.
For the MAX5135/MAX5137, this best fit line is a line drawn between codes 192 and 4032 of the transfer function, once offset and gain errors have been nullified.
DNL is the difference between an actual step height and the ideal value of 1 LSB. If the magnitude of the
DNL is greater than -1 LSB, the DAC guarantees no missing codes and is monotonic.
DAC LATCH CONTENTS
MSB LSB
1111
1000
1111
0000
1111
0000
XXXX
XXXX
0000
0000
0000
0000
0001
0000
XXXX
XXXX
ANALOG OUTPUT, V
OUT_
V
REF
x (4095/4096)
V
REF
x (2048/4096)
V
REF
x (1/4096)
0
Maxim Integrated
MAX5134–MAX5137
Pin-/Software-Compatible,
16-/12-Bit, Voltage-Output DACs
Offset error indicates how well the actual transfer function matches the ideal transfer function at a single point.
Typically, the point at which the offset error is specified is at or near the zero-scale point of the transfer function.
Gain error is the difference between the ideal and the actual full-scale output voltage on the transfer curve, after nullifying the offset error. This error alters the slope of the transfer function and corresponds to the same percentage error in each step.
The settling time is the amount of time required from the start of a transition, until the DAC output settles to the new output value within the converter’s specified accuracy.
Digital feedthrough is the amount of noise that appears on the DAC output when the DAC digital control lines are toggled.
A major carry transition occurs at the midscale point where the MSB changes from low to high and all other bits change from high to low, or where the MSB changes from high to low and all other bits change from low to high. The duration of the magnitude of the switching glitch during a major carry transition is referred to as the digital-to-analog glitch impulse.
The digital-to-analog power-up glitch is the duration of the magnitude of the switching glitch that occurs as the device exits power-down mode.
Crosstalk is the amount of noise that appears on a DAC output set to 0 when the other DAC is updated from 0 to
AVDD
PROCESS: BiCMOS
TOP VIEW
18 17 16 15 14 13
GND 19
N.C.
20
REF0 21
REFI 22
N.C.
23
AVDD 24
+
1 2
MAX5134–
MAX5137
3 4
*EP
5 6
12 SCLK
11 N.C.
10 CS
9 DIN
8 N.C.
7
GND
REFI 1
AVDD 2
OUT0 3
DVDD 4
READY 5
OUT3 6
GND 7
DIN 8
+
MAX5134–
MAX5137
16 REFO
15 GND
14 OUT1
13 M/Z
12 LDAC
11 OUT2**
10 SCLK
9 CS
TSSOP
*EXPOSED PAD.
**N.C. FOR THE MAX5136/MAX5137.
Maxim Integrated 15
MAX5134–MAX5137
Pin-/Software-Compatible,
16-/12-Bit, Voltage-Output DACs
M/Z
MAX5134
MAX5135
POR
CONTROL LOGIC
AVDD DVDD
GND REFI REFO
REFERENCE
POWER-DOWN
CONTROL
INPUT
REGISTER
DAC
REGISTER
12-/16-BIT
DAC
BUFFER
OUT0
CS
SCLK
DIN
SERIAL-TO-
PARALLEL
CONVERTER
INPUT
REGISTER
DAC
REGISTER
12-/16-BIT
DAC
BUFFER
OUT1
INPUT
REGISTER
DAC
REGISTER
12-/16-BIT
DAC
BUFFER
OUT2
INPUT
REGISTER
DAC
REGISTER
12-/16-BIT
DAC
BUFFER
OUT3
READY
LDAC
16 Maxim Integrated
MAX5134–MAX5137
Pin-/Software-Compatible,
16-/12-Bit, Voltage-Output DACs
M/Z
MAX5136
MAX5137
CS
SCLK
DIN
SERIAL-TO-
PARALLEL
CONVERTER
READY
POR
CONTROL LOGIC
AVDD DVDD
GND
REFI REFO
REFERENCE
POWER-DOWN
CONTROL
INPUT
REGISTER
DAC
REGISTER
12-/16-BIT
DAC
BUFFER
INPUT
REGISTER
DAC
REGISTER
12-/16-BIT
DAC
BUFFER
LDAC
OUT0
OUT1
Maxim Integrated 17
MAX5134–MAX5137
Pin-/Software-Compatible,
16-/12-Bit, Voltage-Output DACs
DIGITAL POWER
SUPPLY
100nF
ANALOG POWER
SUPPLY
100nF
100nF
M/Z
DVDD
LDAC
CS
SCLK
DIN
READY
DAC
MAX5134–
MAX5137
AVDD
OUT
REFO
REFI
GND
47pF
R1 R2
NOTE:
SHOWN IN BIPOLAR CONFIGURATION.
For the latest package outline information and land patterns (footprints), go to
www.maximintegrated.com/packages
“+”, “#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status.
PACKAGE TYPE
24 TQFN-EP
16 TSSOP
PACKAGE CODE
T2444+4
U16+2
OUTLINE NO.
LAND PATTERN NO.
18 Maxim Integrated
MAX5134–MAX5137
Pin-/Software-Compatible,
16-/12-Bit, Voltage-Output DACs
REVISION
NUMBER
0
1
2
3
4
REVISION
DATE
7/08
10/08
1/10
1/13
11/13
DESCRIPTION
Initial release of MAX5134.
Initial release of MAX5135/MAX5136/MAX5137.
Added the TSSOP package to the
Ordering Information
table,
Absolute Maximum Ratings
section, and
Pin Description
table.
Changed the Major Code Transition Analog Glitch Impulse parameter in the
Electrical
Characteristics
table from 12nV
• s (typ) to 25nV
• s (typ).
In the
Typical Operating Characteristics
; added “SCLK = 0Hz” to TOC22, changed
TOC28 to “500mV/div” from “500mV”; and changed the title of TOC30 to “Reference Input
Response vs. Frequency.”
Added a statement to the
Internal Reference
section regarding using a resistor in series.
Changed the
Functional Diagrams
to show
LDAC drawn to the DAC register.
Replaced the
Typical Operating Circuit
to show the correct op amp.
Revised the Absolute Maximum Ratings and added the
Package Thermal Characteristics
section. Updated the
Electrical Characteristics
table.
Revised
Ordering Information
.
PAGES
CHANGED
—
1–19
1, 2, 9
3
7, 8
10
16, 17
18
2–4, 9
1
Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent licenses are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits) shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.
Maxim Integrated 160 Rio Robles, San Jose, CA 95134 USA 1-408-601-1000
© 2013 Maxim Integrated Products, Inc.
19
Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc.
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