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1

SN65HVD11-HT

SLLS934F – NOVEMBER 2008 – REVISED NOVEMBER 2015

SN65HVD11-HT 3.3-V RS-485 Transceiver

1 Features

1

• Operates With a 3.3-V Supply

• Bus-Pin ESD Protection Exceeds 16-kV Human-

Body Model (HBM)

• 1/8 Unit-Load Option Available (up to 256 Nodes on Bus)

• Optional Driver Output Transition Times for

Signaling Rates (1) of 1 Mbps, 10 Mbps, and

32 Mbps

• Based on ANSI TIA/EIA-485-A

• Bus-Pin Short Circuit Protection From

–7 V to 12 V

• Open-Circuit, Idle-Bus, and Shorted-Bus Fail-Safe

Receiver

• Glitch-Free Power-Up and Power-Down Protection for Hot-Plugging Applications

• SN75176 Footprint

• Supports Extreme Temperature Applications:

– Controlled Baselines

– One Assembly and Test Sites

– One Fabrication Sites

– Available in Extreme (–55°C/210°C)

Temperature Range (2)

– Extended Product Life Cycles

– Extended Product-Change Notifications

– Product Traceability

– Texas Instruments' High Temperature

Products Use Highly Optimized Silicon (Die)

Solutions With Design and Process

Enhancements to Maximize Performance Over

Extended Temperatures.

(1) The signaling rate of a line is the number of voltage transitions that are made per second expressed in the units bits per second (bps).

(2) Custom temperature ranges available

2 Applications

• Down-Hole Drilling

• High Temperature Environments

• Digital Motor Controls

• Utility Meters

• Chassis-to-Chassis Interconnects

• Electronic Security Stations

• Industrial Process Controls

• Building Automation

• Point-of-Sale (POS) Terminals and Networks

3 Description

The SN65HVD11-HT device combines a 3-state differential line driver and differential input line receiver that operates with a single 3.3-V power supply. It is designed for balanced transmission lines and meets or exceeds ANSI TIA/EIA-485-A and ISO

8482:1993, with the exception that the thermal shutdown is removed. This differential bus transceiver is a monolithic integrated circuit designed for bidirectional data communication on multipoint bustransmission lines. The driver and receiver have active-high and active-low enables, respectively, that can be externally connected together to function as direction control.

The driver differential outputs and receiver differential inputs connect internally to form a differential input/ output (I/O) bus port that is designed to offer minimum loading to the bus when the driver is disabled or V

CC

= 0.

PART NUMBER

Device Information

(1)

PACKAGE BODY SIZE (NOM)

SN65HVD11-HT

SOIC (8)

CFP (8)

(2)

CFP (8)

(3)

CDIP SB (8)

4.90 mm × 3.91 mm

6.90 mm × 5.65 mm

6.90 mm × 5.65 mm

11.81 mm × 7.49 mm

(1) For all available packages, see the orderable addendum at the end of the data sheet.

(2) HKJ Package

(3) HKQ Package

Typical Application Diagram

R

RE

DE

D D

R

A

B

R

T

A B A B

R

T

A

B

R

D

R

RE

DE

D

R

D

R RE DE D

R

D

R RE DE D

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA.

SN65HVD11-HT

SLLS934F – NOVEMBER 2008 – REVISED NOVEMBER 2015

www.ti.com

1

Features ..................................................................

1

2

Applications ...........................................................

1

3

Description .............................................................

1

4

Revision History.....................................................

2

5

Pin Configuration and Functions .........................

3

6

Specifications.........................................................

4

6.1

Absolute Maximum Ratings ......................................

4

6.2

ESD Ratings..............................................................

5

6.3

Recommended Operating Conditions .......................

5

6.4

Thermal Information ..................................................

5

6.5

Driver Electrical Characteristics ................................

6

6.6

Receiver Electrical Characteristics ...........................

7

6.7

Driver Switching Characteristics ...............................

8

6.8

Receiver Switching Characteristics...........................

9

6.9

Typical Characteristics ............................................

12

7

Parameter Measurement Information ................

14

8

Detailed Description ............................................

19

8.1

Overview .................................................................

19

Table of Contents

8.2

Functional Block Diagram .......................................

19

8.3

Feature Description.................................................

19

8.4

Device Functional Modes........................................

19

9

Application and Implementation ........................

21

9.1

Application Information............................................

21

9.2

Typical Application ..................................................

22

10

Power Supply Recommendations .....................

25

11

Layout...................................................................

25

11.1

Layout Guidelines .................................................

25

11.2

Layout Example ....................................................

25

11.3

Thermal Considerations ........................................

26

12

Device and Documentation Support .................

27

12.1

Community Resources..........................................

27

12.2

Trademarks ...........................................................

27

12.3

Electrostatic Discharge Caution ............................

27

12.4

Glossary ................................................................

27

13 Mechanical, Packaging, and Orderable

Information ...........................................................

27

4 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Revision E (June 2012) to Revision F Page

• Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and

Mechanical, Packaging, and Orderable Information section .................................................................................................

1

2

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5 Pin Configuration and Functions

R

RE

DE

D

D, JD, or HKJ Package

8-Pin SOIC, PDIP, or CFP

Top View

3

4

1

2

6

5

8

7

V

CC

B

A

GND

SN65HVD11-HT

SLLS934F – NOVEMBER 2008 – REVISED NOVEMBER 2015

8

HKQ Package

8-Pin CFP

Top View

1

V

CC

B

A

GND

R

RE

DE

D

5 4

NAME

A

B

D

DE

GND

R

RE

V

CC

PIN

SOIC,

PDIP

6

7

4

3

5

1

2

8

HKQ

4

3

6

7

5

1

2

8

Pin Functions

TYPE DESCRIPTION

Bus input/output Driver output or receiver input (complementary to B)

Bus input/output Driver output or receiver input (complementary to A)

Digital input

Digital input

Reference potential

Driver data input

Active-high driver enable

Local device ground

Digital output

Digital input

Supply

Receive data output

Active-low receiver enable

3-V to 3.6-V supply

BACKSIDE FINISH

Bare Die Information

BACKSIDE

POTENTIAL

Silicon with backgrind GND

BOND PAD

METALLIZATION COMPOSITION

Cu-Ni-Pd

DIE THICKNESS

15 mils.

DESCRIPTION

(1)

R

~RE

DNC

DNC

DE

DNC

DNC

D

DNC

GND

GND

DNC

A

B

DNC

VCC

Bond Pad Coordinates in Microns - Rev A

PAD NUMBER

6

7

8

9

10

1

2

3

4

5

14

15

16

11

12

13

a

69.3

388.75

722.4

891.4

1174.8

1754.35

1907.35

2280.55

2733.5

2691

2535

2253.45

1961.55

799.55

498.35

244.8

(1) DNC = Do Not Connect

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b

372.15

71.5

55.4

55.4

71.5

65.4

65.4

69.5

371.5

1693.1

1693.1

1685.65

1693.1

1693.1

1681.2

1668.5

c

185.3

503.75

839.4

1008.4

1289.8

1869.35

2022.35

2395.55

2848.5

2808

2652

2368.45

2078.55

916.55

613.35

359.8

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d

489.15

186.5

172.4

172.4

186.5

180.4

180.4

184.5

486.5

1810.1

1810.1

1800.65

1810.1

1810.1

1796.2

1783.5

3

SN65HVD11-HT

SLLS934F – NOVEMBER 2008 – REVISED NOVEMBER 2015

DESCRIPTION

(1)

VCC

Bond Pad Coordinates in Microns - Rev A (continued)

PAD NUMBER

17

a

91.8

b

1668.5

c

206.8

www.ti.com

d

1783.5

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)

(1)

I

V

CC

O

Supply voltage

Voltage at A or B

Input voltage at D, DE, R, or RE

Voltage input, transient pulse, A and B, through 100 Ω (see

Figure 20

)

Receiver output current

Continuous total power dissipation

MIN

–0.3

–9

–0.5

–50

MAX

V

CC

6

14

+ 0.5

50

–11

See

Thermal Information

11

(1) All voltage values, except differential I/O bus voltages, are with respect to network ground terminal.

UNIT

V

V

V

V mA

4

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SN65HVD11-HT

SLLS934F – NOVEMBER 2008 – REVISED NOVEMBER 2015

6.2 ESD Ratings

V

(ESD)

Electrostatic discharge

A, B, and GND

Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001

(1)

All pins

Charged-device model (CDM), per JEDEC specification JESD22-C101

(2)

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

VALUE

±16000

±4000

±1000

UNIT

V

6.3 Recommended Operating Conditions

I

I

V

CC

V

I or V

IC

V

IH

V

IL

V

OH

OL

R

C

T

ID

L

L

J

(2)

Supply voltage

Voltage at any bus terminal (separately or common-mode)

High-level input voltage

Low-level input voltage

Differential input voltage

Figure 16

Driver

High-level output current

D, DE, RE

D, DE, RE

Receiver

Driver

Low-level output current

Receiver

Differential load resistance

Differential load capacitance

Signaling rate

Operating junction temperature

T

A

= –55°C to 125°C

T

A

= 175°C

T

A

= 210°C

MIN

3

–7

(1)

2

0

–12

–60

–8

54

NOM

60

50

129

179

214

MAX

3.6

12

V

CC

0.8

12

60

8

10

(1) The algebraic convention, in which the least-positive (most-negative) limit is designated as minimum, is used in this data sheet.

(2) See

Thermal Information

table for information regarding this specification.

UNIT

V

V

V

V

V mA mA

Ω pF

Mbps

°C

6.4 Thermal Information

THERMAL METRIC

(1)

R

θJA

R

θJC(top)

R

θJB

ψ

JT

ψ

JB

R

θJC(bot)

Junction-to-ambient thermal resistance

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case (bottom) thermal resistance

D (SOIC)

8 PINS

101.5

53.6

45.1

4.8

41.8

N/A

SN65HVD11-HT

JD (CDIP SB)

8 PINS

73.9

N/A

39.8

6.9

49.2

9.1

HKJ (CFP)

8 PINS

N/A

N/A

N/A

N/A

N/A

6.2

HKQ (CFP)

8 PINS

170

6.2

195

3.8

146.8

N/A

UNIT

°C/W

°C/W

°C/W

°C/W

°C/W

°C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953 .

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6.5 Driver Electrical Characteristics

over recommended operating conditions (unless otherwise noted)

V

IK

|V

OD

|

PARAMETER

Input clamp voltage

Differential output voltage

TEST CONDITIONS

I

I

= –18 mA

I

O

= 0

R

L

= 54 Ω, See

Figure 10

V test

= –7 V to 12 V,

See

Figure 11

Δ|V

OD

|

V

OC(PP)

V

OC(SS)

ΔV

OC(SS)

I

OZ

Change in magnitude of differential output voltage

Peak-to-peak common mode output voltage

Steady-state common mode output voltage

Change in steady-state common mode output voltage

High-impedance output current

V test

= –7 V to 12 V,

See

Figure 10

and

Figure 11

See

Figure 12

See

Figure 12

See

Figure 12

See receiver input currents

I

I

Input current

D

T

A

= –55°C to 125°C

T

A

= 175°C

(1)

T

A

= 210°C

(2)

I

OS

C

(OD)

DE

Short circuit output current

Differential output capacitance

–7 V ≤ V

O

≤ 12 V

V

OD

= 0.4 sin (4E6

DE = 0 V

πt) + 0.5 V,

I

CC

Supply current

RE = V

CC

D and

,

DE = V

CC,

No load

RE = V

CC

,

D = V

CC

,

DE = 0 V,

No load

RE = 0 V,

D and

DE = V

CC

,

No load

Receiver disabled and driver enabled

Receiver disabled and driver disabled

(standby)

Receiver enabled and driver enabled

T

A

= –55°C to

125°C

T

A

= 175°C

(1)

T

A

= 210°C

(2)

T

A

= –55°C to

125°C

T

A

= 175°C

(1)

T

A

= 210°C

(2)

T

A

= –55°C to

125°C

T

A

= 175°C

(1)

T

A

= 210°C

(2)

MIN

–1.5

2

1

1

–0.2

1.4

–0.06

–100

–100

–100

0

–250

TYP

400

18

11

11.5

14

2.5

20

175

11

11

11

MAX

V

CC

0.2

2.5

0.06

3

100

0

3

250

15.5

17.5

18

20

150

450

15.5

17.5

18

UNIT

V

V

V mV

V

V

μA mA pF mA

μA mA

(1) Minimum and maximum parameters are characterized for operation at T

A

= 175°C but may not be production tested at that temperature.

Production test limits with statistical guardbands are used to ensure high temperature performance.

(2) Minimum and maximum parameters are characterized for operation at T

A

= 210°C but may not be production tested at that temperature.

Production test limits with statistical guardbands are used to ensure high temperature performance.

6

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SN65HVD11-HT

SLLS934F – NOVEMBER 2008 – REVISED NOVEMBER 2015

6.6 Receiver Electrical Characteristics

over recommended operating conditions (unless otherwise noted)

V

IT+

PARAMETER

Positive-going input threshold voltage

I

O

= –8 mA

TEST CONDITIONS

V

IT–

Negative-going input threshold voltage

I

O

= 8 mA

V hys

Hysteresis voltage

(V

IT+

–V

IT–

)

T

A

= –55°C to 125°C

T

A

= 175°C

(1)

T

A

= 210°C

(2)

V

IK

V

OH

V

OL

I

OZ

Enable-input clamp voltage

High-level output voltage

Low-level output voltage

High-impedance state output current

I

I

= –18 mA

V

ID

= 200 mV, I

See

Figure 16

OH

= –8 mA,

V

ID

= –200 mV, I

See

Figure 16

OL

= 8 mA,

V

O

= 0 or V

CC,

RE = V

CC

I

I

I

IH

Bus input current

High-level input current, RE

V

A or V

B

= 12 V

V

A

V

CC or V

B

= 0 V

= 12 V,

V

A or V

B

= –7 V

V

A

V

CC or V

B

= 0 V

= –7 V,

V

IH

= 2 V

Other input at 0 V

T

A

= –55°C to 125°C

T

A

= 175°C

(1)

T

A

= 210°C

(2)

T

A

= –55°C to 125°C

T

A

= 175°C

(1)

T

A

= 210°C

(2)

T

A

= –55°C to 125°C

T

A

= 175°C

(1)

T

A

= 210°C

(2)

T

A

= –55°C to 125°C

T

A

= 175°C

(1)

T

A

= 210°C

(2)

T

A

= –55°C to 125°C

T

A

= 175°C

(1)

T

A

= 210°C

(2)

I

IL

Low-level input current, RE

V

IL

= 0.8 V

C

ID

I

CC

Differential input capacitance

Supply current

V

ID

= 0.4 sin (4E6

DE at 0 V

πt) + 0.5 V,

RE = 0 V,

D and DE = 0 V,

No load

RE = V

CC

,

D = V

CC

,

DE = 0 V,

No load

RE = 0 V,

D and DE = V

CC

,

No load

Receiver enabled and driver disabled

Receiver disabled and driver disabled

(standby)

Receiver enabled and driver enabled

T

A

= –55°C to 125°C

T

A

= 175°C

(1)

T

A

= 210°C

(2)

T

A

= –55°C to 125°C

T

A

= 175°C

(1)

T

A

= 210°C

(2)

T

A

= –55°C to 125°C

T

A

= 175°C

(1)

T

A

= 210°C

(2)

T

A

= –55°C to 125°C

T

A

= 175°C

(1)

T

A

= 210°C

(2)

MIN

–0.2

–1.5

2.4

–1

–0.1

–0.3

–0.3

–0.1

–0.3

–0.3

–30

–30

–30

–30

TYP

2.5

12.5

175

11

11.5

14

15

18

18

5

7.5

7.5

0.075

0.1

0.1

0.085

0.12

0.12

–0.05

–0.15

–0.15

–0.05

–0.15

–0.15

35

41

41

MAX

–0.01

0.4

1

8

8.5

10

20

200

450

15.5

17.5

18

0.11

0.15

0.15

0.13

0.16

0.16

0

3

3

0

UNIT

V

V mV

V

V

V

μA mA

μA

μA pF mA

μA mA

(1) Minimum and maximum parameters are characterized for operation at T

A

= 175°C but may not be production tested at that temperature.

Production test limits with statistical guardbands are used to ensure high temperature performance.

(2) Minimum and maximum parameters are characterized for operation at T

A

= 210°C but may not be production tested at that temperature.

Production test limits with statistical guardbands are used to ensure high temperature performance.

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6.7 Driver Switching Characteristics

over recommended operating conditions (unless otherwise noted) t

PLH

PARAMETER

Propagation delay time, lowto-high-level output

TEST CONDITIONS

t

PHL

Propagation delay time, highto-low-level output t r t f

Differential output signal rise time

Differential output signal fall time

R

L

C

L

= 54 Ω,

= 50 pF,

See

Figure 13

T

A

= –55°C to 125°C

T

A

= 175°C

(1)

T

A

= 210°C

(2)

T

A

= –55°C to 125°C

T

A

= 175°C

(1)

T

A

= 210°C

(2) t sk(p) t sk(pp)

(3) t

PZH t

PHZ t

PZL t

PLZ t

PZH t

PZL

Pulse skew (|t

PHL

– t

PLH

|)

Part-to-part skew (t

PHL or t

PLH

)

Propagation delay time, highR

L impedance to high-level

= 110

RE = 0 V,

Ω, output See

Figure 14

Propagation delay time, highlevel to high-impedance output

Propagation delay time, highimpedance to low-level output

R

L

= 110

RE = 0 V,

Ω,

See

Figure 15

Propagation delay time, lowlevel to high-impedance output

Propagation delay time, standby to high-level output

Propagation delay time, standby to low-level output

R

L

= 110

RE = 3 V,

Ω,

See

Figure 14

R

L

= 110

RE = 3 V,

Ω,

See

Figure 15

MIN

18

18

10

10

10

10

10

10

TYP

25

25

21

22

22

21

22

22

MAX

40

40

30

2.5

11

30

30

30

30

30

55

55

55

75

6

6

UNIT

ns ns ns ns ns ns ns ns ns ns

μs

μs

(1) Minimum and maximum parameters are characterized for operation at T

A

= 175°C but may not be production tested at that temperature.

Production test limits with statistical guardbands are used to ensure high temperature performance.

(2) Minimum and maximum parameters are characterized for operation at T

A

= 210°C but may not be production tested at that temperature.

Production test limits with statistical guardbands are used to ensure high temperature performance.

(3) t sk(pp) is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both devices operate with the same supply voltages, at the same temperature, and have identical packages and test circuits.

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SN65HVD11-HT

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6.8 Receiver Switching Characteristics

over recommended operating conditions (unless otherwise noted) t

PLH

PARAMETER

Propagation delay time, low-to-highlevel output

TEST CONDITIONS

t

PHL

V

ID

C

L

= –1.5 V to 1.5 V,

= 15 pF,

See

Figure 17

t sk(p) t sk(pp)

(1)

Propagation delay time, high-to-lowlevel output

Pulse skew (|t

PHL

– t

PLH

|)

Part-to-part skew t r t f

Output signal rise time

Output signal fall time

C

L

= 15 pF,

See

Figure 17

T

A

= –55°C to

125°C

T

A

= 175°C

(2)

T

A

= 210°C

(3)

T

A

= –55°C to

125°C

T

A

= 175°C

(2)

T

A

= 210°C

(3) t

PZH

(3) t

PZL

(3) t

PHZ t

PLZ

Output enable time to high level

Output enable time to low level

Output disable time from high level

Output disable time from low level

C

L

= 15 pF, DE = 3 V,

See

Figure 18

t

PZH

(1) t

PZL

(1)

Propagation delay time, standby-tohigh-level output

Propagation delay time, standby-tolow-level output

C

L

= 15 pF, DE = 0,

See

Figure 19

MIN

30

30

1

1

1

1

1

1

TYP

55

55

3

4

4

3

4

4

MAX

70

5

15

20

15

5

5

15

5

5

5

70

4

15

6

6

UNIT

ns ns ns ns ns ns ns ns ns ns

μs

μs

(1) t sk(pp) is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both devices operate with the same supply voltages, at the same temperature, and have identical packages and test circuits.

(2) Minimum and maximum parameters are characterized for operation at T

A

= 175°C but may not be production tested at that temperature.

Production test limits with statistical guardbands are used to ensure high temperature performance.

(3) Minimum and maximum parameters are characterized for operation at T

A

= 210°C but may not be production tested at that temperature.

Production test limits with statistical guardbands are used to ensure high temperature performance.

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SLLS934F – NOVEMBER 2008 – REVISED NOVEMBER 2015 xxx

1000000

100000

Electromigration Fail Mode

10000

Wirebond Fail Mode

1000

110 120 130 140 150 160 170

Continuous T

J

(°C)

180 190 200 210

(1) See data sheet for absolute maximum and minimum recommended operating conditions.

(2) Silicon operating life design goal is 10 years at 105°C junction temperature (does not include package interconnect life).

(3) The predicted operating lifetime vs. junction temperature is based on reliability modeling using electromigration as the dominant failure mechanism affecting device wearout for the specific device process and design characteristics.

(4) Wirebond fail mode applicable for D package only.

(5) Wirebond life approaches 0 hours < 200°C which is only true of the HD device.

Figure 1. SN65HVD11SJD/SKGDA/SHKJ/SHKQ/HD

Operating Life Derating Chart

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SN65HVD11-HT

SLLS934F – NOVEMBER 2008 – REVISED NOVEMBER 2015

D

0 or 3 V

DE

Input

Generator

V

50 W

Y

V

OD

60 W

±

1%

Z

-7 V < V

(TEST)

< 12 V

50% t pZH

(diff)

V

OD

(high)

1.5 V

0 V t pZL

(diff)

-1.5 V

V

OD

(low)

Note: The time t pZL

(x) is the measure from DE to V

OD

(x). V

OD is valid when it is greater than 1.5 V.

Figure 2. Driver Enable Time From De to V

OD

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6.9 Typical Characteristics

70

T

A

= 25°C

RE at V

CC

DE at V

CC

60

R

L

C

L

= 54 W

= 50 pF

V

CC

= 3.6 V

50

V

CC

= 3.3 V

V

CC

= 3 V

I CC

40

30

0 2.5

5

Signaling Rate − Mbps

7.5

10

Figure 3. RMS Supply Current vs Signaling Rate

150

100

T

A

= 25°C

DE at V

CC

D at V

CC

V

CC

= 3.3 V

50

0

−50

−100

I OH

−150

−200

−4

V

OH

−2 0 2 4

− Driver High-Level Output Voltage − V

6

Figure 5. High-Level Output Current vs Driver High-Level

Output Voltage

2.5

2.4

2.3

V

CC

= 3.3 V

V

Test

= 12 V

2.2

2.1

2.0

1.9

1.8

1.7

1.6

1.5

-100 -50 0 50 100 150

T

A

– Free-Air Temperature – °C

200 250

Figure 7. Driver Differential Output vs Free-Air Temperature www.ti.com

I I

30

20

10

0

−10

60

50

40

90

80

70

T

A

= 25°C

DE at 0 V

V

CC

= 0 V

V

CC

= 3.3 V

−20

−30

−40

−50

−60

−7−6 −5 −4 −3 −2 −1 0 1 2 3 4 5 6 7 8 9 10 11 12

V

I

− Bus Input Voltage − V

Figure 4. Bus Input Current vs Bus Input Voltage

200

180

160

140

120

100

T

A

= 25°C

DE at V

CC

D at 0 V

V

CC

= 3.3 V

I OL

80

60

40

20

0

−20

−4 −2 0 2 4 6

V

OL

− Driver Low-Level Output Voltage − V

8

Figure 6. Low-Level Output Current vs Driver Low-Level

Output Voltage

−40

−35

T

A

= 25°C

DE at V

CC

D at V

CC

R

L

= 54 W

−30

−25

−20

−15

I O

−10

−5

0

0 0.50

1 1.50

2 2.50

V

CC

− Supply Voltage − V

3 3.50

Figure 8. Driver Output Current vs Supply Voltage

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Typical Characteristics (continued)

600

500

400

SN65HVD11-HT

SLLS934F – NOVEMBER 2008 – REVISED NOVEMBER 2015

300

200

100

0

-7 -2 3 8

V

(TEST)

− Common-Mode Voltage − V

13

Figure 9. Enable Time vs Common Mode Voltage (See

Figure 2

)

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SLLS934F – NOVEMBER 2008 – REVISED NOVEMBER 2015

7 Parameter Measurement Information

I

I

V

CC

DE

A

0 or 3 V

B

V

I

I

OA

I

OB

V

OB

V

OA

V

OD

54 Ω ±1%

www.ti.com

Figure 10. Driver V

OD

Test Circuit and Voltage and Current Definitions

0 or 3 V

D

V

CC

DE

A

B

V

OD

375 Ω ±1%

60 Ω ±1%

+

_

−7 V < V

(test)

< 12 V

375 Ω ±1%

Figure 11. Driver V

OD

With Common Mode Loading Test Circuit

Input

D

V

CC

DE

A

27 Ω ± 1%

B

27 Ω ± 1%

C

L

= 50 pF ±20%

V

OC

A

B

V

OC

V

OC(PP)

V

A

V

B

∆V

OC(SS)

A.

B.

Input: PRR = 500 kHz, 50% Duty Cycle, t r

<6ns, t f

<6ns, Z

O

= 50

C

L

Includes fixture and instrumentation capacitance

Figure 12. Test Circuit and Definitions for Driver Common Mode Output Voltage

Input

Generator

V

I

D

V

CC

DE

A

50

B

R

L

= 54

±

1%

V

OD

C

L

= 50 pF

±

20%

C

L

Includes Fixture and Instrumentation

Capacitance

V

I

V

OD t

PLH

0 V

10% t r

1.5 V

90% t

PHL

90%

Generator: PRR = 500 kHz, 50% Duty Cycle, t r

<6 ns, t f

<6 ns, Z o

= 50

Figure 13. Driver Switching Test Circuit and Voltage Waveforms

t f

1.5 V

3 V

2 V

0 V

10%

–2 V

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SN65HVD11-HT

SLLS934F – NOVEMBER 2008 – REVISED NOVEMBER 2015

Parameter Measurement Information (continued)

Input

Generator

V

I

A

3 V

D

S1

DE

B

C

L

= 50 pF

±

20%

50

C

L

Includes Fixture and Instrumentation

Capacitance

V

O

R

L

= 110

±

1%

V

I

V

O t

PZH

1.5 V

2.3 V

1.5 V

0.5 V

0 V t

PHZ

Generator: PRR = 500 kHz, 50% Duty Cycle, t r

<6 ns, t f

<6 ns, Z o

= 50

Figure 14. Driver High-Level Enable and Disable Time Test Circuit and Voltage Waveforms

3 V

V

OH

0 V

Input

Generator

V

3 V

I

A

S1

D

B

DE

C

L

= 50 pF

±

20%

50

C

L

Includes Fixture and Instrumentation

Capacitance

3 V

R

L

= 110

±

1%

V

O

V

I

V

O t

PZL

1.5 V

2.3 V t

PLZ

1.5 V

3 V

0 V

0.5 V

3 V

V

OL

Generator: PRR = 500 kHz, 50% Duty Cycle, t r

<6 ns, t f

<6 ns, Z o

= 50

Figure 15. Driver Low-Level Output Enable and Disable Time Test Circuit and Voltage Waveforms

V

A

+ V

B

2

V

IC

V

A

V

B

I

A

V

ID

I

B

A

B

R

I

O

V

O

Figure 16. Receiver Voltage and Current Definitions

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SLLS934F – NOVEMBER 2008 – REVISED NOVEMBER 2015

Parameter Measurement Information (continued)

A

R

V

O

Input

Generator

V

I

50

1.5 V

B

0 V

RE

C

L

= 15 pF

±

20%

C

L

Includes Fixture and Instrumentation

Capacitance

Generator: PRR = 500 kHz, 50% Duty Cycle, t r

<6 ns, t f

<6 ns, Z o

= 50

3 V

V

I

1.5 V 1.5 V

0 V

V

O t

PLH

1.5 V

10% t r t

PHL

90% 90% t f

V

OH

1.5 V

10%

V

OL

Figure 17. Receiver Switching Test Circuit and Voltage Waveforms

0 V or 3 V

D

3 V

DE

Input

Generator

V

I

A

B

50

R

RE

V

O

1 k

Ω ±

1%

C

L

= 15 pF

±

20%

C

L

Includes Fixture and Instrumentation

Capacitance

3 V

A

S1

B www.ti.com

Generator: PRR = 500 kHz, 50% Duty Cycle, t r

<6 ns, t f

<6 ns, Z o

= 50

3 V

V

I

1.5 V 1.5 V

0 V t

PZH(1) t

PHZ

V

OH

–0.5 V

V

OH

V

O

1.5 V

0 V

D at 3 V

S1 to B

V

O t

PZL(1)

1.5 V t

PLZ

3 V

D at 0 V

S1 to A

V

OL

+0.5 V

V

OL

Figure 18. Receiver Enable and Disable Time Test Circuit and Voltage Waveforms With Drivers Enabled

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SN65HVD11-HT

SLLS934F – NOVEMBER 2008 – REVISED NOVEMBER 2015

Parameter Measurement Information (continued)

0 V or 1.5 V

1.5 V or 0 V

Input

Generator

V

I

A

B

50

R

V

O

RE

1 k

Ω ±

1%

C

L

= 15 pF

±

20%

C

L

Includes Fixture and Instrumentation

Capacitance

3 V

A

S1

B

Generator: PRR = 100 kHz, 50% Duty Cycle, t r

<6 ns, t f

<6 ns, Z o

= 50

3 V

V

I

1.5 V

0 V t

PZH(2)

V

O

V

OH

1.5 V

A at 1.5 V

B at 0 V

S1 to B

GND t

PZL(2)

V

O

1.5 V

3 V

V

OL

A at 0 V

B at 1.5 V

S1 to A

Figure 19. Receiver Enable Time From Standby (Driver Disabled)

A

0 V or 3 V

RE

R

B

+

_

100

±

1%

Pulse Generator,

15

µ

s Duration,

1% Duty Cycle t r

, t f

100 ns

D

DE

3 V or 0 V

NOTE

:

This test is conducted to test survivability only. Data stability at the R output is not specified.

Figure 20. Test Circuit, Transient Overvoltage Test

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Parameter Measurement Information (continued)

D and RE Inputs DE Input

V

CC

Input

100 kΩ

1 kΩ

9 V

Input

1 kΩ

9 V

100 kΩ

V

CC www.ti.com

A Input

Input

16 V

16 V

R3

R2

R1

V

CC

Input

16 V

R3

16 V

R2

B Input

R1

V

CC

A and B Outputs

16 V

Output

16 V

V

CC

R Output

V

CC

5 Ω

Output

9 V

R1/R2 = 36 kΩ

R3 = 180 kΩ

Figure 21. Equivalent Input and Output Schematic Diagrams

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8 Detailed Description

SN65HVD11-HT

SLLS934F – NOVEMBER 2008 – REVISED NOVEMBER 2015

8.1 Overview

The SN65HVD11-HT device is a 3.3 V, half-duplex, RS-485 transceiver available in 3 speed grades suitable for data transmission up to 32 Mbps, 10 Mbps, and 1 Mbps, respectively.

The device has active-high driver enables and active-low receiver enables. A standby current of less than

5 µA can be achieved by disabling both driver and receiver.

8.2 Functional Block Diagram

8.3 Feature Description

Internal ESD protection circuits protect the transceiver bus terminals against ±16-kV Human Body Model (HBM) electrostatic discharges and ±4-kV electrical fast transients (EFT) according to IEC61000-4-4.

The SN65HVD11-HT half-duplex device provides internal biasing of the receiver input thresholds for open-circuit, bus-idle, or short circuit failsafe conditions, and a typical receiver hysteresis of 35 mV.

8.4 Device Functional Modes

When the driver enable pin, DE, is logic high, the differential outputs A and B follow the logic states at data input

D. A logic high at D causes A to turn high and B to turn low. In this case the differential output voltage defined as

V

OD

= V negative.

A

– V

B is positive. When D is low, the output states reverse, B turns high, A becomes low, and V

OD is

When DE is low, both outputs turn high-impedance. In this condition the logic state at D is irrelevant. The DE pin has an internal pulldown resistor to ground; thus, when left open, the driver is disabled (high-impedance) by default. The D pin has an internal pullup resistor to V

CC

; thus, when left open while the driver is enabled, output A turns high and B turns low.

INPUT

D

H

L

X

X

OPEN

ENABLE

DE

H

H

L

OPEN

H

Table 1. Driver Functions

(1)

Z

Z

H

A

H

L

OUTPUTS

Z

Z

L

B

L

H

FUNCTION

Actively drive bus High

Actively drive bus Low

Driver disabled

Driver disabled by default

Actively drive bus High by default

(1) H = high level; L = low level; Z = high impedance; X = irrelevant; ? = indeterminate

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When the receiver enable pin, RE, is logic low, the receiver is enabled. When the differential input voltage defined as V

ID

= V

A

– V

B is positive and higher than the positive input threshold, V

IT+

, the receiver output, R, turns high. When V low. If V

ID

ID is negative and lower than the negative input threshold, V

IT– is between V

IT+ and V

IT–

, the output is indeterminate.

, the receiver output, R, turns

When RE is logic high or left open, the receiver output is high-impedance and the magnitude and polarity of V

ID are irrelevant. Internal biasing of the receiver inputs causes the output to go failsafe-high when the transceiver is disconnected from the bus (open-circuit), the bus lines are shorted (short-circuit), or the bus is not actively driven

(idle bus).

DIFFERENTIAL INPUT

V

ID

= V

A

– V

B

V

ID

> V

IT+

V

IT–

< V

ID

< V

IT+

V

ID

< V

IT–

X

X

Open-circuit bus

Short circuit bus

Table 2. Receiver Functions

(1)

ENABLE

RE

L

L

L

H

OPEN

L

L

OUTPUT

R

H

Z

Z

?

L

H

H

FUNCTION

Receive valid bus High

Indeterminate bus state

Receive valid bus Low

Receiver disabled

Receiver disabled by default

Fail-safe high output

Fail-safe high output

(1) H = high level; L = low level; Z = high impedance; X = irrelevant; ? = indeterminate

8.4.1 Low-Power Standby Mode

When both the driver and receiver are disabled (DE low and RE high) the device is in standby mode. If the enable inputs are in this state for less than 60 ns, the device does not enter standby mode. This guards against inadvertently entering standby mode during driver or receiver enabling. Only when the enable inputs are held in this state for 300 ns or more, the device is assured to be in standby mode. In this low-power standby mode, most internal circuitry is powered down, and the supply current is typically less than 1 µA. When either the driver or the receiver is reenabled, the internal circuitry becomes active.

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9 Application and Implementation

SN65HVD11-HT

SLLS934F – NOVEMBER 2008 – REVISED NOVEMBER 2015

NOTE

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.

9.1 Application Information

The SN65HVD11-HT is a half-duplex RS-485 transceiver commonly used for asynchronous data transmissions.

The driver and receiver enable pins allow for the configuration of different operating modes.

R

RE

DE

D

D

R

A

B

R

RE

DE

D

D

R

A

B

R

RE

DE

D

D

R

A

B a) Independent driver and receiver enable signals b) Combined enable signals for use as directional control pin c) Receiver always on

Figure 22. Half-Duplex Transceiver Configurations

a. Using independent enable lines provides the most flexible control as it allows for the driver and the receiver to be turned on and off individually. While this configuration requires two control lines, it allows for selective listening into the bus traffic, whether the driver is transmitting data or not.

b. Combining the enable signals simplifies the interface to the controller by forming a single direction-control signal. In this configuration, the transceiver operates as a driver when the direction-control line is high, and as a receiver when the direction-control line is low.

c. Only one line is required when connecting the receiver-enable input to ground and controlling only the driverenable input. In this configuration, a node not only receives the data from the bus, but also the data it sends and can verify that the correct data have been transmitted.

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9.2 Typical Application

An RS-485 bus consists of multiple transceivers connected in parallel to a bus cable. To eliminate line reflections, each cable end is terminated with a termination resistor, R

T impedance, Z

0

, whose value matches the characteristic

, of the cable. This method, known as parallel termination, allows for higher data rates over a longer cable length.

R

RE

DE

D D

R

A

B

R

T

A B A B

R

T

A

B

R

D

R

RE

DE

D

R R

R RE DE D R RE DE D

Figure 23. Typical RS-485 Network With Half-Duplex Transceivers

9.2.1 Design Requirements

RS-485 is a robust electrical standard suitable for long-distance networking that may be used in a wide range of applications with varying requirements, such as distance, data rate, and number of nodes.

9.2.1.1 Data Rate and Bus Length

There is an inverse relationship between data rate and bus length, meaning the higher the data rate, the shorter the cable length; and conversely, the lower the data rate, the longer the cable may be without introducing data errors. While most RS-485 systems use data rates between 10 kbps and 100 kbps, some applications require data rates up to 250 kbps at distances of 4000 feet and longer. Longer distances are possible by allowing for small signal jitter of up to 5 or 10%.

10000

5%, 10%, and 20% Jitter

1000

D D

Conservative

Characteristics

100

10

100 1k 10k 100k

Data Rate (bps)

1M 10M 100M

Figure 24. Cable Length vs Data Rate Characteristic

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SN65HVD11-HT

SLLS934F – NOVEMBER 2008 – REVISED NOVEMBER 2015

Typical Application (continued)

9.2.1.2 Stub Length

When connecting a node to the bus, the distance between the transceiver inputs and the cable trunk, known as the stub, should be as short as possible. Stubs present a nonterminated piece of bus line which can introduce reflections as the length of the stub increases. As a general guideline, the electrical length, or round-trip delay, of a stub should be less than one-tenth of the rise time of the driver, thus giving a maximum physical stub length as shown in

Equation 1 .

L

(STUB)

≤ 0.1 × t r

× v × c where

• t r is the 10/90 rise time of the driver

v is the signal velocity of the cable or trace as a factor of c

c is the speed of light (3 × 10

8 m/s) (1)

Per

Equation 1 , Table 3

lists the maximum cable-stub lengths for the minimum-driver output rise-times of the

SN65HVD1x full-duplex family of transceivers for a signal velocity of 78%.

DEVICE

Table 3. Maximum Stub Length

MINIMUM DRIVER OUTPUT

RISE TIME (ns)

10

MAXIMUM STUB LENGTH

(m) (ft)

0.23

0.75

SN65HVD11-HT

9.2.1.3 Bus Loading

The RS-485 standard specifies that a compliant driver must be able to driver 32 unit loads (UL), where 1 unit load represents a load impedance of approximately 12 k Ω. Because the SN65HVD11-HT and HVD12 are each

1/8 UL transceivers, it is possible to connect up to 256 receivers to the bus. The SN65HVD11-HT is a 1/4 UL transceiver, and up to 64 receivers may be connected to the bus.

9.2.1.4 Receiver Failsafe

The differential receivers of the SN65HVD11-HT are failsafe to invalid bus states caused by:

• Open bus conditions, such as a disconnected connector

• Shorted bus conditions, such as cable damage shorting the twisted-pair together

• Idle bus conditions that occur when no driver on the bus is actively driving.

In any of these cases, the differential receiver will output a failsafe logic High state so that the output of the receiver is not indeterminate.

Receiver failsafe is accomplished by offsetting the receiver thresholds such that the input indeterminate range does not include zero volts differential. To comply with the RS-422 and RS-485 standards, the receiver output must output a High when the differential input V

ID is more positive than 200 mV, and must output a Low when V

ID is more negative than –200 mV. The receiver parameters which determine the failsafe performance are V

IT(+)

V

IT(–) and

. As shown in

Receiver Electrical Characteristics

, differential signals more negative than –200 mV will

always cause a Low receiver output, and differential signals more positive than 200 mV will always cause a High receiver output.

When the differential input signal is close to zero, it is still above the maximum V

IT(+) the receiver output will be High.

threshold of –10 mV, and

9.2.2 Detailed Design Procedure

To protect bus nodes against high-energy transients, the implementation of external transient protection devices is therefore necessary.

Figure 25

shows a protection circuit against 10-kV ESD (IEC 61000-4-2), 4-kV EFT (IEC

61000-4-4), and 1-kV surge (IEC 61000-4-5) transients.

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SLLS934F – NOVEMBER 2008 – REVISED NOVEMBER 2015

RxD

MCU

DIR

TxD

Vcc

10k

1

R Vcc

8

Vcc

0.1μF

2

RE

3

DE

XCVR

A

B

7

6

4

D GND

5

10k

R1

TVS

R2

Figure 25. Transient Protection Against ESD, EFT, and Surge Transients

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DEVICE

XCVR

R1, R2

TVS

Table 4. Bill of Materials

FUNCTION

3.3-V, full-duplex RS-485 transceiver

10Ω, pulse-proof, thick-film resistor

Bidirectional 400-W transient suppressor

ORDER NUMBER

SN65HVD11-HT

CRCW0603010RJNEAHP

CDSOT23-SM712

MANUFACTURER

TI

Vishay

Bourns

9.2.3 Application Curve

Figure 26

demonstrates operation of the SN65HVD11-HT at a signaling rate of 250 kbps. Two SN65HVD11-HT transceivers are used to transmit data through a 2000 foot (600 m) segment of Commscope 5524 category 5e+ twisted pair cable. The bus is terminated at each end by a 100Ω resistor, matching the cable characteristic impedance.

Driver Input

Driver Output

Receiver Input

Receiver Output

Figure 26. SN65HVD11-HT Input and Output Through 2000 Feet of Cable

24

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SN65HVD11-HT

SLLS934F – NOVEMBER 2008 – REVISED NOVEMBER 2015

10 Power Supply Recommendations

To assure reliable operation at all data rates and supply voltages, each supply must be buffered with a 100-nF ceramic capacitor located as close to the supply pins as possible. The TPS76333 linear voltage regulator is suitable for the 3.3-V supply.

11 Layout

11.1 Layout Guidelines

On-chip IEC-ESD protection is sufficient for laboratory and portable equipment but never sufficient for EFT and surge transients occurring in industrial environments. Therefore, robust and reliable bus node design requires the use of external transient protection devices.

Because ESD and EFT transients have a wide frequency bandwidth from approximately 3 MHz to 3 GHz, highfrequency layout techniques must be applied during PCB design.

1. Place the protection circuitry close to the bus connector to prevent noise transients from entering the board.

2. Use V

CC and ground planes to provide low-inductance. High-frequency currents follow the path of least inductance and not the path of least impedance.

3. Design the protection components into the direction of the signal path. Do not force the transient currents to divert from the signal path to reach the protection device.

4. Apply 100-nF to 220-nF bypass capacitors as close as possible to the V

CC controller ICs on the board.

pins of transceiver, UART, and

5. Use at least two vias for V

CC minimize effective via-inductance.

and ground connections of bypass capacitors and protection devices to

6. Use 1-k Ω to 10-kΩ pullup or pulldown resistors for enable lines to limit noise currents in these lines during transient events.

7. Insert pulse-proof series resistors into the A and B bus lines if the TVS clamping voltage is higher than the specified maximum voltage of the transceiver bus terminals. These resistors limit the residual clamping current into the transceiver and prevent it from latching up.

8. While pure TVS protection is sufficient for surge transients up to 1 kV, higher transients require metal-oxide varistors (MOVs) which reduce the transients to a few hundred volts of clamping voltage, and transient blocking units (TBUs) that limit transient current to less than 1 mA.

11.2 Layout Example

5

R

C

4

Via to ground

Via to V

CC

MCU

6

R

6

R

XCVR

R

7

R

R

5

5

1

TVS

Figure 27. SN65HVD11-HT Layout Example

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SN65HVD11-HT

SLLS934F – NOVEMBER 2008 – REVISED NOVEMBER 2015

www.ti.com

11.3 Thermal Considerations

R

θJA

(Junction-to-Ambient Thermal Resistance) is defined as the difference in junction temperature to ambient

temperature divided by the operating power.

R

θJA is not a constant and is a strong function of:

• the PCB design (50% variation)

• altitude (20% variation)

• device power (5% variation)

R

θJA can be used to compare the thermal performance of packages if the specific test conditions are defined and used. Standardized testing includes specification of PCB construction, test chamber volume, sensor locations, and the thermal characteristics of holding fixtures.

temperatures for other installations.

θ

JA is often misused when it is used to calculate junction

TI uses two test PCBs as defined by JEDEC specifications. The low-k board gives average in-use condition thermal performance, and it consists of a single copper trace layer 25-mm long and 2-oz thick. The high-k board gives best case in-use condition, and it consists of two 1-oz buried power planes with a single copper trace layer

25-mm long and 2-oz thick. A 4% to 50% difference in θ

JA can be measured between these two test cards.

R

θJC

(Junction-to-Case Thermal Resistance) is defined as difference in junction temperature to case divided

by the operating power. It is measured by putting the mounted package up against a copper block cold plate to force heat to flow from die, through the mold compound into the copper block.

R

θJC is a useful thermal characteristic when a heatsink is applied to package. It is not a useful characteristic to predict junction temperature because it provides pessimistic numbers if the case temperature is measured in a nonstandard system and junction temperatures are backed out. It can be used with θ

JB simulation of a package system.

in 1-dimensional thermal

R

θJB

(Junction-to-Board Thermal Resistance) is defined as the difference in the junction temperature and the

PCB temperature at the center of the package (closest to the die) when the PCB is clamped in a cold-plate structure.

θ

JB is only defined for the high-k test card.

R

θJB provides an overall thermal resistance between the die and the PCB. It includes a bit of the PCB thermal resistance (especially for BGA’s with thermal balls) and can be used for simple 1-dimensional network analysis of package system, see

Figure 28 .

Figure 28. Thermal Resistance

26

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12 Device and Documentation Support

SN65HVD11-HT

SLLS934F – NOVEMBER 2008 – REVISED NOVEMBER 2015

12.1 Community Resources

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of

Use .

TI E2E™ Online Community

TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers.

Design Support

TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support.

12.2 Trademarks

E2E is a trademark of Texas Instruments.

All other trademarks are the property of their respective owners.

12.3 Electrostatic Discharge Caution

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.

12.4 Glossary

SLYZ022 — TI Glossary.

This glossary lists and explains terms, acronyms, and definitions.

13 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

Copyright © 2008–2015, Texas Instruments Incorporated

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PACKAGE OPTION ADDENDUM

www.ti.com

2-Oct-2015

PACKAGING INFORMATION

Orderable Device

SN65HVD11HD

Status

(1)

ACTIVE

ACTIVE

Package Type Package

Drawing

Pins Package

Qty

SOIC

CFP

D

HKJ

8

8

75

1

Eco Plan

(2)

Green (RoHS

& no Sb/Br)

TBD

Lead/Ball Finish

(6)

CU NIPDAU

MSL Peak Temp

(3)

Level-1-260C-UNLIM

Op Temp (°C)

-55 to 175 HD11

Device Marking

(4/5)

SN65HVD11SHKJ

SN65HVD11SHKQ

SN65HVD11SJD

ACTIVE

ACTIVE

CFP

CDIP SB

HKQ

JDJ

8

8

1

1

TBD

TBD

Call TI

AU

POST-PLATE

N / A for Pkg Type

N / A for Pkg Type

N / A for Pkg Type

-55 to 210

-55 to 210

-55 to 210

SN65HVD11S

HKJ

HVD11S

HKQ

SN65HVD11SJD

SN65HVD11SKGDA ACTIVE XCEPT KGD 0 130 TBD Call TI N / A for Pkg Type -55 to 210

(1)

The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2)

Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

(3)

MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)

There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)

Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device.

Samples

Addendum-Page 1

PACKAGE OPTION ADDENDUM

www.ti.com

2-Oct-2015

(6)

Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

OTHER QUALIFIED VERSIONS OF SN65HVD11-HT :

Catalog: SN65HVD11

NOTE: Qualified Version Definitions:

Catalog - TI's standard catalog product

Addendum-Page 2

IMPORTANT NOTICE

Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All semiconductor products (also referred to herein as “components”) are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment.

TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms and conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where mandated by applicable law, testing of all parameters of each component is not necessarily performed.

TI assumes no liability for applications assistance or the design of Buyers’ products. Buyers are responsible for their products and applications using TI components. To minimize the risks associated with Buyers’ products and applications, Buyers should provide adequate design and operating safeguards.

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