OPERATION GUIDE

UHF Narrow band radio transceiver

STD-302S

429 MHz

Operation Guide

Version 1.1 (Apr. 2015)



This product requires electrical and radio knowledge for setup and operation.



To ensure proper and safe operation, please read this operation guide thoroughly prior to use.



Please keep this operation guide for future reference.

CIRCUIT DESIGN, INC.,

7557-1 Hotaka, Azumino

Nagano 399-8303 JAPAN

Tel: + +81-(0)263-82-1024

Fax: + +81-(0)263-82-1016 e-mail: [email protected]

http://www.circuitdesign.jp

OG_STD-302S-429M_v11e

OPERATION GUIDE

CONTENTS

GENERAL DESCRIPTION & FEATURES ...........................3

SPECIFICATIONS STD-302S 429 MHz ...........................4

PIN DESCRIPTION .............................................................6

BLOCK DIAGRAM...............................................................9

DIMENSIONS....................................................................10

PLL IC CONTROL ............................................................. 11

PLL IC control

.................................................................. 11

How to calculate the setting values for the PLL register

........12

Method of serial data input to the PLL

.................................13

TIMING CHART.................................................................14

PLL FREQUENCY SETTING REFERENCE .....................16

TEST DATA .......................................................................18

CAUTIONS & WARNINGS ................................................19

OG_STD-302S-429M_v11e 2 Circuit Design, Inc.

OPERATION GUIDE

GENERAL DESCRIPTION & FEATURES

General Description

The UHF FM narrow band semi-duplex radio data module STD-302S is a high performance transceiver designed for use in industrial applications requiring long range, high performance and reliability.

All high frequency circuits are enclosed inside a robust housing to provide superior resistance against shock and vibration. A narrow band technique enables high interference rejection and concurrent operation with multiple modules.

STD-302S 429 MHz, a narrowband module with 12.5 kHz channel steps, achieves high TX/RX switching speed, making it an ideal RF unit for inclusion in feedback systems.

This product is designed to meet the basic specifications of Japanese ARIB STD-T67 standard, however it has not been certified for conformity with the technical regulations. Users are required to perform the procedures for certification with their final products after installing this product in their systems.

Features



10 mW RF power, 3.0 V operation



Programmable RF channel



Fast TX/RX switching time



High sensitivity -120 dBm



Excellent mechanical durability, high vibration & shock resistance



ARIB STD-T67 compliant

Applications

 Telemetry

Water level monitor for rivers, dams, etc.

Monitoring systems for environmental data such as temperature, humidity, etc.

Transmission of measurement data (pressure, revolutions, current, etc) to PC

Security alarm monitoring



Telecontrol

Industrial remote control systems

Remote control systems for factory automation machines

Control of various driving motors



Data transmission

RS232/RS485 serial data transmission

OG_STD-302S-429M_v11e 3 Circuit Design, Inc.

OPERATION GUIDE

SPECIFICATIONS

STD-302S 434 MHz

All ratings at 25 +/-10 °C unless otherwise noted

General characteristics

Item

Communication method

Emission class

Operating frequency range

Operation temperature range

Storage temperature range

Frequency drift / year

Initial frequency tolerance

Dimensions

Weight

Units mm g

MIN TYP MAX

Simplex, Half-duplex

F1D

MHz 429.25

°C -20

°C -30 ppm ppm

-1

-1.5

429.7375

30 x 50 x 9 mm

25 g

60

75

1

1.5

Remarks

No dew condensation

No dew condensation

TX freq., RX Lo freq.

TX freq., RX Lo freq.

Not including antenna

Electrical specification <Common>

Item

Oscillation type

Frequency stability

(-20 to 60°C) ppm

TX/RX switching time

Channel step ms kHz

Data rate

Max. pulse width

Min. pulse width

Data polarity

PLL reference frequency

PLL response

Antenna impedance

Operating voltage

TX consumption current

RX consumption current bps ms us

MHz ms

Ω

V mA mA

Transmitter part

Item

RF output power

Deviation

DI input level

Residual FM noise

Spurious emission

Adjacent CH power

Occupied freq. bandwidth mW kHz

V kHz dBm dB kHz

MIN TYP MAX

PLL controlled VCO

-4 4

15

12.5

20

2400

200

3.0

15

Positive

21.25

30

50

44

26

Reference frequency at 25 °C

DI/DO

Remarks

60

5.5

48

30

4800 DO/DI

20 DO/DI

DO/DI

DO/DI

TCXO from PLL setting to LD out

Nominal

Vcc = 3.0 V

Vcc = 3.0 V

MIN

5

±1.7

0

40

TYP

9

±2.0

0.17

-37

MAX Remarks

12 Conducted 50 Ω, 429.5 MHz

±2.3

PN9 4800 bps

5.5

L= GND, H = 3 V- Vcc

-27

8.5

DI=L, LPF=20 kHz

Conducted

50 Ω

PN9 4800 bps

PN9 4800 bps

OG_STD-302S-429M_v11e 4 Circuit Design, Inc.

OPERATION GUIDE

Receiver part

Receiver type

Item

1st IF frequency

2nd IF frequency

Maximum input level

BER (0 error/2556 bits)

BER (1 % error)

*2

Sensitivity 12dB/ SINAD

*1

Spurious response rejection

*3

Adjacent CH selectivity

*3

Intermodulation

DO output level

*4

RSSI rising time

Time until valid Data-out

Spurious radiation

RSSI

*5

MHz kHz dBm dBm dBm dBm dB dB dB

V ms ms dBm mV

MIN TYP MAX Remarks

Double superheterodyne

21.7

450

10

-108 -115 PN 9 4800bps

-120

-120

70

55

50

50

PN 9 4800bps fm1 k/ dev 2kHz CCITT

1 st Mix, 2 signal method, 1 % error

2 nd Mix, 2 signal method, 1 % error

+/- 12.5kHz,

2 signal method, 1 % error

2 signal method, 1 % error

0

30

50

50

70

2.8

50

70

100

120

L = GND H = 2.8 V

CH shift of 12.5 kHz (from PLL setup)

When power ON (from PLL setup)

CH shift of 12.5 kHz (from PLL setup)

When power ON (from PLL setup)

300

190

-60 -54 Conducted 50 ohm

350

240

400

290

With -97 dBm at 429.5 MHz

With -113 dBm at 429.5 MHz

Specifications are subject to change without prior notice

Notice



The time required until a stable DO is established may get longer due to the possible frequency drift caused by operation environment changes, especially when switching from TX to RX, from RX to TX and changing channels. Please make sure to optimize the timing. The recommended preamble is more than 20 ms.



Antenna connection is designed as pin connection.



RF output power, sensitivity, spurious emission and spurious radiation levels may vary with the trace used between the RF pin and the coaxial connection. Please make sure to verify those parameters before use.



The feet of the shield case should be soldered to a wide GND pattern to avoid any change in characteristics.

Notes about the specification values

*1

BER: RF level where no error per 2556 bits is confirmed with the signal of PN9 and 4800 bps.

*2

BER (1 % error) : RF level where 1% error per 2556 bits is confirmed with the signal of PN9 and 4800 bps.

*3

*4

*5

Spurious response, CH selectivity: Jamming signal used in the measurement is unmodulated.

Intermodulation: Ratio between the receiver input level with BER 1% and the signal level (PN9 4800 bps) added at the points of 'Receiving frequency - 200 kHz ' + ' Receiving frequency -100kHz' with which BER

1% is achieved.

Time until valid Data-out : Valid DO is determined at the point where Bit Error Rate meter starts detecting the signal of 4800bps, 1010repeated signal.

All specifications are specified based on the data measured in a shield room using the PLL setting controller board prepared by Circuit Design.

Measuring equipment:

SG=ANRITUS communication analyzer MT8802

Spectrum analyzer = ANRITSU MS2830A

BER measure = ANRITSU MP1201G

OG_STD-302S-429M_v11e 5 Circuit Design, Inc.

OPERATION GUIDE

PIN DESCRIPTION

Pin name I/O Description

RF I/O

RF input terminal

Antenna impedance nominal 50

Ω

Equivalent circuit

GND I

GROUND terminal

The GND pins and the feet of the shield case should be connected to a wide GND plane.

VCC

TXSEL

RXSEL

I

I

I

Power supply terminal

DC 3.0 to 5.5 V

TX select terminal

GND = TXSEL active

To enable the transmitter circuits, connect TXSEL to GND and RXSEL to OPEN or 2.8 V.

RX select terminal

GND= RXSEL active

To enable the receiver circuits, connect RXSEL to GND and TXSEL to OPEN or 2.8 V.

AFOUT O

Analogue output terminal

There is a DC offset of approx. 1 V.

Refer to the specification table for amplitude level.

CLK I

Clock terminal fof PLL data setting input

Interface voltage H = 2.8 V, L = 0 V

DATA I

PLL data setting input terminal

Interface voltage H = 2.8 V, L = 0 V

OG_STD-302S-429M_v11e 6 Circuit Design, Inc.

OPERATION GUIDE

LE I

Load enable signal input terminal for

PLL data setting input

Interface voltage H = 2.8 V, L = 0 V

LD O

PLL lock/unlock indicator terminal

Lock = H (2.8 V), Unlock = L (0 V)

RSSI O

Received Signal Strength Indicator terminal

DO O

Data output terminal

Interface voltage: H=2.8V, L=0V

DI I

Data input terminal

Interface voltage: H=2.8V to Vcc,

L=0V

Input data pulse width Min.200 μs

Max. 20 ms

OG_STD-302S-429M_v11e 7 Circuit Design, Inc.

OPERATION GUIDE

FREQUENCY TABLE (STD-T67)

Channel number

1

2

3

4

5

6

7

8

9

10

18

19

20

21

22

23

24

11

12

13

14

15

16

17

31

32

33

34

35

25

26

27

28

29

30

36

37

38

39

40

41

42

43

44

45

46

Operating frequency (MHz)

429.1750

429.1875

429.2000

429.2125

429.2250

429.2375

429.2500

429.2625

429.2750

429.2875

429.3000

429.3125

429.3250

429.3750

429.3875

429.3625

429.3750

429.3875

429.4000

429.4125

429.4250

429.4375

429.4500

429.4625

429.4750

429.4875

429.5000

429.5125

429.5250

429.5375

429.5500

429.5625

429.5750

429.5875

429.6000

429.6125

429.6250

429.6375

429.6500

429.6625

429.6750

429.6875

429.7000

429.7125

429.7250

429.7375

Transmission time restriction

Transmission for 40 sec, pause for 2 sec

Continuous transmission

(Intermittent communication possible)

OG_STD-302S-429M_v11e 8 Circuit Design, Inc.

BLOCK DIAGRAM

<STD-302S 429MHz>

OPERATION GUIDE

.

OG_STD-302S-429M_v11e 9 Circuit Design, Inc.

OPERATION GUIDE

.

DIMENSIONS

OG_STD-302S-429M_v11e 10 Circuit Design, Inc.

OPERATION GUIDE

.

PLL IC CONTROL



PLL IC control

up to 1200MHz

Figure 1

VCO

Voltage Controled

Oscillator

LPF

Reference Oscillator

21.25MHz

+2.8v

Fin

Xf in

CLK

Data

GND LE

Do

VCC

PLL

MB15E03SL

PS

ZC

Vp

OSCout

OSCin

LD/f out

P

R

2kohm

2kohm

2kohm

2kohm

CLK

DATA

LE

LD

STD-302

Control pin name

#:Control v oltage = +2.8v

STD-302S is equipped with an internal PLL frequency synthesizer as shown in Figure 1. The operation of the PLL circuit enables the VCO to oscillate at a stable frequency. Transmission frequency is set externally by the controlling IC. STD-302S has control terminals (CLK, LE, DATA) for the PLL IC and the setting data is sent to the internal register serially via the data line. Also STD-302S has a Lock Detect (LD) terminal that shows the lock status of the frequency. These signal lines are connected directly to the PLL IC through a 2 kΩ resistor.

The interface voltage of STD-302S is 2.8 V, so the control voltage must be the same.

STD-302S comes equipped with a Fujitsu MB15E03SL PLL IC. Please refer to the manual of the PLL IC.

The following is a supplementary description related to operation with STD-302S. In this description, the same names and terminology as in the PLL IC manual are used, so please read the manual beforehand.

OG_STD-302S-429M_v11e 11 Circuit Design, Inc.

OPERATION GUIDE

.



How to calculate the setting values for the PLL register

The PLL IC manual shows that the PLL frequency setting value is obtained with the following equation.

f vco f vco

= [(M x N)+A] x f osc

/ R -- Equation 1

: Output frequency of external VCO f

M: Preset divide ratio of the prescaler (64 or 128)

N: Preset divide ratio of binary 11-bit programmable counter (3 to 2,047)

A: Preset divide ratio of binary 7-bit swallow counter (0 ≤ A ≤ 127 A<N)) osc

: Output frequency of the reference frequency oscillator

R: Preset divide ratio of binary 14-bit programmable reference counter (3 to 16,383)

With STD-302S, there is an offset frequency (f offset

) 21.7 MHz for the transmission RF channel frequency f

Therefore the expected value of the frequency generated at VCO (f expect f vco

= f expect

= f ch

– f offset ----

Equation 2

) is as below.

ch

.

The PLL internal circuit compares the phase to the oscillation frequency f vco.

(f comp

) must be decided. f

This phase comparison frequency oscillator by reference counter R. STD-302S uses 21.25 MHz for the reference clock f

12.5 kHz or 25 kHz.

comp is made by dividing the frequency input to the PLL from the reference frequency osc.

f comp is one of 6.25 kHz, f vco

The above equation 1 results in the following with n = M x N + A, where “n” is the number for division.

=n*f comp

---- Equation 3 n = f vco

/f comp

---- Equation 4 note: f comp

= f osc

/R

Also, this PLL IC operates with the following R, N, A and M relational expressions.

R=f osc

/f comp

---- Equation 5 N = INT (n / M) ---- Equation 6 A = n - (M x N) ---- Equation 7

INT: integer portion of a division.

As an example, the setting value of RF channel frequency f

The constant values depend on the electronic circuits of STD-302S.

Conditions: Channel center frequency: ch

Constant: Offset frequency: f offset

Constant: Reference frequency:

429.500 MHz can be calculated as below.

f f ch

=21.7 M osc

= 429.500 MHz

=21.25 MHz

Set 12.5 kHz for Phase comparison frequency and 64 for Prescaler value M

The frequency of VCO will be f vco

= f expect

= f ch

- f offset

= 429.500–21.7 = 407.800 MHz

Dividing value “n” is derived from Equation 4 n = f vco

/ f comp

= 407.800 MHz/12.5 kHz = 32624

Value “R” of the reference counter is derived from Equation 5.

R = f osc

/f comp

= 21.25 MHz/125.5 kHz = 1700

Value “N” of the programmable counter is derived from Equation 6.

N = INT (n/M) = INT(32624/64) = 509

Value “A“ of the swallow counter is derived from Equation 7.

A = n – (M x N) = 32624-64x509 = 48

The frequency of STD-302S is locked at a center frequency f ch by inputting the PLL setting values N, A and R obtained with the above equations as serial data. The above calculations are the same for the other frequencies.

Excel sheets that contain automatic calculations for the above equations can be found on our web site

(www.circuitdesign.jp).

The result of the calculations is arranged as a table in the CPU ROM. The table is read by the channel change routine each time the channel is changed, and the data is sent to the PLL.

OG_STD-302S-429M_v11e 12 Circuit Design, Inc.

OPERATION GUIDE

.



Method of serial data input to the PLL

After the RF channel table plan is decided, the data needs to be allocated to the ROM table and read from there or calculated with the software.

Together with this setting data, operation bits that decide operation of the PLL must be sent to the PLL.

The operation bits for setting the PLL are as follows. These values are placed at the head of the reference counter value and are sent to the PLL.

1.

CS: Charge pump current select bit

VCO is optimized to +/-1.5 mA

2.

3.

CS = 0 +/-1.5 mA select

LDS: LD/fout output setting bit

LDS = 0 LD select

FC: Phase control bit for the phase comparator

FC = 1

Hardware is set to LD output

Hardware operates at this phase

Figure 2

DATA

2nd data

1st data

N11

CS

MSB

N10

LDS

N9

FC

N8

SW

1st Data

N7

R14

N6

R13

A1

R1

CNT=0

CNT=1

LSB

Inv alid Data

2nd Data

CLK t6 t1 t2 t3 t0

LE

STD-302 terminal name

#: t0,t5 >= 100 ns t1,t2,t6 >= 20 ns t3,t4 >= 30 ns t4

#: Keep the LEterminal at a low level, w hen w rite the data to the shift resister.

t5

The PLL IC, which operates as shown in the block diagram in the manual, shifts the data to the 19-bit shift register and then transfers it to the respective latch (counter, register) by judging the CNT control bit value input at the end.

1. CLK [Clock]: Data is shifted into the shift register on the rising edge of this clock.

2. LE [Load Enable]: Data in the 19-bit shift register is transferred to respective latches on the rising edge of the clock. The data is transferred to a latch according to the control bit CNT value.

3. Data [Serial Data]: You can perform either reference counter setup or programmable counter setup first.

OG_STD-302S-429M_v11e 13 Circuit Design, Inc.

OPERATION GUIDE

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TIMING CHART

Control timing in a typical application is shown in Figure 3.

Initial setting of the port connected to the radio module is performed when power is supplied by the CPU and reset is completed. MOS-FET for supply voltage control of the radio module, RXSEL and TXSEL are set to inactive to avoid unwanted emissions. The power supply of the radio module is then turned on. When the radio module is turned on, the PLL internal resistor is not yet set and the peripheral VCO circuit is unstable. Therefore data transmission and reception is possible 40 ms after the setting data is sent to the PLL at the first change of channel, however from the second change of channel, the circuit stabilizes within 20 ms and is able to handle the data.

Changing channels must be carried out in the receive mode. If switching is performed in transmission mode, unwanted emission occurs.

If the module is switched to the receive mode when operating in the same channel, (a new PLL setting is not necessary) it can receive data within 5 ms of switching reception to transmission

*2

.

*1

. For data transmission, if the RF channel to be used for transmission is set while still in receiving mode, data can be sent at 5 ms after the radio module is switched from

Check that the Lock Detect signal is “high” 20 ms after the channel is changed. In some cases the Lock Detect signal becomes unstable before the lock is correctly detected, so it is necessary to note if processing of the signal is interrupted. It is recommended to observe the actual waveform before writing the process program.

*1

DC offset may occur due to frequency drift caused by ambient temperature change. Under conditions below -

10 °C, 10 to 20 ms delay of DO output is estimated. The customer is requested to verify operation at low temperature and optimize the timing.

*2

Sending ‘10101…..’ preamble just after switching to transmission mode enables smoother operation of the binarization circuit of the receiver. For 4800 bps, a preamble of ‘11001100’ is effective.

Remark

For details about PLL control and the sample programs, see our technical document ‘STD-302 interface method’

OG_STD-302S-429M_v11e 14 Circuit Design, Inc.

Figure 3: Timing diagram for STD-302

Status immediately after pow er comes on.

Channel change

Normal status

No channel change

OPERATION GUIDE

.

CPU

Pow er on

STD-302

Pow er on

RXSEL

CPU control,

CH change

&

Data rec.

Timing

LD

#:1 #:2

#:3

#:4

CH

TXSEL

Data transmit

40 ms

Receiv e mode activ e period

Data #:5

Check LD signal

#:4

CH

Receiv e mode activ e period

Data #:6

Check LD signal

5 ms

Transmit mode activ e

10 to 20 ms

Transmit mode activ e

Receiv e mode activ e period

Data #:7

Check LD signal

Transmit mode activ e

Activ e period

#:4

CH

#:1 Reset control CPU

#:2 Initialize the port connected to the module.

#:3 Supply pow er to the module after initializing CPU.

#:4 RFchannel change must be performed in receiving mode.

5 ms 5 ms 5 ms

#:5 40 ms later, the receiver can receive the data after changing the channel..

#:6 10 to 20 ms later, the receiver can receive the data after changing the channel.

#:7 5 ms later, the data can be received if the RF channel is not changed.

OG_STD-302S-429M_v11e 15 Circuit Design, Inc.

No.

10

11

12

13

14

15

16

17

18

19

20

7

8

5

6

9

3

4

1

2

27

28

29

30

31

32

21

22

23

24

25

26

33

OPERATION GUIDE

PLL FREQUENCY SETTING DATA REFERENCE

429 MHz ISM band (429.1750 – 429.7375 MHz)

Parameter name

Phase Comparing Frequency F comp

Start Channel Frequency F ch

[MHz]

Channel Step Frequency [kHz]

Number of Channel

[kHz]

Prescaler M

Value

12.5

429.1750

12.5

46

64

Parameter name

Reference Frequency F osc

Offset Frequency F offset

[MHz]

[MHz]

Value

21.25

21.7

: For data input

: Result of calculation

: Fixed value

Parameter name

Reference Counter R

Programmable Counter N Min. Value

Programmable Counter N Max. Value

Swallow Counter A Min. Value

Swallow Counter A Max. Value

Value

1700

509

510

0

63

Channel

Frequency FCH

(MHz)

429.1750

429.1875

429.2000

429.2125

429.2250

429.2375

429.2500

429.2625

429.2750

429.2875

429.3000

429.3125

429.3250

429.3375

429.3500

429.3625

429.3750

429.3875

429.4000

429.4125

429.4250

429.4375

429.4500

429.4625

429.4750

429.4875

429.5000

429.5125

429.5250

429.5375

429.5500

429.5625

429.5750

Expect

Frequency

Ｆ

EXPECT

(MHz)

407.4750

407.4875

407.5000

407.5125

407.5250

407.5375

407.5500

407.5625

407.5750

407.5875

407.6000

407.6125

407.6250

407.6375

407.6500

407.6625

407.6750

407.6875

407.7000

407.7125

407.7250

407.7375

407.7500

407.7625

407.7750

407.7875

407.8000

407.8125

407.8250

407.8375

407.8500

407.8625

407.8750

Lock

Frequency

FVCO

Number of

Division n

(MHz)

407.4750

32598

407.4875

32599

407.5000

32600

407.5125

32601

407.5250

32602

407.5375

32603

407.5500

32604

407.5625

32605

407.5750

32606

407.5875

32607

407.6000

32608

407.6125

32609

407.6250

32610

407.6375

32611

407.6500

32612

407.6625

32613

407.6750

32614

407.6875

32615

407.7000

32616

407.7125

32617

407.7250

32618

407.7375

32619

407.7500

32620

407.7625

32621

407.7750

32622

407.7875

32623

407.8000

32624

407.8125

32625

407.8250

32626

407.8375

32627

407.8500

32628

407.8625

32629

407.8750

32630

Programable

Counter

N

509

509

509

509

509

509

509

509

509

509

509

509

509

509

509

509

509

509

509

509

509

509

509

509

509

509

509

509

509

509

509

509

509

Swallow Counter

A

31

32

33

34

35

36

37

38

39

40

41

26

27

28

29

30

22

23

24

25

48

49

50

51

52

53

42

43

44

45

46

47

54

OG_STD-302S-429M_v11e 16 Circuit Design, Inc.

34

35

36

37

38

39

40

41

42

43

44

45

46

429.5875

429.6000

429.6125

429.6250

429.6375

429.6500

429.6625

429.6750

429.6875

429.7000

429.7125

429.7250

429.7375

407.8875

407.9000

407.9125

407.9250

407.9375

407.9500

407.9625

407.9750

407.9875

408.0000

408.0125

408.0250

408.0375

407.8875

32631

407.9000

32632

407.9125

32633

407.9250

32634

407.9375

32635

407.9500

32636

407.9625

32637

407.9750

32638

407.9875

32639

408.0000

32640

408.0125

32641

408.0250

32642

408.0375

32643

OPERATION GUIDE

509

509

509

509

509

509

509

509

509

510

510

510

510

55

56

57

58

59

60

61

62

63

0

1

2

3

OG_STD-302S-429M_v11e 17 Circuit Design, Inc.

TEST DATA

RSSI output level characteristic

Measurement frequency: 429 MHz / Modulation: unmodulated

OPERATION GUIDE

25°C +/- 5°C

Signal level

(dBm)

-130

-120

-110

-100

-90

-80

-70

-60

-50

-40

-30

-20

-10

0

RSSI (mV)

130

177

243

288

347

405

460

523

550

552

552

552

552

552

Measurement is done with the PLL setting control board prepared by Circuit Design.

OG_STD-302S-429M_v11e 18 Circuit Design, Inc.

OPERATION GUIDE

Important notice



Customers are advised to consult with Circuit Design sales representatives before ordering.

Circuit Design believes the provided information is accurate and reliable. However, Circuit Design reserves the right to make changes to this product without notice.



Circuit Design products are neither designed nor intended for use in life support applications where malfunction can reasonably be expected to result in significant personal injury to the user. Any use of Circuit Design products in such safety-critical applications is understood to be fully at the risk of the customer and the customer must fully indemnify Circuit Design, Inc for any damages resulting from any improper use.



As the radio module communicates using electronic radio waves, there are cases where transmission will be temporarily cut off due to the surrounding environment and method of usage. The manufacturer is exempt from all responsibility relating to resulting harm to personnel or equipment and other secondary damage.



The manufacturer is exempt from all responsibility relating to secondary damage resulting from the operation, performance and reliability of equipment connected to the radio module.

Copyright



All rights in this operation guide are owned by Circuit Design, Inc. No part of this document may be copied or distributed in part or in whole without the prior written consent of Circuit Design, Inc.

Cautions



As the radio module communicates using electronic radio waves, there are cases where transmission will be temporarily cut off due to the surrounding environment and method of usage. The manufacturer is exempt from all responsibility relating to resulting harm to personnel or equipment and other secondary damage.



Do not use the equipment within the vicinity of devices that may malfunction as a result of electronic radio waves from the radio module.



The manufacturer is exempt from all responsibility relating to secondary damage resulting from the operation, performance and reliability of equipment connected to the radio module.



Communication performance will be affected by the surrounding environment, so communication tests should be carried out before actual use.



Ensure that the power supply for the radio module is within the specified rating. Short circuits and reverse connections may result in overheating and damage and must be avoided at all costs.



Ensure that the power supply has been switched off before attempting any wiring work.



The case is connected to the GND terminal of the internal circuit, so do not make contact between the '+' side of the power supply terminal and the case.



When batteries are used as the power source, avoid short circuits, recharging, dismantling, and pressure.

Failure to observe this caution may result in the outbreak of fire, overheating and damage to the equipment.

Remove the batteries when the equipment is not to be used for a long period of time. Failure to observe this caution may result in battery leaks and damage to the equipment.



Do not use this equipment in vehicles with the windows closed, in locations where it is subject to direct sunlight, or in locations with extremely high humidity.



The radio module is neither waterproof nor splash proof. Ensure that it is not splashed with soot or water. Do not use the equipment if water or other foreign matter has entered the case.



Do not drop the radio module or otherwise subject it to strong shocks.



Do not subject the equipment to condensation (including moving it from cold locations to locations with a significant increase in temperature.)



Do not use the equipment in locations where it is likely to be affected by acid, alkalis, organic agents or corrosive gas.



Do not bend or break the antenna. Metallic objects placed in the vicinity of the antenna will have a great effect on communication performance. As far as possible, ensure that the equipment is placed well away from metallic objects.



The GND for the radio module will also affect communication performance. If possible, ensure that the case

GND and the circuit GND are connected to a large GND pattern.

Warnings



Do not take a part or modify the equipment.



Do not remove the product label (the label attached to the upper surface of the module.) Using a module from which the label has been removed is prohibited.

OG_STD-302S-429M_v11e

Copyright 2015, Circuit Design, Inc.

19 Circuit Design, Inc.

REVISION HISTORY

Version

1.0

1.1

Date

Jan. 2015

Apr. 2015

Description

RSSI graph was revised (P.18)

OPERATION GUIDE

Remark

OG_STD-302S-429M_v11e 20 Circuit Design, Inc.