IT66121FN Datasheet v1 02

IT66121FN Datasheet v1 02

Specification V1.02

IT66121FN

Low Power Transmitter with HDMI1.4 3D

Datasheet

ITE TECH. INC.

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T8720F V0.7.1

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IT66121FN

General Description

The IT66121 is a high-performance and low-power single channel HDMI transmitter, fully compliant with HDMI 1.3a, HDCP 1.2 and backward compatible to DVI 1.0 specifications. IT66121 also provide the HDMI1.4 3D feature, which enables direct 3D displays through an HDMI link. The IT66121 serves to provide the most cost-effective HDMI solution for DTV-ready consumer electronics such as set-top boxes, DVD players and A/V receivers, as well as DTV-enriched PC products such as notebooks and desktops, without compromising the performance. Its backward compatibility to DVI standard allows connectivity to myriad video displays such as LCD and CRT monitors, in addition to the ever-so-flourishing Flat Panel TVs.

Aside from the various video output formats supported, the IT66121 also supports 8 channels of I

2

S digital audio, with sampling rate up to 192kHz and sample size up to 24 bits. IT66121 also support

S/PDIF input of up to 192kHz sampling rate.

The newly supported High-Bit Rate (HBR) audio by HDMI Specifications v1.3 is provided by the

IT66121 in two interfaces: with the four I

2

S input ports or the S/PDIF input port. With both interfaces the highest possible HBR frame rate is supported at up to 768kHz

By default the IT66121 comes with integrated HDCP ROMs which are pre-programmed with HDCP keys that ensures secure digital content transmission. Users need not worry about the procurement and maintenance of the HDCP keys.

The IT66121 also provides a complete solution of Consumer Electronics Control (CEC) function. This optional CEC feature of HDMI specification allows the user to control two or more CEC-enabled devices through HDMI network. With IT66121 embedded CEC PHY, user can use high-level software

API to easily implement all the necessary remote control commands. The CEC bus related protocol is handled by the CEC PHY which eliminates extra loading of the MCU.

Features

Single channel HDMI transmitter

Compliant with HDMI 1.3a, HDCP 1.2 and DVI 1.0 specifications

Supporting pixel rates from 25MHz to 165MHz

DTV resolutions: 480i, 576i, 480p, 576p, 720p, 1080i up to 1080p

PC resolutions: VGA, SVGA, XGA, SXGA up to UXGA

Various video input interface supporting digital video standards such as:

24-bit RGB/YCbCr 4:4:4 with RB swap option

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IT66121FN

16/20/24-bit YCbCr 4:2:2 with YC swap option

8/10/12-bit YCbCr 4:2:2 (CCIR-656)

BTA-T1004 format

DE-only interface

DDR option

Support HDMI1.4 3D feature

Frame packing mode up to [email protected]/24Hz and [email protected]/60Hz

Top and Bottom up to [email protected]/60Hz

Side-by-Side (Half) up to [email protected]/60Hz

Side-by-Side (Full) up to [email protected]/60Hz

Bi-direction Color Space Conversion (CSC) between RGB and YCbCr color spaces with programmable coefficients.

Digital audio input interface supporting

audio sample rate: 32~192 kHz

sample size: 16~24 bits

four I

2

S interfaces supporting 8-channel audio

S/PDIF interface supporting PCM, Dolby Digital, DTS digital audio transmission at up to

192kHz

Support for high-bit-rate (HBR) audio such as DTS-HD and Dolby TrueHD through the four I

2

S interface or the S/PDIF interface, with frame rates as high as 768kHz

Compatible with IEC 60958 and IEC 61937

Software programmable HDMI output current, enabling user to optimize the performance for fixed-cable systems or those with pre-defined cable length

MCLK input is optional for audio operation. Users could opt to implement audio input interface with or without MCLK.

Integrated pre-programmed HDCP keys

Purely hardware HDCP engine increasing the robustness and security of HDCP operation

Monitor detection through Hot Plug Detection and Receiver Termination Detection

Embedded full-function pattern generator

Intelligent, programmable power management

Embedded hardware controlled CEC PHY

Ultra low power consumption, operation power is less than 70mw at [email protected] format.

64-pin (9x9 mm) QFN package

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IT66121FN

Ordering Information

Model Temperature Range

IT66121FN -20~75

Package Type

64-pin QFN

Green/Pb free Option

Green

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T8720F V0.7.1

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IT66121FN

Pin Diagram

SYSRSTN

OVDD

IVDD12

D23

D22

D21

D20

D19

D18

D17

D16

D15

D14

D13

D12

D11

33

32

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

31 30 29

50 51 52

28 27 26 25 24 23 22 21

IT66121FN

QFN-64 9x9

(Top View)

20 19 18 17

16

15

11

10

9

6

5

4

3

2

1

14

13

12

8

7

DDCSCL

DDCSDA

HPD

OVDD33

PCSCL

PCSDA

INT

VCC33

IVDD12

SCK/MCLK

WS

I2S0

I2S1

I2S2

I2S3/SPDIF

OVDD

61 62 63 64 53 54 55 56 57 58 59 60

PIN65: GND PAD

Figure 1. IT66121FN pin diagram

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IT66121FN

Pin Description

Digital Video Input Pins

Pin Name Direction Description

D[23:0] Input Digital video input pins.

DE

HSYNC

VSYNC

PCLK

Input

Input

Input

Input

Data enable

Horizontal sync. signal

Vertical sync. signal

Input data clock

Digital Audio Input Pins

Pin Name

WS

I2S0

I2S1

I2S2

Direction Description

SCK/MCLK Input

Input

Input

Input

Input

I2S3/SPDIF Input

I

2

S

serial clock input /SPDIF master clock input

I

2

S

word select input

I

2

S

0 serial data input

I

2

S

1 serial data input

I

2

S

2 serial data input

I

2

S

3 serial data input /SPDIF audio input

HDMI Interface Pins

Pin Name Direction Description

CEC

DDCSCL

DDCSDA

HPD

I/O

I/O

I/O

Input

CEC signal (5V-tolerant)

I

2

C Clock for DDC (5V-tolerant)

I

2

C Data for DDC (5V-tolerant)

Hot Plug Detection (5V-tolerant)

TMDS front-end interface pins

Pin Name

TX2P

Direction Description

Analog HDMI Channel 2 positive output

TX2M

TX1P

TX1M

TX0P

TX0M

TXCP

Analog HDMI Channel 2 negative output

Analog HDMI Channel 1 positive output

Analog HDMI Channel 1 negative output

Analog HDMI Channel 0 positive output

Analog HDMI Channel 0 negative output

Analog HDMI Clock Channel positive output

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Type

LVTTL

LVTTL

LVTTL

LVTTL

LVTTL

Type

LVTTL

LVTTL

LVTTL

LVTTL

LVTTL

LVTTL

Type

Schmitt

Schmitt

Schmitt

LVTTL

Pin No.

36-50,

52-55,

57-61

62

63

64

51

Pin No.

7

6

5

4

3

2

Pin No.

17

16

15

14

Type

TMDS

TMDS

TMDS

TMDS

TMDS

TMDS

TMDS

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Pin No.

30

29

27

26

25

24

22

IT66121FN

TXCM

REXT

Analog HDMI Clock Channel negative output

Analog External resistor for setting TMDS output level. Default tied to

AGND via a 5.6K-Ohm SMD resistor.

Programming Pins

Pin Name Direction Description

PCSCL

PCSDA

INT#

Input Serial Programming Clock for chip programming (5V-tolerant)

I/O Serial Programming Data for chip programming (5V-tolerant)

Output Interrupt output. Default active-low (5V-tolerant)

System Control Pins

Pin Name Direction Description

ENTEST

PCADR

Input

Input

SYSRSTN Input

Must be tied low via a resistor.

Serial programming device address select

Hardware reset pin. Active LOW

OVDD

OVDD33

VCC33

PVCC12

PVCC33

AVCC12

DVDD12

GND

Power/Ground Pins

Pin Name

IVDD12

Description

Digital logic power (1.2V)

I/O Pin power (1.8V or 2.5V or 3.3V)

5V-tolerant I/O power (3.3V)

Internal ROM power (3.3V)

HDMI core PLL power (1.2V)

HDMI core PLL power (3.3V)

HDMI analog frontend power (1.2V)

HDMI digital frontend power (1.2V)

Exposed ground pad

Type

Power

Power

Power

Power

Power

Power

Power

Power

Ground

TMDS

Analog

Type

Schmitt

Schmitt

LVTTL

Pin No.

12

11

10

Pin No.

8, 35, 56

1, 34

13

9

18

19

23

28

65

21

20

Type

LVTTL

LVTTL

Schmitt

Pin No.

31

32

33

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T8720F V0.7.1

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IT66121FN

Functional Description

IT66121 is a low-power version of HDMI 1.3 transmitter and provides complete solutions for HDMI

Source systems by implementing all the required HDMI functions. In addition, advanced processing algorithms are employed to optimize the performance of video processing such as color space conversion and YCbCr up/down-sampling. The following picture is the functional block diagram of

IT66121, which describes clearly the data flow.

PCSCL PCSDA ROMSCL ROMSDA

SYSRSTN

PCADR

I2C Master

(to HDCP

EEPROM)

I2C Master

(HDCP

Controller)

DDCSCL

DDCSDA

Configuration

Register Blocks

I2C Slave

(to host)

CEC

PHY

CEC

PCLK

VSYNC

HSYNC

DE

D[23:0]

SCK/MCLK

WS

I2S0

I2S1

I2S2

I2S3/SPDIF

Video Data

Capture

&

DE Generator

Audio Data

Capture

Color Space

Conversion

4:2:2

4:4:4

Pixel Repeat

HDCP Cipher

&

Encryption Enginer

TMDS

Transmitter

(DVI/HDMI)

TX2P/M

TX1P/M

TX0P/M

TXCP/M

INT Interrupt Controller HPD

Figure 2. Functional block diagram of IT66121

Video Data Processing Flow

Figure 3 depicts the video data processing flow. For the purpose of retaining maximum flexibility, most of the block enabling and path bypassing are controlled through register programming. Please refer to

IT66121 Programming Guide for detailed and precise descriptions.

As can be seen from Figure 3, the first step of video data processing is to prepare the video data

(Data), data enable signal (DE), video clock (Clock), horizontal sync and vertical sync signals

(H/VSYNC). While the video data and video clock are always readily available from input pins, the preparation of the data enable and sync signals require special extraction process (Embedded Ctrl.

Signals Extraction & DE Generator) depending on the format of input video data.

All the data then undergo a series of video processing including color-space conversion and YCbCr

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IT66121FN

up/down-sampling. Depending on the selected input and output video formats, different processing blocks are either enabled or bypassed via register control. For the sake of flexibility, this is all done in software register programming. Therefore, extra care should be taken in keeping the selected input-output format combination and the corresponding video processing block selection. Please refer to the IT66121 Programming Guide for suggested register setting.

PCLK

Clock

H/VSYNC

DE

H/VSYNC

DE

Generator

DE

Embedded Ctrl.

Signals

Extraction

H/VSYNC

DE

Data

D[23:0]

YCbCr422 to

YCbCr444

(upsampler)

YCbCr

«

RGB

(CSC)

YCbCr444 to

YCbCr422

(downsampler)

HDCP

TMDS

Driver

TX2

TX1

TX0

TXC

Figure 3. Video data processing flow of IT66121

Designated as D[23:0], the input video data could take on bus width of 8 bits to 24 bits. This input interface could be configured through register setting to provide various data formats as listed in Table

1.

Although not explicitly depicted in Figure 3, input video clock (PCLK) can be configured to be multiplied by 0.5, 1, 2 or 4, so as to support special formats such as CCIR-656 and pixel-repeating.

This is also enabled by software programming.

General description of block functions is as follows:

Extraction of embedded control signals (Embedded Ctrl. Signals Extraction)

Input video formats with only embedded sync signals rely on this block to derive the proper Hsync,

Vsync and DE signals. Specifically, CCIR-656 video stream includes Start of Active Video (SAV) and

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IT66121FN

End of Active Video (EAV) that this block uses to extract the required control signals.

Generation of data enable signal (DE Generator)

DE signal defines the region of active video data. In cases where the video decoders supply no such

DE signals to IT66121, this block is used to generate appropriate DE signal from Hsync, Vsync and

Clock.

Upsampling (YCbCr422 to YCbCr444)

In cases where input signals are in YCbCr 4:2:2 format and output is selected as 4:4:4, this block is enabled to do the upsampling.

Bi-directional Color Space Conversion (YCbCr « RGB)

Many video decoders only offer YCbCr outputs, while DVI 1.0 supports only RGB color space. In order to offer full compatibility between various Source and Sink combination, this block offers bi-directional

RGB

« YCbCr color space conversion (CSC). To provide maximum flexibility, the matrix coefficients of the CSC engine in IT66121 are fully programmable. Users of IT66121 could elect to employ their preferred conversion formula.

Downsampling (YCbCr444 to YCbCr422)

In cases where input signals are in YCbCr 4:4:4 format and output is selected as YCbCr 4:2:2, this block is enabled to do the downsampling.

HDCP engine (HDCP)

The HDCP engine in IT66121 handles all the processing required by HDCP mechanism in hardware.

Software intervention is not necessary except checking for revocation. Preprogrammed HDCP keys are also embedded in IT66121. Users need not worry about the purchasing and management of the

HDCP keys.

TMDS driver (TMDS Driver)

The final stop of the data processing flow is TMDS serializer. The TMDS driver serializes the input parallel data and drive out the proper electrical signals to the HDMI cable. The output current level is controlled through connecting a precision resistor of proper value to Pin 20 (REXT).

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IT66121FN

Supported Input Video Formats

Table 1 lists the input video formats supported by IT66121.

Color

Space

RGB

Video

Format

4:4:4

Bus

Width

24

12

Input Pixel clock frequency (MHz)

DDR/

SDR

Hsync/

Vsync

480i 480p XGA 720p 1080i SXGA 1080p UXGA

SDR Separate 13.5 27 65 74.25 74.25 108 148.5 162

DDR Separate 13.5 27 65 74.25 74.25

YCbCr

4:4:4

4:2:2

24

24

12

DDR Separate 13.5 32.5 37.125 37.125 54 74.25 81

SDR Separate 13.5 27 65 74.25 74.25 108 148.5 162

DDR Separate 13.5 27 65 74.25 74.25

24 DDR Separate 13.5 32.5 37.125 37.125 54 74.25 81

Separate 13.5 27 65 74.25 74.25 108 148.5 162

16/20/24 SDR

Embedded 13.5 27 65 74.25 74.25 108 148.5 162

Separate 13.5 32.5 37.125 37.125 54 74.25 81

16/20/24 DDR

Embedded 13.5 32.5 37.125 37.125 54 74.25 81

8/10/12

8/10/12

SDR

DDR

Separate 27 54 130 148.5 148.5

Embedded 27 54 130 148.5 148.5

Separate 13.5 27 65 74.25 74.25

Embedded 13.5 27 65 74.25 74.25

Table 1. Input video formats supported by IT66121

Notes:

1. Table cells that are left blanks are those format combinations that are not supported by IT66121.

2. Embedded sync signals are defined by CCIR-656 standard, using SAV/EAV sequences of FF, 00, 00, XY.

3. The original pixel clock of 480i is 13.5MHz. HDMI standard mandates that a 27MHz pixel clock be used and pixel repeating is employed to keep the frequency range of the HDMI link within control.

Audio Data Capture and Processing

IT66121 takes in four I

2

S inputs as well as one S/PDIF input of audio data. The four I

2

S inputs allow transmission of 8-channel uncompressed audio data at up to 192kHz sample rate. The S/PDIF input allows transmission of uncompressed PCM data (IEC 60958) or compressed multi-channel data (IEC

61937) at up to 192kHz.

Note that MCLK input is optional for the IT66121. By default IT66121 generates the MCLK internally to process the audio. Neither I

2

S nor S/PDIF inputs requires external MCLK signal. However, if the jitter or the duty cycle of the input S/PDIF is considerable, coherent external MCLK input is recommended and such configuration could be enabled through register setting. Refer to IT66121 Programming

Guide for such setting.

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IT66121FN

High-Bit-Rate (HBR) Audio is first introduced in the HDMI 1.3 standard. It is called upon by high-end audio system such as DTS-HD and Dolby TrueHD. No specific interface is defined by the HBR standard. The IT66121 supports HBR audio in two ways. One is to employ the four I

2

S inputs simultaneously, where the original streaming HBR audio is broken into four parallel data streams before entering the IT66121. The other is to use the S/PDIF input port. Since the data rate here is as high as 98.304Mbps, a coherent MCLK is required in this application.

Interrupt Generation

The system micro-controller should take in the interrupt signal output by IT66121 at PIN 10 (INT). INT pin can be configured as Push-pull or Tristate mode depending on user’s application. IT66121 generates an interrupt signal with events involving the following signals or situations:

1. Hot-plug detection (Pin 14, HPD) experiences state changes.

2. Receiver detection circuit reports the presence or absence of an active termination at the TMDS

Clock Channel (RxSENDetect)

3. DDC bus is hanged for any reasons

4. Audio FIFO overflows

5. HDCP authentication fails

6. Audio/Video data is stable or not

A typical initialization of HDMI link should be based on interrupt signal and appropriate register probing.

Recommended flow is detailed in IT66121 Programming Guide. Simply put, the microcontroller should monitor the HPD status first. Upon valid HPD event, move on to check RxSENDetect register to see if the receiver chip is ready for further handshaking. When RxSENDetect is asserted, start reading EDID data through DDC channels and carry on the rest of the handshaking subsequently.

If the micro-controller makes no use of the interrupt signal as well as the above-mentioned status registers, the link establishment might fail. Please do follow the suggested initialization flow recommended in IT66121 Programming Guide.

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IT66121FN

Configuration and Function Control

IT66121 includes two serial programming ports by default (i.e. with embedded HDCP keys): one for interfacing with micro-controller, the other for accessing the DDC channels of HDMI link.

The serial programming interface for interfacing the micro-controller is a slave interface, comprising

PCSCL (Pin 12) and PCSDA (Pin 11). The micro-controller uses this interface to monitor all the statuses and control all the functions. Two device addresses are available, depending on the input logic level of PCADR (Pin 32). If PCADR is pulled high by the user, the device address is 0x9A. If pulled low, 0x98.

The I

2

C interface for accessing the DDC channels of the HDMI link is a master interface, comprising

DDCSCL (Pin 16) and DDCSDA (Pin 15). IT66121 uses this interface to read the EDID data and perform HDCP authentication protocol with the sink device over the HDMI cable.

For temporarily storing the acquired EDID data, IT66121 includes a 32 bytes dedicated FIFO. The micro-controller may command IT66121 to acquire 32 bytes of EDID information, read it back and then continue to read the next 32 bytes until getting all necessary EDID information.

The HDCP protocol of IT66121 is completely implemented in hardware. No software intervention is needed except for revocation list checking. Various HDCP-related statuses are stored in HDCP registers for the reference of micro-controller. Refer to IT66121 Programming Guide for detailed register descriptions. The HDCP Standard also specifies a special message read protocol other than the standard I

2

C protocol. See Figure 4 for checking HDCP port link integrity.

S Slave Addr (7) R A Read Data (8) A Read Data (8) A Read Data (8) NA P

S=Start; R=Read; A=Ack; NA=No Ack; P=Stop

Figure 4. HDCP port link integrity message read

All serial programming interfaces conform to standard I

2

C transactions and operate at up to 100kHz.

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IT66121FN

Electrical Specifications

Absolute Maximum Ratings

Symbol Parameter

IVDD12

OVDD33

OVDD

OVDD

OVDD

VCC33

AVCC12

PVCC12

PVCC33

DVDD12

V

I

V

O

T

J

T

STG

ESD_HB

Core logic supply voltage

5V-tolerance I/O pins supply voltage

1.8V I/O pins supply voltage (OVDD=1.8V)

2.5V I/O pins supply voltage (OVDD=2.5V)

3.3V I/O pins supply voltage (OVDD=3.3V)

ROM supply voltage

HDMI analog frontend supply voltage

HDMI core PLL supply voltage

HDMI core PLL supply voltage

HDMI AFE digital supply voltage

Input voltage

Output voltage

Junction Temperature

Storage Temperature

Human body mode ESD sensitivity

-0.5

-0.5

-0.3

-0.5

-0.3

-0.3

-65

2000

Min.

-0.5

-0.3

-0.3

-0.3

-0.3

-0.3

Typ Max

1.5

4.0

2.5

3.2

4.0

4.0

1.5

1.5

4.0

1.5

OVDD+0.3 V

OVDD+0.3 V

125

150

C

C

V

V

V

V

V

Unit

V

V

V

V

V

V

ESD_MM Machine mode ESD sensitivity 200 V

Notes:

1. Stresses above those listed under Absolute Maximum Ratings might result in permanent damage to the device.

2. Refer to Functional Operation Conditions for normal operation.

Functional Operation Conditions

Symbol Parameter

IVDD12 Core logic supply voltage

OVDD33

OVDD

VCC33

AVCC12

PVCC12

PVCC33

DVDD12

V

CCNOISE

T

A

I/O pins supply voltage

1.8V I/O pins supply voltage

2.5V I/O pins supply voltage

3.3V I/O pins supply voltage

ROM supply voltage

HDMI analog frontend supply voltage

HDMI core PLL supply voltage

HDMI core PLL supply voltage

HDMI AFE digital supply voltage

Supply noise

Ambient temperature

Min.

1.14

3.0

1.62

2.25

3.0

3.0

1.14

1.14

3.0

1.14

0

3.3

1.2

1.2

3.3

Typ

1.2

3.3

1.8

2.5

3.3

1.2

25

Max

1.26

3.6

1.98

2.75

3.6

3.6

1.26

1.26

3.6

1.26

100

70

V

V

V

V

V mV pp

C

Unit

V

V

V

V

V

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IT66121FN

ja

Junction to ambient thermal resistance

Notes:

1. AVCC12, PVCC12 and PVCC33 should be regulated.

2. See System Design Consideration for supply decoupling and regulation.

40 C/W

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T8720F V0.7.1

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IT66121FN

DC Electrical Specification

Under functional operation conditions

Symbol Parameter

V

IH

Input high voltage

1

V

IL

Input low voltage

1

For 1.8V OVDD For 2.5V OVDD For 3.3V OVDD

Pin Type Min Typ Max Min Typ Max Min Typ Max

LVTTL

1.2 1.7 2.0

LVTTL

0.6 0.7 0.8

V

T-

V

T+

V

OL

V

OH

I

IN

Schmitt trigger negative going threshold voltage

1

Schmitt trigger positive going threshold voltage

1

Output low voltage

1

Output high voltage

1

Input leakage current

1

Schmitt

0.63 0.75 0.94 1.06 1.22 1.39

Schmitt

LVTTL

LVTTL

1.4 all -10

1.05 1.14

0.4

2.1

+10 -10

1.35 1.48

0.4

2.9

+10 -10

1.70 1.92

0.4

+10

I

OZ

I

OL

Tri-state output leakage current

1

Serial programming output sink current

2 all

Schmitt

-10 +10 -10 +10 -10

2.5

+10

10

Unit

V

V

V

V

V

V

A

A mA

V swing

TMDS output single-ended swing

3

TMDS

400 600 400 600 400 600 mV

I

OFF

Single-ended standby output current

3

TMDS

10 10 10 A

Notes:

1. Guaranteed by I/O design.

2. The serial programming output ports are not real open-drain drivers. Sink current is guaranteed by I/O design under the condition of driving the output pin with 0.2V. In a real serial programming environment, multiple devices and pull-up resistors could be present on the same bus, rendering the effective pull-up resistance much lower than that specified by the I

2

C Standard. When set at maximum current, the serial programming output ports of

IT66121 are capable of pulling down an effective pull-up resistance as low as 500 connected to 5V termination voltage to the standard I

2

C V

IL

. When experiencing insufficient low level problem, try setting the current level to higher than default. Refer to IT66121 Programming Guide for proper register setting.

3. Limits defined by HDMI standard

Audio AC Timing Specification

Under functional operation conditions

Symbol Parameter

F

S_I2S

I

2

S sample rate

F

S_SPDIF

S/PDIF sample rate

Conditions

Up to 8 channels

2 channels

Min Typ Max

32 192

32 192

Unit kHz kHz

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T8720F V0.7.1

Apr-2013 Rev:1.02 16/40

IT66121FN

Video AC Timing Specification

Under functional operation conditions

Symbol Parameter

T pixel

PCLK pixel clock period

1

F pixel

PCLK pixel clock frequency

1

T

CDE

PCLK dual-edged clock period

2

F

CDE

PCLK dual-edged clock frequency

2

T

PDUTY

PCLK clock duty cycle

Conditions

Single-edged clocking

Dual-edged clocking

Min

6.06

25

13.47

25

40%

Typ Max

40

165

40

Unit ns

MHz ns

74.25 MHz

60%

T

PJ

PCLK worst-case jitter 2.0 ns

T

S

Video data setup time

3

Single-edged 1.5 ns

T

H

Video data hold time

3 clocking

0.7 ns

T

SDE

Video data setup time

3

Dual-edged

1.5 ns

T

HDE

Video data hold time

3 clocking 0.7 ns

Notes:

1. Fpixel is the inverse of Tpixel. Operating frequency range is given here while the actual video clock frequency should comply with all video timing standards. Refer to Table 1 for supported video timings and corresponding pixel frequencies.

2. 12-bit dual-edged clocking is supported up to 74.5MHz of PCLK frequency, which covers 720p/1080i.

3. All setup time and hold time specifications are with respect to the latching edge of PCLK selected by the user through register programming.

www.ite.com.tw

T8720F V0.7.1

Apr-2013 Rev:1.02 17/40

IT66121FN

Operation Supply Current Specification

Normal Operation Mode

TYPICAL Mode TTL input test 3.3V, 2.5V and 1.8V

Resolution Mode HDCP

Video

In/Out

Format

Audio Deep Color

[email protected]

[email protected] HDMI

[email protected]

[email protected] DVI

On

Off

YUV444 to

RGB444

No CSC

48K2Ch

Off

8bits

8bits

Resolution Mode

MAX Mode TTL input test 3.3V, 2.5V and 1.8V

HDCP

Video

In/Out

Format

Audio Deep Color

[email protected]

[email protected]

[email protected]

HDMI On

YUV444to

RGB444

192K2Ch 8bits

[email protected] DVI Off

No CSC Off 8bits

I

OVDD33

I

VCC33

Symbol

I

PVCC33

www.ite.com.tw

Video Timing

480P60 8-bit

720P60 8-bit

1080P60 8-bit

1600x1200P60 8-bit

480P60 8-bit

720P60 8-bit

1080P60 8-bit

1600x1200P60 8-bit

480P60 8-bit

Video Pattern

Video Pattern

PCLK(MHz) TYPICAL MAX Unit

27.0 0.07 0.07 mA

74.25

148.5

162.0

27.0

74.25

148.5

162.0

27.0

0.07

0.07

0.07

0.04

0.04

0.04

0.00

1.68

0.07

0.07

0.07

0.04

0.04

0.04

0.00

1.68 mA mA mA mA mA mA mA mA

T8720F V0.7.1

Apr-2013 Rev:1.02 18/40

IT66121FN

I

I

I

I

IVDD12

DVDD12

AVCC12

PVCC12

720P60 8-bit

1080P60 8-bit

1600x1200P60 8-bit

480P60 8-bit

720P60 8-bit

1080P60 8-bit

1600x1200P60 8-bit

480P60 8-bit

720P60 8-bit

1080P60 8-bit

1600x1200P60 8-bit

480P60 8-bit

720P60 8-bit

1080P60 8-bit

1600x1200P60 8-bit

480P60 8-bit

720P60 8-bit

1080P60 8-bit

1600x1200P60 8-bit

When OVDD=3.3V

I

OVDD

TTL input is 3.3V

P

TOTAL

TTL input is 3.3V

480P60 8-bit

720P60 8-bit

1080P60 8-bit

1600x1200P60 8-bit

480P60 8-bit

720P60 8-bit

1080P60 8-bit

1600x1200P60 8-bit

When OVDD=2.5V

I

OVDD

TTL input is 2.5V

480P60 8-bit

720P60 8-bit

1080P60 8-bit

1600x1200P60 8-bit

480P60 8-bit

P

TOTAL

www.ite.com.tw

27.0

74.25

148.5

162.0

27.0

74.25

148.5

162.0

74.25

148.5

162.0

27.0

74.25

148.5

162.0

27.0

74.25

148.5

162.0

27.0

74.25

148.5

162.0

27.0

74.25

148.5

162.0

3.44

6.69

7.2

9.95

10.69

11.84

12.0

0.87

5.77

3.16

3.53

4.77

11.02

21.22

16.745

1.36

2.32

2.6

2.85 mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA

3.44

6.69

7.2

9.95

10.69

11.84

12.0

0.87

5.77

3.16

3.53

6.10

13.24

24.63

20.6

1.36

2.32

2.6

2.85

0.13

0.3

0.49

0.44

26.676

53.358

63.228

63.84

0.15

0.37

0.65

0.75

28.338

56.253

68.848

65.535 mA mA mA mA mW mW mW mW

27.0

74.25

148.5

162.0

27.0

0.036

0.132

0.248

0.264

25.6752

0.065

0.164

0.328

0.461

27.372 mA mA mA mA mW

T8720F V0.7.1

Apr-2013 Rev:1.02 19/40

IT66121FN

TTL input is 2.5V

720P60 8-bit

1080P60 8-bit

1600x1200P60 8-bit

74.25

148.5

162.0

50.7324

60.4056

60.7368

When OVDD=1.8V

I

OVDD

TTL input is 1.8V

P

TOTAL

TTL input is 1.8V

480P60 8-bit

720P60 8-bit

1080P60 8-bit

1600x1200P60 8-bit

480P60 8-bit

720P60 8-bit

1080P60 8-bit

1600x1200P60 8-bit

27.0

74.25

148.5

162.0

27.0

74.25

148.5

162.0

Standby Mode

Resolution

Standby Mode TTL input test 3.3V, 2.5V and 1.8V

HDCP Video In/Out Format Audio Deep Color

0.000

0.043

0.115

0.121

25.632

50.6256

60.246

60.5652

53.6658

65.1216

62.6682

0.000

0.052

0.172

0.228

27.294

53.5314

64.933

62.3886 mW mW mW

Video Pattern mW mW mW mW mA mA mA mA

[email protected] On YUV444toRGB444 On 8bits

Symbol

Standby

PCLK / No PCLK

I

OVDD33

0.023 / 0.023

I

VCC33

0.000 / 0.000

I

PVCC33

0.000 / 0.000

I

IVDD12

0.539 / 0.114

I

DVDD12

0.174 / 0.173

I

AVCC12

0.000 / 0.000

I

PVCC12

0.133 / 0.000

I

OVDD (3.3V)

0.102 / 0.000

I

OVDD (2.5V)

0.056 / 0.000

I

OVDD (1.8V)

0.016 / 0.000

TTL input is 3.3V

www.ite.com.tw

Unit Symbol

Standby

PCLK / No PCLK mA mA mA mA mA mA mA mA mA mA

P

TOTAL

3.3V

1.2V

0.023 / 0.023

0.846 / 0.287

I

OVDD (3.3V)

I

OVDD (2.5V)

I

OVDD (1.8V)

0.102 / 0.000

0.056 / 0.000

0.016 / 0.000

1.4277 / 0.4203

Unit mA mA mA mA mA mW

T8720F V0.7.1

Apr-2013 Rev:1.02 20/40

IT66121FN

TTL input is 2.5V

P

TOTAL

1.2311 / 0.4203 mW

TTL input is 1.8V

P

TOTAL

1.1199 / 0.4203 mW

Notes:

1.

P

TOTAL

are calculated by multiplying the supply currents with their corresponding supply voltage and summing up all the items.

Video Data Bus Mappings

IT66121 supports various input data mappings and formats, including those with embedded control signals only. Corresponding register setting is mandatory for any chosen input data mappings. Refer to IT66121 Programming Guide for detailed instruction.

Color Space Video Format Bus Width SDR/DDR H/Vsync Clocking Table Figure

RGB

YCbCr

4:4:4

4:4:4

4:2:2

24

12

24

24

12

24

16/20/24

16/20/24

8/10/12

8/10/12

SDR

DDR

DDR

SDR

DDR

DDR

SDR

DDR

SDR

DDR

Separate

Separate

Separate

Embedded

Separate

Embedded

Separate

Embedded

Separate

Embedded

1X

0.5X

1X

0.5X

1X

0.5X

2X

1X

12

13

4

5

3

12

13

3

14

Note 1

14

8

7

Note 2

10

9

15 15

12

13

6

7

5

12

13

5

Table 2. Input video format supported by IT66121

Notes:

1. The mapping of this format is the same as Table 5 and the timing diagram is similar to Figure 14 except the syncs are embedded.

2. The mapping of this format is the same as Table 8 and the timing diagram is similar to Figure 15 except the syncs are separated.

With certain input formats, not all 24 data input pins are used. In that case, it is recommended to tie the unused input pins to ground.

www.ite.com.tw

T8720F V0.7.1

Apr-2013 Rev:1.02 21/40

IT66121FN

24-bit RGB/YCbCr444 (Separate Syncs)

These are the simplest formats, with a complete definition of every pixel in each clock period. Timing diagram is depicted in Fig.5.

Pin Name

D0

D1

D2

D3

D4

D5

D6

D7

D8

D9

D10

D11

D12

D13

D14

D15

D16

D17

D18

D19

D20

D21

D22

D23

HSYNC

VSYNC

DE

G4

G5

G6

G7

R0

R1

R2

R3

RGB

B0

B1

B2

B3

B4

B5

B6

B7

G0

G1

G2

G3

R4

R5

R6

R7

HSYNC

VSYNC

DE

Y4

Y5

Y6

Y7

Cr0

Cr1

Cr2

Cr3

YCbCr

Cb0

Cb1

Cb2

Cb3

Cb4

Cb5

Cb6

Cb7

Y0

Y1

Y2

Y3

Cr4

Cr5

Cr6

Cr7

HSYNC

VSYNC

DE

Table 3. Mappings of 24-bit RGB/YCbCr444 (separate syncs)

D[23:16] blank Pixel0 Pixel1 Pixel2 Pixel3 Pixel4 Pixel5 Pixel6 val

R/Cr pix0

R/Cr pix1

R/Cr pix2

R/Cr pix3

R/Cr pix4

R/Cr pix5

R/Cr pix6

...

....

blank val val val

D[15:8] val

G/Y pix0

G/Y pix1

G/Y pix2

G/Y pix3

G/Y pix4

G/Y pix5

G/Y pix6

....

val val val

D[7:0]

PCLK

DE

H/VSYNC val

B/Cb pix0

B/Cb pix1

B/Cb pix2

B/Cb pix3

B/Cb pix4

B/Cb pix5

B/Cb pix6

....

val val val

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Figure 5. 24-bit RGB/YCbCr444 (separate syncs)

T8720F V0.7.1

Apr-2013 Rev:1.02 22/40

IT66121FN

16/20/24-bit YCbCr422 with Separate Syncs

YCbCr 4:2:2 format does not have one complete pixel for every clock period. Luminace channel (Y) is given for every pixel, while the two chroma channels are given alternatively on every other clock period. The DE period should contain an even number of clock periods.

YCbCr 4:2:2 16-bit YCbCr 4:2:2 20-bit YCbCr 4:2:2 24-bit

Pin Name Pixel#2N Pixel#2N+1 Pixel#2N Pixel#2N+1 Pixel#2N Pixel#2N+1

D0

D1

D2

D3 grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded

Y0

Y1 grounded grounded

Y0

Y1

Y0

Y1

Y2

Y3

Y0

Y1

Y2

Y3

D4

D5

D6

D7

D8

D9

D10

Y0

Y1

Y2

Y3

Y4

Y5

Y6

Y0

Y1

Y2

Y3

Y4

Y5

Y6

Y2

Y3

Y4

Y5

Y6

Y7

Y8

Y2

Y3

Y4

Y5

Y6

Y7

Y8

Y4

Y5

Y6

Y7

Y8

Y9

Y10

Y4

Y5

Y6

Y7

Y8

Y9

Y10

D11

D12

D13

D14

D15

D16

D17

D18

Y7 Y7 Y9 Y9 grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded Cb0 Cr0 grounded grounded

Cb0 Cr0

Cb1

Cb2

Cr1

Cr2

Cb1

Cb2

Cb3

Cb4

Cr1

Cr2

Cr3

Cr4

Y11

Cb0

Cb1

Cb2

Cb3

Cb4

Cb5

Cb6

Y11

Cr0

Cr1

Cr2

Cr3

Cr4

Cr5

Cr6

D19

D20

D21

D22

D23

HSYNC

VSYNC

DE

Cb3

Cb4

Cb5

Cb6

Cb7

HSYNC

VSYNC

DE

Cr3

Cr4

Cr5

Cr6

Cr7

HSYNC

VSYNC

DE

Cb5

Cb6

Cb7

Cb8

Cb9

HSYNC

VSYNC

DE

Cr5

Cr6

Cr7

Cr8

Cr9

HSYNC

VSYNC

DE

Cb7

Cb8

Cb9

Cb10

Cb11

HSYNC

VSYNC

DE

Cr7

Cr8

Cr9

Cr10

Cr11

HSYNC

VSYNC

DE

Table 4. Mappings of 16/20/24-bit YCbCr422 with separate syncs

blank Pixel0 Pixel1 Pixel2 Pixel3 Pixel4 Pixel5 Pixel6 ...

blank

D[23:12] val

Cb pix0

Cr pix0

Cb pix2

Cr pix2

Cb pix4

Cr pix4

Cb pix6

....

val val val

D[11:0] val

Y pix0

Y pix1

Y pix2

Y pix3

Y pix4

Y pix5

Y pix6

....

val val val

PCLK

DE

H/VSYNC

Figure 6. 16/20/24-bit YCbCr422 with separate syncs

www.ite.com.tw

T8720F V0.7.1

Apr-2013 Rev:1.02 23/40

IT66121FN

16/20/24-bit YCbCr422 with Embedded Syncs

This is similar to the previous format. The only difference is that the syncs are embedded. Bus width could be 16-bit, 20-bit or 24-bit.

YCbCr 4:2:2 16-bit YCbCr 4:2:2 20-bit YCbCr 4:2:2 24-bit

Pin Name Pixel#2N Pixel#2N+1 Pixel#2N Pixel#2N+1 Pixel#2N Pixel#2N+1

D0

D1

D2

D3 grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded

Y0

Y1 grounded grounded

Y0

Y1

Y0

Y1

Y2

Y3

Y0

Y1

Y2

Y3

D4

D5

D6

D7

D8

D9

D10

Y0

Y1

Y2

Y3

Y4

Y5

Y6

Y0

Y1

Y2

Y3

Y4

Y5

Y6

Y2

Y3

Y4

Y5

Y6

Y7

Y8

Y2

Y3

Y4

Y5

Y6

Y7

Y8

Y4

Y5

Y6

Y7

Y8

Y9

Y10

Y4

Y5

Y6

Y7

Y8

Y9

Y10

D11

D12

D13

D14

D15

D16

D17

D18

Y7 Y7 Y9 Y9 grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded Cb0 Cr0 grounded grounded

Cb0 Cr0

Cb1

Cb2

Cr1

Cr2

Cb1

Cb2

Cb3

Cb4

Cr1

Cr2

Cr3

Cr4

Y11

Cb0

Cb1

Cb2

Cb3

Cb4

Cb5

Cb6

Y11

Cr0

Cr1

Cr2

Cr3

Cr4

Cr5

Cr6

D19

D20

D21

D22

Cb3

Cb4

Cb5

Cb6

Cr3

Cr4

Cr5

Cr6

Cb5

Cb6

Cb7

Cb8

Cr5

Cr6

Cr7

Cr8

Cb7

Cb8

Cb9

Cb10

Cr7

Cr8

Cr9

Cr10

D23 Cb7 Cr7 Cb9 Cr9 Cb11 Cr11

HSYNC grounded grounded grounded grounded grounded grounded

VSYNC grounded grounded grounded grounded grounded grounded

DE grounded grounded grounded grounded grounded grounded

Table 5. Mappings of 16/20/24-bit YCbCr422 with embedded syncs

D[23:12] val val blank

SAV val val val

Pixel0 Pixel1 Pixel2 Pixel3 Pixel4 Pixel5 Pixel6

Cb pix0

Cr pix0

Cb pix2

Cr pix2

Cb pix4

Cr pix4

Cb pix6

...

....

blank

EAV val val

D[11:0] val FF 00 00 XY

Y pix0

Y pix1

Y pix2

Y pix3

Y pix4

Y pix5

Y pix6

....

FF 00

PCLK

DE

H/VSYNC

Figure 7. 16/20/24-bit YCbCr422 with embedded syncs

www.ite.com.tw

T8720F V0.7.1

Apr-2013 Rev:1.02 24/40

IT66121FN

Note:

1. FF, 00, 00, XY information are mapped to D[11:4]

2. 20-bit mode is compatible with BT1120 format 20-bit mode

www.ite.com.tw

T8720F V0.7.1

Apr-2013 Rev:1.02 25/40

IT66121FN

16/20/24-bit YCbCr422 with Embedded Syncs (BTA-T1004 Format)

The BTA-T1004 format is similar to the previous format except the SAV and EAV positions.

YCbCr 4:2:2 16-bit YCbCr 4:2:2 20-bit YCbCr 4:2:2 24-bit

Pin Name Pixel#2N Pixel#2N+1 Pixel#2N Pixel#2N+1 Pixel#2N Pixel#2N+1

D0

D1

D2

D3 grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded

Y0

Y1 grounded grounded

Y0

Y1

Y0

Y1

Y2

Y3

Y0

Y1

Y2

Y3

D4

D5

D6

D7

D8

D9

D10

Y0

Y1

Y2

Y3

Y4

Y5

Y6

Y0

Y1

Y2

Y3

Y4

Y5

Y6

Y2

Y3

Y4

Y5

Y6

Y7

Y8

Y2

Y3

Y4

Y5

Y6

Y7

Y8

Y4

Y5

Y6

Y7

Y8

Y9

Y10

Y4

Y5

Y6

Y7

Y8

Y9

Y10

D11

D12

D13

D14

D15

D16

D17

D18

Y7 Y7 Y9 Y9 grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded Cb0 Cr0 grounded grounded

Cb0 Cr0

Cb1

Cb2

Cr1

Cr2

Cb1

Cb2

Cb3

Cb4

Cr1

Cr2

Cr3

Cr4

Y11

Cb0

Cb1

Cb2

Cb3

Cb4

Cb5

Cb6

Y11

Cr0

Cr1

Cr2

Cr3

Cr4

Cr5

Cr6

D19

D20

D21

D22

Cb3

Cb4

Cb5

Cb6

Cr3

Cr4

Cr5

Cr6

Cb5

Cb6

Cb7

Cb8

Cr5

Cr6

Cr7

Cr8

Cb7

Cb8

Cb9

Cb10

Cr7

Cr8

Cr9

Cr10

D23 Cb7 Cr7 Cb9 Cr9 Cb11 Cr11

HSYNC grounded grounded grounded grounded grounded grounded

VSYNC grounded grounded grounded grounded grounded grounded

DE grounded grounded grounded grounded grounded grounded

Table 6. Mappings of YCbCr422 with embedded syncs (BTA-T1004 format)

D[23:12] val blank

SAV

FF 00

Pixel0 Pixel1 Pixel2 Pixel3 Pixel4 Pixel5 Pixel6

Cb pix0

Cr pix0

Cb pix2

Cr pix2

Cb pix4

Cr pix4

Cb pix6

...

....

FF

EAV blank

00 val

D[11:0] val 00 XY

Y pix0

Y pix1

Y pix2

Y pix3

Y pix4

Y pix5

Y pix6

....

00 XY val

PCLK

DE

H/VSYNC

Figure 8. 16/20/24-bit YCbCr422 with embedded syncs (BTA-T1004 format)

Note:

1. FF, 00, 00, XY information are mapped to D[23:16] and D[11:4]

www.ite.com.tw

T8720F V0.7.1

Apr-2013 Rev:1.02 26/40

IT66121FN

8/10/12-bit YCbCr422 with Embedded Syncs

This format is another variation of the YCbCr formats. The bus width is further reduced by half compared from the previous YCbCr 4:2:2 formats, to either 8-bit, 10-bit or 12-bit. To compensate for the halving of data bus, PCLK is doubled. With the double-rate input clock, luminance channel (Y) and chroma channels (Cb or Cr) are alternated.

D14

D15

D16

D17

D18

D19

D20

D21

D22

D23

HSYNC

VSYNC

DE

YCbCr 4:2:2 8-bit YCbCr 4:2:2 10-bit YCbCr 4:2:2 12-bit

Pin Name 1st PCLK 2nd PCLK 1st PCLK 2nd PCLK Pixel#2N Pixel#2N+1

D0

D1 grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded

D2

D3

D4

D5 grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded

C0

C1

Y0

Y1

D6

D7

D8

D9

D10

D11

D12

D13 grounded grounded grounded grounded

C0

C1

C2

C3

C4

C5

Y0

Y1

Y2

Y3

Y4

Y5

C0

C1

C2

C3

C4

C5

C6

C7

Y0

Y1

Y2

Y3

Y4

Y5

Y6

Y7

C2

C3

C4

C5

C6

C7

C8

C9

Y2

Y3

Y4

Y5

Y6

Y7

Y9

Y9

C6

C7 grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded

Y6

Y7 grounded grounded grounded grounded grounded

C8

C9 grounded grounded grounded grounded grounded

Y8

Y9 grounded grounded grounded grounded grounded

C10

C11 grounded grounded grounded grounded grounded

Y10

Y11 grounded grounded grounded grounded grounded

Table 7. Mappings of 8/10/12-bit YCbCr422 with embedded syncs

blank

SAV Pixel0 Pixel1 Pixel2 ...

...

blank

EAV

D[23:16]&[3:0]

D[15:4]

PCLK

DE

H/VSYNC

www.ite.com.tw val FF 00 00 XY

Cb pix0/1

Y pix0

Cr pix0/1

Y pix1

Cb pix2/3

Y pix2

Cr pix2/3

....

FF 00

T8720F V0.7.1

Apr-2013 Rev:1.02 27/40

IT66121FN

Figure 9. 8/10/12-bit YCbCr422 with embedded syncs

Note:

1. FF, 00, 00, XY information are mapped to D[15:8]

2. 8-bit mode is compatible with CCIR656 format

3. 10-bit mode is compatible with BT1120 format 10-bit mode

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T8720F V0.7.1

Apr-2013 Rev:1.02 28/40

IT66121FN

8/10/12-bit YCbCr422 with Separate Syncs

This format is simply the variation of previously mentioned one plus separate syncs.

YCbCr 4:2:2 8-bit

YCbCr 4:2:2 10-bit YCbCr 4:2:2 12-bit

Pin Name 1st PCLK 2nd PCLK 1st PCLK 2nd PCLK Pixel#2N Pixel#2N+1

D0

D1

D2

D3 grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded

D4

D5

D6

D7

D8

D9

D10 grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded

C0

C1

C2

Y0

Y1

Y2

C0

C1

C2

C3

C4

Y0

Y1

Y2

Y3

Y4

C0

C1

C2

C3

C4

C5

C6

Y0

Y1

Y2

Y3

Y4

Y5

Y6

D11

D12

D13

D14

D15

D16

D17

D18

C3

C4

Y3

Y4

C5

C6

Y5

Y6

C7

C8

Y7

Y9

C5

C6

Y5

Y6

C7

C8

Y7

Y8

C9

C10

Y9

Y10

C7 Y7

C9 Y9 C11 Y11 grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded

D19

D20

D21

D22

D23

HSYNC

VSYNC

DE grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded

HSYNC HSYNC HSYNC

VSYNC

DE

VSYNC

DE

VSYNC

DE

Table 8. Mappings of 8/10/12-bit YCbCr422 with separate syncs

blank Pixel0 Pixel1 Pixel2 ...

...

blank

D[23:16]&[3:0]

D[15:4] val

Cb pix0/1

Y pix0

Cr pix0/1

Y pix1

Cb pix2/3

Y pix2

Cr pix2/3

....

val val val

PCLK

DE

H/VSYNC

Figure 10. 8/10/12-bit YCbCr422 with separate syncs

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T8720F V0.7.1

Apr-2013 Rev:1.02 29/40

IT66121FN

The IT66121 supports another IO mapping method of YCbCr 4:2:2 formats which we call

Non-sequential IO Mode. The only difference between these two modes is the Y/Cb/Cr data mapping sequence of the IO pin. The following tables show the different mappings of these two modes.

Non-sequential IO mode of 16/20/24-bit YCbCr422

YCbCr 4:2:2 16-bit YCbCr 4:2:2 20-bit YCbCr 4:2:2 24-bit

Pin Name Pixel#2N Pixel#2N+1 Pixel#2N Pixel#2N+1 Pixel#2N Pixel#2N+1

D0

D1

D2

D3 grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded

Y0

Y1 grounded grounded

Y0

Y1

Y0

Y1

Y2

Y3

Y0

Y1

Y2

Y3

D4

D5

D6

D7

D8

D9

D10 grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded

Y0

Y1

Y2

Y0

Y1

Y2

Cb0

Cb1

Y2

Y3

Y4

Cr0

Cr1

Y2

Y3

Y4

Cb0

Cb1

Cb2

Cb3

Y4

Y5

Y6

Cr0

Cr1

Cr2

Cr3

Y4

Y5

Y6

D11

D12

D13

D14

D15

D16

D17

D18

Y3

Y4

Y5

Y6

Y7

Cb0

Cb1

Cb2

Y3

Y4

Y5

Y6

Y7

Cr0

Cr1

Cr2

Y5

Y6

Y7

Y8

Y9

Cb2

Cb3

Cb4

Y5

Y6

Y7

Y8

Y9

Cr2

Cr3

Cr4

Y7

Y8

Y9

Y10

Y11

Cb4

Cb5

Cb6

Y7

Y8

Y9

Y10

Y11

Cr4

Cr5

Cr6

D19

D20

D21

D22

D23

HSYNC

VSYNC

DE

Cb3

Cb4

Cb5

Cb6

Cb7

HSYNC

VSYNC

DE

Cr3

Cr4

Cr5

Cr6

Cr7

HSYNC

VSYNC

DE

Cb5

Cb6

Cb7

Cb8

Cb9

HSYNC

VSYNC

DE

Cr5

Cr6

Cr7

Cr8

Cr9

HSYNC

VSYNC

DE

Cb7

Cb8

Cb9

Cb10

Cb11

HSYNC

VSYNC

DE

Cr7

Cr8

Cr9

Cr10

Cr11

HSYNC

VSYNC

DE

Table 9. Mappings of 16/20/24-bit YCbCr422 non-sequential IO mode

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T8720F V0.7.1

Apr-2013 Rev:1.02 30/40

IT66121FN

Non-sequential IO mode of 8/10/12-bit YCbCr422

D14

D15

D16

D17

D18

D19

D20

D21

D22

D23

HSYNC

VSYNC

DE

YCbCr 4:2:2 8-bit YCbCr 4:2:2 10-bit YCbCr 4:2:2 12-bit

Pin Name 1st PCLK 2nd PCLK 1st PCLK 2nd PCLK Pixel#2N Pixel#2N+1

D0

D1 grounded grounded grounded grounded grounded grounded grounded grounded

C0

C1

Y0

Y1

D2

D3

D4

D5 grounded grounded grounded grounded grounded grounded grounded grounded

C0

C1 grounded grounded

Y0

Y1 grounded grounded

C2

C3 grounded grounded

Y2

Y3 grounded grounded

D6

D7

D8

D9

D10

D11

D12

D13 grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded

C0

C1

C2

C3

C4

C5

Y0

Y1

Y2

Y3

Y4

Y5

C2

C3

C4

C5

C6

C7

Y2

Y3

Y4

Y5

Y6

Y7

C4

C5

C6

C7

C8

C9

Y4

Y5

Y6

Y7

Y9

Y9

C6

C7 grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded

Y6

Y7 grounded grounded grounded grounded grounded

C8

C9 grounded grounded grounded grounded grounded

Y8

Y9 grounded grounded grounded grounded grounded

C10

C11 grounded grounded grounded grounded grounded

Y10

Y11 grounded grounded grounded grounded grounded

Table 10. Mappings of 8/10/12-bit YCbCr422 non-sequential IO mode

In additional to the previous input formats, there are three options can be supported by the IT66121.

DE-only option can be used for those input formats without H/VSync information. Dual-edge triggering with half bus width option can be used to reduce the necessary bus width and dual-edge triggering with half pixel clock option allows half input pixel clock. No all the input formats listed above can support three options and please refer to the IT66121 programming guide for more information. Some examples shown below are the corresponding timing relations when these options are enabled.

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T8720F V0.7.1

Apr-2013 Rev:1.02 31/40

IT66121FN

DE-Only Option: use 24-bit RGB/YCbCr444 (DE-only mode) as example

Pin Name

D0

D1

D2

D3

D4

D5

D6

D7

D8

D9

D10

D11

D12

D13

D14

D15

D16

D17

D18

D19

RGB

B0

B1

B2

B3

B4

B5

B6

B7

G0

G1

G2

G3

G4

G5

G6

G7

R0

R1

R2

R3

D20

D21

D22

D23

R4

R5

R6

R7

Cr4

Cr5

Cr6

Cr7

HSYNC grounded grounded

VSYNC grounded grounded

DE DE DE

Y4

Y5

Y6

Y7

Cr0

Cr1

Cr2

Cr3

YCbCr

Cb0

Cb1

Cb2

Cb3

Cb4

Cb5

Cb6

Cb7

Y0

Y1

Y2

Y3

Table 11. Mappings of 24-bit RGB/YCbCr444 (DE-only mode)

D[23:16] blank Pixel0 Pixel1 Pixel2 Pixel3 Pixel4 Pixel5 Pixel6 val

R/Cr pix0

R/Cr pix1

R/Cr pix2

R/Cr pix3

R/Cr pix4

R/Cr pix5

R/Cr pix6

...

....

blank val val val

D[15:8] val

G/Y pix0

G/Y pix1

G/Y pix2

G/Y pix3

G/Y pix4

G/Y pix5

G/Y pix6

....

val val val

D[7:0]

PCLK

DE

H/VSYNC val

B/Cb pix0

B/Cb pix1

B/Cb pix2

B/Cb pix3

B/Cb pix4

B/Cb pix5

B/Cb pix6

....

val val val

Figure 11. 24-bit RGB/YCbCr444 (DE-only mode)

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T8720F V0.7.1

Apr-2013 Rev:1.02 32/40

IT66121FN

Dual-Edge Triggering with Half Bus Width: use 12-bit RGB/YCbCr444 format as example

RGB YCbCr

Pin Name 1st edge 2nd edge 1st edge 2nd edge

D0

D1

D2

D3

B0

B1

B2

B3

G4

G5

G6

G7

Cb0

Cb1

Cb2

Cb3

Y4

Y5

Y6

Y7

D4

D5

D6

D7

D8

D9

D10

B4

B5

B6

B7

G0

G1

G2

R0

R1

R2

R3

R4

R5

R6

Cb4

Cb5

Cb6

Cb7

Y0

Y1

Y2

Cr0

Cr1

Cr2

Cr3

Cr4

Cr5

Cr6

D11

D12

D13

D14

D15

D16

D17

D18

G3 grounded grounded grounded grounded grounded grounded grounded

R7 grounded grounded grounded grounded grounded grounded grounded

Y3 grounded grounded grounded grounded grounded grounded grounded

Cr7 grounded grounded grounded grounded grounded grounded grounded

D19

D20

D21

D22

D23

HSYNC

VSYNC

DE grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded

HSYNC HSYNC

VSYNC

DE

VSYNC

DE

Table 12. Mappings of 12-bit RGB/YCbCr444 dual-edge triggering (separate syncs)

blank Pixel0 Pixel1 Pixel2 ...

...

blank

D[23:12]

D[11:8] val

G/Y pix0

[3:0]

R/Cr pix0

[7:4]

G/Y pix1

[3:0]

R/Cr pix1

[7:4]

G/Y pix2

[3:0]

R/Cr pix2

[7:4]

G/Y pix3

[3:0]

....

val val val

D[7:4] val

B/Cb pix0

[7:4]

R/Cr pix0

[3:0]

B/Cb pix1

[7:4]

R/Cr pix1

[3:0]

B/Cb pix2

[7:4]

R/Cr pix2

[3:0]

B/Cb pix3

[7:4]

....

val val val

D[3:0] val

B/Cb pix0

[3:0]

G/Y pix0

[7:4]

B/Cb pix1

[3:0]

G/Y pix1

[7:4]

B/Cb pix2

[3:0]

G/Y pix2

[7:4]

B/Cb pix3

[3:0]

....

val val val

PCLK

DE

H/VSYNC

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Figure 12. 12-bit RGB/YCbCr444 dual-edge triggering (separate syncs)

T8720F V0.7.1

Apr-2013 Rev:1.02 33/40

IT66121FN

Dual-Edge Triggering with Half Pixel Clock:

Example 1: 24-bit RGB/YCbCr444 with Separate Syncs and Dual-Edge Triggering

Pin Name

D0

D1

D2

D3

D4

D5

D6

D7

D8

D9

D10

D11

D12

D13

D14

D15

D16

D17

D18

D19

D20

D21

D22

D23

HSYNC

VSYNC

DE

G4

G5

G6

G7

R0

R1

R2

R3

RGB

B0

B1

B2

B3

B4

B5

B6

B7

G0

G1

G2

G3

R4

R5

R6

R7

HSYNC

VSYNC

DE

Y4

Y5

Y6

Y7

Cr0

Cr1

Cr2

Cr3

YCbCr

Cb0

Cb1

Cb2

Cb3

Cb4

Cb5

Cb6

Cb7

Y0

Y1

Y2

Y3

Cr4

Cr5

Cr6

Cr7

HSYNC

VSYNC

DE

Table 13. Mappings of 24-bit RGB/YCbCr444 dual-edge triggering (separate syncs)

D[23:16] blank Pixel0 Pixel1 Pixel2 Pixel3 Pixel4 Pixel5 Pixel6 val

R/Cr pix0

R/Cr pix1

R/Cr pix2

R/Cr pix3

R/Cr pix4

R/Cr pix5

R/Cr pix6

...

....

blank val val val

D[15:8] val

G/Y pix0

G/Y pix1

G/Y pix2

G/Y pix3

G/Y pix4

G/Y pix5

G/Y pix6

....

val val val

D[7:0]

PCLK

DE

H/VSYNC val

B/Cb pix0

B/Cb pix1

B/Cb pix2

B/Cb pix3

B/Cb pix4

B/Cb pix5

B/Cb pix6

....

val val val

Figure 13. 24-bit RGB/YCbCr444 dual-edge triggering (separate syncs)

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T8720F V0.7.1

Apr-2013 Rev:1.02 34/40

IT66121FN

Example 2: 16/20/24-bit YCbCr422 with Separate Syncs using Dual-Edge Triggering

YCbCr 4:2:2 16-bit YCbCr 4:2:2 20-bit YCbCr 4:2:2 24-bit

Pin Name 1st edge 2nd edge 1st edge 2nd edge 1st edge 2nd edge

D0

D1

D2

D3 grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded

Y0

Y1 grounded grounded

Y0

Y1

Y0

Y1

Y2

Y3

Y0

Y1

Y2

Y3

D4

D5

D6

D7

D8

D9

D10

Y0

Y1

Y2

Y3

Y4

Y5

Y6

Y0

Y1

Y2

Y3

Y4

Y5

Y6

Y2

Y3

Y4

Y5

Y6

Y7

Y8

Y2

Y3

Y4

Y5

Y6

Y7

Y8

Y4

Y5

Y6

Y7

Y8

Y9

Y10

Y4

Y5

Y6

Y7

Y8

Y9

Y10

D11

D12

D13

D14

D15

D16

D17

D18

Y7 Y7 Y9 Y9 grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded Cb0 Cr0 grounded grounded

Cb0 Cr0

Cb1

Cb2

Cr1

Cr2

Cb1

Cb2

Cb3

Cb4

Cr1

Cr2

Cr3

Cr4

Y11

Cb0

Cb1

Cb2

Cb3

Cb4

Cb5

Cb6

Y11

Cr0

Cr1

Cr2

Cr3

Cr4

Cr5

Cr6

D19

D20

D21

D22

D23

HSYNC

VSYNC

DE

Cb3

Cb4

Cb5

Cb6

Cb7

HSYNC

VSYNC

DE

Cr3

Cr4

Cr5

Cr6

Cr7

HSYNC

VSYNC

DE

Cb5

Cb6

Cb7

Cb8

Cb9

HSYNC

VSYNC

DE

Cr5

Cr6

Cr7

Cr8

Cr9

HSYNC

VSYNC

DE

Cb7

Cb8

Cb9

Cb10

Cb11

HSYNC

VSYNC

DE

Cr7

Cr8

Cr9

Cr10

Cr11

HSYNC

VSYNC

DE

Table 14. Mappings of 16/20/24-bit YCbCr422 dual-edge triggering (separate syncs)

blank Pixel0 Pixel1 Pixel2 Pixel3 Pixel4 Pixel5 Pixel6 ...

blank

D[23:12] val

Cb pix0

Cr pix0

Cb pix2

Cr pix2

Cb pix4

Cr pix4

Cb pix6

....

val val val

D[11:0] val

Y pix0

Y pix1

Y pix2

Y pix3

Y pix4

Y pix5

Y pix6

....

val val val

PCLK

DE

H/VSYNC

Figure 14. 16/20/24-bit YCbCr422 dual-edge triggering (separate syncs)

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T8720F V0.7.1

Apr-2013 Rev:1.02 35/40

IT66121FN

Example 3: 8/10/12-bit YCbCr422 with Embedded Syncs using Dual-Edge Triggering

D15

D16

D17

D18

D19

D20

D21

D22

D23

HSYNC

VSYNC

DE

Pin Name

D0

D1

D2

D3

D4

D5

D6

D7

D8

D9

D10

D11

D12

D13

D14

YCbCr 4:2:2 8-bit YCbCr 4:2:2 10-bit YCbCr 4:2:2 12-bit

1st edge 2nd edge 1st edge 2nd edge 1st edge 2nd edge grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded

C0

C1

Y0

Y1

C0

C1

C2

C3

Y0

Y1

Y2

Y3

C0

C1

C2

C3

C4

C5

C6

C7

Y0

Y1

Y2

Y3

Y4

Y5

Y6

Y7

C2

C3

C4

C5

C6

C7

C8

C9

Y2

Y3

Y4

Y5

Y6

Y7

Y8

Y9

C4

C5

C6

C7

C8

C9

C10

C11

Y4

Y5

Y6

Y7

Y9

Y9

Y10

Y11 grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded

Table 15. Mappings of 8/10/12-bit YCbCr422 dual-edge triggering (embedded syncs)

blank

SAV Pixel0 Pixel1 Pixel2 ...

...

blank

EAV

D[23:16]&[3:0]

D[15:4]

PCLK val FF 00 00 XY

Cb pix0/1

Y pix0

Cr pix0/1

Y pix1

Cb pix2/3

Y pix2

Cr pix2/3

....

DE

H/VSYNC

Figure 15. 8/10/12-bit YCbCr422 dual-edge triggering (embedded syncs)

FF 00

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T8720F V0.7.1

Apr-2013 Rev:1.02 36/40

IT66121FN

System Design Consideration

As a high-performance receiver/transmitter, ITE’s RX/TX is capable of receiving/transmitting those signals that are attenuated and degraded by the HDMI cables. These signals are usually very small in amplitudes in addition to the distortion that the cable inflicts on them. The analog front-end of ITE’s

RX/TX is designed to combat environment noises as well as interference to some degree. However, to get the optimum performance the system designers should follow the guideline below when designing the application circuits and PCB layout.

HDMI Differential Signal

The characteristic impedance of all differential PCB traces (RX2P/M, RX1P/M, RX0P/M, and

RXCP/M) should be kept 100_ all the way from the HDMI connector to ITE’s RX/TX. This is very crucial to the system performance at high speeds. When routing these 4 differential transmission lines (8 single-ended lines in total), the following guidelines should be followed:

1. The signals traces should be on the outside layers (e.g. TOP layer) while beneath it there should be a continuous ground plane in order to maintain the called micro-strip structure, giving stable and well-defined characteristic impedances.

2. Cornering, through holes, crossing and any irregular signal routing should be avoided so as to prevent from disrupting the EM field and creating discontinuity in characteristic impedance.

3. ITE’s RX/TX should be placed as close to the HDMI connector as possible. Since the TMDS signal pins of ITE’s RX/TX perfectly match the order of the connector pins, it is very convenient to route the signal directly into the chip, without through holes or angling.

4. Carefully choose the width and spacing of the differential transmission lines as their characteristic impedance depends on various parameters of the PCB: trace width, trace spacing, copper thickness, dielectric constant, dielectric thickness, etc. Careful 3D EM simulation is the best way to derive a correct dimension that enables nominal 100_ differential impedance. Please contact us directly for technical support of this issue.

5. The sensitive HDMI differential signals should be taken when routing. To reduce the differential unbalanced effect, it is recommended to separate at least 3 times the dielectric thickness between the signal layer and the reference layer to any other adjacent signal or

GND plane to reduce noise inference and jitter. (or 25 mils is enough space in almost PCB stack)

ESD Consideration

Special care should be taken when adding discrete ESD devices to all differential PCB traces

(RX2P/M, RX1P/M, RX0P/M, and RXCP/M). ITE’s RX/TX is designed to provide ESD protection for up to 2kV at these pins. Adding discrete ESD diodes could enhance the ESD capability, but at the same time will inevitably add capacitive loads, therefore degrade the electrical performance at

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T8720F V0.7.1

Apr-2013 Rev:1.02 37/40

IT66121FN

high speeds. If not chosen carefully, these diodes coupled with less-than-optimal layout would prevent the system from passing the SINK TMDS-Differential Impedance test in the HDMI

Compliance Test (Test ID 8-8). Besides, most general-purpose ESD diodes are relatively large in size, forcing the high-speed differential lines to corner several times and therefore introducing severe reflection. Carefully choosing an ESD diode that's designed for HDMI signaling could lead to a minimum loading as well as an optimized layout. Commercially available devices such as

Semtech's RClamp0524p that take into consideration of all aspects are recommended. A layout example is shown in Fig. 16, with referenced FR4 PCB structure included. Note that the ESD diodes should be placed as close to the HDMI connectors as possible to yield the best ESD performances.

100ohm differentially

68 67 66 65

52

51

50

49

56

55

54

53

60

59

58

57

64

63

62

61

44

43

42

41

40

39

48

47

46

45

EXAMPLE:

W S

ε r

=4.3

W

1.8mil

8mil

1.4mil

GND

GND

RClamp0524p

RClamp0524p

100 ohm: W=9mil, S=11mil

DATA2+

GND

DATA2-

DATA1+

GND

DATA1-

DATA0+

GND

DATA0-

CLOCK+

GND

CLOCK-

CEC

reserved

SCL

SDA

GND

+5V

HPD

Figure 16: PCB layout example for high-speed transmission lines with RClamp0524p

Notes: The PCB stack and material will affect differential impedance. The customer shall co-work with PCB provider to obtain the real 100 ohm impedance based on actual PCB stack and material.

Power Supply Bypassing

1. It is recommended to bypass each group of power supply pin with a 0.1µF capacitor.

2. It is also recommended that the bypass capacitor be located within about 0.5cm distance of each power pin.

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T8720F V0.7.1

Apr-2013 Rev:1.02 38/40

IT66121FN

Device

VCC

0.01uF

Low ESL

VCC

Decoupling

Capacitor

VSS

Via to GND

3. Avoid placing the capacitor on the opposite side of the PC board from the HDMI IC.

4. It is recommended to add ferrite beads for analog powers. Ex. PVDD, PVCC, AVDD etc…

5. Shorter power loop makes better performance.

High Speed Digital Input/Output Signals(Both Data and Clocks)

1. To obtain good signal quality and avoid EMI issue, 4-layres PCB stacks are recommended.

2. Try to minimize the trace length that the digital outputs have to drive.

3. Keep these high speed signals refer to a continue GND or power plane, no GND or power slot break the returning current path.

4. It’s recommended to add a series resistor of value 33 ohm to suppress reflections, reduce

EMI, and reduce the current spikes. These series resistors should be place as close to the driving pins as possible.

5. If possible, try to place ITE’s RX/TX and related “Scalar IC” on the same PCB side and route these high speed signals not to through vias to get the better signal quality.

6. The sensitive clock (PCLK) signals should be taken when routing. To reduce the crosstalk effect, it is recommended to separate at least 2 times the maximum dielectric thickness between the signal layer and the reference layer to any other adjacent signal to reduce noise inference and jitter.

www.ite.com.tw

T8720F V0.7.1

Apr-2013 Rev:1.02 39/40

IT66121FN

Package Dimensions

www.ite.com.tw

Figure 17. 64-pin QFN Package Dimensions

T8720F V0.7.1

Apr-2013 Rev:1.02 40/40

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