Datasheet for Ic-ttl Shift Register

Datasheet for Ic-ttl Shift Register
NTE74166
Integrated Circuit
TTL − 8−Bit Parallel or Serial−In/Serial−Out Shift Register
Description:
The NTE74166 is an 8−bit parallel−in or serial−in, serial−out shift register in a 16−Lead plastic DIP
type package having the complexity of 77 equivalent gates on a monolithic chip. The parallel−in or
serial−in modes are established by the shift/load input. When high, this input enables the serial data
input and couples the eight flip−flops for serial shifting with each clock pulse. When low, the parallel
(broadside) data inputs are enabled and synchronous loading occurs on the next clock pulse. During
parallel loading, serial data flow is inhibited. Clocking is accomplished on the low−to−high−level edge
of the clock pulse through a two−input positive NOR gate permitting one input to be used as a clock
enable or clock−inhibit function. Holding either of the clock inputs high inhibits clocking; holding either
low enables the other clock input. This, of course, allows the system clock to be free−running and the
register can be stopped on command with the other clock input. The clock inhibit input should be
changed to the high level only while the clock input is high. A buffered, direct clear input overrides all
other inputs, including the clock, and sets all flip−flops to zero.
The NTE74166 is compatible with most other TTL logic families and all inputs are buffered to lower
the drive requirements to one LS−TTL standard load. Input clamping diodes minimize switching transients an simplify system design.
Features:
D Synchronous Load
D Direct Overriding Clear
D Parallel−to−Serial Conversion
Absolute Maximum Ratings: (Note 1)
Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7V
DC Input Voltage, VIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5V
Power Dissipation, PD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 360mW
Operating Temperature Range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0C to +70C
Storage Temperature Range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65C to +150C
Note 1. Unless otherwise specified, all voltages are referenced to GND.
Recommended Operating Conditions:
Parameter
Symbol
Min
Typ
Max
Unit
Supply Voltage
VCC
4.75
5.0
5.25
V
High−Level Output Current
IOH
−
−
−800
A
Low−Level Output Current
IOL
−
−
16
mA
fclock
0
−
25
MHz
Width of Clock or Clear Pulse
tw
20
−
−
ns
Mode−Control Setup Time
tsu
30
−
−
ns
Data Setup Time
tsu
20
−
−
ns
Hold Time at Any Input
th
0
−
−
ns
Operating Temperature Range
TA
0
−
+70
C
Min
Typ
Max
Unit
Clock Frequency
Electrical Characteristics: (Note 2, Note 3)
Parameter
Symbol
Test Conditions
High Level Input Voltage
VIH
2
−
−
V
Low Level Input Voltage
VIL
−
−
0.8
V
Input Clamp Voltage
VIK
VCC = MIN, II = −12mA
−
−
−1.5
V
High Level Output Voltage
VOH
VCC = MIN, VIH = 2V, VIL = 0.8V, IOH = −800A
2.4
3.4
−
V
Low Level Output Voltage
VOL
VCC = MIN, VIH = 2V, VIL = 0.8V, IOL = 16mA
−
0.2
0.4
V
1
mA
Input Current
II
VCC = MAX, VI = 5.5V
−
−
High Level Input Current
IIH
VCC = MAX, VI = 2.4V
−
−
40
A
Low Level Input Current
IIL
VCC = MAX, VI = 0.4V
−
−
−1.6
mA
Short−Circuit Output Current
IOS
VCC = MAX, Note 4
−18
−
−57
mA
Supply Current
ICC
VCC = MAX, Note 5
−
90
122
mA
Note 2. .For conditions shown as MIN or MAX, use the appropriate value specified under “Recommended
Operation Conditions”.
Note 3. All typical values are at VCC = 5V, TA = +25C.
Note 4. Not more than one output should be shorted at a time.
Note 5. With all outputs open, 4.5V applied to the serial input, all other inputs except the clock grounded,
ICC is measured after a momentary GND, then 4.5V, is applied to clock.
Switching Characteristics: (VCC = 5V, TA = +25C unless otherwise specified)
Parameter
Maximum Clock Frequency
Symbol
fmax
Test Conditions
RL = 400, CL = 15pF
Min
Typ
Max
Unit
25
35
−
MHz
Propagation Delay Time
(From Clear Input to High−to−Low Level Output)
tPHL
−
23
35
ns
Propagation Delay Time
(From Clock Input to High−to−Low Level Output)
tPHL
−
20
30
ns
Propagation Delay Time
(From Clock Input to Low−to−High Level Output)
tPLH
−
17
26
ns
Function Table:
Inputs
CLEAR
L
H
H
H
H
H
SHIFT/
LOAD
X
X
L
H
H
X
Clock
Inhibit
X
L
L
L
L
H
Clock
X
L




Serial
X
X
X
H
L
X
Parallel
A...H
X
X
a...h
X
X
X
Internal
Outputs
QA
QB
L
L
QA0 QB0
a
b
H
QAn
L
QAn
QA0 QB0
Pin Connection Diagram
SER 1
16 VCC
A 2
B 3
15 SH/LD
14 H
C 4
13 QH
D 5
12 G
CLK INH 6
11 F
CLK 7
10 E
GND 8
9 CLR
16
9
1
8
.870 (22.0) Max
.260 (6.6)
Max
.200
(5.08)
Max
.100 (2.54)
.700 (17.78)
.099 (2.5) Min
Output
QH
L
QH0
h
QGn
QGn
QH0
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