User's manual | Eagle Technology PCI703-16/A User`s manual

PCI 703 Series

PCI PnP Analog Board

User’s Manual

PCI703-16/A, PCI703-32/A PCI703-64/A

PCI703S-8/A, PCI703S-16/A

Eagle Technology – Cape Town, South Africa

Copyright © 2001-2004

www.eagledaq.com

PCI 703 User Manual Eagle Technology - Data Acquisition

Analog Boards

Data Acquisition and Process Control

© Eagle Technology

31-35 Hout Street

•

Cape Town

•

South Africa

Phone +27 21 423 4943

•

Fax +27 21 424 4637

Email [email protected]

Eagle Technology © Copyright 2001-2004 – www.eagledaq.com i


Copyright

All rights reserved. No part of this publication may be reproduced, stored in a retrieval system , or transmitted, in any form or any means, electronic, mechanical, by photographing, recording, or otherwise without prior written permission.

Copyright © Eagle Technology, South Africa

July 2004

Revision 1.12

Information furnished in this manual is believed to be accurate and reliable; however no responsibility is assumed for its use, or any infringements of patents or other rights of third parties, which may result from its use.

Trademarks and Logos in this manual are the property of their respective owners.

Product Warranty

Eagle Technology, South Africa, warrants its products from defect in material and workmanship from confirmed date of purchase for a period of one year if the conditions listed below are met. The product warranty will call the Eagle Technology Data Acquisition Device short as ETDAQD.

•

The warranty does not apply to an ETDAQD that has been previously repaired, altered, extended by any other company or individual outside the premises of Eagle Technology.

•

That a qualified person configure and install the ETDAQD, and damages caused to a device during installation shall make the warranty void and null.

•

The warranty will not apply to conditions where the ETDAQD has been operated in a manner exceeding its specifications.

Eagle Technology, South Africa, does not take responsibility or liability of consequential damages, project delays, damaging of equipment or capital loss as a result of its products.

Eagle Technology, South Africa, holds the option and final decision to repair or replace any

ETDAQD. Proof of purchase must be supplied when requesting a repair.

Eagle Technology © Copyright 2001-2004 – www.eagledaq.com ii


TABLE OF CONTENTS

1.

INTRODUCTION

Features

Applications

Key Specifications

Software Support

Contact Details

2.

INSTALLATION

Package

Operating System Support

Hardware Installation

Software Installation

Windows 98/2000/ME

Post installation

Windows NT

Accessories

3.

INTERCONNECTIONS

External Connectors

PCI703-16/A

Connector Pin Assignments

PCI703-16/A

PCI703-32/64/A

PCI703S-8/16/A

Cable Pin Assignments

Y–Cable 1 (PCI 703-16/A) Analog –DB37 F

Y-Cable 3 (PCI 703-64/A) Analog

Y–Cable 1, Y-Cable 3, Y-Cable 4 (PCI 703-16/64/S/A) Digital –DB37 F

Signal Definitions

Pin Descriptions

Analog Input (ACH0-63)

Analog Input Sensing (AISENSE)

Analog Input Ground (AIGND)

Analog Out put Ground (AOGND)

Analog Outputs (DAC0-1)

Digital Input/Outputs (DIO0-7)

Multi Function Digital Input/Outputs (PIO0-7)

TRIG1

3

3

3

3

4

4

7

9

9

2

2

2

1

1

2

10

10

10

12

12

13

13

14

11

11

11

11

14

14

14

14

14

14

14

14

14

Eagle Technology © Copyright 2001-2004 – www.eagledaq.com iii

PCI 703 User Manual

Frequency Output (FREQ_OUT)

ADC Scan Clock (SCANCLK)

Counters (GPCTR0-1)

+5V Power Pin (+5V)

Digital Ground (DGND)

Eagle Technology - Data Acquisition

Analog Input Connections

Analog Input Connections - SAMPLE-AND-HOLD

Differential Input Pairing

4.

PROGRAMMING GUIDE

EDR Enhanced API

Digital Inputs/Outputs

Reading the Digital Inputs

Writing to the Digital Outputs

Counters

Writing the initial counter value

Configuring a counter

Controlling the counter gate

Analog Output

Writing to a DAC channel

Generating a Waveform

Analog Input

Reading a single voltage from a channel

Configuring the ADC subsystem for scanning

Digital triggering

Analog triggering

Starting and Stopping the ADC process

Getting data from the driver buffer

Querying the ADC subsystem

Query Codes

How to use query codes

API Call

ActiveX Call

How to change the hardware FIFO depth

How to check for available data

How to get the driver buffer size

How to get the number of ADC channels

How to check the status of the driver buffer

5.

CALIBRATION

Requirements

A.

SPECIFICATIONS

Maximum Transfer Bandwidth – PCI703/S

Analog Input Characteristics – PCI703

Input Characteristics

Eagle Technology © Copyright 2001-2004 – www.eagledaq.com iv

17

17

18

18

18

19

19

19

20

21

21

21

28

28

28

28

28

29

29

29

29

23

23

23

24

24

26

26

27

30

30

31

31

31

31

15

15

15

14

14

15

15

15


Conversion Characteristics

Differential Input Amplifier Characteristics (AD620BR)

Analog Input Characteristics – PCI703S

Differential Input Amplifier Characteristics (AD620BR)

Sample and Hold Amplifier Characteristics (AD684)

Programmable Gain Amplifier Characteristics

Input Characteristics

Conversion Characteri stics

Analog Output Characteristics

Output Characteristics

Conversion Characteristics (Calibrated)

Voltage Output Characteristics

Digital Input/Output Characteristics

Multifunction Input/Output Characteristics

Timing Input/Output Characteristics

Other

B.

CONFIGURATION CONSTANTS

Query Codes

Error Codes

Digital I/O Codes

Analog Input Gain Codes – PCI703-16/32/64/A

Analog Input Gain Codes – PCI703S -8/16/A

Analog Input Range Codes – PCI703-16/32/64/A

C.

LAYOUT DIAGRAM

D.

ORDERING INFORMATION

35

35

35

35

35

35

35

31

31

33

33

33

33

33

32

32

32

32

32

32

33

34

34

37

38

Eagle Technology © Copyright 2001-2004 – www.eagledaq.com v


Table of Figures

Figure 3 -A PCI 703 Interconnections ............................................................................................................10

Figure 4 -A EDR Enhanced Design ................................................................................................................17

Eagle Technology © Copyright 2001-2004 – www.eagledaq.com vi


Table of Tables

Table 1-1 PCI703 16/32/64 Versions ..............................................................................................................1

Table 1-2 PCI703S Versions .............................................................................................................................2

Table 2-1 Operating System Support .............................................................................................................3

Table 3-1 Pinouts for PCI703-16/A (External Connector – SCSI 68) ................................................11

Table 3-2 Pinouts for PCI703-32/64/A (External Connector – SCSI 100) .......................................11

Table 3-3 Pinouts for PCI703S -8/16/A (External Connector – SCSI 68) .........................................12

Table 3-4 Y-Cable 1 Analog Connector .......................................................................................................12

Table 3-5 Y-Cable 3 Analog Connector .......................................................................................................13

Table 3-6 Y-Cable 1,3,4 Digital Connector.................................................................................................13

Table 3-7 Differential Channel Assignment................................................................................................16

Table 4-1 Counter Assignment .......................................................................................................................19

Table 4-2 Counter Configuration....................................................................................................................20

Table 4-3 Gate Configuration ..........................................................................................................................20

Table D-D-1 Ordering Information .................................................................................................................38

Eagle Technology © Copyright 2001-2004 – www.eagledaq.com vii

Eagle Technology - Data Acquisition PCI 703 User Manual

1

1. Introduction

The PCI703 series are 32-bit PCI bus architecture data acquisition boards. They are available in four models, the 16, 32 and 64 channels analog input board and the sample-and-hold version. The PCI703 contains digital input and output ports, onboard counters, a frequency generator, analog-in and analog-out sub-systems. The PCI703 is a multi-purpose analog board that can be used in many applications.

Features

The PCI703 does have some very unique features and are short listed below:

•

32-bit PCI bus Revision 2.2 compliant at 33MHz.

•

PCI Bus 3.3V compatible.

•

PCI Bus Master DMA.

•

Fully individually programmable analog-in channels.

•

Analog-out waveform generation support.

•

Sample-and-hold option.

Feature

Number of analog input channels

PCI703-XX

PCI703-16 PCI703-32 PCI703-64

16 32 64

0

PCI703-XXA

PCI703-16A PCI703-32A

16 32

2 Number of analog output channels

A/D resolution @ 400 KHz

A/D FIFO depth

A/D channel list depth

D/A resolution @ 100 KHz

D/A FIFO depth

D/A waveform generation capability

Triggering capability

14

4096

4096

-

-

-

14

4096

4096

14

4096

YES

Counters

Frequency generation

Number of digital input/output lines

Number of multi function digital

I/O lines

Internal, External.

Analog & Digital.

Post & Pre-Trigger

3

1

8

10

Internal, External.

Analog & Digital.

Post & Pre-Trigger

3

1

8

10

PCI703-64A

64

Table 1-1 PCI703 16/32/64 Versions

Eagle Technology © Copyright 2001-2004 – www.eagledaq.com 1


Feature

Number of analog input channels

Number of analog output channels

A/D resolution @ 400 KHz

A/D FIFO depth

A/D channel list depth

D/A resolution @ 100 KHz

D/A FIFO depth

D/A waveform generation capability

Triggering capability

PCI 703S-8

8

0

14

4096

4096

-

-

-

Internal, External.

Analog & Digital.

Post & Pre-Trigger

3

1

8

10


PCI 703S-8A

16

2

4096

4096

14

4096

YES

Internal, External.

Analog & Digital.

Post & Pre-Trigger

3

2

8

10

PCI 703S-16

16

0

14

4096

4096

-

-

-

Internal, External.

Analog & Digital.

Post & Pre-Trigger

3

1

8

10

Counters

Frequency generation

Number of digital input/output lines

Number of multi function digital I/O lines

Table 1-2 PCI703S Versions

Applications

The PCI703 can be used in the following applications:

•

Vibration monitoring.

•

Transducer monitoring.

•

Automation and test equipment.

•

Signal generation.

•

Laboratory training.

•

Medical applications.

Key Specifications

•

14-bit analog input @ 400 KHz.

•

Fully programmable sample-and-hold analog input system with triggering.

•

14-bit analog output @ 400 KHz.

•

Independent waveform generation capability.

PCI 703S-16A

16

2

14

4096

4096

14

4096

YES

Internal, External.

Analog & Digital.

Post & Pre-Trigger

3

1

8

10

Software Support

The PCI703 is supported by EDR Enhanced and comes with an extensive range of examples.

The software will help you to get your hardware going very quickly. It also makes it easy to develop complicated control applications quickly. All operating system drivers, utility and test software are supplied on the Eagle Technology CD-Rom. The latest drivers can also be downloaded from the Eagle Technology website. For further support information see the

Contact Details section.

Contact Details

Below are the contact details of Eagle Technology.

Eagle Technology

PO Box 4376

Cape Town

8000

South Africa

Telephone +27 (021) 423 4943

Fax +27 (021) 424 4637

E-Mail [email protected]

Website http://www.eagledaq.com



2

2. Installation

This chapter describes how to install and configure the PCI703 for the first time. Minimal configuration is necessary; almost all settings are done through software. The PCI BIOS or operating system will take care of all resource assignments.

Package

PCI703 package will contain the following:

•

PCI703 PCI board

•

Software CD-Rom

Operating System Support

PCI703 support the following operating systems

Board Type

PCI703-16/A

PCI703-16/A

PCI703-64/A

PCI703S-8/16/A

Revision

Revision 1

Revision 2

Revision 2

Revision 1

Operating Systems

Windows NT/2000

Windows NT/2000/98/ME



Table 2-1 Operating System Support

Driver Type

NT Sys

NT Sys, WDM PnP

NT Sys, WDM PnP

NT Sys, WDM PnP

Hardware Installation

This section will describe how to install your PCI board into your computer.

•

Switch off the computer and disconnect from power socket.

Failure to disconnect all power cables can result in hazardous conditions, as there may be dangerous voltage levels present in externally connected cables.

•

Remove the cover of the PC.

•

Choose any open PCI slot and insert PCI board

•

Insert bracket screw and ensure that the board sits firmly in the PCI socket.

•

Replace the cover of the PC.

•

Reconnect all power cables and switch the power on.

•

The hardware installation is now completed.



Software Installation

Windows 98/2000/ME

Installing the Windows 98/2000 device driver is a very straightforward task. Because it is plug and play Windows will auto detect the PCI board as soon as it is installed. No setup is necessary. You simply have to supply Windows with a device driver.

Wait until Windows detects the new hardware

Select Next



Select “Search for a suitable driver for my device…” and select next

Make sure only “Specify a location” is selected and select next



Select the browse button and search for the PCI703.inf file on the Eagle CD-Rom.

The driver is normally located in the <CDROM>:\EDRE\DRIVERS \WDM \PCI703 directory.

The PCI703/16/64 use the same driver.

However the PCI703S has a different driver. Please sure that you use the appropriate driver for your board.



Select next when found.


Select next again.

When done you might have to restart your computer.

Post installation

When done with the driver installation the device manager can be open to make sure the installation was a success.



•

First make sure that the driver is working properly by opening the Device Manager.

•

Check under the Eagle Data Acquisition list if your board is listed and working properly. See picture below.

•

Clearly you can see that the PCI device is listed and working properly.

•

Further open the control panel and then the EagleDAQ folder. This dialog should list all installed hardware. Verify your board’s properties on this dialog. See picture below



Now the first part of your installation has been completed and ready to install the EDR

Enhanced Software Development Kit.

•

Run edreapi.exe found on the Eagle CD-Rom and follow the on screen instructions

Windows NT

Windows NT does not require any special setup procedure. The Windows NT driver does not support plug and play. If Windows 2000 detects a new device simply install a default driver, or so called placeholder. This will disable the device in the plug and play manager.

To install the Windows NT drivers simply run edrewinnt.exe on the Eagle CD-Rom. This will automatically install the device drivers. Restart your computer when done. Open the

EagleDAQ folder in the control panel to check if your installation was successful.

Accessories

The PCI703 has got a wide variety of accessories that it can be connected too. See the Eagle

Technology catalog for more information.



3

3. Interconnections

The PCI703 has got one external connector that includes connections for analog-in, analogout, digital I/O, counters and power. All connections are made through this connector situated on the card’s bracket.

A wide variety of genuine accessories available from Eagle Technology also make interfacing to the PCI703 very easy. Accessories are available in the form of cables, screw terminals and application modules.

External Connectors

PCI703-16/A

The PCI703-16/A has a SCSI male centronics 68-way connector. Two types of cables are available, 68-way SCSI-II D -Sub (F) to (M) screened cable connecting to an adaptor

ADPT6868 and a Y-Cable 68-way SCSI-II D -Sub (F) to 2 x DB37 (F) connection to application modules and adaptors. Application modules include the PC43A4 and PC52A1.

Adaptors would be the ADPT3740. See diagram below.

Figure 3-A PCI 703 Interconnections



Connector Pin Assignments

PCI703-16/A

7

8

9

5

6

3

4

Pin

1

2

14

15

16

17

10

11

12

13

Name

FREQ_OUT

GPCTR0

PFI9

DGND

PFI6

PFI5

DGND

+5V

DGND

PFI1

PFI0/TRIG1

DGND

DGND

+5V

DGND

DIO6

DIO1

Pin

18

19

20

21

22

23

24

25

26

31

32

33

34

27

28

29

30

AIGND

ACH4

AIGND

ACH3

ACH10

AIGND

ACH1

ACH8

Name

DGND

DIO4

RESERVED

DAC1

DAC0

ACH15

AIGND

ACH6

ACH13

Pin

35

36

37

38

39

40

41

42

43

48

49

50

51

44

45

46

47

Name

DGND

DGND

Pin

52

53

PFI8/ CPCTR1

PFI7

DGND

GPCTR1

54

55

56

57

PFI4

PFI3/CPCTR0

58

59

PFI2/CONVERT 60

DGND

RESERVED

SCANCLK

DIO3

DIO7

DIO2

DGND

DIO5

65

66

67

68

61

62

63

64

Table 3-1 Pinouts for PCI703-16/A (External Connector – SCSI 68)

The following cables can be used with this connector.

•

Y-Cable 1

•

SCSI D-Sub 68 M/F

PCI703-32/64/A

11

12

13

14

15

16

6

7

4

5

2

3

Pin

1

8

9

10

17

18

19

20

21

22

23

24

25

Name

AIGND

AIGND

ACH0

ACH8

ACH1

ACH9

ACH2

ACH10

ACH3

ACH11

ACH4

ACH12

ACH5

ACH13

ACH6

ACH14

ACH7

ACH15

AISENSE

42

43

44

DAC0OUT 45

DAC1OUT 46

EXTREF

AOGND

47

48

DGND

DIO0

49

50

36

37

38

39

40

41

29

30

31

32

Pin

26

27

28

33

34

35

Name

DIO4

DIO1

DIO5

DIO2

DIO6

DIO3

DIO7

DGND

+5V

+5V

SCANCLK

EXTSTROBE

PFI0/TRIG1

PFI1

PFI2/CONVERT

PFI3/ CPCTR0

PFI4

GPCTR1

PFI5/UPDATE

PFI6/WFTRIG

PFI7/STARTSCAN

PFI8/ CPCTR1

PFI9

GPCTR0

FREQ_OUT

61

62

63

64

65

66

54

55

56

57

Pin

51

52

53

58

59

60

67

68

69

70

71

72

73

74

75

Name

ACH16

ACH24

ACH17

ACH25

ACH18

ACH26

ACH19

ACH27

ACH20

ACH28

ACH21

ACH29

ACH22

ACH30

ACH23

ACH31

ACH32

ACH40

ACH33

ACH41

ACH34

ACH42

ACH35

ACH43

AISENSE

Table 3-2 Pinouts for PCI703-32/64/A (External Connector – SCSI 100)

The following cable can be used with this connector

•

Y-Cable 3

•

SCSI D-Sub 100 M/M

PCI703S-8/16/A

2

3

Pin

1

4

AIGND

ACH14-

ACH14+

Name

ACH12-

Pin

18

19

20

21

Name

ACH0+

DAC0

AOGND

DGND

Pin

35

36

37

38

AIGND

ACH15-

ACH15+

Name

ACH13-

86

87

88

89

90

91

79

80

81

82

Pin

76

77

78

83

84

85

92

93

94

95

96

97

98

99

100

Name

DIO0

DGND

AOGND

AOGND

AIGND

ACH7

ACH14

AIGND

ACH5

ACH12

AISENSE

ACH11

AIGND

ACH2

ACH9

AIGND

ACH0

Pin

52

53

54

55

ACH59

ACH52

ACH60

ACH53

ACH61

ACH54

ACH62

ACH55

ACH63

Name

AIGND

ACH36

ACH44

ACH37

ACH45

ACH38

ACH46

ACH39

ACH47

ACH48

ACH56

ACH49

ACH57

ACH50

ACH58

ACH51

Name

ACH1+

DAC1

AOGND

DGND



9

10

11

12

13

7

8

5

6

14

15

16

17

ACH12+

ACH10-

ACH10+

ACH8-

ACH8+

AIGND

ACH6-

ACH6+

ACH4-

ACH4+

ACH2-

ACH2+

ACH0-

26

27

28

29

30

22

23

24

25

31

32

33

34

FREQ_OUT

GPCTR0

PFI8/ CPCTR1

PFI6

PFI4

PFI2/CONVERT

PFI0/TRIG1

+5V

DGND

DIO6

DIO4

DIO2

DIO0

43

44

45

46

47

39

40

41

42

48

49

50

51

ACH13+

ACH11-

ACH11+

ACH9-

ACH9+

AIGND

ACH7-

ACH7+

ACH5-

ACH5+

ACH3-

ACH3+

ACH1-

Table 3-3 Pinouts for PCI703S-8/16/A (External Connector – SCSI 68)

The following cable can be used with this connector.

•

SCSI D-Sub M/F-S

•

Y-Cable 4

60

61

62

63

64

56

57

58

59

65

66

67

68

NC

GPCTR1

PFI9

PFI7/STARTSCAN

PFI5

PFI3/ CPCTR0

PFI1

+5V

DGND

DIO7

DIO5

DIO3

DIO1

Cable Pin Assignments

Y–Cable 1 (PCI 703-16/A) Analog –DB37 F

Name

AIGND

ACH1

ACH2

AIGND

ACH5

ACH6

AIGND

ACH9

ACH10

AIGND

ACH13

ACH14

AIGND

AIGND

NC

AOGND

AOGND

AOGND

AOGND

8

9

10

11

12

13

14

4

5

6

7

Pin

1

2

3

15

16

17

18

19

Name

ACH0

AIGND

ACH3

ACH4

AIGND

ACH7

ACH8

AIGND

ACH11

ACH12

AIGND

ACH15

AISENSE

NC

NC

EXTREF

DAC0

DAC1

27

28

29

30

31

32

33

23

24

25

26

Pin

20

21

22

34

35

36

37

Table 3-4 Y-Cable 1 Analog Connector



Y-Cable 3 (PCI 703-64/A) Analog

12

13

14

15

16

17

18

19

20

8

9

10

11

4

5

6

7

Pin

1

2

3

Name

AIGND

ACH0

ACH1

ACH2

ACH3

ACH4

ACH5

ACH6

ACH7

ANALOG I/P SENSE

AIGND

ACH16

ACH17

ACH18

ACH19

ACH20

ACH21

ACH22

ACH23

AIGND

32

33

34

35

36

37

38

39

40

28

29

30

31

24

25

26

27

Pin

21

22

23

Name

ACH32

ACH33

ACH34

ACH35

ACH36

ACH37

ACH38

ACH39

AIGND

ACH48

ACH49

ACH50

ACH51

ACH52

ACH53

ACH54

ACH55

AOGND

DAC0

AOGND

Table 3-5 Y-Cable 3 Analog Connector

52

53

54

55

56

57

58

59

60

48

49

50

51

44

45

46

47

Pin

41

42

43

Name

AIGND

ACH8

ACH9

ACH10

ACH11

ACH12

ACH13

ACH14

ACH15

AAIGND

ANALOG I/P SENSE

ACH24

ACH25

ACH26

ACH27

ACH28

ACH29

ACH30

ACH31

AIGND

72

73

74

75

76

77

78

79

80

68

69

70

71

64

65

66

67

Pin

61

62

63

Y–Cable 1, Y -Cable 3, Y -Cable 4 (PCI 703-16/64/S/A) Digital –DB37 F

10

11

12

13

6

7

8

9

Pin

1

2

3

4

5

14

15

16

17

18

19

Name

DGND

DIO1

DIO2

DGND

DIO5

DIO6

DGND

DGND

EXTSTROBE

DGND

DGND

PFI2/CONVERT

DGND

PFI5

DGND

PFI7

DGND

GPCTR0

GND

29

30

31

32

25

26

27

28

Pin

20

21

22

23

24

33

34

35

36

37

Name

DIO0

DGND

DIO3

DIO4

DGND

DIO7

+5V

SCANCLK

PFI0/TRIG1

+5V

PFI1

PFI3

PFI4

PFI6

GPCTR1

PFI8

PFI9

FREQ_OUT

Table 3-6 Y-Cable 1,3,4 Digital Connector

Name

ACH40

ACH41

ACH42

ACH43

ACH44

ACH45

ACH46

ACH47

AIGND

ACH56

ACH57

ACH58

ACH59

ACH60

ACH61

ACH62

ACH63

AOGND

DAC1

EXTREF



Signal Definitions

This sections deal with all the signals abbreviations.

Signal

ACH0-63

AIGND

AOGND

AISENSE

DAC0-1

DIO0-7

PFI0-9

TRIG1

FREQ_OUT

SCANCLK

GPCTR0-1

CPCTR0-1

+5V

DGND

Description

Analog inputs

Analog input ground

Analog output ground

Analog input sensing

Analog outputs

Digital inputs/outputs

Programmable multi function digital inputs/outputs

Digital trigger pin

Frequency generator

A/D external convert

Counter Outputs

Counter Inputs

Power output

Digital ground

Table 3-2 Signal definitions

Pin Descriptions

Analog Input (ACH0-63)

This is the analog input-channels. Depending on the version there are either 16/64 single ended input channels or 8/32 differential input channels.

Analog Input Sensing (AISENSE)

This input is used as a reference analog input ground. This is normally used where the measurement point is very far from the PCI703 connector.

Analog Input Ground (AIGND)

This is the analog reference used by single ended analog inputs.

Analog Output Ground (AOGND)

This is the analog reference used by analog outputs.

Analog Outputs (DAC0 -1)

The A version of the PCI703 has two analog outputs, DAC0 and DAC1.

Digital Input/Outputs (DIO0-7)

The DIO0-7 pins are the pins for the digital I/O system.

Multi Function Digital Input/Outputs (PIO0 -7)

These pins are digital I/O, but can also be used for some other functions. Th ey represent the same function as the digital I/O pins.

TRIG1

This pin is used for digital triggering.

Frequency Output (FREQ_OUT)

This is the output pin of the frequency generator system.

ADC Scan Clock (SCANCLK)

This input is used to externally clock the ADC system.



Counters Output (GPCTR0 -1)

These are the outputs of the two user counters.


Counters External Clock (CPCTR0-1)

These are the external clock inputs of the two user counters.

+5V Power Pin (+5V)

This is a +5 volt fused power pin.

Digital Ground (DGND)

All digital ground signals should be connected to this pin.

Analog Input Connections

WARNING!!

All unused analog inputs must be connected to analog ground. The analog input system of the PCI703 can be damaged or become unstable when scanning channels that is left floating.

Analog Input Connections - SAMPLE-AND-HOLD

WARNING!!

Don’t feed any voltage into the

PCI703S while the computer is switched off. This will damage the analog input cicuitry. The sample -andhold devices will be damaged parmanently and result in multfunctioning of the board.

Differential Input Pairing

The table below shows the differential channel pairing. This is for the PCI703-16/32/64 boards. Please note that if any channel is assigned as a differential input, the paired channel will automatically become unavailable. The positive channel is the channel that needs to be configured.

Channel

Number

5

6

3

4

0

1

2

7

8

9

Positive

Channel

3

4

5

6

0

1

2

7

16

17

Negative

Channel

8

9

10

11

12

13

14

15

24

25

Channel

Number

16

17

18

19

20

21

22

23

24

25

Positive

Channel

32

33

34

35

36

37

38

39

48

49

Negative

Channel

43

44

45

46

40

41

42

47

56

57



10

11

12

13

14

15

18

19

20

21

22

23

26

27

28

29

30

31

26

27

28

29

30

31

50

51

52

53

54

55

Table 3-7 Differential Channel Assignment

58

59

60

61

62

63



4

4. Programming Guide

The PCI703 is supplied with a complete software development kit. EDR Enhanced (EDRE

SDK) comes with drivers for many operating systems and a common application program interface (API). The API also serves as a hardware abstraction layer (HAL) between the control application and the hardware. The EDRE API makes it possible to write an application that can be used on all hardware with common sub-systems.

The PCI703 can also be programmed at register level, but it is not recommended. A detailed knowledge of the PCI703 is needed and some knowledge about programming Plug and Play

PCI devices. We recommend that you only make use of the software provided by Eagle

Technology.

EDR Enhanced API

The EDR Enhanced SDK comes with both ActiveX controls and a Windows DLL API.

Examples are provided in many different languages and serve as tutorials. EDRE is also supplied with a software manual and user’s guide.

The EDRE API hides the complexity of the hardware and makes it really easy to program the

PCI703. It has got functions for each basic sub-system and is real easy to learn.

Figure 4-A EDR Enhanced Design



Digital Inputs/Outputs

The PCI703 has got 8 digital I/O lines and 10 multi I/O lines that can all be used for digital control purposes. The EDRE API supports auto direction configuration. By writing to or reading from a port, it is automatically configured as an output or input. A port is defined as a collection of simultaneous configurable entities. Thus in the case of the PCI703 each port is only 1 -bit wide. In total the PCI703 has got 18 digital ports that can be configured in any direction. Some of which has got more than one function when configured as an input.

Reading the Digital Inputs

A single call is necessary to read a digital I/O port.

API-CALL

Long EDRE_DioRead(ulng Sn, ulng Port, ulng *Value)

The serial number, port, and a pointer to variable to hold the result must be passed by the calling function. A return code will indicate if any errors occurred.

ACTIVEX CALL

Long EDREDioX.Read(long Port)

Only the port-number needs to be passed and the returned value will either hold an error or the value read. If the value is negative an error did occur.

Writing to the Digital Outputs

A single call is necessary to write to a digital I/O port.

API-CALL

Long EDRE_DioWrite(ulng Sn, ulng Port, ulng Value)

The serial number, port, and a value must be passed by the calling function. A return code will indicate if any errors occurred.

ACTIVEX CALL

Long EDREDioX.Write(long Por, ulng Value)

The port number and value to be written needs to be passed and the returned value holds an error or the value read. If the value is negative an error did occur.



Counters

The counter sub-system is supported by functions to Write, Configure and controlling the gate. There are 3 counters and 1 frequency generator. Only the first two counters and the frequency generator are available for the user. See the table below that shows the relation of the counters and their assigned numbers.

Counter

2

3

0

1

Assigned Number

0

1

<Not Used>

2

Description

Counter 0

Counter 1

A/D Timing

Frequency Out Counter

Table 4-1 Counter Assignment

Writing the initial counter value

A single call is necessary to write a counter’s initial load value.

API-CALL

Long EDRE_CTWrite(ulng Sn, ulng Ct, ulng Value)

The serial number, counter-number, and a value must be passed by the calling function. A return code will indicate if any errors occurred.

ACTIVEX CALL

Long EDRECTX.Write(long Port, ulng Value)

The port number and value to be written needs to be passed and the returned value holds an error or the value read. If the value is negative an error did occur.

Configuring a counter

A single call is necessary to configure a counter.

API-CALL

Long EDRE_CTConfig(ulng Sn, ulng Ct, ulng Mode, ulng Type, ulng ClkSrc, ulng

GateSrc)

The serial number, counter-number, mode, type, clock source and gate source is needed to specify a counter’s configuration. A return code will indicate if any errors occurred.

ACTIVEX CALL

Long EDRECTX.Configure(long ct, long mode, long type, ulng source, ulng gate)

The counter-number, mode, type, clock source and gate source is needed to specify a counter’s configuration. A return code will indicate if any errors occurred.

Only the counter mode, clock source and type parameters are used by the PCI703. The table below shows the options for each parameter.

Parameter

Sn

Ct

Mode

Type

Source

Description

Serial Number

Counter Number:

0 : Counter 0

1 : Counter 1

2 : Frequency Out Counter

0 : PULSE

1 : TOGGLE

Invalid parameter for counter 2

Interrupt on TC:

0 : Disabled

1 : Enabled

This bit will only generate a interrupt at the interrupt sub-system. The interrupt sub-system must also be setup to generate a PCI Bus interrupt.

0 : 20MHz internal clock

1 : 100KHz internal clock

2 : External clock on CPCTRx pin<invalid for counter 2>



Gate <not use>

Table 4-2 Counter Configuration


Controlling the counter gate

A single call is necessary to setup/control a counter’s gate. This function call is invalid for the frequency generator (counter 2). Counter 2 does not have a gate.

API-CALL

Long EDRE_CTSoftGate(ulng Sn, ulng Ct, ulng Gate)

The serial number, counter-number and gate are needed to control a counter’s gate. A return code will indicate if any errors occurred.

ACTIVEX CALL

Long EDRECTX.SoftGate(ulng Sn, ulng Ct, ulng Gate)

The counter-number and mode is needed to control a counter’s gate. A return code will indicate if any errors occurred.

These values are acceptable as a gate source.

Value Description

0

1

Gate disabled

Gate enabled

Table 4-3 Gate Configuration



Analog Output

The PCI703-X/A version has got 2 DAC channels that support single write and waveform generation. The DAC subsystem uses the onboard counters for timing and a FIFO for data transfer. The two DAC channels are controlled independently from each other. The DAC subsystem is control via 3 functions: SingleWrite, Control and Configure.

Writing to a DAC channel

A single call is necessary to set a voltage on a DAC channel.

API-CALL

Long EDRE_DAWrite (ulng Sn, ulng Channel, long uVoltage)

The serial number, DAC channel and micro-voltage is needed to set a DAC channel’s voltage. A return code will indicate if any errors occurred.

ACTIVEX CALL

Long EDREDAX.Write (ulng Channel, long uVoltage)

The DAC channel and micro-voltage is needed to set a DAC channel’s voltage. A return code will indicate if any errors occurred.

Generating a Waveform

Generating a waveform is basically a two-step process. First configure a channel then start and stop it. Two modes are available, FIFO non-loop mode and pattern mode. FIFO non-loop the FIFO data only gets outputted once. The DAC output voltage will be the same as the last value in the FIFO. In pattern mode the FIFO data is outputted continuously. Please note that the frequency is not the total frequency of the waveform, but the update rate of the DAC channel. This is the value written directly to the counter.

Update frequency = (Internal clock frequency) / (counter value +1)

API-CALL

Long EDRE_DAConfig (ulng Sn, ulng Channel, ulng Frequency, ulng ClkSrc, ulng

GateSrc, ulng Continuous, ulng Length, long *uVoltage)

Parameter

Sn

Channel

Frequency

ClkSrc

GateSrc

Continuous

Length uVoltage

Return

Type

Unsigned long

Unsigned long

Unsigned long

Unsigned long

Unsigned long

Unsigned long

Unsigned long

Pointer to a long buffer

Long

Description

Board’s serial number

Channel

0: DAC Channel 0

1: DAC Channel 1

Actual value written to counter

Clock source

0: Internal 20 MHz

1: Internal 100 KHz

2: External Clock

Gate Source – Ignored

Mode

0: NON LOOP MODE

1: LOOP MODE

Buffer length

Buffer filled with micro voltages

Error Code

ACTIVEX CALL

Long EDRDAX.Configure (long Channel, long Frequency, long ClkSrc, long GateSrc, long Continuous, long Length, long *uVoltage)

Parameter Type Description



Channel

Frequency

ClkSrc

GateSrc

Continuous

Length uVoltage

Return

Long

Long

Long

Long

Long

Long

Pointer to a long buffer

Long

Channel

0: DAC Channel 0

1: DAC Channel 1

Actual value written to counter

Clock source

0: Internal 20 MHz

1: Internal 100 KHz

2: External Clock

Gate Source – Ignored

Mode

Number of samples in buffer

Buffer filled with micro voltages

Error Code

API-CALL

Long EDRE_DAControl (ulng Sn, ulng Channel, ulng Command)

Parameter

Sn

Channel

Command

Return

Type

Unsigned long

Unsigned long

Unsigned long

Long

Description


Channel

0: DAC Channel 0

1: DAC Channel 1

Command Code

0: NULL

1: Start process

2: Stop process

3: Pause process

4: Continue process

Error Code

ACTIVEX CALL

Long EDREDAX.Control (long Channel, long Command)

Parameter

Channel

Command

Return

Long

Long

Long

Type Description

Channel

0: DAC Channel 0

1: DAC Channel 1

Command Code

0: NULL

1: Start process

2: Stop process

3: Pause process

4: Continue process

Error Code



Analog Input

The PCI703 has got a very unique A/D subsystem and is fully configurable. Configuration includes dynamic range, gain, reference and differential or single ended. Each of these settings can be applied to an individual channel while scanning.

Please not that although the PCI703 and PCI703S is similar in operation and uses the same functions, not all parameters apply to the PCI703S. This is because the PCI703S only supports bipolar-differential mode. The frequency is also implemented differently. Where the frequency is the timer tic for the ADC on the PCI703, it is the total frequency on the PCI703S.

Reading a single voltage from a channel

To read a single ADC channel you need to know the voltage range and gain.

API-CALL

Long EDRE_ADSingle (ulng Sn, ulng Channel, ulng Gain, ulng Range, plong uVoltage)

Parameter

Sn

Channel

Gain

Range uVoltage

Return

Type

Unsigned long

Unsigned long

Unsigned long

Unsigned long

Pointer to a long

Long

Description


ADC Channel

Gain code. See appendix for details

Range code. See appendix for details

Voltage read from channel

Error Code

ACTIVEX CALL

Long EDREADX.SingleRead (long Channel)

Parameter

Channel

Return

Long

Long


ADC Channel

Voltage returned from channel.

Make sure to set the Gain and Range properties of the ADC ActiveX control. This will in turn set the range and gain when reading the ADC channel.

Configuring the ADC subsystem for scanning

This is the most complicated part of configuring the PCI703 for auto scanning. Make sure that you use the correct format when applying the channel list configuration. There are many loopholes and care should be taken when implementing code to configure the PCI703.

API-CALL

Long EDRE_ADConfig (ulng Sn, pulng Freq, ulng ClkSrc, ulng Burst, ulng Range, pulng ChanList, pulng GainList, ulng ListSize)

The following parameters must be specified when configuring the ADC sub-system.

Parameter

Sn

Freq

ClkSrc


Unsigned long Board’s serial number.

Pointer to an Sampling frequency. The actual sampling frequency will be returned with this parameter. unsigned long

Unsigned long This parameter is used to configure the clocking system of the ADC.

Format

Offset (bits) Description

0 Clock Source (C0-C7)

0: Undefined

8

1: Internal

2: External – PIN PFI2/CONVERT

Trigger Source (T0-T3)

0: Internal

1: Reference – DAC CHAN 1 (NOT SUPPORTED BY PCI 703S)

2: External – PIN TRIG1



Burst

Range

ChanList

GainList

ListSize


12 Trigger Mode – Only applies to the reference trigger source. (M0-M3)

0: Positive

1: Negative

2: Rising

3: Falling

Example Layout:

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

M

3

M

2

M

1

M

0

T3 T2 T1 T0 C

7

C

6

C

5

C

4

C

3

C

2

C

1

C

0

Unsigned long Not used

Unsigned long Not used

Pointer to an unsigned long


This is an array of unsigned longs which contains the channels to be sampled when scanning the ADC sub-system. The max size of the channel list is half the FIFO depth.

The gain list contains an array of unsigned longs which sp ecifies the setup for each channel according to the previous list. The table below shows the format for each channel.


0

8

12

Specifies the gain of the channel. See table on ADC gain codes. (G)

Specifies the range of the channel. See table on ADC range codes. (R)

Specifies the analog reference.

0: analog in sense pin.

1: analog ground. (F)

Example Layout:

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

F3 F2 F1 F0 R R R R G G G G G G G

3 2 1 0 7 6 5 4 3 2 1

Unsigned long This parameter determines the length the two previous arrays. This is also the depth of the channel list that is programmed to the board.

G

0

Digital triggering

If digital triggering is used, pin TRIG1 is used. This pin is active high and will start the ADC process when it is high. The process will continue until it is stopped via software.

Analog triggering

If analog triggering is used, the voltage on analog output channel 1 is used as reference voltage. This voltage can be changed at set and the PCI703 will compare the current input voltage to the ADC system, this can be from any channel included in the channel list, with the voltage of DAC channel 1. The trigger event can be any of the four settings.

ACTIVEX CALL

Long EDREADX.Configure (plong Channels, plong Gains, long ListSize)

Parameter Type Description

Channels

Gains

Pointer to a long

Pointer to a long

This is an array of longs that contains the channels to be sampled when scanning the ADC sub-system.

The max size of the channel list is half the FIFO depth.

The gain list contains an array of longs that specifies the setup for each channel according to the previous list. The table below shows the format for each channel.


0

8

Specifies the gain of the channel. See table on ADC gain codes. (G)

Specifies the range of the channel. See table on ADC range codes. (R)

12 Specifies the analog reference.

0: analog in sense pin.

1: analog ground. (F)

Example Layout:

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0



ListSize

F3 F2 F1 F0 R

3

R

2

R

1

R

0

G

7

G

6

G

5

G

4

G

3

G

2

G

1

Unsigned long This parameter determines the length the two previous arrays. This is also the depth of the channel list that is programmed to the board.

G

0

The range code does not apply to the S models, for the are always differenti al and bipolar.

The Frequency and ClockSource ADC ActiveX control must be setup before calling the configure function.

EDREADX.Frequency

Frequency The ADC sampling frequency

WARNING!!

î On the PCI703 the frequency is the update rate of the A/D converter. This means that the board will convert the channels at a period of equal to the frequency and the channels in the sequence of the channel list. The end result is that the time between samples is equal to 1/Frequency.

î The PCI703S -frequency relates to th e total sampling frequency. The effective sampling frequency is the frequency divided by the channel list length. The channel-list holds all the channels that need to be simultaneous -sampled-andholded. Thus the all channel in a set are sampled at the same time but the space between a set is the total sampling frequency divided by the channel list length. Also note that the sample-andhold counts as one channel. This reduces the maximum frequency by one count plus the channel list length. For example the max for one channel is 200KHz.

Frequency Example:

Frequency = 200 000 Hz

PCI703

Channel List Length = 10

Time = 5 uS

Time between channels = 5 uS

PCI703S

Frequency = 200 000 Hz

Channel List Length = 10

Effective Frequency = 20 000 Hz

Time = 50 uS

Time between channels = 0 uS

Time between sets = 50 uS



EDREADX.ClockSource

ClockSource This parameter is used to configure the clocking system of the ADC.

Format


0 Clock Source (C0-C7)

8

12

0: Undefined

1: Internal

2: External

Trigger Source (T0-T3)

0: Internal

1: Reference (NOT SUPPORTED BY PCI 703S)

2: External

Trigger Mode – Only applies to the reference trigger source. (M0-M3)

0: Positive

1: Negative

2: Rising

3: Falling

Example Layout:

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

M

3

M

2

M

1

M

0

T3 T2 T1 T0 C

7

C

6

C

5

C

4

C

3

C

2

C

1

C

0

Starting and Stopping the ADC process

A single call is necessary to start or stop the ADC process

API-CALL

Long EDRE_ADStart (ulng Sn)

Parameter

Sn

Return

Type

Unsigned long

Long

Description


Error Code

ACTIVEX CALL

Long EDREADX.Start ()

Parameter

Return Long

Type

API-CALL

Long EDRE_ADStop (ulng Sn)

Parameter

Sn

Return

Type

Unsigned long

Long

ACTIVEX CALL

Long EDREADX.Stop ()

Parameter

Return Long

Type

Description

Error Code

Description


Error Code

Description

Error Code

Getting data from the driver buffer

A single call is necessary copy data from the driver buffer to the user buffer.

API-CALL

Long EDRE_ADGetData (ulng Sn, plong Buf, pulng BufSize)



Parameter

Sn

Buf

BufSize

Return

Type

Unsigned long

Pointer to a long buffer.


Long

Description


Buffer to copy micro voltages too.

Size of buffer must be passed or number of samples requested. The returned value will indicate the number of actual samples copied to the buffer.

Error Code

ACTIVEX CALL

Long EDREADX.GetData (plong Buffer, plong Size)

Parameter

Buf

BufSize

Return

Type

Pointer to a long buffer.

Pointer to a long

Long

Description

Buffer to copy micro voltages too.

Size of buffer must be passed or number of samples requested. The returned value will indicate the number of actual samples copied to the buffer.

Error Code

Querying the ADC subsystem

The driver can be queried to check the status of the ADC subsystem. The number of unread samples is one example.

API-CALL

Long EDRE_Query (ulng Sn, ulng QueryCode, ulng Param)

Parameter

Sn

QueryCode

Param

Return

Type

Unsigned long

Unsigned long

Unsigned long

Long

Description


Query code. See appendix

Example:

ADUNREAD: This will tell you the number of available samples.

ADBUSY: Is the ADC subsystem busy?

Extra parameter.

Returned query code

ACTIVEX CALL

Long EDREADX.GetUnread ()

Parameter

Return Long


Number of samples available in the driver.

This function automatically queries the ADC driver buffer for the number of available samples.



Query Codes

This chapter explains query codes and their functions relating to the PCI703 series. It will show examples of typical query codes that can make custom application allot easier to develop and tailor made for the PCI703 boards. Please note that all examples or pseudo code will show the API call and not the ActiveX call. Use the section below to translate between the two different implementations.

How to use query codes

The appendix shows a list of query code that can be used. The function prototypes below show how to implement a query code for both the EDR Enhanced API and Utility ActiveX control.

API Call

Long EDRE_Query (ulng Sn, ulng QueryCode, ulng Param)

Parameter

Sn

QueryCode

Param

Return

Type

Unsigned long

Unsigned long

Unsigned long

Long

Description



Example:

ADUNREAD: This will tell you the number of available samples.

ADBUSY: Is the ADC subsystem busy?

Extra parameter.

Returned query code

ActiveX Call

Long EDREUTLX.Query (long Code, long Param)

Parameter

Code

Param

Return

Type

Unsigned long

Unsigned long

Long

Description


Extra parameter.

Returned query code

The above functions are used to execute query codes that can do a variety of functions. The returned value will have the result of the query code. The query function can also execute functions or changes settings of the driver system.

How to change the hardware FIFO depth

The hardware FIFO depth can be set with a single query call. This also relates to the interrupt depth and data update rate. If sampling at maximum speed set this depth to max and for slower speeds, under a 1000 Hz to a lower level.

PSEUDO BEGIN

UI32 Sn=1000000001 /*32-bit unsigned integer - Serial Number*/

UI32 Depth=1000 /*32-bit unsigned integer - FIFO Depth, Max is 4095*/

I32 Status /*32-bit integer*/

Status=EDRE_Query(Sn, ADIRQLEVEL /*Code 142*/,Depth)

If Status < 0 Then Error

PSEUDO END



How to check for available data

To check for the number of samples available in the driver buffer use the query functions as below.

PSEUDO BEGIN



Status=EDRE_Query(Sn, ADUNREAD /*Code 109*/,0)


Print “Samples available = “ + Status

PSEUDO END

How to get the driver buffer size

To get the driver buffer size, use the query below.

PSEUDO BEGIN



Status=EDRE_Query(Sn, ADBUFFSIZE/*Code 106*/,0)


Print “Driver buffer size = “ + Status

PSEUDO END

How to get the number of ADC channels

To check for the number of ADC channels

PSEUDO BEGIN



Status=EDRE_Query(Sn, ADNUMCHAN /*Code 100*/,0)


Print “Channels available = “ + Status

PSEUDO END

How to check the status of the driver buffer

The driver buffer can be queried to check if a overrun condition occured.

PSEUDO BEGIN



Status=EDRE_Query(Sn, ADBUFFOVER/*Code 107*/,0)

If Status = 0 Then Print “Buffer OK”

Else Print ”Buffer Error”

PSEUDO END



5

5. Calibration

Calibrating the PCI703 is simple task. EDR Enhanced must be installed and the calibration software. Both can be found on the Eagle Technology Software CD-Rom

(<EAGLECD>\EDRE\APPS\PCI700CAL\PCI700CALIBRATIONSOFTWARE.EXE). The latest version will also be available on http://www.eagle.co.za

.

Requirements

1. 1 x PCI703 with cable and adaptor.

2. Installed software

3. High accuracy calibration source,

4. High accuracy digital voltmeter.



A

A.Specifications

Maximum Transfer Bandwidth – PCI703/S

The ADC and DAC subsystems share a common data path to the FIFO module. This limits the maximum data transfer between the FIFO’s, the appropriate device and across PCI. The maximum bandwidth is 450 000 cycles per second.

Analog Input Characteristics – PCI703

Input Characteristics

Input Signal Ranges

Input Coupling

Maximum Working Voltage

Over Voltage Protection

FIFO Buffer Size

Channel List Buffer Size

Data Transfer

Channel

Gain

Unipolar

Range

Bipolar

Range

0.25

0.50

1.00

2.50

5.00

10.00

25.00

50.00

100.00

0-10V

0-10V

0-5V

0-2V

0-1V

0-500mV

0-200mV

0-100mV

0-50mV

± 10V

± 5V

± 2.5V

± 1V

± 500 mV

± 250 mV

± 100 mV

± 50 mV

± 25 mV

DC

±

11V relative to analog ground

±

25V when power is on, relative to analog ground

±

35V when power is off, relative to analog ground

4096

Maximum 2048

Programmed I/O, Interrupts, BM DMA

Conversion Characteristics

Maximum Sampling Rate

Resolution

Relative Accuracy

Offset Error (Gain = 1)



Gain Error

400 000 samples per second (S/s)

14 bits

±

1 LSB max

±

0.4 mV max

±

0.6 mV max

±

0.1 mV max

±

0.02% of max reading

Differential Input Amplifier Characteristics (AD620BR)

Input Impedance

Bandwidth

Settling Time

System Noise

10 G

Ω

, in parallel with 100 pF maximum

600 KHz

5 uS to 2 LSB

15 uS to 1 LSB

Gains < 5, 0.6 LSB (rms)



Maximum Safe Input Range

Maximum Operating Input Range

Gains > 5, 0.8 LSB (rms)

±

15V

±

5V

Analog Input Characteristics – PCI703S

Differential Input Amplifier Characteristics (AD620BR)

Input Coupling

Input Impedance

Bandwidth

Offset Voltage

Gain Error

Maximum Safe Input Range

Maximum Operating Input Range

DC

>1 G

Ω

, in parallel with 50 pF maximum

120 KHz at

±

5V input voltage swing

±

500 uV

±

0.002% (Gain=1)

±

15V

±

5V

Sample and Hold Amplifier Characteristics (AD684)

Bandwidth

Hold Mode Offset Voltage

Gain Error

1 MHz at

±


±

3 mV

±

0.05%

Programmable Gain Amplifier Characteristics

Bandwidth

Offset Voltage

Gain Error

600 KHz at

±


±

200 uV

±

0.008%

Input Characteristics

Input Signal Ranges

Input Coupling

Maximum Working Voltage

Over Voltage Protection


Channel List Buffer Size

Data Transfer

Channel Gain

0.50

1.00

2.50

5.00

10.00

25.00

50.00

Bipolar Range

± 5V

± 2.5V

± 1V

± 500 mV

± 250 mV

± 100 mV

± 50 mV

± 25 mV

DC

100.00

±

10V relative to analog ground

±

25V when power is on, relative to analog ground

±

35V when power is off, relative to analog ground

4096

Maximum 2048


Conversion Characteristics

Maximum Sampling Rate

Resolution





Gain Error

400 000 samples per second (S/s)

14 bits

±

1 LSB max

±

0.4 mV max

±

0.6 mV max

±

0.1 mV max

±

0.02% of max reading



Analog Output Characteristics

Output Characteristics

Resolution

Maximum Update Rate


Data Transfer

14 bits

400 KHz to 0.02% full scale

4096


Conversion Characteristics (Calibrated)

Resolution


Full Scale Error

Zero Scale Error

14 bits

±

1.0 LSB max

±

0.9 LSB

±

0.9 LSB

Voltage Output Characteristics

Range

Output Settling Time

Output Impedance

Output Drive

Power-on State

±

10 Volt

2.5 us to 0.02% full scale

0.2

Ω

±

5 mA

0V

Digital Input/Output Characteristics

Number of Channels

Compatibility

I/O Characteristics

8 independent programmable

TTL

Level

Input Low Voltage

Input High Voltage

Low Level Input

Current

High Level Input

Current

Output High

Voltage

Output Low

Voltage

Low Level Output

Current

High Level Output

Current

Min

0V

2.0V

2.4V

Max

0.8V

5.25V

- 100 uA

100 uA

0.6V

-24 mA

4 mA

Multifunction Input/Output Characteristics


Compatibility


10 independent programmable

TTL

Level

Input Low Voltage

Input High Voltage

Low Level Input

Current

High Level Input

Current

Output High

Voltage

Output Low

Voltage

Low Level Output

Current

High Level Output

Current

Min

0V

2.0V

2.4V

Max

0.8V

5.25V

- 100 uA

100 uA

0.6V

-24 mA

4 mA



Timing Input/Output Characteristics


Resolution

Clock Source


2

24 bits

20 MHz, 100 KHz, External

Level

Input Low Voltage

Input High Voltage

Low Level Input

Min

0V

2.0V

Current

High Level Input

Current

Output High

Voltage

Output Low

Voltage

Low Level Output

Current

High Level Output

Current

2.4V

Other

Bus Interface

Power Requirements

PCI 2.2 Compatible

Master & Slave

3.3V or 5V

+5V (

±

5%) @ 1.3 A

Max

0.8V

5.25V

- 100 uA

100 uA

0.6V

-24 mA

4 mA



B

B.Configuration Constants

Query Codes

Please see the file <EAGLECD>\EDRE\INCLUDE\QUERY.H for the latest query codes.

Error Codes

Please see the file <EAGLECD>\EDRE\INCLUDE\ERRORS.H for the latest error codes.

Digital I/O Codes

Name

DIOOUT

DIOIN

DIOINOROUT

DIOINANDOUT

0

1

2

3

Value Description

Port is an output.

Port is an input.

Port can be configured as in or out.

Port is an input and an output.

Analog Input Gain Codes – PCI703-16/32/64/A

GAIN 0.25

GAIN 0.50

GAIN 1.00

GAIN 2.50

GAIN 5.00

GAIN 10.0

GAIN 25.0

GAIN 50.0

Name

0

1

2

3

4

5

6

7

Value

Gain of ¼ ( ± 10V, NU)

Gain of ½ ( ± 5V, 0-10V)

Gain of 1 ( ± 2.5V, 0-5V)

Gain of 2.5 (

±

1V, 0-2V)

Gain 0f 5 ( ± 500mV, 0-1V)

Gain of 10 ( ± 250mV, 0-500mV)

Gain of 25 ( ± 100mV, 0-200mV)

Gain of 50 ( ± 50mV, 0-100mV)

Description

Analog Input Gain Codes – PCI703S-8/16/A

Name

GAIN 0.50

GAIN 1.00

GAIN 2.50

GAIN 5.00

GAIN 10.0

GAIN 25.0

GAIN 50.0

GAIN 100.0

Value

0

1

2

3

4

5

6

7

Description

Gain of ½ ( ± 5V)

Gain of 1 ( ± 2.5V)

Gain of 2.5 ( ± 1V)

Gain 0f 5 ( ± 500mV)

Gain of 10 ( ± 250mV)

Gain of 25 ( ± 100mV,)

Gain of 50 ( ± 50mV)

Gain of 100 ( ± 25mV,)

Analog Input Range Codes – PCI703-16/32/64/A

*The range code does no apply to the S-models for they are always in differential bipolar mode.



Name

UNIPOLAR, SINGLE ENDED

BIPOLAR, SINGLE ENDED

UNIPOLAR, DIFFERENTIAL

BIPOLAR, DIFFERENTIAL

Value

0

1

2

3


Description

Channel is single ended unipolar input.

Channel is single ended bipolar input.

Channel is differential unipolar input.

Channel is differential bipolar input.



C

C.Layout Diagram




D

D.Ordering Information

For ordering information please contact Eagle Technology directly or visit our website www.eagle.co.za

. They can also be emailed at [email protected]

.

PCI 703-16

PCI 703-16A

PCI 703-32

PCI 703-32A

PCI 703-64

PCI 703-64A

PCI 703S-8

PCI 703S-8A

PCI 703S-16

PCI 703S-16A

Board Description

16 Channel analog input board

16 Channel analog input and 2 channel analog output board





16 Channel sample-and-hold analog input board

16 Channel sample-and-hold analog input board and 2 channel analog output board

16 Channel sample-and-hold analog input board

16 Channel sample-and-hold analog input board and 2 channel analog output board

Table D-D-1 Ordering Information

Please visit our website to have a look at our wide variety of data acquisition products and accessories.


User's manual | Eagle Technology PCI703-16/A User`s manual

PCI 703 Series

PCI PnP Analog Board

User’s Manual

Eagle Technology – Cape Town, South Africa

Copyright © 2001-2004

www.eagledaq.com

Analog Boards

Data Acquisition and Process Control

© Eagle Technology

31-35 Hout Street

Cape Town

South Africa

Phone +27 21 423 4943

Fax +27 21 424 4637

Email [email protected]

TABLE OF CONTENTS

Table of Figures

Table of Tables

1. Introduction

Features

Applications

Key Specifications

Software Support

Contact Details

2. Installation

Package

Operating System Support

Hardware Installation

Failure to disconnect all power cables can result in hazardous conditions, as there may be dangerous voltage levels present in externally connected cables.

Software Installation

The PCI703/16/64 use the same driver.

However the PCI703S has a different driver. Please sure that you use the appropriate driver for your board.

Accessories

3. Interconnections

External Connectors

Connector Pin Assignments

Cable Pin Assignments

Signal Definitions

Pin Descriptions

Analog Input Connections

All unused analog inputs must be connected to analog ground. The analog input system of the PCI703 can be damaged or become unstable when scanning channels that is left floating.

Analog Input Connections - SAMPLE-AND-HOLD

Don’t feed any voltage into the

PCI703S while the computer is switched off. This will damage the analog input cicuitry. The sample -andhold devices will be damaged parmanently and result in multfunctioning of the board.

Differential Input Pairing

4. Programming Guide

EDR Enhanced API

Digital Inputs/Outputs

Counters

Analog Output

Analog Input

Query Codes

5. Calibration

Requirements

A.Specifications

Maximum Transfer Bandwidth – PCI703/S

Analog Input Characteristics – PCI703

Analog Input Characteristics – PCI703S

Analog Output Characteristics

Digital Input/Output Characteristics

Multifunction Input/Output Characteristics

Timing Input/Output Characteristics

Other

B.Configuration Constants

Query Codes

Error Codes

Digital I/O Codes

Analog Input Gain Codes – PCI703-16/32/64/A

Analog Input Gain Codes – PCI703S-8/16/A

Analog Input Range Codes – PCI703-16/32/64/A

C.Layout Diagram

D.Ordering Information

Table of contents