Datasheet for Ic-ttl Shift Register

Datasheet for Ic-ttl Shift Register
NTE74164
Integrated Circuit
TTL − 8−Bit Parallel−Out Serial Shift Register
Description:
The NTE74164 is an 8−bit parallel−out serial shift register in a 14−Lead plastic DIP type package that
features gated serial inputs and asynchronous clear. The gated serial inputs (A and B) permit complete
control over incoming data as a low at either input inhibits entry of the new data and resets the first flip−flop
to the low level at the next clock pulse. A high−level input enables the other input which will then determine
th state of the first flip−flop. Data at the serial inputs may be changed while the clock is high or low, but
only information meeting the setup−time requirements will be entered. Clocking occurs on the low−to−
high−level transition of the clock input. All inputs are diode−clamped to minimize transmission−line effects.
Features:
D Gated Serial Inputs
D Fully Buffered Clock and Serial Inputs
D Asynchronous Clear
Absolute Maximum Ratings: (Note 1)
Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7V
DC Input Voltage, VIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5V
Power Dissipation (per Bit), PD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21mW
Operating Temperature Range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0C to +70C
Storage Temperature Range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65C to +150C
Note 1. Unless otherwise specified, all voltages are referenced to GND.
Recommended Operating Conditions:
Parameter
Symbol
Min
Typ
Max
Unit
Supply Voltage
VCC
4.75
5.0
5.25
V
High−Level Output Current
IOH
−
−
−400
A
Low−Level Output Current
IOL
−
−
8
mA
fclock
0
−
25
MHz
Width of Clock or Clear Input Pulse
tw
20
−
−
ns
Data Setup Time
tsu
15
−
−
ns
Data Hold Time
th
5
−
−
ns
Operating Temperature Range
TA
0
−
+70
C
Clock Frequency
Electrical Characteristics: (Note 2, Note 3)
Parameter
Symbol
Test Conditions
Min
Typ
Max
Unit
High Level Input Voltage
VIH
2
−
−
V
Low Level Input Voltage
VIL
−
−
0.8
V
Input Clamp Voltage
VIK
VCC = MIN, II = −12mA
−
−
−1.5
V
High Level Output Voltage
VOH
VCC = MIN, VIH = 2V, VIL = 0.8V, IOH = −400A
2.4
3.4
−
V
Low Level Output Voltage
VOL
VCC = MIN, VIH = 2V, VIL = 0.8V, IOL = 8mA
−
0.2
0.4
V
Input Current
II
VCC = MAX, VI = 5.5V
−
−
1
mA
High Level Input Current
IIH
VCC = MAX, VI = 2.4V
−
−
40
A
Low Level Input Current
IIL
VCC = MAX, VI = 0.4V
−
−
−1.6
mA
Short−Circuit Output Current
IOS
VCC = MAX, Note 4
−9
−
−27.5
mA
Supply Current
ICC
VCC = MAX, VI(clock) = 0.4V, Note 5
−
30
−
mA
VCC = MAX, VI(clock) = 2.4V, Note 5
−
37
54
mA
Note 2. .For conditions shown as MIN or MAX, use the appropriate value specified under “Recommended
Operation Conditions”.
Note 3. All typical values are at VCC = 5V, TA = +25C.
Note 4. Not more than one output should be shorted at a time.
Note 5. ICC is measured with outputs open, serial inputs grounded, and a momentary GND, then
4.5V, applied to clear.
Switching Characteristics: (VCC = 5V, TA = +25C unless otherwise specified)
Parameter
Symbol
Maximum Clock Frequency
fmax
Propagation Delay Time
(High−to−Low−Level Q Outputs from Clear Input)
tPHL
Propagation Delay Time
(Low−to−High−Level Q Outputs from Clock Input)
tPLH
Propagation Delay Time
(High−to−Low−Level Q Outputs from Clock Input)
tPHL
Test Conditions
RL = 800
Min
Typ
Max
Unit
CL = 15pF
25
36
−
MHz
CL = 15pF
−
24
36
ns
CL = 50pF
−
28
42
ns
CL = 15pF
8
17
27
ns
CL = 50pF
10
20
30
ns
CL = 15pF
10
21
32
ns
CL = 50pF
10
25
37
ns
Function Table:
Inputs
Outputs
Clear
Clock
A
B
QA
QB
...
QH
L
X
X
X
L
L
L
H
L
X
X
QA0
QB0
QH0
H

H
H
H
QAn
QGn
H

L
X
L
QAn
QGn
H

X
L
L
QAn
QGn
H = HIGH Level (Steady State)
L = LOW Level (Steady State)
X = Irrelevant (Any Input, including Transitions)
 = Transition from LOW to HIGH Level
QA0, QB0, QH0 = The level of QA, QB, or QH, respectively, before the indicated steady−
state input conditions were established.
QAn, QGn = The level of QA or QG before the most recent  transition of the clock; indicates
a one−bit shift.
Pin Connection Diagram
A 1
14 VCC
B 2
QA 3
13 QH
12 QG
QB 4
11 QF
QC 5
10 QE
QD 6
9 CLR
GND 7
8 CLK
14
8
1
7
.300 (7.62)
.785 (19.95) Max
.200
(5.08)
Max
.100 (2.45)
.600 (15.24)
.099 (2.5) Min
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