MATLAB EMBEDDED IDE LINK 4 - FOR USE WITH ANALOG DEVICES VISUALDSP PLUSPLUS User manual

MATLAB EMBEDDED IDE LINK 4 - FOR USE WITH ANALOG DEVICES VISUALDSP PLUSPLUS User manual
DSP Selection Guide
2002 Edition
• Introduction to ADI DSPs
• Processor Selection Guides
• DSP Development Tools
• Support Resources
• Benchmarks
• Training Workshops
www.analog.com/dsp
DSP SOLUTIONS THAT MAKE YOUR
DESIGN CHALLANGE EASIER
Contents
Introduction to ADI DSPs and Key Product Guides
16-Bit DSP and Blackfin DSP Key Products
SHARC DSP Key Products
Mixed Signal DSP Key Products
Embedded DSP-Based Control Key Products
ADI DSP Overview
Markets and Applications
Key Benefits
Customer Support
2
3
4
5
6
7
8
9
DSP Development Tools
VisualDSP++ Integrated Development Environment
16-Bit DSP and Blackfin DSP Tools
SHARC and TigerSHARC DSP Tools
10
14
15
ADI’s Third Party Network – The DSP Collaborative
16
SPA DSP Software Algorithms
18
Benchmarks
Comparing DSPs
16-Bit DSP and Blackfin DSP Families
SHARC DSP Family
21
23
24
DSP Part Numbering System
25
16-bit DSP Competitor Cross Reference Guide
34
Products and Selection Guides
Blackfin DSP Family
ADSP-21535
ADSP-21532
ADSP-21xx Family
ADSP-219x
ADSP-218x
SHARC DSP Family
ADSP-TS101
ADSP-21161N
ADSP-21160
ADSP-21065L
ADSP-2199x Family
ADSP-21990
ADMC Embedded Control Family
ADMCF34x/ADMC34x
ADMC401
Quad-SHARCs
AD14060/AD14160
Software and Systems Technologies (SST)
SST-Melody-32
SST-Melody-SU
SST-NAV-GPS
dspConverters
AD73411
AD73422
AD73460
University Program
Literature Selection Guide
Technical Training Workshops
ADI DSP-Power Management Guide
26
28
29
30
32
33
35
36
37
38
40
41
42
43
44
45
46
46
48
48
49
50
51
52
53
54
55
56
58
59
16-Bit DSP Key Products
Recommended for New Designs
Max
Blackfin DSP Package MMACs
TM
Program and
Data Memory
Words
Vcc
154K
ADSP-21535P
B
600
1.5V
ADSP-21532S
CA
600
2.25-3.6V**
Status
Samples Now
Release July 2002
Samples Summer 2002
Release 1Q03
58K***
Price*
$32.00
$11.50
Vcc
Program
Memory
Words
ADSP-2191M
ADSP-2195M
ADSP-2196M
ST,CA
ST,CA
ST,CA
160
160
160
2.5V
2.5V
2.5V
32K
32K***
24K***
32K
16K
8K
Released
Released
Released
Price*
$16.85
$13.90
$11.10
ADSP-2188N
ADSP-2189N
ADSP-2187N
ADSP-2185N
ADSP-2186N
ADSP-2184N
ST,CA
ST,CA
ST,CA
ST,CA
ST,CA
ST,CA
80
80
80
80
80
80
1.8V
1.8V
1.8V
1.8V
1.8V
1.8V
48K
32K
32K
16K
8K
4K
56K
48K
32K
16K
8K
4K
Released
Released
Released
Released
Released
Released
$26.00
$21.00
$17.00
$9.50
$7.25
$5.75
ADSP-2188M
ADSP-2189M
ADSP-2185M
ADSP-2186M
ST,CA
ST,CA
ST,CA
ST,CA
75
75
75
75
2.5V
2.5V
2.5V
2.5V
48K
32K
16K
8K
56K
48K
16K
8K
Released
Released
Released
Released
$28.00
$23.00
$10.00
$7.50
ADSP-21xx
DSP
Package
Max
MMACs
Data
Memory
Words
Status
Packages: ST = Thin Quad Flat Pack (LQFP)
CA = Mini Ball Grid Array
B = Plastic Ball Grid Array
* US Dollars. Lowest grade suggested resale price per unit in 1000 unit quantities
All pricing is budgetary – subject to change
** External voltage range – core voltage regulation on-chip
*** Includes 16K words ROM
Blackfin DSP
Development Tools ADSP-218x M/N
ADSP-219x
Evaluation Development ADDS-2189M-EZLITE $295
Platform
ADDS-2191-EZLITE $295 ADDS-21535-EZLITE $295
Emulator
VisualDSP++
Development Software
ADDS-218X-ICE-2.5V $1995
ADDS-APEX-ICE
$4995
ADDS-SUMMIT-ICE $4995
VDSP-21XX-PC-FULL $3500
VDSP-21XX-PCFLOAT $4250
VDSP-BLKFN-PC-FULL
$3500
VDSP-BLKFN-PCFLOAT
$4250
Note: DSP tools pricing is US dollars and subject to change at anytime. Volume discounts are available for VisualDSP++.
Please contact your local ADI sales representative or distributor for more information.
2
DSP Selection Guide
http://www.analog.com/dsp
SHARC® and TigerSHARC® DSP Key Products
Recommended for New Designs
1600
TigerSHARC ADSP-TS101S
250 MHz
1500 MFLOPS
2 Billion 16-Bit MACs
MFLOPS
1400
800
ADSP-21161N
600
ADSP-21160N
SIMD SHARC
ADSP-21160M
400
100 MHz SHARC Core
SIMD Doubles Cycle Performance
200
ADSP-21065L SISD SHARC
60 MHz SHARC Core
1999
2000
2001
2002
Package
Max
MFLOPS
Vcc
On-Chip
SRAM
ADSP-21161N
ADSP-21160M
CA
B
600
480
1.8/3.3V
2.5/3.3V
1 Mbits
4 Mbits
ADSP-21160N
ADSP-21065L
B
S, CA
570
198
1.9/3.3V
3.3V
4 Mbits
544 Kbits
ADSP-TS101S
B
1500
1.2/3.3V
6 Mbits
32-Bit
Generic
2003+
Status
Samples Now
Release 2Q02
Released
Samples Now
Release 3Q02
Released
Samples Now
Release 4Q02
Price*
$24.63
$145.00
$145.00
$19.50
$207.00
Packages: B = Plastic Ball Grid Array (PBGA)
S = Plastic Quad Flat Pack (PQFP)
CA = Mini Ball Grid Array
* US Dollars. Lowest grade suggested resale price per unit in 1000 unit quantities
All pricing is budgetary – subject to change
Processor
ADSP-21161N
ADSP-21160M
ADSP-21160N
ADSP-21065L
ADSP-TS101S
Evaluation
Development Platform
Development
Software
Emulator
ADDS-21161N-EZLITE $495 ADDS-APEX-ICE
ADDS-SUMMIT-ICE
ADDS-21160-EZLITE $595 ADDS-APEX-ICE
(Available 2Q02)
ADDS-SUMMIT-ICE
ADDS-21160N-EZLITE $650 ADDS-APEX-ICE
(Available 3Q02)
ADDS-SUMMIT-ICE
ADDS-21065L-EZLITE $299 ADDS-APEX-ICE
ADDS-SUMMIT-ICE
ADDS-TS101S-EZLITE $995 ADDS-APEX-ICE
ADDS-SUMMIT-ICE
$4995
$4995
$4995
$4995
$4995
$4995
$4995
$4995
$4995
$4995
VDSP-SHARC-PC-FULL
VDSP-SHARC-PCFLOAT
VDSP-SHARC-PC-FULL
VDSP-SHARC-PCFLOAT
VDSP-SHARC-PC-FULL
VDSP-SHARC-PCFLOAT
VDSP-SHARC-PC-FULL
VDSP-SHARC-PCFLOAT
VDSP-TS-PC-FULL
VDSP-TS-PCFLOAT
$3500
$4250
$3500
$4250
$3500
$4250
$3500
$4250
$3500
$4250
Note: DSP tools pricing is US dollars and subject to change at anytime. Volume discounts are available for VisualDSP++.
Please contact your local ADI sales representative or distributor for more information.
http://www.analog.com/dsp
DSP Selection Guide
3
Mixed Signal DSP Key Products
Recommended for New Designs
Performance and Functionality
ADSP-2199x Family
ADSP-2199x
Higher MIPs
ADSP-21991
32K PM/8K DM
ADSP-21990
ADSP-2199x
Increased Mixed-Signal
160 MIPs
14-Bit, 20 MSPS ADC
ADSP-2199x
Different Peripherals
2001
2002
2003+
Package
Max
MIPS
Program
RAM Words
Data
RAM Words
ADSP-21990
ST, BC
160
4K
4K
ADSP-21991
ST, BC
160
32K
8K
Device
ADC
Status
14-Bit
20 MSPS
14-Bit
20 MSPS
Samples Now
Release 2Q02
Samples 3Q02
Release 4Q02
Packages: ST = Thin Quad Flat Pack (LQFP)
BC = Mini Ball Grid Array (10 x 10 mm)
Processor
Evaluation
Development Platform
ADSP-2199X
ADDS-21990-EZLITE $495
Emulator
Development
Software
ADDS-APEX-ICE
$4995
ADDS-SUMMIT-ICE $4995
VDSP-21XX-PC-FULL $3500
VDSP-21XX-PCFLOAT $4250
Note: DSP tools pricing is US dollars and subject to change at anytime. Volume discounts are available for VisualDSP++.
Please contact your local ADI sales representative or distributor for more information.
4
DSP Selection Guide
http://www.analog.com/dsp
Embedded DSP-Based Control Key Products
Recommended for New Designs
High Performance Control
ADSP-21991
32K PM RAM
8K DM RAM
Performance and Functionality
ADSP-21990
160 MIPS
14-Bit, 20 MSPS ADC
ADSP-217x
ADMC401
ADSP-219x
12-Bit, 6 MSPS ADC
Address/Data Bus
Low-Cost Control
ADMCF34x
ADMCF32x
TM
DashDSP
28-Lead SOIC/PDIP
Flash & ROM
ISENSE
2000-2001
Released
Sampling
Package
Max
MIPs
ADMC401
144-LQFP
26
ADMC340/F340
28-Lead SOIC
64 QFP
Flash & ROM
Enhanced ISENSE
1998-1999
Device
ADMC32x
ADMCF32x
ADMC341/F341
Processor
Core
28-SOIC
28-SOIC
28-SOIC
64-TQFP
20
20
20
20
2002-2003
Program Program Program Data
RAM
FLASH
ROM
RAM
2K
0.5K
0.5K
0.5K
0.5K
2K
4K
4K
4K (F341)
4K (F340)
4K (341)
4K (340)
1K
0.5K
0.5K
0.5K
0.5K
ADC
8 Channel,
12-Bit
Varies
Varies
6 Channel,
10-Bit
13 Channel,
10-Bit
Price*
$19.95
**CF
$11.65
**CF
**CF
* US Dollars. Lowest grade suggested resale price per unit in 1000 unit quantities
All pricing is budgetary – subject to change
** CF = Contact factory for pricing
Device
Evaluation Development Platform
ADMC401
ADMC32x/F32x
ADMC401-ADVEVALKIT
ADMCF326-EVALKIT
ADMCF327-EVALKIT
ADMCF328-EVALKIT
ADMCF341-EVALKIT
ADMCF340-EVALKIT
ADMC341/F341
ADMC340/F340
http://www.analog.com/motorcontrol
Price
$395
$395
$395
$395
DSP Selection Guide
5
ADI DSP Overview
Architectural Roadmaps
Analog Devices is the world's fastest-growing DSP supplier. Our portfolio includes mixed-signal DSPs,
general-purpose DSPs, such as the SHARC®, TigerSHARC®, Blackfin, and ADSP-21xx DSP families,
and embedded DSP solutions that serve secure data, ADSL modems, GSM handsets, internet access,
speech processing and motor control applications. ADI leverages 30 years of high performance analog
expertise to develop DSPs that make the design challenge easier. ADI's DSP architectures feature simple,
yet powerful programming models and are supported by high-quality development tools. More than 30,000
software developers have invested in our 16-bit and 32-bit fixed-point and floating-point DSP architectures.
Analog Devices 16-Bit DSP Roadmap
First to integrate 32Kw SRAM on a DSP
,
World s smallest DSP (ADSP-2183)
Highest memory density in industry (ADSP-2188N)
,
First Blackfin DSP, industry s highest performance Dual MAC DSP
(ADSP-21535
at 300 MHz)
,
Industry s highest performance, low cost Dual MAC DSP
(ADSP-21532 at 300 MHz at $10)
First to market a sub-$10 DSP at 160 MHz (ADSP-2196)
1994
2000 MMACs
1996
1998
2000
2002
2004
2006+
600 MMACs
Blackfin
DSP Family
500 MMACs
Up to 2000 MMACs
400 MMACs
300 MMACs
200 MMACs
ADSP-219x
Family
100 MMACs
Up to 300 MMACs
ADSP-218x Family
80 MMACs, Pin-for-Pin Compatibility
Analog Devices SHARC DSP Roadmap
First DSP to integrate 30 million transistors (ADSP-21060)
First 32-bit DSP to 120 MFLOPS
First 32-bit DSP to 1 GigaFLOPS
First DSP to 2 Billion MACS
1994
2700 MFLOPS
1995
1996
1997
1998
1999
2000
2001
2002
2004
2006+
TigerSHARC DSP
5 Billion Operations per Second
8-Bit, 16-Bit, 32-Bit DSP
2100 MFLOPS
1500 MFLOPS
STATIC SUPERSCALAR
SHARC DSP
900 MFLOPS
1200 - 2400 MFLOPS
SIMD SHARC DSP
300 MFLOPS
1200 MFLOPS
Next Generation $5 SHARC DSP
Multiprocessing Leader
SISD SHARC DSP
Up to 198 MFLOPS and as Low as $10 per Unit
6
DSP Selection Guide
http://www.analog.com/dsp
DSP Markets and Applications
As the processing capabilities of DSPs increase,
they are used in more and more applications.
Audio Signal Processing
DSP Function
• Reverb
• Tone Control
• Echo
• Filtering
• Audio Compression
• Frequency Equalization
• Pitch Shifting
• Spatial Effects
• Surround Sound
Application
• Musical Instruments & Amplifiers
• Audio Mixing Consoles
• Recording Equipment
• Disc Jockey Mixing Consoles
• Broadcast Equipment
• Cable TV Equipment
• Audio Equipment & Boards for PCs
• Toys & Games
• Automotive Sound Systems
• Digital Audio Tape Players
• Compact Disk Players
• HDTV Equipment
• Digital TV
• DVD Players
• Home Theater AVR Systems
Recommended DSPs
• ADSP-21065L • ADSP-TS101S
• ADSP-2116x • ADSST-MEL-30
• ADSP-21532 • ADSST-AUDIO-7085
Speech Processing
DSP Function
• Speech Synthesis
• Speech Recognition
• Speech Compression
• Text to Speech
• Pitch Shifting
• Filtering
• Speech Record &
Playback
Application
• Digital Tapeless Recorders
• Voice Store Equipment
• Phone Mail
• Voice Secure Entry Systems
• Intercom Systems
• Personal ID Systems
• Audio Equipment & Boards for PCs
• Toys & Games
Recommended DSPs
• ADSP-218xM/N • ADSP-219x
• ADSP-2153x
• ADSP-21065L
• ADSP-TS101S
• ADSP-21161N
Communications
DSP Function
• Modulation &
Transmission
• Demodulation &
Reception
• Speech Compression
• T1 Switching
• DTMF
• Data Encryption
• Signal Recovery
• Echo Cancellation
• Voice Over Data
• Voice Over IP
Application
• Modems
• Fax Machines
• PBX Systems
• Phone Mail Systems
• Private Data Communications
Systems
• Automatic Teller Machines
• Broadcast Equipment
• Mobile Phones
• Digital Pagers
• Global Positioning Systems
• Secure, Speaker, & Video Telephones
• Digital Answering Machines
• Satellite Phones
• Wireless Local Loop
• Telecom Infrastructure
Recommended DSPs
• ADSP-218xM/N • ADSP-2153x
• ADSP-21065L • ADSP-TS101S
• ADSST-NAV2400
• ADSP-219x
Instrumentation and Measurement
DSP Function
• Fast Fourier Transform
(FFT)
• Filtering
• Waveform Synthesis
• Adaptive Filtering
• High Speed Numeric
Calculations
Medical Electronics
DSP Function
• Filtering
• Echo Cancellation
• Fast Fourier Transform
(FFT)
• Beam Forming
Application
• Respiration Monitoring Equipment
• Heart Rate/Cardiac Monitoring
• Ultra Sound Equipment
• Medical Imaging Equipment
• Blood Analyzers
• Fetal/Infant Monitors
• Patient Monitors
• Blood Flow Monitors
• CAT Scanners
• Hearing Aids
Recommended DSPs
• ADSP-218xM/N • ADSP-2153x
• ADSP-2116x
• ADSP-TS101S
• ADSP-2106x
• ADSP-219x
Optical and Image Processing
DSP Function
• 2-Dimensional Filtering
• Fast Fourier Transform
(FFT)
• Pattern Recognition
• Image Smoothing
Application
• Bar Code Scanners
• Underwater Object Finders
• Automatic Inspection Systems
• Fingerprint Recognition
• Digital Televisions
• Sonar/Radar Systems
• Robotic Vision
• Vision Systems
Recommended DSPs
• ADSP-2106x
• ADSP-2199x
• ADSP-2116x
• ADSP-2153x
• ADSP-219x
• ADSP-TS101S
Industrial/Motor Control
DSP Function
• Filtering
• Fast Fourier Transform
(FFT)
• Control Loops
• Noise Cancellation
• Flash Memory
Multimedia
DSP Function
• Audio Encoding
• Audio Compression
• Video Encoding
• Video Compression
• Image Encoding
• Image Compression
Application
• Test & Measurement Equipment
• Vibration Analysis Equipment
• I/O Cards for PCs
• Automotive Engine Analyzers
• Automotive Wheel Balancers
• Industrial Scales & Measurement
• Active Mufflers
• Oil Drilling Equipment
• Seismic Instruments
• Power Meters
• Exercise Machines
• Signal Analyzers
• Function/Signal Generators
Recommended DSPs
• ADSP-218xM/N • ADSP-2153x
• ADSP-21065L
• ADSP-TS101S
• ADSP-21161N
• ADSP-2199x
• ADSP-219x
Application
• Digital Imaging
• Digital Printing
• Internet Appliance
• Broadband
• PDA
• Video Conferencing
Recommended DSPs
• ADSP-2153x
• ADSP-TS101S
http://www.analog.com/dsp
Application
• Motors in Appliances, Robotics or
Office Automation
• Power Management Equipment
• Generators
• Elevators
• Air Conditioners
• High Speed
• Traffic Control
Controls
Systems
• Uninterruptible
• Navigation
Power Suppies
• Disk Drives
• Switched Mode
• Vibration
Power Supplies
Analyzers
Recommended DSPs
• ADSP-2106x
• ADSP-218xM/N
• ADSP-2116x
• ADSP-219x
• ADMCxxx
• ADSP-2153x
• ADSP-2199x
DSP Selection Guide
7
ADI DSP Key Benefits
Selecting a DSP processor can be a difficult task.
Design engineers are concerned with time-to-market, for which ease of use, quality development
tools, extensive application engineering support,
and the availability of algorithm code are critical.
Of course, designers are also concerned with low
production cost, low power consumption, system
integration, and other criteria such as clock frequency, size of on-chip memory, and high-level
8
language support. To understand the benefits of
ADI’s families of 16- and 32-bit DSPs and how
ADI’s architectures are optimized for digital signal processing, keep in mind three basic features
of DSP. DSPs must have the ability to:
1) Perform fast arithmetic
2) Fetch data at a fast rate
3) Sequence efficiently through repetitive
operations
Key Feature
Benefit
Single Cycle Instruction
Execution
• One cycle per instruction execution
• ADSP-218x requires no extra latency cycles for decision branches, condition
code checking, or subroutine calls
• Delayed branches increase efficiency on pipelined architectures such as the
SHARC® and ADSP-219x DSP families
• Deterministic operations make it easy to develop, profile, and benchmark code
• Blackfin DSP allows for 1 instruction and 2 data fetches per cycle
Code Compatible Family
Members
• All ADSP-21xx Family members share the same base architecture and
assembly language
• All SHARC DSP Family members share the same base architecture and
assembly language
• No need to learn or invest in new development tools when moving from one
family member to another
• Software investment is preserved
• Blackfin DSPs utilize an interlocked pipeline so future core versions will protect SW code investment
Simple Programming
Language
• Algebraic syntax assembly language makes code easy to use, easy to
learn, and easy to read
• Unlike competitors who use mnemonics like SPAC and XORX, ADI
assembly language syntax makes programming in highly-efficient assembly language easy
Balanced Core, Memory
and I/O Integration
• Fast core processing, large on-chip memories, and high bandwidth I/O
simplify real-time system development
• Up to 14 channels of non-intrusive Direct Memory Access (DMA) allow
data movement without interrupting math processing
• Blackfin DSPs offer dual-ported L1 memory so the core can be fed while
simultaneously loading in new data non-intrusively
Large On-Chip Memory
• Provides ample on-chip storage for most common DSP tasks such as digital filtering and FFTs, eliminating the need for off-chip memory
Efficient Program
Sequencing and
Zero-Overhead Looping
• Minimizes off-chip memory access wait states
• On-chip hardware manages looping and provides the most efficient code
execution with no extra programming for repetitive DSP code
• No need to control looping with complex software
Pin-for-Pin Compatible
Family Members
• Increase speed or memory integration within a common pin-out
• Adds flexibility without requiring board redesign
DSP Selection Guide
http://www.analog.com/dsp
ADI DSP Customer Support
Web
You can visit Analog Devices’ World Wide
Web home page. Browse through a wide
assortment of information about the company
and products. You can also get detailed technical information as well as cross reference information. A search engine and site map will help
you find what you are looking for. You can
reach Analog Devices over the internet at
www.analog.com/dsp. Here you’ll find:
• Applications and Solutions
• Development Tools
• Data Sheets & Manuals
• DSP Collaborative
• Technical Support
• University Program
• Training and Education
Literature
North America:
Telephone: 800-ANALOGD
Faxback:
800-446-6212
Europe:
Telephone: +49 89 76903 312
DSP Tools Support
North America:
Telephone: 800-ANALOGD
Worldwide:
Email:
[email protected]
Web: http://www.analog.com/dsp/tools
Faxback System
You can get 24 hour access to data sheets for
Analog Devices products by using the Analog
Devices FAXback automated literature delivery
system. Simply call 1-800-446-6212 and follow
the recorded instructions. By providing a FAX
code and your FAX number, you can receive a
copy of a data sheet in a matter of minutes. An
index of products and FAX codes can be faxed
to you upon demand. (available for USA and
Canada only).
DSP Customer Support
Technical Assistance
North America:
Email:
[email protected]
Fax:
781-461-3010
Europe:
Telephone: +49 89 76903 333
Email:
[email protected]
Fax:
+49 89 76903 307
Worldwide Headquarters:
One Technology Way
Norwood, MA 02062-9106, U.S.A.
Telephone: 1-781-329-4700
(1-800-262-5643 USA only)
Fax:
1-781-326-8703
Europe Headquarters
Am Westpark 1-3
81373 Munchen, Germany
Telephone: +49 89 76903-0
Fax:
+49 89 76903-157
Japan Headquarters
New Pier Takeshiba, South Tower Building
1-16-1 Kaigan Minato-Ku,
Tokyo 105-6891, Japan
Telephone: +81 3-5402-8210
Fax:
+81 3-5402-1063
Southeast Asia Headquarters
4501 Nat West Tower, Times Square
Causeway Bay, Hong Kong
Telephone: +852 2506 9336
Fax:
+852 2506 4755
http://www.analog.com/dsp/tools
DSP Selection Guide
9
VisualDSP++
Integrated Development Environment
Overview
Features
Integrated Development and Debugger
Environment
• Develop within a single interface (IDE/debugger)
• Profile and trace instruction execution of C/C++
and assembly programs (simulator only)
• Set watchpoints (conditional breakpoints) on
processor registers and stacks, as well as program and data memory including:
– Statistical profiling
– MP (multiprocessing)
– Graphical plotting
• Define all project and tool configurations
through property page dialog boxes
• Set project-wide or individual file settings for
debug or release mode project builds
• Create source files using an integrated, fullfeatured editor with syntax highlighting, OLE
drag and drop, and bookmarks

VisualDSP++ is an easy-to-use project
management environment, comprised of an
integrated development environment (IDE) and
debugger. VisualDSP++ enables management
of projects from start to finish from within a
single interface. The project development and
debug environments are integrated, allowing
movement easily between editing, building, and
debugging activities.
VisualDSP++ Kernel (VDK)
• Scheduling and resource management
• Supports threads, events, semaphores, critical
and unscheduled regions
Code Generation Key Features
• Develop applications using an optimizing
C/C++ compiler
• Intersperse inline assembly statements within
C/C++ source code
• Create executables using a linker that supports multiprocessing, shared memory, and
code overlays
• Access numerous math, DSP, and C/C++
runtime library routines
• Create host, link port, and PROM boot
images
• Initialize all data and code memory locations
using modifiable loader
• Concatenate multiple executables within
single PROM image
10 DSP Selection Guide
VisualDSP++ interface
Platform and Processor Support
VisualDSP++ supports the SHARC® DSP,
TigerSHARC® DSP , Blackfin DSP, and the
ADSP-218x and ADSP-219x DSP families on
Windows® 98, Windows NT, Windows 2000,
and Windows XP. Refer to ADI’s web site for
specifications and availability.

Flexible Project Management
The IDE provides flexible project management
for the development of DSP applications. The
IDE includes access to all the activities
necessary to create and debug DSP projects.
The IDE editor allows the creation or
modification of source files or viewing of
listing or map files. This powerful editor is part
of the IDE and includes multiple language
syntax highlighting, OLE drag and drop,
bookmarks, and standard editing operations
such as undo/redo, find/replace, copy/paste/cut,
and go to.
http://www.analog.com/dsp/tools
VisualDSP++
The IDE allows access to the DSP C/C++
compiler, C/C++ runtime library, assembler,
linker, loader, and splitter. Specification of
options for these tools is made possible through
the property page dialogs. Property page
dialogs are easy to use and simplify
configuring, changing, and managing projects.
These options may be defined once and then
modified to meet changing development needs.
The DSP code generation tools can be accessed
from the operating system command line.
Greatly Reduced Debugging Time
The VisualDSP++ debugger has an easy-to-use,
common interface to all DSP simulators and
emulators available through Analog Devices,
Inc. (ADI) and from many third party partners.
The debugger has many features that greatly
reduce debugging time. C/C++ source can be
viewed interspersed with the resulting assembly
VisualDSP++
Development
Environment
Software
Simulator
EZ-KIT Lite™
Hardware
complex signal processing data types and take
advantage of specialized DSP operations
without having to understand the underlying
DSP architecture.
VisualDSP++ simplifies DSP development via
common development environment across all
Analog Devices hardware and DSPs.
VisualDSP++ Kernel
The VisualDSP++ Kernel (VDK) provides
state-of-the-art scheduling and resource
allocation techniques tailored specifically to
address the memory and timing constraints of
DSP programming. These techniques enable
engineers to use example code more efficiently,
eliminating the need to start from the very
beginning. The VDK has standard libraries and
frameworks with defined APIs that allow easy
inclusion of boilerplate, class libraries and
value-added IP code.
ActiveX
Emulator
Hardware
Third-Party
Hardware
SHARC DSP, TigerSHARC DSP,
ADSP-21xx, Blackfin DSP
TM
VisualDSP++ simplifies DSP development via
common development environment across all
ADI hardware and DSPs
code. Users can profile execution of a range of
instructions in a program; set watch points on
hardware and software registers, program and
data memory; and trace instruction execution
and memory accesses. These features enable
users to correct coding errors, identify
bottlenecks, and examine DSP performance.
The custom register option allows developers
to select any combination of registers to view
in a single window. The debugger, when used
with the simulator, can also generate inputs,
outputs, and interrupts to simulate real world
application conditions. With C++, developers
can realize a significant increase in time to
market with the ability to efficiently work with
ActiveX allows new functionality to be added
by developers and third parties to VisualDSP++
in the form of “plug-ins” that integrate into the
VisualDSP++ environment. Third parties will
be able to seamlessly port their software to
VisualDSP++’s front-end. Developers will be
able to merge tool suites together to improve
design, analysis and verification thus they will
only need to learn one interface to use ADI
third party tools.
Multiprocessing Support
VisualDSP++’s smart multiprocessor (MP)
debug support provides a seamless interface to
multiple DSPs on the same physical hardware.
Users are able to issue parallel step, run, and
halt commands to all of the applicable DSPs.
The developer can pick and choose individual
DSP register or memory sets of interest by
pinning those that should be updated between
runs, halts and steps. This feature also
eliminates screen clutter in multiprocessor
debugging.
http://www.analog.com/dsp/tools
DSP Selection Guide
11
VisualDSP++
VisualDSP++’s multiprocessor dialog box and toolbar
Statistical Profiling
Statistical profiling allows for a more
generalized form of profiling that JTAG
emulator debug targets can take advantage of.
The debugger has the ability to unintrusively
random sample the target processors PC and
then present the user with a graphical display
of the resultant samples. This allows the user to
easily see where their application is spending
most of its time.
VisualDSP++’s statistical profiling window
Graphical Profiling
The plot window supports exporting images to
both bitmap and JPEG format files and has
highly configurable formatting options such as
title, subtitle, font size, font face, font color and
element colors.
Code Generation Tools
DSP code generation tools allow development
of applications that take full advantage of the
DSPs architecture, including multiprocessing,
shared memory, and memory overlays. Code
generation tools include the C/C++ compiler,
C/C++ runtime library, DSP and math libraries,
assembler, linker, loader and splitter. Code
generation tools work seamlessly within the
VisualDSP++ environment.
12 DSP Selection Guide
VisualDSP++’s plot window
VisualDSP++ Component Software
Engineering (VCSE)
VCSE supports an Interface Definition
Language (IDL) and compiler that allows
developers to create and use components
without having to become familiar with the
detail of the model and the mechanisms it
involves, allowing them to concentrate on the
application itself. Component Software is
designed to function as a re-usable part of a
larger program. Components can easily be
integrated into an application and capable of
reusability. Integration with VisualDSP++
simplifies the process of incorporating and
utilizing components from a variety of
developers.
C/C++ Compiler and Assembler
The C/C++ compiler generates efficient code
that is optimized for both code density and
execution time. The C/C++ compiler can be
easily interfaced with assembly code modules.
Thus, users can program in C/C++ and still use
assembly for time-critical loops. The math,
DSP, and C/C++ runtime library routines help
shorten time to market. The SHARC DSP,
TigerSHARC DSP, Blackfin DSP, ADSP-218x
(ADSP-218x does not have C++) and
ADSP-219x DSP family assembly language is
based on an algebraic syntax that is easy to
learn, program, and debug. The enhanced
assembler helps the programmer write optimal
assembly code by analyzing code sequences and
http://www.analog.com/dsp/tools
VisualDSP++
providing feedback to the user on latencies and
stalls. Feedback is given as warnings and
informational messages out of the assembler and
in the assembler listing.
Linker & Loader
The linker provides flexible system definition
through linker description files (.ldf). In a
single .ldf file, users are able to define different
types of executables for a single or
multiprocessor system. The linker resolves
symbols over multiple executables, maximizes
memory use, and allows common code to be
shared among multiple processors. The loader
supports creation of host, link port, and PROM
boot images. Along with the linker, the loader
allows multiprocessor system configuration
with smaller code and faster boot time.
Expert Linker
The “Expert” Linker creates a graphical utility
that makes it easier for users to produce Linker
Definition File (LDF) without having to learn
the LDF syntax. The graphical representation of
the commands in an LDF file also allows the
engineer to manipulate the graphical
representation for changes to the LDF or
generation of an LDF file. The Expert Linker
also allows users to optimize their placement of
code.
Cache
The Blackfin DSP simulator collects cache
statistics that are associated with both the
PC/Source Line and the Cache Line/Set.
Collectable statistics are; Total Cache Accesses,
Cache Hits, and Cache Misses. There will be
three types of displays: Histogram by PC/Source
Line, Cache Line Display where hit/miss data is
associated by Cache Line/Set(way), Summary
Display of totals for hits/misses by cache.
Pipeline Viewer
The Pipeline Viewer is an ActiveX plug-in that
allows a user to visually display the instruction
flow through the sequencer's pipeline. Stalls,
aborts and other pipeline events are graphically
displayed. Visualization of the pipeline and of
the pipeline events allows a user to better
understand where and why latencies and stalls
are being introduced into an executable. Armed
with this knowledge the user can optimize an
executable's instruction sequence to minimize
the number of pipeline events.
The DSP Collaborative
The VisualDSP++ environment enables
independent third party companies to add value
using ADI’s published set of application
programming interfaces (API’s). The DSP
Collaborative is a comprehensive collection of
DSP development support companies. The DSP
Collaborative product offerings – real-time
operating systems, emulators, high-level
language compilers, and multiprocessor hardware
– can interface seamlessly with VisualDSP++
thereby simplifying development across all
platforms and targets.
Ordering Information
Please call your local Analog Devices sales
representative or distributor for pricing and
ordering information. You may also visit the ADI
web site and buy online at www.analog.com.
http://www.analog.com/dsp/tools
http://www.analog.com/dsp/tools
DSP Selection Guide 13
Development Tools
16-Bit DSP Family and Blackfin DSP Family
Development tools from Analog Devices are
one of the industry's most complete lines, from
the economical EZ-KIT Lite™ evaluation kits to
an integrated development environment. These
tools are easy to learn and easy to use, and
allow designers to bring DSP-based products to
market quickly and efficiently.
VisualDSP++ Integrated Development
Environment
VisualDSP++™ is a comprehensive toolset for
Blackfin DSP, ADSP-218x and ADSP-219x
DSPs. VisualDSP++ enables design engineers to
easily develop, debug, and deploy code throughout
the research, design, development, and test
stages of any project. VisualDSP++ integrates
all of the code generation tools below:
• Assembler
• Linker
• Simulator
• C/C++ compiler
• Debugger
• PROM splitter
• Graphical plotting
• Expert Linker
• Math, DSP and
C/C++ runtime library
• Integrated develoment
environment
• VisualDSP++ Kernel
• Statistical profiling
• VisualDSP++
Component Software
Engineering
Emulators: Emulators provide non-intrusive
target-based debugging of DSP systems.
Compact and easy to use, these in-circuit emulators perform a wide range of emulation functions including single-step and full-speed execution with pre-defined breakpoints, viewing
and/or altering of register and memory contents. A serial port emulator is available for the
ADSP-218x DSP family and JTAG emulators
are available for ADSP-219x DSPs and the
Blackfin™ DSP family.
Model
Supported DSP
Evaluation Kits
ADDS-2181-EZLITE
ADDS-2189M-EZLITE
ADDS-2191-EZLITE
ADDS-21535-EZLITE
ADSP-2100 Family
ADSP-2181
ADSP-218x Family
ADSP-219x
Blackfin DSP
Development Software
VDSP-21XX-PC-FULL
ADSP-21xx Family
VisualDSP++ IDE, Debugger,
Compiler, Assembler, Linker with
Emulation and Simulation Support
VDSP-21XX-PCFLOAT
ADSP-21xx Family
VisualDSP++ Floating License
VDSP-21XX-PC-TEST
ADSP-21xx Family
VisualDSP++ Test Drive
30-Day Free Trial
(ADSP-218x does not have C++ support)
EZ-KIT Lite Evaluation Kit: The EZ-KIT
Lite provides an easy way to evaluate the
power of ADI’s DSPs and begin to develop
applications. These systems consist of a standalone evaluation board and an evaluation suite
of VisualDSP++ to facilitate architecture
evaluations via a PC-hosted tool set.
Restrictions: Software is limited for use with
the EZ-KIT Lite and program memory is
limited in size. With the EZ-KIT Lite users can:
VDSP-BLKFN-PC-FULL Blackfin DSP Family
VisualDSP++ IDE, Debugger,
Compiler, Assembler, Linker with
Emulation and Simulation Support
™
VDSP-BLKFN-PCFLOAT Blackfin DSP Family
VisualDSP++ Floating License
VDSP-BLKFN-PC-TEST Blackfin DSP Family
VisualDSP++ Test Drive
30-Day Free Trial
Emulators
ADDS-218X-ICE-2.5V
ADDS-APEX-ICE
ADDS-SUMMIT-ICE
• Evaluate ADI's DSPs
• Learn about DSP applications
• Simulate & debug applications
• Prototype applications
14 DSP Selection Guide
http://www.analog.com/dsp/tools
ADSP-218xM/N Family
ADSP-219x and
Blackfin DSP USB-Based
ADSP-219x and
Blackfin DSP PCI-Based
Development Tools
®
SHARC and TigerSHARC® DSP Family
The 32-bit floating-point SHARC® DSP family
of products offer the simplicity of floatingpoint mathematics coupled with high memory
integration. With the highest level of floatingpoint performance, the TigerSHARC® DSP
products offer the flexibility of 1, 8, 16 and 32bit fixed-point math in addition to floatingpoint arithmetic.
Emulators: Emulators provide non-intrusive
target-based debugging of DSP systems. Compact and easy to use, these JTAG emulators
perform a wide range of emulation functions
including single-step and full-speed execution
with pre-defined breakpoints, viewing and/or
altering of register and memory contents. DSP
emulators are available for PCI and USB host
platforms.
VisualDSP++ Integrated Development
Environment
VisualDSP++ is a comprehensive toolset for
SHARC and TigerSHARC DSPs. VisualDSP++
enables design engineers to easily develop, debug,
and deploy code throughout the research, design,
development, and test stages of any project.
VisualDSP++ integrates all of the code generation
tools below:
• Assembler
• Math, DSP and
• Linker
C/C++ runtime library
• Simulator
• Integrated develoment
• C/C++ compiler
environment
• Debugger
• VisualDSP++ Kernel
• PROM splitter
• Statistical profiling
• Graphical plotting • VisualDSP++
• Expert Linker
Component Software
Engineering
Model
EZ-KIT Lite™ Evaluation Kit: The EZ-KIT
Lite provides an easy way to evaluate the
power of ADI’s DSPs and begin to develop
applications. These systems consist of a standalone evaluation board and fundamental debugging software to facilitate architecture evaluations via a PC-hosted tool set. Restrictions:
Software is limited for use with the EZ-KIT
Lite and program memory is limited in size.
With the EZ-KIT Lite users can:
• Evaluate ADI's DSPs
• Learn about DSP applications
• Simulate & debug applications
• Prototype applications
Supported DSP
Evaluation Kits
ADDS-21061-EZLITE
ADDS-21160-EZLITE
ADDS-21160N-EZLITE
ADDS-21161N-EZLITE
ADDS-21065L-EZLITE
ADDS-TS101S-EZLITE
ADSP-2106x Family
ADSP-21160M
ADSP-21160N
ADSP-21161N
ADSP-21065L
ADSP-TS101S
Development Software
VDSP-SHARC-PC-FULL SHARC DSP Family
VisualDSP++ IDE, Debugger,
Compiler, Assembler, Linker
with Emulation and Simulation
Support
VDSP-SHARC-PCFLOAT SHARC DSP Family
VisualDSP++ Floating License
VDSP-SHARC-PC-TEST SHARC DSP Family
VisualDSP++ Test Drive
30-Day Free Trial
VDSP-TS-PC-FULL
TigerSHARC DSP Family
VisualDSP++ IDE, Debugger,
Compiler, Assembler, Linker with
Emulation and Simulation
Support
VDSP-TS-PCFLOAT
TigerSHARC DSP Family
VisualDSP++ Floating License
VDSP-TS-PC-TEST
TigerSHARC DSP Family
VisualDSP++ Test Drive
30-Day Free Trial
Emulators
ADDS-APEX-ICE
ADDS-SUMMIT-ICE
USB-Based
PCI-Based
http://www.analog.com/dsp/tools
http://www.analog.com/dsp/tools
DSP Selection Guide 15
The DSP Collaborative
ADI’s Third Party Partner Network
Tap Into the Experience and Global Reach of the DSP Collaborative
Working together to extend your design team
The DSP Collaborative partners (Analog
Devices’ Third Party Network) offer tools, services and solutions for a wide range of applications/markets:
Communications
Audio
Medical imaging
Speech processing
Motor control
Industrial automation
Optical networking
Voice over IP
Speed up your design process by leveraging the
solutions our partners have to offer:
When you select Analog Devices as your DSP
vendor, you’re broadening your design team to
include the industry-leading resources of the
DSP Collaborative. The DSP Collaborative is
comprised of over 180 partners who offer more
than 700 commercial products, in addition to
hundreds of custom solutions that build on
more than 35 years of signal processing experience found in every one of our DSPs. These
partners offer consulting services as well as a
wide range of commercial off-the-shelf (COTS)
products. Their development tools are specifically designed to work with Analog Devices’
DSP-based systems.
16 DSP Selection Guide
With the DSP Collaborative, you are supported
by highly-reputable brands, patented technologies, and the pioneers in real-time system
design and debug. The DSP Collaborative partners offer products and services that provide
both system and application-level expertise.
Algorithms and libraries
MATLAB® DSP support
Real-Time Operating Systems
Development and evaluation boards
COTS hardware boards
DSP systems
Emulators
Debuggers
Design with Analog Devices’ DSP
Collaborative team approach with a proven
strategy for maximizing your resources!
http://www.analog.com/dsp/3rdparty
http://www.analog.com/dsp/3rdparty
The DSP Collaborative
Key Partners
BittWare, Inc.
Transtech DSP
BittWare, Inc. is a leading supplier of SHARC-based
Transtech DSP is a total solutions provider of high
hardware and software solutions, providing our
performance DSP equipment. Pioneers of multi-pro-
clients with innovative off-the-shelf and application-
cessing DSP systems for more than fourteen years,
specific solutions for their high-performance, real-
Transtech systems use a number of processors
time signal processing and I/O requirements.
families, including the SHARC and TigerSHARC
Based exclusively on Analog Devices' SHARC tech-
DSPs, and a choice of industry standard formats
nology, BittWare’s product family includes innova-
such as VME, PCI, PMC and CompactPCI. The com-
tive standard DSP boards and I/O peripherals on a
pany's extensive product line also includes I/O
variety of embedded platforms including PCI bus,
boards, software tools, libraries, drivers, and enclo-
CompactPCI, PC/104, PC/104-Plus, PMC, PMC+,
sures, to provide our customers with complete sys-
and ISA bus. From prototype to high-volume pro-
tems or custom designs. Transtech products are
duction, off-the-shelf products to application-specif-
used to solve the most computer intensive of signal
ic solutions, BittWare is the embedded SHARC DSP
processing problems, which include radar, sonar,
solutions provider.
software radio, surveillance and medical imaging.
http://www.bittware.com
http://www.transtech-dsp.com
TM
LYRtech Signal Processing (LSP)
LYRtech Signal Processing (LSP) provides engineers
with complete, board-level solutions to their signal
processing needs. It offers a comprehensive line of
mixed DSP/FPGA boards that result in increased
performance, cost effectiveness and overall efficiency
of developed systems. Simplifying the design task,
LSP provides its users with a high-level integration
with The MathWorks' MATLAB/SIMULINK tools, as
well as Xilinx's System Generator. The integration
makes it possible to rapidly implement designs, but
later also perform software optimization through lowlevel schemes (embedded JTAG, optimized libraries,
profilers, etc.). Completing the line, LSP provides customers with comprehensive consulting
and support packages in the fields of
telecommunications and multimedia.
http://www.signal-lsp.com
http://www.analog.com/dsp/3rdparty
DSP Selection Guide 17
SPA DSP Software Algorithms
Analog Devices SPA Technology Centre (formerly Signal Processing Associates) is recognized
worldwide for providing expertise in DSP solutions for the telecommunications and multimedia
industry since 1987. The SPA product range consists of a broad portfolio of DSP software algorithms including speech compression, echo cancellation, fax and data modem-pumps, error correction and numerous other telephony code modules. Typical product application areas are listed
below. The SPA Technology Centre is renowned for excellent customer support, product documentation and APIs that allow rapid integration of the code into customer’s new product designs.
Audio/Speech Software Algorithms
G.723.1 (5.3/6.3 kbit/s)
G.723.1A (5.3/6.3 kbit/s)
G.729 (8 kbit/s)
G.729A (8 kbit/s)
G.729B (8 kbit/s)
G.729AB (8 kbit/s)
G.728 (16 kbit/s)
G.726 (40/32/24/16 kbit/s)
G.727 (40/32/24/16 kbit/s)
G.722 (64/56/48 kbit/s)
G.711 (64 kbit/s)
Variable Rate Coders
H.32x Audio Modules
Voice Activity Detectors (VAD)
Voice AGC (Variable response time)
Comfort Noise Generator (CNG)
End to End Synchronization
Echo Cancellation Software Algorithms
G.168 Line Echo Canceller (LEC)
G.165 Line Echo Cancellation (LEC)
Acoustic Echo Cancellation (AEC – variable span)
Acoustic Echo Suppression (AES)
Data Modem Software Algorithms
V.33 (14,400 bps 4-wire)
V.32bis (14,400 bps)
V.32 (9,600 bps)
V.29 (9,600 bps 4-wire)
V.22bis (2,400 bps)
V.27ter (4,800 bps 4-wire)
V.22 (1,200 bps)
V.23 (1,200/75 bps)
Bell 212A (1,200 bps)
Bell 103 (300 bps)
V.21 (300 bps)
Facsimile Modem Software Algorithms
V.17 (14,400 bps)
V.33 (14,400 bps)
V.29 (9,600 bps)
18 DSP Selection Guide
V.27ter (4,800 bps)
V.21 (300 bps)
Forward Error Correction (FEC) Software Algorithms
Viterbi / Trellis
Interleavers
Reed Solomon
Telephony Software Algorithms
Relay (4-64 kbit/s transmission of voice/fax/data over
internet, satellite, radio, microwave, ISDN, LAN, ATM
& other packet networks)
Internet Audio
Speakerphone
DTMF Detector (high performance & Bellcore, EIA,
ETSI, Telstra compliant)
DTMF Encoder (high performance & ITU, Bellcore,
EIA, ETSI, Telstra compliant)
Call Progress
Caller ID
RTP/JIB (Jitter Buffer)
Ring Detector
E & M Signalling
Tone Detection System (TDS)
Gaussian Noise Source (GNS) Ultra-high quality
wideband gaussian noise generator
Product Application Areas
Internet Telephony
H.324
VoN
H.323
VoIP
H.320
VoDSL
Audioconferencing
VoATM
Videophones/Feature-phones
VoCable
Digital Voice Storage
FoN
Frame Relay
FoIP
PBX Equipment
TRAU/Transcoders RAS
Basestations
DSVD
Wireless/Mobile
DCME
Gateways
ISDN
CPE/IADs/SOHO/CO Rural Radio Networks
IP Phones
Satellite/Microwave Systems
http://www.analog.com/spa
http://www.analog.com/dsp
SPA DSP Software Algorithms
Peak
MIPS
Average
MIPS
PM
(Words)
18.4
18.9
18.6
19.1
19.9
10.8
20.1
12.7
16.9
17.6
17
17.6
18.9
10.4
19.3
10.8
9558
9558
9558
9558
8844
7932
12064
11900
11679
11679
11679
11679
4634
4677
5405
7700
0
0
0
0
0
0
0
0
951
951
951
951
1432
1532
1603
1821
29
8.5
9.9
12.9
0.4
1
27
8
N/A
N/A
0.4
N/A
7947
1466
1262
1458
111
2011
2272
240
252
217
6
1700
930
47
0
0
1743
100
0
50
16 msec, ECD On
16 msec, ECD Off
32 msec, ECD On
32 msec, ECD Off
64 msec
128 msec (sparse)
Acoustic Echo Canceller
6.6/7.03
4.5/4.97
9.2/10.6
7.1/8.57
15
5.2
N/A
N/A
N/A
N/A
N/A
N/A
N/A
1100/1211
1100/1211
1100/1211
1100/1211
1000
3153
354/412
354/412
354/412
354/412
124
3059
276
276
276
276
0
340
340
340
340
1700
Acoustic Echo Canceller
7.2
N/A
3153
3059
Acoustic Echo Canceller
11.2
N/A
3153
3059
Acoustic Echo Canceller
15.2
N/A
3153
3059
Encoder
Decoder
*Bellcore (I & II)
*Tone Generation
*Tone Detection System
Voice Activity Detection
Comfort Noise Generation
0.5
1
1.8
0.5
2.5
0.2-2.0
1
N/A
N/A
N/A
N/A
N/A
N/A
N/A
68
1300
939
70
1207
515
2011
78
320
53
80
641
166
1700
2
0
0
4
0
0
0
256
180
2
123
50
Description
DM
PM+
(Words) (Words)
DM+
(Words)
Vocoders
G.723.1
G.723.1
G.723.1A
G.723.1A
G.729
G.729A
G.729B
G.729AB
G.728
G.726
G.727
G.722
G.711
G.711 (II)
5.3 kbit/s
6.3 kbit/s
5.3 kbit/s + VAD/CNG
6.3 kbit/s + VAD/CNG
8 kbit/s
8 kbit/s (low MIPS)
8 kbit/s + VAD/CNG
8 kbit/s (low MIPS +
VAD/CNG)
16 kbit/s
40/32/24/16 kbit/s
40/32/24/16 kbit/s
64/56/48 kbit/s
64 kbit/s
64 kbit/s + adaptive CNG
Echo Cancellation
G.165/G.168
G.165/G.168
G.165/G.168
G.165/G.168
G.168
G.168
AEC
64 msec span
AEC
128 msec span
AEC
256 msec span
AEC
384 msec span
Telephony
DTMF
DTMF
Caller ID
Call Progress
TDS
VAD
CNG
This table presents only a selection of SPA’s most popular ADSP-218x and ADSP-219x based code modules.
Please contact SPA or refer to the SPA web site (www.analog.com/spa) for a full list of available algorithms.
Not currently multiple instance
Contact SPA for figures
* Other Standards on request
http://www.analog.com/spa
DSP Selection Guide 19
SPA DSP Software Algorithms
SPA Code Modules
The table on the previous pages summarize the key
resources used by SPA’s most commonly used DSP
software code modules. Please contact SPA or refer to
the SPA web site (www.analog.com/spa) for a full set
of available algorithms. Apart from the addition of
new modules, SPA also continuously revises existing
implementations in order to further reduce MIPS and
memory figures.
Optimized Assembler Code
The algorithms presented have been implemented for
execution on the Analog Devices ADSP-218x series of
fixed-point DSPs and are currently being ported to the
new ADSP-219x series of fixed-point DSPs. The
code has been written in highly optimized assembler
code and is hand-crafted by experienced DSP engineers in order to provide the lowest possible use of
DSP resources (MIPS, Program Memory and Data
Memory).
MIPS & Multiple Channels
It should be noted that SPA provides both peak and
average MIPS figures, as any MIPS budget should use
peak figures in order to choose a DSP of sufficient
resources. Most of SPA’s code modules have been written to be multiple-instance capable. This means multiple channels of the same function can be run on one
DSP. For example, six channels of G.729A can be executed concurrently on an 80 MIPS ADSP-218xN DSP.
G.729A, G.726, G.168 and DTMF detection simultaneously on one 52 MIPS DSP.
Choice of DSPs
The table on the previous pages allows you to calculate
how many MIPS and how much memory will be
required by a given set of functions. Knowing these
figures, and allowing for any user specific shell or functions, will enable you to select the most appropriate
DSP (of sufficient resources) from the ADSP-218x
product range. With the release of the new 160 MIPS
based ADSP-219x core comes an even higher channel
density capability per DSP. Added benefits of the higher MIPS DSPs include lower power consumption per
channel and lower board space per channel.
Standards Compliance & Code Quality
SPA code modules are compliant with international
standards such as the International Telecommunications
Union (ITU) and the voice coders are 100% bit compliant with the ITU test vectors. SPA’s algorithms have
been extensively tested, are used by numerous companies world-wide and have proven interoperability. SPA
code modules have a common Application
Programming Interface (API) based on a memory
mapped interface scheme. Detailed specification sheets
are available for download from the SPA web site
(www.analog.com/spa). Other support documentation
includes developer’s guides and test reports.
Commercial Aspects
Program & Data Memory
Running multiple channels of the same algorithm on
the same DSP requires only one copy of the program,
thus keeping Program Memory (PM) usage low. Each
additional instance of the same algorithm also requires
less Data Memory (DM), due to re-use of common
tables and variables. This is referred to as DM+ in the
table overleaf. A similar concept applies to storage of
data in Program Memory for additional instances, and
is referred to as PM+ in the table.
SPA can provide demonstration code for evaluation purposes and has excellent customer support to assist with
selection and integration issues. Specialized customization and consulting services are also available. SPA
provides flexible pricing and licensing arrangements.
The benefits of licensing SPA’s code, compared to inhouse development, include improved time-to-market,
experienced support, reduced risk, controlled cost and
the ability to allocate resources to other projects.
Multiple Functions
Analog Devices - SPA Technology Centre
Analog Devices Australia Pty Ltd
Unit 3, 97 Lewis Road
Wantirna, Victoria, 3152, Australia
Tel: +61 3 9800 2000 Fax: +61 3 9800 2111
[email protected]
www.analog.com/spa
Low MIPS and memory not only allows multiple
channels of the same module to be run on one DSP, it
also allows many different functions/modules to be
run on one DSP. For example, you could run G.723.1,
20 DSP Selection Guide
To Order - Contact SPA
http://www.analog.com/spa
Benchmarks
Comparing DSPs
To truly assess a processor’s performance, you
have to look beyond MHz, MIPS, or MFLOPS.
There are many attributes which may be more
accurate predictors of a DSP’s real-time embedded processing performance.
Circular Buffers
Circular buffers allow a region of memory to
be continually accessed without explicit program interaction. The buffer uses a pointer that
automatically resets to the beginning of the
buffer (wrap around) if the pointer is advanced
beyond the last location in the buffer. Circular
buffers are a key feature of DSP routines.
Multiple buffers are used in the same routine to
store filter coefficients and implement a delay
line of input samples. Performance suffers if
the DSP core has to perform pointer calculations along with the calculations for the routine. Performance also suffers if the DSP core
only supports one circular buffer and must save
and restore address registers to implement multiple buffers.
ADI’s DSPs have hardware support for multiple circular buffers, eliminating processor
overhead for address calculations.
Data Registers
The number of general-purpose data registers
available can impact the code performance.
Fewer registers require intermediate results to
be stored in memory decreasing performance
and increasing the load on the memory bus.
DMA Channels/Non-Intrusive DMA
The DMA (Direct Memory Access) channels
transfer data between an external source and
the DSP’s on-chip memory. With DMA channels, data transfers occur without the core
processor having to execute data movement
instructions. For example, the overhead clock
cycles used to move data for an FFT can add a
significant amount of time to overall algorithm
execution. With multiple DMA channels available, all data transfers happen without core
involvement, eliminating any overhead clock
cycles.
One of the strengths of Analog Devices’ DSP
architecture is that these DMAs do not interfere with the core operation. This capability
is referred to as non-intrusive or
zero-overhead DMA.
Interrupt Latency
Interrupt latency is a measure of how
quickly a DSP responds to an interrupt.
Quick response is important especially in
real-time processing. For example, an
interrupt might indicate the availability of
data which is only available for a finite
amount of time. Therefore, fast response is
critical or the data will be lost.
ADI DSPs feature fast interrupt response
time for quick execution of interrupt service
routines.
ADI DSPs feature a secondary register set
which allows for quick context saves when
interrupts occur, rather than delaying
responses to the interrupt while all register
values are saved to memory.
http://www.analog.com/dsp
DSP Selection Guide 21
Benchmarks
Comparing DSPs
Multiprocessing Support
TDM Mode
Even with the powerful DSPs available today,
there are times when the DSP task for a given
system does not fit into a single DSP. Examples
of such applications include sonar, radar, medical imaging, audio mixers, etc. In these cases,
the ability to connect multiple DSPs in a system without any glue logic greatly simplifies
the implementation.
TDM (Time Division Multiplexed) mode refers
to time division multiplexing which is a common mode for transferring serial data. In
telecommunications applications, T1 and E1
lines use TDM. TDM allows multiple serial
devices to send and receive information using
the same physical connection. TDM also allows
communication between multiple DSPs.
ADI offers SHARC DSPs with specialized
hardware for glueless multiprocessing.
All ADI DSPs support TDM mode in the
serial ports.
On-Chip Memory/On-Chip SRAM Size
Zero-Overhead Looping
The amount of on-chip memory available can
greatly impact system performance, cost, size,
power consumption and complexity. Any time
the DSP core accesses external memory, the
performance can suffer. Off-chip memory often
requires the core to wait additional cycles. In
contrast, the DSP core can access on-chip
memory at the same rate as its instruction rate.
The addition of external memory adds extra
components to the system which increases cost,
power consumption, and complexity.
The code for most DSP routines falls naturally
into a set of nested loops. Without the support
for zero-overhead looping, the DSP core must
spend cycles calculating the loop termination
values, in addition to the cycles used to process
the algorithm’s computations. Without zerooverhead looping, performance degrades.
ADI offers 16-bit fixed-point and 32-bit
fixed/floating-point DSPs with zero
overhead, nestable looping to save instruction cycles.
ADI leads the industry in DSP SRAM integration. ADI processors have on-chip memories which often eliminate the need for external memory in a system. Furthermore, the
memory is configurable for data word size,
code word size and storage size. This allows
designers to tailor the memory to meet the
algorithm requirements.
22 DSP Selection Guide
http://www.analog.com/dsp
16-Bit DSP Family Benchmarks
ADSP-21535 Benchmarks
Cycle Count
Execution Time @ 300 MHz
h/2
2.5*bq
2*h
13938
3610
Block FIR Filter
Biquad IIR Filter (4 coeff)
Complex FIR Filter
1024-Point Complex FFT (prescaled)
256-Point Complex FFT (out-of-place)
ADSP-219x Benchmarks
Cycle Count
FIR Filter Tap
Biquad IIR Filter (4 coeff)
Complex FIR Filter
1024-Point Complex FFT Radix 2
Division
Sin/Cos
Arc Tangent
In/log10
47 us
12 us
Execution Time @ 160 MHz
h
5*bq
4*h
48320
19
11
13
11
ADSP-218x Benchmarks
Cycle Count
FIR Filter Tap
Biquad IIR Filter (4 coeff)
Complex FIR Filter
1024-Point Complex FFT Radix 4
256-Point Complex FFT Radix 4
Division
Sin/Cos
Arc Tangent
In/log10
Square Root
302
119
69
81
69
us
ns
ns
ns
ns
Execution Time @ 80 MHz
h
5*bq
4*h
37203
7423
19
25
13
11
23
465
93
238
313
163
138
288
us
us
ns
ns
ns
ns
ns
h = # of taps
bq = # of biquads
x = # of samples
BDTImark2000 Scores
TM
ADSP-21535
ADSP-219x
ADSP-218x
(300 MHz)
(160 MHz)
(80 MHz)
1690
420
240
The BDTImark2000 is a summary measure of DSP speed, distilled from a suite of DSP benchmarks (not shown) developed and independently verified
by Berkeley Design Technology, Inc. A higher BDTImark2000 score indicates a faster processor. For a complete description of the BDTImark2000 and
underlying benchmarking methodology, as well as additional scores, please visit http://www.bdti.com. BDTImark2000 (c) 2002 BDTI.
TM
TM
TM
TM
http://www.analog.com/dsp
DSP Selection Guide 23
SHARC® DSP Family Benchmarks
Just looking at the cycle time, clock speed,
MIPS or MFLOPS of a DSP cannot give an
accurate indication of the true performance of
the processor. Benchmarks are important in that
they show how a particular DSP performs in
the context of an application. The smaller the
benchmark number, the quicker the algorithm
execution. If a DSP can perform the task quicker, the processor can perform more tasks in a
given amount of time.
Benchmarks
Clock Speed
Instruction Cycle Time
MFLOPS Sustained, Peak
MOPS (32-bit Fixed-Point)
Sustained, Peak
1024-Point Complex FFT
(Radix 4, with Digit Reverse)
FIR Filter (per Tap)
IIR Filter (per Biquad)
Matrix Multiply
(3x3) x (3x1)
(4x4) x (4x1)
Divide (y/x)
Inverse Square Root
SHARC DSPs are the highest performance
32-bit DSPs available. These processors excel
at IEEE floating-point math, 32-bit fixed-point
math, and extended precision 40-bit floatingpoint math.
The ADI 32-bit DSP family offers a maximum
performance for minimum system cost, while
dramatically shortening product development
time and critical time-to-market.
ADSP-21065L
66 MHz
15 ns
132, 198 MFLOPS
132, 198 MFLOPS
ADSP-21161N
100 MHz
10 ns
400, 600 MFLOPS
400, 600 MFLOPS
0.27 ms (SISD)
0.09 ms*
5 ns*
20 ns*
15 ns
60 ns
135
240
90
135
45
80
60
90
ns
ns
ns
ns
ns*
ns*
ns*
ns*
1024-Point Complex FFT (in place)
32-BIT Floating-Point DSPs
DSP
Processor
TMS320C6701
TMS320C6711
TMS320C6712
ADSP-21065L
ADSP-21160N
ADSP-21161N
Instruction
Rate
167
150
100
66
95
100
MHz
MHz
MHz
MHz
MHz
MHz
Instruction
Cycle Time
6
6.7
10
15
11
10
ns
ns
ns
ns
ns
ns
Number
of Cycles
19, 875
19, 875
19, 875
18, 221
10,778*
10,778*
Total FFT
Time
0.12
0.13
0.19
0.27
0.10
0.09
* These benchmarks provide single channel extrapolation of measured dual channel processing performance.
Specification Source: TI, website www.ti.com
24 DSP Selection Guide
http://www.analog.com/dsp
ms
ms
ms
ms
ms
ms
DSP Part Numbering System
Core Voltage (v)
No designator
L
M
N
P
R
S
Package (p)
= 5V
= 3V
= 2.5V internal (3.3V I/O)
= 1.8V internal (3.3V I/O)
= 1.5V
= 1.2V
= 1.0V
Analog Devices
Digital Signal Processing
S = Plastic Quad Flat Pack (MQFP)
ST = Thin Quad Flat Pack (LQFP)
B = Plastic Ball Grid Array (PBGA)
Z = Ceramic QFP, Heat slug up
W = Ceramic QFP, Heat slug down
P = PLCC
G = PGA
X-Grade
BC, CA = Mini BGA
X = Pre-Production
No Suffix = Released
ADSP-21xxxvtpp-qqqX(R or REEL)
Tape and Reel
Product Number
Speed (q)
21xx = 16-Bit DSP
215xx = Blackfin DSP
2199x = Mixed Signal DSP
210xx and 211xx = SHARC DSP
TSxxx = TigerSHARC DSP
ADSP-219x, ADSP-2153x,
ADSP-2116x, TigerSHARC DSP
Speed Grade = Maximum frequency of operation
e.g.: -160 = 160 MHz
ADSP-218x, ADSP-2106x
Speed Grade = 4x maximum frequency of operation
e.g.:-160 = 40 MHz
Temperature (t)
J,K,L,M
A,B,C
S,T,U
W,Y,Z
= Commercial temp range*
= Industrial temp range*
= Military temp range*
= Automotive temp range*
* Please refer to individual data sheets
for specific range
Examples:
ADSP-21535PKB-300
ADSP-2191MKST-160X
ADSP-2189NKCA-320
ADSP-21161NKCA100X
http://www.analog.com/dsp
DSP Selection Guide 25
Blackfin DSP Family
TM
High Performance, Low Power Dual-MAC, 16-Bit Fixed-Point DSP
ADI’s new Blackfin DSP family is based on the
Micro Signal Architecture (MSA) jointly developed by ADI and the Intel Corporation. Blackfin
DSPs enable efficient processing of video, image,
and voice data by combining high-performance
signal processing functionality with the advantages of a RISC microcontroller instruction set.
This unified programming model eliminates the
complexities traditionally associated with multiprocessor systems consisting of individual signal
and control processing elements.
Highly Parallel Computational Blocks
Computational blocks within the architecture are
designed to maximize the number of math operations that can execute within the same cycle.
The heart of the Blackfin DSP architecture is the
Data Arithmetic Unit that includes two 16-bit
Multiplier Accumulators (MACs), two 40-bit
Arithmetic Logic Units (ALUs), four 8-bit video
ALUs, and a single 40-bit barrel shifter. Each
MAC can perform a 16-bit by 16-bit multiply on
four independent data operands every cycle. The
40-bit ALUs can accumulate either two 40-bit
results or four 16-bit results. With this architecture, 8-, 16- and 32-bit data word sizes can be
processed natively for maximum efficiency.
frame pointer, and stack pointer-- that can be
used as pointers for general indexing of variables and stack locations.
Hierarchical Memory
Blackfin DSPs support a hierarchical memory
model that expedites memory access to the core
for maximized throughput. The L1 memory is
connected directly to the core and operates at
full system clock speed. L2 memory, also operating at full system clock speed, is utilized for
accessing larger, bulk arrays of program and
data memory.
To provide for the performance needs of a DSP
and the programming ease of a RISC MCU, L1
memory can be configured as SRAM, cache, or
a combination of both. System designers can
map critical DSP data sets that require high
bandwidth and low latency into SRAM, while
maintaining the simple cache programming
model for microcontroller code.
The Memory Management Unit provides a
memory protection mechanism that, when coupled with the core’s User and Supervisor modes,
can support a full OS Kernel, a feature not typically found on general-purpose DSPs.
Address Arithmetic Unit
Flexible Addressing Capabilities
Blackfin DSPs provide efficient addressing of
data variables by supporting multiple addressing modes including indirect, auto-increment
and decrement, indexed, and bit reversed. Two
data address generators (DAG) provide
addresses for simultaneous dual operand fetches from memory. The DAGs share a register
file that contains four sets of 32-bit index,
modify, length, and base registers useful for
implementing multiple circular buffers in internal or external memory. There are also eight
additional 32-bit registers – P0 through P5,
SP
FP
P5
P4
P3
P2
P1
P0
I3
I2
I1
I0
L3
L2
L1
L0
B3
B2
B1
B0
M3
M2
M1
M0
DAG1
Sequencer
Align
Decode
Loop Buffer
R7
R6
R5
R4
R3
R2
R1
R0
8
Barrel
Shifter
16
8
40
Acc0
Data Arithmetic Unit
26 DSP Selection Guide
DAG0
http://www.analog.com/dsp
8
16
Control Unit
8
40
Acc1
Core
Processor
Blackfin DSP Family
TM
High Performance, Low Power Dual-MAC, 16-Bit Fixed-Point DSP
Dynamic Power Management
Blackfin DSP Dynamic Power Management permits system designers to dynamically vary both
the operating frequency and voltage of the DSP.
This capability enables the DSP power consumption characteristics to be optimized to the
individual algorithm being executed. Transitions
between various performance levels can be
implemented under user control resulting in significantly lower system power consumption and
longer battery life for handheld devices.
Superior Code Density
Blackfin DSPs provide excellent code density by
employing a variable length instruction encoding
scheme. The more frequently used instructions
such as data moves are encoded as compact 16bit words. The more challenging DSP and math
operations are encoded as 32-bit double words.
Additionally, a 64-bit multi-operation packet
consisting of one 32-bit and two 16-bit words
can be constructed for a variety of instruction
combinations. This merging of CISC and RISC
instruction encoding formats enables excellent
code density while retaining high system performance. Blackfin DSPs also support both 16-bit
General
Purpose
1 GHz
Ultra High
Performance
Broadband
ADSP-215xx
ADSP-21532
ADSP-21535
Video Instructions
Blackfin DSPs integrate quad 8-bit video ALUs
that facilitate the processing of arrays of 8-bit
data – the common word size of red-green-blue
pixel processing algorithms. The Blackfin DSP
instruction set architecture also includes specific
pixel manipulation instructions. These instructions enable the optimized execution of algorithms such as MPEG-2, MPEG-4, and JPEG
compression and decompression. Implementing
video algorithms in software allows OEMs to
adapt to evolving standards and new functional
requirements without hardware changes.
Roadmap to Maximum Performance
The current Blackfin DSP family combines performance of 300 MHz/600 MMACs with a
robust and complete set of peripherals. Future
product offerings will extend this performance
base to 1 GHz/2 GMACs with expanded peripheral functionality. Blackfin DSP technology will
also be leveraged to provide application specific
solutions for a variety of rapidly growing vertical market segments including
wired/wireless communications and digital imaging.
Media
Wireless Products
These complete solutions combine optimized hardware components with validated software components.
Ultra
Low Power
ADSP-215xx
300 MHz
and 32-bit external memory arrays with no
memory alignment restrictions.
3G
SoftFone
TM
Low Power
System Integration
http://www.analog.com/dsp
DSP Selection Guide 27
ADSP-21535 Blackfin DSP
TM
High Performance 16-Bit DSP for Networking & Digital Imaging
The new ADSP-21535 combines a high performance DSP, Dynamic Power Management, programming ease of use with a rich, powerful
peripheral set in order to be the central element
for a variety of application solutions with a
minimum of external components and cost.
Features
• High-performance 300 MHz/600 MMAC
dual-MAC DSP core
• 308 KBytes of On-Chip Memory
- 16 KBytes of L1 Program Memory
- 36 KBytes of L1 Data Memory
- 256 KBytes of Unified L2 Memory
• External Memory Controller with glueless
support for synchronous and asynchronous
memories
• Memory Management Unit providing memory protection
• 32-bit 33 MHz PCI V2.2 interface with both
master and slave functionality
• USB Device V1.1 controller supporting up to
8 endpoints
• Two full-duplex Synchronous Serial ports
(SPORTs)
• Three 32-bit timer/counters supporting PWM
output and pulse width/event count input
modes
• 12 channel peripheral and memory DMA controller capable of internal, external and PCI
transfers
• Two UARTs with auto-baud capability
(one supports IrDA® functionality)
• Two SPI-compatible ports
• 16 General Purpose I/O
• PLL capable of 1x to 31x frequency
multiplication
• Event controller
• Real-time clock
• Watchdog timer
• Debug/JTAG interface
• Commercial and industrial temperature range
• 260-Lead (19 mm x 19 mm) PBGA package
28 DSP Selection Guide
Benefits
• World’s first truly high-performance DSP
processor with integrated RISC MCU functionality and multimedia processing capabilities in a single instruction set
• Flexible Software Controlled Dynamic Power
Management
• Optimized compiler and architecture that supports development in High Level Languages
like C/C++ while also delivering comparable
code densities of traditional microcontrollers.
• Variety of architectural features that support
efficient use of a full RTOS to manage application tasks
Applications
• Automotive applications
• Broadband home gateways
• Central office/network switch
• Digital imaging and printing
• Global positioning systems
• Home networking/wireless LAN
• Industrial signal processing
• Internet appliances
• Internet audio
• Modem solutions
• Private Branch Exchanges (PBX)
• Telecommunications
• Video conferencing
• VoIP phone solutions
L1/L2
Memory
ADSP-21535PKB-300 52KB/256KB
ADSP-21535PKB-200 52KB/256KB
ADSP-21535PBB-200 52KB/256KB
Model
MHz Pin/Pkg
Price*
(1000)
300
200
200
$32.00
$30.00
$31.00
K = Commercial Temp ( 0ºC to +85ºC Case)
B = Industrial Temp ( -40ºC to +105ºC Case)
* All pricing is budgetary – subject to change
http://www.analog.com/dsp
260-PBGA
260-PBGA
260-PBGA
ADSP-21532 Blackfin DSP
TM
Low Cost, 16-Bit DSP for Consumer Multimedia
The ADSP-21532 is a low cost member of the
Blackfin DSP family. The ADSP-21532 integrates a variety of general purpose and application-tuned peripherals that minimize the overall
system IC count and bill of materials costs.
This system integration and enhanced peripheral set make the ADSP-21532 particularly well
suited for consumer multimedia and other cost
sensitive applications including video security
systems, video-enabled information appliances,
Internet audio and video, and home and car
entertainment.
Features
Benefits
• Flexible, software-controlled Dynamic Power
Management with on-chip voltage regulation
from 2.25V to 3.6V input supply
• Enhanced instructions to process audio,
image, and video data in multimedia applications
• Enhanced interfaces enabling glueless
connection to a variety of audio, video, and
multimedia data converters
• User definable ROM option reduces the
requirement for external components and
minimizes system bill of materials costs
• High-performance 300 MHz/600 MMAC dualApplications
MAC DSP core
• Automotive telematics
• 116 KBytes of on-chip L1 memory
• Biometrics
- 48 KBytes Program RAM
• Games and learning aids
- 32 KBytes Program ROM
- 36 KBytes Data RAM
• Home theatre
• External Memory Controller with glueless sup• Information appliances
port for synchronous and asynchronous mem• Internet audio
ories
• Set top boxes
• Memory Management Unit providing memory
• Video conferencing
protection
• Video security and surveillance
• Parallel Peripheral Interface supporting ITU-R
656 video data formats
L1
• Two dual-channel, full-duplex Synchronous
Memory MHz Pin/Pkg
Model
Serial Ports (SPORTs) supporting eight
ADSP-21532SBCA-300 116KB
300 160-MiniBGA
stereo I2S channels
• Three 32-bit timer/counters supporting
B = Industrial Temp ( -40ºC to +105ºC Case)
PWM output and pulse width/event count
* All pricing is budgetary – subject to change
input modes
• 12 channel peripheral and memory DMA
controller supporting one and
two-dimensional data transfers
• Three timer/counters supporting PWM and
pulse width/event count modes
• UART with support for IrDA®
• SPI-compatible port
• PLL capable of 1x to 31x frequency
multiplication
• Event handler
• Real-time clock
• Watchdog timer
• Debug/JTAG interface
• 160-lead (12 mm x 12 mm) Mini-BGA package
• Industrial temperature range
http://www.analog.com/dsp
Price*
(1000)
$11.50
DSP Selection Guide 29
ADSP-2100 Architecture
Providing over 15 Years of Code-Compatible DSP Excellence
The ADSP-2100 family architecture is built
around a common instruction set architecture
(ISA) which is optimized for signal processing.
All instructions are executed in a single clock
cycle, including multi-function instructions. The
architecture also features a high level algebraic
programming syntax.
In addition, ADSP-21xx processors operate on
24-bit instructions and 16-bit data. The wider
instruction word allows the device to use a more
complex and robust instruction set than a 16-bit
opcode. The 16-bit data word provides wide
dynamic range, while the narrower bus width
(16-bit as opposed to 32- or 64-bit wide) reduces
power consumption.
Processors are available with up to 2.4 Mbits of
SRAM around the DSP core to increase code
execution and overall system performance. All
ADSP-21xx processors integrate a programmable DMA controller to support maximum I/O
throughput and processor efficiency. The
ADSP-218x supports up to 4 Mbytes of external
memory while the ADSP-219x architecture
increases its address bus to 24-bits to support a
total of 16M words of external memory. The
ADSP-219x also balances a high performance
processor core with high performance buses
(PM, DM, DMA). It also provides two 40-bit
accumulators and a 40-bit shifter, which help
minimize data overflow during complex operations.
Addressing modes
ADSP-21xx processors also support immediate,
register-direct, memory-direct, and register-indirect addressing modes. The ADSP-219x adds
register, indirect-post-modify, immediate-modify, and direct- and indirect-offset addressing
modes. Each address generator supports as many
as four circular buffers, each with three registers.
The ADSP-219x supports as many as 16 circular
buffers using a DAG shadow register set and a
set of base registers for additional circularbuffering flexibility.
DSP Processor Core
ProgramSequencer
Inst
Register
DAG1
DAG2
Cache
Internal Memory
PM
Sequencer
DM
JTAG and
Emulation
PM Addr
DM Addr
PM Data
DM Data
24
24
24
16
Peripheral and
DMA Interface
Data Registers
ADSP-219x Core Enhanced Features
ALU
30 DSP Selection Guide
MAC
Shift
Compiler-efficient Data Register File
Up to 16M words of address range
Unified memory space
Instruction Cache
http://www.analog.com/dsp
ADSP-2100 Architecture
Providing over 15 Years of Code-Compatible DSP Excellence
Special Instructions
Compiler Friendly
The ADSP-2100 architecture contains dedicated
loop hardware and a “DO UNTIL” loop instruction that supports loops ranging from zero to 16K
iterations, or loops with infinite iterations. The
ADSP-218x supports up to four-deep nesting via
its loop hardware and the ADSP-219x supports
as many as eight. In addition to the standard
arithmetic and logic instructions, the ALU (arithmetic-logic unit) supports division primitives.
The ADSP-219x program sequencer features a
6-deep pipeline, and supports delayed branching.
The ADSP-219x buses and instruction cache
also provide rapid, unimpeded data flow to the
core to maintain the high execution rate.
Many of the enhancements to the ADSP-219x
architecture were made to improve compiler
efficiency. More flexible DAG addressing
modes, added secondary DAG register,
increased depth to stacks, and extended address
reach to 16M words drastically improves compiler code efficiency.
Performance
Code Compatible
ADSP-219x
300 MIPS
ADSP-219x
ADSP-219x
Platform
ADSP-218x
Platform
ADSP-218x
80 MIPS
ADSP-2185
80 MIPS
ADSP-2186
80 MIPS
ADSP-219x
Roadmap
ADSP-2191
160 MIPS
ADSP-2195
160 MIPS
ADSP-2196
160 MIPS
Higher Performance
ADSP-219x
High Performance
Low Cost
Performance Upgrade
Processor
Core
ADSP-219x
ADSP-218x
Low Power
Low Cost
Time
http://www.analog.com/dsp
DSP Selection Guide 31
ADSP-219x Family
160 MHz DSPs for Telephony and Signal Processing
The ADSP-219x series represent ADIs newest
generation of ADSP-2100 code-compatible,
fixed-point DSPs operating at 160 MHz. DSPs
in this series integrate a high level of system
interfaces to provide DSP developers with a
rapid upgrade path to higher performance and
lower system cost. The ADSP-219x DSP
peripheral set has been optimized for
Telephony applications by integrating three
multi-channel serial ports that support up to
128 TDM channels, a 16-bit parallel and 16-bit
host interface – this enables rapid deployment
of cost effective voice platforms. The DSPs
integrate up to 32K words of 24-bit program
memory RAM, 32K words of 16-bit data memory RAM, and 16K words of 24-bit ROM. The
ADSP-2191, ADSP-2195, and ADSP-2196 are
all pin-compatible allowing many possibilities
for system upgrades. Pin-to-pin compatibility
allows programmers to migrate to larger memory models to increase end-product functionality without hardware redesign.
Features
• 160 MHz / MIPs 16-bit performance
• Up to 64K words on-chip SRAM
• 16K words on-chip ROM
• Boot ROM
• 16-bit external memory interface
• Host port interface (8- or 16-bit)
• Three full duplex multi channel
TDM serial ports
• Two SPI interfaces
• One UART
• Three general purpose timers with
PWM and input capture modes
• 16 general purpose I/O pins
• 11 DMA channels
• On-chip PLL with 1x to 32x
input frequency multiplication
• IEEE JTAG 1149.1 test access port
• 2.5 volt supply with 3.3 volt I/O
• 144-Lead LQFP, 144-Lead mini-BGA
32 DSP Selection Guide
Benefits
• Programmable PLL with oscillator enables
full speed operation from low-speed input
clocks or crystals
• User selectable power-down modes reduces
system power consumption
• On-chip ROM with application specific user
code lowers cost in high volume systems
• Up to 11 DMA channels operate in parallel
maximizes I/O throughput
• Efficient C/C++ compiler simplifies software
programming task
Applications
• Telephony
• Modems
• Private Branch Exchange (PBX)
• Voice over network
• Home gateways
• Integrated access devices
• Optical networking
• Data acquisition
• Industrial automation
ADSP-2191MKST-160
ADSP-2191MBST-140
ADSP-2191MKCA-160
ADSP-2191MBCA-140
DM
RAM
32K
32K
32K
32K
PM
RAM
32K
32K
32K
32K
PM
ROM
–
–
–
–
ADSP-2195MKST-160
ADSP-2195MBST-140
ADSP-2195MKCA-160
ADSP-2195MBCA-140
16K
16K
16K
16K
16K
16K
16K
16K
ADSP-2196MKST-160
ADSP-2196MBST-140
ADSP-2196MKCA-160
ADSP-2196MBCA-140
8K
8K
8K
8K
8K
8K
8K
8K
Model
160
140
160
140
Price*
(1000)
144-LQFP $16.85
144-LQFP $16.85
144-MBGA $16.85
144-MBGA $16.85
16K
16K
16K
16K
160
140
160
140
144-LQFP
144-LQFP
144-MBGA
144-MBGA
$13.90
$13.90
$13.90
$13.90
16K
16K
16K
16K
160
140
160
140
144-LQFP
144-LQFP
144-MBGA
144-MBGA
$11.10
$11.10
$11.10
$11.10
MHz Pin/Pkg
M indicates 2.5 volt operation
K = Commercial Temp ( 0ºC to +70ºC ambient)
B = Industrial Temp ( -40ºC to +85ºC ambient)
* All pricing is budgetary – subject to change
http://www.analog.com/dsp
ADSP-218x M and N Series
16-Bit Fixed-Point Digital Signal Processors
The ADSP-218x M and N series members offer
low power (1.8V), low cost, and high performance 16-bit DSPs. All series members are pin
and code compatible and are differentiated solely
by the amount of on-chip SRAM. These feature
combined with ADSP-21xx code compatibility
provide a great deal of flexibility in the design
decision.
Features
• .3mA/[email protected] 1.8V core supply1
• 12.5 ns instruction cycle time (80 MIPS)2
• Up to 48K words program RAM and 56K
words data words on chip
• I/O voltage support to 3.3V
• 16-bit bit internal DMA port
• 8 bit memory DMA
• Two double buffered serial ports (1 with
TDM mode)
• I/O memory interface with 2048 locations
• 100-lead LQFP, 144-lead mini-BGA
Model
PM/DM MHz Pin/Pkg
ADSP-2188NBST-320
ADSP-2188NBCA-320
ADSP-2189NBST-320
ADSP-2189NBCA-320
ADSP-2187NBST-320
ADSP-2187NBCA-320
ADSP-2185NBST-320
ADSP-2185NBCA-320
ADSP-2186NBST-320
ADSP-2186NBCA-320
ADSP-2184NBST-320
ADSP-2184NBCA-320
48K/56K
48K/56K
32K/48K
32K/48K
32K/32K
32K/32K
16K/16K
16K/16K
8K/8K
8K/8K
4K/4K
4K/4K
80
80
80
80
80
80
80
80
80
80
80
80
128-LQFP
144-MBGA
128-LQFP
144-MBGA
128-LQFP
144-MBGA
128-LQFP
144-MBGA
128-LQFP
144-MBGA
128-LQFP
144-MBGA
Price*
(1000)
$26.00
$28.00
$21.00
$23.00
$17.00
$19.00
$9.50
$12.00
$7.25
$9.25
$5.75
$7.75
ADSP-2188MBST-266
ADSP-2188MBCA-266
ADSP-2189MBST-266
ADSP-2189MBCA-266
ADSP-2185MBST-266
ADSP-2185MBCA-266
ADSP-2186MBST-266
ADSP-2186MBCA-266
48K/56K
48K/56K
32K/48K
32K/48K
16K/16K
16K/16K
8K/8K
8K/8K
75
75
75
75
75
75
75
75
128-LQFP
144-MBGA
128-LQFP
144-MBGA
128-LQFP
144-MBGA
128-LQFP
144-MBGA
$28.00
$30.00
$23.00
$25.00
$10.00
$12.00
$7.50
$9.50
ADSP-2188NKST-320
ADSP-2188NKCA-320
ADSP-2189NKST-320
ADSP-2189NKCA-320
ADSP-2187NKST-320
ADSP-2187NKCA-320
ADSP-2185NKST-320
ADSP-2185NKCA-320
ADSP-2186NKST-320
ADSP-2186NKCA-320
ADSP-2184NKST-320
ADSP-2184NKCA-320
48K/56K
48K/56K
32K/48K
32K/48K
32K/32K
32K/32K
16K/16K
16K/16K
8K/8K
8K/8K
4K/4K
4K/4K
80
80
80
80
80
80
80
80
80
80
80
80
128-LQFP
144-MBGA
128-LQFP
144-MBGA
128-LQFP
144-MBGA
128-LQFP
144-MBGA
128-LQFP
144-MBGA
128-LQFP
144-MBGA
$26.00
$28.00
$21.00
$23.00
$17.00
$19.00
$9.50
$12.00
$7.25
$9.25
$5.75
$7.75
ADSP-2188MKST-300
ADSP-2188MKCA-300
ADSP-2189MKST-300
ADSP-2189MKCA-300
ADSP-2185MKST-300
ADSP-2185MKCA-300
ADSP-2186MKST-300
ADSP-2186MKCA-300
48K/56K
48K/56K
32K/48K
32K/48K
16K/16K
16K/16K
8K/8K
8K/8K
75
75
75
75
75
75
75
75
128-LQFP
144-MBGA
128-LQFP
144-MBGA
128-LQFP
144-MBGA
128-LQFP
144-MBGA
$28.00
$30.00
$23.00
$25.00
$10.00
$11.50
$7.50
$9.50
Benefits
• Simple algebraic assembly language reduces
development time and time to market
• Pin compatible packages mitigates product
developments risks
• 16-bit bit DMA port makes bus interfacing
easier
• Code compatible with all 21xx derivatives
ensures reuse of legacy code
• Large on chip memory eliminates the need for
expensive SRAM
• 144-ball mini-BGA package provides for
maximum space savings (10 mm x 10 mm)
Applications
• Consumer telephony
• Embedded speech processing
• POS terminals
• PBX
• Smart card readers
• Multi channel voice processing
• Industrial measurement control
1
2
.5mA/Mip, 75 MIPS on ‘M’ series
13 ns on ‘M’ series
N indicates 1.8 volt operation
M indicates 2.5 volt operation
B = Industrial Temp ( -40ºC to +85ºC ambient)
K = Commercial Temp ( 0ºC to +70ºC ambient)
* All pricing is budgetary – subject to change
http://www.analog.com/dsp
DSP Selection Guide 33
16-Bit DSP Competitor Cross Reference Guide
Competition
Device
Part Number
MMACS
RAM
(Kwords)
Operating
Voltage
(Core, I/O)
Smallest
Package
ADI Suggested
Functional
Competitive Device
Texas Instruments C54X Family
TMS320VC5441
TMS320VC5421
TMS320VC5420
532
200
200
640
256
200
1.6V/3.3V
1.8V/3.3V
1.8V, 3.3V
179BGA
144BGA
144BGA
TMS320VC5416
160
128
1.5V,3.3V
144BGA
TMS320VC5410A
TMS320VC5409A
TMS320VC5402A
TMS320VC5407
TMS320VC5404
TMS320UC5409
TMS320UC5402
TMS320VC5401
160
160
160
120
120
80
80
50
64
32
16
40
16
32
16
8
1.6V/3.3V
1.6V/3.3V
1.6V/3.3V
1.5V/3.3V
1.5V/3.3V
1.8V - 3.6V
1.8V - 3.6V
1.8V/3.3V
144BGA
144BGA
144BGA
144BGA
144BGA
144BGA
144BGA
144BGA
ADSP-21535P
ADSP-21535P
ADSP-21535P
ADSP-2191M
ADSP-2191M
ADSP-2188N
ADSP-2191M
ADSP-2195M
ADSP-2196M
ADSP-2195M
ADSP-2196M
ADSP-2185N
ADSP-2186N
ADSP-2184N
160
128
32
1.6V/3.3V
1.5V/3.3V
1.5V/3.3V
240BGA
176BGA
176BGA
ADSP-21535P
ADSP-21535P
ADSP-21532S
600
500
400
400
400
334
448
192
64
64
64
36
1.2V/3.3V
1.5V/3.3V
1.8V/3.3V
1.5V/3.3V
1.5V/3.3V
1.8V/3.3V
352BGA
352BGA
352BGA
288BGA
288BGA
384BGA
ADSP-21535P
ADSP-21535P
ADSP-21532S
ADSP-21532S
ADSP-21532S
ADSP-21532S
600
600
160
160
160
80
80
80
80
80
80
75
75
75
75
154
58
64
32
16
104
80
64
32
16
8
104
80
32
16
1.5V/3.3V
2.25 - 3.6V*
2.5/3.3V
2.5/3.3V
2.5/3.3V
1.8V,2.5-3.6V
1.8V,2.5-3.6V
1.8V,2.5-3.6V
1.8V,2.5-3.6V
1.8V,2.5-3.6V
1.8V,2.5-3.6V
2.5V, 2.5V-3.3V
2.5V, 2.5V-3.3V
2.5V, 2.5V-3.3V
2.5V, 2.5V-3.3V
260BGA
160BGA
144BGA
144BGA
144BGA
144BGA
144BGA
144BGA
144BGA
144BGA
144BGA
144BGA
144BGA
144BGA
144BGA
Texas Instruments C55X Family
TMS320VC5510
TMS320VC5509
TMS320VC5502
400
400
400
Texas Instruments C62X Family
TMS320C6203C
TMS320C6202B
TMS320C6201
TMS320C6204
TMS320C6205
TMS320C6211B
Analog Devices
ADSP-21535P
ADSP-21532S
ADSP-2191M
ADSP-2195M
ADSP-2196M
ADSP-2188N
ADSP-2189N
ADSP-2187N
ADSP-2185N
ADSP-2186N
ADSP-2184N
ADSP-2188M
ADSP-2189M
ADSP-2185M
ADSP-2186M
* External voltage range -- Core voltage regulation on-chip
34 DSP Selection Guide
http://www.analog.com/dsp
SHARC® DSP Family
Real-Time, Multiprocessing Leader
The Analog Devices SHARC® DSP family features a "super" Harvard architecture optimized
to enable a variety of real-time embedded
applications. These 32-bit DSPs allow users to
program with equal efficiency in both fixedpoint and floating-point arithmetic. The unique
memory architecture – two large on-chip, dualported SRAM blocks coupled with the sophisticated I/O processor – gives the SHARC DSPs
the bandwidth for sustained high-speed computations for real-time embedded DSP development.
Code-compatibility helps to keep development
time at a minimum, and maximize our customers' software investments.
architecture is optimized for computationally
demanding and multiprocessor applications.
SHARC DSPs are the leader in multiprocessing
applications. Patented link port technology has
helped establish SHARC as a de facto standard.
Applications
• Prosumer audio
• 3D graphics
• Arcade games
• Imaging
• Video conferencing
• Medical imaging
• Radar and sonar guidance
• Audio equipment
• Call processing
• Speech recognition
• Cellular base stations
• Instrumentation
SHARC Roadmap
Commitment to Code Compatibility into Tomorrow
The original Single-Instruction, Single-Data
(SISD) SHARC DSPs feature a broad range of
memory sizes and price points. For very high
performance applications, ADI has extended
the architecture to a code-compatible, SingleInstruction, Multiple-Data (SIMD) platform.
570 MFLOPS
4 Mbits
Integrated MP
250-500 MHz
6 Mbits
New MP support
or
ADSP-21160
ss
MFLOPS
ul
tip
ro
ce
Market focused
SHARC
t
arke
M
The next generation TigerSHARC 128-bit DSP
combines multiple computation units for floating-point and fixed-point processing, as well as
very wide word widths, by using a MultipleInstruction, Multiple Data (MIMD) platform.
Its ultra-high-performance static superscaler
Tiger
SHARC
ADSP-2106x
M
Lo
w
120-198 MFLOPS
.5-4 Mbits memory
d
use
Foc
Co
st
600 MFLOPS
1 Mbit
ADSP-21161
Higher performance
New peripherals
Target at vertical markets
Low Cost
SHARC
1200 MFLOPs
From $5
Price performance
Time/Process
32-BIT
Generic
ADSP-21160N
ADSP-21160M
ADSP-21161N
ADSP-21065L
ADSP-21062/L
ADSP-21061/L
ADSP-21060/L
ADSP-TS101S
Package
Max MIPS
Vcc
B
B
CA
S, CA
B,S
S
B,S
B
95
80
100
66
40
50
40
250
1.9/3.3V
2.5/3.3V
1.8/3.3V
3.3V
3.3/5V
3.3/5V
3.3/5V
1.2/3.3V
Package: B = Plastic Ball Grid Array (PBGA)
G = Ceramic Pin Grid Array (PGA)
On-Chip
SRAM
4
4
1
544
2
1
4
6
Mbits
Mbits
Mbit
Kbits
Mbits
Mbit
Mbits
Mbits
Serial
Ports
Price*
(1000)
2
2
2
2
2
2
2
0
$145.00
$145.00
$24.63
$19.50
$100.00
$37.43
$249.29
$207.00
S = Plastic Quad Flat Pack (PQFP)
CA = Mini Ball Grid Array (MBGA)
* US Dollars. Lowest grade suggested resale price per unit in 1000 unit quantities
All pricing is budgetary - subject to change
DSP Selection Guide 35
ADSP-TS101
Next Generation SHARC® DSP
The ADSP-TS101 is the newest member of the
high performing SHARC® DSP family.
Operating at 250 MHz, TigerSHARC DSP
offers best-in-class floating-point performance
at a minimum power consumption. The
TigerSHARC DSP supports arithmetic for 8-,
16-, and 32-bit data, and contains 6 Mbit onchip SRAM internally organized in three banks
with user-defined partitioning. Three internal
128-bit wide internal buses provide a total
memory bandwidth of 8.64 Gbytes per second.
Applications
• Medical, CT, ultrasound
• Sonar systems
• Echo and noise cancellation systems
• Flight simulator
• Infrastructure equipment
• Military smart munitions
• Test equipment
• Imaging, printers, video
Features
Model
• 2 billion 16-bit MACs-per-second
• 550 MFLOP/watt – industry best
• 1.2 volt supply with 3.3 volt I/O
• 4.0 ns instruction cycle time at 250 MHz
• Eight 16-bit MACs/cycle with 40-bit
accumulation
• Two 32-bit MACs/cycle with 80-bit
accumulation
• 6 Mbit on-chip SRAM
• IEEE floating-point compatible
• 14 DMA channels
• 4 Link ports – 1 GByte/sec transfer rate, aggregate
• 32/64-bit external port – 800 MBytes/sec
PROGRAM SEQUENCER
• 128 general purpose registers
• Optimizing C/C++ compiler
• Glueless multiprocessing
• 19 x 19 mm or 27 x 27 mm PBGA
PC
BTB
IRQ
ADDR
FETCH
IAB
MHz
ADSP-TS101SKB1250X
ADSP-TS101SKB2250X
250
250
Pkg
27 x 27 mm PBGA
19 x 19 mm PBGA
K = Commercial Temp (-40ºC to +85ºC case)
Development Tools
ADDS-TS101S-EZLITE
VDSP-TS-PC-FULL
VDSP-TS-PCFLOAT
ADDS-APEX-ICE
ADDS-SUMMIT-ICE
Evaluation Kit
VisualDSP++
VisualDSP++ Floating License
USB-Based Emulator
PCI-Based Emulator
DATA ADDRESS GENERATION
32
INTERNAL MEMORY
32
INTEGER
J ALU
INTEGER
K ALU
32 x32
32 x32
MEMORY
M0
64 x 32
A
D
MEMORY
M1
64 x 32
A
D
MEMORY
M2
64 x 32
A
D
6
JTAG
PORT
SDRAM
CONTROLLER
EXTERNAL PORT
Benefits
32
• Flexible development environment
that supports both algebraic
assembly language and C/C++
• Large on-chip RAM makes
reprogramming easy
• 4 Link ports enable direct
chip-to-chip connections
without the need for complex
external circuitry
• VisualDSP++ tools support
provides same software interface
as other ADI DSPs
• Multiple-instruction, multiple-data
(MIMD) instructions
• Fully interruptible with full
computation performance
36 DSP Selection Guide
MULTIPROCESSOR
INTERFACE
M0 ADDR
128
M0 DATA
HOST
INTERFACE
32
M1 ADDR
128
INPUT
FIFO
M1 DATA
32
32
ADDRESS
64
M2 ADDR
128
OUTPUT
BUFFER
DATA
M2 DATA
32
I/O
ADDRESS
32
128
DAB
128
DAB
128
DMA
ADDRESS
128
DMA
DATA
LINK
DATA
CNTRL
OUTPUT
FIFO
CLUSTER
BUS
ARBITER
3
X
REGISTER
FILE
32 x 32
Y
REGISTER
FILE
32 x 32
MULTIPLIER
MULTIPLIER
ALU
ALU
SHIFTER
SHIFTER
L0
DMA
CONTROLLER
LINK PORT
CONTROLLER
8
3
L1
8
3
PROCESSING ELEMENTS
http://www.analog.com/dsp
CONTROL/
STATUS/
TCBs
CONTROL/
STATUS/
BUFFERS
L2
8
3
L3
I/O PROCESSOR
8
LINK PORTS
ADSP-21161N
Low-Cost, Single-Instruction, Multiple-Data (SIMD) SHARC®
• 3.3 Volt external/1.8 volt internal
• 1 Mbit on-chip SRAM
• 14 zero-overhead DMA channels
• SPI-compatible port for serial host and
peripheral control
• 4 SPORTs supporting 128 channel TDM and I2S
• 12 general purpose I/O lines, 4 IRQ lines,1 timer
• Code-compatible to all other SHARC family DSPs
• Single-Instruction, Multiple-Data (SIMD)
computational architecture – two 32-bit IEEE
floating-point computation units, each with a
multiplier, ALU, shifter, and register file
• 100 MHz (10 ns) core instruction rate
600 MFLOPS peak and 400 MFLOPs sustained
performance
• Dual Data Address Generators (DAGs) with
modulo and bit-reverse addressing
• Zero-overhead looping with single-cycle loop
setup, providing efficient program sequencing
• IEEE 1149.1 JTAG standard test access port
and on-chip emulation
• 225-ball 17 mm x 17 mm PBGA package
Price*
Model
MHz Pin/Pkg
ADSP-21161NKCA-100 100
ADSP-21161NCCA-100 100
(1000)
225-MBGA $24.63
225-MBGA $29.55
N indicates 1.8 volt operation
K = Commercial Temp ( 0ºC to +85ºC case)
C = Industrial Temp ( -40ºC to +105ºC case)
* All pricing is budgetary – subject to change
• Two 100 Mbyte/S link ports simplify connection and communication in multiprocessing
systems
• 14 zero-overhead DMA channels mean no
cycles stolen from the core to move data on
and off chip
• Cluster multiprocessing enables universally
addressable memory system
• SDRAM controller for controlling large banks
of DRAM
• 4 serial ports allow for 16 channels of data to
be transferred in/out of the DSP
Applications
• High-end consumer audio
• Professional audio
• Automatic car systems
• Finger print recognition
• Medical equipment
• ADSL/cable test equipment
• Multi access motor control
• Voice recognition
• Global positioning
• Power line modems
• Telephony
• MP3 encoder
• Video phones
• Digital broadcast radio
Core Processor
DAG1
8 x 4 x 32
JTAG
Test and
Emulation
Dual-Ported SRAM
Timer
DAG2
8x4x
Instruction
Cache
32 x 48-Bit
Block 0
Features
Benefits
Two Independent
Dual-Ported Blocks
Processor Port
Data
Addr
Addr
Data
I/O Port
Data
Addr
Data
Addr
IOD
64
IOA
32
Block 1
The ADSP-21161N is the newest member of
the high performing SIMD SHARC DSP family. This device offers the industry’s highest
32-bit DSP performance at a price that will
support consumer applications.
GPIO
Flags
SDRAM
Controller
Program
Sequencer
PM Address Bus
32
DM Address Bus
32
PM Data Bus
64
DM Data Bus
64
6
12
8
External Port
Address
Bus
Mux
24
Multiprocessor
Interface
Development Tools
ADDS-2116X-WKSHP
ADDS-21161N-EZLITE
VDSP-SHARC-PC-FULL
VDSP-SHARC-PCFLOAT
ADDS-APEX-ICE
ADDS-SUMMIT-ICE
Bus
Connect
(PX)
DSP Workshop
Evaluation Kit
VisualDSP++
VisualDSP++ Floating License
USB-Based Emulator
PCI-Based Emulator
Data
Bus
Mux
32
Host Port
Mult
Data
Register
File
(PEx)
16 x 40-Bit
Barrel
Shifter
Barrel
Shifter
Data
Register
File
(PEy)
16 x 40-Bit
Mult
DMA
Controller
IOP
Registers
(Memory
Mapped)
Serial Ports
(4)
Control,
Status, and
Data Buffers
ALU
http://www.analog.com/dsp
ALU
Link Ports
(2)
SPI Ports
(1)
5
16
20
4
I/O Processor
DSP Selection Guide 37
ADSP-21160
Single-Instruction, Multiple-Data (SIMD) SHARC®
Applications
38 DSP Selection Guide
• Cellular base stations
• Call processing
• Speech recognition
• Instrumentation
• 3D graphics acceleration for workstations
and arcade video games
• Imaging
• High-end audio
• Radar and sonar
Model
MHz
Price*
(1000)
Pin/Pkg
ADSP-21160MKB-80 80
400-PBGA $145.00
ADSP-21160NKB-95 95
400-PBGA $145.00
M indicates 2.5V operation
N indicates 1.9V operation
K = Commercial Temp (0ºC to +85ºC case)
* All pricing is budgetary – subject to change
Development Tools
ADDS-2116X-WKSHP
ADDS-21160-EZLITE
ADDS-21160N-EZLITE
VDSP-SHARC-PC-FULL
VDSP-SHARC-PCFLOAT
ADDS-APEX-ICE
ADDS-SUMMIT-ICE
DSP Workshop
Evaluation Kit for “M”
Evaluation Kit for “N”
VisualDSP++
VisualDSP++ Floating License
USB-Based Emulator
PCI-Based Emulator
Core Processor
Dual-Ported SRAM
Timer
DAG1
8 x 4 x 32
DAG2
8 x 4 x 32
Instruction
Cache
32 x 48-Bit
Block 0
• 540 MFLOPS (32-bit floating-point) peak
operation
• 540 MOPS (32-bit fixed-point) peak operation
• 90 MHz core operation, 11 ns cycle time
• 92 µs 1024-point comlex FFT benchmark
with bit reversal
• Code compatible with first generation
SHARC
• SIMD core includes 2 multipliers, 2 ALUs,
2 shifters, and 2 register files
• 4 Mbits on-chip dual-ported SRAM
• Division of SRAM between program and
data memory is selectable
• Core can fetch four 32-bit words from memory in a single processor cycle using two
64-bit wide buses
• Dual data address generators with modulo
and bit-reverse addressing
• Efficient program sequencing with zero-overhead looping—single-cycle loop setup
• IEEE JTAG standard 1149.1 test access port
and on-chip emulation
• 32-bit single-precision IEEE floating-point
data type and 40-bit extended precision
floating-point data type support
• 32-bit fixed-point formats, integer and fractional, with 80-bit accumulators in both processing elements
• 14 channels of zero-overhead DMA
• Glueless connection for scaleable DSP
multiprocessing architectures
• Distributed on-chip bus arbitration for parallel
bus connect of up to six ADSP-21160s plus
host
• Six 100 Mbytes/sec link ports for point-topoint connectivity and array multi-processing
• 2.5 volt core, 3.3 volt I/O (80 MHz
ADSP-21160M)
• 1.9 volt core, 3.3 volt I/O (95 MHz
ADSP-21160N)
Two Independent
Dual-Ported Blocks
Processor Port
Addr
Data
Addr
Data
Data
I/O Port
Addr
Data
Addr
Block 1
Features
7
JTAG
Test and
Emulation
Program
Sequencer
PM Address Bus
32
DM Address Bus
32
PM Data Bus
32/48/64
DM Data Bus
32/40/64
IOD
64
IOA
32
External Port
32
Address
Mux
Bus
Multiprocessor
Interface
Bus
Connect
(PX)
64
Data
Mux
Bus
Host Port
Mult
http://www.analog.com/dsp
Data
Register
File
(PEx)
16 x 40-Bit
Barrel
Shifter
Barrel
Shifter
Data
Register
File
(PEy)
16 x 40-Bit
Mult
IOP
Registers
(Memory
Mapped)
Control,
Status, and
Data Buffers
ALU
ALU
DMA
Controller
4
6
Serial Ports
(2)
Link Ports
(6)
I/O Processor
6
60
ADSP-21160 vs. TMS320C6x
Comparison
Features
TMS320C62x
TMS320C67x
ADSP-21160 SHARC
IEEE 32-bit floating-point support
Native 32-bit fixed-point support
Dual-ported internal memory
Built-in multiprocessing support
Number of DMA channels
Zero-overhead DMA support1
Number of registers
Accumulator size
64-bit product support
Memory bandwidth2
Software loop support
No
No
No
No
4
No
32
40 bits
No
64 bits/cycle
No interrupts for
compact loops
Highly complex
Yes
No
No
No
4
No
32
40 bits
Yes
128 bits/cycle
No interrupts for
compact loops
Highly complex
8
Requires extra
register
100 instructions
35mm, 352 ball
8
Requires extra
register
100 instructions
35mm, 352 ball
Yes
Yes
Yes
Cluster and link
14
Yes
128
80 bits
Yes
128 bits/cycle
Interrupts allowed
in compact loops
Algebraic assembly
language
32
Dedicated conditional
logic
25 instructions
27mm, 400 ball
Assembly complexity3
Number of circular buffers supported4
Conditional execution support
FIR filter code size5
Package size
1
2
3
4
5
The TMS320C6x does DMA by stealing cycles from the core.
“Memory bandwidth” refers to the data path widths between the register file and memory.
Hand-optimized TMS320C6x assembly language must be written in a highly-complex, non-single assignment form.
The TMS320C6x only allows two different lengths of circular buffers and the lengths must be power of two.
TMS32062xx Programmer’s Guide page 4-112.
http://www.analog.com/dsp
DSP Selection Guide 39
ADSP-21065L
Low-Cost Entry-Point to the SHARC® DSP Family
Features
Applications
• 16K 32-bit dual-ported on-chip memory
(544 KBits configurable)
• 64M x 32-bit word external address space
• 198 MFLOPS (32-bit floating-point)
• 198 MOPS (32-bit fixed-point)
• Glueless SDRAM interface
• 2 serial transmit/receive ports support
32-channel TDM
• I2S mode supports up to 16 channels
• 2 timers with event capture and PWM options
• 12 programmable I/O pins
• 10 DMA channels
• Glueless multiprocessing with 2
ADSP-21065L’s
• Code compatible with all SHARC family
members
• 3.3 volt, 208-pin MQFP, 196 MBGA
• Digital audio
• Keyless entry using voice
analysis/recognition
• Bar code scanners
• Imaging
• Ultrasound equipment
• Digital oscilloscopes
• Fingerprint recognition
Price*
Model
MHz Pin/Pkg (1000)
ADSP-21065LKS-240* 60 208-MQFP $19.50
ADSP-21065LKS-264 66 208-MQFP $37.50
ADSP-21065LKCA-240 60 196-MBGA $38.00
ADSP-21065LKCA-264 66 196-MBGA $39.50
ADSP-21065LCS-240
60 208-MQFP $37.50
L Indicates 3.3 Volt Operation
K = Commercial Temp (0ºC to +85ºC case)
C = Industrial Temp (-40ºC to +100ºC case)
*All pricing is budgetary – subject to change
Development Tools
ADDS-2106X-WKSHP
ADDS-21065L-EZLITE
VDSP-SHARC-PC-FULL
VDSP-SHARC-PCFLOAT
ADDS-APEX-ICE
ADDS-SUMMIT-ICE
Dual-Ported SRAM
Instruction
Cache
32 x 48-Bit
Two Independent
Dual-Ported Blocks
Processor Port
Addr
Data
Addr
DAG1
8 x 4 x 32
DAG2
8 x 4 x 32
Bus
Connect
(PX)
I/O Port
Addr
Data
Addr
PM Address Bus
24
DM Address Bus
32
PM Data Bus
48
DM Data Bus
40
16 x 40-Bit
Barrel
Shifter
IOD
48
IOP
Registers
(Memory
Mapped)
ALU
Control,
Status, and
Data Buffers
IOA
17
DMA
Controller
SPORT 0
SPORT 1
I/O Processor
40 DSP Selection Guide
7
External Port
SDRAM Interface
Multiprocessor
Interface
Program
Sequencer
Data
Register
File
Multiplier
Data
Data
JTAG
Test and
Emulation
Block 1
Timer 1 Timer 2
Block 0
Core Processor
DSP Workshop
Evaluation Kit
VisualDSP++
VisualDSP++ Floating License
USB-Based Emulator
PCI-Based Emulator
http://www.analog.com/dsp
Host Port
Address
Mux
Bus
24
Data
Mux
Bus
32
4
(2 Rx, 2 Tx)
I2S
(2 Rx, 2 Tx)
I2S
ADSP-2199x Family
Mixed Signal DSPs
The ADSP-2199x family of mixed-signal DSPs
provides a single-chip high-performance solution with signal processing and mixed-signal
integration for both current and future embedded control and signal processing applications.
These products combine the ADSP-219x codecompatible DSP core, multichannel, high-resolution analog/ digital conversion, the right mix
of embedded control peripherals, and comprehensive development tools. A variety of memory sizes address emerging market requirements
with power efficient and high-performance
solutions.
tools and statistical profiling to quickly identify
bottlenecks and reduce development time. The
tools suite also includes a low-cost EZ-KIT
Lite™ evaluation platform. The EZ-KIT Lite
can also be extended with JTAG In-circuit
Emulation (ICE) for full control of software
debugging. PCI and USB versions are of the
emulator available.
Development Tools
ADDS-21990-EZLITE
VDSP-21XX-PC-FULL
VDSP-21XX-PCFLOAT
ADDS-APEX-ICE
ADDS-SUMMIT-ICE
Evaluation Kit
VisualDSP++
VisualDSP++ Floating License
USB-Based Emulator
PCI-Based Emulator
Development Tools
All ADSP-219x products, including the ADSP2199x series are supported by ADI’s CROSSCORE™ software and hardware development
tools. The development tools suite includes the
VisualDSP++™ integrated software development environment with the C/C++ compiler,
VisualDSP++ Kernel (VDK), advanced plotting
Embedded Control applications support can be
obtained at [email protected] Users can
also obtain additional support, free software
upgrades, and sample code by visiting the
Motor Control Web site at
www.analog.com/motorcontrol
Program
Max MIPS RAM Words
Data
RAM Words
Device
ADSP-21990
Package
ST, BC
160
4K
4K
ADSP-21991
ST, BC
160
32K
8K
ADC
Status
14-Bit
20 MSPS
14-Bit
20 MSPS
Samples Now
Release 2Q02
Samples 3Q02
Release 4Q02
Packages: ST = Thin Quad Flat Pack (LQFP)
BC = Mini Ball Grid Array (10 x 10 mm)
http://www.analog.com/motorcontrol
DSP Selection Guide 41
ADSP-21990
Mixed Signal DSP
Features
Benefits
• 160 MHz, ADSP-219x DSP core
• 8-Channel, 14-Bit, 20 MSPS ADC
• On-chip voltage reference and power-on-reset
• 4K words program memory RAM
• 4K words data memory RAM
• External memory interface (to 1M Word)
• Embedded Control Peripherals
– Three-phase PWM generation unit
– Incremental encoder interface unit
– Dual auxiliary PWM outputs
– Watchdog timer
– Three 32-Bit, general purpose timers
– 16-Bit general purpose flag I/O port
– Peripheral interrupt controller
– Synchronous serial (SPORT) and SPI
– Communications ports
• ADSP-219x core delivers highest performance
mixed-signal DSP for control designs with up to
160 MIPS sustained performance
• Code compatible solution ensures investment
protection with lower software cost
• State-of-the-art development tools
• Integrated single-chip pin-compatible
solutions facilitate high-performance design
with higher reliability, reduces development
time with lower overall system cost
• External memory interface provides direct
access from DSP to external memory
for data or instruction
• Fabricated in high-speed, low power consumption, CMOS process
Development Tools
Applications
• Industrial motor drives
• Un-interruptible power supplies
• Optical networking control
• Data acquisition systems
• Test and measurement systems
• Portable
Instrumentation
• Intelligent sensors
• Robotic control
JTAG
Test and
Emulation
ADDS-21990-EZLITE
VDSP-21XX-PC-FULL
VDSP-21XX-PCFLOAT
ADDS-APEX-ICE
ADDS-SUMMIT-ICE
Evaluation Kit
VisualDSP++
VisualDSP++ Floating License
USB-Based Emulator
PCI-Based Emulator
Clock Gen/PLL
160 MHz
ADSP-219x
DSP
To
32k x 24
PM RAM
To
8k x 16
DM RAM
4k x 24
PM ROM
Address
External
Memory
Interface
(EMI)
Bus
Data
Control
I/O Registers
MEMDMA
Peripheral Interface Bus/Peripheral DMA
PMW
Generator
Unit
Device
ADSP-21990BBC
ADSP-21990BST
42 DSP Selection Guide
Encoder
Interface
Unit
(& EET)
Status
Pre-Release
Pre-Release
Auxiliary
PWM
Unit
Timer 0
Timer 1
Timer 2
Flag
I/O
SPI
Comms
Port
SPORT
Watch
Dog
Timer
Package
Description
Pin
Count
Ball Grid Array
Thin LQFP 1.4mm Thick
196
176
http://www.analog.com/motorcontrol
ADC Control
POR
14-Bit ADC
VREF
Interrupt
Control
(ICNTL)
Temperature
Range
Industrial
Industrial
ADMC Embedded Control Family
Embedded DSP-Based Controllers
The ADMC family of embedded DSP-based
Controllers integrate 16-bit, fixed-point DSPs
with software and analog circuitry optimized
for motor control applications. All processors
are fully code compatible, allowing for additional features and enhanced performance,
while protecting the software development
investment.
Development Tools
Generic specific evaluation and development
tools are available for each ADMCxxx device.
Development tool kits include everything
required to quickly and easily develop user specific applications including:
• VisualDSP++-based motion control debugger
• Connector board
• Compiler, linker, assembler
• Serial cable
• Example software
• User documentation and reference guides
• Modular processor board
Embedded Control applications support can be
obtained at [email protected] Users can
also obtain additional support, free software
upgrades, and sample code by visiting the
Motor Control Web site at:
www.analog.com/motorcontrol
Embedded DSP Motor Control Selector Guide
Device
Data
RAM
Program
Program Program
MIPS RAM Words FLASH ROM Words Words
ADMC401
26
2K
ADMC341
ADMCF341
ADMC340
ADMCF340
20
512
ADMC328
ADMCF328
ADMC326
ADMCF326
20
512
ADMC331
26
ADMC300
25
4K (F34x)
2K
1K
4K (34x)
512
Embedded
Control
Peripherals
ADC
8 Channel • 3 Phase PWM
12-bit
• Aux PWM
• Encoder Interface
13 Channel • 3 Phase PWM
10-bit
• Aux PWM
• 25 Digital I/O
Package
Options
144 Pin
LQFP
64 Pin
LQFP
28 Pin
SOIC
4K (32x)
512
6 Channel
10-bit
• 3 Phase PWM
• Aux PWM
28 Pin
SOIC
2K
2K
1K
7 Channel • 3 Phase PWM
• Aux PWM
10-bit
• 24 PIOS
80 Pin
LQFP
4K
2K
1K
5 Channel
12-bit
Sigma
Delta
4K (F32x)
http://www.analog.com/motorcontrol
• 3 Phase PWM
• Aux PWM
• Encoder Interface
80 Pin
LQFP
DSP Selection Guide 43
ADMCF34x/ADMC34x
Embedded DSP Controllers with Flash Memory
Features
Applications
• Integrated 10-bit ADC subsystem
– 13 channels (F340/340)
– 6 channels (F341/341)
– Integrated current sense amplifiers
– Internal voltage reference
• Three phase PWM generation
• Two auxiliary PWM outputs
• 20 MIPS fixed-point DSP core
– 4K flash memory (ADMCF34x only)
– 4K program memory ROM (ADMC34x
only)
– 512 program memory RAM
– 512 data memory RAM
• Up to 24 digital I/O line
• Integrated power-on-reset function
• 28 pin SOIC and 64 QFP packages
• Motor types - AC Induction Motors (ACIM),
Permanent Magnet Synchronous Motors
(PMSM), Brushless DC Motors (BDCM),
Switched Reluctance Motors (SRM)
• Industrial variable speed and servo drives
• Uninterruptable power supplies
• Electric vehicles
Model
ADMCF341BR
ADMCF340BST
MHz
Pin/Pkg
20
20
28 SOIC
64 LQFP
B = Industrial Temp ( -40ºC to +85ºC ambient)
* Each ROM order requires a 25,000-piece minimum
order quantity and a $10,000 NRE charge
Benefits
Development Tools
Price
ADMCF340-EVALKIT
ADMCF341-EVALKIT
$395.00
$395.00
• ADC subsystems and peripherals tailored for
specific motor types to simplify development
• 3 Sector on-chip Flash memory allows for incircuit programming for software upgrade ability and rapid code development
• Integrated Power-On-Reset and precision volt
age reference reduce system costs
• Pin for pin compatible ROM device provide low
cost high volume option
Memory Block
ADSP-21xx Base
Architecture
Data Address
Generators
DAG 1 DAG 2
Program
Sequencer
Program ROM
2K x 24
Prog FLASH
4K x 24
(ADMCF34x)
Program RAM
512 x 24
Data RAM
512 x 16
Motor Control
Peripherals
13
Analog
Inputs
VREF
3x
ISENSE
Amp
16-Bit
3 Phase
PWM
Program Memory Address
Data Memory Address
Program Memory Data
Data Memory Data
Serial Port
Arithmetic Units
POR
ALU
MAC
Shifter
44 DSP Selection Guide
Timer
SPORT 1
8-Bit
PIO
http://www.analog.com/motorcontrol
2 x 8-Bit
Auxiliary
PWM
WatchDog
Timer
ADMC401
Single-Chip, High Performance Embedded DSP Controller
Features
Applications
• High resolution integrated 12-bit multi-channel ADC (> 70 dB SNR)
– 8 channel simultaneous sampling (8 channels converted in < 2µ sec)
– Integrated precision voltage reference
• Three phase 16-bit PWM generation unit
• Two 8-bit auxiliary PWM outputs
• 26 MIPS fixed-point DSP core
– 2K x 24-bit program memory RAM
– 2K x 24-bit program memory ROM
– 1K x 16-bit data memory RAM
– 14-bit adress bus and 24-bit data bus for
external memory expansion
• Incremental encoder interface
• Programmable digital I/O
• Integrated power-on-reset
• Motor types - AC Induction Motors (ACIM),
Permanent Magnet Synchronous Motors
(PMSM), Brushless DC Motors (BDCM),
Switched Reluctance Motors (SRM)
• Industrial variable speed and servo drives
• Uninterruptable power supplies
• Numerical control machines
• Robotics
Price*
Pin/Pkg
(100-499)
144 Pin
$24.95
LQFP
B = Industrial Temp (-40ºC to +85ºC ambient)
* All pricing is budgetary – subject to change
MHz
26
Model
ADMC401BST
Development Tools
Price
ADMC401-ADVEVALKIT
$395.00
Benefits
• High performance DSP integrated with fast
12-bit ADC provides for true single chip
solution
• Fully code compatible with all ADSP-21xx
and ADMCxx family products
• Algebraic assembly language for easy programming
• External address and data bus allows external memory to be added as needed
• Flexible encoder interface unit for position
feedback
ADSP-21xx Base
Program ROM
Architecture
• Integrated power-on2K x 24
Data Address
reset function and
Generators
Program
Program RAM
Sequencer
DAG 1 DAG 2
2K x 24
voltage reference
remove system cost
Program Memory Address
Motor Control 4
Peripherals
Memory
Block
Data RAM
1K x 16
WatchDog
Timer
POR
Program
Interrupt
Controller
Encoder
Interface
2
12
Event
Capture
Timers
Digital
I/O
Data Memory Address
Program Memory Data
Data Memory Data
Serial Ports
Arithmetic Units
ALU
MAC
Shifter
SPORT 0
5
SPORT 1
Interval
Timer
2-Channel
Auxiliary
PWM
8-Channel
12-Bit
ADC
Precision
Voltage
Reference
16-Bit
PWM
Generation
6
2
http://www.analog.com/motorcontrol
8
6
DSP Selection Guide 45
Quad-SHARCs AD14060/AD14160
480-MFLOP, Single Package Multiprocessor
The AD14060 Quad-SHARC is a first generation (CQFP) DSP multiprocessor. Using highdensity packaging techniques, the module fits
four SHARCs in approximately 30% of the
space required using discrete packages.
Applications
Multi-SHARC designs with tight area/volume
constraints, such as large array and image
processors, smart missiles, avionics, and others
will benefit. The AD14060/AD14160 are
available as both industrial and MIL-SMD
grade parts in 5V (AD14060/AD14160) or
3.3V (AD14060L/AD14160L) versions.
The AD14160 Quad-SHARC Ceramic Ball
Grid Array (CBGA) puts the power of the first
generation AD14060 (CQFP) DSP multiprocessor into a very high density ball grid array
package, the module fits four SHARCs in
approximately 30% of the space required using
discrete packages; now with additional link and
serial I/O pinned out, beyond that from the
CQFP package.
Competition
http://www.analog.com/milsystems
TDO
FLAG3
TCK, TMS, TRST
SPORT 0
FLAG1
IRQ2-0
FLAG2,0
LINK 4
LINK 3
LINK 1
CS
TIMEXP
RESET
CLKIN
EMU
EBOOT,
LBOOT, BMS
FLAG2,0
IRQ2-0
LINK 4
TDO
FLAG3
CPA
SPORT 1
ID2-0 = 3
LINK 3
FLAG1
TCK, TMS, TRST
SPORT 0
RESET
SHARC_C
LINK 1
LINK 0
LINK 2
LINK 5
TDO
CLKIN
(ADDR31-0, DATA47-0, MS3-0, RD, WR, PAGE, ADRCLK, SW, ACK,
SBTS, HBR, HBG, REDY, BR6-1, RPBA, DMAR1-2, DMAG1-2)
TIMEXP
FLAG2,0
IRQ2-0
LINK 4
LINK 3
LINK 1
TIMEXP
ID2-0 = 2
AD14060 Functional Block Diagram
46 DSP Selection Guide
CPA
SPORT 1
SHARC_B
CS
LINK 0
LINK 2
LINK 5
TDI
ID2-0 = 4
CS
FLAG3
FLAG1
SPORT 0
SHARC_D
TCK, TMS, TRST
RESET
CLKIN
SHARC BUS
LINK 0
LINK 2
LINK 5
TDI
EBOOT,
LBOOT, BMS
EMU
FLAG1
TCK, TMS, TRST
SPORT 0
FLAG3
IRQ2-0
LINK 4
FLAG2,0
LINK 3
RESET
CLKIN
EMU
ID2-0 = 1
AD14060/
AD14060L
CPA
SPORT 1
TDO
LINK 0
LINK 2
LINK 5
TDO
SHARC_A
EBOOT,
LBOOT, BMS
EMU
The AD14060/AD14160 take advantage of the built-in multiprocessing
features of the ADSP-21060, to
achieve 480 peak MFLOPS with a single chip type, in a single package. The
on-chip SRAM of the DSPs provides
16 Mbits of on-module shared SRAM.
The complete shared bus (48-bit data,
32-address) is also brought off-module
for interfacing with expansion memory and/or other peripherals.
EBOOT,
LBOOT, BMS
CPA
SPORT 1
TDI
LINK 1
CS
The core of the multiprocessors is the
ADSP-21060 DSP Microcomputer. The
AD14060/ AD14160 modules have the highest
performance-density and lowest cost-performance ratios of any multiprocessors in
their class. They are ideal for applications requiring higher levels of performance and/or functionality per unit
area.
TIMEXP
With 480 MFLOPS of throughput, the
AD14060/AD14160 have no competition. TI's
Dual C40 MCM provides a similar function,
but delivers only 80 MFLOPS in a significantly
larger package, and roughly equivalent cost.
The Quad-SHARC AD14060/AD14160 is targeted to be priced such that users can take
advantage of system cost advantages of using
MCMs.
Quad-SHARCs AD14060/AD14160
AD14060
Development Tools
Both the AD14060 and AD14160 are supported
with a complete set of software and hardware
development tools, including an ADSP-21061
EZ-KIT Lite, and development software.
Features
• ADSP-21060 core processor (. . . x4)
• 480 MFLOPS Peak, 320 MFLOPS sustained
• 25 ns instruction rate, single-cycle instruction
execution - each of 4 processors
• 16 Mbit shared SRAM (internal to SHARC’s)
• 4 gigawords addressable off - module
memory
• 48-bit shared memory bus, 48-bit data bus
• Full 32-bit address bus
• Interrupts, flag pins, and timers are also avail
able as I/O
• 32-Bit single precision and 40-Bit extended
precision IEEE floating-point data formats, or
32-Bit fixed-point data format
• User configurable boot modes, bus priority,
and other features with control lines
• IEEE JTAG standard 1149.1 test access port
and on-chip emulation
– Twelve 40 Mbyte/s link ports (3 per SHARC)
accessible to/from the outside world
– Four link ports connected internally in a
ring configuration
– Four 40 Mbit/s independent serial ports
(one from each SHARC)
– One 40 Mbit/s common serial port
– Ceramic quad flat pack with enhanced I/O
– Low-profile 2.05” 308 lead ceramic quad
flat pack package
AD14160
– Sixteen 40 Mbyte/s link ports (per SHARC)
accessible to/from the outside world
– Eight link ports connected internally in ring
configuration
– Eight 40 Mbit/s independent serial ports
(two from each SHARC) available from
outside
– Ceramic ball grid array QUAD-SHARC
with enhanced I/O
– Low-profile 1.85" ceramic ball grid array
package
For any further inquiries, please contact MCP
Marketing in Greensboro, NC at 336-668-9511
http://www.analog.com/milsystems
http://www.analog.com/milsystems
DSP Selection Guide 47
Software and Systems Technologies (SST)
Marketplace pressures of the newest technologies,
faster time to market, and ever-lower systems
costs drive leading OEMs to look for the newest,
fastest ways to introduce their products to their
customers.
To meet this need, Analog Devices Inc. offers
numerous chipset and algorithm reference designs
and third party support in emerging and high
growth market segments.
SST-Melody-32
For High Volume Multi-Channel Digital Audio Processing
Features
Reference Block Diagram
• 32-bit implementation of industry standard
audio formats on new DSP platform
• Decodes up to 8 channels of multiplexed
audio: scaleable between 1 and 8 channels,
with 6.1 core channels and 2 extended channels
• Sufficient computing power for custom OEM
applications such as speaker equalizers and
surround fields
S/PDIF Rx
Codec
(AD 183x)
SPI Bus
Melody 32
Applications
• Home theater AVR systems
• Automotive audio
• DVD players
• Video game consoles
• Set Top boxes
48 DSP Selection Guide
SRAM
64kx16, 20 ns.
Not required
For 5.1 models
Benefits
• Melody 32 offers end-to-end 32-bit precision of
decode & post-processing for leading digital
audio formats in real-time.
• The Melody reference design decodes up to 7.1
channels of DTS ES Extended Surround, Dolby
Digital, Dolby Pro Logic II, AAC, MP3, and
includes THX Surround EX, Bass Management,
Delay Management, and automatic detection of
the incoming audio bit-stream.
• Decoder supports all bit rates (up to 1,536 kbps),
compression ratios (up to 40:1) and sampling
frequencies (32, 44.1, and 48 kHz per channel)
specified by the DTS (Digital Theater Systems)
and Dolby audio standards. It also supports fea
tures specified by the DTS standard -- including
Dynamic Range Control, Down-Mixing, and Reequalization of all channels independently.
Host
Boot Flash
512kx8, 100 ns.
Chipsets
ADSST-MEL-20: Bundled chipset that includes the
high performance of the ADSST-MEL322 processor
with a high performance audio codec. It includes
decoding / post processing for Dolby Digital EX,
Dolby Pro Logic II, AAC (LC), DTS ES (Discrete
and Matrix), DTS Neo:6.
ADSST-MEL-30: Includes decoding / post processing for Dolby Digital EX, Dolby Pro Logic II, DTS ES
(Discrete and Matrix), DTS Neo:6, THX EX, SRS
Circle Surround II, TruBass codes. The chipset
includes ADI Surround modes, Speaker EQ as well
as Bass Management and Delay.
ADSST-MEL-40: Features of the ADSST-MEL-30
but without THX processing.
ADSST-MEL-50: Includes decoding / post processing for Dolby Digital EX, Dolby Pro Logic II, DTS ES
(Discrete and Matrix), DTS Neo:6 and SRS Circle
Surround II codes. The chipset includes
Wavesurround Headphone and Loudspeaker
Virtualizer modes, Bass Management and Delay.
http://www.analog.com/solutions
SST-Melody-SU
Highest Performance Multi-Channel Audio Processing
Features
Reference Block Diagram
• 32-Bit floating-point implementation for
decoding the leading encoded audio content .
• Decoders operate in real-time with the ability
to auto-detect and display bit stream information
• Decoders support all of the bit rates (up to
6,144 kbps) and sampling frequencies (32,
44.1, 48, 88.2, 96 and 192 kHz per channel)
specified by the encoding standards
S/PDIF Rx
Codec
(AD 183x)
Host
SPI Bus
TM
Melody
SHARC
Ultra
SDRAM
1Mx16, 100 MHz
(2 x 512k*32)
Boot Flash
Benefits
• This enables OEMs to produce high-quality,
low-cost designs featuring decoder algorithms
and post processors for :
– DTS-ES Extended Surround (including
both DTS ES Discrete 6.1 and DTS ES
Matrix 6.1)
– DTS 96/24
– DTS Neo:6
– Dolby Digital, Dolby Pro Logic II, Dolby
Headphone
– THX, THX Surround EX, THX Ultra2
– HDCD
– MPEG1 Audio Layer III (also known as
MP3)
– MPEG AAC (both MP and LC versions)
– SRS Circle Surround II, SRS 3D Sound,
SRS TruSurround, SRS Focus and SRS
TruBass
– MLP
Applications
1Mx8, 100 ns.
Models
Model ADSST-AUDIO-7060: is a twin combination
chipset and includes decoding/post-processing for
Dolby Digital, Dolby Pro Logic II, DTS, THX, DTS
ES-Matrix, Bass Management and Delay.
Model ADSST-AUDIO-7070: Includes Dolby Digital
and Dolby Pro Logic codes.
Model ADSST-AUDIO-7075: includes Dolby Digital,
Dolby Pro Logic and DTS 5.1 codes.
Model ADSST-AUDIO-7085: Includes Dolby Digital,
Dolby Pro Logic II, DTS ES, DTS 6.1, DTS 96/24,
DTS Neo:6, AAC LC and MP, THX Ultra2, Bass
Management and Delay Management.
Model ADSST-AUDIO-7090: Includes Dolby Digital,
DTS ES, DTS 6.1, DTS 96/24, MPEG2 BC, MPEG2
AAC LC and MP, Dolby Pro Logic II, DTS Neo:6.
Model ADSST-AUDIO 7095: Includes Dolby EX,
DTS ES Matrix, Bass Management, THX Ultra2,
Delay Management and Dolby Headphone.
• Multi-channel audio decoders and postprocessors for digital audio designs using
DSPs (Digital Signal Processors) in home
theater
• Automotive audio receivers
• DVD players
http://www.analog.com/solutions
DSP Selection Guide 49
SST-NAV-GPS
NAV2400 Global Positioning Satellite Receiver Chipset
Features
Reference Block Diagram
• L1 band GPS standard positioning service
• Twelve parallel channels
• Computes user's position and velocity and
time
• Efficient algorithms for very low time to first
fix even without almanac
• Soft solution approach for correlation
• TTL output through serial link
• NMEA0183 compatible message format for
host communication
• Real time executive based software
architecture
• Differential GPS compatibility
• Power down features for extremely low
power operation
Benefits
• NAV2400 with its spare processing power
becomes an ideal building block for a variety
of OEM applications. This approach minimizes the additional processing hardware
requirements for integrated GPS based OEM
applications resulting in a cost-effective end
product.
GPS
Antenna
ADSSTGPSRF01
ADSSTNAV2400
User
Interface
Correlator and Navigation Processor
NAV2400 Chipset
GPS receiver based on NAV2400 chipset
Models
Model ADSST-NAV2400: Includes ADSSTGPSRF01 RF Front End and ADSST-NAV2400
Correlation and Navigation Processor to form a
GPS receiver.
Model ADSST-NAV24-SDK: Includes NAV2400
chipset as part of a software development kit and
evaluation platform.
http://www.analog.com/solutions
Applications
• Car telematics
• Fleet management
• Asset management
• Recreational tracking
• Navigation
50 DSP Selection Guide
Boot
EPROM
http://www.analog.com/milsystems
dspConverter
Integrated DSP and Data Converter for Voice
No Digital Feedthrough Problems
ADI’s dspConverters feature our industry leading data converters, 16-bit fixed-point DSPs
and flash memory all packed into one small
(14 mm x 22 mm) BGA package.
The analog front ends are based on our
AD733xx family which include 16-bit linear
codecs, input/output conditioning circuitry and
a flexible serial interface. The DSPs are based
on the ADSP-218x family.
One of the critical aspects of mixed-signal
design is digital feedthrough from high-speed
processors to high-resolution analog circuitry.
This is fully addressed in our dspConverters
with careful circuit layout and synchronization
of clocks. Test results have verified that clock
noise is absent from the digitized analog spectrum even when the DSP is running at full
speed.
Analog Front Ends (AFEs)
Converter Performance and Group Delay
The analog front ends are much more than
codecs. Each channel includes:
• Sigma-delta DAC
• Sigma-delta ADC
• PGA for each encoder and decoder
• Input conditioning circuitry
• Reference
• SPORT
The converters are fully specified with
SNR+THD figures of 78 dB for the encoders
and 77 dB for the decoders. A notable feature
of the performance specification is it’s clarity.
Group delay can be critical in noise cancellation applications. It’s important to cancel the
noise as close to the source as possible. Delays
increase modeling errors, require larger filters
and inhibit random noise cancellation systems.
All analog front ends in the family offer group
delays, which are 25 µs for the encoder and
50 µs for the decoder.
dspConverter Selection Table
Generic
AFE
Channels
AD73411-40
AD73411-80
AD73422-40
AD73422-80
AD73460-80
1
1
2
2
6-Ch ADC
DSP
52
52
52
52
52
MIPS
MIPS
MIPS
MIPS
MIPS
Program
Memory
Data
Memory
Price*
8K
16K
8K
16K
16K
8K
16K
8K
16K
16K
$17.65
$21.18
$20.41
$23.47
$23.47
* US Dollars. Lowest grade suggested resale price per unit in 100 unit quantities
All pricing is budgetary – subject to change
http://www.analog.com
DSP Selection Guide 51
AD73411
Low Power Analog Front End with DSP
Benefits
Features
AFE PERFORMANCE
• 16-Bit A/D converter
• 16-Bit D/A converter
• Programmable input/output sample rates
• 76 dB ADC SNR
• 77 dB DAC SNR
• 64 kS/s maximum sample rate
• –90 dB crosstalk
• Low group delay (25 µs typ per ADC
channel, 50 µs typ per DAC channel)
• Programmable input/output gain
• On-chip reference
• Extensive analog front ends include A/Ds,
D/A, PGAs, reference and input conditioning
circuitry
• Reduced design risk – all the interface design
work is done
• Programmable, high-speed DSP based on
ADSP-218x Family
Applications
DSP PERFORMANCE
• 19 ns instruction cycle time @ 3.3 Volts,
52 MIPS performance
• Single-cycle instruction execution
• Single-cycle context switch
• 3-Bus architecture allows dual operand
fetches in every instruction cycle
• Multifunction instructions
• Power-down mode featuring low CMOS
standby
• Power dissipation with 400 cycle recovery
from power-down condition
Data Address
Generators
• Low power dissipation in idle mode
• General purpose analog I/O
• Speech processing
• Cordless and personal communications
• Telephony
• Wireless local loop
• Active control of sound and vibration
• Data communications
Prog
Data
Memory
8/8K
16/16K
AFE
CHNS
Model
1
AD73411-40
1
AD73411-80
Pin/Pkg
119 PBGA
119 PBGA
Powerdown
Control
Memory
Program
Sequencer
DAG 1 DAG 2
16K PM
(Optional
Program)
16K DM
(Optional
Data)
Programmable
I/O and
Flags
Full Memory
Mode
External
Addr Bus
Program Memory Address
External
Data Bus
Data Memory Address
Program Memory Data
Byte DMA
Controller
Data Memory Data
Arithmetic Units
ALU
MAC
Shifter
Serial Ports
SPORT 0 SPORT 1
ADSP-218X DSP
Serial Ports
REF
Analog Front
End Section
52 DSP Selection Guide
http://www.analog.com
Timer
SPORT 2
ADC
DAC
AD73422
Dual Low Power Analog Front End with DSP
Features
Benefits
AFE PERFORMANCE
• 16-Bit A/D converter
• 16-Bit D/A converter
• Programmable input/output sample rates
• 76 dB ADC SNR
• 77 dB DAC SNR
• 64 kS/s maximum sample rate
• –90 dB crosstalk
• Low group delay (25 µs typ per ADC
channel, 50 µs typ per DAC channel)
• Programmable input/output gain
• On-chip reference
• Extensive analog front ends include A/Ds,
D/A, PGAs, reference and input conditioning
circuitry
• Reduced design risk – all the interface design
work is done
• Programmable, high-speed DSP based on
ADSP-218x Family
Applications
• General purpose analog I/O
• Speech processing
• Cordless and personal communications
• Telephony
• Wireless local loop
• Active control of sound and vibration
• Data communications
DSP PERFORMANCE
• 19 ns instruction cycle time @ 3.3 Volts,
52 MIPS performance
• Single-cycle instruction execution
• Single-cycle context switch
AFE
• 3-Bus architecture allows dual operand
CHNS
Model
fetches in every instruction cycle
AD73422-40
2
• Multifunction instructions
AD73422-80
2
• Power-down mode featuring low CMOS
standby
Powerdown
Control
• Power dissipation with 400 cycle
Address
Memory
Generators
recovery from power-down condition Data
Program
Sequencer
DAG 1 DAG 2
Program
Data
• Low power dissipation in idle mode
Memory
Memory
Prog
Data
Memory
8/8K
16/16K
Pin/Pkg
119 PBGA
119 PBGA
Full Memory
Mode
Programmable
I/O and
Flags
External
Addr Bus
External
Data Bus
Program Memory Address
http://www.analog.com/dspconverter
Byte DMA
Controller
Data Memory Address
Program Memory Data
Or
Host Mode
Data Memory Data
External
Data Bus
Arithmetic Units
ALU
MAC
Shifter
Serial Ports
SPORT 0 SPORT 1
ADSP-218X DSP
Timer
Internal
DMA Port
Serial Ports
REF
ADC 1
SPORT 2
DAC 1
ADC 2
DAC 2
Analog Front End Section
http://www.analog.com
DSP Selection Guide 53
AD73460
Low Power, Six-Channel ADC with DSP
Features
Benefits
AFE PERFORMANCE
• Six 16-Bit A/D converters
• Programmable input sample rate
• 72 dB ADC SNR
• 64 kS/s maximum sample rate
• –80 dB crosstalk
• Low group delay (25 µs typ per ADC
channel)
• Programmable input gain
• Single supply operation
• On-chip reference
• Extensive analog front ends include A/Ds,
D/As, PGAs, reference and input conditioning
circuitry
• Reduced design risk – all the interface design
work is done
• Programmable, high-speed DSP based on
ADSP-218x Family
Applications
DSP PERFORMANCE
• 19 ns instruction cycle time @ 3.3 Volts,
52 MIPS sustained performance
• Single-cycle instruction execution
• Single-cycle context switch
• 3-Bus architecture allows dual operand
fetches in every instruction cycle
• Multifunction instructions
• Power-down mode featuring low CMOS
standby
• Power dissipation with 400 cycle
Data Address
recovery from power-down condition Generators
DAG 1 DAG 2
• Low power dissipation in idle mode
• General purpose I/O
• Industrial metering
• Active control of sound and vibration
• Speech processing
• Data communications
Model
AD73460BB-40
AD73460BB-80
AFE
CHNS
6
6
Prog
Data
Memory Pin/Pkg
8/8K
119 PBGA
16/16K
119 PBGA
Powerdown
Control
Memory
Program
Sequencer
16K PM
(Optional
8K)
16K DM
(Optional
8K)
Programmable
I/O and
Flags
Full Memory
Mode
External
Addr Bus
Program Memory Address
External
Data Bus
Data Memory Address
Program Memory Data
Byte DMA
Controller
Data Memory Data
Arithmetic Units
ALU
MAC
Shifter
ADSP-2100 Base
Architecture
Serial Ports
SPORT 0 SPORT 1
Serial Ports
REF
ADC1
54 DSP Selection Guide
http://www.analog.com
Timer
SPORT 2
ADC2
ADC3
ADC4
Analog Front
End Section
ADC5
ADC6
ADI Support for Universities
The ADI DSP University Program provides the next generation of engineers with DSP knowledge
to help them compete in the industry of tomorrow.
The ADI DSP University Program offers:
• Complete DSP Software and Hardware Tools to set up a DSP LAB
• Teaching material to help design experiments
• Priority technical support to professors
Analog Devices DSP technology is easy to teach:
• DSP architectures that are the simplest to program in the industry
• Simple instruction sets
• High levels of SRAM integration
Hundreds of universities in 37 countries use ADI DSPs
for teaching and research.
To request a University discount or learn more, go to:
http://www.analog.com/dsp/university
http://www.analog.com/dsp/university
DSP Selection Guide 55
DSP Literature Selection Guide
Title
Where to Order
Publication Number Price
ADSP-21xx Development Board and Emulator Publications
ADSP-218x DSP family and ADSP-2192 EZ-KIT Lite Installation Procedure
www.analog.com/dsp
NC
ADSP-2191 EZ-KIT Lite Manual
www.analog.com/dsp
NC
ADSP-2192-12 EZ-KIT Lite Manual
www.analog.com/dsp
NC
ADSP-2181 EZ-KIT Lite Evaluation Manual
www.analog.com/dsp
NC
ADSP-2189M EZ-KIT Lite Evaluation System Manual
www.analog.com/dsp
NC
ADSP-218X Family EZ-ICE® Hardware Installation Guide
www.analog.com/dsp
NC
Summit-ICE™ Emulator Hardware User's Guide
www.analog.com/dsp
NC
Apex-ICE™ USB Emulator Hardware Installation Guide
www.analog.com/dsp
NC
VisualDSP++ for the ADSP-21xx
Complete Set of ADSP-21xx VisualDSP++ Manuals - includes the following:
From ADI Sales and Dist.
VDSP-21XX-MAN-FULL
$100.00
VisualDSP++ Getting Started Guide for ADSP-21xx DSPs
www.analog.com/dsp
NC
VisualDSP++ User's Guide for ADSP-21xx DSPs
www.analog.com/dsp
NC
VisualDSP++ C Compiler and Library Manual for ADSP-218x DSPs
www.analog.com/dsp
NC
VisualDSP++ C/C++ Compiler and Library Manual for ADSP-219x DSPs
www.analog.com/dsp
NC
VisualDSP++ Assembler and Preprocessor Manual for ADSP-218x DSPs
www.analog.com/dsp
NC
VisualDSP++ Assembler and Preprocessor Manual for ADSP-219x DSPs
www.analog.com/dsp
NC
VisualDSP++ Linker and Utilities Manual for ADSP-21xx DSPs
www.analog.com/dsp
NC
VisualDSP++ Kernel (VDK) User's Guide VisualDSP++ Installation Guide
www.analog.com/dsp
NC
VisualDSP++ for Blackfin DSPs
Complete Set of ADSP-21xx VisualDSP++ Manuals - includes the following:
From ADI Sales and Dist.
VDSP-BLKFN-MAN-FUL
$100.00
VisualDSP++ Getting Started Guide for Blackfin DSPs
www.analog.com/dsp
NC
VisualDSP++ User's Guide for Blackfin DSPs
www.analog.com/dsp
NC
VisualDSP++ C/C++ Compiler and Library Manual for Blackfin DSPs
www.analog.com/dsp
NC
VisualDSP++ Assembler and Preprocessor Manual for Blackfin DSPs
www.analog.com/dsp
NC
VisualDSP++ Linker and Utilities Manual for Blackfin DSPs
www.analog.com/dsp
NC
VisualDSP++ Kernel (VDK) User's Guide (Second Revision
www.analog.com/dsp
NC
www.analog.com/dsp
NC
VisualDSP++ Installation Guide
ADSP-21xx Publications
ADSP-2100 Family User's Manual
Lit Center
82-000780-03
NC
ADSP-218x DSP Hardware Reference Manual
Lit Center
82-002010-01
NC
ADSP-218x DSP Instruction Set Reference
Lit Center
82-002000-01
NC
ADSP-219x/2191 DSP Hardware Reference Manual
Lit Center
82-000390-06
NC
ADSP-219x/2192 DSP Hardware Reference Manual
Lit Center
82-002001-01
NC
ADSP-219x DSP Instruction Set Reference
Lit Center
82-000390-07
NC
ADSP-21xx Data Sheets
ADSP-2181
www.analog.com/dsp
NC
ADSP-2183
www.analog.com/dsp
NC
ADSP-2185M
www.analog.com/dsp
NC
ADSP-2186M
www.analog.com/dsp
NC
ADSP-2188M
www.analog.com/dsp
NC
ADSP-2189M
www.analog.com/dsp
NC
ADSP-218xN Series
www.analog.com/dsp
NC
ADSP-2191M
www.analog.com/dsp
NC
ADSP-2192
www.analog.com/dsp
NC
Blackfin DSP Publications
ADSP-21535 Blackfin DSP Hardware Reference, Preliminary Edition
www.analog.com/dsp
Preliminary
NC
Blackfin DSP Instruction Set Reference, Preliminary Edition
www.analog.com/dsp
Preliminary
NC
Blackfin DSP Data Sheets
ADSP-21532
www.analog.com/dsp
Preliminary
NC
ADSP-21535
www.analog.com/dsp
Preliminary
NC
56 DSP Selection Guide
http://www.analog.com/dsp/tech_doc
DSP Literature Selection Guide
Title
Where to Order
Publication Number Price
SHARC DSP Development Board and Emulator Publications
ADSP-21061 EZ-KIT Lite Manual
www.analog.com/dsp
NC
ADSP-21065L EZ-KIT Lite Manual
www.analog.com/dsp
NC
ADSP-21161N EZ-KIT Lite Manual
www.analog.com/dsp
NC
Apex-ICE™ USB Emulator Hardware Installation Guide
www.analog.com/dsp
NC
Summit-ICE™ Emulator Hardware User's Guide
www.analog.com/dsp
NC
VisualDSP++ for SHARC DSPs
Complete Set of SHARC VisualDSP++ Manuals - includes the following:
From ADI Sales and Dist.
VisualDSP++ Getting Started Guide
www.analog.com/dsp
NC
VisualDSP++ User's Guide for the ADSP-21xxx Family DSPs
www.analog.com/dsp
NC
Assembler and Preprocessor Manual for the ADSP-21xxx Family DSPs
www.analog.com/dsp
NC
C/C++ Compiler & Library Manual for the ADSP-21xxx Family DSPs
www.analog.com/dsp
NC
Linker & Utilities Manual for the ADSP-21xxx Family DSPs
www.analog.com/dsp
NC
VisualDSP++ Kernel (VDK) User's Guide
www.analog.com/dsp
NC
VisualDSP++ Installation Guide
www.analog.com/dsp
NC
VDSP-SHARC-MAN-FUL
$100.00
VisualDSP++ for TigerSHARC DSPs
Complete Set of TigerSHARC VisualDSP++ Manuals - includes the following:
From ADI Sales and Dist.
VisualDSP++ User's Guide for TigerSHARC DSPs
www.analog.com/dsp
NC
VisualDSP++ Assembler and Preprocessor Manual for TigerSHARC DSPs
www.analog.com/dsp
NC
VisualDSP++ C/C++ Compiler and Library Manual for TigerSHARC DSPs
www.analog.com/dsp
NC
VisualDSP++ Linker and Utilities Manual for TigerSHARC DSPs
www.analog.com/dsp
NC
VisualDSP++ Kernel (VDK) User's Guide
www.analog.com/dsp
NC
VisualDSP++ Installation Guide
www.analog.com/dsp
NC
VDSP-TS-MAN-FULL
$100.00
SHARC DSP and TigerSHARC DSP Publications
ADSP-2106x SHARC Family User's Manual, 2nd Edition
Lit Center
E2003a-16-5/97
NC
ADSP-21065L User's Manual & Technical Reference
Lit Center
82-001833-01
NC
ADSP-21160 SHARC Hardware Reference
Lit Center
82-001966-01
NC
ADSP-21160 SHARC Instruction Set Reference
Lit Center
82-001967-01
NC
ADSP-21161 SHARC Hardware Reference
Lit Center
82-001944-01
NC
ADSP-21000 Family Applications Handbook
www.analog.com/dsp
NC
TigerSHARC ADSP-TS101S Hardware Specification Rev 1.01, July 2001
www.analog.com/dsp
NC
TigerSHARC Instruction Specification ADSP-TS101S Revision 1.0, July 2001
www.analog.com/dsp
NC
SHARC DSP and TigerSHARC DSP Data Sheets
ADSP-21060/ADSP-21060L
www.analog.com/dsp
NC
ADSP-21061/ADSP-21061L
www.analog.com/dsp
NC
ADSP-21062/ADSP-21062L
www.analog.com/dsp
NC
ADSP-21065L
www.analog.com/dsp
NC
ADSP-21060C/ADSP-21060LC
www.analog.com/dsp
NC
ADSP-21160M
www.analog.com/dsp
NC
ADSP-21160N
www.analog.com/dsp
NC
ADSP-21161N
www.analog.com/dsp
NC
ADSP-TS101S
www.analog.com/dsp
NC
* NC = No charge
** Data Sheets and Manuals can also be downloaded from the ADI DSP website
http://www.analog.com/dsp/tech_doc
http://www.analog.com/dsp/tech_doc
DSP Selection Guide 57
DSP Technical Training Workshops
Description
How to Register
The DSP System Development and
Programming workshops are comprehensive,
hands-on workshops. The workshops are
geared towards people who have a working
knowledge of microprocessors and want to
learn how to use Analog Devices DSPs. These
courses cover the DSP architecture, assembly
language syntax, I/O interface, hardware and
software development tools. Throughout the
workshop, attendees learn how easy it is to use
Analog Devices’ DSPs from lecture sessions
and hands-on exercises.
To enroll, customers should register online at the
Analog Devices web site at:
http://www.analog.com/dsp/training
You will be notified when your seat is confirmed.
Locations and Schedules
ADSP-218x Workshop
This is a 3-day workshop which covers the
ADSP-218x family of DSPs and development
tools. For registration and price, contact
Momentum Data Systems via e-mail at
[email protected], or by phone at 714-378-5805.
Part Number: ADDS-218X-WKSP
Price: Contact
Momentum
ADSP-2106x Workshop
The workshops are offered monthly in North
America. Workshop schedules and more details
on DSP workshops are also available on the
web site.
http://www.analog.com/dsp/training
This is a 3.5 day workshop which covers all the
ADSP-2106x DSPs including the ADSP21065L and development tools. For registration
and price, contact Melinda Rosauro at bEST Inc,
at [email protected] or 905-821-7800 X3330.
Part Number: ADDS-2106X-WKSP Price: Contact bEST
ADSP-2116x Workshop
This is a 3.5 day workshop which covers
ADSP-21160 and development tools. For registration and price, contact Melinda Rosauro at
bEST Inc, at [email protected] or
905-821-7800 X3330.
Part Number: ADDS-2116X-WKSP Price: Contact bEST
ADSP-219x Workshop
This is a 3.5 day workshop which covers the
ADSP-219x family of DSPs and development
tools. For registration and price, contact Melinda
Rosauro at bEST Inc, at [email protected] or
905-821-7800 X3330.
Part Number: ADDS-219X-WKSP
Price: Contact bEST
* Analog Devices also offers workshops in France, Germany, Italy, Scandinavia, UK, and Spain. The schedule of
classes can be viewed online at http://www.analog.com/technology/dsp/training/events/schedule.html
58 DSP Selection Guide
http://www.analog.com/dsp/training
ADI DSP-Power Management Guide
Recommended ADI Power Management
Devices for Maximum DSP Core and I/O Currents
ADSP-21xx Platform
DSP Family
ADSP-2184N
ADSP-2185M
ADSP-2185N
ADSP-2186M
ADSP-2186N
ADSP-2187N
ADSP-2188M
ADSP-2188N
ADSP-2189M
ADSP-2189N
ADSP-2191M
ADSP-2195M
ADSP-2196M
DSP
Supply
Voltage
(nominal)
Max
Supply
Current
1.8V core
3.3V I/O
2.5V core
3.3V I/O
1.8V core
3.3V I/O
2.5Vcore
3.3V I/O
1.8Vcore
3.3V I/O
1.8Vcore
3.3V I/O
2.5Vcore
3.3V I/O
1.8Vcore
3.3V I/O
2.5Vcore
3.3V I/O
1.8Vcore
3.3V I/O
2.5V core
3.3V I/O
2.5V core
3.3V I/O
2.5V core
3.3V I/O
25 mA
14 mA
38 mA
12 mA
25 mA
14 mA
38 mA
12 mA
25 mA
14 mA
26 mA
14 mA
44 mA
12 mA
25 mA
14 mA
32 mA
15mA
26 mA
14 mA
184 mA
14 mA
184 mA
14 mA
184 mA
14 mA
1 DSP
2 or More DSPs
LDO
DC/DC
Switching
Regulator or
Controller
LDO
DC/DC
Switching
Regulator or
Controller
ADP3331
ADP3309
ADP3309
ADP3300
ADP3331
ADP3300
ADP3309
ADP3300
ADP3331
ADP3330
ADP3331
ADP3300
ADP3309
ADP3300
ADP3331
ADP3300
ADP3309
ADP3300
ADP3331
ADP3330
ADP3330
ADP3300
ADP3330
ADP3300
ADP3330
ADP3300
ADP3088
ADP3088
ADP3088
ADP3088
ADP3088
ADP3088
ADP3088
ADP3088
ADP3088
ADP3088
ADP3088
ADP3088
ADP3088
ADP3088
ADP3088
ADP3088
ADP3088
ADP3088
ADP3088
ADP3088
ADP3088
ADP3088
ADP3088
ADP3088
ADP3088
ADP3088
ADP3331
ADP3309
ADP3309
ADP3309
ADP3331
ADP3309
ADP3309
ADP3309
ADP3331
ADP3309
ADP3331
ADP3309
ADP3309
ADP3309
ADP3331
ADP3309
ADP3331
ADP3309
ADP3331
ADP3309
ADP3335
ADP3309
ADP3335
ADP3309
ADP3335
ADP3309
ADP3088
ADP3088
ADP3088
ADP3088
ADP3088
ADP3088
ADP3088
ADP3088
ADP3088
ADP3088
ADP3088
ADP3088
ADP3088
ADP3088
ADP3088
ADP3088
ADP3088
ADP3088
ADP3088
ADP3088
ADP3088
ADP3088
ADP3088
ADP3088
ADP3088
ADP3088
ADP3333
ADP3309
ADP3338/9
ADP3309
ADP3338/9
ADP3309
ADP3338
ADP3309
ADP3088
ADP3088
ADP3088
ADP3088
ADP3088
ADP3088
ADP3088
ADP3088
ADP3338
ADP3309
ADP3309
ADP3330
ADP3330
ADP3088
ADP3088
ADP3088
ADP3088
ADP3050
ADP3088
ADSP-21xxx SHARC Platform
ADSP-21065L
ADSP-21160M
ADSP-21160N
ADSP-21161N
3.3Vcore
3.3V I/O
2.5Vcore
3.3V I/O
1.8V core
3.3V I/O
1.8V core
3.3V I/O
275 mA
21 mA
875 mA
41 mA
875 mA
72 mA
550 mA
56 mA
http://www.analog.com/dsp
DSP Selection Guide 59
Remember . . .
Analog Devices Offers Products and Solutions
for the Entire Signal Chain
VREF
In
Amp
Sensor
AntiAliasing
Filter
Mux
or DIFF Amp
Analog
Out
Smoothing
Filter
PC
Interface
Logic
Sampling
ADC
PGA
VREF
PC
DSP
DAC
Interface
I/O
Sup
ervis
ory
Vo
lta
ge
Re
fer
en
ce
s
Interface
r
o
s
n
Se
s
Reset
Generators
Cs
A
&D
s
C
D
A
rs
e
t
r
e
v
n
Co
ers
x
e
l
p
i
t
l
Mu
d
n
a
s
e
Switch
Power M
anagem
ent
Am
plif
iers
. . . and much, much more
http://www.analog.com
DSP Support
Tel:
1 781 329 4700
1 800 262 5643 (U.S.A. only)
Email: In the U.S.A.: [email protected]
In Europe: [email protected]
Fax: In the U.S.A.: 1 781 461 3010
In Europe: +49 89 76903 307
World Wide Web site:
http://www.analog.com/dsp
World Headquarters
One Technology Way, P.O. Box 9106
Tel: 1 781 329 4700
1 800 262 5643 (U.S.A. only)
Fax: 1 781 326 8703
World Wide Web site:
http://www.analog.com
Europe Headquarters
Am Westpark I-3
D081373 München, Germany
Tel: +49 89 76903-0
Fax: +49 89 76903-157
Japan Headquarters
New Pier Takeshiba
South Tower Building
1-16-1 Kaigan, Minato-ku
Tokyo 105-6891, Japan
Tel: 3 5402 8210
Fax: 3 5402 1063
Southeast Asia Headquarters
4501 Nat West Tower
Times Square
1 Matheson Street
Causeway Bay
Hong Kong, PRC
Tel: 852 2 506 9336
Fax: 852 2 506 4755
G02458-25-6/02 (H)
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