Product information | ACT PRO MIFARE DESFIRE EV1 - REV 1.0 Product data

MFRC522

Standard 3V MIFARE reader solution

Rev. 3.8 — 17 September 2014

112138

Product data sheet

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1. Introduction

This document describes the functionality and electrical specifications of the contactless reader/writer MFRC522.

Remark: The MFRC522 supports all variants of the MIFARE Mini, MIFARE 1K,

MIFARE 4K, MIFARE Ultralight, MIFARE DESFire EV1 and MIFARE Plus RF identification protocols. To aid readability throughout this data sheet, the MIFARE Mini,

MIFARE 1K, MIFARE 4K, MIFARE Ultralight, MIFARE DESFire EV1 and MIFARE Plus products and protocols have the generic name MIFARE.

The MFRC522 is a highly integrated reader/writer IC for contactless communication at 13.56 MHz. The MFRC522 reader supports ISO/IEC 14443 A/MIFARE mode.

The MFRC522’s internal transmitter is able to drive a reader/writer antenna designed to communicate with ISO/IEC 14443 A/MIFARE cards and transponders without additional active circuitry. The receiver module provides a robust and efficient implementation for demodulating and decoding signals from ISO/IEC 14443 A/MIFARE compatible cards and transponders. The digital module manages the complete ISO/IEC 14443 A framing and error detection (parity and CRC) functionality.

The MFRC522 supports MF1xxS20, MF1xxS70 and MF1xxS50 products. The MFRC522 supports contactless communication and uses MIFARE higher transfer speeds up to

848 kBd in both directions.

The following host interfaces are provided:

• Serial Peripheral Interface (SPI)

• Serial UART (similar to RS232 with voltage levels dependant on pin voltage supply)

• I 2 C-bus interface

2.1 Differences between version 1.0 and 2.0

The MFRC522 is available in two versions:

• MFRC52201HN1, hereafter referred to version 1.0 and

• MFRC52202HN1, hereafter referred to version 2.0.

The MFRC522 version 2.0 is fully compatible to version 1.0 and offers in addition the following features and improvements:

NXP Semiconductors

MFRC522


• Increased stability of the reader IC in rough conditions

• An additional timer prescaler, see

Section 8.5

.

• A corrected CRC handling when RX Multiple is set to 1

This data sheet version covers both versions of the MFRC522 and describes the differences between the versions if applicable.

3. Features and benefits

 Highly integrated analog circuitry to demodulate and decode responses

 Buffered output drivers for connecting an antenna with the minimum number of external components

 Supports ISO/IEC 14443 A/MIFARE

 Typical operating distance in Read/Write mode up to 50 mm depending on the antenna size and tuning

 Supports MF1xxS20, MF1xxS70 and MF1xxS50 encryption in Read/Write mode

 Supports ISO/IEC 14443 A higher transfer speed communication up to 848 kBd

 Supports MFIN/MFOUT

 Additional internal power supply to the smart card IC connected via MFIN/MFOUT

 Supported host interfaces

 SPI up to 10 Mbit/s

 I 2 C-bus interface up to 400 kBd in Fast mode, up to 3400 kBd in High-speed mode

 RS232 Serial UART up to 1228.8 kBd, with voltage levels dependant on pin voltage supply

 FIFO buffer handles 64 byte send and receive

 Flexible interrupt modes

 Hard reset with low power function

 Power-down by software mode

 Programmable timer

 Internal oscillator for connection to 27.12 MHz quartz crystal

 2.5 V to 3.3 V power supply

 CRC coprocessor

 Programmable I/O pins

 Internal self-test

4. Quick reference data

Table 1.

Quick reference data

Symbol Parameter

V

DDA

V

DDD analog supply voltage digital supply voltage

V

DD(TVDD)

TVDD supply voltage

V

DD(PVDD)

PVDD supply voltage

V

DD(SVDD)

SVDD supply voltage

Conditions

V

DD(PVDD)

 V

DDA

= V

DDD

= V

DD(TVDD)

;

V

SSA

= V

SSD

= V

SS(PVSS)

= V

SS(TVSS)

= 0 V

V

SSA

= V

SSD

= V

SS(PVSS)

= V

SS(TVSS)

= 0 V

Min Typ Max Unit

[1][2]

2.5

3.3

3.6

V

2.5

3.3

3.6

V

2.5

[3]

1.6

1.6

-

3.3

1.8

3.6

3.6

3.6

V

V

V

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Table 1.

Quick reference data …continued

I

Symbol Parameter pd power-down current

Conditions

V

DDA

= V

DDD

= V

DD(TVDD)

= V

DD(PVDD)

= 3 V hard power-down; pin NRSTPD set LOW

I

I

DDD

DDA digital supply current analog supply current soft power-down; RF level detector on pin DVDD; V

DDD

= 3 V pin AVDD; V

DDA

RcvOff bit = 0

= 3 V, CommandReg register’s

I

I

T

DD(PVDD)

DD(TVDD) amb

PVDD supply current

TVDD supply current ambient temperature pin AVDD; receiver switched off; V

DDA

= 3 V,

CommandReg register’s RcvOff bit = 1 pin PVDD pin TVDD; continuous wave

HVQFN32

[4]

[4]

-

-

-

-

-

Min

[5]

-

[6][7][8]

-

25

-

-

-

-

Typ

6.5

7

3

60

Max

5

10

9

10

5

40

Unit

A

A mA mA mA mA

100 mA

+85

C

[1] Supply voltages below 3 V reduce the performance in, for example, the achievable operating distance.

[2] V

DDA

, V

DDD

and V

DD(TVDD)

must always be the same voltage.

[3] V

DD(PVDD)

must always be the same or lower voltage than V

DDD

.

[4] I pd

is the total current for all supplies.

[5] I

DD(PVDD)

depends on the overall load at the digital pins.

[6] I

DD(TVDD)

depends on V

DD(TVDD)

and the external circuit connected to pins TX1 and TX2.

[7] During typical circuit operation, the overall current is below 100 mA.

[8] Typical value using a complementary driver configuration and an antenna matched to 40

 between pins TX1 and TX2 at 13.56 MHz.

Table 2.

Ordering information

Type number Package

Name

MFRC52201HN1/TRAYB [1]

MFRC52201HN1/TRAYBM

MFRC52202HN1/TRAYB [1]

MFRC52202HN1/TRAYBM

[2]

[2]

Description

HVQFN32 plastic thermal enhanced very thin quad flat package; no leads;

32 terminal; body 5

 5  0.85 mm


32 terminal; body 5

 5  0.85 mm


32 terminal; body 5

 5  0.85 mm


32 terminal; body 5

 5  0.85 mm

[1] Delivered in one tray.

[2] Delivered in five trays.

Version

SOT617-1

SOT617-1

SOT617-1

SOT617-1

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The analog interface handles the modulation and demodulation of the analog signals.

The contactless UART manages the protocol requirements for the communication protocols in cooperation with the host. The FIFO buffer ensures fast and convenient data transfer to and from the host and the contactless UART and vice versa.

Various host interfaces are implemented to meet different customer requirements.

ANTENNA

ANALOG

INTERFACE

CONTACTLESS

UART

FIFO

BUFFER

REGISTER BANK

SERIAL UART

SPI

I

2

C-BUS

HOST

001aaj627

Fig 1.

Simplified block diagram of the MFRC522

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SDA/NSS/RX EA I2C

24 32 1

D6/ADR_0/

D2/ADR_4

D1/ADR_5

D4/ADR_2

D3/ADR_3

MOSI/MX

D5/ADR_1/

SCK/DTRQ

D7/SCL/

MISO/TX

25 26 27 28 29 30 31

PVDD PVSS

2 5

SPI, UART, I

2

C-BUS INTERFACE CONTROL

FIFO CONTROL

64-BYTE FIFO

BUFFER

STATE MACHINE

COMMAND REGISTER

PROGRAMABLE TIMER

CONTROL REGISTER

BANK

INTERRUPT CONTROL

VOLTAGE

MONITOR

AND

POWER ON

DETECT

3

4

DVDD

DVSS

15

18

AVDD

AVSS

RESET

CONTROL

POWER-DOWN

CONTROL

6

NRSTPD

23

IRQ

MIFARE CLASSIC UNIT

RANDOM NUMBER

GENERATOR

CRC16

GENERATION AND CHECK

PARALLEL/SERIAL

CONVERTER

BIT COUNTER

PARITY GENERATION AND CHECK

FRAME GENERATION AND CHECK

BIT DECODING BIT ENCODING

AMPLITUDE

RATING

REFERENCE

VOLTAGE

ANALOG TO DIGITAL

CONVERTER

ANALOG TEST

MULTIPLEXOR

AND

DIGITAL TO

ANALOG

CONVERTER

I-CHANNEL

AMPLIFIER

I-CHANNEL

DEMODULATOR

Q-CHANNEL

AMPLIFIER

Q-CHANNEL

DEMODULATOR

16 19 20 17

VMID AUX1 AUX2 RX

Fig 2.

Detailed block diagram of the MFRC522

SERIAL DATA SWITCH

CLOCK

GENERATION,

FILTERING AND

DISTRIBUTION

Q-CLOCK

GENERATION

TRANSMITTER CONTROL

OSCILLATOR

7

8

9

MFIN

MFOUT

SVDD

21

OSCIN

22

OSCOUT

TEMPERATURE

SENSOR

10, 14

TVSS

11

TX1

13

TX2

12

TVDD 001aak602

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I2C

PVDD

DVDD

DVSS

PVSS

NRSTPD

MFIN

MFOUT

1

2

3

4

5

6

7

8

MFRC522

24

23

22

21

20

19

18

17

SDA/NSS/RX

IRQ

OSCOUT

OSCIN

AUX2

AUX1

AVSS

RX

001aaj819

Transparent top view

Fig 3.

Pinning configuration HVQFN32 (SOT617-1)

7.1 Pin description

10

11

12

13

7

8

9

14

15

5

6

3

4

Table 3.

Pin description

Pin Symbol Type

[1]

1

2

I2C

PVDD

I

P

DVDD

DVSS

PVSS

NRSTPD I

P

G

G

Description

I 2 C-bus enable input

[2]

pin power supply digital power supply digital ground

[3]

MFIN

MFOUT

SVDD

TVSS

TX1

TVDD

TX2

TVSS

AVDD

I

O

P

G

O

P

O

G

P pin power supply ground reset and power-down input: power-down: enabled when LOW; internal current sinks are switched off, the oscillator is inhibited and the input pins are disconnected from the outside world reset: enabled by a positive edge

MIFARE signal input

MIFARE signal output

MFIN and MFOUT pin power supply transmitter output stage 1 ground transmitter 1 modulated 13.56 MHz energy carrier output transmitter power supply: supplies the output stage of transmitters 1 and 2 transmitter 2 modulated 13.56 MHz energy carrier output transmitter output stage 2 ground analog power supply

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Table 3.

Pin description …continued

Pin Symbol Type [1] Description

16 VMID P internal reference voltage

17

18

19

20

21

RX

AVSS

AUX1

AUX2

OSCIN

I

I

G

O

O

RF signal input analog ground auxiliary outputs for test purposes

22

23

24

25

OSCOUT

IRQ

SDA

NSS

RX

D1

ADR_5

I

I

O

O

I/O

I/O

I/O auxiliary outputs for test purposes crystal oscillator inverting amplifier input; also the input for an externally generated clock

(f clk

= 27.12 MHz) crystal oscillator inverting amplifier output interrupt request output: indicates an interrupt event

I 2 C-bus serial data line input/output

[2]

SPI signal input

[2]

UART address input [2]

test port

[2]

I 2

C-bus address 5 input [2]

26

27

28

29

30

31

32

D2

ADR_4

D3

ADR_3

D4

ADR_2

D5

ADR_1

SCK

DTRQ

D6

ADR_0

MOSI

MX

D7

SCL

MISO

TX

EA

I

I

I/O

I

I/O

I

I/O

I

I/O

I

O

I/O

I/O

O

I/O

I/O

I/O

I

O test port

I 2


test port

I 2


test port

I 2


test port

I 2


SPI serial clock input [2]

UART request to send output to microcontroller [2]

test port

I 2


SPI master out, slave in [2]

UART output to microcontroller

[2]

test port

I 2 C-bus clock input/output

[2]

SPI master in, slave out [2]

UART data output to microcontroller

[2]

external address input for coding I 2

C-bus address [2]

[1] Pin types: I = Input, O = Output, I/O = Input/Output, P = Power and G = Ground.

[2] The pin functionality of these pins is explained in

Section 8.1 “Digital interfaces” .

[3] Connection of heatsink pad on package bottom side is not necessary. Optional connection to pin DVSS is possible.

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The MFRC522 transmission module supports the Read/Write mode for

ISO/IEC 14443 A/MIFARE using various transfer speeds and modulation protocols.

BATTERY

MFRC522 ISO/IEC 14443 A CARD

MICROCONTROLLER reader/writer

Fig 4.

MFRC522 Read/Write mode contactless card

001aak583

The physical level communication is shown in

Figure 5 .

(1)

ISO/IEC 14443 A

READER

MFRC522

(2)

ISO/IEC 14443 A CARD

001aak584

(1) Reader to card 100 % ASK, Miller encoded, transfer speed 106 kBd to 848 kBd.

(2) Card to reader subcarrier load modulation, Manchester encoded or BPSK, transfer speed 106 kBd to 848 kBd.

Fig 5.

ISO/IEC 14443 A/MIFARE Read/Write mode communication diagram

The physical parameters are described in

Table 4

.

Table 4.

Communication overview for ISO/IEC 14443 A/MIFARE reader/writer

Communication direction

Signal type Transfer speed

Reader to card (send data from the

MFRC522 to a card) reader side modulation bit encoding

106 kBd

100 % ASK

212 kBd

100 % ASK

424 kBd

100 % ASK bit length modified Miller encoding

128 (13.56

s) modified Miller encoding

64 (13.56

s) modified Miller encoding

32 (13.56

s)

Card to reader

(MFRC522 receives data from a card) card side modulation subcarrier frequency subcarrier load modulation

13.56 MHz / 16 subcarrier load modulation

13.56 MHz / 16 subcarrier load modulation

13.56 MHz / 16 bit encoding Manchester encoding

BPSK BPSK

848 kBd

100 % ASK modified Miller encoding

16 (13.56

s) subcarrier load modulation

13.56 MHz / 16

BPSK

The MFRC522’s contactless UART and dedicated external host must manage the complete ISO/IEC 14443 A/MIFARE protocol.

Figure 6 shows the data coding and

framing according to ISO/IEC 14443 A/MIFARE.

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ISO/IEC 14443 A framing at 106 kBd start

8-bit data start bit is 1 odd parity

8-bit data odd parity


ISO/IEC 14443 A framing at 212 kBd, 424 kBd and 848 kBd start

8-bit data odd parity start bit is 0 burst of 32 subcarrier clocks


8-bit data even parity even parity at the end of the frame

001aak585

Fig 6.

Data coding and framing according to ISO/IEC 14443 A

The internal CRC coprocessor calculates the CRC value based on ISO/IEC 14443 A part 3 and handles parity generation internally according to the transfer speed. Automatic parity generation can be switched off using the MfRxReg register’s ParityDisable bit.

8.1 Digital interfaces

8.1.1 Automatic microcontroller interface detection

The MFRC522 supports direct interfacing of hosts using SPI, I 2 C-bus or serial UART interfaces. The MFRC522 resets its interface and checks the current host interface type automatically after performing a power-on or hard reset. The MFRC522 identifies the host interface by sensing the logic levels on the control pins after the reset phase. This is done using a combination of fixed pin connections.

Table 5

shows the different connection configurations.

D6

D5

D4

D3

D2

D1

Table 5.

Connection protocol for detecting different interface types

Pin Interface type

UART (input) SPI (output) I 2 C-bus (I/O)

SDA

I2C

EA

D7

RX

0

0

TX

NSS

0

1

MISO

SDA

1

EA

SCL

-

-

-

-

MX

DTRQ

-

-

-

-

MOSI

SCK

ADR_0

ADR_1

ADR_2

ADR_3

ADR_4

ADR_5

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8.1.2 Serial Peripheral Interface

A serial peripheral interface (SPI compatible) is supported to enable high-speed communication to the host. The interface can handle data speeds up to 10 Mbit/s. When communicating with a host, the MFRC522 acts as a slave, receiving data from the external host for register settings, sending and receiving data relevant for RF interface communication.

An interface compatible with SPI enables high-speed serial communication between the

MFRC522 and a microcontroller. The implemented interface is in accordance with the SPI standard.

The timing specification is given in

Section 14.1 on page 78

.

SCK

MOSI

MISO

NSS

MFRC522

SCK

MOSI

MISO

NSS

001aak586

Fig 7.

SPI connection to host

The MFRC522 acts as a slave during SPI communication. The SPI clock signal SCK must be generated by the master. Data communication from the master to the slave uses the

MOSI line. The MISO line is used to send data from the MFRC522 to the master.

Data bytes on both MOSI and MISO lines are sent with the MSB first. Data on both MOSI and MISO lines must be stable on the rising edge of the clock and can be changed on the falling edge. Data is provided by the MFRC522 on the falling clock edge and is stable during the rising clock edge.

8.1.2.1

SPI read data

Reading data using SPI requires the byte order shown in Table 6

to be used. It is possible to read out up to n-data bytes.

The first byte sent defines both the mode and the address.

Table 6.

MOSI and MISO byte order

Line

MOSI

MISO

Byte 0 address 0

X

[1]

Byte 1 address 1 data 0

Byte 2 address 2 data 1

[1] X = Do not care.

To

...

...

Remark: The MSB must be sent first.

Byte n address n data n

 1

Byte n + 1

00 data n

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8.1.2.2

SPI write data

To write data to the MFRC522 using SPI requires the byte order shown in

Table 7

. It is possible to write up to n data bytes by only sending one address byte.

The first send byte defines both the mode and the address byte.

Table 7.

MOSI and MISO byte order

Line

MOSI

MISO

Byte 0 address 0

X

[1]

Byte 1 data 0

X [1]

Byte 2 data 1

X [1]


To

...

...

Byte n data n

 1

X [1]

Remark: The MSB must be sent first.

Byte n + 1 data n

X [1]

8.1.2.3

SPI address byte

The address byte must meet the following format.

The MSB of the first byte defines the mode used. To read data from the MFRC522 the

MSB is set to logic 1. To write data to the MFRC522 the MSB must be set to logic 0. Bits 6 to 1 define the address and the LSB is set to logic 0.

Table 8.

Address byte 0 register; address MOSI

7 (MSB)

1 = read

0 = write

6 address

5 4 3 2 1 0 (LSB)

0

8.1.3 UART interface

8.1.3.1

Connection to a host

RX

TX

RX

MFRC522

TX

DTRQ

MX

DTRQ

MX

001aak587

Fig 8.

UART connection to microcontrollers

Remark: Signals DTRQ and MX can be disabled by clearing TestPinEnReg register’s

RS232LineEn bit.

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8.1.3.2

Selectable UART transfer speeds

The internal UART interface is compatible with an RS232 serial interface.

The default transfer speed is 9.6 kBd. To change the transfer speed, the host controller must write a value for the new transfer speed to the SerialSpeedReg register. Bits

BR_T0[2:0] and BR_T1[4:0] define the factors for setting the transfer speed in the

SerialSpeedReg register.

The BR_T0[2:0] and BR_T1[4:0] settings are described in

Table 9

. Examples of different

transfer speeds and the relevant register settings are given in Table 10 .

Table 9.

BR_T0 and BR_T1 settings

BR_Tn

BR_T0 factor

BR_T1 range

Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7

1 1 2 4 8 16 32 64

1 to 32 33 to 64 33 to 64 33 to 64 33 to 64 33 to 64 33 to 64 33 to 64

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Table 10.

Selectable UART transfer speeds

Transfer speed (kBd) SerialSpeedReg value

7.2

9.6

14.4

Decimal

250

235

218

Hexadecimal

FAh

EBh

DAh

19.2

38.4

57.6

115.2

128

230.4

460.8

921.6

1228.8

203

171

154

122

116

90

58

28

21

CBh

ABh

9Ah

7Ah

74h

5Ah

3Ah

1Ch

15h

[1] The resulting transfer speed error is less than 1.5 % for all described transfer speeds.

Transfer speed accuracy

(%) [1]

0.25

0.32

0.25

0.32

0.32

0.25

0.25

0.06

0.25

0.25

1.45

0.32

The selectable transfer speeds shown in Table 10

are calculated according to the following equations:

If BR_T0[2:0] = 0: transfer speed =



27.12

10

6

BR_T0 + 1



(1)

If BR_T0[2:0] > 0: transfer speed =









27.12

2

10 6

BR_T1 + 33



BR_T0 – 1











(2)

Remark: Transfer speeds above 1228.8 kBd are not supported.



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RX

8.1.3.3

UART framing

Table 11.

UART framing

Bit

Start

Data

Stop

Length

1-bit

8 bits

1-bit

Value

0 data

1

Remark: The LSB for data and address bytes must be sent first. No parity bit is used during transmission.

Read data: To read data using the UART interface, the flow shown in

Table 12

must be used. The first byte sent defines both the mode and the address.

Table 12.

Read data byte order

Pin Byte 0

RX (pin 24)

TX (pin 31) address

Byte 1

data 0

ADDRESS

SA A0 A1 A2 A3 A4 A5 (1) R/W SO

TX

DATA

SA D0 D1 D2 D3 D4 D5 D6 D7 SO

MX

DTRQ

001aak588

(1) Reserved.

Fig 9.

UART read data timing diagram

Write data: To write data to the MFRC522 using the UART interface, the structure shown in

Table 13 must be used.

The first byte sent defines both the mode and the address.

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Table 13.

Write data byte order

Pin Byte 0

RX (pin 24)

TX (pin 31) address 0

MFRC522


Byte 1 data 0 address 0

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RX

ADDRESS

SA A0 A1 A2 A3 A4 A5 (1) R/W SO

DATA

SA D0 D1 D2 D3 D4 D5 D6 D7 SO

TX

ADDRESS

SA A0 A1 A2 A3 A4 A5 (1) R/W SO

MX

DTRQ

001aak589

(1) Reserved.

Fig 10. UART write data timing diagram

Remark: The data byte can be sent directly after the address byte on pin RX.

Address byte: The address byte has to meet the following format:

The MSB of the first byte sets the mode used. To read data from the MFRC522, the MSB is set to logic 1. To write data to the

MFRC522 the MSB is set to logic 0. Bit 6 is reserved for future use, and bits 5 to 0 define the address; see Table 14

.


MFRC522


Table 14.

Address byte 0 register; address MOSI

7 (MSB)

1 = read

0 = write

6 5 reserved address

4 3 2 1 0 (LSB)

8.1.4 I 2 C-bus interface

An I 2 C-bus (Inter-IC) interface is supported to enable a low-cost, low pin count serial bus interface to the host. The I 2 C-bus interface is implemented according to

NXP Semiconductors’ I 2 C-bus interface specification, rev. 2.1, January 2000. The interface can only act in Slave mode. Therefore the MFRC522 does not implement clock generation or access arbitration.

PULL-UP

NETWORK

PULL-UP

NETWORK

MFRC522

SDA

SCL

MICROCONTROLLER

CONFIGURATION

WIRING

I2C

EA

ADR_[5:0]

001aak590

Fig 11. I 2 C-bus interface

The MFRC522 can act either as a slave receiver or slave transmitter in Standard mode,

Fast mode and High-speed mode.

SDA is a bidirectional line connected to a positive supply voltage using a current source or a pull-up resistor. Both SDA and SCL lines are set HIGH when data is not transmitted. The

MFRC522 has a 3-state output stage to perform the wired-AND function. Data on the

I 2 C-bus can be transferred at data rates of up to 100 kBd in Standard mode, up to

400 kBd in Fast mode or up to 3.4 Mbit/s in High-speed mode.

If the I 2 C-bus interface is selected, spike suppression is activated on lines SCL and SDA as defined in the I 2 C-bus interface specification.

See

Table 155 on page 79 for timing requirements.

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8.1.4.1

Data validity

Data on the SDA line must be stable during the HIGH clock period. The HIGH or LOW state of the data line must only change when the clock signal on SCL is LOW.

SDA

SCL

Fig 12. Bit transfer on the I 2 C-bus data line stable; data valid change of data allowed mbc621

8.1.4.2

START and STOP conditions

To manage the data transfer on the I 2 C-bus, unique START (S) and STOP (P) conditions are defined.

• A START condition is defined with a HIGH-to-LOW transition on the SDA line while

SCL is HIGH.

• A STOP condition is defined with a LOW-to-HIGH transition on the SDA line while

SCL is HIGH.

The I 2 C-bus master always generates the START and STOP conditions. The bus is busy after the START condition. The bus is free again a certain time after the STOP condition.

The bus stays busy if a repeated START (Sr) is generated instead of a STOP condition.

The START (S) and repeated START (Sr) conditions are functionally identical. Therefore,

S is used as a generic term to represent both the START (S) and repeated START (Sr) conditions.

SDA SDA

SCL SCL

S

START condition

P

STOP condition mbc622

Fig 13. START and STOP conditions

8.1.4.3

Byte format

Each byte must be followed by an acknowledge bit. Data is transferred with the MSB first;

see Figure 16 . The number of transmitted bytes during one data transfer is unrestricted

but must meet the read/write cycle format.

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8.1.4.4

Acknowledge

An acknowledge must be sent at the end of one data byte. The acknowledge-related clock pulse is generated by the master. The transmitter of data, either master or slave, releases the SDA line (HIGH) during the acknowledge clock pulse. The receiver pulls down the

SDA line during the acknowledge clock pulse so that it remains stable LOW during the

HIGH period of this clock pulse.

The master can then generate either a STOP (P) condition to stop the transfer or a repeated START (Sr) condition to start a new transfer.

A master-receiver indicates the end of data to the slave-transmitter by not generating an acknowledge on the last byte that was clocked out by the slave. The slave-transmitter releases the data line to allow the master to generate a STOP (P) or repeated START (Sr) condition.

data output by transmitter not acknowledge data output by receiver

SDA

SCL from master

1

S

START condition

Fig 14. Acknowledge on the I 2 C-bus

MSB

SCL

S or

Sr

START or repeated START condition

1 2

2 acknowledge

8 9 clock pulse for acknowledgement mbc602

7

P acknowledgement signal from slave byte complete, interrupt within slave clock line held LOW while interrupts are serviced acknowledgement signal from receiver

Sr

8 9

ACK

1 2 3 - 8 9

ACK

Sr or

P

STOP or repeated START condition msc608

Fig 15. Data transfer on the I 2 C-bus

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8.1.4.5

7-Bit addressing

During the I 2 C-bus address procedure, the first byte after the START condition is used to determine which slave will be selected by the master.

Several address numbers are reserved. During device configuration, the designer must ensure that collisions with these reserved addresses cannot occur. Check the I 2 C-bus

specification for a complete list of reserved addresses.

The I 2 C-bus address specification is dependent on the definition of pin EA. Immediately after releasing pin NRSTPD or after a power-on reset, the device defines the I 2 C-bus address according to pin EA.

If pin EA is set LOW, the upper 4 bits of the device bus address are reserved by

NXP Semiconductors and set to 0101b for all MFRC522 devices. The remaining 3 bits

(ADR_0, ADR_1, ADR_2) of the slave address can be freely configured by the customer to prevent collisions with other I 2 C-bus devices.

If pin EA is set HIGH, ADR_0 to ADR_5 can be completely specified at the external pins according to

Table 5 on page 9 . ADR_6 is always set to logic 0.

In both modes, the external address coding is latched immediately after releasing the reset condition. Further changes at the used pins are not taken into consideration.

Depending on the external wiring, the I 2 C-bus address pins can be used for test signal outputs.

MSB LSB bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 R/W slave address

Fig 16. First byte following the START procedure

001aak591

8.1.4.6

Register write access

To write data from the host controller using the I 2 C-bus to a specific register in the

MFRC522 the following frame format must be used.

• The first byte of a frame indicates the device address according to the I 2 C-bus rules.

• The second byte indicates the register address followed by up to n-data bytes.

In one frame all data bytes are written to the same register address. This enables fast

FIFO buffer access. The Read/Write (R/W) bit is set to logic 0.

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S

8.1.4.7

Register read access

To read out data from a specific register address in the MFRC522, the host controller must use the following procedure:

• Firstly, a write access to the specific register address must be performed as indicated in the frame that follows

• The first byte of a frame indicates the device address according to the I 2 C-bus rules

• The second byte indicates the register address. No data bytes are added

• The Read/Write bit is 0

After the write access, read access can start. The host sends the device address of the

MFRC522. In response, the MFRC522 sends the content of the read access register. In one frame all data bytes can be read from the same register address. This enables fast

FIFO buffer access or register polling.

The Read/Write (R/W) bit is set to logic 1.

I

2

C-BUS

SLAVE ADDRESS

[A7:A0]

0

(W)

A 0 write cycle

0

JOINER REGISTER

ADDRESS [A5:A0]

A [0:n]

DATA

[7:0]

A

P

S read cycle

I

2

C-BUS

SLAVE ADDRESS

[A7:A0]

0

(W)

A 0 0

JOINER REGISTER

ADDRESS [A5:A0] optional, if the previous access was on the same register address

[0:n]

A

S

I

2

C-BUS

SLAVE ADDRESS

[A7:A0]

1

(R)

A [0:n]

DATA

[7:0]

A

P sent by master

S

P

A start condition stop condition acknowledge

DATA

[7:0]

A P

A not acknowledge

W write cycle

R read cycle sent by slave

Fig 17. Register read and write access

001aak592

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8.1.4.8

High-speed mode

In High-speed mode (HS mode), the device can transfer information at data rates of up to

3.4 Mbit/s, while remaining fully downward-compatible with Fast or Standard mode

(F/S mode) for bidirectional communication in a mixed-speed bus system.

8.1.4.9

High-speed transfer

To achieve data rates of up to 3.4 Mbit/s the following improvements have been made to

I 2 C-bus operation.

• The inputs of the device in HS mode incorporate spike suppression, a Schmitt trigger on the SDA and SCL inputs and different timing constants when compared to

F/S mode

• The output buffers of the device in HS mode incorporate slope control of the falling edges of the SDA and SCL signals with different fall times compared to F/S mode

8.1.4.10

Serial data transfer format in HS mode

The HS mode serial data transfer format meets the Standard mode I 2 C-bus specification.

HS mode can only start after all of the following conditions (all of which are in F/S mode):

1. START condition (S)

2. 8-bit master code (00001XXXb)

3. Not-acknowledge bit (A)

When HS mode starts, the active master sends a repeated START condition (Sr) followed by a 7-bit slave address with a R/W bit address and receives an acknowledge bit (A) from the selected MFRC522.

Data transfer continues in HS mode after the next repeated START (Sr), only switching back to F/S mode after a STOP condition (P). To reduce the overhead of the master code, a master links a number of HS mode transfers, separated by repeated START conditions

(Sr).

F/S mode HS mode (current-source for SCL HIGH enabled) F/S mode

S MASTER CODE A Sr SLAVE ADDRESS R/W A DATA

(n-bytes + A)

A/A P

HS mode continues

Sr SLAVE ADDRESS

001aak749

Fig 18. I 2 C-bus HS mode protocol switch

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SDA high

S

8-bit master code 0000 1xxx A t

1 t

H

SCL high

1 2 to 5 6

F/S mode

7 8 9

Sr

7-bit SLA R/W A n + (8-bit data + A/A)

Sr P

SDA high

SCL high

1 2 to 5 6 7 8 9 1

HS mode

2 to 5 6 7 8 9 t

H

= Master current source pull-up

= Resistor pull-up

Fig 19. I 2 C-bus HS mode protocol frame t

FS

If P then

F/S mode

If Sr (dotted lines) then HS mode msc618

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8.1.4.11

Switching between F/S mode and HS mode

After reset and initialization, the MFRC522 is in Fast mode (which is in effect F/S mode as

Fast mode is downward-compatible with Standard mode). The connected MFRC522 recognizes the “S 00001XXX A” sequence and switches its internal circuitry from the Fast mode setting to the HS mode setting.

The following actions are taken:

1. Adapt the SDA and SCL input filters according to the spike suppression requirement in HS mode.

2. Adapt the slope control of the SDA output stages.

It is possible for system configurations that do not have other I 2 C-bus devices involved in the communication to switch to HS mode permanently. This is implemented by setting

Status2Reg register’s I 2 CForceHS bit to logic 1. In permanent HS mode, the master code is not required to be sent. This is not defined in the specification and must only be used when no other devices are connected on the bus. In addition, spikes on the I 2 C-bus lines must be avoided because of the reduced spike suppression.

8.1.4.12

MFRC522 at lower speed modes

MFRC522 is fully downward-compatible and can be connected to an F/S mode I 2 C-bus system. The device stays in F/S mode and communicates at F/S mode speeds because a master code is not transmitted in this configuration.

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8.2 Analog interface and contactless UART

8.2.1 General

The integrated contactless UART supports the external host online with framing and error checking of the protocol requirements up to 848 kBd. An external circuit can be connected to the communication interface pins MFIN and MFOUT to modulate and demodulate the data.

The contactless UART handles the protocol requirements for the communication protocols in cooperation with the host. Protocol handling generates bit and byte-oriented framing. In addition, it handles error detection such as parity and CRC, based on the various supported contactless communication protocols.

Remark: The size and tuning of the antenna and the power supply voltage have an important impact on the achievable operating distance.

8.2.2 TX p-driver

The signal on pins TX1 and TX2 is the 13.56 MHz energy carrier modulated by an envelope signal. It can be used to drive an antenna directly using a few passive components for matching and filtering; see

Section 15 on page 81 . The signal on pins TX1

and TX2 can be configured using the TxControlReg register; see

Section 9.3.2.5 on page 50

.

The modulation index can be set by adjusting the impedance of the drivers. The impedance of the p-driver can be configured using registers CWGsPReg and

ModGsPReg. The impedance of the n-driver can be configured using the GsNReg register. The modulation index also depends on the antenna design and tuning.

The TxModeReg and TxSelReg registers control the data rate and framing during transmission and the antenna driver setting to support the different requirements at the different modes and transfer speeds.

Table 15.

Register and bit settings controlling the signal on pin TX1

Bit

Tx1RFEn

0

Bit

Force

100ASK

X

[1]

Bit

InvTx1RFOn

X

[1]

Bit

InvTx1RFOff

X

[1]

Envelope

X

[1]

Pin

TX1

X [1]

GSPMos GSNMos Remarks

X [1]

X

[1]

not specified if RF is switched off

1 0

0

0

1

X

[1]

X

[1]

0

1

0

1

RF

RF

RF

RF pMod pCW pMod pCW nMod nCW nMod nCW

100 % ASK: pin TX1 pulled to logic 0, independent of the

InvTx1RFOff bit

1 1 X

[1]

0

1

0

RF_n pMod pCW nMod nCW


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Table 16.

Register and bit settings controlling the signal on pin TX2

Bit

Tx1RFEn

0

Bit

Force

100ASK

X [1]

Bit

Tx2CW

X [1]

Bit

InvTx2RFOn

X [1]

Bit

InvTx2RFOff

X [1]

Envelope Pin

X [1]

TX2

X [1]

GSPMos GSNMos Remarks

X

[1]

X

[1]

1 0 0 0

X [1]

not specified if

RF is switched off

1

1

0

1

1

0

1

0

1

0

1

X

X

X

X

X

X

X

[1]

[1]

[1]

[1]

[1]

[1]

[1]

0

1

0

1

X [1]

X [1]

0

1

0

1

X [1]

X [1]

RF pMod

RF pCW

RF_n pMod

RF_n pCW

RF pCW

RF_n pCW

0

RF pMod pCW

0 pMod

RF_n pCW

RF pCW

RF_n pCW nMod nCW nMod nCW nCW nCW nMod nCW nMod nCW nCW nCW conductance always CW for the Tx2CW bit

100 % ASK: pin

TX2 pulled to logic 0

(independent of the

InvTx2RFOn/Inv

Tx2RFOff bits)


The following abbreviations have been used in

Table 15

and

Table 16

:

• RF: 13.56 MHz clock derived from 27.12 MHz quartz crystal oscillator divided by 2

• RF_n: inverted 13.56 MHz clock

• GSPMos: conductance, configuration of the PMOS array

• GSNMos: conductance, configuration of the NMOS array

• pCW: PMOS conductance value for continuous wave defined by the CWGsPReg register

• pMod: PMOS conductance value for modulation defined by the ModGsPReg register

• nCW: NMOS conductance value for continuous wave defined by the GsNReg register’s CWGsN[3:0] bits

• nMod: NMOS conductance value for modulation defined by the GsNReg register’s

ModGsN[3:0] bits

• X = do not care.

Remark: If only one driver is switched on, the values for CWGsPReg, ModGsPReg and

GsNReg registers are used for both drivers.

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8.2.3 Serial data switch

Two main blocks are implemented in the MFRC522. The digital block comprises the state machines, encoder/decoder logic. The analog block comprises the modulator and antenna drivers, the receiver and amplifiers. It is possible for the interface between these two blocks to be configured so that the interfacing signals are routed to pins MFIN and

MFOUT.

This topology allows the analog block of the MFRC522 to be connected to the digital block of another device.

The serial signal switch is controlled by the TxSelReg and RxSelReg registers.

Figure 20

shows the serial data switch for p-driver TX1 and TX2.

INTERNAL

CODER

MFIN

INVERT IF

InvMod = 1 envelope

3-state

1

DriverSel[1:0]

00

01

10

11 to driver TX1 and TX2

0 = impedance = modulated

1 = impedance = CW

INVERT IF

PolMFin = 0

001aak593

Fig 20. Serial data switch for p-driver TX1 and TX2

8.2.4 MFIN and MFOUT interface support

The MFRC522 is divided into a digital circuit block and an analog circuit block. The digital block contains state machines, encoder and decoder logic and so on. The analog block contains the modulator and antenna drivers, receiver and amplifiers. The interface between these two blocks can be configured so that the interfacing signals can be routed to pins MFIN and MFOUT; see

Figure 21 on page 28

. This configuration is implemented using TxSelReg register’s MFOutSel[3:0] and DriverSel[1:0] bits and RxSelReg register’s

UARTSel[1:0] bits.

This topology allows some parts of the analog block to be connected to the digital block of another device.

Switch MFOutSel in the TxSelReg register can be used to measure MIFARE and

ISO/IEC14443 A related signals. This is especially important during the design-in phase or for test purposes as it enables checking of the transmitted and received data.

The most important use of pins MFIN and MFOUT is found in the active antenna concept.

An external active antenna circuit can be connected to the MFRC522’s digital block.

Switch MFOutSel must be configured so that the internal Miller encoded signal is sent to pin MFOUT (MFOutSel = 100b). UARTSel[1:0] must be configured to receive a

Manchester signal with subcarrier from pin MFIN (UARTSel[1:0] = 01).

It is possible to connect a passive antenna to pins TX1, TX2 and RX (using the appropriate filter and matching circuit) and an active antenna to pins MFOUT and MFIN at the same time. In this configuration, two RF circuits can be driven (one after another) by a single host processor.

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Remark: Pins MFIN and MFOUT have a dedicated supply on pin SVDD with the ground on pin PVSS. If pin MFIN is not used it must be connected to either pin SVDD or pin

PVSS. If pin SVDD is not used it must be connected to either pin DVDD, pin PVDD or any other voltage supply pin.

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xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx

MFOUT

TX bit stream

DIGITAL MODULE

MFRC522

MILLER

CODER

3-state

LOW

HIGH test bus internal envelope

TX serial data stream reserved

RX serial data stream

6

7

4

5

0

1

2

3

MFOutSel[3:0]

RX bit stream MANCHESTER

DECODER

UART

Sel[1:0]

0

1

2

3

LOW

Manchester with subcarrier

SUBCARRIER

DEMODULATOR internal modulated

NRZ coding without subcarrier (> 106 kBd)

3-state internal envelope envelope from pin MFIN

HIGH

0

1

2

3

DRIVER

Sel[1:0]

MODULATOR DRIVER

ANALOG MODULE

MFRC522

DEMODULATOR

TX2

TX1

RX

MFIN 001aak594

Fig 21. Overview of MFIN and MFOUT signal routing


MFRC522


8.2.5 CRC coprocessor

The following CRC coprocessor parameters can be configured:

• The CRC preset value can be either 0000h, 6363h, A671h or FFFFh depending on the ModeReg register’s CRCPreset[1:0] bits setting

• The CRC polynomial for the 16-bit CRC is fixed to x 16 + x 12 + x 5 + 1

• The CRCResultReg register indicates the result of the CRC calculation. This register is split into two 8-bit registers representing the higher and lower bytes.

• The ModeReg register’s MSBFirst bit indicates that data will be loaded with the MSB first.

Table 17.

CRC coprocessor parameters

Parameter Value

CRC register length

CRC algorithm

CRC preset value

16-bit CRC algorithm according to ISO/IEC 14443 A and ITU-T

0000h, 6363h, A671h or FFFFh depending on the setting of the

ModeReg register’s CRCPreset[1:0] bits

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8.3 FIFO buffer

An 8

 64 bit FIFO buffer is used in the MFRC522. It buffers the input and output data stream between the host and the MFRC522’s internal state machine. This makes it possible to manage data streams up to 64 bytes long without the need to take timing constraints into account.

8.3.1 Accessing the FIFO buffer

The FIFO buffer input and output data bus is connected to the FIFODataReg register.

Writing to this register stores one byte in the FIFO buffer and increments the internal FIFO buffer write pointer. Reading from this register shows the FIFO buffer contents stored in the FIFO buffer read pointer and decrements the FIFO buffer read pointer. The distance between the write and read pointer can be obtained by reading the FIFOLevelReg register.

When the microcontroller starts a command, the MFRC522 can, while the command is in progress, access the FIFO buffer according to that command. Only one FIFO buffer has been implemented which can be used for input and output. The microcontroller must ensure that there are not any unintentional FIFO buffer accesses.

8.3.2 Controlling the FIFO buffer

The FIFO buffer pointers can be reset by setting FIFOLevelReg register’s FlushBuffer bit to logic 1. Consequently, the FIFOLevel[6:0] bits are all set to logic 0 and the ErrorReg register’s BufferOvfl bit is cleared. The bytes stored in the FIFO buffer are no longer accessible allowing the FIFO buffer to be filled with another 64 bytes.

8.3.3 FIFO buffer status information

The host can get the following FIFO buffer status information:

• Number of bytes stored in the FIFO buffer: FIFOLevelReg register’s FIFOLevel[6:0]

• FIFO buffer almost full warning: Status1Reg register’s HiAlert bit


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• FIFO buffer almost empty warning: Status1Reg register’s LoAlert bit

• FIFO buffer overflow warning: ErrorReg register’s BufferOvfl bit. The BufferOvfl bit can only be cleared by setting the FIFOLevelReg register’s FlushBuffer bit.

The MFRC522 can generate an interrupt signal when:

• ComIEnReg register’s LoAlertIEn bit is set to logic 1. It activates pin IRQ when

Status1Reg register’s LoAlert bit changes to logic 1.

• ComIEnReg register’s HiAlertIEn bit is set to logic 1. It activates pin IRQ when

Status1Reg register’s HiAlert bit changes to logic 1.

If the maximum number of WaterLevel bytes (as set in the WaterLevelReg register) or less are stored in the FIFO buffer, the HiAlert bit is set to logic 1. It is generated according to

Equation 3 :

HiAlert =



64 – FIFOLength (3)

If the number of WaterLevel bytes (as set in the WaterLevelReg register) or less are stored in the FIFO buffer, the LoAlert bit is set to logic 1. It is generated according to

Equation 4 :

LoAlert = FIFOLength



WaterLevel (4)

8.4 Interrupt request system

The MFRC522 indicates certain events by setting the Status1Reg register’s IRq bit and, if activated, by pin IRQ. The signal on pin IRQ can be used to interrupt the host using its interrupt handling capabilities. This allows the implementation of efficient host software.

8.4.1 Interrupt sources overview

Table 18 shows the available interrupt bits, the corresponding source and the condition for

its activation. The ComIrqReg register’s TimerIRq interrupt bit indicates an interrupt set by the timer unit which is set when the timer decrements from 1 to 0.

The ComIrqReg register’s TxIRq bit indicates that the transmitter has finished. If the state changes from sending data to transmitting the end of the frame pattern, the transmitter unit automatically sets the interrupt bit. The CRC coprocessor sets the DivIrqReg register’s CRCIRq bit after processing all the FIFO buffer data which is indicated by

CRCReady bit = 1.

The ComIrqReg register’s RxIRq bit indicates an interrupt when the end of the received data is detected. The ComIrqReg register’s IdleIRq bit is set if a command finishes and the Command[3:0] value in the CommandReg register changes to idle (see

Table 149 on page 70

).

The ComIrqReg register’s HiAlertIRq bit is set to logic 1 when the Status1Reg register’s

HiAlert bit is set to logic 1 which means that the FIFO buffer has reached the level indicated by the WaterLevel[5:0] bits.

The ComIrqReg register’s LoAlertIRq bit is set to logic 1 when the Status1Reg register’s

LoAlert bit is set to logic 1 which means that the FIFO buffer has reached the level indicated by the WaterLevel[5:0] bits.


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The ComIrqReg register’s ErrIRq bit indicates an error detected by the contactless UART during send or receive. This is indicated when any bit is set to logic 1 in register ErrorReg.

Table 18.

Interrupt sources

Interrupt flag

IRq

TxIRq

CRCIRq

RxIRq

IdleIRq

HiAlertIRq

Interrupt source timer unit transmitter

CRC coprocessor receiver

Trigger action the timer counts from 1 to 0 a transmitted data stream ends all data from the FIFO buffer has been processed a received data stream ends

ComIrqReg register command execution finishes

FIFO buffer the FIFO buffer is almost full

LoAlertIRq

ErrIRq

FIFO buffer contactless UART the FIFO buffer is almost empty an error is detected

8.5 Timer unit

The MFRC522A has a timer unit which the external host can use to manage timing tasks.

The timer unit can be used in one of the following timer/counter configurations:

• Timeout counter

• Watchdog counter

• Stop watch

• Programmable one shot

• Periodical trigger

The timer unit can be used to measure the time interval between two events or to indicate that a specific event occurred after a specific time. The timer can be triggered by events explained in the paragraphs below. The timer does not influence any internal events, for example, a time-out during data reception does not automatically influence the reception process. Furthermore, several timer-related bits can be used to generate an interrupt.

The timer has an input clock of 13.56 MHz derived from the 27.12 MHz quartz crystal oscillator. The timer consists of two stages: prescaler and counter.

The prescaler (TPrescaler) is a 12-bit counter. The reload values (TReloadVal_Hi[7:0] and

TReloadVal_Lo[7:0]) for TPrescaler can be set between 0 and 4095 in the TModeReg register’s TPrescaler_Hi[3:0] bits and TPrescalerReg register’s TPrescaler_Lo[7:0] bits.

The reload value for the counter is defined by 16 bits between 0 and 65535 in the

TReloadReg register.

The current value of the timer is indicated in the TCounterValReg register.

When the counter reaches 0, an interrupt is automatically generated, indicated by the

ComIrqReg register’s TimerIRq bit setting. If enabled, this event can be indicated on pin IRQ. The TimerIRq bit can be set and reset by the host. Depending on the configuration, the timer will stop at 0 or restart with the value set in the TReloadReg register.

The timer status is indicated by the Status1Reg register’s TRunning bit.


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The timer can be started manually using the ControlReg register’s TStartNow bit and stopped using the ControlReg register’s TStopNow bit.

The timer can also be activated automatically to meet any dedicated protocol requirements by setting the TModeReg register’s TAuto bit to logic 1.

The delay time of a timer stage is set by the reload value + 1. The total delay time (t d1

) is calculated using

Equation 5 :

t d1

=



TPrescaler 2 + 1

  

TReloadVal + 1



13.56 MHz

(5)

An example of calculating total delay time (t d

) is shown in

Equation 6 , where the

TPrescaler value = 4095 and TReloadVal = 65535:

39.59 s =



4095 2 + 1

  

65535 + 1



13.56 MHz

Example: To give a delay time of 25

s requires 339 clock cycles to be counted and a

TPrescaler value of 169. This configures the timer to count up to 65535 time-slots for every 25

s period.

(6)

The MFRC522 version 2.0 offers in addition a second prescaler timer. Due to the fact that the prescaler counts down to 0 the prescaler period always count an odd number of clocks (1, 3, 5, ..). This may lead to inaccuracy. The second available prescaler timer implements the possibility to change the prescaler reload value to odd numbers, which results in an even prescaler period. This new prescaler can be enabled only in version 2.0

using the register bit DemodeReg, see Table 72 . Within this option, the total delay time

(t d2

) is calculated using

Equation 5

: t d2

=



TPrescaler 2 + 2

  

TReloadVal + 1



13.56 MHz

(7)

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8.6 Power reduction modes

8.6.1 Hard power-down

Hard power-down is enabled when pin NRSTPD is LOW. This turns off all internal current sinks including the oscillator. All digital input buffers are separated from the input pins and clamped internally (except pin NRSTPD). The output pins are frozen at either a HIGH or

LOW level.

8.6.2 Soft power-down mode

Soft Power-down mode is entered immediately after the CommandReg register’s

PowerDown bit is set to logic 1. All internal current sinks are switched off, including the oscillator buffer. However, the digital input buffers are not separated from the input pins and keep their functionality. The digital output pins do not change their state.

During soft power-down, all register values, the FIFO buffer content and the configuration keep their current contents.

After setting the PowerDown bit to logic 0, it takes 1024 clocks until the Soft power-down mode is exited indicated by the PowerDown bit. Setting it to logic 0 does not immediately clear it. It is cleared automatically by the MFRC522 when Soft power-down mode is exited.

Remark: If the internal oscillator is used, you must take into account that it is supplied by pin AVDD and it will take a certain time (t osc

) until the oscillator is stable and the clock cycles can be detected by the internal logic. It is recommended for the serial UART, to first send the value 55h to the MFRC522. The oscillator must be stable for further access to the registers. To ensure this, perform a read access to address 0 until the MFRC522 answers to the last read command with the register content of address 0. This indicates that the MFRC522 is ready.

8.6.3 Transmitter power-down mode

The Transmitter Power-down mode switches off the internal antenna drivers thereby, turning off the RF field. Transmitter power-down mode is entered by setting either the

TxControlReg register’s Tx1RFEn bit or Tx2RFEn bit to logic 0.

8.7 Oscillator circuit

MFRC522

OSCOUT OSCIN

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27.12 MHz

001aak595

Fig 22. Quartz crystal connection


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The clock applied to the MFRC522 provides a time basis for the synchronous system’s encoder and decoder. The stability of the clock frequency, therefore, is an important factor for correct operation. To obtain optimum performance, clock jitter must be reduced as much as possible. This is best achieved using the internal oscillator buffer with the recommended circuitry.

If an external clock source is used, the clock signal must be applied to pin OSCIN. In this case, special care must be taken with the clock duty cycle and clock jitter and the clock quality must be verified.

8.8 Reset and oscillator start-up time

8.8.1 Reset timing requirements

The reset signal is filtered by a hysteresis circuit and a spike filter before it enters the digital circuit. The spike filter rejects signals shorter than 10 ns. In order to perform a reset, the signal must be LOW for at least 100 ns.

8.8.2 Oscillator start-up time

If the MFRC522 has been set to a Power-down mode or is powered by a V

DDX

supply, the start-up time for the MFRC522 depends on the oscillator used and is shown in

Figure 23 .

The time (t startup

) is the start-up time of the crystal oscillator circuit. The crystal oscillator start-up time is defined by the crystal.

The time (t d

) is the internal delay time of the MFRC522 when the clock signal is stable before the MFRC522 can be addressed.

The delay time is calculated by: t d

=

1024

27

s

= 37.74

s

The time (t osc

) is the sum of t d

and t startup

.

(8) device activation oscillator clock stable clock ready t startup t osc t d t

001aak596

Fig 23. Oscillator start-up time

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9.1 Register bit behavior

Depending on the functionality of a register, the access conditions to the register can vary.

In principle, bits with same behavior are grouped in common registers. The access conditions are described in

Table 19

.

Table 19.

Behavior of register bits and their designation

Abbreviation Behavior

R/W

Description read and write These bits can be written and read by the microcontroller. Since they are used only for control purposes, their content is not influenced by internal state machines, for example the

ComIEnReg register can be written and read by the microcontroller. It will also be read by internal state machines but never changed by them.

D dynamic

R read only

These bits can be written and read by the microcontroller.

Nevertheless, they can also be written automatically by internal state machines, for example the CommandReg register changes its value automatically after the execution of the command.

These register bits hold values which are determined by internal states only, for example the CRCReady bit cannot be written externally but shows internal states.

W reserved

RFT write only

-

-

Reading these register bits always returns zero.

These registers are reserved for future use and must not be changed. In case of a write access, it is recommended to always write the value “0”.

These register bits are reserved for future use or are for production tests and must not be changed.

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9.2 Register overview

15h

16h

17h

18h

19h

1Ah

1Bh

1Ch

Table 20.

MFRC522 register overview

Address

(hex)

Register name Function

Page 0: Command and status

00h Reserved

01h

02h

CommandReg

ComlEnReg reserved for future use starts and stops command execution enable and disable interrupt request control bits

03h

04h

05h

06h

07h

08h

09h

0Ah

0Bh

0Ch

0Dh

0Eh

DivlEnReg

ComIrqReg

DivIrqReg

ErrorReg

Status1Reg

Status2Reg

FIFODataReg

FIFOLevelReg

WaterLevelReg

ControlReg

BitFramingReg

CollReg enable and disable interrupt request control bits interrupt request bits interrupt request bits error bits showing the error status of the last command executed communication status bits receiver and transmitter status bits input and output of 64 byte FIFO buffer number of bytes stored in the FIFO buffer level for FIFO underflow and overflow warning miscellaneous control registers adjustments for bit-oriented frames bit position of the first bit-collision detected on the RF interface reserved for future use 0Fh Reserved

Page 1: Command

10h

11h

Reserved

ModeReg

12h

13h

14h

TxModeReg

RxModeReg

TxControlReg

TxASKReg

TxSelReg

RxSelReg

RxThresholdReg

DemodReg

Reserved

Reserved

MfTxReg reserved for future use defines general modes for transmitting and receiving defines transmission data rate and framing defines reception data rate and framing controls the logical behavior of the antenna driver pins TX1 and TX2 controls the setting of the transmission modulation selects the internal sources for the antenna driver selects internal receiver settings selects thresholds for the bit decoder

Refer to

Table 21 on page 38

Table 23 on page 38

Table 25 on page 38

Table 27 on page 39

Table 29 on page 39

Table 31 on page 40

Table 33 on page 41

Table 35 on page 42

Table 37 on page 43

Table 39 on page 44

Table 41 on page 44

Table 43 on page 44

Table 45 on page 45

Table 47 on page 46

Table 49 on page 46

Table 51 on page 47

Table 53 on page 47

Table 55 on page 48

Table 57 on page 48

Table 59 on page 49

Table 61 on page 50

Table 63 on page 51

Table 65 on page 51

Table 67 on page 52

Table 69 on page 53

defines demodulator settings reserved for future use

Table 71 on page 53

Table 73 on page 54

reserved for future use

Table 75 on page 54

controls some MIFARE communication transmit parameters

Table 77 on page 55

1Dh

1Eh

MfRxReg

Reserved

1Fh SerialSpeedReg

Page 2: Configuration

20h Reserved controls some MIFARE communication receive parameters

Table 79 on page 55


Table 81 on page 55

selects the speed of the serial UART interface

Table 83 on page 55


Table 85 on page 57

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Table 20.

MFRC522 register overview …continued

Address

(hex)

Register name Function

21h CRCResultReg shows the MSB and LSB values of the CRC calculation

22h

23h

24h

25h

26h

27h

28h

29h

2Ah

2Bh

2Ch

Reserved

ModWidthReg

Reserved

RFCfgReg

GsNReg

CWGsPReg

ModGsPReg

TModeReg

TPrescalerReg

TReloadReg

Refer to defines the 16-bit timer reload value

Table 87 on page 57

Table 89 on page 57

Table 91 on page 58

reserved for future use controls the ModWidth setting reserved for future use defines the conductance of the p-driver output during periods of modulation defines settings for the internal timer

Table 93 on page 58

Table 95 on page 58

configures the receiver gain defines the conductance of the p-driver output during periods of no modulation

Table 97 on page 59

selects the conductance of the antenna driver pins TX1 and

TX2 for modulation

Table 99 on page 59






2Dh

2Eh

2Fh

30h

31h

32h

33h

34h

35h

36h

37h

TCounterValReg

Page 3: Test register

Reserved

TestSel1Reg

TestSel2Reg

TestPinEnReg

TestPinValueReg

TestBusReg

AutoTestReg

VersionReg

38h

39h

3Ah

3Bh

AnalogTestReg

TestDAC1Reg

TestDAC2Reg

TestADCReg

3Ch to 3Fh Reserved shows the 16-bit timer value reserved for future use general test signal configuration general test signal configuration and PRBS control enables pin output driver on pins D1 to D7 defines the values for D1 to D7 when it is used as an I/O bus


shows the status of the internal test bus


controls the digital self test shows the software version



controls the pins AUX1 and AUX2 defines the test value for TestDAC1 defines the test value for TestDAC2 shows the value of ADC I and Q channels reserved for production tests












Table 141 to on page 69

Table 147

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9.3 Register descriptions

9.3.1 Page 0: Command and status

9.3.1.1

Reserved register 00h

Functionality is reserved for future use.

Table 21.

Reserved register (address 00h); reset value: 00h bit allocation

Bit

Symbol

Access

7 6 5 4 reserved

-

3 2 1 0

Table 22.

Reserved register bit descriptions

Bit

7 to 0 -

Symbol Description reserved

9.3.1.2

CommandReg register

Starts and stops command execution.

Table 23.

CommandReg register (address 01h); reset value: 20h bit allocation

Bit 7 6 5 4 3 2 1

Symbol:

Access: reserved

-

RcvOff PowerDown

R/W D

Command[3:0]

D

0

Table 24.

CommandReg register bit descriptions

Bit Symbol Value Description

7 to 6 reserved

5

4

RcvOff

PowerDown

3 to 0 Command[3:0] -

-

1

1

0 reserved for future use analog part of the receiver is switched off

Soft power-down mode entered

MFRC522 starts the wake up procedure during which this bit is read as a logic 1; it is read as a logic 0 when the MFRC522 is

ready; see Section 8.6.2 on page 33

Remark: The PowerDown bit cannot be set when the SoftReset command is activated activates a command based on the Command value; reading this register shows which command is executed; see


9.3.1.3

ComIEnReg register

Control bits to enable and disable the passing of interrupt requests.

Table 25.

ComIEnReg register (address 02h); reset value: 80h bit allocation

Bit 7

Symbol IRqInv

Access R/W

6

TxIEn

R/W

5

R/W

4

R/W

3

R/W

2

R/W

1

R/W

0

RxIEn IdleIEn HiAlertIEn LoAlertIEn ErrIEn TimerIEn

R/W

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Table 26.

ComIEnReg register bit descriptions


7 IRqInv 1 signal on pin IRQ is inverted with respect to the Status1Reg register’s

IRq bit

0

6

5

4

3

2

1

0

TxIEn

RxIEn

IdleIEn

HiAlertIEn

ErrIEn

TimerIEn

-

-

-

-

-

-

LoAlertIEn signal on pin IRQ is equal to the IRq bit; in combination with the

DivIEnReg register’s IRqPushPull bit, the default value of logic 1 ensures that the output level on pin IRQ is 3-state allows the transmitter interrupt request (TxIRq bit) to be propagated to pin IRQ allows the receiver interrupt request (RxIRq bit) to be propagated to pin

IRQ allows the idle interrupt request (IdleIRq bit) to be propagated to pin IRQ allows the high alert interrupt request (HiAlertIRq bit) to be propagated to pin IRQ allows the low alert interrupt request (LoAlertIRq bit) to be propagated to pin IRQ allows the error interrupt request (ErrIRq bit) to be propagated to pin IRQ allows the timer interrupt request (TimerIRq bit) to be propagated to pin

IRQ

9.3.1.4

DivIEnReg register

Control bits to enable and disable the passing of interrupt requests.

Table 27.

DivIEnReg register (address 03h); reset value: 00h bit allocation

Bit 7 6 5 4 3 2

Symbol

Access

IRQPushPull reserved MfinActIEn reserved

R/W R/W -

CRCIEn

R/W

1 0 reserved

-

Table 28.

DivIEnReg register bit descriptions


7 IRQPushPull 1

0

6 to 5 reserved

4 MfinActIEn

3

2 reserved

CRCIEn

-

-

-

pin IRQ is a standard CMOS output pin pin IRQ is an open-drain output pin reserved for future use allows the MFIN active interrupt request to be propagated to pin IRQ reserved for future use

1 to 0 reserved allows the CRC interrupt request, indicated by the DivIrqReg register’s CRCIRq bit, to be propagated to pin IRQ reserved for future use

9.3.1.5

ComIrqReg register

Interrupt request bits.

Table 29.

ComIrqReg register (address 04h); reset value: 14h bit allocation

Bit

Symbol

Access

7

W

6

D

5

D

4

D

3

D

2

D

1

D

0

Set1 TxIRq RxIRq IdleIRq HiAlertIRq LoAlertIRq ErrIRq TimerIRq

D

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Table 30.

ComIrqReg register bit descriptions

All bits in the ComIrqReg register are cleared by software.

Bit Symbol

7 Set1

Value Description

1 indicates that the marked bits in the ComIrqReg register are set

6

5

TxIRq

RxIRq

0

1

1 indicates that the marked bits in the ComIrqReg register are cleared set immediately after the last bit of the transmitted data was sent out receiver has detected the end of a valid data stream if the RxModeReg register’s RxNoErr bit is set to logic 1, the RxIRq bit is only set to logic 1 when data bytes are available in the FIFO

4 IdleIRq

3

2

1

0

HiAlertIRq

LoAlertIRq

ErrIRq

TimerIRq

1

1

1

1

1

If a command terminates, for example, when the CommandReg changes

its value from any command to the Idle command (see Table 149 on page 70 )

if an unknown command is started, the CommandReg register

Command[3:0] value changes to the idle state and the IdleIRq bit is set

The microcontroller starting the Idle command does not set the IdleIRq bit the Status1Reg register’s HiAlert bit is set in opposition to the HiAlert bit, the HiAlertIRq bit stores this event and can only be reset as indicated by the Set1 bit in this register

Status1Reg register’s LoAlert bit is set in opposition to the LoAlert bit, the LoAlertIRq bit stores this event and can only be reset as indicated by the Set1 bit in this register any error bit in the ErrorReg register is set the timer decrements the timer value in register TCounterValReg to zero

9.3.1.6

DivIrqReg register

Interrupt request bits.

Table 31.

DivIrqReg register (address 05h); reset value: x0h bit allocation

Bit 7 6 5 4 3 2 1

Symbol

Access

Set2

W reserved

-

MfinActIRq reserved CRCIRq

D D reserved

-

0

Table 32.

DivIrqReg register bit descriptions

All bits in the DivIrqReg register are cleared by software.

Bit

7

Symbol

Set2


1 indicates that the marked bits in the DivIrqReg register are set

6 to 5 reserved -

0

4 MfinActIRq 1 indicates that the marked bits in the DivIrqReg register are cleared reserved for future use

MFIN is active this interrupt is set when either a rising or falling signal edge is detected

3

2 reserved

CRCIRq

1 to 0 reserved -

-

1 reserved for future use the CalcCRC command is active and all data is processed reserved for future use

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9.3.1.7

ErrorReg register

Error bit register showing the error status of the last command executed.

Table 33.

ErrorReg register (address 06h); reset value: 00h bit allocation

Bit 7 6 5 4 3 2 1 0

Symbol WrErr TempErr reserved BufferOvfl CollErr CRCErr ParityErr ProtocolErr

Access R R R R R R R

Table 34.

ErrorReg register bit descriptions

Bit Symbol

7 WrErr


1 data is written into the FIFO buffer by the host during the MFAuthent command or if data is written into the FIFO buffer by the host during the time between sending the last bit on the RF interface and receiving the last bit on the RF interface

6 TempErr

[1]

1 internal temperature sensor detects overheating, in which case the antenna drivers are automatically switched off

5 reserved reserved for future use

4 BufferOvfl 1

3

2

CollErr

CRCErr

1

1 the host or a MFRC522’s internal state machine (e.g. receiver) tries to write data to the FIFO buffer even though it is already full a bit-collision is detected cleared automatically at receiver start-up phase only valid during the bitwise anticollision at 106 kBd always set to logic 0 during communication protocols at 212 kBd,

424 kBd and 848 kBd the RxModeReg register’s RxCRCEn bit is set and the CRC calculation fails automatically cleared to logic 0 during receiver start-up phase

1 ParityErr

0 ProtocolErr

1

1 parity check failed automatically cleared during receiver start-up phase only valid for ISO/IEC 14443 A/MIFARE communication at 106 kBd set to logic 1 if the SOF is incorrect automatically cleared during receiver start-up phase bit is only valid for 106 kBd during the MFAuthent command, the ProtocolErr bit is set to logic 1 if the number of bytes received in one data stream is incorrect

[1] Command execution clears all error bits except the TempErr bit. Cannot be set by software.

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9.3.1.8

Status1Reg register

Contains status bits of the CRC, interrupt and FIFO buffer.

Table 35.

Status1Reg register (address 07h); reset value: 21h bit allocation

Bit 7 6 5

Symbol reserved CRCOk CRCReady

Access R R

4

IRq

R

3

R

2

-

1

TRunning reserved HiAlert LoAlert

R

0

R

Table 36.

Status1Reg register bit descriptions

Bit Symbol

7 reserved

6 CRCOk

-


1 reserved for future use

5 CRCReady 1 the CRC result is zero for data transmission and reception, the CRCOk bit is undefined: use the

ErrorReg register’s CRCErr bit indicates the status of the CRC coprocessor, during calculation the value changes to logic 0, when the calculation is done correctly the value changes to logic 1 the CRC calculation has finished only valid for the CRC coprocessor calculation using the CalcCRC command

4 IRq -

3

2

1

0

TRunning reserved

HiAlert

LoAlert

-

1

1

1 indicates if any interrupt source requests attention with respect to the setting of the interrupt enable bits: see the ComIEnReg and DivIEnReg registers

MFRC522’s timer unit is running, i.e. the timer will decrement the

TCounterValReg register with the next timer clock

Remark: in gated mode, the TRunning bit is set to logic 1 when the timer is enabled by TModeReg register’s TGated[1:0] bits; this bit is not influenced by the gated signal reserved for future use the number of bytes stored in the FIFO buffer corresponds to equation:

HiAlert =



64 – FIFOLength

 

WaterLevel example:

FIFO length = 60, WaterLevel = 4

 HiAlert = 1


 HiAlert = 0 the number of bytes stored in the FIFO buffer corresponds to equation:

LoAlert = FIFOLength



WaterLevel example:


 LoAlert = 1


 LoAlert = 0

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9.3.1.9

Status2Reg register

Contains status bits of the receiver, transmitter and data mode detector.

Table 37.

Status2Reg register (address 08h); reset value: 00h bit allocation

Bit 7 6

Symbol TempSensClear I 2 CForceHS

Access R/W R/W

5 4 reserved

-

3

MFCrypto1On

D

2 1

R

0

ModemState[2:0]

Table 38.

Status2Reg register bit descriptions

Bit

7

Symbol

TempSensClear

6

5 to 4

3

I 2 CForceHS reserved

MFCrypto1On -

-


1

1

0 clears the temperature error if the temperature is below the alarm limit of 125

C

I 2 C-bus input filter settings: the I 2 C-bus input filter is set to the High-speed mode independent of the I 2 C-bus protocol the I 2 C-bus input filter is set to the I 2 C-bus protocol used reserved

2 to 0 ModemState[2:0] -

000 indicates that the MIFARE Crypto1 unit is switched on and therefore all data communication with the card is encrypted can only be set to logic 1 by a successful execution of the

MFAuthent command only valid in Read/Write mode for MIFARE standard cards this bit is cleared by software shows the state of the transmitter and receiver state machines: idle

001

010

011

100

101

110 wait for the BitFramingReg register’s StartSend bit

TxWait: wait until RF field is present if the TModeReg register’s TxWaitRF bit is set to logic 1 the minimum time for TxWait is defined by the TxWaitReg register transmitting

RxWait: wait until RF field is present if the TModeReg register’s TxWaitRF bit is set to logic 1 the minimum time for RxWait is defined by the

RxWaitReg register wait for data receiving

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9.3.1.10

FIFODataReg register

Input and output of 64 byte FIFO buffer.

Table 39.

FIFODataReg register (address 09h); reset value: xxh bit allocation

Bit

Symbol

7 6 5 4 3

FIFOData[7:0]

2 1

Access D

0

Table 40.

FIFODataReg register bit descriptions

Bit

7 to 0

Symbol Description

FIFOData[7:0] data input and output port for the internal 64-byte FIFO buffer

FIFO buffer acts as parallel in/parallel out converter for all serial data stream inputs and outputs

9.3.1.11

FIFOLevelReg register

Indicates the number of bytes stored in the FIFO.

Table 41.

FIFOLevelReg register (address 0Ah); reset value: 00h bit allocation

Bit 7

Symbol FlushBuffer

6 5 4 3

FIFOLevel[6:0]

2 1

Access W R

0

Table 42.

FIFOLevelReg register bit descriptions

Bit

7

Symbol Value Description

FlushBuffer 1 immediately clears the internal FIFO buffer’s read and write pointer and ErrorReg register’s BufferOvfl bit reading this bit always returns 0

6 to 0 FIFOLevel

[6:0]

indicates the number of bytes stored in the FIFO buffer writing to the FIFODataReg register increments and reading decrements the FIFOLevel value

9.3.1.12

WaterLevelReg register

Defines the level for FIFO under- and overflow warning.

Table 43.

WaterLevelReg register (address 0Bh); reset value: 08h bit allocation

Bit 7 6 5 4 3 2 1

Symbol

Access reserved

-

WaterLevel[5:0]

R/W

0

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Table 44.

WaterLevelReg register bit descriptions

Bit Symbol Description

7 to 6

5 to 0 reserved

WaterLevel

[5:0] reserved for future use defines a warning level to indicate a FIFO buffer overflow or underflow:

Status1Reg register’s HiAlert bit is set to logic 1 if the remaining number of bytes in the FIFO buffer space is equal to, or less than the defined number of WaterLevel bytes

Status1Reg register’s LoAlert bit is set to logic 1 if equal to, or less than the WaterLevel bytes in the FIFO buffer

Remark: to calculate values for HiAlert and LoAlert see


.

9.3.1.13

ControlReg register

Miscellaneous control bits.

Table 45.

ControlReg register (address 0Ch); reset value: 10h bit allocation

Bit 7 6

Symbol TStopNow TStartNow

5 4 reserved

3 2 1

RxLastBits[2:0]

Access W W R

0

Table 46.

ControlReg register bit descriptions

Bit

7

Symbol

TStopNow

Value

1

Description timer stops immediately reading this bit always returns it to logic0

6 TStartNow 1

5 to 3

2 to 0 reserved

RxLastBits[2:0] -

timer starts immediately reading this bit always returns it to logic 0 reserved for future use indicates the number of valid bits in the last received byte if this value is 000b, the whole byte is valid

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9.3.1.14

BitFramingReg register

Adjustments for bit-oriented frames.

Table 47.

BitFramingReg register (address 0Dh); reset value: 00h bit allocation

Bit 7

Symbol StartSend

6 5

RxAlign[2:0]

4 3 reserved

2 1

TxLastBits[2:0]

Access W R/W R/W

0

Table 48.

BitFramingReg register bit descriptions

Bit

7

Symbol

StartSend


1 starts the transmission of data only valid in combination with the Transceive command

6 to 4 RxAlign[2:0]

0

1 used for reception of bit-oriented frames: defines the bit position for the first bit received to be stored in the FIFO buffer example:

LSB of the received bit is stored at bit position 0, the second received bit is stored at bit position 1

LSB of the received bit is stored at bit position 1, the second received bit is stored at bit position 2

3

2 to 0 reserved

TxLastBits[2:0] -

-

7 LSB of the received bit is stored at bit position 7, the second received bit is stored in the next byte that follows at bit position 0

These bits are only to be used for bitwise anticollision at

106 kBd, for all other modes they are set to 0 reserved for future use used for transmission of bit oriented frames: defines the number of bits of the last byte that will be transmitted

000b indicates that all bits of the last byte will be transmitted

9.3.1.15

CollReg register

Defines the first bit-collision detected on the RF interface.

Table 49.

CollReg register (address 0Eh); reset value: xxh bit allocation

Bit 7 6 5

Symbol ValuesAfterColl reserved CollPosNotValid

4 3 2

CollPos[4:0]

1

Access R/W R R

0

Table 50.

CollReg register bit descriptions

Bit

7

6

5

Symbol

ValuesAfterColl reserved

CollPosNotValid

-


0

1 all received bits will be cleared after a collision only used during bitwise anticollision at 106 kBd, otherwise it is set to logic 1 reserved for future use no collision detected or the position of the collision is out of the range of CollPos[4:0]

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Table 50.

CollReg register bit descriptions …continued

Bit Symbol

4 to 0 CollPos[4:0] -

Value Description shows the bit position of the first detected collision in a received frame only data bits are interpreted

00h

01h

08h example: indicates a bit-collision in the 32 nd bit indicates a bit-collision in the 1 st bit indicates a bit-collision in the 8 th bit

These bits will only be interpreted if the

CollPosNotValid bit is set to logic 0

9.3.1.16

Reserved register 0Fh


Table 51.

Reserved register (address 0Fh); reset value: 00h bit allocation

Bit

Symbol

Access

7 6 5 4 reserved

-

3 2 1 0

Table 52.


Bit

7 to 0

Symbol reserved

Description reserved for future use

9.3.2 Page 1: Communication

9.3.2.1



Table 53.


Bit 7 6 5 4 3 2

Symbol

Access reserved

-

1

Table 54.



7 to 0 reserved reserved for future use

0

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9.3.2.2

ModeReg register

Defines general mode settings for transmitting and receiving.

Table 55.

ModeReg register (address 11h); reset value: 3Fh bit allocation

Bit 7 6 5 4 3 2

Symbol MSBFirst reserved TxWaitRF reserved PolMFin reserved

Access R/W R/W R/W -

1 0

CRCPreset[1:0]

R/W

4

3

6

5

Table 56.

ModeReg register bit descriptions

Bit

7

Symbol

MSBFirst

Value

1

Description

CRC coprocessor calculates the CRC with MSB first in the CRCResultReg register the values for the

CRCResultMSB[7:0] bits and the CRCResultLSB[7:0] bits are bit reversed

Remark: during RF communication this bit is ignored reserved

TxWaitRF reserved

PolMFin

-

-

1 reserved for future use transmitter can only be started if an RF field is generated reserved for future use defines the polarity of pin MFIN

Remark: the internal envelope signal is encoded active LOW, changing this bit generates a MFinActIRq event polarity of pin MFIN is active HIGH 1

-

0

2 reserved

1 to 0 CRCPreset

[1:0] polarity of pin MFIN is active LOW reserved for future use defines the preset value for the CRC coprocessor for the CalcCRC command

Remark: during any communication, the preset values are selected automatically according to the definition of bits in the

RxModeReg and TxModeReg registers

00

01

10

11

0000h

6363h

A671h

FFFFh

9.3.2.3

TxModeReg register

Defines the data rate during transmission.

Table 57.

TxModeReg register (address 12h); reset value: 00h bit allocation

Bit 7 6 5 4 3 2 1

Symbol TxCRCEn

Access R/W

TxSpeed[2:0]

D

InvMod

R/W reserved

-

0

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Table 58.

TxModeReg register bit descriptions


7 TxCRCEn 1

6 to 4 TxSpeed[2:0] enables CRC generation during data transmission

Remark: can only be set to logic 0 at 106 kBd defines the bit rate during data transmission the MFRC522 handles transfer speeds up to

848 kBd

106 kBd

3

2 to 0

InvMod reserved -

000

001

010

011

100

101

110

111

1

212 kBd

424 kBd

848 kBd reserved reserved reserved reserved modulation of transmitted data is inverted reserved for future use

9.3.2.4

RxModeReg register

Defines the data rate during reception.

Table 59.

RxModeReg register (address 13h); reset value: 00h bit allocation

Bit 7 6 5 4 3 2 1

Symbol RxCRCEn

Access R/W

RxSpeed[2:0]

D

RxNoErr RxMultiple

R/W R/W reserved

-

0

Table 60.

RxModeReg register bit descriptions


7 RxCRCEn 1

6 to 4 RxSpeed[2:0] enables the CRC calculation during reception

Remark: can only be set to logic 0 at 106 kBd defines the bit rate while receiving data the MFRC522 handles transfer speeds up to 848 kBd

3 RxNoErr

100

101

110

111

1

000

001

010

011

106 kBd

212 kBd

424 kBd

848 kBd reserved reserved reserved reserved an invalid received data stream (less than 4 bits received) will be ignored and the receiver remains active

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Table 60.

RxModeReg register bit descriptions …continued

Bit

2

Symbol

RxMultiple

Value

0

Description receiver is deactivated after receiving a data frame

1

1 to 0 reserved able to receive more than one data frame only valid for data rates above 106 kBd in order to handle the polling command after setting this bit the Receive and Transceive commands will not terminate automatically. Multiple reception can only be deactivated by writing any command (except the Receive command) to the CommandReg register, or by the host clearing the bit if set to logic 1, an error byte is added to the FIFO buffer at the end of a received data stream which is a copy of the ErrorReg register value. For the MFRC522 version 2.0 the CRC status is reflected in the signal CRCOk, which indicates the actual status of the CRC coprocessor. For the MFRC522 version 1.0 the CRC status is reflected in the signal CRCErr.


9.3.2.5

TxControlReg register

Controls the logical behavior of the antenna driver pins TX1 and TX2.

Table 61.

TxControlReg register (address 14h); reset value: 80h bit allocation

Bit

Symbol

7

InvTx2RF

On

6

InvTx1RF

On

5

InvTx2RF

Off

4

InvTx1RF

Off

3 2 1 0

Tx2CW reserved Tx2RFEn Tx1RFEn

Access R/W R/W R/W R/W R/W R/W R/W

Table 62.

TxControlReg register bit descriptions


7 InvTx2RFOn 1 output signal on pin TX2 inverted when driver TX2 is enabled

6 InvTx1RFOn 1

5 InvTx2RFOff 1

4 InvTx1RFOff 1

3 Tx2CW 1 output signal on pin TX1 inverted when driver TX1 is enabled output signal on pin TX2 inverted when driver TX2 is disabled output signal on pin TX1 inverted when driver TX1 is disabled output signal on pin TX2 continuously delivers the unmodulated

13.56 MHz energy carrier

Tx2CW bit is enabled to modulate the 13.56 MHz energy carrier

2

1

0 reserved

Tx2RFEn

Tx1RFEn

0

-

1

1 reserved for future use output signal on pin TX2 delivers the 13.56 MHz energy carrier modulated by the transmission data output signal on pin TX1 delivers the 13.56 MHz energy carrier modulated by the transmission data

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9.3.2.6

TxASKReg register

Controls transmit modulation settings.

Table 63.

TxASKReg register (address 15h); reset value: 00h bit allocation

Bit 7 6

Symbol reserved Force100ASK

5 4 3 reserved

2

Access R/W -

1 0

Table 64.

TxASKReg register bit descriptions

Bit

7

6

Symbol reserved -


Force100ASK 1 reserved for future use

5 to 0 reserved forces a 100 % ASK modulation independent of the ModGsPReg register setting reserved for future use

9.3.2.7

TxSelReg register

Selects the internal sources for the analog module.

Table 65.

TxSelReg register (address 16h); reset value: 10h bit allocation

Bit

Symbol:

7 reserved

6 5 4

DriverSel[1:0]

3 2 1

MFOutSel[3:0]

Access: R/W R/W

0

Table 66.

TxSelReg register bit descriptions

Bit Symbol Value

7 to 6 reserved -

5 to 4 DriverSel

[1:0]

-

00

01

10

11

Description reserved for future use selects the input of drivers TX1 and TX2

3-state; in soft power-down the drivers are only in 3-state mode if the DriverSel[1:0] value is set to 3-state mode modulation signal (envelope) from the internal encoder, Miller pulse encoded modulation signal (envelope) from pin MFIN

HIGH; the HIGH level depends on the setting of bits

InvTx1RFOn/InvTx1RFOff and InvTx2RFOn/InvTx2RFOff

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Table 66.

TxSelReg register bit descriptions …continued


3 to 0 MFOutSel

[3:0]

0000 selects the input for pin MFOUT

3-state

0001

0010

0011

LOW

HIGH

0100 test bus signal as defined by the TestSel1Reg register’s

TstBusBitSel[2:0] value modulation signal (envelope) from the internal encoder, Miller pulse encoded

0101 serial data stream to be transmitted, data stream before Miller encoder

0110

0111 reserved serial data stream received, data stream after Manchester decoder

1000 to 1111 reserved

9.3.2.8

RxSelReg register

Selects internal receiver settings.

Table 67.

RxSelReg register (address 17h); reset value: 84h bit allocation

Bit

Symbol

7 6

UARTSel[1:0]

5 4 3 2

RxWait[5:0]

Access R/W R/W

1 0

Table 68.

RxSelReg register bit descriptions

Bit

7 to 6

Symbol Value Description

UARTSel

[1:0]

00 selects the input of the contactless UART constant LOW

01 Manchester with subcarrier from pin MFIN

10

11

5 to 0 RxWait

[5:0]

modulated signal from the internal analog module, default

NRZ coding without subcarrier from pin MFIN which is only valid for transfer speeds above 106 kBd after data transmission the activation of the receiver is delayed for

RxWait bit-clocks, during this ‘frame guard time’ any signal on pin RX is ignored this parameter is ignored by the Receive command all other commands, such as Transceive, MFAuthent use this parameter the counter starts immediately after the external RF field is switched on

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9.3.2.9

RxThresholdReg register

Selects thresholds for the bit decoder.

Table 69.

RxThresholdReg register (address 18h); reset value: 84h bit allocation

Bit

Symbol

7 6 5

MinLevel[3:0]

4 3 reserved

2 1

CollLevel[2:0]

Access R/W R/W

0

Table 70.

RxThresholdReg register bit descriptions

Bit

7 to 4

3

2 to 0

Symbol

MinLevel

[3:0] reserved

CollLevel

[2:0]

Description defines the minimum signal strength at the decoder input that will be accepted if the signal strength is below this level it is not evaluated reserved for future use defines the minimum signal strength at the decoder input that must be reached by the weaker half-bit of the Manchester encoded signal to generate a bit-collision relative to the amplitude of the stronger half-bit

9.3.2.10

DemodReg register

Defines demodulator settings.

Table 71.

DemodReg register (address 19h); reset value: 4Dh bit allocation

Bit 7 6 5 4 3 2 1

Symbol AddIQ[1:0] TauRcv[1:0]

0

TauSync[1:0]

Access R/W

FixIQ TPrescal

Even

R/W R/W R/W R/W

Table 72.

DemodReg register bit descriptions


7 to 6 AddIQ

[1:0]

defines the use of I and Q channel during reception

Remark: the FixIQ bit must be set to logic 0 to enable the following settings:

00

01

5 FixIQ

10

11

1 selects the stronger channel selects the stronger channel and freezes the selected channel during communication reserved reserved if AddIQ[1:0] are set to X0b, the reception is fixed to I channel if AddIQ[1:0] are set to X1b, the reception is fixed to Q channel

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Table 72.

DemodReg register bit descriptions …continued

Bit

4

Symbol

TPrescalEven


R/W Available on RC522 version 1.0 and version 2.0:

If set to logic 0 the following formula is used to calculate the timer frequency of the prescaler: f timer

= 13.56 MHz / (2*TPreScaler+1).

Only available on version 2.0:

If set to logic 1 the following formula is used to calculate the timer frequency of the prescaler: f timer


Default TPrescalEven bit is logic 0, find more information on the prescaler in

Section 8.5

.

3 to 2 TauRcv[1:0] -

1 to 0 TauSync[1:0] changes the time-constant of the internal PLL during data reception

Remark: if set to 00b the PLL is frozen during data reception changes the time-constant of the internal PLL during burst

9.3.2.11

Reserved register 1Ah


Table 73.

Reserved register (address 1Ah); reset value: 00h bit allocation

Bit 7 6 5 4 3 2

Symbol

Access reserved

-

1 0

Table 74.




9.3.2.12

Reserved register 1Bh


Table 75.

Reserved register (address 1Bh); reset value: 00h bit allocation

Bit

Symbol

Access

7 6 5 4 reserved

-

3 2 1 0

Table 76.


Bit

7 to 0

Symbol reserved


9.3.2.13

MfTxReg register

Controls some MIFARE communication transmit parameters.

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Table 77.

MfTxReg register (address 1Ch); reset value: 62h bit allocation

Bit 7 6 5 4 3 2

Symbol

Access reserved

-

1 0

TxWait[1:0]

R/W

Table 78.

MfTxReg register bit descriptions


7 to 2

1 to 0 reserved

TxWait reserved for future use defines the additional response time

7 bits are added to the value of the register bit by default

9.3.2.14

MfRxReg register

Table 79.

MfRxReg register (address 1Dh); reset value: 00h bit allocation

Bit 7 6 5 4 3 2

Symbol

Access reserved

-

ParityDisable

R/W reserved

-

1 0

Table 80.

MfRxReg register bit descriptions


7 to 5 reserved

4

-

ParityDisable 1

3 to 0 reserved reserved for future use generation of the parity bit for transmission and the parity check for receiving is switched off the received parity bit is handled like a data bit reserved for future use

9.3.2.15

Reserved register 1Eh


Table 81.

Reserved register (address 1Eh); reset value: 00h bit allocation

Bit 7 6 5 4 3 2

Symbol

Access reserved

-

1 0

Table 82.




9.3.2.16

SerialSpeedReg register

Selects the speed of the serial UART interface.

Table 83.

SerialSpeedReg register (address 1Fh); reset value: EBh bit allocation

Bit

Symbol

7 6

BR_T0[2:0]

5 4 3 2

BR_T1[4:0]

1

Access R/W R/W

0

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Table 84.

SerialSpeedReg register bit descriptions


7 to 5 BR_T0[2:0]

4 to 0 BR_T1[4:0] factor BR_T0 adjusts the transfer speed: for description, see


factor BR_T1 adjusts the transfer speed: for description, see


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9.3.3 Page 2: Configuration

9.3.3.1



Table 85.


Bit 7 6 5 4 3 2

Symbol

Access

reserved

1 0

Table 86.




9.3.3.2

CRCResultReg registers

Shows the MSB and LSB values of the CRC calculation.

Remark: The CRC is split into two 8-bit registers.

Table 87.

CRCResultReg (higher bits) register (address 21h); reset value: FFh bit allocation

Bit

Symbol

7 6 5 4 3

CRCResultMSB[7:0]

2 1 0

Access R

Table 88.

CRCResultReg register higher bit descriptions

Bit

7 to 0

Symbol

CRCResultMSB

[7:0]

Description shows the value of the CRCResultReg register’s most significant byte only valid if Status1Reg register’s CRCReady bit is set to logic 1

Table 89.

CRCResultReg (lower bits) register (address 22h); reset value: FFh bit allocation

Bit

Symbol

7 6 5 4 3

CRCResultLSB[7:0]

2 1 0

Access R

Table 90.

CRCResultReg register lower bit descriptions

Bit

7 to 0

Symbol

CRCResultLSB

[7:0]

Description shows the value of the least significant byte of the CRCResultReg register only valid if Status1Reg register’s CRCReady bit is set to logic 1

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9.3.3.3



Table 91.


Bit

Symbol

Access

7 6 5 4 reserved

-

3 2 1

Table 92.


Bit

7 to 0

Symbol reserved


9.3.3.4

ModWidthReg register

Sets the modulation width.

Table 93.

ModWidthReg register (address 24h); reset value: 26h bit allocation

Bit 7 6 5 4 3 2 1

Symbol

Access

ModWidth[7:0]

R/W

0

0

Table 94.

ModWidthReg register bit descriptions


7 to 0 ModWidth[7:0] defines the width of the Miller modulation as multiples of the carrier frequency (ModWidth + 1 / f clk

) the maximum value is half the bit period

9.3.3.5



Table 95.


Bit

Symbol

Access

7 6 5 4 reserved

-

3 2 1 0

Table 96.


Bit

7 to 0

Symbol reserved


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9.3.3.6

RFCfgReg register

Configures the receiver gain.

Table 97.

RFCfgReg register (address 26h); reset value: 48h bit allocation

Bit 7

Symbol reserved

Access -

6 5

RxGain[2:0]

R/W

4 3 2 reserved

-

1 0

Table 98.

RFCfgReg register bit descriptions

Bit

7

Symbol reserved

6 to 4 RxGain

[2:0]

-

Value

000

Description reserved for future use defines the receiver’s signal voltage gain factor:

18 dB

001

010

011

100

23 dB

18 dB

23 dB

33 dB

3 to 0 reserved

101

110

-

111

38 dB

43 dB

48 dB reserved for future use

9.3.3.7

GsNReg register

Defines the conductance of the antenna driver pins TX1 and TX2 for the n-driver when the driver is switched on.

Table 99.

GsNReg register (address 27h); reset value: 88h bit allocation

Bit

Symbol

7 6 5

CWGsN[3:0]

4 3 2 1

ModGsN[3:0]

Access R/W R/W

0

Table 100. GsNReg register bit descriptions

Bit Symbol

7 to 4 CWGsN

[3:0]

Description defines the conductance of the output n-driver during periods without modulation which can be used to regulate the output power and subsequently current consumption and operating distance

Remark: the conductance value is binary-weighted during soft Power-down mode the highest bit is forced to logic 1 value is only used if driver TX1 or TX2 is switched on

3 to 0 ModGsN

[3:0] defines the conductance of the output n-driver during periods without modulation which can be used to regulate the modulation index

Remark: the conductance value is binary weighted during soft Power-down mode the highest bit is forced to logic 1 value is only used if driver TX1 or TX2 is switched on

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9.3.3.8

CWGsPReg register

Defines the conductance of the p-driver output during periods of no modulation.

Table 101. CWGsPReg register (address 28h); reset value: 20h bit allocation

Bit

Symbol

Access

7 reserved

-

6 5 4 3

R/W

2

CWGsP[5:0]

1 0

Table 102. CWGsPReg register bit descriptions

Bit

7 to 6

5 to 0

Symbol reserved


CWGsP[5:0] defines the conductance of the p-driver output which can be used to regulate the output power and subsequently current consumption and operating distance

Remark: the conductance value is binary weighted during soft Power-down mode the highest bit is forced to logic 1

9.3.3.9

ModGsPReg register

Defines the conductance of the p-driver output during modulation.

Table 103. ModGsPReg register (address 29h); reset value: 20h bit allocation

Bit 7 6 5 4 3 2 1

Symbol

Access reserved

-

ModGsP[5:0]

R/W

0

Table 104. ModGsPReg register bit descriptions

Bit

7 to 6

5 to 0

Symbol reserved


ModGsP[5:0] defines the conductance of the p-driver output during modulation which can be used to regulate the modulation index

Remark: the conductance value is binary weighted during soft Power-down mode the highest bit is forced to logic 1 if the TxASKReg register’s Force100ASK bit is set to logic 1 the value of ModGsP has no effect

9.3.3.10

TModeReg and TPrescalerReg registers

These registers define the timer settings.

Remark: The TPrescaler setting higher 4 bits are in the TModeReg register and the lower

8 bits are in the TPrescalerReg register.

Table 105. TModeReg register (address 2Ah); reset value: 00h bit allocation

Bit 7 6 5 4 3 2 1

Symbol

Access

TAuto

R/W

TGated[1:0]

R/W

TAutoRestart

R/W

TPrescaler_Hi[3:0]

R/W

0

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Table 106. TModeReg register bit descriptions


7 TAuto 1 timer starts automatically at the end of the transmission in all communication modes at all speeds if the RxModeReg register’s RxMultiple bit is not set, the timer stops immediately after receiving the 5th bit (1 start bit, 4 data bits) if the RxMultiple bit is set to logic 1 the timer never stops, in which case the timer can be stopped by setting the

ControlReg register’s TStopNow bit to logic 1

0

6 to 5

4

TGated[1:0]

TAutoRestart

00

01

10

11

1 indicates that the timer is not influenced by the protocol internal timer is running in gated mode

Remark: in gated mode, the Status1Reg register’s

TRunning bit is logic 1 when the timer is enabled by the

TModeReg register’s TGated[1:0] bits this bit does not influence the gating signal non-gated mode gated by pin MFIN

gated by pin AUX1

3 to 0 TPrescaler_Hi[3:0] -

0 timer automatically restarts its count-down from the 16-bit timer reload value instead of counting down to zero timer decrements to 0 and the ComIrqReg register’s

TimerIRq bit is set to logic 1 defines the higher 4 bits of the TPrescaler value

The following formula is used to calculate the timer frequency if the DemodReg register’s TPrescalEven bit in

Demot Regis set to logic 0: f timer


Where TPreScaler = [TPrescaler_Hi:TPrescaler_Lo]

(TPrescaler value on 12 bits) (Default TPrescalEven bit is logic 0)

The following formula is used to calculate the timer frequency if the DemodReg register’s TPrescalEven bit is set to logic 1: f timer


See Section 8.5 “Timer unit”

.

Table 107. TPrescalerReg register (address 2Bh); reset value: 00h bit allocation

Bit 7 6 5 4 3 2 1

Symbol

Access

TPrescaler_Lo[7:0]

R/W

0

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Table 108. TPrescalerReg register bit descriptions


7 to 0 TPrescaler_Lo[7:0] defines the lower 8 bits of the TPrescaler value

The following formula is used to calculate the timer frequency if the

DemodReg register’s TPrescalEven bit is set to logic 0: f timer


Where TPreScaler = [TPrescaler_Hi:TPrescaler_Lo] (TPrescaler value on 12 bits) (Default TPrescalEven bit is logic 0)

The following formula is used to calculate the timer frequency if the

DemodReg register’s TPrescalEven bit inDemoReg is set to logic 1: f timer


See

Section 8.5 “Timer unit”

.

9.3.3.11

TReloadReg register

Defines the 16-bit timer reload value.

Remark: The reload value bits are contained in two 8-bit registers.

Table 109. TReloadReg (higher bits) register (address 2Ch); reset value: 00h bit allocation

Bit 7 6 5 4 3 2 1 0

Symbol

Access

TReloadVal_Hi[7:0]

R/W

Table 110. TReloadReg register higher bit descriptions


7 to 0 TReloadVal_Hi[7:0] defines the higher 8 bits of the 16-bit timer reload value on a start event, the timer loads the timer reload value changing this register affects the timer only at the next start event

Table 111. TReloadReg (lower bits) register (address 2Dh); reset value: 00h bit allocation

Bit

Symbol

7 6 5 4 3

TReloadVal_Lo[7:0]

2 1 0

Access R/W

Table 112. TReloadReg register lower bit descriptions


7 to 0 TReloadVal_Lo[7:0] defines the lower 8 bits of the 16-bit timer reload value on a start event, the timer loads the timer reload value changing this register affects the timer only at the next start event

9.3.3.12

TCounterValReg register

Contains the timer value.

Remark: The timer value bits are contained in two 8-bit registers.

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Table 113. TCounterValReg (higher bits) register (address 2Eh); reset value: xxh bit allocation

Bit

Symbol

7 6 5 4 3

TCounterVal_Hi[7:0]

2 1

Access R

0

Table 114. TCounterValReg register higher bit descriptions

Bit

7 to 0

Symbol

TCounterVal_Hi

[7:0]

Description timer value higher 8 bits

Table 115. TCounterValReg (lower bits) register (address 2Fh); reset value: xxh bit allocation

Bit 7 6 5 4 3 2 1

Symbol

Access

TCounterVal_Lo[7:0]

R

0

Table 116. TCounterValReg register lower bit descriptions


7 to 0 TCounterVal_Lo

[7:0] timer value lower 8 bits

9.3.4 Page 3: Test

9.3.4.1



Table 117. Reserved register (address 30h); reset value: 00h bit allocation

Bit

Symbol

Access

7 6 5 4 reserved

-

3 2 1 0

Table 118. Reserved register bit descriptions

Bit

7 to 0

Symbol reserved


9.3.4.2

TestSel1Reg register

General test signal configuration.

Table 119. TestSel1Reg register (address 31h); reset value: 00h bit allocation

Bit 7 6 5 4 3 2 1

Symbol

Access reserved

-

TstBusBitSel[2:0]

R/W

0

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Table 120. TestSel1Reg register bit descriptions


7 to 3

2 to 0 reserved

TstBusBitSel

[2:0] reserved for future use selects a test bus signal which is output at pin MFOUT if AnalogSelAux2[3:0] = FFh in AnalogTestReg register, test bus signal is also output at pins AUX1 or AUX2

9.3.4.3

TestSel2Reg register

General test signal configuration and PRBS control.

Table 121. TestSel2Reg register (address 32h); reset value: 00h bit allocation

Bit 7 6 5 4 3 2 1

Symbol TstBusFlip PRBS9 PRBS15

Access R/W R/W R/W

TestBusSel[4:0]

R/W

0

Table 122. TestSel2Reg register bit descriptions


7 TstBusFlip 1 test bus is mapped to the parallel port in the following order:

TstBusBit4,TstBusBit3, TstBusBit2, TstBusBit6, TstBusBit5,

TstBusBit0; see


6

5

PRBS9

PRBS15

4 to 0 TestBusSel[4:0] -

-

starts and enables the PRBS9 sequence according to ITU-TO150

Remark: all relevant registers to transmit data must be configured before entering PRBS9 mode the data transmission of the defined sequence is started by the

Transmit command starts and enables the PRBS15 sequence according to

ITU-TO150

Remark: all relevant registers to transmit data must be configured before entering PRBS15 mode the data transmission of the defined sequence is started by the

Transmit command

selects the test bus; see Section 16.1 “Test signals”

9.3.4.4

TestPinEnReg register

Enables the test bus pin output driver.

Table 123. TestPinEnReg register (address 33h); reset value: 80h bit allocation

Bit 7 6 5 4 3 2 1

Symbol RS232LineEn

Access R/W

TestPinEn[5:0]

R/W

0 reserved

-

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Table 124. TestPinEnReg register bit descriptions


7 RS232LineEn 0

6 to 1 TestPinEn

[5:0]

-

0 reserved serial UART lines MX and DTRQ are disabled enables the output driver on one of the data pins D1 to D7 which outputs a test signal

Example: setting bit 1 to logic 1 enables pin D1 output setting bit 5 to logic 1 enables pin D5 output

Remark: If the SPI is used, only pins D1 to D4 can be used. If the serial UART interface is used and the RS232LineEn bit is set to logic 1 only pins D1 to D4 can be used.


9.3.4.5

TestPinValueReg register

Defines the HIGH and LOW values for the test port D1 to D7 when it is used as I/O.

Table 125. TestPinValueReg register (address 34h); reset value: 00h bit allocation

Bit

Symbol

7

UseIO

6 5 4 3

TestPinValue[5:0]

2 1 0 reserved

Access R/W R/W -

Table 126. TestPinValueReg register bit descriptions

Bit

7

Symbol

UseIO


1 enables the I/O functionality for the test port when one of the serial interfaces is used the input/output behavior is defined by value TestPinEn[5:0] in the

TestPinEnReg register the value for the output behavior is defined by TestPinValue[5:0]

6 to 1 TestPinValue

[5:0]

0 reserved -

defines the value of the test port when it is used as I/O and each output must be enabled by TestPinEn[5:0] in the TestPinEnReg register

Remark: Reading the register indicates the status of pins D6 to D1 if the UseIO bit is set to logic 1. If the UseIO bit is set to logic 0, the value of the TestPinValueReg register is read back.


9.3.4.6

TestBusReg register

Shows the status of the internal test bus.

Table 127. TestBusReg register (address 35h); reset value: xxh bit allocation

Bit 7 6 5 4 3 2 1

Symbol

Access

TestBus[7:0]

R

0

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Table 128. TestBusReg register bit descriptions


7 to 0 TestBus[7:0] shows the status of the internal test bus the test bus is selected using the TestSel2Reg register; see


9.3.4.7

AutoTestReg register

Controls the digital self-test.

Table 129. AutoTestReg register (address 36h); reset value: 40h bit allocation

Bit 7 6

Symbol reserved AmpRcv

Access R/W

5

RFT

-

4 3 2

R/W

1

SelfTest[3:0]

0

Table 130. AutoTestReg register bit descriptions

Bit

7

6

Symbol reserved

AmpRcv

-


1 reserved for production tests

5 to 4 RFT

3 to 0 SelfTest[3:0] -

internal signal processing in the receiver chain is performed non-linearly which increases the operating distance in communication modes at 106 kBd

Remark: due to non-linearity, the effect of the RxThresholdReg register’s MinLevel[3:0] and the CollLevel[2:0] values is also non-linear reserved for production tests enables the digital self test the self test can also be started by the CalcCRC command; see


the self test is enabled by value 1001b

Remark: for default operation the self test must be disabled by value 0000b

9.3.4.8

VersionReg register

Shows the MFRC522 software version.

Table 131. VersionReg register (address 37h); reset value: xxh bit allocation

Bit

Symbol

7 6 5 4 3

Version[7:0]

2 1

Access R

0

Table 132. VersionReg register bit descriptions

Bit

7 to 4

3 to 0

Symbol

Chiptype

Version

Description

‘9’ stands for MFRC522

‘1’ stands for MFRC522 version 1.0 and ‘2’ stands for MFRC522 version 2.0.

MFRC522 version 1.0 software version is: 91h.

MFRC522 version 2.0 software version is: 92h.

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9.3.4.9

AnalogTestReg register

Determines the analog output test signal at, and status of, pins AUX1 and AUX2.

Table 133. AnalogTestReg register (address 38h); reset value: 00h bit allocation

Bit

Symbol

7 6 5

AnalogSelAux1[3:0]

4 3 2 1

AnalogSelAux2[3:0]

Access R/W R/W

0

Table 134. AnalogTestReg register bit descriptions

Bit Symbol

7 to 4 AnalogSelAux1

[3:0]

Value Description controls pin AUX1

0000

0001

0010

0011

0100

0101

0110

0111

1000

1001

3-state output of TestDAC1 (AUX1), output of TestDAC2 (AUX2)

[1]

test signal Corr1

[1]

reserved

DAC: test signal MinLevel

[1]

DAC: test signal ADC_I

[1]

DAC: test signal ADC_Q

[1]

reserved reserved, test signal for production test

[1]

reserved

1010

1011

1100

1101

HIGH

LOW

TxActive: at 106 kBd: HIGH during Start bit, Data bit, Parity and CRC at 212 kBd: 424 kBd and 848 kBd: HIGH during data and

CRC

RxActive: at 106 kBd: HIGH during Data bit, Parity and CRC at 212 kBd: 424 kBd and 848 kBd: HIGH during data and

CRC

3 to 0 AnalogSelAux2

[3:0]

-

1110

1111 subcarrier detected:

106 kBd: not applicable

212 kBd: 424 kBd and 848 kBd: HIGH during last part of data and CRC test bus bit as defined by the TestSel1Reg register’s

TstBusBitSel[2:0] bits

Remark: all test signals are described in


controls pin AUX2 (see bit descriptions for AUX1)

[1] Remark: Current source output; the use of 1 k

 pull-down resistor on AUXn is recommended.

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9.3.4.10

TestDAC1Reg register

Defines the test value for TestDAC1.

Table 135. TestDAC1Reg register (address 39h); reset value: xxh bit allocation

Bit

Symbol

Access

7 reserved

-

6 5 4 3

R/W

2

TestDAC1[5:0]

1

Table 136. TestDAC1Reg register bit descriptions

Bit

7

Symbol reserved

Description reserved for production tests

6


TestDAC1[5:0] defines the test value for TestDAC1 output of DAC1 can be routed to AUX1 by setting value

AnalogSelAux1[3:0] to 0001b in the AnalogTestReg register

9.3.4.11

TestDAC2Reg register

Defines the test value for TestDAC2.

Table 137. TestDAC2Reg register (address 3Ah); reset value: xxh bit allocation

Bit

Symbol

Access

7 reserved

-

6 5 4 3

R/W

2

TestDAC2[5:0]

1

Table 138. TestDAC2Reg register bit descriptions

Bit

7 to 6

5 to 0

Symbol reserved


TestDAC2[5:0] defines the test value for TestDAC2 output of DAC2 can be routed to AUX2 by setting value

AnalogSelAux2[3:0] to 0001b in the AnalogTestReg register

9.3.4.12

TestADCReg register

Shows the values of ADC I and Q channels.

Table 139. TestADCReg register (address 3Bh); reset value: xxh bit allocation

Bit

Symbol

7 6

ADC_I[3:0]

5 4 3 2 1

ADC_Q[3:0]

Access R R

Table 140. TestADCReg register bit descriptions

Bit

7 to 4

3 to 0

Symbol

ADC_I[3:0]

ADC_Q[3:0]

Description

ADC I channel value

ADC Q channel value

9.3.4.13

Reserved register 3Ch

Functionality reserved for production test.

0

0

0

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Table 141. Reserved register (address 3Ch); reset value: FFh bit allocation

Bit 7 6 5 4 3 2 1

Symbol

Access

RFT

-



7 to 0 reserved reserved for production tests

Table 143. Reserved register (address 3Dh); reset value: 00h bit allocation

Bit

Symbol

Access

7 6 5 4

RFT

-

3 2 1


Bit

7 to 0

Symbol reserved


Table 145. Reserved register (address 3Eh); reset value: 03h bit allocation

Bit 7 6 5 4 3 2

Symbol

Access

RFT

-

1



7 to 0 reserved reserved for production tests

Table 147. Reserved register (address 3Fh); reset value: 00h bit allocation

Bit

Symbol

Access

7 6 5 4 reserved

-

3 2 1


Bit

7 to 0

Symbol reserved


0

0

0

0

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10. MFRC522 command set

10.1 General description

The MFRC522 operation is determined by a state machine capable of performing a set of commands. A command is executed by writing a command code (see

Table 149 ) to the

CommandReg register.

Arguments and/or data necessary to process a command are exchanged via the FIFO buffer.

10.2 General behavior

• Each command that needs a data bit stream (or data byte stream) as an input immediately processes any data in the FIFO buffer. An exception to this rule is the

Transceive command. Using this command, transmission is started with the

BitFramingReg register’s StartSend bit.

• Each command that needs a certain number of arguments, starts processing only when it has received the correct number of arguments from the FIFO buffer.

• The FIFO buffer is not automatically cleared when commands start. This makes it possible to write command arguments and/or the data bytes to the FIFO buffer and then start the command.

• Each command can be interrupted by the host writing a new command code to the

CommandReg register, for example, the Idle command.

10.3 MFRC522 command overview

Table 149. Command overview

Command Command code

Action

Idle

Mem

0000

0001

Generate RandomID 0010

CalcCRC 0011

Transmit

NoCmdChange

0100

0111 no action, cancels current command execution stores 25 bytes into the internal buffer generates a 10-byte random ID number activates the CRC coprocessor or performs a self test transmits data from the FIFO buffer no command change, can be used to modify the

CommandReg register bits without affecting the command, for example, the PowerDown bit

-

Receive

Transceive

MFAuthent

SoftReset

1000

1100

1101

1110

1111 activates the receiver circuits transmits data from FIFO buffer to antenna and automatically activates the receiver after transmission reserved for future use performs the MIFARE standard authentication as a reader resets the MFRC522

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10.3.1 MFRC522 command descriptions

10.3.1.1

Idle

Places the MFRC522 in Idle mode. The Idle command also terminates itself.

10.3.1.2

Mem

Transfers 25 bytes from the FIFO buffer to the internal buffer.

To read out the 25 bytes from the internal buffer the Mem command must be started with an empty FIFO buffer. In this case, the 25 bytes are transferred from the internal buffer to the FIFO.

During a hard power-down (using pin NRSTPD), the 25 bytes in the internal buffer remain unchanged and are only lost if the power supply is removed from the MFRC522.

This command automatically terminates when finished and the Idle command becomes active.

10.3.1.3

Generate RandomID

This command generates a 10-byte random number which is initially stored in the internal buffer. This then overwrites the 10 bytes in the internal 25-byte buffer. This command automatically terminates when finished and the MFRC522 returns to Idle mode.

10.3.1.4

CalcCRC

The FIFO buffer content is transferred to the CRC coprocessor and the CRC calculation is started. The calculation result is stored in the CRCResultReg register. The CRC calculation is not limited to a dedicated number of bytes. The calculation is not stopped when the FIFO buffer is empty during the data stream. The next byte written to the FIFO buffer is added to the calculation.

The CRC preset value is controlled by the ModeReg register’s CRCPreset[1:0] bits. The value is loaded in to the CRC coprocessor when the command starts.

This command must be terminated by writing a command to the CommandReg register, such as, the Idle command.

If the AutoTestReg register’s SelfTest[3:0] bits are set correctly, the MFRC522 enters Self

Test mode. Starting the CalcCRC command initiates a digital self test. The result of the self test is written to the FIFO buffer.

10.3.1.5

Transmit

The FIFO buffer content is immediately transmitted after starting this command. Before transmitting the FIFO buffer content, all relevant registers must be set for data transmission.

This command automatically terminates when the FIFO buffer is empty. It can be terminated by another command written to the CommandReg register.

10.3.1.6

NoCmdChange

This command does not influence any running command in the CommandReg register. It can be used to manipulate any bit except the CommandReg register Command[3:0] bits, for example, the RcvOff bit or the PowerDown bit.

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10.3.1.7

Receive

The MFRC522 activates the receiver path and waits for a data stream to be received. The correct settings must be chosen before starting this command.

This command automatically terminates when the data stream ends. This is indicated either by the end of frame pattern or by the length byte depending on the selected frame type and speed.

Remark: If the RxModeReg register’s RxMultiple bit is set to logic 1, the Receive command will not automatically terminate. It must be terminated by starting another command in the CommandReg register.

10.3.1.8

Transceive

This command continuously repeats the transmission of data from the FIFO buffer and the reception of data from the RF field. The first action is transmit and after transmission the command is changed to receive a data stream.

Each transmit process must be started by setting the BitFramingReg register’s StartSend bit to logic 1. This command must be cleared by writing any command to the


Remark: If the RxModeReg register’s RxMultiple bit is set to logic 1, the Transceive command never leaves the receive state because this state cannot be cancelled automatically.

10.3.1.9

MFAuthent

This command manages MIFARE authentication to enable a secure communication to any MIFARE Mini, MIFARE 1K and MIFARE 4K card. The following data is written to the

FIFO buffer before the command can be activated:

• Authentication command code (60h, 61h)

• Block address

• Sector key byte 0






• Card serial number byte 0




In total 12 bytes are written to the FIFO.

Remark: When the MFAuthent command is active all access to the FIFO buffer is blocked. However, if there is access to the FIFO buffer, the ErrorReg register’s WrErr bit is set.

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This command automatically terminates when the MIFARE card is authenticated and the

Status2Reg register’s MFCrypto1On bit is set to logic 1.

This command does not terminate automatically if the card does not answer, so the timer must be initialized to automatic mode. In this case, in addition to the IdleIRq bit, the

TimerIRq bit can be used as the termination criteria. During authentication processing, the

RxIRq bit and TxIRq bit are blocked. The Crypto1On bit is only valid after termination of the MFAuthent command, either after processing the protocol or writing Idle to the


If an error occurs during authentication, the ErrorReg register’s ProtocolErr bit is set to logic 1 and the Status2Reg register’s Crypto1On bit is set to logic 0.

10.3.1.10

SoftReset

This command performs a reset of the device. The configuration data of the internal buffer remains unchanged. All registers are set to the reset values. This command automatically terminates when finished.

Remark: The SerialSpeedReg register is reset and therefore the serial data rate is set to

9.6 kBd.

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11. Limiting values

Table 150. Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).

Conditions Symbol Parameter

V

DDA analog supply voltage

V

DDD digital supply voltage

V

DD(PVDD)

PVDD supply voltage

V

DD(TVDD)

TVDD supply voltage

V

DD(SVDD)

SVDD supply voltage

V

I input voltage all input pins except pins MFIN and

RX pin MFIN

P tot

T

V j

ESD total power dissipation per package; and V

DDD

in shortcut mode junction temperature electrostatic discharge voltage HBM; 1500

, 100 pF;

JESD22-A114-B

MM; 0.75

H, 200 pF;

JESD22-A114-A

Charged device model;

JESD22-C101-A on all pins on all pins except SVDD in

TFBGA64 package

-

-

-

-

-

Min Max Unit

0.5

0.5

0.5

0.5

+4.0

+4.0

+4.0

+4.0

V

V

V

V

0.5

+4.0

V

V

SS(PVSS)

 0.5 V

DD(PVDD)

+ 0.5 V

-

V

SS(PVSS)

 0.5 V

DD(SVDD)

+ 0.5 V

200 mW

100

2000

200

200

500

C

V

V

V

V

12. Recommended operating conditions

Table 151. Operating conditions

Symbol Parameter Conditions

V

V

V

V

DDA

DDD

DD(TVDD)

DD(PVDD) analog supply voltage V

DD(PVDD)

 V

DDA

= V

DDD

= V

DD(TVDD)

;

V

SSA

= V

SSD

= V

SS(PVSS)

= V

SS(TVSS)

= 0 V digital supply voltage V

DD(PVDD)

 V

DDA

= V

DDD

= V

DD(TVDD)

;

V

SSA

= V

SSD

= V

SS(PVSS)

= V

SS(TVSS)

= 0 V

TVDD supply voltage

PVDD supply voltage

V

DD(PVDD)

 V

DDA

= V

DDD

= V

DD(TVDD)

;

V

SSA

= V

SSD

= V

SS(PVSS)

= V

SS(TVSS)

= 0 V

V

DD(PVDD)

 V

DDA

= V

DDD

= V

DD(TVDD)

;

V

SSA

= V

SSD

= V

SS(PVSS)

= V

SS(TVSS)

= 0 V

V

DD(SVDD)

SVDD supply voltage

T amb ambient temperature

V

SSA

= V

SSD

HVQFN32

= V

SS(PVSS)

= V

SS(TVSS)

= 0 V

[1] Supply voltages below 3 V reduce the performance (the achievable operating distance).

[2] V

DDA

, V

DDD

and V

DD(TVDD)

must always be the same voltage.

[3] V

DD(PVDD)

must always be the same or lower voltage than V

DDD

.

Min Typ Max Unit

[1][2]

2.5

3.3

3.6

V

[1][2]

2.5

[1][2]

2.5

[3]

1.6

3.3

3.3

1.8

3.6

3.6

3.6

V

V

V

1.6

25

-

3.6

V

+85

C

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13. Thermal characteristics

Table 152. Thermal characteristics


R th(j-a) thermal resistance from junction to ambient

Conditions in still air with exposed pin soldered on a

4 layer JEDEC PCB

14. Characteristics

Table 153. Characteristics


Input characteristics

Conditions

I

Pins EA, I2C and NRSTPD

LI

V

IH

V

IL

Pin MFIN input leakage current

HIGH-level input voltage

LOW-level input voltage input leakage current


I

LI

V

IH

V

IL

Pin SDA

I

LI

V

IH

V

IL

Pin RX [1]

V i

C i

LOW-level input voltage input leakage current


LOW-level input voltage input voltage input capacitance

R i input resistance

V

DDA

= 3 V; receiver active;

V

RX(p-p)

= 1 V; 1.5 V (DC) offset

V

DDA

= 3 V; receiver active;

V

RX(p-p)

= 1 V; 1.5 V (DC) offset

Input voltage range; see Figure 24

V

V i(p-p)(min) i(p-p)(max) minimum peak-to-peak input voltage

Manchester encoded;

V

DDA

= 3 V maximum peak-to-peak input voltage

Manchester encoded;

V

DDA

= 3 V

Input sensitivity; see Figure 24

V mod modulation voltage minimum Manchester encoded; V

DDA

= 3 V;

RxGain[2:0] = 111b (48 dB)

Pin OSCIN

I

LI

V

IH

V

IL input leakage current


LOW-level input voltage

-

-

-

-

Min

-

1

0.7V

DD(PVDD)

-

-

-

-

1

0.7V

DD(SVDD)

-

-

-

1

-

0.7V

DD(PVDD)

-

-

-

-

1

-

1

0.7V

DDA

-

-

-

Typ

-

10

350

100

4

5

Package Typ Unit

HVQFN32 40 K/W

-

-

-

-

Max

-

+1

0.3V

DD(PVDD)

A

V

V

-

+1

0.3V

DD(SVDD)

A

V

V

+1

-

0.3V

DD(PVDD)

A

V

V

-

V

DDA

+1

-

+1

0.3V

DDA

Unit

V pF

 mV

V mV

A

V

V

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Table 153. Characteristics …continued


C i input capacitance

Conditions

V

DDA

= 2.8 V; DC = 0.65 V;

AC = 1 V (p-p)

Input/output characteristics pins D1, D2, D3, D4, D5, D6 and D7

I

LI

V

IH

V

IL

V

OH input leakage current


LOW-level input voltage

HIGH-level output voltage V

DD(PVDD)

= 3 V; I

O

= 4 mA

I

V

OL

LOW-level output voltage

I

OH

HIGH-level output current

I

OL

LOW-level output current

Output characteristics

Pin MFOUT

V

OH

HIGH-level output voltage

V

OL

OL

I

OH

Pin IRQ

V

OH





V

DD(PVDD)

= 3 V; I

O

= 4 mA

V

DD(PVDD)

= 3 V

V

DD(PVDD)

= 3 V

V

V

V

DD(SVDD)

= 3 V

V

DD(SVDD)

= 3 V

V

DD(SVDD)

DD(SVDD)

DD(PVDD)

= 3 V; I

O

= 3 V; I

O

= 3 V; I

O

= 4 mA

= 4 mA

= 4 mA

V

OL


I

OL

I

OH



Pins AUX1 and AUX2

V

OH

V

OL



I

OL

I

OH



Pins TX1 and TX2

V

DD(PVDD)

= 3 V; I

O

= 4 mA

V

DD(PVDD)

= 3 V

V

DD(PVDD)

= 3 V

V

V

V

DDD

DDD

DDD

V

DDD

= 3 V; I

O

= 3 V; I

= 3 V

= 3 V

O

= 4 mA

= 4 mA

-

Min Typ

2 -

Max Unit pF

-

-

1

0.7V

DD(PVDD)

-

V

DD(PVDD)



0.4

V

SS(PVSS)

-

-

-

-

-

-

-

-

+1

0.3V

DD(PVDD)

V

V

DD(PVDD)

V

A

V

4

4

V

SS(PVSS)

+

0.4

V mA mA

-

-

V

DD(SVDD)



0.4

V

SS(PVSS)

-

-

-

-

-

-

V

DD(PVDD)



0.4

V

SS(PVSS)

-

-

-

-

-

-

V

DDD

 0.4

-

V

SS(PVSS)

-

-

-

V

DD(SVDD)

V

V

SS(PVSS)

+

0.4

4

4

V mA mA

V

DD(PVDD)

V

4

4

V

SS(PVSS)

+

0.4

V mA mA

4

4

V

DDD

V

SS(PVSS)

+

0.4

V

V mA mA

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V

OH


V

OL


Conditions

V

DD(TVDD)

= 3 V;

I

DD(TVDD)

= 32 mA;

CWGsP[5:0] = 3Fh

V

DD(TVDD)

= 3 V;

I

DD(TVDD)

= 80 mA;

CWGsP[5:0] = 3Fh

V

DD(TVDD)

= 2.5 V;

I

DD(TVDD)

= 32 mA;

CWGsP[5:0] = 3Fh

V

DD(TVDD)

= 2.5 V;

I

DD(TVDD)

= 80 mA;

CWGsP[5:0] = 3Fh

I

V

DD(TVDD)

= 3 V;

DD(TVDD)

= 32 mA;

CWGsP[5:0] = 0Fh

V

DD(TVDD)

= 3 V;

I

DD(TVDD)

= 80 mA;

CWGsP[5:0] = 0Fh

I

V

DD(TVDD)

= 2.5 V;

DD(TVDD)

= 32 mA;

CWGsP[5:0] = 0Fh

V

DD(TVDD)

= 2.5 V;

I

DD(TVDD)

= 80 mA;

CWGsP[5:0] = 0Fh

I

Current consumption pd power-down current

I

I

I

DDD

DDA

DD(PVDD) digital supply current analog supply current

PVDD supply current

I

I

DD(TVDD)

TVDD supply current

DD(SVDD)

SVDD supply current

Clock frequency f clk

 clk clock frequency clock duty cycle t jit jitter time

Crystal oscillator

V

DDA

= V

DDD

= V

DD(TVDD)

V

DD(PVDD)

= 3 V

= hard power-down; pin

NRSTPD set LOW soft power-down; RF level detector on pin DVDD; V

DDD

= 3 V pin AVDD; V

DDA

= 3 V;

CommandReg register’s bit RcvOff = 0 pin AVDD; receiver switched off; V

DDA

= 3 V;

CommandReg register’s bit RcvOff = 1 pin PVDD pin TVDD; continuous wave pin SVDD

[2]

[2]

[3]

-

[4][5][6]

-

[7]

-

-

-

-

-

-

RMS

-

-

-

-

-

-

40

Min

V

DD(TVDD)



0.15

-

Typ

V

DD(TVDD)



0.4

-

V

DD(TVDD)



0.24

-

V

DD(TVDD)



0.64

-

-

-

-

-

-

-

-

-

-

6.5

7

3

60

27.12

50

-

-

-

-

-

Max

0.15

0.4

0.24

0.64

5

10

9

10

5

40

100

4

60

10

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Unit

V

V

V

V

V

V

V

V

A

A mA mA mA mA mA mA

MHz

% ps


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HIGH-level output voltage V

OH

V

OL

C i

LOW-level output voltage input capacitance

Conditions pin OSCOUT pin OSCOUT pin OSCOUT pin OSCIN f

Typical input requirements xtal

ESR crystal frequency equivalent series resistance

C

L

P xtal load capacitance crystal power dissipation

-

-

-

-

-

-

-

-

Min Typ

1.1

0.2

2

2

27.12

-

10

50

-

-

-

-

-

-

Max

100

100

MHz

 pF mW

[1] The voltage on pin RX is clamped by internal diodes to pins AVSS and AVDD.

[2] I pd

is the total current for all supplies.

[3] I

DD(PVDD)

depends on the overall load at the digital pins.

[4] I

DD(TVDD)

depends on V

DD(TVDD)

and the external circuit connected to pins TX1 and TX2.

[5] During typical circuit operation, the overall current is below 100 mA.

[6] Typical value using a complementary driver configuration and an antenna matched to 40

 between pins TX1 and TX2 at 13.56 MHz.

[7] I

DD(SVDD)

depends on the load at pin MFOUT.

Unit

V

V pF pF

V mod

V i(p-p)(max)

V i(p-p)(min)

VMID

13.56 MHz carrier

0 V

001aak012

MFRC522


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Fig 24. Pin RX input voltage range

14.1 Timing characteristics

Table 154. SPI timing characteristics

Symbol Parameter Conditions t

WL t

WH pulse width LOW pulse width HIGH t h(SCKH-D)

SCK HIGH to data input hold time line SCK line SCK

SCK to changing

MOSI


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Min

50

50

25

-

-

-

Typ

-

-

-

Max Unit ns ns ns


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Table 154. SPI timing characteristics …continued

Symbol Parameter Conditions t su(D-SCKH) data input to SCK HIGH set-up time changing MOSI to

SCK t h(SCKL-Q)

SCK LOW to data output hold time

SCK to changing

MISO t t

(SCKL-NSSH)

SCK LOW to NSS HIGH time

NHNL

NSS high before communication

-

Min

25

0

50

-

-

-

-

Typ

-

-

-

Max

25

Unit ns ns ns ns

Table 155. I 2 C-bus timing in Fast mode

Symbol Parameter t t f t

SU;STA set-up time for a repeated

START condition t t t

SU;STO set-up time for STOP condition

LOW

LOW period of the SCL clock

HIGH t

HD;DAT

HIGH period of the SCL clock data hold time t f t r t t

SU;DAT data set-up time r rise time fall time rise time f

SCL

HD;STA

SCL clock frequency hold time (repeated) START condition fall time

Conditions Fast mode High-speed mode

Unit

Min Max Min Max

0 400 0 3400 kHz

160 ns after this period, the first clock pulse is generated

600 -

600 160 ns

SCL signal

SCL signal

SDA and SCL signals

SDA and SCL signals

600

1300 -

600 -

0

100 -

20

20

20

20

-

300

300

300

160

160

60

900 0

10

300 10

10

10

10

-

-

-

-

70

40

40

80

80 ns ns ns ns ns ns ns ns ns t

BUF bus free time between a STOP and START condition

1.3

1.3

-

s

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SCK t

SCKL t

SCKH t

SCKL t

SLDX t

DXSH

MOSI t

DXSH

MSB t

SHDX

LSB

MISO MSB LSB t

SLNH

NSS

001aaj634

Remark: The signal NSS must be LOW to be able to send several bytes in one data stream.

To send more than one data stream NSS must be set HIGH between the data streams.

Fig 25. Timing diagram for SPI

SDA t f t

LOW

SCL

S t r t

HD;STA t

SU;DAT t f t

HD;DAT t

HIGH t

HD;STA t

SP t

SU;STO

Sr t

SU;STA

Fig 26. Timing for Fast and Standard mode devices on the I 2 C-bus t r t

BUF

P S

001aaj635

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15. Application information

A typical application diagram using a complementary antenna connection to the

MFRC522 is shown in

Figure 27

.

The antenna tuning and RF part matching is described in the application note

Ref. 1 and

Ref. 2

.

MICRO-

PROCESSOR supply

PVDD

2

3

DVDD AVDD

15 12

TVDD

17

RX

PVSS

5

CRx

16

VMID

R1

Cvmid

NRSTPD host interface

6 11

TX1

MFRC522

10, 14

TVSS

L0

IRQ

23 13

TX2

L0

AVSS

18 4

DVSS

21

OSCIN

27.12 MHz

22

OSCOUT

R2

C0

C1

C0

C1

C2

Ra

C2

Ra antenna

Lant

001aaj636

Fig 27. Typical application diagram

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16. Test information

16.1 Test signals

16.1.1 Self test

The MFRC522 has the capability to perform a digital self test. The self test is started by using the following procedure:

1. Perform a soft reset.

2. Clear the internal buffer by writing 25 bytes of 00h and implement the Config command.

3. Enable the self test by writing 09h to the AutoTestReg register.

4. Write 00h to the FIFO buffer.

5. Start the self test with the CalcCRC command.

6. The self test is initiated.

7. When the self test has completed, the FIFO buffer contains the following 64 bytes:

FIFO buffer byte values for MFRC522 version 1.0:

00h, C6h, 37h, D5h, 32h, B7h, 57h, 5Ch,

C2h, D8h, 7Ch, 4Dh, D9h, 70h, C7h, 73h,

10h, E6h, D2h, AAh, 5Eh, A1h, 3Eh, 5Ah,

14h, AFh, 30h, 61h, C9h, 70h, DBh, 2Eh,

64h, 22h, 72h, B5h, BDh, 65h, F4h, ECh,

22h, BCh, D3h, 72h, 35h, CDh, AAh, 41h,

1Fh, A7h, F3h, 53h, 14h, DEh, 7Eh, 02h,

D9h, 0Fh, B5h, 5Eh, 25h, 1Dh, 29h, 79h

FIFO buffer byte values for MFRC522 version 2.0:

00h, EBh, 66h, BAh, 57h, BFh, 23h, 95h,

D0h, E3h, 0Dh, 3Dh, 27h, 89h, 5Ch, DEh,

9Dh, 3Bh, A7h, 00h, 21h, 5Bh, 89h, 82h,

51h, 3Ah, EBh, 02h, 0Ch, A5h, 00h, 49h,

7Ch, 84h, 4Dh, B3h, CCh, D2h, 1Bh, 81h,

5Dh, 48h, 76h, D5h, 71h, 061h, 21h, A9h,

86h, 96h, 83h, 38h, CFh, 9Dh, 5Bh, 6Dh,

DCh, 15h, BAh, 3Eh, 7Dh, 95h, 03Bh, 2Fh

16.1.2 Test bus

The test bus is used for production tests. The following configuration can be used to improve the design of a system using the MFRC522. The test bus allows internal signals to be routed to the digital interface. The test bus comprises two sets of test signals which are selected using their subaddress specified in the TestSel2Reg register’s

TestBusSel[4:0] bits. The test signals and their related digital output pins are described in

Table 156 and Table 157 .

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D5

D4

D3

D2

D1

Table 156. Test bus signals: TestBusSel[4:0] = 07h

Pins Internal signal name

Description

D6 s_data received data stream

s_coll s_valid s_over

RCV_reset bit-collision detected (106 kBd only) s_data and s_coll signals are valid receiver has detected a stop condition receiver is reset reserved

Table 157. Test bus signals: TestBusSel[4:0] = 0Dh

Pins Internal test signal name

Description

D6

D5

D4 to D3 -

D2 clk27

D1 clkstable clk27/8 oscillator output signal oscillator output signal divided by 8 reserved oscillator output signal reserved

16.1.3 Test signals on pins AUX1 or AUX2

The MFRC522 allows the user to select internal signals for measurement on pins AUX1 or

AUX2. These measurements can be helpful during the design-in phase to optimize the design or used for test purposes.

Table 158

shows the signals that can be switched to pin AUX1 or AUX2 by setting

AnalogSelAux1[3:0] or AnalogSelAux2[3:0] in the AnalogTestReg register.

Remark: The DAC has a current output, therefore it is recommended that a 1 k

 pull-down resistor is connected to pin AUX1 or AUX2.

Table 158. Test signal descriptions

AnalogSelAux1[3:0] or

AnalogSelAux2[3:0] value

Signal on pin AUX1 or pin AUX2

0000

0001

0010

0011

3-state

DAC: register TestDAC1 or TestDAC2

DAC: test signal Corr1 reserved

0100

0101

0110

0111 to 1001

1010

1011

1100

DAC: test signal MinLevel

DAC: test signal ADC_I

DAC: test signal ADC_Q reserved

HIGH

LOW

TxActive

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Table 158. Test signal descriptions …continued

AnalogSelAux1[3:0] or

AnalogSelAux2[3:0] value

Signal on pin AUX1 or pin AUX2

1101 RxActive

1110

1111 subcarrier detected

TstBusBit

16.1.3.1

Example: Output test signals TestDAC1 and TestDAC2

The AnalogTestReg register is set to 11h. The output on pin AUX1 has the test signal

TestDAC1 and the output on pin AUX2 has the test signal TestDAC2. The signal values of

TestDAC1 and TestDAC2 are controlled by the TestDAC1Reg and TestDAC2Reg registers.

Figure 28

shows test signal TestDAC1 on pin AUX1 and TestDAC2 on pin AUX2 when the

TestDAC1Reg register is programmed with a slope defined by values 00h to 3Fh and the

TestDAC2Reg register is programmed with a rectangular signal defined by values 00h and 3Fh.

001aak597

(1)

(2)

100 ms/div

(1) TestDAC1 (500 mV/div) on pin AUX1.

(2) TestDAC2 (500 mV/div) on pin AUX2.

Fig 28. Output test signals TestDAC1 on pin AUX1 and TestDAC2 on pin AUX2

16.1.3.2

Example: Output test signals Corr1 and MinLevel

Figure 29

shows test signals Corr1 and MinLevel on pins AUX1 and AUX2, respectively.

The AnalogTestReg register is set to 24h.

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001aak598

(1)

(2)

(3)

10

μ s/div

(1) MinLevel (1 V/div) on pin AUX2.

(2) Corr1 (1 V/div) on pin AUX1.

(3) RF field.

Fig 29. Output test signals Corr1 on pin AUX1 and MinLevel on pin AUX2

16.1.3.3

Example: Output test signals ADC channel I and ADC channel Q

Figure 30

shows the channel behavior test signals ADC_I and ADC_Q on pins AUX1 and

AUX2, respectively. The AnalogTestReg register is set to 56h.

001aak599

(1)

(2)

(3)

MFRC522


COMPANY PUBLIC

5 μ s/div

(1) ADC_I (1 V/div) on pin AUX1.

(2) ADC_Q (500 mV/div) on pin AUX2.

(3) RF field.

Fig 30. Output ADC channel I on pin AUX1 and ADC channel Q on pin AUX2


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16.1.3.4

Example: Output test signals RxActive and TxActive

Figure 31

shows the RxActive and TxActive test signals relating to RF communication.

The AnalogTestReg register is set to CDh.

• At 106 kBd, RxActive is HIGH during data bits, parity and CRC reception. Start bits are not included

• At 106 kBd, TxActive is HIGH during start bits, data bits, parity and CRC transmission

• At 212 kBd, 424 kBd and 848 kBd, RxActive is HIGH during data bits and CRC reception. Start bits are not included

• At 212 kBd, 424 kBd and 848 kBd, TxActive is HIGH during data bits and CRC transmission

001aak600

(1)

(2)

(3)

(1) RxActive (2 V/div) on pin AUX1.

(2) TxActive (2 V/div) on pin AUX2.

(3) RF field.

Fig 31. Output RxActive on pin AUX1 and TxActive on pin AUX2

10 μ s/div

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16.1.3.5

Example: Output test signal RX data stream

Figure 32

shows the data stream that is currently being received. The TestSel2Reg register’s TestBusSel[4:0] bits are set to 07h to enable test bus signals on pins D1 to D6;

see Section 16.1.2 on page 82

. The TestSel1Reg register’s TstBusBitSel[2:0] bits are set to 06h (pin D6 = s_data) and AnalogTestReg register is set to FFh (TstBusBit) which outputs the received data stream on pins AUX1 and AUX2.

001aak601

(1)

(2)

20

μ s/div

(1) s_data (received data stream) (2 V/div).

(2) RF field.

Fig 32. Received data stream on pins AUX1 and AUX2

16.1.3.6

PRBS

The pseudo-random binary sequences PRBS9 and PRBS15 are based on ITU-TO150 and are defined with the TestSel2Reg register. Transmission of either data stream is started by the Transmit command. The preamble/sync byte/start bit/parity bit are automatically generated depending on the mode selected.

Remark: All relevant registers for transmitting data must be configured in accordance with

ITU-TO150 before selecting PRBS transmission.

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17. Package outline

HVQFN32: plastic thermal enhanced very thin quad flat package; no leads;

32 terminals; body 5 x 5 x 0.85 mm SOT617-1

B A D terminal 1 index area

A

A1

E c detail X

L

8

9 e e1

1/2 e b

16

17 e v M w M

C

C

A B y1 C

C y

Eh

1/2 e e2 terminal 1 index area

1

24

32

25

Dh

0 2.5

E

(1) Eh

3.25

2.95

scale

DIMENSIONS (mm are the original dimensions)

UNIT

A

(1) max.

A1 b c D

(1)

Dh mm 1

0.05

0.00

0.30

0.18

0.2

5.1

4.9

3.25

2.95

5.1

4.9

e

0.5

e1

3.5

Note

1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.

OUTLINE

VERSION

SOT617-1

IEC

- - -

REFERENCES

JEDEC JEITA

MO-220 - - e2

3.5

5 mm

L

0.5

0.3

v

0.1

w y y1

0.05

0.05

0.1

EUROPEAN

PROJECTION

X

ISSUE DATE

01-08-08

02-10-18

Fig 33. Package outline SOT617-1 (HVQFN32)

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Detailed package information can be found at: http://www.nxp.com/package/SOT617-1.html.

18. Handling information

Moisture Sensitivity Level (MSL) evaluation has been performed according to

SNW-FQ-225B rev.04/07/07 (JEDEC J-STD-020C). MSL for this package is level 1 which means 260

C convection reflow temperature.

Dry pack is not required.

Unlimited out-of-pack floor life at maximum ambient 30

C/85 % RH.

19. Packing information

The straps around the package of stacked trays inside the plano-box have sufficient pre-tension to avoid loosening of the trays.

strap 46 mm from corner tray chamfer

PIN 1 chamfer

PIN 1 printed plano box

Fig 34. Packing information 1 tray

ESD warning preprinted barcode label (permanent) barcode label (peel-off)

QA seal

Hyatt patent preprinted

In the traystack (2 trays) only ONE tray type* allowed

*one supplier and one revision number.

001aaj740

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20. Abbreviations

Table 159. Abbreviations

Acronym

ADC

Description

Analog-to-Digital Converter

BPSK

CRC

CW

DAC

HBM

I 2 C

LSB

MISO

MM

MOSI

MSB

NRZ

NSS

PLL

PRBS

RX

SOF

SPI

TX

UART

Binary Phase Shift Keying

Cyclic Redundancy Check

Continuous Wave

Digital-to-Analog Converter

Human Body Model

Inter-integrated Circuit

Least Significant Bit

Master In Slave Out

Machine Model

Master Out Slave In

Most Significant Bit

Not Return to Zero

Not Slave Select

Phase-Locked Loop

Pseudo-Random Bit Sequence

Receiver

Start Of Frame

Serial Peripheral Interface

Transmitter

Universal Asynchronous Receiver Transmitter

21. References

[1] Application note — MFRC52x Reader IC Family Directly Matched Antenna

Design

[2] Application note — MIFARE (ISO/IEC 14443 A) 13.56 MHz RFID Proximity

Antennas

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22. Revision history

Table 160. Revision history

Document ID

MFRC522 v.3.8

Modifications:

MFRC522 v.3.7

Modifications:

MFRC522 v.3.6

Modifications:

Release date Data sheet status Change notice Supersedes

20140917 Product data sheet

•

Table 150 “Limiting values”

: updated

20140326 Product data sheet

•

Change of descriptive title

•

Section 23.4 “Licenses” removed

-

MFRC522 v.3.7

MFRC522 v.3.6

20111214 Product data sheet MFRC522_35

•

Section 2.1 “Differences between version 1.0 and 2.0” on page 1 : added

•

Table 2 “Ordering information” on page 3 : updated

•

Section 9.3.2.10 “DemodReg register” on page 53

: register updated and add reference to

Timer unit

•

Section 8.5 “Timer unit” on page 31 : Pre Scaler Information for version 2.0 added

•

Section 9.3.4.8 “VersionReg register” on page 66

: version information structured in chip information and version information updated, including version 1.0 and 2.0

•

Section 16.1 “Test signals” on page 82

: selftest result including values for version 1.0 and

2.0

MFRC522_35

Modifications:

MFRC522_34

Modifications:

MFRC522_33

20100621 Product data sheet MFRC522_34

•

Section 9.3.2.10 “DemodReg register” on page 53

: register updated

•

Section 9.3.3.10 “TModeReg and TPrescalerReg registers” on page 60

: register updated

•

Section 8.5 “Timer unit” on page 31 : timer calculation updated

•

Section 9.3.4.8 “VersionReg register” on page 66

: version B2h updated

•

Section 16.1 “Test signals” on page 82

: selftest result updated

MFRC522_33 20100305 Product data sheet

•

Section 8.5 “Timer unit” : information added

•

Table 106 “TModeReg register bit descriptions”

: bit 7 updated

•

Table 154 “SPI timing characteristics” : row added

20091026 Product data sheet 112132

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23. Legal information

Document status

[1][2]

Objective [short] data sheet

Product status

[3]

Development

Preliminary [short] data sheet Qualification

Product [short] data sheet Production

Definition

This document contains data from the objective specification for product development.

This document contains data from the preliminary specification.

This document contains the product specification.

[1] Please consult the most recently issued document before initiating or completing a design.

[2] The term ‘short data sheet’ is explained in section “Definitions”.

[3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com

.

23.2 Definitions

Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information.

Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail.

Product specification — The information and data provided in a Product data sheet shall define the specification of the product as agreed between

NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the

Product data sheet.

23.3 Disclaimers

Limited warranty and liability — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. NXP Semiconductors takes no responsibility for the content in this document if provided by an information source outside of NXP Semiconductors.

In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory.

Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors.

Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof.

MFRC522


COMPANY PUBLIC

Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors and its suppliers accept no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk.

Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification.

Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the NXP

Semiconductors product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products.

NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP

Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). NXP does not accept any liability in this respect.

Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the

Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device.

Terms and conditions of commercial sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms , unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer.

No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights.



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Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities.

Quick reference data — The Quick reference data is an extract of the product data given in the Limiting values and Characteristics sections of this document, and as such is not complete, exhaustive or legally binding.

Non-automotive qualified products — Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. NXP

Semiconductors accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications.

In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer

(a) shall use the product without NXP Semiconductors’ warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond

NXP Semiconductors’ specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ standard warranty and NXP Semiconductors’ product specifications.

Translations — A non-English (translated) version of a document is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions.

23.4 Trademarks

Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners.

I 2 C-bus — logo is a trademark of NXP Semiconductors N.V.

MIFARE — is a trademark of NXP Semiconductors N.V.

24. Contact information

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: [email protected]

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25. Contents

3

4

5

1

2

2.1

6

7

7.1

8

8.1

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

General description . . . . . . . . . . . . . . . . . . . . . . 1

Differences between version 1.0 and 2.0 . . . . . 1

Features and benefits . . . . . . . . . . . . . . . . . . . . 2

Quick reference data . . . . . . . . . . . . . . . . . . . . . 2

Ordering information . . . . . . . . . . . . . . . . . . . . . 3

Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Pinning information . . . . . . . . . . . . . . . . . . . . . . 6

Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 6

Functional description . . . . . . . . . . . . . . . . . . . 8

Digital interfaces . . . . . . . . . . . . . . . . . . . . . . . . 9

8.2.5

8.3

8.3.1

8.3.2

8.3.3

8.4

8.4.1

8.5

8.1.2 Serial Peripheral Interface . . . . . . . . . . . . . . . 10

8.1.2.1 SPI read data . . . . . . . . . . . . . . . . . . . . . . . . . 10

8.1.2.2 SPI write data . . . . . . . . . . . . . . . . . . . . . . . . . 11

8.1.2.3 SPI address byte . . . . . . . . . . . . . . . . . . . . . . 11

8.1.3 UART interface . . . . . . . . . . . . . . . . . . . . . . . . 11

8.1.3.1 Connection to a host. . . . . . . . . . . . . . . . . . . . 11

8.1.3.2 Selectable UART transfer speeds . . . . . . . . . 12

8.1.3.3 UART framing . . . . . . . . . . . . . . . . . . . . . . . . . 13

8.1.4 I 2

C-bus interface. . . . . . . . . . . . . . . . . . . . . . . 16

8.1.4.1 Data validity . . . . . . . . . . . . . . . . . . . . . . . . . . 17

8.1.4.2 START and STOP conditions . . . . . . . . . . . . . 17

8.1.4.3 Byte format . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

8.1.4.4 Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . 18

8.1.4.5 7-Bit addressing . . . . . . . . . . . . . . . . . . . . . . . 19

8.1.4.6 Register write access . . . . . . . . . . . . . . . . . . . 19

8.1.4.7 Register read access . . . . . . . . . . . . . . . . . . . 20

8.1.4.8 High-speed mode . . . . . . . . . . . . . . . . . . . . . . 21

8.1.4.9 High-speed transfer . . . . . . . . . . . . . . . . . . . . 21

8.1.4.10 Serial data transfer format in HS mode . . . . . 21

8.1.4.11 Switching between F/S mode and HS mode . 23

8.1.4.12 MFRC522 at lower speed modes . . . . . . . . . . 23

8.2 Analog interface and contactless UART . . . . . 24

8.2.1

8.2.2

8.2.3

8.2.4

General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

TX p-driver . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Serial data switch . . . . . . . . . . . . . . . . . . . . . . 26

MFIN and MFOUT interface support . . . . . . . 26

CRC coprocessor . . . . . . . . . . . . . . . . . . . . . . 29

FIFO buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Accessing the FIFO buffer . . . . . . . . . . . . . . . 29

Controlling the FIFO buffer . . . . . . . . . . . . . . . 29

FIFO buffer status information . . . . . . . . . . . . 29

Interrupt request system . . . . . . . . . . . . . . . . . 30

Interrupt sources overview . . . . . . . . . . . . . . . 30

Timer unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

8.6

8.6.1

8.6.2

8.6.3

8.7

8.8

8.8.1

8.8.2

Power reduction modes . . . . . . . . . . . . . . . . . 33

Hard power-down. . . . . . . . . . . . . . . . . . . . . . 33

Soft power-down mode . . . . . . . . . . . . . . . . . 33

Transmitter power-down mode . . . . . . . . . . . 33

Oscillator circuit . . . . . . . . . . . . . . . . . . . . . . . 33

Reset and oscillator start-up time . . . . . . . . . 34

Reset timing requirements . . . . . . . . . . . . . . . 34

Oscillator start-up time . . . . . . . . . . . . . . . . . . 34

9 MFRC522 registers . . . . . . . . . . . . . . . . . . . . . 35

9.1

9.2

9.3

Register bit behavior . . . . . . . . . . . . . . . . . . . 35

Register overview . . . . . . . . . . . . . . . . . . . . . 36

Register descriptions . . . . . . . . . . . . . . . . . . . 38

9.3.1 Page 0: Command and status . . . . . . . . . . . . 38

9.3.1.1 Reserved register 00h . . . . . . . . . . . . . . . . . . 38

9.3.1.2 CommandReg register . . . . . . . . . . . . . . . . . . 38

9.3.1.3 ComIEnReg register . . . . . . . . . . . . . . . . . . . 38

9.3.1.4 DivIEnReg register . . . . . . . . . . . . . . . . . . . . . 39

9.3.1.5 ComIrqReg register . . . . . . . . . . . . . . . . . . . . 39

9.3.1.6 DivIrqReg register . . . . . . . . . . . . . . . . . . . . . 40

9.3.1.7 ErrorReg register . . . . . . . . . . . . . . . . . . . . . . 41

9.3.1.8 Status1Reg register . . . . . . . . . . . . . . . . . . . . 42

9.3.1.9 Status2Reg register . . . . . . . . . . . . . . . . . . . . 43

9.3.1.10 FIFODataReg register . . . . . . . . . . . . . . . . . . 44

9.3.1.11 FIFOLevelReg register. . . . . . . . . . . . . . . . . . 44

9.3.1.12 WaterLevelReg register . . . . . . . . . . . . . . . . . 44

9.3.1.13 ControlReg register . . . . . . . . . . . . . . . . . . . . 45

9.3.1.14 BitFramingReg register . . . . . . . . . . . . . . . . . 46

9.3.1.15 CollReg register . . . . . . . . . . . . . . . . . . . . . . . 46

9.3.1.16 Reserved register 0Fh . . . . . . . . . . . . . . . . . . 47

9.3.2 Page 1: Communication. . . . . . . . . . . . . . . . . 47


9.3.2.2 ModeReg register . . . . . . . . . . . . . . . . . . . . . 48

9.3.2.3 TxModeReg register . . . . . . . . . . . . . . . . . . . 48

9.3.2.4 RxModeReg register . . . . . . . . . . . . . . . . . . . 49

9.3.2.5 TxControlReg register . . . . . . . . . . . . . . . . . . 50

9.3.2.6 TxASKReg register . . . . . . . . . . . . . . . . . . . . 51

9.3.2.7 TxSelReg register . . . . . . . . . . . . . . . . . . . . . 51

9.3.2.8 RxSelReg register . . . . . . . . . . . . . . . . . . . . . 52

9.3.2.9 RxThresholdReg register . . . . . . . . . . . . . . . . 53

9.3.2.10 DemodReg register . . . . . . . . . . . . . . . . . . . . 53

9.3.2.11 Reserved register 1Ah . . . . . . . . . . . . . . . . . . 54

9.3.2.12 Reserved register 1Bh . . . . . . . . . . . . . . . . . . 54

9.3.2.13 MfTxReg register . . . . . . . . . . . . . . . . . . . . . . 54

9.3.2.14 MfRxReg register . . . . . . . . . . . . . . . . . . . . . . 55

9.3.2.15 Reserved register 1Eh . . . . . . . . . . . . . . . . . . 55

9.3.2.16 SerialSpeedReg register . . . . . . . . . . . . . . . . 55

9.3.3 Page 2: Configuration . . . . . . . . . . . . . . . . . . 57


continued >>

MFRC522


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MFRC522


9.3.3.2 CRCResultReg registers . . . . . . . . . . . . . . . . 57


9.3.3.4 ModWidthReg register . . . . . . . . . . . . . . . . . . 58


9.3.3.6 RFCfgReg register . . . . . . . . . . . . . . . . . . . . . 59

9.3.3.7 GsNReg register . . . . . . . . . . . . . . . . . . . . . . . 59

9.3.3.8 CWGsPReg register . . . . . . . . . . . . . . . . . . . . 60

9.3.3.9 ModGsPReg register . . . . . . . . . . . . . . . . . . . 60

9.3.3.10 TModeReg and TPrescalerReg registers . . . . 60

9.3.3.11 TReloadReg register . . . . . . . . . . . . . . . . . . . 62

9.3.3.12 TCounterValReg register . . . . . . . . . . . . . . . . 62

9.3.4 Page 3: Test . . . . . . . . . . . . . . . . . . . . . . . . . . 63


9.3.4.2 TestSel1Reg register . . . . . . . . . . . . . . . . . . . 63

9.3.4.3 TestSel2Reg register . . . . . . . . . . . . . . . . . . . 64

9.3.4.4 TestPinEnReg register . . . . . . . . . . . . . . . . . . 64

9.3.4.5 TestPinValueReg register . . . . . . . . . . . . . . . . 65

9.3.4.6 TestBusReg register . . . . . . . . . . . . . . . . . . . . 65

9.3.4.7 AutoTestReg register . . . . . . . . . . . . . . . . . . . 66

9.3.4.8 VersionReg register . . . . . . . . . . . . . . . . . . . . 66

9.3.4.9 AnalogTestReg register . . . . . . . . . . . . . . . . . 67

9.3.4.10 TestDAC1Reg register . . . . . . . . . . . . . . . . . . 68

9.3.4.11 TestDAC2Reg register . . . . . . . . . . . . . . . . . . 68

9.3.4.12 TestADCReg register . . . . . . . . . . . . . . . . . . . 68

9.3.4.13 Reserved register 3Ch . . . . . . . . . . . . . . . . . . 68

10

10.1

10.2

10.3

MFRC522 command set . . . . . . . . . . . . . . . . . 70

General description . . . . . . . . . . . . . . . . . . . . 70

General behavior . . . . . . . . . . . . . . . . . . . . . . 70

MFRC522 command overview . . . . . . . . . . . . 70

10.3.1.1 Idle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

10.3.1.2 Mem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

10.3.1.3 Generate RandomID . . . . . . . . . . . . . . . . . . . 71

10.3.1.4 CalcCRC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

10.3.1.5 Transmit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

10.3.1.6 NoCmdChange . . . . . . . . . . . . . . . . . . . . . . . . 71

10.3.1.7 Receive. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

10.3.1.8 Transceive . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

10.3.1.9 MFAuthent . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

10.3.1.10 SoftReset . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

11 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 74

12

13

Recommended operating conditions. . . . . . . 74

Thermal characteristics . . . . . . . . . . . . . . . . . 75

14

14.1

15

Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 75

Timing characteristics . . . . . . . . . . . . . . . . . . . 78

Application information. . . . . . . . . . . . . . . . . . 81

16 Test information . . . . . . . . . . . . . . . . . . . . . . . . 82

16.1 Test signals . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

16.1.1 Self test. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

16.1.2 Test bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

16.1.3 Test signals on pins AUX1 or AUX2. . . . . . . . 83

TestDAC2. . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

16.1.3.2 Example: Output test signals Corr1 and

MinLevel. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

and ADC channel Q . . . . . . . . . . . . . . . . . . . . 85

TxActive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

16.1.3.6 PRBS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

17

18

Package outline. . . . . . . . . . . . . . . . . . . . . . . . 88

Handling information . . . . . . . . . . . . . . . . . . . 89

19

20

21

22

23

23.1

23.2

23.3

23.4

24

25

Packing information . . . . . . . . . . . . . . . . . . . . 89

Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 90

References. . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

Revision history . . . . . . . . . . . . . . . . . . . . . . . 91

Legal information . . . . . . . . . . . . . . . . . . . . . . 92

Data sheet status . . . . . . . . . . . . . . . . . . . . . . 92

Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . 92

Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 93

Contact information . . . . . . . . . . . . . . . . . . . . 93

Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94

Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’.

© NXP Semiconductors N.V. 2014.

All rights reserved.

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: [email protected]

Date of release: 17 September 2014

112138

Product information | ACT PRO MIFARE DESFIRE EV1 - REV 1.0 Product data

Standard 3V MIFARE reader solution

1. Introduction

3. Features and benefits

4. Quick reference data

10. MFRC522 command set

11. Limiting values

12. Recommended operating conditions

13. Thermal characteristics

14. Characteristics

15. Application information

16. Test information

17. Package outline

18. Handling information

19. Packing information

20. Abbreviations

21. References

22. Revision history

23. Legal information

24. Contact information

25. Contents

Related manuals

Table of contents

Product information | ACT PRO MIFARE DESFIRE EV1 - REV 1.0 Product data

Standard 3V MIFARE reader solution

1. Introduction

3. Features and benefits

4. Quick reference data

10. MFRC522 command set

11. Limiting values

12. Recommended operating conditions

13. Thermal characteristics

14. Characteristics

15. Application information

16. Test information

17. Package outline

18. Handling information

19. Packing information

20. Abbreviations

21. References

22. Revision history

23. Legal information

24. Contact information

25. Contents

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Table of contents