AD7682
FEATURES
16-bit resolution with no missing codes
4-channel (AD7682)/8-channel (AD7689) multiplexer with choice of inputs
Unipolar single-ended
Differential (GND sense)
Pseudobipolar
Throughput: 250 kSPS
INL: ±0.4 LSB typical, ±1.5 LSB maximum (±23 ppm or FSR)
Dynamic range: 93.8 dB
SINAD: 92.5 dB @ 20 kHz
THD: −100 dB @ 20 kHz
Analog input range: 0 V to V
REF
with V
REF
up to VDD
Multiple reference types
Internal selectable 2.5 V or 4.096 V
External buffered (up to 4.096 V)
External (up to VDD)
Internal temperature sensor (TEMP)
Channel sequencer, selectable 1-pole filter, busy indicator
No pipeline delay, SAR architecture
Single-supply 2.3 V to 5.5 V operation with
1.8 V to 5.5 V logic interface
Serial interface compatible with SPI, MICROWIRE,
QSPI, and DSP
Power dissipation
3.5 mW @ 2.5 V/200 kSPS
12.5 mW @ 5 V/250 kSPS
Standby current: 50 nA
Low cost grade available
20-lead 4 mm × 4 mm LFCSP package
APPLICATIONS
Multichannel system monitoring
Battery-powered equipment
Medical instruments: ECG/EKG
Mobile communications: GPS
Power line monitoring
Data acquisition
Seismic data acquisition systems
Instrumentation
Process control
16-Bit, 4-Channel/8-Channel,
250 kSPS PulSAR ADC
AD7682/AD7689
FUNCTIONAL BLOCK DIAGRAM
0.5V TO VDD – 0.5V
0.1µF
0.5V TO VDD
10µF
2.3V TO 5.5V
REFIN REF VDD
BAND GAP
REF
TEMP
SENSOR
AD7689
VIO
1.8V
TO
VDD
IN0
IN1
IN2
IN3
IN4
IN5
IN6
IN7
COM
MUX
16-BIT SAR
ADC
ONE-POLE
LPF
SEQUENCER
SPI SERIAL
INTERFACE
CNV
SCK
SDO
DIN
GND
Figure 1.
Table 1. Multichannel 14-/16-Bit PulSAR® ADC
Type Channels 250 kSPS
500 kSPS ADC
14-Bit 8 AD7949 ADA4841-x
16-Bit 4
16-Bit 8
AD7682 ADA4841-x
AD7689 AD7699 ADA4841-x
GENERAL DESCRIPTION
The AD7682/AD7689 are 4-channel/8-channel, 16-bit, charge redistribution successive approximation register (SAR) analogto-digital converters (ADCs) that operate from a single power supply, VDD.
The AD7682/AD7689 contain all components for use in a multichannel, low power data acquisition system, including a true 16-bit SAR ADC with no missing codes; a 4-channel
(AD7682) or 8-channel (AD7689), low crosstalk multiplexer that is useful for configuring the inputs as single-ended (with or without ground sense), differential, or bipolar; an internal low drift reference (selectable 2.5 V or 4.096 V) and buffer; a temperature sensor; a selectable one-pole filter; and a sequencer that is useful when channels are continuously scanned in order.
The AD7682/AD7689 use a simple SPI interface for writing to the configuration register and receiving conversion results. The
SPI interface uses a separate supply, VIO, which is set to the host logic level. Power dissipation scales with throughput.
The AD7682/AD7689 are housed in a tiny 20-lead LFCSP with operation specified from −40°C to +85°C.
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 www.analog.com
Fax: 781.461.3113 ©2008–2009 Analog Devices, Inc. All rights reserved.
AD7682/AD7689
TABLE OF CONTENTS
Functional Block Diagram .............................................................. 1
General Description ......................................................................... 1
Revision History ............................................................................... 2
Timing Specifications .................................................................. 6
Absolute Maximum Ratings ............................................................ 8
ESD Caution .................................................................................. 8
Pin Configurations and Function Descriptions ........................... 9
Typical Performance Characteristics ........................................... 11
Terminology .................................................................................... 14
Theory of Operation ...................................................................... 15
Overview ...................................................................................... 15
Converter Operation .................................................................. 15
Transfer Functions...................................................................... 16
Typical Connection Diagrams .................................................. 17
Analog Inputs .............................................................................. 18
Driver Amplifier Choice ............................................................ 20
REVISION HISTORY
3/09—Rev. 0 to Rev. A
Changes to Features Section, Applications Section, and
Figure 1 .............................................................................................. 1
Added Table 2; Renumbered Sequentially .................................... 3
Changed VREF to V
REF
.................................................................... 4
Changes to Table 3 ............................................................................ 5
Changes to Table 4 ............................................................................ 6
Changes to Table 5 ............................................................................ 7
Deleted Endnote 2 in Table 6 .......................................................... 8
Changes to Figure 4, Figure 5, and Table 7 ................................... 9
Changes to Figure 6, Figure 9, and Figure 10 ............................. 11
Changes to Figure 22 ...................................................................... 13
Changes to Overview Section and Converter Operation
Section .............................................................................................. 15
Changes to Table 8 .......................................................................... 16
Changes to Figure 26 and Figure 27 ............................................. 17
Changes to Bipolar Single Supply Section and Analog Inputs
Section .............................................................................................. 18
Changes to Internal Reference/Temperature Sensor Section ... 20
Added Figure 31; Renumbered Sequentially .............................. 20
Changes to External Reference and Internal Buffer Section and
External Reference Section ............................................................ 21
Voltage Reference Output/Input .............................................. 20
Power Supply ............................................................................... 22
Supplying the ADC from the Reference .................................. 22
Digital Interface .............................................................................. 23
Reading/Writing During Conversion, Fast Hosts .................. 23
Reading/Writing After Conversion, Any Speed Hosts .......... 23
Reading/Writing Spanning Conversion, Any Speed Host .... 23
Configuration Register, CFG .................................................... 23
General Timing Without a Busy Indicator ............................. 25
General Timing with a Busy Indicator .................................... 26
Channel Sequencer .................................................................... 27
Read/Write Spanning Conversion Without a Busy
Indicator ...................................................................................... 28
Read/Write Spanning Conversion with a Busy Indicator ..... 29
Application Hints ........................................................................... 30
Layout .......................................................................................... 30
Evaluating AD7682/AD7689 Performance ............................ 30
Outline Dimensions ....................................................................... 31
Ordering Guide .......................................................................... 31
Added Figure 32 and Figure 33 .................................................... 21
Changes to Power Supply Section ................................................ 22
Changes to Digital Interface Section, Reading/Writing After
Conversion, Any Speed Hosts Section, and Configuration
Register, CFG Section .................................................................... 23
Changes to Table 10 ....................................................................... 24
Added General Timing Without a Busy Indicator Section and
Figure 37 .......................................................................................... 25
Added General Timing With a Busy Indicator Section and
Figure 38 .......................................................................................... 26
Added Channel Sequencer Section and Figure 39 ..................... 27
Changes to Read/Write Spanning Conversion Without a Busy
Indicator Section and Figure 41 ................................................... 28
Changes to Read/Write Spanning Conversion with a Busy
Indicator and Figure 43 ................................................................. 29
Changes to Evaluating AD7682/AD7689 Performance
Section .............................................................................................. 30
Added Exposed Pad Notation to Outline Dimensions ............. 31
Changes to Ordering Guide .......................................................... 31
5/08—Revision 0: Initial Version
Rev. A | Page 2 of 32
SPECIFICATIONS
VDD = 2.3 V to 5.5 V, VIO = 1.8 V to VDD, V
REF
= VDD, all specifications T
MIN
to T
MAX
, unless otherwise noted.
AD7682/AD7689
Table 2.
RESOLUTION
AD7689A AD7682B/AD7689B
Unit
16 16 Bits
ANALOG INPUT
Voltage Range Unipolar mode
Absolute Input Voltage Positive input, unipolar and bipolar modes
Negative or COM input, unipolar mode
Negative or COM input, bipolar mode f
IN
= 250 kHz Analog Input CMRR
Leakage Current at 25°C
Acquisition phase
THROUGHPUT
Conversion Rate
Transient Response
VDD = 4.5 V to 5.5 V
VDD = 2.3 V to 4.5 V
VDD = 4.5 V to 5.5 V
VDD = 2.3 V to 4.5 V
Full-scale step, full bandwidth
0 +V
REF
0 +V
REF
V
/2 +V
REF
/2 −V
REF
/2 +V
REF
/2
−0.1 V
REF
+ 0.1 −0.1 V
REF
+ 0.1 V
−0.1 +0.1 −0.1 +0.1 V
V
0
0
0
0
REF
/2 − 0.1 V
1
REF
68
/2 V
REF
250
200
50
/2 + 0.1
62.5
V
1
0
0
0
0
REF
1.8
/2 − 0.
V
1
REF
68
/2 V
REF
250
200
/2 + 0.1
62.5
50
V dB nA kSPS kSPS kSPS kSPS
Full-scale step,
¼ bandwidth
ACCURACY
14.5
No Missing Codes
Integral Linearity Error
Differential Linearity Error
Transition Noise
REF = VDD = 5 V
15
−4
0.6
+4
16
−1.5
−1
±0.4 +1.5
±0.25 +1.5
Bits
LSB
0.5 LSB
−8 LSB
Gain Error Match
Gain Error Temperature Drift
VDD = 4.5 V to 5.5 V
Offset Error Match
Offset Error Temperature Drift
Power Supply Sensitivity VDD = 5 V ± 5%
VDD = 2.3 V to 4.5 V
Dynamic Range
Signal-to-Noise f
IN
= 20 kHz, V
REF
= 5 V f
IN
= 20 kHz, V
REF
= 4.096 V, internal REF f
IN
= 20 kHz, V
REF
= 2.5 V, internal REF
SINAD f
IN
= 20 kHz, V
REF
= 5 V f
IN
= 20 kHz, V
REF
= 5 V,
−60 dB input f
IN
= 20 kHz, V
REF
= 4.096 V internal REF f
IN
= 20 kHz, V
REF
= 2.5 V internal REF
−32
±2
±1
±32
±2
±1
±1.5
90.5
90
89
+32
−4
−8
−4
92.5
91
±0.5
±1
±1
±5
±0.5
±1
±1.5
93.8
93.5
92.5
+4
+8
+4
LSB ppm/°C
LSB
LSB
LSB ppm/°C
LSB
dB dB
Rev. A | Page 3 of 32
AD7682/AD7689
Total Harmonic Distortion
(THD)
Spurious-Free Dynamic
Range f f
IN
IN
= 20 kHz
= 20 kHz
Channel-to-Channel Crosstalk f
IN
= 100 kHz on adjacent channel(s)
SAMPLING DYNAMICS
−3 dB Input Bandwidth Full bandwidth
AD7689A AD7682B/AD7689B
Unit
−97 −100 dB
105 110 dB
1.7 1.7 MHz
Aperture Delay 2.5 ns
1
See the Analog Inputs section.
2
The bandwidth is set in the configuration register.
3
LSB means least significant bit. With the 5 V input range, one LSB is 76.3 μV.
4 See the Terminology section. These specifications include full temperature range variation but not the error contribution from the external reference.
5 With VDD = 5 V, unless otherwise noted.
6
All specifications expressed in decibels are referred to a full-scale input FSR and tested with an input signal at 0.5 dB below full scale, unless otherwise specified.
Rev. A | Page 4 of 32
VDD = 2.3 V to 5.5 V, VIO = 1.8 V to VDD, V
REF
= VDD, all specifications T
MIN
to T
MAX
, unless otherwise noted.
AD7682/AD7689
Table 3.
Parameter Conditions/Comments
All Models/Grades
Min Typ Unit
2.490 2.500 2.510 V REF Output Voltage 2.5 V, @ 25°C
2.5
REF Output Current ±300 μA
Line Regulation
Long-Term Drift
Turn-On Settling Time
VDD = 5 V ± 5%
1000 hours
C
REF
= 10 μF
Voltage Range
REF input
REFIN input (buffered)
250 kSPS, REF = 5 V
@
0.5
0.5
±15
50
5
50 ppm/V ppm ms
VDD + 0.3 V
VDD − 0.5 V
μA
V
IL
V
IH
I
IL
I
IH
DIGITAL
V
OL
V
OH
I
I
SINK
= +500 μA
SOURCE
= −500 μA
VDD
VIO
Power Dissipation
Specified performance
VDD and VIO = 5 V, @ 25°C
VDD = 2.5 V, 100 SPS throughput
VDD = 2.5 V, 200 kSPS throughput
VDD = 5 V, 250 kSPS throughput
0.7 × VIO
Energy per Conversion
VDD = 5 V, 250 kSPS throughput with internal reference
VDD = 5V
Specified Performance T
MIN
to T
MAX
1 This is the output from the internal band gap.
2 This is an average current and scales with throughput.
3
The output voltage is internal and present on a dedicated multiplexer input.
4 Unipolar mode: serial 16-bit straight binary.
Bipolar mode: serial 16-bit twos complement.
5
Conversion results available immediately after completed conversion.
6
With all digital inputs forced to VIO or GND as required.
7 During acquisition phase.
8 Contact an Analog Devices, Inc., sales representative for the extended temperature range.
1.8
VIO − 0.3
VIO + 0.3 V
0.4 V
V
VDD + 0.3 V
50
1.7
3.5
12.5 18 nA
μW mW mW
15.5 21
60 mW nJ
Rev. A | Page 5 of 32
AD7682/AD7689
TIMING SPECIFICATIONS
VDD = 4.5 V to 5.5 V, VIO = 1.8 V to VDD, all specifications T
MIN
to T
MAX
, unless otherwise noted.
Table 4.
Parameter 1
Conversion Time: CNV Rising Edge to Data Available
Acquisition Time
Time Between Conversions
Data Write/Read During Conversion
CNV Pulse Width
SCK Period
SCK Low Time
SCK High Time
SCK Falling Edge to Data Remains Valid
SCK Falling Edge to Data Valid Delay
VIO Above 2.7 V
VIO Above 2.3 V
VIO Above 1.8 V
CNV Low to SDO D15 MSB Valid
VIO Above 2.7 V
VIO Above 2.3 V
VIO Above 1.8 V
CNV High or Last SCK Falling Edge to SDO High Impedance
CNV Low to SCK Rising Edge
DIN Valid Setup Time from SCK Rising Edge
DIN Valid Hold Time from SCK Rising Edge
1
See Figure 2 and Figure 3 for load conditions.
Symbol Min Typ Max Unit
t
CONV t
ACQ
1.8 t
CYC
4.0 t
DATA t
CNVH t
SCK t
DSDO
+ 2 ns t
SCKL
11 t
SCKH
ns t
HSDO
4 ns t
DSDO
18 ns
23
28 ns ns t
EN
18
22 ns ns
25 ns t
DIS ns t
CLSCK t
SDIN t
HDIN
5
Rev. A | Page 6 of 32
VDD = 2.3 V to 4.5 V, VIO = 1.8 V to VDD, all specifications T
MIN
to T
MAX
, unless otherwise noted.
Table 5.
Conversion Time: CNV Rising Edge to Data Available
Acquisition Time
Time Between Conversions
Data Write/Read During Conversion
CNV Pulse Width
SCK Period
SCK Low Time
SCK High Time
SCK Falling Edge to Data Remains Valid
SCK Falling Edge to Data Valid Delay
VIO Above 3 V
VIO Above 2.7 V
VIO Above 2.3 V
VIO Above 1.8 V
CNV Low to SDO D15 MSB Valid
VIO Above 3 V
VIO Above 2.7 V
VIO Above 2.3 V
VIO Above 1.8 V
CNV High or Last SCK Falling Edge to SDO High Impedance
CNV Low to SCK Rising Edge
DIN Valid Setup Time from SCK Rising Edge
DIN Valid Hold Time from SCK Rising Edge
1
See Figure 2 and Figure 3 for load conditions.
AD7682/AD7689
Symbol Min Typ Max Unit
t
CONV t
ACQ
1.8 t
CYC
5 t
DATA
1.
2 t
CNVH t
SCK t
DSDO
+ 2 ns t
SCKL
12 t
SCKH
ns t
HSDO
5 ns t
DSDO
24
30 ns ns t
EN
38
48
21 ns ns ns t
DIS
27
35
45 ns ns ns t
CLSCK
10 t
SDIN
5 t
HDIN
500µA I
OL
TO SDO
C
L
50pF
1.4V
500µA I
OH
Figure 2. Load Circuit for Digital Interface Timing
70% VIO
30% VIO t
DELAY
2V OR VIO – 0.5V
1
0.8V OR 0.5V
2 t
DELAY
2V OR VIO – 0.5V
1
0.8V OR 0.5V
2
1
2V IF VIO ABOVE 2.5V, VIO – 0.5V IF VIO BELOW 2.5V.
2
0.8V IF VIO ABOVE 2.5V, 0.5V IF VIO BELOW 2.5V.
Figure 3. Voltage Levels for Timing
Rev. A | Page 7 of 32
AD7682/AD7689
ABSOLUTE MAXIMUM RATINGS
Table 6.
Parameter Rating
Analog Inputs
GND − 0.3 V to VDD + 0.3 V or VDD ± 130 mA
REF, REFIN
Supply Voltages
VDD, VIO to GND
VDD to VIO
DIN, CNV, SCK to GND
SDO to GND
Storage Temperature Range
Junction Temperature
θ
JA
Thermal Impedance (LFCSP)
θ
JC
Thermal Impedance (LFCSP)
1
See the Analog Inputs section.
GND − 0.3 V to VDD + 0.3 V
−0.3 V to +7 V
±7 V
−0.3 V to VIO + 0.3 V
−0.3 V to VIO + 0.3 V
−65°C to +150°C
150°C
47.6°C/W
4.4°C/W
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ESD CAUTION
Rev. A | Page 8 of 32
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
AD7682/AD7689
VDD
REF
REFIN
GND
GND
1
2
3
4
5
PIN 1
INDICATOR
AD7682
TOP VIEW
(Not to Scale)
15 VIO
14 SDO
13 SCK
12 DIN
11 CNV
VDD
REF
REFIN
GND
GND
1
2
3
4
5
PIN 1
INDICATOR
AD7689
TOP VIEW
(Not to Scale)
15 VIO
14 SDO
13 SCK
12 DIN
11 CNV
NOTES
1. NC = NO CONNECT.
2. THE EXPOSED PAD IS NOT CONNECTED
INTERNALLY. FOR INCREASED
RELIABILITY OF THE SOLDER JOINTS, IT
IS RECOMMENDED THAT THE PAD BE
SOLDERED TO THE SYSTEM
GROUND PLANE.
Figure 4. AD7682 Pin Configuration
NOTES
1. THE EXPOSED PAD IS NOT CONNECTED
INTERNALLY. FOR INCREASED
RELIABILITY OF THE SOLDER JOINTS, IT
IS RECOMMENDED THAT THE PAD BE
SOLDERED TO THE SYSTEM
GROUND PLANE.
Figure 5. AD7689 Pin Configuration
Table 7. Pin Function Descriptions
Pin No.
AD7682
Mnemonic
AD7689
1, 20 VDD VDD P Power Supply. Nominally 2.5 V to 5.5 V when using an external reference and decoupled with 10 μF and 100 nF capacitors.
When using the internal reference for a2.5 V output, the minimum should be 3.0 V.
When using the internal reference for 4.096 V output, the minimum should be 4.6 V.
2 REF REF AI/O
When the internal reference is enabled, this pin produces a selectable system reference of
2.5 V or 4.096 V.
When the internal reference is disabled and the buffer is enabled, REF produces a buffered version of the voltage present on the REFIN pin (VDD − 0.5 V maximum), which is useful when using low cost, low power references.
For improved drift performance, connect a precision reference to REF (0.5 V to VDD).
For any reference method, this pin needs decoupling with an external 10 μF capacitor
connected as close to REF as possible. See the Reference Decoupling section.
When using the internal reference, the internal unbuffered reference voltage is present and needs decoupling with a 0.1 μF capacitor.
When using the internal reference buffer, apply a source between 0.5 V and (VDD − 0.5 V) that is buffered to the REF pin, as described in the REF pin description.
4, 5 GND GND P Power Supply Ground.
6 NC IN4 AI
AD7689: Analog Input Channel 4.
7 IN2 IN5 AI
AD7689: Analog Input Channel 5.
8 NC IN6 AI
AD7689: Analog Input Channel 6.
9 IN3 IN7 AI
AD7689: Analog Input Channel 7.
10 COM COM AI Common Channel Input. All input channels, IN[7:0], can be referenced to a commonmode point of 0 V or V
REF
/2 V.
11 CNV CNV DI Conversion Input. On the rising edge, CNV initiates the conversion. During conversion, if
CNV is held low, the busy indictor is enabled.
12 DIN DIN DI Data Input. This input is used for writing to the 14-bit configuration register. The configuration register can be written to during and after conversion.
13 SCK SCK DI Serial Data Clock Input. This input is used to clock out the data on SDO and clock in data on DIN in an MSB first fashion.
Rev. A | Page 9 of 32
AD7682/AD7689
Pin No.
AD7682
Mnemonic
AD7689
14 SDO SDO DO unipolar modes, conversion results are straight binary; in bipolar modes, conversion results are twos complement.
15 VIO VIO P Input/Output Interface Digital Power. Nominally at the same supply as the host interface
(1.8 V, 2.5 V, 3 V, or 5 V).
16 IN0
17 NC
IN0 AI Analog Input Channel 0.
IN1 AI AD7682: no connection.
AD7689: Analog Input Channel 1.
18 IN1 IN2 AI AD7682: Analog Input Channel 1.
AD7689: Analog Input Channel 2.
19 NC IN3 AI AD7682: no connection.
AD7689: Analog Input Channel 3.
21
(EPAD)
Exposed Pad
(EPAD)
Exposed
Pad (EPAD)
NC The exposed pad is not connected internally. For increased reliability of the solder joints, it is recommended that the pad be soldered to the system ground plane.
1
AI = analog input, AI/O = analog input/output, DI = digital input, DO = digital output, P = power, NC = no internal connection.
Rev. A | Page 10 of 32
TYPICAL PERFORMANCE CHARACTERISTICS
VDD = 2.5 V to 5.5 V, V
REF
= 2.5 V to 5 V, VIO = 2.3 V to VDD, unless otherwise noted.
1.5
INL MAX = +0.34 LSB
INL MIN = –0.44 LSB
1.0
1.5
DNL MAX = +0.20 LSB
DNL MIN = –0.22 LSB
1.0
0.5
0.5
0
0
–0.5
–0.5
–1.0
–1.5
0 16,384 32,768
CODES
49,152 65,536
Figure 6. Integral Nonlinearity vs. Code, V
REF
= VDD = 5 V
200k
180k
160k
140k
120k
100k
80k
60k
40k
135,326
124,689
σ = 0.50
V
REF
= VDD = 5V
20k
0
0
7FFA
0 487 619 0 0 0
7FFB 7FFC 7FFD 7FFE 7FFF 8000 8001 8002
CODE IN HEX
Figure 7. Histogram of a DC Input at Code Center
0
–20
–40
–60
–80 f f
V
REF
= VDD = 5V
S
= 250kSPS
IN
= 19.9kHz
SNR = 92.9dB
SINAD = 92.4dB
THD = –102dB
SFDR = 103dB
SECOND HARMONIC = –111dB
THIRD HARMONIC = –104dB
–100
–120
–140
–160
–180
0 125 25 50 75
FREQUENCY (kHz)
Figure 8. 20 kHz FFT, V
REF
= VDD = 5 V
100
AD7682/AD7689
–1.0
0 16,384 32,768
CODES
49,152 65,536
Figure 9. Differential Nonlinearity vs. Code, V
REF
= VDD = 5 V
160k
σ = 0.78
V
REF
= VDD = 2.5V
140k
135,207
120k
100k
80k
63,257
60k
51,778
40k
–120
–140
–160
–180
0
20k
0
6649
1 78
4090
60 1
7FFB 7FFC 7FFD 7FFE 7FFF 8000 8001 8002 8003
CODE IN HEX
Figure 10. Histogram of a DC Input at Code Center
0
–20
–40
–60
–80 f f
V
REF
= VDD = 2.5V
s
= 200kSPS
IN
= 19.9kHz
SNR = 88.0dB
SINAD = 87.0dB
THD = –89dB
SFDR = 89dB
SECOND HARMONIC = –105dB
THIRD HARMONIC = –90dB
–100
25 50
FREQUENCY (kHz)
75
Figure 11. 20 kHz FFT, V
REF
= VDD = 2.5 V
100
Rev. A | Page 11 of 32
AD7682/AD7689
100
85
80
75
95
90
70
65
60
0
V
REF
= VDD = 5V, –0.5dB
V
REF
V
REF
V
REF
= VDD = 5V, –10dB
= VDD = 2.5V, –0.5dB
= VDD = 2.5V, –10dB
50 100
FREQUENCY (kHz)
Figure 12. SNR vs. Frequency
150 200
84
82
88
86
92
90
96
94
SNR @ 2kHz
SINAD @ 2kHz
SNR @ 20kHz
SINAD @ 20kHz
ENOB @ 2kHz
ENOB @ 20kHz
80
1.0
1.5
2.0
2.5
3.0
3.5
4.0
REFERENCE VOLTAGE (V)
4.5
5.0
5.5
13.0
Figure 13. SNR, SINAD, and ENOB vs. Reference Voltage
96 f
IN
= 20kHz
94
V
REF
= VDD = 5V
15.0
14.5
14.0
13.5
17.0
16.5
16.0
15.5
92
90
88
86
V
REF
= VDD = 2.5V
84
–55 –35 –15 5 25 45 65
TEMPERATURE (°C)
Figure 14. SNR vs. Temperature
85 105 125
100
95
90
85
80
75
70
65
V
REF
= VDD = 5V, –0.5dB
V
REF
V
REF
V
REF
= VDD = 5V, –10dB
= VDD = 2.5V, –0.5dB
= VDD = 2.5V, –10dB
60
0 50 100
FREQUENCY (kHz)
150
Figure 15. SINAD vs. Frequency
200
95
90
85
80
75
70
1.0
130
125
120
115
110
105
100
SFDR = 2kHz
SFDR = 20kHz
THD = 20kHz
THD = 2kHz
1.5
2.0
2.5
3.0
3.5
4.0
REFERENCE VOLTAGE (V)
4.5
5.0
Figure 16. SFDR and THD vs. Reference Voltage
–95
–100
–105
–110
–115
5.5
–120
–60
–65
–70
–75
–80
–85
–90
–90 f
IN
= 20kHz
–95
V
REF
= VDD = 5V
V
REF
= VDD = 2.5V
–100
–105
–110
–55 –35 –15 5 25 45 65
TEMPERATURE (°C)
Figure 17. THD vs. Temperature
85 105
125
Rev. A | Page 12 of 32
–60
–70
–80
–90
–100
–110
–120
0
95
94 f
IN
= 20kHz
89
88
87
86
85
–10
93
92
91
90
–8
50 100
V
REF
= VDD = 5V, –0.5dB
V
REF
V
REF
V
REF
= VDD = 2.5V, –0.5dB
= VDD = 2.5V, –10dB
= VDD = 5V, –10dB
150 200
FREQUENCY (kHz)
Figure 18. THD vs. Frequency
V
REF
= VDD = 5V
V
REF
= VDD = 2.5V
–6 –4
INPUT LEVEL (dB)
–2 0
Figure 19. SNR vs. Input Level
3
2
1
0
–1
–2
UNIPOLAR ZERO
UNIPOLAR GAIN
BIPOLAR ZERO
BIPOLAR GAIN
–3
–55 –35 –15 5 25 45 65
TEMPERATURE (°C)
85 105
125
Figure 20. Offset and Gain Errors vs. Temperature
AD7682/AD7689
3000
2750
2500
2250
2000
1750
1500
2.5V INTERNAL REF
4.096V INTERNAL REF
INTERNAL BUFFER, TEMP ON
INTERNAL BUFFER, TEMP OFF
EXTERNAL REF, TEMP ON
EXTERNAL REF, TEMP OFF
VIO f
S
= 200kSPS
1250
1000
2.5
3.0
3.5
4.0
VDD SUPPLY (V)
4.5
5.0
Figure 21. Operating Currents vs. Supply
3000
2750 f
S
= 200kSPS
2500
VDD = 5V, INTERNAL 4.096V REF
2250
2000
VDD = 5V, EXTERNAL REF
1750
1500
VDD = 2.5, EXTERNAL REF
1250
1000
–55 –35 –15 5
VIO
25 45 65
TEMPERATURE (°C)
85 105
40
125
20
80
60
180
160
140
120
100
40
30
5.5
20
60
50
80
70
100
90
Figure 22. Operating Currents vs. Temperature
25
VDD = 2.5V, 85°C
20
15
VDD = 2.5V, 25°C
10
VDD = 5V, 85°C
VDD = 5V, 25°C
5
VDD = 3.3V, 85°C
VDD = 3.3V, 25°C
0
0 20 40 60 80
SDO CAPACITIVE LOAD (pF)
100
Figure 23. t
DSDO
Delay vs. SDO Capacitance Load and Supply
120
Rev. A | Page 13 of 32
AD7682/AD7689
TERMINOLOGY
Least Significant Bit (LSB)
The LSB is the smallest increment that can be represented by a converter. For an analog-to-digital converter with N bits of resolution, the LSB expressed in volts is
LSB
(V)
V
REF
2
N
Integral Nonlinearity Error (INL)
INL refers to the deviation of each individual code from a line drawn from negative full scale through positive full scale. The point used as negative full scale occurs ½ LSB before the first code transition. Positive full scale is defined as a level 1½ LSB beyond the last code transition. The deviation is measured from
the middle of each code to the true straight line (see Figure 25).
Differential Nonlinearity Error (DNL)
In an ideal ADC, code transitions are 1 LSB apart. DNL is the maximum deviation from this ideal value. It is often specified in terms of resolution for which no missing codes are guaranteed.
Offset Error
The first transition should occur at a level ½ LSB above analog ground. The offset error is the deviation of the actual transition from that point.
Gain Error
The last transition (from 111 … 10 to 111 … 11) should occur for an analog voltage 1½ LSB below the nominal full scale. The gain error is the deviation in LSB (or percentage of full-scale range) of the actual level of the last transition from the ideal level after the offset error is adjusted out. Closely related is the full-scale error (also in LSB or percentage of full-scale range), which includes the effects of the offset error.
Aperture Delay
Aperture delay is the measure of the acquisition performance. It is the time between the rising edge of the CNV input and the point at which the input signal is held for a conversion.
Transient Response
Transient response is the time required for the ADC to accurately acquire its input after a full-scale step function is applied.
Dynamic Range
Dynamic range is the ratio of the rms value of the full scale to the total rms noise measured with the inputs shorted together.
The value for dynamic range is expressed in decibels.
Signal-to-Noise Ratio (SNR)
SNR is the ratio of the rms value of the actual input signal to the rms sum of all other spectral components below the Nyquist frequency, excluding harmonics and dc. The value for SNR is expressed in decibels.
Signal-to-(Noise + Distortion) Ratio (SINAD)
SINAD is the ratio of the rms value of the actual input signal to the rms sum of all other spectral components below the Nyquist frequency, including harmonics but excluding dc. The value for
SINAD is expressed in decibels.
Total Harmonic Distortion (THD)
THD is the ratio of the rms sum of the first five harmonic components to the rms value of a full-scale input signal and is expressed in decibels.
Spurious-Free Dynamic Range (SFDR)
SFDR is the difference, in decibels, between the rms amplitude of the input signal and the peak spurious signal.
Effective Number of Bits (ENOB)
ENOB is a measurement of the resolution with a sine wave input. It is related to SINAD by the formula
ENOB
= (SINAD dB
− 1.76)/6.02 and is expressed in bits.
Channel-to-Channel Crosstalk
Channel-to-channel crosstalk is a measure of the level of crosstalk between any two adjacent channels. It is measured by applying a dc to the channel under test and applying a full-scale, 100 kHz sine wave signal to the adjacent channel(s). The crosstalk is the amount of signal that leaks into the test channel and is expressed in decibels.
Reference Voltage Temperature Coefficient
Reference voltage temperature coefficient is derived from the typical shift of output voltage at 25°C on a sample of parts at the maximum and minimum reference output voltage (V
REF
) measured at T
MIN
, T (25°C), and T
MAX
. It is expressed in ppm/°C as
TCV
REF
( ppm/
C )
V
V
REF
REF
(
Max
) –
V
REF
(
25
C
)
(
T
MAX
(
Min
)
–
T
MIN
)
10
6 where:
V
REF
(Max) = maximum V
REF
at T
MIN
, T (25°C), or T
MAX
.
V
REF
(Min) = minimum V
REF
at T
MIN
, T (25°C), or T
MAX
.
V
REF
(25°C) = V
REF
at 25°C.
T
MAX
= +85°C.
T
MIN
= –40°C.
Rev. A | Page 14 of 32
THEORY OF OPERATION
INx+
AD7682/AD7689
REF
GND
32,768C
MSB
16,384C
32,768C 16,384C
MSB
4C
4C
2C
2C
C
C
C
C
LSB SW+
SWITCHES CONTROL
COMP
CONTROL
LOGIC
BUSY
OUTPUT CODE
LSB SW–
CNV
INx– OR
COM
Figure 24. ADC Simplified Schematic
OVERVIEW
The AD7682/AD7689 are 4-channel/8-channel, 16-bit, charge redistribution successive approximation register (SAR) analogto-digital converters (ADCs). These devices are capable of converting 250,000 samples per second (250 kSPS) and power down between conversions. For example, when operating with an external reference at 1 kSPS, they consume 17 μW typically, ideal for battery-powered applications.
The AD7682/AD7689 contain all of the components for use in a multichannel, low power data acquisition system, including
16-bit SAR ADC with no missing codes
4-channel/8-channel, low crosstalk multiplexer
Internal low drift reference and buffer
Temperature sensor
Selectable one-pole filter
Channel sequencer
These components are configured through an SPI-compatible,
14-bit register. Conversion results, also SPI compatible, can be read after or during conversions with the option for reading back the configuration associated with the conversion.
The AD7682/AD7689 provide the user with an on-chip trackand-hold and do not exhibit pipeline delay or latency.
The AD7682/AD7689 are specified from 2.3 V to 5.5 V and can be interfaced to any 1.8 V to 5 V digital logic family. They are housed in a 20-lead, 4 mm × 4 mm LFCSP that combines space savings and allows flexible configurations. They are pin-for-pin compatible with the 16-bit AD7699 and 14-bit AD7949 .
CONVERTER OPERATION
The AD7682/AD7689 are successive approximation ADCs
based on a charge redistribution DAC. Figure 24 shows the
simplified schematic of the ADC. The capacitive DAC consists of two identical arrays of 16 binary-weighted capacitors, which are connected to the two comparator inputs.
During the acquisition phase, terminals of the array tied to the comparator input are connected to GND via SW+ and SW−. All independent switches are connected to the analog inputs.
Thus, the capacitor arrays are used as sampling capacitors and acquire the analog signal on the INx+ and INx− (or COM) inputs. When the acquisition phase is complete and the CNV input goes high, a conversion phase is initiated. When the conversion phase begins, SW+ and SW− are opened first. The two capacitor arrays are then disconnected from the inputs and connected to the GND input. Therefore, the differential voltage between the INx+ and INx− (or COM) inputs captured at the end of the acquisition phase is applied to the comparator inputs, causing the comparator to become unbalanced. By switching each element of the capacitor array between GND and REF, the comparator input varies by binary-weighted voltage steps
(V
REF
/2, V
REF
/4, ... V
REF
/32,768). The control logic toggles these switches, starting with the MSB, to bring the comparator back into a balanced condition. After the completion of this process, the part returns to the acquisition phase, and the control logic generates the ADC output code and a busy signal indicator.
Because the AD7682/AD7689 have an on-board conversion clock, the serial clock, SCK, is not required for the conversion process.
Rev. A | Page 15 of 32
AD7682/AD7689
TRANSFER FUNCTIONS
With the inputs configured for unipolar range (single-ended,
COM with ground sense, or paired differentially with INx− as ground sense), the data output is straight binary.
With the inputs configured for bipolar range (COM = V
REF
/2 or paired differentially with INx− = V
REF
/2), the data outputs are twos complement.
The ideal transfer characteristic for the AD7682/AD7689 is
shown in Figure 25 and for both unipolar and bipolar ranges
with the internal 4.096 V reference.
TWOS
COMPLEMENT
011...111
011...110
011...101
STRAIGHT
BINARY
111...111
111...110
111...101
100...010
100...001
100...000
000...010
000...001
000...000
–FSR
–FSR + 1LSB
–FSR + 0.5LSB
+FSR – 1LSB
+FSR – 1.5LSB
ANALOG INPUT
Figure 25. ADC Ideal Transfer Function
Table 8. Output Codes and Ideal Input Voltages
Description
V
REF
= 4.096 V
FSR − 1 LSB 4.095938 V
Digital Output Code
(Straight Binary Hex)
Bipolar Analog Input
V
REF
= 4.096 V
2
Digital Output Code
(Twos Complement Hex)
Midscale + 1 LSB 2.048063 V 0x8001 62.5 μV 0x0001
Midscale 2.048 V
Midscale − 1 LSB 2.047938 V
−FSR + 1 LSB 62.5 μV
0x8000
0x7FFF
0x0001
1 With COM or INx− = 0 V or all INx referenced to GND.
2 With COM or INx− = V
REF
/2.
3
This is also the code for an overranged analog input ((INx+) − (INx−), or COM, above V
REF
− GND).
4
This is also the code for an underranged analog input ((INx+) − (INx−), or COM, below GND).
0 V
−62.5 μV
−2.047938 V
−2.048 V
0x0000
0xFFFF
0x8001
Rev. A | Page 16 of 32
TYPICAL CONNECTION DIAGRAMS
10µF
2
100nF
5V 1.8V TO VDD
100nF
100nF
V+
0V TO V
REF
ADA4841-x
3
V–
V+
IN0
REF
REFIN VDD
AD7689
IN[7:1]
VIO
0V TO V
REF
ADA4841-x
3
V–
0V OR
V
REF
/2
COM
DIN
SCK
SDO
CNV
MOSI
SCK
MISO
SS
GND
NOTES
1. INTERNAL REFERENCE SHOWN. SEE VOLTAGE REFERENCE OUTPUT/INPUT SECTION FOR
REFERENCE SELECTION.
2. C
REF
IS USUALLY A 10µF CERAMIC CAPACITOR (X5R).
3. SEE THE DRIVER AMPLIFIER CHOICE SECTION FOR ADDITIONAL RECOMMENDED AMPLIFIERS.
4. SEE THE DIGITAL INTERFACE SECTION FOR CONFIGURING AND READING CONVERSION DATA.
Figure 26. Typical Application Diagram with Multiple Supplies
+5V
1.8V TO VDD
10µF
2
V+
ADA4841-x
V–
3
100nF
REF
IN0
AD7689
100nF
REFIN VDD
IN[7:1]
V+
V–
ADA4841-x
3
100nF
VIO
DIN
SCK
SDO
CNV
V
REF
p-p
V
REF
/2
COM
GND
NOTES
1. INTERNAL REFERENCE SHOWN. SEE VOLTAGE REFERENCE OUTPUT/INPUT SECTION FOR
REFERENCE SELECTION.
2. C
REF
IS USUALLY A 10µF CERAMIC CAPACITOR (X5R).
3. SEE THE DRIVER AMPLIFIER CHOICE SECTION FOR ADDITIONAL RECOMMENDED AMPLIFIERS.
4. SEE THE DIGITAL INTERFACE SECTION FOR CONFIGURING AND READING CONVERSION DATA.
Figure 27. Typical Application Diagram Using Bipolar Input
MOSI
SCK
MISO
SS
AD7682/AD7689
Rev. A | Page 17 of 32
AD7682/AD7689
Unipolar or Bipolar
Figure 26 shows an example of the recommended connection
diagram for the AD7682/AD7689 when multiple supplies are available.
Bipolar Single Supply
Figure 27 shows an example of a system with a bipolar input
using single supplies with the internal reference (optional different VIO supply). This circuit is also useful when the amplifier/signal conditioning circuit is remotely located with some common mode present. Note that for any input configuration, the INx inputs are unipolar and are always referenced to GND (no negative voltages even in bipolar range).
For this circuit, a rail-to-rail input/output amplifier can be used; however, the offset voltage vs. input common-mode range should be noted and taken into consideration (1 LSB = 62.5 μV with
V
REF
= 4.096 V). Note that the conversion results are in twos complement format when using the bipolar input configuration.
Refer to the AN-581 Application Note, Biasing and Decoupling
Op Amps in Single Supply Applications,
at www.analog.com
for additional details about using single-supply amplifiers.
ANALOG INPUTS
Input Structure
Figure 28 shows an equivalent circuit of the input structure of
the AD7682/AD7689. The two diodes, D1 and D2, provide ESD protection for the analog inputs, IN[7:0] and COM. Care must be taken to ensure that the analog input signal does not exceed the supply rails by more than 0.3 V because this causes the diodes to become forward biased and to start conducting current.
These diodes can handle a forward-biased current of 130 mA maximum. For instance, these conditions may eventually occur when the input buffer supplies are different from VDD. In such a case, for example, an input buffer with a short circuit, the current limitation can be used to protect the part.
VDD
INx+
OR INx–
OR COM
D1
R
IN
C
IN
C
PIN
D2
GND
Figure 28. Equivalent Analog Input Circuit
This analog input structure allows the sampling of the true differential signal between INx+ and COM or INx+ and INx−.
(COM or INx− = GND ± 0.1 V or V
REF
± 0.1 V). By using these differential inputs, signals common to both inputs are rejected,
60
55
70
65
50
45
40
35
30
1 10 100
FREQUENCY (kHz)
1k
Figure 29. Analog Input CMRR vs. Frequency
10k
During the acquisition phase, the impedance of the analog inputs can be modeled as a parallel combination of the capacitor, C
PIN
, and the network formed by the series connection of R
IN
and C
IN
.
C
PIN
is primarily the pin capacitance. R
IN
is typically 2.2 kΩ and is a lumped component composed of serial resistors and the on resistance of the switches. C
IN
is typically 27 pF and is mainly the ADC sampling capacitor.
Selectable Low-Pass Filter
During the conversion phase, where the switches are opened, the input impedance is limited to C
PIN
. While the AD7682/
AD7689 are acquiring, R
IN
and C
IN
make a one-pole, low-pass filter that reduces undesirable aliasing effects and limits the noise from the driving circuitry. The low-pass filter can be programmed for the full bandwidth or ¼ of the bandwidth with
CFG[6], as shown in Table 10. This setting changes R
IN
to 19 kΩ.
Note that the converter throughput must also be reduced by ¼ when using the filter. If the maximum throughput is used with the bandwidth (BW) set to ¼, the converter acquisition time, t
ACQ
, is violated, resulting in increased THD.
Rev. A | Page 18 of 32
Input Configurations
Figure 30 shows the different methods for configuring the analog
inputs with the configuration register, CFG[12:10]. Refer to the
Configuration Register, CFG, section for more details.
The analog inputs can be configured as
Figure 30A, single-ended referenced to system ground;
CFG[12:10] = 111
2
.
In this configuration, all inputs (IN[7:0]) have a range of
GND to V
REF
.
Figure 30B, bipolar differential with a common reference
point; COM = V
REF
/2; CFG[12:10] = 010
2
.
Unipolar differential with COM connected to a ground sense; CFG[12:10] = 110
2
.
In this configuration, all inputs IN[7:0] have a range of
GND to V
REF
.
Figure 30C, bipolar differential pairs with the negative
input channel referenced to V
REF
/2; CFG[12:10] = 00X
2
.
Unipolar differential pairs with the negative input channel referenced to a ground sense; CFG[12:10] = 10X
2
.
In these configurations, the positive input channels have the range of GND to V
REF
. The negative input channels are a sense referred to V
REF
/2 for bipolar pairs, or GND for unipolar pairs. The positive channel is configured with
CFG[9:7]. If CFG[9:7] is even, then IN0, IN2, IN4, and IN6 are used. If CFG[9:7] is odd, then IN1, IN3, IN5, and IN7 are used, as indicated by the channels with parentheses in
Figure 30C. For example, for IN0/IN1 pairs with the
positive channel on IN0, CFG[9:7] = 000
2
. For IN4/IN5 pairs with the positive channel on IN5, CFG[9:7] = 101
2
.
Note that for the sequencer, detailed in the Channel
Sequencer section, the positive channels are always IN0,
IN2, IN4, and IN6.
Figure 30D, inputs configured in any of the preceding
combinations (showing that the AD7682/AD7689 can be configured dynamically).
AD7682/AD7689
CH0+
CH1+
CH2+
CH3+
CH4+
CH5+
CH6+
CH7+
IN0
IN1
IN2
IN3
IN4
IN5
IN6
IN7
COM
GND
A—8 CHANNELS,
SINGLE ENDED
CH0+
CH1+
CH2+
CH3+
CH4+
CH5+
CH6+
CH7+
COM–
IN4
IN5
IN6
IN7
COM
GND
IN0
IN1
IN2
IN3
B—8 CHANNELS,
COMMON REFERNCE
CH0+ (–)
CH0– (+)
CH1+ (–)
CH1– (+)
CH2+ (–)
CH2– (+)
CH3+ (–)
CH3– (+)
IN4
IN5
IN6
IN7
IN0
IN1
IN2
IN3
COM
GND
CH0+ (–)
CH0– (+)
CH1+ (–)
CH1– (+)
CH2+
CH3+
CH4+
CH5+
COM–
IN4
IN5
IN6
IN7
IN0
IN1
IN2
IN3
COM
GND
C—4 CHANNELS,
DIFFERENTIAL
D—COMBINATION
Figure 30. Multiplexed Analog Input Configurations
Sequencer
The AD7682/AD7689 include a channel sequencer useful for
scanning channels in a repeated fashion. Refer to the Channel
Sequencer section for further details of the sequencer operation.
Source Resistance
When the source impedance of the driving circuit is low, the
AD7682/AD7689 can be driven directly. Large source impedances significantly affect the ac performance, especially THD.
The dc performances are less sensitive to the input impedance.
The maximum source impedance depends on the amount of
THD that can be tolerated. The THD degrades as a function of the source impedance and the maximum input frequency.
Rev. A | Page 19 of 32
AD7682/AD7689
DRIVER AMPLIFIER CHOICE
Although the AD7682/AD7689 are easy to drive, the driver amplifier must meet the following requirements:
The noise generated by the driver amplifier must be kept as low as possible to preserve the SNR and transition noise performance of the AD7682/AD7689. Note that the AD7682/
AD7689 have a noise much lower than most of the other
16-bit ADCs and, therefore, can be driven by a noisier amplifier to meet a given system noise specification. The noise from the amplifier is filtered by the AD7682/AD7689 analog input circuit low-pass filter made by R
IN
and C
IN
or by an external filter, if one is used. Because the typical noise of the AD7682/AD7689 is 35 μV rms (with V
REF
= 5 V), the
SNR degradation due to the amplifier is
SNR
LOSS
20 log
35
2
π
2
35
f
3dB
(
Ne
N
)
2
where:
f
–3dB
is the input bandwidth in megahertz of the AD7682/
AD7689 (1.7 MHz in full BW or 425 kHz in ¼ BW) or the cutoff frequency of an input filter, if one is used.
N is the noise gain of the amplifier (for example, 1 in buffer configuration).
e
N
is the equivalent input noise voltage of the op amp, in nV/√Hz.
For ac applications, the driver should have a THD perfor-
mance commensurate with the AD7682/AD7689. Figure 18
shows THD vs. frequency for the AD7682/AD7689.
For multichannel, multiplexed applications on each input or input pair, the driver amplifier and the AD7682/AD7689 analog input circuit must settle a full-scale step onto the capacitor array at a 16-bit level (0.0015%). In amplifier data sheets, settling at 0.1% to 0.01% is more commonly specified. This may differ significantly from the settling time at a 16-bit level and should be verified prior to driver selection.
Table 9. Recommended Driver Amplifiers
ADA4841-x
AD8655
AD8021
Very low noise, small, and low power
5 V single supply, low noise
Very low noise and high frequency
AD8022
OP184
Low noise and high frequency
Low power, low noise, and low frequency
AD8605 , AD8615 5 V single supply, low power
VOLTAGE REFERENCE OUTPUT/INPUT
The AD7682/AD7689 allow the choice of a very low temperature drift internal voltage reference, an external reference, or an external buffered reference.
The internal reference of the AD7682/AD7689 provide excellent performance and can be used in almost all applications.
There are six possible choices of voltage reference schemes
briefly described in Table 10, with more details in each of the
following sections.
Internal Reference/Temperature Sensor
The precision internal reference, suitable for most applications, can be set for either a 2.5 V or a 4.096 V output, as detailed in
Table 10. With the internal reference enabled, the band gap
voltage is also present on the REFIN pin, which requires an external 0.1 μF capacitor. Because the current output of REFIN is limited, it can be used as a source if followed by a suitable buffer, such as the AD8605. Note that the voltage of REFIN changes depending on the 2.5 V or 4.096 V internal reference.
Enabling the reference also enables the internal temperature sensor, which measures the internal temperature of the
AD7682/AD7689 and is thus useful for performing a system calibration. Note that, when using the temperature sensor, the output is straight binary referenced from the AD7682/AD7689
GND pin.
The internal reference is temperature-compensated to within
10 mV. The reference is trimmed to provide a typical drift of
±10 ppm/°C.
Connect the AD7682/AD7689 as shown in Figure 31 for either
a 2.5 V or 4.096 V internal reference.
10 µ F
REF
100nF
REFIN
AD7682/
AD7689
TEMP
GND
Figure 31. 2.5 V or 4.096 V Internal Reference Connection
Rev. A | Page 20 of 32
External Reference and Internal Buffer
For improved drift performance, an external reference can be
used with the internal buffer, as shown in Figure 32. The
external source is connected to REFIN, the input to the on-chip unity gain buffer, and the output is produced on the REF pin.
An external reference can be used with the internal buffer with
or without the temperature sensor enabled. Refer to Table 10 for
register details. With the buffer enabled, the gain is unity and is limited to an input/output of VDD = −0.2 V; however, the maximum voltage allowable must be ≤(VDD − 0.5 V).
The internal reference buffer is useful in multiconverter applications because a buffer is typically required in these applications.
In addition, a low power reference can be used because the internal buffer provides the necessary performance to drive the
SAR architecture of the AD7682/AD7689.
REF SOURCE
≤ (VDD – 0.5V)
10 µ F
REF
100nF
REFIN
AD7682/
AD7689
TEMP
GND
Figure 32. External Reference Using Internal Buffer
External Reference
In any of the six voltage reference schemes, an external reference
can be connected directly on the REF pin as shown in Figure 33
because the output impedance of REF is >5 kΩ. To reduce power consumption, the reference and buffer should be powered down.
For applications requiring the use of the temperature sensor, the internal reference must be active (internal buffer can be
disabled in this case). Refer to Table 10 for register details. For
improved drift performance, an external reference such as the
ADR43x or ADR44x is recommended.
10 µ F
REF
REF SOURCE
0.5V < REF < (VDD + 0.3V)
NO CONNECTION
REQUIRED
REFIN
AD7682/
AD7689
TEMP
GND
Figure 33.External Reference
Note that the best SNR is achieved with a 5 V external reference as the internal reference is limited to 4.096 V. The SNR degradation is as follows:
SNR
LOSS
20 log
4 .
096
5
AD7682/AD7689
Reference Decoupling
Whether using an internal or external reference, the AD7682/
AD7689 voltage reference output/input, REF, has a dynamic input impedance and should therefore be driven by a low impedance source with efficient decoupling between the REF and GND pins. This decoupling depends on the choice of the voltage reference but usually consists of a low ESR capacitor connected to REF and GND with minimum parasitic inductance.
A 10 μF (X5R, 1206 size) ceramic chip capacitor is appropriate when using the internal reference, the ADR43x/ADR44x external reference, or a low impedance buffer such as the
AD8031 or the AD8605 .
The placement of the reference decoupling capacitor is also important to the performance of the AD7682/AD7689, as explained in
the Layout section. Mount the decoupling capacitor on the same
side as the ADC at the REF pin with a thick PCB trace. The GND should also connect to the reference decoupling capacitor with the shortest distance and to the analog ground plane with several vias.
If desired, smaller reference decoupling capacitor values down to 2.2 μF can be used with a minimal impact on performance, especially on DNL.
Regardless, there is no need for an additional lower value ceramic decoupling capacitor (for example, 100 nF) between the REF and GND pins.
For applications that use multiple AD7682/AD7689 devices or other PulSAR devices, it is more effective to use the internal reference buffer to buffer the external reference voltage, thus reducing SAR conversion crosstalk.
The voltage reference temperature coefficient (TC) directly impacts full scale; therefore, in applications where full-scale accuracy matters, care must be taken with the TC. For instance, a ±10 ppm/°C TC of the reference changes full scale by ±1 LSB/°C.
Rev. A | Page 21 of 32
AD7682/AD7689
POWER SUPPLY
The AD7682/AD7689 use two power supply pins: an analog and digital core supply (VDD) and a digital input/output interface supply (VIO). VIO allows direct interface with any logic between 1.8 V and VDD. To reduce the supplies needed, the
VIO and VDD pins can be tied together. The AD7682/AD7689 are independent of power supply sequencing between VIO and
VDD. Additionally, it is very insensitive to power supply varia-
tions over a wide frequency range, as shown in Figure 34.
75
60
55
50
70
65
45
40
35
30
1 10 100
FREQUENCY (kHz)
Figure 34. PSRR vs. Frequency
1k 10k
The AD7682/AD7689 power down automatically at the end of each conversion phase; therefore, the operating currents and power scale linearly with the sampling rate. This makes the part ideal for low sampling rates (even of a few hertz) and low battery-powered applications.
10,000
1000 VDD = 5V, INTERNAL REF
100
10
1
0.1
0.010
VDD = 5V, EXTERNAL REF
VDD = 2.5V, EXTERNAL REF
VIO
0.001
10 100 1k 10k
SAMPLING RATE (SPS)
100k
Figure 35. Operating Currents vs. Sampling Rate
1M
SUPPLYING THE ADC FROM THE REFERENCE
For simplified applications, the AD7682/AD7689, with their low operating current, can be supplied directly using an
external reference circuit like the one shown in Figure 36. The
reference line can be driven by:
The system power supply directly
A reference voltage with enough current output capability, such as the ADR43x / ADR44x
A reference buffer, such as the
AD8605 , which can also
filter the system power supply, as shown in Figure 36
5V
5V
5V 10kΩ
1µF
AD8605
10µF
1
10Ω
1µF
0.1µF 0.1µF
REF VDD
AD7689
VIO
1
OPTIONAL REFERENCE BUFFER AND FILTER.
Figure 36. Example of an Application Circuit
Rev. A | Page 22 of 32
DIGITAL INTERFACE
The AD7682/AD7689 use a simple 4-wire interface and are compatible with SPI, MICROWIRE™, QSPI™, digital hosts, and DSPs, for example, Blackfin® ADSP-BF53x, SHARC®,
ADSP-219x, and ADSP-218x.
The interface uses the CNV, DIN, SCK, and SDO signals and allows CNV, which initiates the conversion, to be independent of the readback timing. This is useful in low jitter sampling or simultaneous sampling applications.
A 14-bit register, CFG[13:0], is used to configure the ADC for the channel to be converted, the reference selection, and other
components, which are detailed in the Configuration Register,
When CNV is low, reading/writing can occur during conversion, acquisition, and spanning conversion (acquisition plus conversion), as detailed in the following sections. The CFG word is updated on the first 14 SCK rising edges, and conversion results are output on the first 15 (or 16 if busy mode is selected) SCK falling edges. If the CFG readback is enabled, an additional
14 SCK falling edges are required to output the CFG word associated with the conversion results with the CFG MSB following the LSB of the conversion result.
A discontinuous SCK is recommended because the part is selected with CNV low, and SCK activity begins to write a new configuration word and clock out data.
Note that in the following sections, the timing diagrams indicate digital activity (SCK, CNV, DIN, SDO) during the conversion.
However, due to the possibility of performance degradation, digital activity should occur only prior to the safe data reading/ writing time, t
DATA
, because the AD7682/AD7689 provide error correction circuitry that can correct for an incorrect bit during this time. From t
DATA
to t
CONV
, there is no error correction and conversion results may be corrupted. The user should configure the AD7682/AD7689 and initiate the busy indicator (if desired) prior to t
DATA
. It is also possible to corrupt the sample by having
SCK or DIN transitions near the sampling instant. Therefore, it is recommended to keep the digital pins quiet for approximately
20 ns before and 10 ns after the rising edge of CNV, using a discontinuous SCK whenever possible to avoid any potential performance degradation.
READING/WRITING DURING CONVERSION, FAST
HOSTS
When reading/writing during conversion (n), conversion results are for the previous (n − 1) conversion, and writing the
CFG register is for the next (n + 1) acquisition and conversion.
After the CNV is brought high to initiate conversion, it must be brought low again to allow reading/writing during conversion.
Reading/writing should only occur up to t
DATA
and, because this time is limited, the host must use a fast SCK.
AD7682/AD7689
The SCK frequency required is calculated by
f
SCK
Number
_
SCK
_
Edges t
DATA
The time between t
DATA
and t
CONV
is a safe time when digital activity should not occur, or sensitive bit decisions may be corrupt.
READING/WRITING AFTER CONVERSION, ANY
SPEED HOSTS
When reading/writing after conversion, or during acquisition
(n), conversion results are for the previous (n − 1) conversion, and writing is for the (n + 1) acquisition.
For the maximum throughput, the only time restriction is that the reading/writing take place during the t
ACQ
(minimum) time.
For slow throughputs, the time restriction is dictated by the throughput required by the user, and the host is free to run at any speed. Thus for slow hosts, data access must take place during the acquisition phase.
READING/WRITING SPANNING CONVERSION, ANY
SPEED HOST
When reading/writing spanning conversion, the data access starts at the current acquisition (n) and spans into the conversion (n).
Conversion results are for the previous (n − 1) conversion, and writing the CFG register is for the next (n + 1) acquisition and conversion.
Similar to reading/writing during conversion, reading/writing should only occur up to t
DATA
. For the maximum throughput, the only time restriction is that reading/writing take place during the t
ACQ
+ t
DATA
time.
For slow throughputs, the time restriction is dictated by the user’s required throughput, and the host is free to run at any speed. Similar to reading/writing during acquisition, for slow hosts, the data access must take place during the acquisition phase with additional time into the conversion.
Note that data access spanning conversion requires the CNV to be driven high to initiate a new conversion, and data access is not allowed when CNV is high. Thus, the host must perform two bursts of data access when using this method.
CONFIGURATION REGISTER, CFG
The AD7682/AD7689 use a 14-bit configuration register
(CFG[13:0]), as detailed in Table 10, to configure the inputs,
the channel to be converted, the one-pole filter bandwidth, the reference, and the channel sequencer. The CFG register is latched (MSB first) on DIN with 14 SCK rising edges. The CFG update is edge dependent, allowing for asynchronous or synchronous hosts.
Rev. A | Page 23 of 32
AD7682/AD7689
The register can be written to during conversion, during acquisition, or spanning acquisition/conversion, and is updated at the end of conversion, t
CONV
(maximum). There is always a one deep delay when writing the CFG register. Note that, at power-up, the
CFG register is undefined and two dummy conversions are required to update the register. To preload the CFG register with a factory setting, hold DIN high for two conversions. Thus
CFG[13:0] = 0x3FFF. This sets the AD7682/AD7689 for the following:
IN[7:0] unipolar referenced to GND, sequenced in order
Full bandwidth for a one-pole filter
Internal reference/temperature sensor disabled, buffer enabled
Enables the internal sequencer
No readback of the CFG register
Table 10 summarizes the configuration register bit details. See
the Theory of Operation section for more details.
13 12 11 10 9 8 7 6 5 4 3 2 1 0
CFG INCC INCC INCC INx INx INx BW REF REF REF SEQ SEQ RB
Table 10. Configuration Register Description
[13] CFG Configuration update.
0 = keep current configuration settings.
1 = overwrite contents of register.
[12:10] INCC Input channel configuration. Selection of pseudo bipolar, pseudo differential, pairs, single-ended, or temperature sensor. Refer
section.
Bit 12
0
0
0
1
1
Bit 11
0
1
1
0
1
0
Function
Bipolar differential pairs; INx− referenced to V
REF
/2 ± 0.1 V.
Bipolar; INx referenced to COM = V
REF
/2 ± 0.1 V.
1 Temperature
Unipolar differential pairs; INx− referenced to GND ± 0.1 V.
0 Unipolar, INx referenced to COM = GND ± 0.1 V.
[9:7] INx
X
Input channel selection in binary fashion.
Bit 9 Bit 8
AD7682 AD7689
Bit 7 Channel Bit 9 Bit 8 Bit 7 Channel
section.
0 = ¼ of BW, uses an additional series resistor to further bandwidth limit the noise. Maximum throughput must also be reduced to ¼.
1 = full BW.
[5:3] REF Reference/buffer selection. Selection of internal, external, external buffered, and enabling of the on-chip temperature sensor.
Voltage Reference Output/Input
section.
Bit 5
0
1
1
0
0
0
Bit 4
1
1
1
0
0
1
Bit 3
1
0
1
0
1
0
Function
Internal reference, REF = 2.5 V output.
Internal reference, REF = 4.096 V output.
External reference, temperature enabled.
External reference, internal buffer, temperature enabled.
External reference, temperature disabled.
External reference, internal buffer, temperature disabled.
section.
Bit 2
0
0
1
1
Bit 1
0
1
0
1
Function
Update configuration during sequence.
Scan IN0 to IN[7:0] (set in CFG[9:7]), then temperature.
Scan IN0 to IN[7:0] (set in CFG[9:7]).
[0] RB Read back the CFG register.
0 = read back current configuration at end of data.
1 = do not read back contents of configuration.
1
X = don’t care.
Rev. A | Page 24 of 32
AD7682/AD7689
GENERAL TIMING WITHOUT A BUSY INDICATOR
Figure 37 details the timing for all three modes: read/write
during conversion (RDC), read/write after conversion (RAC), and read/write spanning conversion (RSC). Note that the gating item for both CFG and data readback is at the end of conversion
(EOC). At EOC, if CNV is high, the busy indicator is disabled.
As detailed previously in the Digital Interface section, the data
access should occur up to safe data reading/writing time, t
DATA
.
If the full CFG word was not written to prior to EOC, it is discarded and the current configuration remains. If the conversion result is not read out fully prior to EOC, it is lost as the ADC updates SDO with the MSB of the current conversion. For
detailed timing, refer to Figure 40 and Figure 41, which depict
reading/writing spanning conversion with all timing details, including setup, hold, and SCK.
PHASE
POWER
UP t
CYC
EOC t
CONV
CONVERSION
(n – 2) UNDEFINED
SOC
ACQUISITION
(n – 1) UNDEFINED t
DATA
CONVERSION
(n – 1) UNDEFINED
EOC
ACQUISITION
(n)
When CNV is brought low after EOC, SDO is driven from high impedance to the MSB. Falling SCK edges clock out bits starting with MSB − 1.
The SCK can idle high or low depending on the clock polarity
(CPOL) and clock phase (CPHA) settings if SPI is used. A simple
solution is to use CPOL = CPHA = 0 as shown in Figure 37 with
SCK idling low.
From power-up, in any read/write mode, the first three conversion results are undefined because a valid CFG does not take place until the 2 nd
EOC; thus two dummy conversions are required. Also, if the state machine writes the CFG during the power-up state (RDC shown), the CFG register needs to be rewritten again at the next phase. Note that the first valid data occurs in Phase (n + 1) when the CFG register is written during
Phase (n − 1).
CONVERSION
(n)
EOC
ACQUISITION
(n + 1)
CONVERSION
(n + 1)
EOC
ACQUISITION
(n + 2)
CNV
DIN
RDC
SDO
SCK
MSB
XXX
XXX
1
DATA (n – 3)
XXX
16
2
CFG (n)
1
DATA (n – 2)
XXX
16
MSB
XXX
CFG (n + 1)
1
DATA (n – 1)
XXX
16
MSB
(n)
CFG (n + 2)
1
DATA (n)
16
MSB
(n + 1)
CNV
DIN
RAC
SDO
SCK
CFG (n)
1
DATA (n – 2)
XXX
16
2
CFG (n + 1)
1
DATA (n – 1)
XXX
16 1
CFG (n + 2)
DATA (n)
16
1
CFG (n + 3)
DATA (n + 1)
CNV
DIN
RSC
SDO
SCK
CFG (n) CFG (n)
1
DATA (n – 2)
XXX n n + 1
DATA (n – 2)
XXX
16
2
CFG (n + 1) CFG (n + 1)
1
DATA (n – 1)
XXX n n + 1
DATA (n – 1)
XXX
16
1
CFG (n + 2)
DATA (n) n n + 1
CFG (n + 2)
DATA (n)
16
1
CFG (n + 3)
DATA (n + 1) n
SEQEUNCER TIMING
READ/WRITE AFTER CONVERT SHOWN
PHASE
CONVERSION
UNDEFINED
ACQUISITION
UNDEFINED
CONVERSION
UNDEFINED
ACQUISITION
(IN0)
CONVERSION
(IN0)
ACQUISITION
(IN1)
CONVERSION
(IN1)
3
ACQUISITION
(IN2)
1
CNV
DIN CFG SEQ
3
SDO
DATA (n – 2)
XXX
DATA (n – 1)
XXX
DATA (IN0)
3
DATA (IN1)
SCK 1
16
1
16 1 16 1
2
NOTES
1. CNV MUST BE HIGH PRIOR TO THE END OF CONVERSION (EOC) TO AVOID THE BUSY INDICATOR.
2. A TOTAL OF 16 SCK FALLING EDGES ARE REQUIRED TO RETURN SDO TO HIGH-Z. IF CFG READBACK IS ENABLED, A TOTAL OF 30 SCK FALLING EDGES IS
REQUIRED TO RETURN SDO TO HIGH-Z.
3. WITH THE SEQUENCER ENABLED, THE NEXT ACQUISITION PHASE WILL BE FOR IN0 AFTER THE LAST CHANNEL SET IN CFG[9:7] IS CONVERTED.
Figure 37. General Interface Timing for the AD7682/AD7689 Without a Busy Indicator
Rev. A | Page 25 of 32
AD7682/AD7689
GENERAL TIMING WITH A BUSY INDICATOR
Figure 38 details the timing for all three modes: read/write
during conversion (RDC), read/write after conversion (RAC), and read/write spanning conversion (RSC). Note that the gating item for both CFG and data readback is at the end of conversion
(EOC). As detailed previously, the data access should occur up to safe data reading/writing time, t
DATA
. If the full CFG word is not written to prior to EOC, it is discarded and the current configuration remains.
At the EOC, if CNV is low, the busy indicator is enabled. In addition, to generate the busy indicator properly, the host must assert a minimum of 17 SCK falling edges to return SDO to high impedance because the last bit on SDO remains active.
Unlike the case detailed in the General Timing Without a Busy
Indicator section, if the conversion result is not read out fully
prior to EOC, the last bit clocked out remains. If this bit is low, the busy signal indicator cannot be generated because the busy generation requires either a high impedance or a remaining bit
PHASE
POWER
UP t
CONV t
CYC
EOC
START OF CONVERSION
(SOC) t
DATA
CONVERSION
(n – 2) UNDEFINED
ACQUISITION
(n – 1) UNDEFINED
CONVERSION
(n – 1) UNDEFINED
EOC
ACQUISITION
(n)
high-to-low transition. A good example of this occurs when an SPI host sends 16 SCKs because these are usually limited to
8-bit or 16-bit bursts; thus the LSB remains. Because the transition noise of the AD7682/AD7689 is 4 LSBs peak to peak (or greater), the LSB is low 50% of the time. For this interface, the
SPI host needs to burst 24 SCKs, or a QSPI interface can be used and programmed for 17 SCKs.
The SCK can idle high or low depending on the CPOL and
CPHA settings if SPI is used. A simple solution is to use CPOL
= CPHA = 1 (not shown) with SCK idling high.
From power-up, in any read/write mode, the first three conversion results are undefined because a valid CFG does not take place until the 2 nd
EOC; thus, two dummy conversions are required. Also, if the state machine writes the CFG during the power-up state (RDC shown), the CFG register needs to be rewritten again at the next phase. Note that the first valid data occurs in Phase (n + 1) when the CFG register is written during
Phase (n − 1).
CONVERSION
(n)
EOC
ACQUISITION
(n + 1)
CONVERSION
(n + 1)
EOC
ACQUISITION
(n + 2)
CNV
DIN
RDC
SDO
SCK
XXX
1
DATA (n – 3)
XXX
17
NOTE 1
CFG (n)
1
DATA (n – 2)
XXX
17
NOTE 2
CFG (n + 1)
1
DATA (n – 1)
XXX
17
CFG (n + 2)
1
DATA (n)
17
CNV
RAC
DIN
SDO
SCK
NOTE 1
CFG (n)
1
DATA (n – 2)
XXX
17
NOTE 2
CFG (n + 1)
1
DATA (n – 1)
XXX
17
CFG (n + 2)
1
DATA (n)
17
CNV NOTE 1
RSC
DIN
SDO
CFG (n)
DATA (n – 2)
XXX
DATA (n – 2)
XXX
CFG (n + 1)
DATA (n – 1)
XXX
DATA (n – 1)
XXX
CFG (n + 2)
DATA (n)
SCK
1 n n + 1 17 1 n n + 1 17 1
NOTE 2
NOTES
1. CNV MUST BE LOW PRIOR TO THE END OF CONVERSION (EOC) TO GENERATE THE BUSY INDICATOR.
2. A TOTAL OF 17 SCK FALLING EDGES ARE REQUIRED TO RETURN SDO TO HIGH-Z. IF CFG READBACK IS ENABLED,
A TOTAL OF 31 SCK FALLING EDGES IS REQUIRED TO RETURN SDO TO HIGH-Z.
n n + 1
Figure 38. General Interface Timing for the AD7682/AD7689 With a Busy Indicator
DATA (n)
17
1
CFG (n + 3)
DATA (n + 1)
1
CFG (n + 3)
DATA (n + 1)
Rev. A | Page 26 of 32
AD7682/AD7689
CHANNEL SEQUENCER
The AD7682/AD7689 include a channel sequencer useful for scanning channels in a repeated fashion. Channels are scanned as singles or pairs, with or without the temperature sensor, after the last channel is sequenced.
Busy Indicator section for more details. The sequencer can also
be used with the busy indicator and details for these timings can
be found in the General Timing with a Busy Indicator section
and the Read/Write Spanning Conversion with a Busy Indicator
section.
The sequencer starts with IN0 and finishes with IN[7:0] set in
CFG[9:7]. For paired channels, the channels are paired depending on the last channel set in CFG[9:7]. Note that in sequencer mode, the channels are always paired with the positive input on the even channels (IN0, IN2, IN4, IN6), and with the negative input on the odd channels (IN1, IN3, IN5, IN7). For example, setting CFG[9:7] = 110 or 111 scans all pairs with the positive inputs dedicated to IN0, IN2, IN4, and IN6.
For sequencer operation, the CFG register should be set during the (n − 1) phase after power-up. On phase (n), the sequencer setting takes place and acquires IN0. The first valid conversion result is available at phase (n + 1). After the last channel set in
CFG[9:7] is converted, the internal temperature sensor data is output (if enabled), followed by acquisition of IN0.
Examples
CFG[2:1] are used to enable the sequencer. After the CFG register is updated, DIN must be held low while reading data out for Bit 13, or the CFG register begins updating again.
With all channels configured for unipolar mode to GND, including the internal temperature sensor, the sequence scans in the following order:
IN0, IN1, IN2, IN3, IN4, IN5, IN6, IN7, TEMP, IN0, IN1, IN2, …
Note that while operating in a sequence, some bits of the CFG register can be changed. However, if changing CFG[11] (paired or single channel) or CFG[9:7] (last channel in sequence), the sequence reinitializes and converts IN0 (or IN0/IN1 pairs) after the CFG register is updated.
For paired channels with the internal temperature sensor enabled, the sequencer scans in the following order:
IN0, IN2, IN4, IN6, TEMP, IN0, …
Figure 39 details the timing for all three modes without a busy
indicator. Refer to the General Timing Without a Busy Indicator
section and the Read/Write Spanning Conversion Without a
PHASE
POWER
UP t
CONV
CONVERSION
(n – 2) UNDEFINED t
CYC
EOC
SOC
ACQUISITION
(n – 1) UNDEFINED t
DATA
CONVERSION
(n – 1) UNDEFINED
EOC
ACQUISITION
(n), IN0
Note that IN1, IN3, IN5, and IN7 are referenced to a GND sense or V
REF
/2, as detailed in the Input Configurations section.
CONVERSION
(n), IN0
EOC
ACQUISITION
(n + 1), IN1
CONVERSION
(n + 1), IN1
EOC
ACQUISITION
(n + 2), IN2
NOTE 1
CNV
DIN
RDC
SDO
SCK
MSB
XXX
XXX
1
DATA (n – 3)
XXX
16
2
CFG (n)
1
DATA (n – 2)
XXX
16
NOTE 2
MSB
XXX
1
DATA (n – 1)
XXX
16
MSB
IN0
1
DATA IN0
16
MSB
IN1
CNV
DIN
RAC
SDO
SCK
CFG (n)
1
DATA (n – 2)
XXX
16
NOTE 2
1
DATA (n – 1)
XXX
16 1
DATA IN0
16
CNV
RSC
DIN
SDO
CFG (n)
DATA (n – 2)
XXX
CFG (n)
DATA (n – 2)
XXX
DATA (n – 1)
XXX
DATA (n – 1)
XXX
SCK 1 n n + 1
16 1 n n + 1
16
NOTE 2
NOTES
1. CNV MUST BE HIGH PRIOR TO THE END OF CONVERSION (EOC) TO AVOID THE BUSY INDICATOR.
2. A TOTAL OF 16 SCK FALLING EDGES ARE REQUIRED TO RETURN SDO TO HIGH-Z. IF CFG READBACK IS ENABLED,
A TOTAL OF 30 SCK FALLING EDGES IS REQUIRED TO RETURN SDO TO HIGH-Z.
1
DATA IN0 n n + 1
DATA IN0
16
Figure 39. General Channel Sequencer Timing Without a Busy Indicator
1
DATA IN1
1
DATA IN1 n
Rev. A | Page 27 of 32
AD7682/AD7689
READ/WRITE SPANNING CONVERSION WITHOUT
A BUSY INDICATOR
This mode is used when the AD7682/AD7689 are connected to any host using an SPI, serial port, or FPGA. The connection
CPOL = 0. Reading/writing spanning conversion is shown,
which covers all three modes detailed in the Digital Interface
section. For this mode, the host must generate the data transfer based on the conversion time. For an interrupt driven transfer
that uses a busy indicator, refer to the Read/Write Spanning
Conversion with a Busy Indicator section.
A rising edge on CNV initiates a conversion, forces SDO to high impedance, and ignores data present on DIN. After a conversion is initiated, it continues until completion irrespective of the state of CNV. CNV must be returned high before the safe data transfer time, t
DATA
, and then held high beyond the conversion time, t
CONV
, to avoid generation of the busy signal indicator.
After the conversion is complete, the AD7682/AD7689 enter the acquisition phase and power-down. When the host brings
AD7682/
AD7689
CNV
SDO
DIN
SCK
CNV low after t
CONV
(maximum), the MSB is enabled on SDO.
The host also must enable the MSB of the CFG register at this time (if necessary) to begin the CFG update. While CNV is low, both a CFG update and a data readback take place. The first 14
SCK rising edges are used to update the CFG, and the first 15
SCK falling edges clock out the conversion results starting with
MSB − 1. The restriction for both configuring and reading is that they both must occur before the t
DATA
time of the next conversion elapses. All 14 bits of CFG[13:0] must be written, or they are ignored. In addition, if the 16-bit conversion result is not read back before t
DATA
elapses, it is lost.
The SDO data is valid on both SCK edges. Although the rising edge can be used to capture the data, a digital host using the
SCK falling edge allows a faster reading rate, provided it has an acceptable hold time. After the 16 th
(or 30 th
) SCK falling edge, or when CNV goes high (whichever occurs first), SDO returns to high impedance.
If CFG readback is enabled, the CFG register associated with the conversion result is read back MSB first following the LSB of the conversion result. A total of 30 SCK falling edges is required to return SDO to high impedance if this is enabled.
DIGITAL HOST
SS
MISO
MOSI
SCK
CNV t
DATA
> t
CONV t
CONV
FOR SPI USE CPHA = 0, CPOL = 0.
Figure 40. Connection Diagram for the AD7682/AD7689 Without a Busy Indicator
t
CYC t
CONV t
DATA
EOC t
CNVH
RETURN CNV HIGH
FOR NO BUSY t
ACQ
EOC
RETURN CNV HIGH
FOR NO BUSY
ACQUISITION
(n - 1) t
CONVERSION (n – 1)
SCKH t
SCK
(QUIET
TIME)
UPDATE (n)
CFG/SDO
ACQUISITION (n)
SCK
DIN t
SCKL
14 15 t
EN
CFG
LSB
X
END CFG (n)
16/
30
X t
CLSCK t
EN
1
2
CFG
MSB t
SDIN
CFG
MSB – 1 t
HDIN
BEGIN CFG (n + 1) t t
HSDO
DSDO
MSB
MSB – 1
SDO
LSB + 1
LSB t
DIS
END DATA (n – 2) t
DIS
BEGIN DATA (n – 1)
NOTES
1. THE LSB IS FOR CONVERSION RESULTS OR THE CONFIGURATION REGISTER CFG (n – 1) IF
15 SCK FALLING EDGES = LSB OF CONVERSION RESULTS.
29 SCK FALLING EDGES = LSB OF CONFIGURATION REGISTER.
ON THE 16TH OR 30TH SCK FALLING EDGE, SDO IS DRIVEN TO HIGH IMPENDANCE.
t
EN t
DIS
CONVERSION (n)
14
CFG
LSB
X
END CFG (n + 1)
X
LSB + 1
LSB
SEE NOTE
END DATA (n – 1) t
DIS
Figure 41. Serial Interface Timing for the AD7682/AD7689 Without a Busy Indicator
15
SEE NOTE
16/
30
(QUIET
TIME)
ACQUISITION
(n + 1)
UPDATE (n + 1)
CFG/SDO
Rev. A | Page 28 of 32
READ/WRITE SPANNING CONVERSION WITH A
BUSY INDICATOR
This mode is used when the AD7682/AD7689 are connected to any host using an SPI, serial port, or FPGA with an interrupt
host should use CPHA = CPOL = 1. Reading/writing spanning conversion is shown, which covers all three modes detailed in
the Digital Interface section.
A rising edge on CNV initiates a conversion, ignores data present on DIN and forces SDO to high impedance. After the conversion is initiated, it continues until completion irrespective of the state of CNV. CNV must be returned low before the safe data transfer time, t
DATA
, and then held low beyond the conversion time, t
CONV
, to generate the busy signal indicator.
When the conversion is complete, SDO transitions from high impedance to low (data ready), and with a pull-up to VIO, SDO can be used to interrupt the host to begin data transfer.
After the conversion is complete, the AD7682/AD7689 enter the acquisition phase and power-down. The host must enable the MSB of the CFG register at this time (if necessary) to begin
VIO
AD7682/
AD7689
SDO t
DATA
CNV
DIN
SCK
AD7682/AD7689
the CFG update. While CNV is low, both a CFG update and a data readback take place. The first 14 SCK rising edges are used to update the CFG register, and the first 16 SCK falling edges clock out the conversion results starting with the MSB. The restriction for both configuring and reading is that they both occur before the t
DATA
time elapses for the next conversion. All 14 bits of
CFG[13:0] must be written or they are ignored. Also, if the 16-bit conversion result is not read back before t
DATA
elapses, it is lost.
The SDO data is valid on both SCK edges. Although the rising edge can be used to capture the data, a digital host using the
SCK falling edge allows a faster reading rate, provided it has an acceptable hold time. After the optional 17 th (or 31 st ) SCK falling edge, SDO returns to high impedance. Note that if the optional SCK falling edge is not used, the busy feature cannot
be detected, as described in the General Timing with a Busy
If CFG readback is enabled, the CFG register associated with the conversion result is read back MSB first following the LSB of the conversion result. A total of 31 SCK falling edges is required to return SDO to high impedance if this is enabled.
DIGITAL HOST
MISO
IRQ
SS
MOSI
SCK
FOR SPI USE CPHA = 1, CPOL = 1.
Figure 42. Connection Diagram for the AD7682/AD7689 with a Busy Indicator
t
CYC t
ACQ t
DATA t
CONV t
CNVH
CNV
CONVERSION
(n – 1) t
SCKH
CONVERSION (n – 1) t
SCK
(QUIET
TIME)
UPDATE (n)
CFG/SDO
ACQUISITION (n)
SCK
DIN
SDO t
SCKL
15
X
16
END CFG (n)
X
LSB
+ 1
END DATA (n – 2)
17/
31
X
LSB t
DIS
1
2
CFG
MSB t
HDIN t
SDIN
CFG
MSB –1
BEIGN CFG (n + 1) t t
HSDO
DSDO
MSB
MSB
– 1
BEGIN DATA (n – 1) t
EN
NOTES:
1. THE LSB IS FOR CONVERSION RESULTS OR THE CONFIGURATION REGISTER CFG (n – 1) IF
16 SCK FALLING EDGES = LSB OF CONVERSION RESULTS.
30 SCK FALLING EDGES = LSB OF CONFIGURATION REGISTER.
ON THE 17TH OR 31st SCK FALLING EDGE, SDO IS DRIVEN TO HIGH IMPENDANCE.
OTHERWISE, THE LSB REMAINS ACTIVE UNTIL THE BUSY INDICATOR IS DRIVEN LOW.
t
EN t
DIS
CONVERSION (n)
15
SEE NOTE
16
17/
31
(QUIET
TIME)
ACQUISITION
(n + 1)
UPDATE (n + 1)
CFG/SDO
X
X
X
END CFG (n + 1)
LSB
+ 1
END DATA (n – 1)
LSB
SEE NOTE t
DIS t
EN
Figure 43. Serial Interface Timing for the AD7682/AD7689 with a Busy Indicator
Rev. A | Page 29 of 32
AD7682/AD7689
APPLICATION HINTS
LAYOUT
The printed circuit board (PCB) that houses the AD7682/AD7689 should be designed so that the analog and digital sections are separated and confined to certain areas of the board. The pinout of the AD7682/AD7689, with all its analog signals on the left side and all its digital signals on the right side, eases this task.
Avoid running digital lines under the device because these couple noise onto the die unless a ground plane under the
AD7682/AD7689 is used as a shield. Fast switching signals, such as CNV or clocks, should not run near analog signal paths. Avoid crossover of digital and analog signals.
At least one ground plane should be used. It can be common or split between the digital and analog sections. In the latter case, the planes should be joined underneath the AD7682/AD7689.
The AD7682/AD7689 voltage reference input REF has a dynamic input impedance and should be decoupled with minimal parasitic inductances. This is done by placing the reference decoupling ceramic capacitor close to, ideally right up against, the REF and GND pins and connecting them with wide, low impedance traces.
Finally, the power supplies VDD and VIO of the AD7682/
AD7689 should be decoupled with ceramic capacitors, typically
100 nF, placed close to the AD7682/AD7689, and connected using short, wide traces to provide low impedance paths and to reduce the effect of glitches on the power supply lines.
EVALUATING AD7682/AD7689 PERFORMANCE
Other recommended layouts for the AD7682/AD7689 are outlined in the documentation of the evaluation board for the
AD7682/AD7689 ( EVAL-AD7682EDZ / EVAL-AD7689EDZ ).
The evaluation board package includes a fully assembled and tested evaluation board, documentation, and software for controlling the board from a PC via the converter and evaluation development data capture board, EVAL-CED1Z .
Rev. A | Page 30 of 32
AD7682/AD7689
OUTLINE DIMENSIONS
4.00
BSC SQ
0.60 MAX
0.60 MAX
PIN 1
INDICATOR
3.75
BSC SQ
0.50
BSC
15
16
EXPOSED
PAD
(BOTTOM VIEW)
20
1
5
11
10 6
PIN 1
INDICATOR
2.65
2.50 SQ
2.35
TOP VIEW
0.50
0.40
0.30
0.25 MIN
1.00
0.85
0.80
12° MAX
SEATING
PLANE
0.80 MAX
0.65 TYP
0.05 MAX
0.02 NOM
COPLANARITY
0.08
0.20 REF
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
0.30
0.23
0.18
COMPLIANT TO JEDEC STANDARDS MO-220-VGGD-1
Figure 44. 20-Lead Lead Frame Chip Scale Package (LFCSP_VQ)
4 mm × 4 mm Body, Very Thin Quad
(CP-20-4)
Dimensions shown in millimeters
ORDERING GUIDE
Model
Integral
Nonlinearity
±2 LSB max
±2 LSB max
±6 LSB max
±6 LSB max
±2 LSB max
±2 LSB max
No Missing
Code
16 bits
16 bits
15 bits
15 bits
16 bits
16 bits
Temperature
Range Package Description
−40°C to +85°C 20-Lead QFN (LFCSP_VQ)
−40°C to +85°C 20-Lead QFN (LFCSP_VQ)
−40°C to +85°C 20-Lead QFN (LFCSP_VQ)
−40°C to +85°C 20-Lead QFN (LFCSP_VQ)
−40°C to +85°C 20-Lead QFN (LFCSP_VQ)
−40°C to +85°C 20-Lead QFN (LFCSP_VQ)
Package
Option
CP-20-4
CP-20-4
CP-20-4
CP-20-4
CP-20-4
CP-20-4
Ordering
Quantity
Tray, 490
Reel, 1,500
Tray, 490
Reel, 1,500
Tray, 490
Reel, 1,500
Converter Evaluation and
Development Board
1 Z = RoHS Compliant Part.
2
This controller board allows a PC to control and communicate with all Analog Devices evaluation boards whose model numbers end in ED.
Rev. A | Page 31 of 32
AD7682/AD7689
NOTES
©2008–2009 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D07353-0-3/09(A)
Rev. A | Page 32 of 32
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