AD9878

AD9878
Mixed-Signal Front End
for Broadband Applications
AD9878
FUNCTIONAL BLOCK DIAGRAM
FEATURES
APPLICATIONS
I
Tx
TxID[5:0]
Q
SINC–1
16
12
DAC
Tx
DDS
Σ -∆
SDIO
Σ-∆ OUTPUT
3
4
CA PORT
CONTROL REGISTERS
MCLK
PLL
IF10[4:0]
10
MUX
OSCIN
IF10 INPUT
ADC
12
ADC
IF12B INPUT
MUX
Σ
IF12[11:0]
Cable set-top boxes
Cable and wireless modems
VIDEO IN
–
CLAMP
LEVEL
MUX
MUX
12
FLAG[2:1]
ADC
IF12A INPUT
03277-001
Low cost 3.3 V CMOS MxFE™ for broadband applications
DOCSIS, EURO-DOCSIS, DVB, DAVIC compliant
232 MHz quadrature digital upconverter
12-bit direct IF DAC (TxDAC+®)
Up to 65 MHz carrier frequency DDS
Programmable sampling clock rates
Analog Tx output level adjust
Dual 12-bit, 29 MSPS direct IF ADCs with video clamp input
10-bit, 29 MSPS sampling ADC
8-bit ∑-∆ auxiliary DAC
Direct interface to AD832x family of PGA cable drivers
Figure 1.
GENERAL DESCRIPTION
The AD9878 is a single-supply, cable modem/set-top box,
mixed-signal front end. The device contains a transmit path
interpolation filter, a complete quadrature digital upconverter,
and a transmit DAC. The receive path contains dual 12-bit
ADCs and a 10-bit ADC. All internally required clocks and an
output system clock are generated by the phase-locked loop
(PLL) from a single crystal oscillator or clock input.
The transmit path interpolation filter provides an upsampling
factor of 16× with an output signal bandwidth up to 4.35 MHz.
Carrier frequencies up to 65 MHz with 26 bits of frequency tuning
resolution can be generated by the direct digital synthesizer
(DDS). The transmit DAC resolution is 12 bits and can run at
sampling rates as high as 232 MSPS. Analog output scaling from
0 dB to 7.5 dB in 0.5 dB steps is available to preserve SNR when
reduced output levels are required.
The 12-bit ADCs provide excellent undersampling performance,
allowing this device to typically deliver better than 10 ENOBs
with IF inputs up to 70 MHz. The 12-bit IF ADCs can sample at
rates up to 29 MHz, allowing them to process wideband signals.
The AD9878 includes a programmable ∑-∆ DAC, which can be
used to control an external component such as a variable gain
amplifier (VGA) or a voltage controlled tuner.
The AD9878 also integrates a CA port that enables a host
processor to interface with the AD832x family of programmable
gain amplifier (PGA) cable drivers or industry equivalent via
the MxFE serial port (SPORT).
The AD9878 is available in a 100-lead, LQFP package. The
AD9878 is specified over the extended industrial (−40°C to
+85°C) temperature range.
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.326.8703
© 2005 Analog Devices, Inc. All rights reserved.
AD9878
TABLE OF CONTENTS
Electrical Characteristics ................................................................. 4
Transmit Timing......................................................................... 21
Absolute Maximum Ratings............................................................ 7
Interpolation Filter..................................................................... 21
Explanation of Test Levels ........................................................... 7
Half-Band Filters (HBFs) .......................................................... 21
Thermal Characteristics .............................................................. 7
Cascade Integrator Comb (CIC) Filter.................................... 21
ESD Caution.................................................................................. 7
Combined Filter Response........................................................ 21
Pin Configuration and Function Descriptions............................. 8
Digital Upconverter ................................................................... 22
Typical Performance Characteristics ........................................... 10
Tx Signal Level Considerations ................................................ 22
Terminology .................................................................................... 13
Tx Throughput and Latency ..................................................... 23
Register Bit Definitions.................................................................. 14
DAC.............................................................................................. 23
Register 0x00—Initialization .................................................... 15
Programming the AD8321/AD8323 or
AD8322/AD8327/AD8238 Cable-Driver Amplifiers............ 23
Register 0x01—Clock Configuration....................................... 15
Register 0x02—Power-Down.................................................... 15
Register 0x03—Flag Control..................................................... 15
Register 0x04—∑-∆ Control Word........................................... 15
Register 0x07—Video Input Configuration............................ 16
Register 0x08—ADC Clock Configuration ............................ 16
Register 0x0C—Die Revision.................................................... 16
Register 0x0D—Tx Frequency Tuning Words LSBs.............. 16
Register 0x0E—DAC Gain Control ......................................... 16
Register 0x0F—Tx Path Configuration ................................... 16
Registers 0x10 Through 0x17—Burst Parameter................... 17
Serial Interface for Register Control ............................................ 18
General Operation of the Serial Interface ............................... 18
Instruction Byte .......................................................................... 18
Serial Interface Port Pin Descriptions ..................................... 18
MSB/LSB Transfers..................................................................... 19
Notes on Serial Port Operation ................................................ 19
Theory of Operation ...................................................................... 20
Transmit Path.............................................................................. 21
OSCIN Clock Multiplier ........................................................... 24
Clock and Oscillator Circuitry ................................................. 24
Programmable Clock Output REFCLK .................................. 24
Power-Up Sequence ................................................................... 26
Reset ............................................................................................. 26
Transmit Power-Down .............................................................. 26
∑-∆ Outputs ................................................................................ 27
Receive Path (Rx) ....................................................................... 27
IF10 and IF12 ADC Operation ................................................ 27
ADC Voltage References ........................................................... 29
Video Input ................................................................................. 29
PCB Design Considerations.......................................................... 30
Component Placement .............................................................. 30
Power Planes and Decoupling .................................................. 30
Ground Planes ............................................................................ 30
Signal Routing............................................................................. 30
Outline Dimensions ....................................................................... 36
Ordering Guide .......................................................................... 36
Data Assembler........................................................................... 21
Rev. A | Page 2 of 36
AD9878
REVISION HISTORY
3/05—Rev. 0 to Rev. A
Changed OSCOUT to REFCLK.................................................. Universal
Changes to Electrical Characteristics ........................................................4
Changes to Pin Configuration and Function Descriptions....................8
Changes to ∑-∆ Output Signals (Figure 32)............................................27
Change to ∑-∆ RC Filter (Figure 33) .......................................................27
Changes to Evaluation PCB Schematic (Figure 38 and Figure 39)......31
Updated Outline Dimensions...................................................................36
Changes to Ordering Guide......................................................................36
5/03—Revision 0: Initial Version
Rev. A | Page 3 of 36
AD9878
ELECTRICAL CHARACTERISTICS
VAS = 3.3 V ± 5%, VDS = 3.3 V ± 10%, fOSCIN = 27 MHz, fSYSCLK = 216 MHz, fMCLK = 54 MHz (M = 8), ADC clock derived from OSCIN,
RSET = 4.02 kΩ, maximum. Fine gain, 75 Ω DAC load.
Table 1.
PARAMETER
OSCIN and XTAL CHARACTERISTICS
Frequency Range
Duty Cycle
Input Impedance
MCLK Cycle-to-Cycle Jitter (fMCLK derived from PLL)
Tx DAC CHARACTERISTICS
Maximum Sample Rate
Resolution
Full-Scale Output Current
Gain Error (Using Internal Reference)
Offset Error
Reference Voltage (REFIO Level)
Differential Nonlinearity (DNL)
Integral Nonlinearity (INL)
Output Capacitance
Phase Noise @ 1 kHz Offset, 42 MHz Carrier
Output Voltage Compliance Range
Wideband SFDR
5 MHz Analog Output, IOUT = 10 mA
65 MHz Analog Output, IOUT = 10 mA
Narrow-Band SFDR (±1 MHz Window)
5 MHz Analog Output, IOUT = 10 mA
65 MHz Analog Output, IOUT = 10 mA
Tx MODULATOR CHARACTERISTICS
I/Q Offset
Pass-Band Amplitude Ripple (f < fIQCLK/8)
Pass-Band Amplitude Ripple (f < fIQCLK/4)
Stop-Band Response (f > fIQCLK × 3/4)
Tx GAIN CONTROL
Gain Step Size
Gain Step Error
Settling Time, 1% (Full-Scale Step)
10-BIT ADC CHARACTERISTICS
Resolution
Maximum Conversion Rate
Pipeline Delay
Analog Input
Input Voltage Range
Differential Input Impedance
Full Power Bandwidth
Dynamic Performance (AIN = −0.5 dBFS, f = 5 MHz)
Signal-to-Noise and Distortion (SINAD)
Effective Number of Bits (ENOB)
Total Harmonic Distortion (THD)
Spurious-Free Dynamic Range (SFDR)
Reference Voltage Error, REFT10 to REFB10 (1.0 V)
Temp
Test Level
Min
Full
25°C
25°C
25°C
II
II
III
III
3
35
Full
N/A
Full
25°C
25°C
25°C
25°C
25°C
25°C
25°C
Full
II
N/A
II
I
I
I
III
III
III
III
II
232
−0.5
Full
Full
II
II
62.4
50.3
68
53.5
dB
dB
Full
Full
II
II
71
61
74
64
dB
dB
Full
Full
Full
Full
II
II
II
II
50
55
25°C
25°C
25°C
III
III
III
N/A
Full
N/A
N/A
II
N/A
Full
25°C
25°C
II
III
III
Full
Full
Full
Full
Full
II
II
II
II
I
Rev. A | Page 4 of 36
4
−2.0
1.18
Typ
50
100||3
6
12
10
−1
±1.0
1.23
±2.5
±8
5
−110
Max
Unit
29
65
MHz
%
MΩ||pF
ps rms
20
+2.0
1.28
+1.5
±0.1
±0.5
−63
65.7
dB
dB
dB
dB
0.5
<0.05
1.8
dB
dB
µs
10
4.5
Bits
MHz
ADC cycles
2
4||2
90
VPPD
kΩ||pF
MHz
59.7
9.6
−71.1
72.4
±4
dB
Bits
dB
dB
mV
29
57.6
9.3
MHz
Bits
mA
% FS
% FS
V
LSB
LSB
pF
dBc/Hz
V
−63.6
±100
AD9878
PARAMETER
Dynamic Performance (AIN = −0.5 dBFS, f = 50 MHz)
Signal-to-Noise and Distortion (SINAD)
Effective Number of Bits (ENOB)
Total Harmonic Distortion (THD)
Spurious-Free Dynamic Range (SFDR)
12-BIT ADC CHARACTERISTICS
Resolution
Maximum Conversion Rate
Pipeline Delay
Analog Input
Input Voltage Range
Differential Input Impedance
Aperture Delay
Aperture Jitter
Full Power Bandwidth
Input Referred Noise
Reference Voltage Error, REFT12 to REFB12 (1 V)
Dynamic Performance (AIN = −0.5 dBFS, f = 5 MHz)
ADC Sample Clock = OSCIN
Signal-to-Noise and Distortion (SINAD)
Effective Number of Bits (ENOBs)
Signal-to-Noise Ratio (SNR)
Total Harmonic Distortion (THD)
Spurious-Free Dynamic Range (SFDR)
ADC Sample Clock = PLL
Signal-to-Noise and Distortion (SINAD)
Effective Number of Bits (ENOB)
Signal-to-Noise Ratio (SNR)
Total Harmonic Distortion (THD)
Spurious-Free Dynamic Range (SFDR)
Dynamic Performance (AIN = −0.5 dBFS, f = 50 MHz)
ADC Sample Clock = OSCIN
Signal-to-Noise and Distortion (SINAD)
Effective Number of Bits (ENOB)
Signal-to-Noise Ratio (SNR)
Total Harmonic Distortion (THD)
Spurious-Free Dynamic Range (SFDR)
Differential Phase
Differential Gain
VIDEO ADC PERFORMANCE (AIN = −0.5 dBFS, f = 5 MHz)
ADC Sample Clock = OSCIN
Signal-to-Noise and Distortion (SINAD)
Signal-to-Noise Ratio (SNR)
Total Harmonic Distortion (THD)
Spurious-Free Dynamic Range (SFDR)
CHANNEL-TO-CHANNEL ISOLATION
Tx DAC-to-ADC Isolation (5 MHz Analog Output)
Isolation Between Tx and 10-Bit ADC
Isolation Between Tx and 12-Bit ADCs
ADC-to-ADC Isolation (AIN = –0.5 dBFS, f = 5 MHz)
Isolation Between IF10 and IF12A/B
Isolation Between IF12A and IF12B
Temp
Test Level
Min
Typ
Full
Full
Full
Full
II
II
II
II
54.8
8.8
57.8
9.3
−63.3
63.7
N/A
Full
N/A
N/A
II
N/A
Full
25°C
25°C
25°C
25°C
25°C
Full
III
III
III
III
III
III
I
Full
Full
Full
Full
Full
II
II
II
II
II
61.0
9.8
64.2
Full
Full
Full
Full
Full
II
II
II
II
II
60.4
9.74
62.4
Full
Full
Full
Full
Full
25°C
25°C
II
II
II
II
II
III
III
61.0
9.8
64.2
Full
Full
Full
Full
II
II
II
II
46.7
54.3
25°C
25°C
III
III
>60
>80
dB
dB
25°C
25°C
III
III
>85
>85
dB
dB
Rev. A | Page 5 of 36
56.9
Max
−56.9
12
62.8
62.7
62.8
45.9
dB
Bits
dB
dB
5.5
Bits
MHz
ADC cycles
2
4||2
2.0
1.2
85
75
±16
VPPD
kΩ||pF
ns
ps rms
MHz
µV
mV
29
−100
Unit
67
10.8
66
−72.7
74.6
64.4
10.4
65.1
−72.7
74.6
65.2
10.5
67.4
−72.8
74.6
<0.1
<1
53
63.2
−50.2
50
+100
−61.7
−61.8
−61.8
−45.9
dB
Bits
dB
dB
dB
dB
Bits
dB
dB
dB
dB
Bits
dB
dB
dB
Degrees
LSB
dB
Bits
dB
dB
AD9878
PARAMETER
TIMING CHARACTERISTICS (10 pF Load)
Wake-Up Time
Minimum RESET Pulse Width Low, tRL
Digital Output Rise/Fall Time
Tx/Rx Interface
MCLK Frequency, fMCLK
TxSYNC/TxIQ Setup Time, tSU
TxSYNC/TxIQ Hold Time, tHU
MCLK Rising Edge to RxSYNC Valid Delay, tMD
REFCLK Rising or Falling Edge to
RxSYNC Valid Delay, tOD
REFCLK Edge to MCLK Falling Edge, tEE
SERIAL CONTROL BUS
Maximum SCLK Frequency, fSCLK
Minimum Clock Pulse Width High, tPWH
Minimum Clock Pulse Width Low, tPWL
Maximum Clock Rise/Fall Time
Minimum Data/Chip-Select Setup Time, tDS
Minimum Data Hold Time, tDH
Maximum Data Valid Time, tDV
CMOS LOGIC INPUTS
Logic 1 Voltage
Logic 0 Voltage
Logic 1 Current
Logic 0 Current
Input Capacitance
CMOS LOGIC OUTPUTS (1 mA Load)
Logic 1 Voltage
Logic 0 Voltage
POWER SUPPLY
Supply Current, IS (Full Operation)
Analog Supply Current, IAS
Digital Supply Current, IDS
Supply Current, IS
Standby (PWRDN Pin Active, IAS + IDS )
Full Power-Down (Register 0x02 = 0xFF)
Power-Down Tx Path (Register 0x02 = 0x60)
Power-Down IF12 Rx Path (Register 0x02 = 0x1B)
Power Supply Rejection (Differential Signal)
Tx DAC
10-Bit ADC
12-Bit ADC
Temp
Test Level
Min
N/A
N/A
Full
N/A
N/A
II
5
2.8
Full
Full
Full
Full
Full
II
II
II
II
II
Full
II
Full
Full
Full
Full
Full
Full
Full
II
II
II
II
II
II
II
25°C
25°C
25°C
25°C
25°C
II
II
II
II
III
VDRVDD − 0.7
25°C
25°C
II
II
VDRVDD − 0.6
25°C
25°C
25°C
II
III
III
25°C
25°C
25°C
25°C
25°C
25°C
25°C
Typ
Max
Unit
200
tMCLK cycles
tMCLK cycles
ns
4
58
3
3
0
tOSCIN/
4 − 2.0
−1.0
1.0
tOSCIN/
4 + 3.0
+1.0
15
30
30
1
25
0
30
0.4
12
12
3
MHz
ns
ns
ns
ns
ns
MHz
ns
ns
µs
ns
ns
ns
V
V
µA
µA
pF
0.4
V
V
184
105
79
204
115
89
mA
mA
mA
II
II
III
III
124
46
124
131
137
52
mA
mA
mA
mA
III
III
III
<0.25
<0.0001
<0.0004
Rev. A | Page 6 of 36
159
% FS
% FS
% FS
AD9878
ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter
Power Supply (VAVDD, VDVDD, VDRVDD)
Digital Output Current
Digital Inputs
Analog Inputs
Operating Temperature
Maximum Junction Temperature
Storage Temperature
Lead Temperature (Soldering, 10 sec)
Rating
3.9 V
5 mA
−0.3 V to VDRVDD + 0.3 V
−0.3 V to VAVDD + 0.3 V
−40°C to +85°C
150°C
−65°C to +150°C
300°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other condition s above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
EXPLANATION OF TEST LEVELS
I. Devices are 100% production tested at 25°C and guaranteed
by design and characterization testing for extended industrial
operating temperature range (−40°C to +85°C).
II. Parameter is guaranteed by design and/or characterization
testing.
III. Parameter is a typical value only.
N/A. Test level definition is not applicable.
THERMAL CHARACTERISTICS
Thermal resistance of 100-lead LQFP: θJA = 40.5°C/W
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. A | Page 7 of 36
AD9878
AVDD
AGND
VIDEO IN
AGND
IF12A+
IF12A–
AGND
AVDD
REFT12A
REFB12A
AVDD
AGND
IF12B+
IF12B–
AGND
AVDD
REFT12B
REFB12B
AVDD
AGND
AVDD10
AGND10
IF10+
IF10–
AGND
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
REFT10
DRVDD 2
74
REFB10
(MSB) IF12(11) 3
73
AGND10
IF12(10) 4
72
AVDD10
IF12(9) 5
71
DRVDD
IF12(8) 6
70
DRGND
IF12(7) 7
69
REFCLK
IF12(6) 8
68
SIGDELT
IF12(5) 9
67
FLAG1
IF12(4) 10
66
FLAG2
IF12(3) 11
65
CA_EN
64
CA_DATA
63
CA_CLK
62
DVDDOSC
(MSB) IF10(4) 15
61
OSCIN
IF10(3) 16
60
XTAL
IF10(2) 17
59
DGNDOSC
IF10(1) 18
58
AGNDPLL
IF10(0) 19
57
PLLFILT
RxSYNC 20
56
AVDDPLL
DRGND 21
55
DVDDPLL
DRVDD 22
54
DGNDPLL
MCLK 23
53
AVDDTx
DVDD 24
52
Tx+
DGND 25
51
Tx–
AD9878
IF12(2) 12
TOP VIEW
(Not to Scale)
IF12(1) 13
41
42
43
44
45
46
47
48
49
50
REFIO
FSADJ
AGNDTx
DVDD
40
PWRDN
TxIQ(0)
39
DVDDTx
TxIQ(1)
38
DGNDTx
TxIQ(2)
37
SDO
TxIQ(3)
36
SDIO
TxIQ(4)
35
CS
TxSYNC
34
SCLK
33
DGND
32
DVDD
31
RESET
30
PROFILE
29
DGND
28
DVDD
27
DGND
26
(MSB) TxIQ(5)
IF12(0) 14
Figure 2. Pin Configuration
Table 3. Pin Function Descriptions
Pin No.
1, 21, 70
2, 22, 71
3
4 to 14
15
16 to 19
20
23
24, 33, 35, 39
25, 34, 36, 40
26
27
28 to 32
37
38
41
42
43
Mnemonic
DRGND
DRVDD
(MSB) IF12(11)
IF12[10:0]
(MSB) IF10(4)
IF10[3:0]
RxSYNC
MCLK
DVDD
DGND
TxSYNC
(MSB) TxIQ(5)
TxIQ[4:0]
PROFILE
RESET
SCLK
CS
SDIO
Descriptions
Pin Driver Digital Ground
Pin Driver Digital 3.3 V Supply
12-Bit ADC Digital Ouput
12-Bit ADC Digital Ouput
10-Bit ADC Digital Ouput
10-Bit ADC Digital Ouput
Sync Output, 10-Bit and 12-Bit ADCs
Master Clock Output
Digital 3.3 V Supply
Digital Ground
Sync Input for Transmit Port
Digital Input for Transmit Port
Digital Input for Transmit Port
Profile Selection Input
Chip Reset Input
SPORT Clock
SPORT Chip Select
SPORT Data I/O
Rev. A | Page 8 of 36
03277-002
DRGND 1
AD9878
Pin No.
44
45
46
47
48
49
50
51, 52
53
54
55
56
57
58
59
60
61
62
63
64
65
66, 67
68
69
72, 80
73, 79
74
75
76, 81, 86, 89, 94,
97, 99
77, 78
82, 85, 90, 93, 100
83
84
87, 88
91
92
95, 96
98
Mnemonic
SDO
DGNDTx
DVDDTx
PWRDN
REFIO
FSADJ
AGNDTx
Tx−, Tx+
AVDDTx
DGNDPLL
DVDDPLL
AVDDPLL
PLLFILT
AGNDPLL
DGNDOSC
XTAL
OSCIN
DVDDOSC
CA_CLK
CA_DATA
CA_EN
FLAG[2:1]
SIGDELT
REFCLK
AVDD10
AGND10
REFB10
REFT10
AGND
Descriptions
SPORT Data Output
Tx Path Digital Ground
Tx Path Digital 3.3 V Supply
Power-Down Transmit Path
TxDAC Decoupling (to AGND)
DAC Output Adjust (External Resistor)
Tx Path Analog Ground
Tx Path Complementary Outputs
Tx Path Analog 3.3 V Supply
PLL Digital Ground
PLL Digital 3.3 V Supply
PLL Analog 3.3 V Supply
PLL Loop Filter Connection
PLL Analog Ground
Oscillator Digital Ground
Crystal Oscillator Inverted Output
Oscillator Clock Input
Oscillator Digital 3.3 V Supply
Serial Clock-to-Cable Driver
Serial Data-to-Cable Driver
Serial Enable-to-Cable Driver
Programmable Flag Outputs
∑-∆ DAC Output
Reference Clock Output
10-Bit ADC Analog 3.3 V Supply
10-Bit ADC Analog Ground
10-Bit ADC Reference Decoupling Node
10-Bit ADC Reference Decoupling Node
12-Bit ADC Analog Ground
IF10−, IF10+
AVDD
REFB12B
REFT12B
IF12B−, IF12B+
REFB12A
REFT12A
IF12A−, IF12A+
VIDEO IN
Differential Input to 10-bit ADC
12-Bit ADC Analog 3.3 V Supply
ADC12B Reference Decoupling Node
ADC12B Reference Decoupling Node
Differential Input to ADC12B
ADC12A Reference Decoupling Node
ADC12A Reference Decoupling Node
Differential Input to ADC12A
Video Clamp Input
Rev. A | Page 9 of 36
AD9878
0
0
–10
–10
–20
–20
–30
–30
MAGNITUDE (dB)
–40
–50
–60
–70
–50
–60
–70
03277-022
–90
–100
0
2
4
6
8
10
12
14
FREQUENCY (MHz)
16
18
–90
–100
55
20
Figure 3. Dual-Sideband Spectral Plot, fC = 5 MHz, f = 1 MHz,
RSET = 10 kΩ (IOUT = 4 mA), RBW = 1 kHz
57
59
61
63
65
67
69
FREQUENCY (MHz)
71
73
75
Figure 6. Dual-Sideband Spectral Plot, fC = 65 MHz, f = 1 MHz,
RSET = 4 kΩ (IOUT = 10 mA), RBW = 1 kHz
0
–10
–10
–20
–20
–30
–30
MAGNITUDE (dB)
0
–40
–50
–60
–70
–80
–40
–50
–60
–70
03277-023
–80
–90
–100
0
2
4
6
8
10
12
14
FREQUENCY (MHz)
16
18
–90
–100
20
0
Figure 4. Dual-Sideband Spectral Plot, fC = 5 MHz, f = 1 MHz,
RSET = 4 kΩ (IOUT = 10 mA), RBW = 1 kHz
20
40
60
80
FREQUENCY (MHz)
100
120
Figure 7. Single Sideband @ 65 MHz, fC = 66 MHz,
f = 1 MHz, RSET = 10 kΩ (IOUT = 4 mA), RBW = 2 kHz
0
–10
–10
–20
–20
–30
–30
MAGNITUDE (dB)
0
–40
–50
–60
–70
–80
–40
–50
–60
–70
–90
–100
55
57
59
61
63
65
67
69
FREQUENCY (MHz)
70
73
03277-027
–80
03277-024
MAGNITUDE (dB)
03277-025
–80
–80
MAGNITUDE (dB)
–40
03277-026
MAGNITUDE (dB)
TYPICAL PERFORMANCE CHARACTERISTICS
–90
–100
75
0
Figure 5. Dual-Sideband Spectral Plot, fC = 65 MHz,
f = 1 MHz, RSET = 10 kΩ (IOUT = 4 mA), RBW = 1 kHz
20
40
60
80
FREQUENCY (MHz)
100
Figure 8. Single Sideband @ 65 MHz, fC = 66 MHz,
f = 1 MHz, RSET = 4 kΩ (IOUT = 10 mA), RBW = 2 kHz
Rev. A | Page 10 of 36
120
AD9878
0
0
–10
–10
–20
–20
MAGNITUDE (dB)
–40
–50
–60
–70
–30
–40
–50
–60
03277-028
–90
–100
0
20
40
60
80
FREQUENCY (MHz)
100
03277-031
–70
–80
–80
–90
0
120
20
0
0
–10
–10
–20
–20
–30
–30
–40
–50
–60
120
–40
–50
–60
03277-029
–80
–90
0
20
40
60
80
FREQUENCY (MHz)
100
03277-032
–70
–70
–80
–90
–2.5
120
–2.0
–1.5
–1.0
–0.5
0
0.5
1.0
FREQUENCY (MHz)
1.5
2.0
2.5
Figure 13. Single Sideband @ 65 MHz, fC = 66 MHz,
f = 1 MHz, RSET = 10 kΩ (IOUT = 4 mA), RBW = 500 Hz
Figure 10. Single Sideband @ 42 MHz, fC = 43 MHz,
f = 1 MHz, RSET = 4 kΩ (IOUT = 10 mA), RBW = 2 kHz
0
0
–10
–10
–20
–20
MAGNITUDE (dB)
–30
–40
–50
–60
–70
–30
–40
–50
–60
–70
–80
03277-030
MAGNITUDE (dB)
100
Figure 12. Single Sideband @ 5 MHz, fC = 6 MHz,
f = 1 MHz, RSET = 4 kΩ (IOUT = 10 mA), RBW = 2 kHz
MAGNITUDE (dB)
MAGNITUDE (dB)
Figure 9. Single Sideband @ 42 MHz, fC = 43 MHz,
f = 1 MHz, RSET = 10 kΩ (IOUT = 4 mA), RBW = 2 kHz
40
60
80
FREQUENCY (MHz)
–90
–100
0
20
40
60
80
FREQUENCY (MHz)
100
03277-033
MAGNITUDE (dB)
–30
–80
–90
–2.5
120
Figure 11. Single Sideband @ 5 MHz, fC = 6 MHz,
f = 1 MHz, RSET = 10 kΩ (IOUT = 4 mA), RBW = 2 kHz
–2.0
–1.5
–1.0
–0.5
0
0.5
1.0
FREQUENCY (MHz)
1.5
2.0
Figure 14. Single Sideband @ 65 MHz, fC = 66 MHz,
f = 1 MHz, RSET = 4 kΩ (IOUT = 10 mA), RBW = 500 Hz
Rev. A | Page 11 of 36
2.5
AD9878
0
0
–10
–10
–20
–20
MAGNITUDE (dB)
MAGNITUDE (dB)
–30
–40
–50
–60
–70
–30
–40
–50
–60
–80
–40
–30
–20
–10
0
10
20
FREQUENCY (MHz)
30
40
03277-036
–100
–50
–70
03277-034
–90
–80
0
50
Figure 15. Single Sideband @ 65 MHz, fC = 66 MHz,
f = 1 MHz, RSET = 10 kΩ (IOUT = 4 mA), RBW = 50 Hz
5
10
15
20
25
30
35
FREQUENCY (MHz)
40
45
50
Figure 17. 16-QAM @ 42 MHz Spectral Plot, RBW = 1 kHz
0
0
–10
–10
–20
–20
MAGNITUDE (dB)
–40
–50
–60
–70
–30
–40
–50
–60
–80
–2.0
–1.5
–1.0
–0.5
0
0.5
1.0
FREQUENCY (MHz)
1.5
2.0
03277-037
–90
–100
–2.5
–70
03277-035
MAGNITUDE (dB)
–30
–80
2.5
0
Figure 16. Single Sideband @ 65 MHz, fC = 66 MHz,
f = 1 MHz, RSET = 10 kΩ (IOUT = 4 mA), RBW = 10 Hz
5
10
15
20
25
30
35
FREQUENCY (MHz)
40
45
Figure 18. 16-QAM @ 5 MHz Spectral Plot, RBW = 1 kHz
Rev. A | Page 12 of 36
50
AD9878
TERMINOLOGY
Differential Nonlinearity Error (DNL, No Missing Codes)
An ideal converter exhibits code transitions that are exactly 1 LSB
apart. DNL is the deviation from this ideal value. No missing
codes indicates that all of the ADC codes must be present over
all operating ranges.
Aperture Delay
The aperture delay is a measure of the sample-and-hold amplifier
(SHA) performance that specifies the time delay between the
rising edge of the sampling clock input and when the input
signal is held for conversion.
Integral Nonlinearity Error (INL)
Linearity error refers to the deviation of each individual code from
a line drawn from negative full scale through positive full scale.
The point used as negative full scale occurs ½ LSB before the first
code transition. Positive full scale is defined as a level 1½ LSB
beyond the last code transition. The deviation is measured from
the middle of each code to the true straight line.
Aperture Jitter
Aperture jitter is the variation in aperture delay for successive
samples and is manifested as noise on the input to the ADC.
Phase Noise
Single-sideband, phase-noise power is specified relative to the
carrier (dBc/Hz) at a given frequency offset (1 kHz) from the
carrier. Phase noise can be measured directly in single-tone
transmit mode with a spectrum analyzer that supports noise
marker measurements. It detects the relative power between
the carrier and the offset (1 kHz) sideband noise and takes
the resolution bandwidth (RBW) into account by subtracting
10 × log(RBW). It also adds a correction factor that compensates
for the implementation of the resolution bandwidth, log display,
and detector characteristic.
Input Referred Noise
The rms output noise is measured using histogram techniques.
The standard deviation of the ADC output codes is calculated
in LSB, and converted to an equivalent voltage. This results in a
noise figure that can be directly referred to the input of the MxFE.
Signal-to-Noise and Distortion (SINAD) Ratio
SINAD is the ratio of the rms value of the measured input signal
to the rms sum of other spectral components below the Nyquist
frequency, including harmonics, but excluding dc. The value for
SINAD is expressed in decibels.
Effective Number of Bits (ENOB)
For a sine wave, SINAD can be expressed in terms of the number
of bits. Using the following formula, it is possible to get a measure
of performance expressed as N, the effective number of bits:
N = (SINAD − 1.76 ) dB 6.02
Output Compliance Range
The range of allowable voltage at the output of a current-output
DAC. Operation beyond the maximum compliance limits can
cause either output stage saturation or breakdown, resulting in
nonlinear performance.
Thus, the effective number of bits for a device for sine wave
inputs at a given input frequency can be calculated directly
from its measured SINAD.
Spurious-Free Dynamic Range (SFDR)
The difference, in dB, between the rms amplitude of the DAC
output signal (or ADC input signal) and the peak spurious signal
over the specified bandwidth (Nyquist bandwidth, unless
otherwise noted).
Signal-to-Noise Ratio (SNR)
SNR is the ratio of the rms value of the measured input signal
to the rms sum of other spectral components below the Nyquist
frequency, excluding harmonics and dc. The value for SNR is
expressed in decibels.
Pipeline Delay (Latency)
The number of clock cycles between conversion initiation and
the associated output data being made available.
Total Harmonic Distortion (THD)
THD is the ratio of the rms sum of the first six harmonic
components to the rms value of the measured input signal.
It is expressed as a percentage, or in decibels.
Offset Error
The first code transition should occur at an analog value ½ LSB
above negative full scale. Offset error is defined as the deviation
of the actual transition from that point.
Gain Error
The first code transition should occur at an analog value ½ LSB
above negative full scale. The last transition should occur for an
analog value 1½ LSB below the nominal full scale. Gain error
is the deviation of the actual difference between first and last
code transitions and the ideal difference between first and last
code transitions.
Power Supply Rejection
Power supply rejection specifies the converter’s maximum fullscale change when the supplies are varied from nominal to
minimum or maximum specified voltages.
Channel-to-Channel Isolation (Crosstalk)
In an ideal multichannel system, the signal in one channel does
not influence the signal level of another channel. The channelto-channel isolation specification is a measure of the change
that occurs in a grounded channel as a full-scale signal is
applied to another channel.
Rev. A | Page 13 of 36
AD9878
REGISTER BIT DEFINITIONS
Table 4. Register Map
Address
(Hex)
0x00
0x01
0x02
Bit 7
SDIO
bidirectional
PLL lock
detect
Power down
PLL
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0x0A
0x0B
0x0C
0x0D
0x0E
0x0F
0x10
0x11
0x12
0x13
0x14
0x15
0x16
0x17
Bit 6
LSB
first
Bit 5
Reset
Bit 3
Bit 2
Bit 1
OSCIN multiplier M[4:0]
Bit 0
MCLK divider R[5:0]
Power
down
DAC
Tx
Power
down
digital
Tx
Video
input
into
ADC12B
MSB/Flag 0
Video input
enable
ADC clocked
directly from
OSCIN
Bit 4
Power
down
ADC12A
Power down
ADC12B
Power
down
ADC10
Flag 2
Power
down
reference
ADC12A
Flag 1
Power
down
reference
ADC12B
Flag 0
enable
∑-∆ output control word [7:0]
Clamp level for video input [6:0]
Rx port
fast
edge
rate
Power
down
RxSYNC
generator
Power down
reference
ADC10
Send
ADC12A
data only
Send
ADC12B
data only
Version [3:0]
Tx frequency tuning word
Tx frequency tuning
profile 1 LSB [1:0]
word profile 0 LSBs [1:0]
DAC fine gain control [3:0]
Tx path
Tx path
Tx path
Tx path
Tx
spectral
transmit
select
AD8321/AD8323 path
single
Profile 1
bypass inversion
gain control
tone
sinc–1
mode
filter
Tx Path Frequency Tuning Word Profile 0 [9:2]
Tx Path Frequency Tuning Word Profile 0 [17:10]
Tx Path Frequency Tuning Word Profile 0 [25:18]
Cable-driver amplifier,
Cable-driver amplifier,
Fine Gain Control Profile 0 [3:0]
Coarse Gain Control Profile 0 [7:4]
Tx Path Frequency Tuning Word Profile 1 [9:2]
Tx Path Frequency Tuning Word Profile 1 [17:10]
Tx Path Frequency Tuning Word Profile 1 [25:18]
Cable-driver amplifier,
Cable-driver amplifier,
Fine Gain Control Profile 1 [3:0]
Coarse Gain Control Profile 1 [7:4]
Rev. A | Page 14 of 36
Default
(Hex)
0x08
Type
Read/write
0x00
Read/write
0x00
Read/write
0x00
Read/write
0x00
0x00
0x00
0x00
Read/write
Read/write
Read only
Read/write
0x80
Read/write
0x00
0x00
0x00
0x00
0x00
Read/write
Read/write
Read/write
Read/write
Read/write
0x00
0x00
Read/write
Read/write
0x00
0x00
0x00
0x00
Read/write
Read/write
Read/write
Read/write
0x00
0x00
0x00
0x00
Read/write
Read/write
Read/write
Read/write
AD9878
REGISTER 0x00—INITIALIZATION
Bit 1: Power Down ADC12A Voltage Reference
Bits 0 to 4: OSCIN Multiplier
Active high powers down the voltage reference circuit for
the ADC12A.
This register field is used to program the on-chip clock
multiplier that generates the chip’s high frequency system clock,
fSYSCLK. For example, to multiply the external crystal clock fOSCIN
by 16, program Register 0x00, Bits 4:0, to 0x10. The default
clock multiplier value, M, is 0x08. Valid entries range from 1 to
31. When M is set to 1, the PLL is disabled and internal clocks
are derived directly from OSCIN. The PLL requires 200 MCLK
cycles to regain frequency lock after a change in M. After the
recapture time of the PLL, the frequency of fSYSCLK is stable.
Bit 2: Power Down ADC10
Active high powers down the 10-bit ADC.
Bit 3: Power Down ADC12B
Active high powers down the ADC12B.
Bit 4: Power Down ADC12A
Active high powers down the ADC12A.
Bit 5: Power Down Tx
Bit 5: Reset
Writing 1 to this bit resets the registers to their default values
and restarts the chip. The reset bit always reads back 0. The bits
in Register 0x00 are not affected by this software reset. However,
a low level at the RESET pin forces all registers, including all
bits in Register 0x00, to their default states.
Active high powers down the digital transmit section of the
chip, similar to the function of the PWRDN pin.
Bit 6: Power Down DAC Tx
Active high powers down the DAC.
Bit 7: Power Down PLL
Bit 6: LSB First
Active high powers down the OSCIN multiplier.
Active high indicates SPI serial port access of instruction byte and
data registers is LSB first. Default low indicates MSB-first format.
REGISTER 0x03—FLAG CONTROL
Bit 7: SDIO Bidirectional
Active high configures the serial port as a 3-signal port with
the SDIO pin used as a bidirectional input/output pin. Default
low indicates that the serial port uses four signals with SDIO
configured as an input and SDO configured as an output.
Bit 0: Flag 0 Enable
When this bit is active high, the SIGDELT pin maintains a fixed
logic level determined directly by the MSB of the ∑-∆ control
word of Register 0x04.
Bit 1: Flag 1
The logic level of this bit is applied at the FLAG1 pin.
REGISTER 0x01—CLOCK CONFIGURATION
Bits [5:0]: MCLK Divider
Bit 4: Flag 2
This register determines the output clock on the REFCLK pin.
At default 0 (R = 0), REFCLK provides a buffered version of the
OSCIN clock signal for other chips. The register can also be used
to divide the chip’s master clock fMCLK by R, where R is an integer
between 2 and 63. The generated reference clock on REFCLK pin
can be used for external frequency controlled devices.
The logic level of this bit is applied at the FLAG2 pin.
Bit 5: Video Input into ADC12B
If the video input is enabled, setting this bit high sends the
signal applied to the VIDEO IN pin to the ADC12B. Otherwise,
the signal applied to the VIDEO IN pin is sent to the ADC12A.
REGISTER 0x04—∑-∆ CONTROL WORD
Bit 7: PLL Lock Detect
When this bit is set low, the REFCLK pin functions in its
default mode and provides an output clock with frequency
fMCKL/R, as described above. If this bit is set to 1, the REFCLK pin
is configured to indicate whether the PLL is locked to fOSCIN. In
this mode, the REFCLK pin should be low-pass filtered with an
RC filter of 1.0 kΩ and 0.1 µF. A low output on REFCLK indicates
that the PLL has achieved lock with fOSCIN.
Bits [7:0]: ∑-∆ Control Word
The ∑-∆ control word is 8 bits wide and controls the duty cycle
of the digital output on the SIGDELT pin. Changes to the ∑-∆
control word take effect immediately for every register write.
∑-∆ output control words have a default value of 0. The control
words are in straight binary format, with 0x00 corresponding to
the bottom of scale or 0% duty cycle, and 0xFF corresponding
to the top of scale or near 100% duty cycle.
REGISTER 0x02—POWER-DOWN
Bit 7: Flag 0 (∑-∆ Control Word MSB)
Unused sections of the chip can be powered down when the
corresponding bits are set high. This register has a default value
of 0x00, all sections active.
When the Flag 0 enable bit (Register 0x03, Bit 0) is set, the logic
level of this bit appears on the output of the SIGDELT pin.
Bit 0: Power Down ADC12B Voltage Reference
Active high powers down the voltage reference circuit
for ADC12B.
Rev. A | Page 15 of 36
AD9878
REGISTER 0x07—VIDEO INPUT CONFIGURATION
REGISTER 0x0C—DIE REVISION
Bits [6:0]: Clamp Level Control Value
Bits [3:0]: Version
The 7-bit clamp-level control value is used to set an offset to the
automatic clamp-level control loop. The actual ADC output has a
clamp-level offset equal to 16 times the clamp level control value.
The die version of the chip can be read from this register.
Clamp - Level Offset Clamp - Level Control Value = ( x ) 16
The default value for the clamp-level control value is 0x20. This
results in an ADC output clamp-level offset of 512 LSBs. The
valid programming range for the clamp-level control value is
0x16 to 0x127.
Bit 7: Video Input Enable
This bit enables the video input. In default with Bit 7 = 0, both
IF12 ADCs are connected to IF inputs. If the video input is
enabled by setting bit 7 = 1, the video input will be connected to
the IF12 ADC selected by REG 0x03, Bit 6.
REGISTER 0x08—ADC CLOCK CONFIGURATION
Bit 0: Send ADC12B Data Only
When this bit is set high, the device enters a nonmultiplexed
mode, and only the data from the ADC12B is sent to the
IF[11:0] digital output port.
Bit 1: Send ADC12A Data Only
When this bit is set high, the device enters a nonmultiplexed
mode, and only the data from the ADC12A is sent to the
IF[11:0] digital output port.
If both the send ADC12B data only and send ADC12A data
only register bits are set high, the device sends both ADC12A
and ADC12B data in the default multiplexed mode.
Bit 3: Power Down ADC10 Voltage Reference
Active high powers down the voltage reference circuit for
the ADC10.
REGISTER 0x0D—Tx FREQUENCY TUNING WORDS
LSBs
This register accommodates the 2 LSBs for each frequency tuning
word (FTW). See the Registers 0x10 Through 0x17—
Burst Parameter section.
REGISTER 0x0E—DAC GAIN CONTROL
This register allows the user to program the DAC gain if the
Tx Gain Control Select Bit 3 in Register 0x0F is set to 0.
Table 5. DAC Gain Control
Bits [3:0]
0000
0001
0010
0011
…
1110
1111
DAC Gain (dB)
0.0 (default)
0.5
1.0
1.5
…
7.0
7.5
REGISTER 0x0F—Tx PATH CONFIGURATION
Bit 0: Single Tone Tx Mode
Active high configures the AD9878 for single-tone applications
(e.g., FSK). The AD9878 supplies a single frequency output, as
determined by the FTW selected by the active profile. In this
mode, the TxIQ input data pins are ignored, but should be tied
to a valid logic voltage level. Default value is 0x00 (inactive).
Bit 1: Spectral Inversion Tx
When set to 1, inverted modulation is performed:
Bit 4: Power Down RxSYNC Generator
[
]
MODULATOR _ OUT = I cos (ωt ) + Q sin (ωt ) .
Setting this bit to 1 powers down the 10-bit ADC’s sampling
clock and makes the RxSYNC output pin stay low. It can be
used for additional power saving on top of the power-down
selections in Register 0x02.
Default is Logic 0, noninverted modulation:
[
]
MODULATOR _ OUT = I cos (ωt ) − Q sin (ωt ) .
Bit 5: Rx PORT Fast Edge Rate
Setting this bit to 1 increases the output drive strength of all digital
output pins, except MCLK, REFCLK, SIGDELT, and
FLAG[2:1]. These pins always have high output drive capability.
Bit 2: Bypass Inv Sinc Tx Filter
Active high configures the AD9878 to bypass the sin(x)/x compensation filter. Default value is 0x00 (inverse sinc filter enabled).
Bit 7: ADC Clocked Directly from OSCIN
Bit 3: CA Interface Mode Select
When set high, the ADC sampling clock is derived directly from
the input clock at OSCIN. In this mode, the clock supplied to the
OSCIN pin should originate from an external crystal or low jitter
crystal oscillator. When this bit is low, the ADC sampling clock
is derived from the internal PLL and the frequency of the clock
is equal to fOSCIN × M/8.
This bit changes the format of the AD9878 3-wire CA interface to
a format in which the AD9878 digitally interfaces to external
variable gain amplifiers. This is accomplished by changing
the interpretation of the bits in Register 0x13, Register 0x17,
Register 0x1B, and Register 0x1F. See the Cable-Driver Gain
Control section for more detail.
Rev. A | Page 16 of 36
AD9878
Setting this bit to 0 (default) configures the serial interface to be
compatible with AD8321/AD8323/AD8328 variable cable gain
amplifiers. Setting this bit to 1 configures the serial interface to be
compatible with AD8322/AD8327 variable cable gain amplifiers.
Bit 5: Profile Select
The AD9878 quadrature digital upconverter can store two
preconfigured modulation modes, called profiles. Each profile
defines a transmit FTW, cable-driver amplifier gain setting, and
DAC gain setting. The profile select bit or PROFILE pin programs
the current register profile to be used. If the PROFILE pin is used
to switch between profiles, the profile select bit should be set to 0
and tied low.
Table 6. Cable-Driver Gain Control
Bits [7:4]
0000
0001
0010
0011
0100
0101
0110
0111
1000
CA Interface Transmit Word
0000 0000 (default)
0000 0001
0000 0010
0000 0100
0000 1000
0001 0000
0010 0000
0100 0000
1000 0000
Table 7. DAC Output Fine Gain Setting
REGISTERS 0x10 THROUGH 0x17—
BURST PARAMETER
Tx Frequency Tuning Words
The FTW determines the DDS-generated carrier frequency (fC)
and is formed via a concatenation of register addresses.
The 26-bit FTW is spread over four register addresses. Bit 25 is
the MSB, and Bit 0 is the LSB. The carrier frequency equation is
as follows:
f C = (FTW × f SYSCLK ) 2 26
Bits [3:0]
0000
0001
0010
0011
…
1110
1111
DAC Fine Gain (dB)
0.0 (default)
0.5
1.0
1.5
…
7.0
7.5
New data is automatically sent over the 3-wire CA interface
(and DAC gain adjust) whenever the value of the active gain
control register changes or a new profile is selected. The default
value is 0x00 (lowest gain).
Where f SYSCLK = M × f OSCIN , and FTW < 0 x2000 .
Changes to FTW bytes take effect immediately.
Cable-Driver Gain Control
The AD9878 has a 3-pin interface to the AD832x family of
programmable gain cable-driver amplifiers. This allows direct
control of the cable driver’s gain through the AD9878. In its
default mode, the complete 8-bit register value is transmitted
over the 3-wire cable amplifier (CA) interface.
If Bit 3 of Register 0x0F is set high, Bits [7:4] of Register 0x13
and Register 0x17 determine the 8-bit word sent over the CA
interface, according to the specifications in Table 6. Bits [3:0] of
Register 0x13 and Register 0x17 determine the fine gain setting
of the DAC output, according to specifications in Table 7.
The formula for the combined output-level calculation of
AD9878 fine gain and AD8327 or AD8322 coarse gain is:
V8327 = V9878 ( 0 ) + ( fine ) 2 + (coarse ) − 19
V8322 = V9878 ( 0 ) + ( fine ) 2 + (coarse ) − 14
where:
fine is the decimal value of Bits [3:0].
coarse is the decimal value of Bits [7:4].
V9878(0) is the level at AD9878 output in dBmV for fine = 0.
V8327 is the level at output of AD8327 in dBmV.
V8322 is the level at output of AD8322 in dBmV.
Rev. A | Page 17 of 36
AD9878
SERIAL INTERFACE FOR REGISTER CONTROL
There are two phases of a communication cycle with the AD9878.
Phase 1 is the instruction cycle, which is the writing of an instruction byte into the AD9878, coincident with the first eight
SCLK rising edges. The instruction byte provides the AD9878
serial port controller with information regarding the data transfer
cycle, which is Phase 2 of the communication cycle.
The Phase 1 instruction byte defines whether the upcoming data
transfer is a read or write, the number of bytes in the data transfer,
and the starting register address for the first byte of the data
transfer. The first eight SCLK rising edges of each communication
cycle are used to write the instruction byte into the AD9878.
N1
0
0
1
1
N0
0
1
0
1
Description
Transfer 1 byte
Transfer 2 bytes
Transfer 3 bytes
Transfer 4 bytes
Bits [A4:A0] determine which register is accessed during the
data transfer portion of the communication cycle. For multibyte transfers, this address is the starting byte address. The
remaining register addresses are generated by the AD9878.
tDS
tSCLK
CS
tPWH
tPWL
SCLK
tDS
SDIO
tDH
INSTRUCTION BIT 7
INSTRUCTION BIT 6
Figure 19. Timing Diagram for Register Write
CS
SCLK
tDV
The eight remaining SCLK edges are for Phase 2 of the communication cycle. Phase 2 is the actual data transfer between the
AD9878 and the system controller. Phase 2 of the communication
cycle is a transfer of one to four data bytes, as determined by the
instruction byte. Normally, using one multibyte transfer is the
preferred method. However, single-byte data transfers are useful
to reduce CPU overhead when register access requires only one
byte. Registers change immediately upon writing to the last bit
of each transfer byte.
INSTRUCTION BYTE
The R/W bit of the instruction byte determines whether a read
or a write data transfer occurs after the instruction byte write.
Logic high indicates a read operation; logic low indicates a write
operation. The [N1:N0] bits determine the number of bytes to
be transferred during the data transfer cycle. The bit decodes
are shown in Table 9. The timing diagrams are shown in Figure 19
and Figure 20.
Table 8. Instruction Byte Information
MSB 17
R/W
16
N1
15
N0
14
A4
13
A3
12
A2
11
A1
LSB 10
A0
03277-005
GENERAL OPERATION OF THE SERIAL INTERFACE
Table 9. Bit Decodes
SDIO
SDO
DATA BIT N
DATA BIT N
03277-006
The AD9878 serial port is a flexible, synchronous, serial
communications port that allows easy interface to many
industry-standard microcontrollers and microprocessors.
The interface allows read/write access to all registers that
configure the AD9878. Single or multiple byte transfers are
supported. Also, the interface can be programmed to read words
either MSB first or LSB first. The AD9878 serial interface port
I/O can be configured to have one bidirectional I/O (SDIO)
pin, or two unidirectional I/O (SDIO/SDO) pins.
Figure 20. Timing Diagram for Register Read
SERIAL INTERFACE PORT PIN DESCRIPTIONS
SCLK—Serial Clock. The serial clock pin is used to synchronize
data transfers from the AD9878 and to run the serial port state
machine. The maximum SCLK frequency is 15 MHz. Input data
to the AD9878 is sampled up on the rising edge of SCLK. Output
data changes upon the falling edge of SCLK.
CS—Chip Select. Active low input starts and gates a communication cycle. It allows multiple devices to share a common
serial port bus. The SDO and SDIO pins go into a high impedance
state when CS is high. Chip select should stay low during the
entire communication cycle.
SDIO—Serial Data I/O. Data is always written into the AD9878
on this pin. However, this pin can be used as a bidirectional
data line. The configuration of this pin is controlled by Bit 7 of
Register 0x00. The default is Logic 0, which configures the SDIO
pin as unidirectional.
SDO—Serial Data Out. Data is read from this pin for protocols
that use separate lines for transmitting and receiving data. In
the case where the AD9878 operates in a single bidirectional
I/O mode, this pin does not output data and is set to a high
impedance state.
Rev. A | Page 18 of 36
AD9878
MSB/LSB TRANSFERS
NOTES ON SERIAL PORT OPERATION
The AD9878 serial port can support either MSB-first or LSB-first
data formats. This functionality is controlled by the LSB-first bit
in Register 0x00.
The AD9878 serial port configuration bits reside in Bit 6 and
Bit 7 of Register Address 0x00. Note that the configuration
changes immediately upon writing to the last bit of the register.
For multibyte transfers, writing to this register might occur
during a communication cycle. Measures must be taken to
compensate for this new configuration for the remaining bytes of
the current communication cycle.
The AD9878 default serial port mode is MSB-first (see Figure 21),
which is programmed by setting Register 0x00 low. In MSB-first
mode, the instruction byte and data bytes must be written from
the MSB to the LSB. In MSB-first mode, the serial port internal
byte address generator decrements for each byte of the multibyte
communication cycle. When decrementing from 0x00, the
address generator changes to 0x1F.
When the LSB-first bit in Register 0x00 is set active high, the
AD9878 serial port is in LSB-first format (Figure 22). In LSBfirst mode, the instruction byte and data bytes must be written
from the LSB to the MSB. In LSB-first mode, the serial port
internal byte address generator increments for each byte of the
multibyte communication cycle. When incrementing from
0x1F, the address generator changes to 0x00.
INSTRUCTION CYCLE
CS
The same considerations apply when setting the reset bit in
Register Address 0x00. All other registers are set to their default
values, but the software reset does not affect the bits in Register
Address 0x00. It is recommended to use only single-byte transfers
when changing serial port configurations or initiating a software
reset. A write to Bit 1, Bit 2, and Bit 3 of Address 0x00 with the
same logic levels as Bit 7, Bit 6, and Bit 5 (bit pattern: XY1001YX
binary) allows the user to reprogram a lost serial port configuration and to reset the registers to their default values. A
second write to Address 0x00, with the reset bit low and the
serial port configuration as specified above (XY), reprograms
the OSCIN multiplier setting. A changed fSYSCLK frequency is
stable after a maximum of 200 fMCLK cycles (wake-up time).
DATA TRANSFER CYCLE
SDIO
R/W N1
N0
A4
A3
A2
A1
SDO
A0 D7n D6n
D20 D10 D00
D7n D6n
D20 D10 D00
03277-003
SCLK
Figure 21. Serial Register Interface Timing, MSB-First Mode
INSTRUCTION CYCLE
CS
DATA TRANSFER CYCLE
SDIO
SDO
A0
A1
A2
A3
A4
N0
N1 R/W D00 D10 D20
D6n D7n
D00 D10 D20
D6n D7n
03277-004
SCLK
Figure 22. Serial Register Interface Timing, LSB-First Mode
Rev. A | Page 19 of 36
AD9878
THEORY OF OPERATION
For a general understanding of the AD9878, refer to Figure 23, a
block diagram of the device architecture. The device consists of a
transmit path, receive path, and auxiliary functions, such as a PLL,
a ∑-∆ DAC, a serial control port, and a cable amplifier interface.
The 12-bit and 10-bit IF ADCs can convert direct IF inputs of
up to 70 MHz and run at sample rates of up to 29 MSPS. A video
input with an adjustable signal clamping level, along with the
10-bit ADC, allow the AD9878 to process an NTSC and a QAM
channel simultaneously.
The transmit path contains an interpolation filter, a complete
quadrature digital upconverter, an inverse sinc filter, and a 12-bit
current output DAC.
The programmable ∑-∆ DAC can be used to control external
components, such as variable gain amplifiers (VGAs) or voltagecontrolled tuners. The CA port provides an interface to the
AD832x family of programmable gain amplifier (PGA) cable
drivers, enabling host processor control via the MxFE serial
port (SPORT).
The receive path contains a 10-bit ADC and dual 12-bit ADCs.
All internally required clocks and an output system clock are
generated by the PLL from a single crystal or clock input.
QUADRATURE
MODULATOR
DATA
ASSEMBLER
6
I
TxIQ[5:0]
12
4
DAC GAIN CONTROL
CIC LPF
FIR LPF
COS
12
FSADJ
SINC–1
BYPASS
4
MUX
12
Tx OUTPUT
DAC
SINC–1
TxSYNC
Q
12
4
12
4
(fSYSCLK)
SIN
(fOSCIN)
DDS
(fIQCLK)
÷4
PLL
OSCIN × M
÷4
XTAL
MCLK
3
Σ-∆ INPUT
CA
INTERFACE
4
8
Σ-∆
FLAG[2:1]
10
IF10 INPUT
ADC
IF10[4:0]
RxSYNC
5
IF10
MUX
÷2
Rx PORT
(fOSCIN)
IF12[11:0]
12
Σ-∆ OUTPUT
÷2
SERIAL
INTERFACE
(fOSCIN)
5
OSCIN
÷8
PROFILE
SELECT
PROFILE
SDIO
FLAG0
12
IF12
12
ADC
MUX
IF12B INPUT
VIDEO IN
MUX
12
–
AD9878
MUX
IF12A INPUT
+
CLAMP LEVEL
Figure 23. AD9878 Block Diagram
Rev. A | Page 20 of 36
ADC
DAC
03277-007
CA PORT
(fMCLK)
÷R
REFCLK
AD9878
tSU
MCLK
tHU
TxIQ
TxI[11:6]
TxI[5:0]
TxQ[11:6]
TxQ[5:0]
TxI[11:6]
TxI[5:0]
TxQ[11:6]
TxQ[5:0]
TxI[11:6]
TxI[5:0]
03277-008
TxSYNC
Figure 24. Tx Timing Diagram
TRANSMIT PATH
The transmit path contains an interpolation filter, a complete
quadrature digital upconverter, an inverse sinc filter, and a 12-bit
current output DAC. The maximum output current of the DAC is
set by an external resistor. The Tx output PGA provides additional
transmit signal level control. The transmit path interpolation
filter provides an upsampling factor of 16 with an output signal
bandwidth as high as 4.35 MHz for <1 dB droop. Carrier
frequencies up to 65 MHz with 26 bits of frequency tuning
resolution can be generated by the direct digital synthesizer
(DDS). The transmit DAC resolution is 12 bits, and it can run at
sampling rates of up to 232 MSPS. Analog output scaling from
0 dB to 7.5 dB in 0.5 dB steps is available to preserve SNR when
reduced output levels are required.
to the sample rate increase, the half-band filters provide the
low-pass filtering characteristics necessary to suppress the spectral
images between the original sampling frequency and the new
(16× higher) sampling frequency.
HALF-BAND FILTERS (HBFs)
HBF 1 and HBF 2 are both interpolating filters, each of which
doubles the sampling rate. Together, HBF 1 and HBF 2 have
26 taps and increase the sampling rate by a factor of 4
(4 × fIQCLK or 8 × fNYQ).
In relation to phase response, both HBFs are linear phase filters.
As such, virtually no phase distortion is introduced within the pass
band of the filters. This is an important feature, because phase distortion is generally intolerable in a data transmission system.
DATA ASSEMBLER
CASCADE INTEGRATOR COMB (CIC) FILTER
The AD9878 data path operates on two 12-bit words, the I and Q
components, that form a complex symbol. The data assembler
builds the 24-bit complex symbol from four consecutive 6-bit
words read over the TxIQ [5:0] bus. These words are strobed
into the data assembler synchronous to the master clock (MCLK).
A high level on TxSYNC signals the start of a transmit symbol.
The first two 6-bit words of the symbol form the I component;
the second two 6-bit words form the Q component. Symbol
components are assumed to be in twos complement format. The
timing of the interface is fully described in the Transmit Timing
section. The I/Q sample rate fIQCLK puts a bandwidth limit on the
maximum transmit spectrum. This is the familiar Nyquist limit
(hereafter referred to as fNYQ) and is equal to half fIQCLK.
The CIC filter is configured as a programmable interpolator
and provides a sample rate increase by a factor of 4. The
frequency response of the CIC filter is given by:
TRANSMIT TIMING
The AD9878 has a master clock and expects 6-bit, multiplexed
TxIQ data upon each rising edge (see Figure 24). Transmit
symbols are framed with the TxSYNC input. TxSYNC high
indicates the start of a transmit symbol. Four consecutive 6-bit
data packages form a symbol (I MSB, I LSB, Q MSB, and Q LSB).
INTERPOLATION FILTER
Once through the data assembler, the IQ data streams are fed
through a 4× FIR low-pass filter and a 4× cascaded integrator
comb (CIC) low-pass filter. The combination of these two filters
results in the sample rate increasing by a factor of 16. In addition
⎡ 1 1 − e − j (2 πf ( 4 ) ) ⎤
⎡⎛ 1 ⎞ sin (4 πf ) ⎤
H ( f ) − ⎢⎛⎜ ⎞⎟
⎥ = ⎢⎜ ⎟
⎥
j 2 πf
⎢⎣⎝ 4 ⎠ sin (πf ) ⎥⎦
⎢⎣⎝ 4 ⎠ 1 − e
⎥⎦
3
3
COMBINED FILTER RESPONSE
The combined frequency response of the HBF and CIC filters
limits the input signal bandwidth that can be propagated through
the AD9878.The usable bandwidth of the filter chain limits the
maximum data rate that can be propagated through the AD9878.
A look at the pass-band detail of the combined filter response
(Figure 25) indicates that to maintain an amplitude error of
1 dB or less, signal bandwidth is restricted to about 60% or less
of fNYQ.
Max BW (1dB droop) = 0.60 * fMCLK/8
Thus, in order to keep the bandwidth of the data in the flat
portion of the filter pass band, the user must oversample the
baseband data by at least a factor of two prior to presenting it to
the AD9878. Note that without oversampling, the Nyquist
bandwidth of the baseband data corresponds to fNYQ. As such,
the upper end of the data bandwidth suffers 6 dB or more of
attenuation due to the frequency response of the digital filters.
Furthermore, if the baseband data applied to the AD9878 has
Rev. A | Page 21 of 36
AD9878
0 < α < 1.
A value of 0 causes the data bandwidth to correspond to the
Nyquist bandwidth. A value of 1 causes the data bandwidth to
be extended to twice the Nyquist bandwidth. Thus, with 2× oversampling of the baseband data and α = 1, the Nyquist bandwidth
of the data corresponds with the I/Q Nyquist bandwidth. As stated
earlier, this results in problems near the upper edge of the data
bandwidth due to the frequency response of the filters. The
maximum value of α that can be implemented is 0.45, because the
data bandwidth becomes
1 2 (1 + α ) f NYQ = 0.725 f NYQ
Tx SIGNAL LEVEL CONSIDERATIONS
The quadrature modulator itself introduces a maximum gain of
3 dB in signal level. To visualize this, assume that both the I and
Q data are fixed at the maximum possible digital value, x. Then,
the output of the modulator, z, is
[
Q
X
Z
X
I
Figure 26. 16-Quadrature Modulation
It can be shown that |z| assumes a maximum value of
z = x 2 + x 2 = x 2 (a gain of +3 dB). However, if the
which puts the data bandwidth at the extreme edge of the flat
portion of the filter response.
If a particular application requires an α value between 0.45 and 1,
the user must oversample the baseband data by at least a factor of
4. Over the frequency range of the data to be transmitted, the
combined HBF 1, HBF 2, and CIC filters introduce a worst-case
droop of less than 0.2 dB.
same number of bits represent |z| and x, an overflow occurs.
To prevent this, an effective −3 dB attenuation is internally
implemented on the I and Q data path:
z = 1 2 +1 2 = x
The following example assumes a peak rms level of 10 dB:
Maximum Symbol Component Input Value =
1
± 2047 LSBs − 0.2 dB = ± 2000 LSBs
0
Maximum Complex Input RMS Value =
2000 LSBs ± 6 dB − Peak rms (dB ) = 1265 LSBs rms
–1
MAGNITUDE (dB)
]
z = x cos (ωt ) − x sin (ωt )
03277-010
been pulse shaped, there is an additional concern. Typically,
pulse shaping is applied to the baseband data via a filter with a
raised cosine response. In such cases, an α value is used to modify
the bandwidth of the data, where the value of α is such that
–2
The maximum complex input rms value calculation uses both
I and Q symbol components that add a factor of two (6 dB)
to the formula. Table 10 shows typical I-Q input test signals
with amplitude levels related to 12-bit full scale (FS).
–3
–4
03277-009
–5
–6
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
FREQUENCY RELATIVE TO I/Q NYQ BW
0.9
Table 10. I-Q Input Test Signals
Analog
Output
Single Tone
(fC − f)
1.0
Figure 25. Cascaded Filter Pass Band
DIGITAL UPCONVERTER
The digital quadrature modulator stage following the CIC filters
is used to frequency shift (upconvert) the baseband spectrum of
the incoming data stream to the desired carrier frequency. The
carrier frequency is controlled numerically by a direct digital
synthesizer (DDS). The DDS uses the internal system clock
(fSYSCLK) to generate the desired carrier frequency with a high
degree of precision. The carrier is applied to the I and Q
multipliers in a quadrature fashion (90° phase offset) and
summed to yield a data stream that is the modulated carrier. The
modulated carrier becomes the 12-bit sample sent to the DAC.
Single Tone
(fC + f)
Dual Tone
(fC ± f)
Rev. A | Page 22 of 36
Digital Input
I = cos(f)
Q = cos(f + 90°)
= −sin(f)
I = cos(f)
Q = cos(f + 270°)
= +sin(f)
I = cos(f)
FS − 0.2 dBFS
Q = cos(f + 180°)
= −cos(f) or
Q = +cos(f)
Input Level
FS − 0.2 dB
FS − 0.2 dB
Modulator
Output Level
FS − 3.0 dB
FS − 0.2 dB
FS − 0.2 dB
FS − 3.0 dB
FS − 0.2 dB
FS
FS − 0.2 dB
AD9878
Data inputs affect the output fairly quickly, but remain effective
due to the AD9878 filter characteristics. Data transmit latency
through the AD9878 is easiest to describe in terms of fSYSCLK clock
cycles (4 × fMCLK). The numbers provided indicate the number of
fSYSCLK cycles before the AD9878 output responds to a change in
the input.
Latency of I/Q data from the time it enters the data assembler
(AD9878 input) to the time of DAC output is 119 fSYSCLK clock
cycles (29.75 fMCLK cycles). DC values applied to the data assembler
input take up to 176 fSYSCLK clock cycles (44 fMCLK cycles) to
propagate and settle at the DAC output.
Frequency hopping is accomplished via changing the PROFILE
input pin. The time required to switch from one frequency to
another is less than 232 fSYSCLK cycles (58.5 fMCLK cycles).
DAC
A 12-bit digital-to-analog converter (DAC) is used to convert the
digitally processed waveform into an analog signal. The worstcase spurious signals due to the DAC are the harmonics of the
fundamental signal and their aliases (see the Analog Devices
DDS tutorial at www.analog.com/dds). The conversion process
produces aliased components of the fundamental signal at
n × f SYSCLK ± f CARRIER (n = 1, 2, 3). These are typically filtered
with an external RLC filter at the DAC output. It is important
for this analog filter to have a sufficiently flat gain and linear
phase response across the bandwidth of interest to avoid
modulation impairments. A relatively inexpensive seventhorder, elliptical, low-pass filter is sufficient to suppress the
aliased components for HFC network applications.
capacitance and inductance. The load can be a simple resistor to
ground, an op amp current-to-voltage converter, or a transformercoupled circuit. It is best not to directly drive a highly reactive
load, such as an LC filter. Driving an LC filter without a
transformer requires that the filter be doubly terminated for
best performance—that is, both the filter input and output should
be resistively terminated with the appropriate values. The parallel
combination of the two terminations determines the load that
the AD9878 sees for signals within the filter pass band. For
example, a 50 Ω terminated input/output low-pass filter looks
like a 25 Ω load to the AD9878. The output compliance voltage
of the AD9878 is −0.5 V to +1.5 V. Any signal developed at the
DAC output should not exceed 1.5 V; otherwise, signal distortion
results. Furthermore, the signal can extend below ground as much
as 0.5 V without damage or signal distortion. The AD9878 true
and complement outputs can be differentially combined for
common-mode rejection using a broadband 1:1 transformer.
Using a grounded center tap results in signals at the AD9878 DAC
output pins that are symmetrical about ground. As previously
mentioned, by differentially combining the two signals, the user
can provide some degree of common-mode signal rejection.
A differential combiner can consist of a transformer or an
op amp. The object is to combine or amplify the difference
between only two signals and to reject any common—usually
undesirable—characteristics, such as 60 Hz hum or clock
feedthrough, that is equally present on both signals.
AD9878
DAC
AD832x
Tx
CA
The AD9878 provides true and complement current outputs. The
full-scale output current is set by the RSET resistor at Pin 49 and
the DAC gain register. Assuming maximum DAC gain, the value
of RSET for a full-scale IOUT is determined using the equation:
R SET = 32 V DACRSET I OUT = 39.4 I OUT
For example, if a full-scale output current of 20 mA is desired,
then RSET = (39.4/0.02), or approximately 2 kΩ.
The following equation calculates the full-scale output current,
including the programmable DAC gain control:
I OUT = 39.4 R SET × 10 (−7.5 + 0.5 N GAIN ) 20
LOW-PASS
FILTER
75Ω
3
CA_EN
CA_DATA
CA_CLK
VARIABLE GAIN
CABLE DRIVER
AMPLIFIER
03277-011
Tx THROUGHPUT AND LATENCY
Figure 27. Cable Amplifier Connection
Connecting the AD9878 true and complement outputs to the
differential inputs of the programmable gain cable drivers
AD8321/AD8323 or AD8322/AD8327 (see Figure 27)
provides an optimized solution for the standard compliant
cable modem upstream channel. The cable driver’s gain
can be programmed through a direct 3-wire interface
using the AD9878 profile registers.
PROGRAMMING THE AD8321/AD8323 OR
AD8322/AD8327/AD8238 CABLE-DRIVER
AMPLIFIERS
where NGAIN is the value of DAC fine gain control [3:0].
The full-scale output current range of the AD9878 is 4 to
20 mA. Full-scale output currents outside this range degrade
SFDR performance. SFDR is also slightly affected by output
matching—that is, the two outputs should be terminated equally
for best SFDR performance. The output load should be located
as close as possible to the AD9878 package to minimize stray
Users can program the gain of the AD832x family of cable-driver
amplifiers via the AD9878 cable amplifier control interface. Two
(one per profile) 8-bit registers within the AD9878 store the gain
value to be written to the serial 3-wire port. Typically, either the
AD8321/AD8323 or AD8322/AD8327 variable gain cable
amplifiers are connected to the chip’s 3-wire cable amplifier
Rev. A | Page 23 of 36
AD9878
interface. The Tx gain control select bit in Register 0x0F changes
the interpretation of the bits in Register 0x13, Register 0x17,
Register 0x1B, and Register 0x1F. See Figure 28 and the
Cable-Driver Gain Control section.
8 tMCLK
4 tMCLK
8 tMCLK
CA_EN
8 tMCLK
External loop filter components, consisting of a series resistor
(1.3 kΩ) and capacitor (0.01 µF), provide the compensation
zero for the OSCIN multiplier PLL loop. The overall loop
performance is optimized for these component values.
4 tMCLK
MSB
LSB
03277-012
CA_CLK
CA_DATA
Figure 28. Cable Amplifier Interface Timing
Data transfers to the programmable gain cable-driver amplifier
are initiated by the following conditions:
•
•
•
•
30% of fSYSCLK. For a 65 MHz carrier, the system clock required is
above 216 MHz. The OSCIN multiplier function maintains
clock integrity, as evidenced by the part’s excellent phase noise
characteristics and low clock-related spur in the output spectrum.
Power-Up and Hardware Reset: Upon initial power-up and
every hardware reset, the AD9878 clears the contents of the
gain control registers to 0, which defines the lowest gain
setting of the AD832x. Thus, the AD9878 writes all 0s out
of the 3-wire cable amplifier control interface.
Software Reset: Writing a 1 to Bit 5 of Address 0x00 initiates
a software reset. Upon a software reset, the AD9878 clears
the contents of the gain control registers to 0 for the lowest
gain and sets the profile select to 0. The AD9878 writes all 0s
out of the 3-wire cable amplifier control interface if the
gain is previously on a different setting (different from 0).
Change in Profile Selection: The AD9878 samples the
PROFILE input pin together with the two profile select bits
and writes to the AD832x gain control registers when a
change in profile and gain is determined. The data written
to the cable-driver amplifier comes from the AD9878 gain
control register associated with the current profile.
Write to the AD9878 Cable-Driver Amplifier Control
Registers: The AD9878 writes gain control data associated
with the current profile to the AD832x when the selected
AD9878 cable-driver amplifier gain setting is changed. Once
a new, stable gain value is detected (48 to 64 MCLK cycles
after initiation) a data write starts with CA_EN going low.
The AD9878 always finishes a write sequence to the cabledriver amplifier once it is started. The logic controlling data
transfers to the cable-driver amplifier uses up to
200 MCLK cycles and is designed to prevent erroneous
write cycles from occurring.
CLOCK AND OSCILLATOR CIRCUITRY
The AD9878’s internal oscillator generates all sampling clocks
from a simple, low cost, parallel resonance, fundamental frequency quartz crystal. Figure 29 shows how the quartz crystal is
connected between OSCIN (Pin 61) and XTAL (Pin 60) with
parallel resonant load capacitors, as specified by the crystal
manufacturer. The internal oscillator circuitry can also be
overdriven by a TTL-level clock applied to OSCIN with
XTAL left unconnected.
f OSCIN = f MCLK × M
An internal PLL generates the DAC sampling frequency, fSYSCLK,
by multiplying the OSCIN frequency by M. The MCLK signal
(Pin 23), fMCLK, is derived by dividing fSYSCLK by 4.
f SYSCLK = f OSCIN × M
f MCLK = f OSCIN × M 4
An external PLL loop filter (Pin 57), consisting of a series resistor
and ceramic capacitor (Figure 29: R1 = 1.3 kΩ, C12 = 0.01 µF),
is required for stability of the PLL. Also, a shield surrounding
these components is recommended to minimize external noise
coupling into the PLL’s voltage-controlled oscillator input (guard
trace connected to AVDDPLL).
Figure 23 shows that ADCs are either sampled directly by a
low jitter clock at OSCIN or by a clock that is derived from the
PLL output. Operating modes can be selected in Register 0x08.
Sampling the ADCs directly with the OSCIN clock requires that
MCLK is programmed to be twice the OSCIN frequency.
PROGRAMMABLE CLOCK OUTPUT REFCLK
The AD9878 provides an auxiliary output clock on Pin 69,
REFCLK. The value of the MCLK divider bit field, R, determines
its output frequency, as shown in the following equations:
OSCIN CLOCK MULTIPLIER
f REFCLK = f MCLK R , for R = 2 to 63
The AD9878 can accept either an input clock into the OSCIN
pin or a fundamental-mode crystal across the OSCIN and
XTAL pins as the device’s main clock source. The internal PLL
then generates the fSYSCLK signal from which all other internal
signals are derived. The DAC uses fSYSCLK as its sampling clock.
For DDS applications, the carrier is typically limited to about
f REFCLK = f OSCIN , for R = 0
In its default setting (0x00 in Register 0x01), the REFCLK pin
provides a buffered output of fOSCIN.
Rev. A | Page 24 of 36
AD9878
CP2
10µF
C4
C5
0.1µF 0.1µF
CP1
10µF
C6
0.1µF
C1
C2
0.1µF 0.1µF
C3
0.1µF
AVDD
AGND
VIDEO IN
AGND
IF12A+
IF12A–
AGND
AVDD
REFT12A
REFB12A
AVDD
AGND
IF12B+
IF12B–
AGND
AVDD
REFT12B
REFB12B
AVDD
AGND
AVDD10
AGND10
IF10+
IF10–
AGND
CP1
10µF
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
C1
C2
0.1µF 0.1µF
DRGND 1
75
REFT10
DRVDD 2
74
REFB10
(MSB) IF12(11) 3
73
AGND10
IF12(10) 4
72
AVDD10
IF12(9) 5
71
DRVDD
IF12(8) 6
70
DRGND
IF12(7) 7
69
REFCLK
IF12(6) 8
68
SIGDELT
IF12(5) 9
67
FLAG1
IF12(4) 10
66
FLAG2
65
CA_EN
64
CA_DATA
63
CA_CLK
62
DVDDOSC
(MSB) IF10(4) 15
61
OSCIN
IF10(3) 16
60
XTAL
IF10(2) 17
59
DGNDOSC
IF10(1) 18
58
AGNDPLL
IF10(0) 19
57
PLLFILT
RxSYNC 20
56
AVDDPLL
DRGND 21
55
DVDDPLL
DRVDD 22
54
DGNDPLL
MCLK 23
53
AVDDTx
DVDD 24
52
Tx+
DGND 25
51
Tx–
AD9878
IF12(2) 12
TOP VIEW
(Not to Scale)
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
TxSYNC
(MSB) TxIQ(5)
TxIQ(4)
TxIQ(3)
TxIQ(2)
TxIQ(1)
TxIQ(0)
DVDD
DGND
DVDD
DGND
PROFILE
RESET
DVDD
DGND
SCLK
CS
SDIO
SDO
DGNDTx
DVDDTx
PWRDN
REFIO
FSADJ
IF12(0) 14
C13
0.1µF
Figure 29. Basic Connection Diagram
Rev. A | Page 25 of 36
C11
20pF
GUARD TRACE
R1
C12
1.3kΩ 0.01µF
50
AGNDTx
IF12(1) 13
C10
20pF
RSET
4.02Ω
03277-013
IF12(3) 11
C3
0.1µF
AD9878
POWER-UP SEQUENCE
RESET
Upon initial power-up, the RESET pin should be held low until the
power supply is stable (see Figure 30). Once RESET is deasserted,
the AD9878 can be programmed over the serial port. The onchip PLL requires a maximum of 1 ms after the rising edge of
RESET or a change of the multiplier factor (M) to completely
settle. It is recommended that the PWRDN pin is held low during
the reset and PLL settling time. Changes to ADC clock select
(Register 0x08) or System Clock Divider N (Register 0x01) should
be programmed before the rising edge of PWRDN. Once the PLL
is frequency locked and after the PWRDN pin is brought high,
transmit data can be sent reliably. If the PWRDN pin cannot be
held low throughout the reset and PLL settling time period,
the power-down digital Tx bit, or the PWRDN pin, should be
pulsed after the PLL has settled. This ensures correct transmit
filter initialization.
To initiate a hardware reset, the RESET pin should be held low
for at least 100 ns. All internally generated clocks, except REFCLK,
stop during reset. The rising edge of RESET resets the PLL clock
multiplier and reinitializes the programmable registers to their
default values. The same sequence as described in the Power-Up
Sequence section should be followed after a reset or change in M.
VS
RESET
5MCLK MIN.
PWRDN
Figure 30. Power-Up Sequence for Tx Data Path
03277-014
1ms MIN.
A software reset (writing 1 into Bit 5 of Register 0x00) is functionally equivalent to a hardware reset, but does not force
Register 0x00 to its default value.
TRANSMIT POWER-DOWN
A low level on the PWRDN pin stops all clocks linked to the
digital transmit data path and resets the CIC filter. Deasserting
PWRDN reactivates all clocks. The CIC filter is held in a reset
state for 80 MCLK cycles after the rising edge of PWRDN to
allow for flushing of the half-band filters with new input data.
Transmit data bursts should be padded with at least 20 symbols
of null data directly before the PWRDN pin is deasserted.
Immediately after the PWRDN pin is deasserted, the transmit
burst should start with a minimum of 20 null data symbols (see
Figure 31). This avoids unintended DAC output samples caused
by the transmit path latency and filter settling time.
Software power-down digital Tx (Bit 5 in Register 0x02) is functionally equivalent to the hardware PWRDN pin and takes effect
immediately after the last register bit is written over the serial port.
PWRDN
5MCLK MIN.
20 NULL SYMBOLS
0
0
0
DATA SYMBOLS
0
20 NULL SYMBOLS
0
0
0
0
03277-015
TxIQ
TxSYNC
Figure 31. Timing Sequence to Flush Tx Data Path
Rev. A | Page 26 of 36
AD9878
∑-∆ OUTPUTS
RECEIVE PATH (Rx)
An on-chip ∑-∆ output provides a digital logic bit stream with
an average duty cycle that varies between 0% and (255/256)%,
depending on the programmed code, as shown in Figure 32.
The AD9878 includes three high speed, high performance ADCs.
The 10-bit and dual 12-bit direct-IF ADCs deliver excellent undersampling performance with input frequencies as high as 70 MHz.
The sampling rate can be as high as 29 MSPS. The ADC sampling
frequency can be derived directly from the OSCIN signal, or from
the on-chip OSCIN multiplier. For highest dynamic performance,
choose an OSCIN frequency that can be directly used as the
ADC sampling clock. Digital 12-bit ADC outputs are multiplexed
to one 12-bit bus, clocked by a frequency (fMCLK) four times the
sampling rate. The IF ADCs use a multiplexer to a 12-bit interface
with an output word rate of fMCLK.
8 tMCLK
256 × 8 tMCLK
00h
01h
02h
80h
FFh
IF10 AND IF12 ADC OPERATION
03277-016
256 × 8 tMCLK
8 tMCLK
The IF10 and IF12 ADCs have a common architecture and
share several characteristics from an applications standpoint.
Most of the information in the following section is applicable to
both IF ADCs; differences, where they exist, are highlighted.
Figure 32. ∑-∆ Output Signals
This bit stream can be low-pass filtered to generate a
programmable dc voltage of
[
Input Signal Range and Digital Output Codes
]
VDC = (∑ -∆ Code 256 )× VH + VL
The IF ADCs have differential analog inputs labeled IF+ and IF−.
The signal input, VAIN, is the voltage difference between the two
input pins, VAIN = VIF+ − VIF−. The full-scale input voltage range is
determined by the internal reference voltages, REFT and REFB,
which define the top and bottom of the scale. The peak input
voltage to the ADC is the difference between REFT and REFB,
which is 1 V p-p. This results in an ADC full-scale input voltage
of 2 VPPD. The digital output codes are straight binary and are
shown in Table 11.
where:
V H = V DRVDD − 0.6 V
V L = 0. 4 V
In cable set-top box applications, the output can be used to
control external variable gain amplifiers or RF tuners. A
single-pole, RC, low-pass filter provides sufficient filtering
(see Figure 33). In more demanding applications, where
additional gain, level-shift, or drive capability is required,
consider using a first- or second-order filter (see Figure 34).
AD9878
DAC
8
CONTROL
WORD
Table 11. Digital Output Codes
R
Σ-∆
DC (VL TO VH)
C
÷8
MCLK
03277-017
TYPICAL: R = 50kΩ
C = 0.01µF
f–3dB = 1/(2πRC) = 318Hz
Figure 33. ∑-∆ RC Filter
C
R1
AD9878
R
IF12[11:0]
111…111
111…111
111…110
…
100…001
100…000
011…111
…
000…001
000…000
000…000
SIGMA-DELTA
VOUT
R
Σ-∆
VSD
OP250
C
R
VOFFSET
TYPICAL: R = 50kΩ
C = 0.01µF
f–3dB = 1/(2πRC) = 318Hz
03277-018
VOUT = (VSD + VOFFSET) (1 + R/R1)/2
Figure 34. ∑-∆ Active Filter with Gain and Offset
Rev. A | Page 27 of 36
Input Signal Voltage
VAIN ≥ +1.0 V
VAIN = +1.0 V − 1 LSB
VAIN = +1.0 V − 2 LSB
…
VAIN = 0 V + 1 LSB
VAIN = 0.0 V
VAIN = 0 V − 1 LSB
…
VAIN = −1.0 V + 2 LSB
VAIN = −1.0 V
VAIN < −1.0 V
AD9878
Driving the Input
Receive Timing
The IF ADCs have differential switched capacitor sample-andhold amplifier (SHA) inputs. The nominal differential input
impedance is 4.0 kΩ||3 pF. This impedance can be used as the
effective termination impedance when calculating filter transfer
characteristics and voltage signal attenuation from nonzero source
impedances. For best performance, additional requirements must
be met by the signal source. The SHA has input capacitors that
must be recharged each time the input is sampled. This results in
a dynamic input current at the device input, and demands that
the source has low (<50 Ω) output impedance at frequencies up
to the ADC sampling frequency. Also, the source must have
settling of better than 0.1% in less than half the ADC clock period.
The AD9878 sends multiplexed data to the IF10 and IF12 outputs
upon every rising edge of MCLK. RxSYNC frames the start of
each IF10 data symbol. The 10-bit and 12-bit ADCs are read
completely upon every second MCLK cycle. RxSYNC is high
for every second 10-bit ADC data if the 10-bit ADC is not in
power-down mode. The Rx timing diagram is shown in Figure 36.
33Ω
CC
33Ω
CC
IF10 DATA
tOD
IF10[9:5] IF10[4:0] IF10[9:5] IF10[4:0] IF10[9:5] IF10[4:0]
RxSYNC
IF12 DATA
IF12A
IF12B
IF12B
IF12B
IF12A
IF12B
Rx PORT TIMING (DEFAULT MODE: MUXED IF12 ADC DATA)
tEE
REFCLK
M/N = 2
tMD
tOD
MCLK
IF10 DATA
IF10[9:5]
IF10[4:0]
IF10[9:5]
IF10[4:0]
IF10[9:5]
IF10[4:0]
RxSYNC
IF DATA
IF12A OR IF12B
IF12A OR IF12B
IF12A OR IF12B
Rx PORT TIMING (OUTPUT DATA FROM ONLY ONE IF12 ADC)
Figure 36. Rx Port Timing
AIN+
CS
AIN–
M/N = 2
tMD
MCLK
03277-019
VS
REFCLK
Figure 35. Simple ADC Drive Configuration
Rev. A | Page 28 of 36
03277-020
Another consideration for getting the best performance from the
ADC inputs is the dc biasing of the input signal. Ideally, the signal
should be biased to a dc level equal to the midpoint of the ADC
reference voltages, REFT12 and REFB12. Nominally, this level is
1.2 V. When ac-coupled, the ADC inputs self-bias to this voltage
and require no additional input circuitry. Figure 35 illustrates a
recommended circuit that eases the burden on the signal source
by isolating its output from the ADC input. The 33 Ω series
termination resistors isolate the amplifier outputs from any
capacitive load, which typically improves settling time. The series
capacitors provide ac signal coupling, which ensures that the
ADC inputs operate at the optimal dc-bias voltage. The shunt
capacitor sources the dynamic currents required to charge the
SHA input capacitors, removing this requirement from the ADC
buffer. The values of CC and CS should be calculated to
determine the correct HPF and LPF corner frequencies.
tEE
AD9878
ADC VOLTAGE REFERENCES
VIDEO INPUT
The AD9878 has three independent internal references for its
10-bit and 12-bit ADCs. Both 12-bit and 10-bit ADCs are
designed for 2 V p-p input voltages and have their own internal
reference. Figure 29 shows the proper connections of the REFT
and REFB reference pins. External references might be necessary
for systems that require high accuracy gain matching between
ADCs, or for improvements in temperature drift and noise
characteristics. External references REFT and REFB must be
centered at AVDD/2, with offset voltages as specified by the
following equations:
For sampling video-type waveforms, such as NTSC and PAL
signals, the video input channel provides black-level clamping.
Figure 37 shows the circuit configuration for using the video
channel input (Pin 98). An external blocking capacitor is used
with the on-chip video clamp circuit to level-shift the input signal
to a desired reference point. The clamp circuit automatically
senses the most negative portion of the input signal and adjusts
the voltage across the input capacitor. This forces the black level
of the input signal to be equal to the value programmed in the
clamp level register (Register Address 0x07).
REFT − 10, − 12 : AVDD 2 + 0.5 V
REFT − 10, − 12 : AVDD 2 − 0.5 V
A differential level of 1 V between the reference pins results in a
2 V p-p ADC input level AIN. Internal reference sources can be
powered down when external references are used (Address 0x02).
By default, the video input is disabled and disconnected from
both ADCs. By setting Register 0x07, Bit 7 = 1, the video input
is enabled and connected to the ADC input as determined by
the state of Reg 0x03, Bit 6 ( 0= ADC12A connected, 1 =
ADC12B connected.)
CLAMP LEVEL + FS/2
AD9878
CLAMP LEVEL
VIDEO INPUT
BUFFER
12
0.1µF
ADC
–
+
DAC
LPF
OFFSET
Figure 37. Video Clamp Circuit Input
Rev. A | Page 29 of 36
03277-021
2mA
CLAMP
LEVEL
AD9878
PCB DESIGN CONSIDERATIONS
Although the AD9878 is a mixed-signal device, the part should be
treated as an analog component. The on-chip digital circuitry is
designed to minimize the impact of digital switching noise on the
operation of the analog circuits. Following the recommendations
in this section helps achieve the best performance from the MxFE.
COMPONENT PLACEMENT
The following guidelines for component placement are
recommended to achieve optimal performance:
• Manage the path of return currents to ensure that high
frequency switching currents from the digital circuits do not
flow into the ground plane under the MxFE or analog circuits.
• Keep noisy digital signal paths and sensitive receive signal
paths as short as possible.
• Keep digital (noise-generating) and analog (noise-susceptible)
circuits as far apart as possible.
To best manage the return currents, pure digital circuits that
generate high switching currents should be closest to the power
supply entry. This keeps the highest frequency return current
paths short and prevents them from traveling over the sensitive
MxFE and analog portions of the ground plane. Also, these
circuits should be generously bypassed at each device to further
reduce high frequency ground currents. The MxFE should be
placed adjacent to the digital circuits, such that the ground return
currents from the digital sections do not flow into the ground
plane under the MxFE. The analog circuits should be placed
furthest from the power supply. The AD9878 has several pins that
are used to decouple sensitive internal nodes: REFIO, REFB12A,
REFT12A, REFB12B, REFT12B, REFB10, and REFT10. The
decoupling capacitors connected to these points should have low
ESR and ESL, be placed as close as possible to the MxFE, and be
connected directly to the analog ground plane. The resistor
connected to the FSADJ pin and the RC network connected to
the PLLFILT pin should also be placed close to the device and
connected directly to the analog ground plane.
POWER PLANES AND DECOUPLING
The AD9878 evaluation board (Figure 38 and Figure 39)
demonstrates a good power supply distribution and decoupling
strategy. The board has four layers: two signal layers, one ground
plane, and one power plane. The power plane is split into a 3-VDD
section that is used for the 3 V digital logic circuits, a DVDD
section that is used to supply the digital supply pins of the
AD9878, an AVDD section that is used to supply the analog
supply pins of the AD9878, and a VANLG section that supplies
the higher voltage analog components on the board. The 3-VDD
section typically has the highest frequency currents on the power
plane and should be kept the furthest from the MxFE and analog
sections of the board.
The DVDD portion of the plane carries the current used to power
the digital portion of the MxFE to the device. This should be
treated similarly to the 3-VDD power plane and be kept from going
underneath the MxFE or analog components. The MxFE should
largely sit above the AVDD portion of the power plane. The
AVDD and DVDD power planes can be fed from the same low
noise voltage source; however, they should be decoupled from
each other to prevent the noise generated in the DVDD portion
of the MxFE from corrupting the AVDD supply. This can be done
by using ferrite beads between the voltage source and DVDD, and
between the source and AVDD. Both DVDD and AVDD should
have a low ESR, bulk-decoupling capacitor on the MxFE side of
the ferrite as well as low ESR- and ESL-decoupling capacitors on
each supply pin (for example, the AD9878 requires 17 power
supply decoupling capacitors). The decoupling capacitors should
be placed as close as possible to the MxFE supply pins. An
example of proper decoupling is shown in the AD9878 evaluation
board’s two-page schematic (Figure 38 and Figure 39).
GROUND PLANES
In general, if the component placing guidelines discussed earlier
can be implemented, it is best to have at least one continuous
ground plane for the entire board. All ground connections should
be as short as possible. This results in the lowest impedance return
paths and the quietest ground connections. If the components
cannot be placed in a manner that keeps the high frequency
ground currents from traversing under the MxFE and analog
components, it might be necessary to put current-steering
channels into the ground plane to route the high frequency
currents around these sensitive areas. These current-steering
channels should be used only when and where necessary.
SIGNAL ROUTING
The digital Rx and Tx signal paths should be as short as possible.
Also, these traces should have a controlled impedance of about
50 Ω. This prevents poor signal integrity and the high currents
that can occur during undershoot or overshoot caused by ringing.
If the signal traces cannot be kept shorter than about 1.5 inches,
then series termination resistors (33 Ω to 47 Ω) should be placed
close to all signal sources. It is a good idea to series terminate all
clock signals at their source, regardless of trace length. The receive
signals are the most sensitive signals on the evaluation board.
Careful routing of these signals is essential for good receive path
performance. The IF+/IF− signals form a differential pair and
should be routed together. By keeping the traces adjacent to each
other, noise coupled onto the signals appears as common mode
and is largely rejected by the MxFE receive input. Keeping the
driving point impedance of the receive signal low and placing
any low-pass filtering of the signals close to the MxFE further
reduces the possibility of noise corrupting these signals.
Rev. A | Page 30 of 36
2
R24
49.9Ω
1
8
U9
C91
10µF
16V +
A_BUFF–
C96
10µF
16V +
RC0805
R23
523Ω
RC0805
A_BUFF+
AD8138
AGND; 3, 4, 5
R18
SMAEDGE
499Ω
1
J12
RC0805
BCASE
6
VO–
4
RC0805
R22
499Ω
C97
0.1µF
3
–IN
VCC
VO+
RC0805
R21
33Ω
2
RC0805
RC0805
5
R14
33Ω
R15
10kΩ
JP4
R9
49.9Ω
R17
499Ω
C90
0.1µF
RC0805
AD8138 VOC
VEE
+IN
BCASE
CC0805
RC0805
J3
CC0805
C19
0.1µF
BCASE
R7
500Ω
AD8138 3
2
4
AD8138 3
8138–
C95
47pF
C88 J11
47pF
2
A
4
3
2
3
A
1
JP23
A
2
3
C94
0.1µF
CC0603
B
4
3
RC0805
AD8138 1
5
6
2
R13
33Ω
RC0805
IF12A–
C92
20pF
VCML
TRANSF
R19
33Ω
JP22
TRANSF
IF12A+
IF12B–
RC0805
RC0805
C98
20pF
VCML
TRANSF
R25
33Ω
JP24
R20
49.9Ω
1
IF12B+
IF10–
TRANSF
RC0805
R26
33Ω
RC0805
C108
20pF
VCML
TRANSF
R32
33Ω
DIP06RCUP
T2
IF10+
XTAL
OSCIN
EXT_CLK
JP1
TRANSF
RC0805
R31
33Ω
Y1
VAL
JP30
C86
2 0.1µF
JP21
B
8138+
2
CC0603
C102
0.1µF
CC0603
B
VCML
A
JP26
DIP06RCUP
5
2
T3
1
6
AD8138 3
AGND; 3, 4, 5
SMAEDGE
1
CC0603
1
R16
5.11kΩ
IF12A
C87
0.1µF
8138–
AD8138 1
RC0805
R27
2
49.9Ω
3
CC0603
C112
0.1µF
C101
2 0.1µF
2
B
JP25
B
A
JP32
DIP06RCUP
5
6
3
T5
1
2
AGND; 3, 4, 5
SMAEDGE
1
J13
A
C111
0.1µF
RC0805
1
2
JP31
B
CC0603
C17
18pF
CC0805
3
CC0805
C18
18pF
RC0805
1
CC0805
CC0805
R5
33Ω
C110
0.1µF
R33
49.9Ω
AD8138 1
IF12B
8138+
8138–
J13
AGND; 3, 4, 5
SMAEDGE
1
IF10
4
U13
NC7SZ04
2
POT1 AGND; 3
10kΩ V_CLK; 5
8138+
CW
RC0805
CC1206
OSCIN_CLK
AGND; 3, 4, 5
SMA200UP
RC0805
CC0805
CC0805
C84
0.1µF
C4
10µF
10V
C3
0.1µF
C2
0.1µF
C14
10µF
16V
C8
10µF
10V
C7
0.1µF
C6
0.1µF
RC0805
Tx_OUT
J4
C9
0.1µF
C5
0.1µF
+
+
C12
0.1µF
+
3
AVDD
DRVDD
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
J1
2
1
AGND; 3, 4, 5
SMAEDGE
CC0603
CC0603
U2
R12
37.5Ω
RC0605
RC0605
R11
37.5Ω
AGNDTx
FSADJ
REFIO
PWRDN
DVDDTx
DGNDTx
SDO
SDIO
CS
SCLK
DGND4
DVDD4
RESET
PROFILE
DGND3
DVDD3
DGND2
DVDD2
TxIQ0
TxIQ1
TxIQ2
TxIQ3
TxIQ4
TxIQ5
TxSYNC
DGND1
DVDD1
MCLK
DRVDD2
DRGND2
RxSYNC
IFB0
IFB1
IFB2
IFB3
IFB4
IF0
IF1
IF2
IF3
IF4
IF5
IF6
IF7
IF8
IF9
IF10
IF11
DRVDD1
DRGND1
RC0805
CC0603
C10
R2
33Ω 0.1µF
R1
75Ω
1
2
3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
S P
TOKOB5F C72
0.1µF
5
T6
AD9878LQFP
Tx–
Tx+
AVDDTx
DGNDPLL
DVDDPLL
AVDDPLL
PLLFILT
AGNDPLL
DGNDOSC
XTAL
OSCIN
DVDDOSC
CA_CLK
CA_DATA
CA_EN
FLAG2
FLAG1
SIGDELT
REFCLK
DRGND
DRVDD
AVDD10
AGND10
REFB10
REFT10
AGND1
IF10B–
IF10B+
AGND10-A
AVDD10-A
AGND2
AVDD1
REFB12B
REFT12B
AVDD2
AGND3
IF12B–
IF12B+
AGND4
AVDD3
REFB12A
REFT12A
AVDD4
AGND5
IF12A–
IF12A+
AGND6
VIDEO IN
AGND7
AVDD5
VIDEO IN
AVDDTx
4
C24
0.1µF
R40
86.6Ω
S P
DIP06RCUP
DVDDPLL/
DVDDOSC
2
6
2
RC0605
R39
43.3Ω 4
C23
0.1µF
T1
J8
AGND; 3, 4, 5
SMAEDGE
1
Tx_OUT
AD8328
RC0605
5
2
AGND; 3, 4, 5
SMAEDGE
1 1
TP15 TP6 TP5 TP1 TP2
WHT WHT WHT WHT WHT
CC0603
C16
R4
0.01µF 1.3kΩ
C13
0.1µF
TP3
WHT
RC0805
R3
100kΩ
C11
0.1µF
CA_CLK
CA_DATA
CA_EN
FLAG2
FLAG1
SIGDELT0
REFCLK
CC0603
C15
0.01µF
CC0603
CC0603
TP4
WHT
C66
0.1µF
C69
0.1µF
CC0603
CC0603
CC0603
CC0603
CC0603
CC0603
CC0603
C21
0.1µF
RxSYNC
IFB0
IFB1
IFB2
IFB3
IFB4
IF0
IF1
IF2
IF3
IF4
IF5
IF6
IF7
IF8
IF9
IF10
IF11
MCLK
DRVDD
B
2
B
C22
0.1µF
JP7
A
PROFILE1
TxIQ0
TxIQ1
TxIQ2
TxIQ3
TxIQ4
TxIQ5
TxSYNC
DVDD
SDO
SDIO
CS
SCLK
PWRDN
DVDDTx
R10
10kΩ
RC0805
TRANSF 1
2
RC0603
JP8
A
Tx–
TRANSF 1
Tx+
CA_SLEEP
C116
0.1µF
C115
0.1µF
CC0603
V_CLK
CC0603
CC0603
CC0603
CC0603
R6
C83 +
500Ω 10µF
16V
CC0805
BCASE
C20
18pF
3
1
2
AD8328
3
U4
AD8328
L16
220
3
4
L15
220
VCC
GND
R29
10kΩ
JP9
3
2
C113
0.01µF
R37
59Ω
C114
0.01µF
C1
0.1µF
DRVDD
CC0603
CC0603
IF[0:11]
IFB[0:4]
1
3
5
7
9
11
13
15
17
19
21
23
25
2
4
6
8
10
12
14
16
18
20
22
24
26
J2
RIBBON
SDO, SDIO, CS, SCLK
ADM1818-10ART
U1
RESET
RC0805
R36
75Ω
RC0805
R38
75Ω
CA_EN
CA_DATA
CA_CLK
DRVDD PWRDN
1
LC1210
L14
220
C58
18pF
LC1210
AGND; 5
RESET
SW1
RESET
LC1210
L13
220
C57
33pF
LC1210
1
5V AD8328
GND5
GND
2
VCC
VCC1
3
GND1
TxEN
4
GND2
RAMP
5
VIN+
VOUT+
6
VIN–
VOUT–
7
BYP
GND3
8
NC
DATAEN
9
SLEEP
SDATA
10
GND4
CLK
AD8328
11
12
13
14
15
16
17
18
19
20
RC0805
RC0805
BCASE
BCASE
CC0805
RP1
CC0805
1
RCOM
2 22 R1
3
R2
4
R3
5
R4
6
R5
7
R6
8
R7
9
R8
10
R9
CC0805
RC0805
CC0603
DUTY
CYCLE
CC0603
CC0603
CC0603
Rev. A | Page 31 of 36
CC0805
Figure 38. Evaluation PCB Schematic
CC0805
OSCIN
CC1206
XTAL
RC07CUP
HEADER RA RIBBON
R28
1kΩ
DIGITAL TRANSMIT
C117
0.1µF
03277-038
5V AD8328
AD9878
POWER
TB1 1
TB1 2
TB1 3
TB1 4
TB1 5
TB1 6
TB1 7
TB1 8
3.3V_ANA
GND
–5V_ANA
GND
+5V_ANA
GND
5V_DIG
3.3V_DIG
5V
3.3V_DIG
JP2
AD8328
ABUFF+
ABUFF–
3.3V_ANA
BCASE
C41
10µF
16V
BCASE
C42
10µF
16V
BCASE
C27
10µF
16V
BCASE
C40
10µF
16V
BCASE
C26
10µF
16V
BCASE
C25
10µF
16V
BCASE
C79
10µF
16V
BCASE
C77
10µF
16V
BCASE
C78
10µF
16V
BCASE
C60
10µF
16V
BCASE
C61
10µF
16V
BCASE
C59
10µF
16V
L11
+
L8
+
L9
+
+
L5
+
L6
+
L3
+
L4
+
L2
+
L1
+
L12
+
L10
LC1210
LC1210
LC1210
LC1210
LC1210
LC1210
LC1210
LC1210
LC1210
LC1210
LC1210
LC1210
VAL
VAL
VAL
VAL
VAL
VAL
VAL
VAL
VAL
VAL
VAL
VAL
CC0603
CC0805
CC0603
CC0805
CC0603
CC0805
CC0603
CC0805
CC0603
CC0805
C47
0.1µF
CC0603
C44
0.1µF
CC0805
TP11
CLR
C56
0.1µF
C45
0.1µF
TP10
CLR
C33
0.1µF
C30
0.1µF
DVDDTx
CC0603
CC0805
TP9
CLR
C52
0.1µF
C43
0.1µF
TP8
CLR
C32
0.1µF
C29
0.1µF
TP7
CLR
C31
0.1µF
CC0603
C38
0.1µF
DRVDD
CC0603
C37
0.1µF
CC0603
C73
0.1µF
AVDDTx
CC0603
C74
0.1µF
CC0603
C50
0.1µF
CC0605
C54
0.1µF
CC0603
C36
0.1µF
CC0603
C49
0.1µF
CC0603
C55
0.1µF
CC0805
C51
0.1µF
AVDD
CC0603
C68
0.1µF
CC0603
C53
0.1µF
5V_BUFF
CC0603
C100
0.1µF
IFB[0:4]
C48
0.1µF
CC0605
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
IF[0:11]
3.3V_BUFF
CC0603
C39
0.1µF
5V_BUFF
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
J5
RIBBON
HDR040RA
CC0805
C75
0.1µF
CC0603
C71
0.1µF
3.3V_BUFF
CC0605
C46
0.1µF
DVDDPLL/
DVDDOSC
CC0603
C35
0.1µF
CC0603
C34
0.1µF
DVDD
5V_AD8328
A_BUFF+
A_BUFF–
C28
0.1µF
TP19
CLR
CC0805
C82
0.1µF
TP13
CLR
CC0805
C80
0.1µF
TP12
CLR
CC0805
C81
0.1µF
TP14
CLR
CC0805
C63
0.1µF
CC0603
C70
0.1µF
CC0603
C76
0.1µF
AVDDPLL
CC0603
CC0805
TP16
CLR
C67
0.1µF
C64
0.1µF
TP17
CLR
C85
0.1µF
C62
0.1µF
TP18
CLR
CC0805
DIGITAL RECEIVE
L7
24
BCASE
CC0603
C65
0.1µF
9
9
8
IF11
V_CLK
10
10
7
IF10
VCCB
12
11
6
IF9
VCCA
1
11
6
12
5
C93
0.1µF
2
RP3 22
22
OE
23
NC
T/R
8
14
14
IF8
9
A7
10
RP6 22
7
B7
A6
15
B6
A5
5
7
16
U5
A4
B5
74LVXC3245
17
B4
TSSOP24
13
4
IF7
8
13
4
B3
14
3
5
A3
16
1
A2
18
15
2
IF6
6
3
19
B2
15
2
IF5
4
A1
13
B1
20
B0
21
GND3
A0
11
GND1
12
GND2
3
16
1
IF4
1
J7
1
RC0603
R35
33Ω
2
A
2
IF0
JP13
B
3
IFB4
U3
4
NC7SZ04
AGND; 3
5V_BUFF; 5
2
MCLK
AGND; 3, 4, 5
SMAEDGE
3
B
A
+
9
8
IF3
INVERT CLK
JP5 2
13
1
B
A
TP20
CLR
10
7
IF2
24
1
9
11
6
IF1
VCCB
23
NC
RP5 22
8
12
5
VCCA
22
T/R
2
RP2 22
B7
OE
A7
10
11
6
13
9
A6
14
10
7
B6
A5
15
12
5
U6
7
16
A4
74LVXC3245 B5 17
6
B4
TSSOP24
4
8
13
4
18
B3
A2
5
14
3
A3
14
3
19
15
2
20
16
1
21
B2
A1
15
2
4
B1
13
B0
16
1
3
GND3
A0
11
GND1
24
GND2
12
RP4 22
22
NC
RP7 22
VCCB
23
OE
T/R
2
A0
3
8
1
MCLK
VCCA
1
16
1
B0
7
2
RxSYNC
11
6
1
14
3
6
3
4
A1
21
15
2
20
B1
A2
5
4
5
4
DEL_CLK
RC0603
R8
100Ω
10
1
2
3
4
5
6
7
8
11
RJ45
13
12
11
10
9
8
7
6
5
4
3
SDO
12
25
24
23
22
21
20
19
18
17
16
15
14
J6
DCN2 5 RPT
9
2
JP3
SCS
SSCLK
SSDIO
SDOPC
P1
1
22
RC0603
16
R34
1kΩ
23
DEL_CLK
JP6 2
DEL_CLK
10
7
3
12
5
6
19
U7
A3
B2
74LVXC3245
7
18
A4
B3
TSSOP24
17
9
8
B4
A5
16
B5
15
B6
14
B7
21
VAL
CA_SLEEP DVDD
A6
13
A7
24
1
NC
T/R
2
20
B0
OE
A0
3
B1
A1
5
SDIO
GND1
8
19
6
CS
A2
4
SDOPC
GND3
9
15
B5
A6
LC1210
A3
B2
U8
7
18
A4 74LVXC3245 B3
17
TSSOP24
B4
SCLK
GND2
10
A5
8
VCCB
11
14
B6
A7
9
VCCA
12
13
B7
GND1
10
GND3
GND2
Rev. A | Page 32 of 36
11
Figure 39. Evaluation PCB Schematic (Continued)
12
L17
PC PARALLEL PORT
03277-039
+
C89
10µF
16V
AD9878
03277-040
AD9878
03277-041
Figure 40. Evaluation PCB—Top Assembly
Figure 41. Evaluation PCB—Bottom Assembly
Rev. A | Page 33 of 36
03277-042
AD9878
03277-043
Figure 42. Evaluation PCB Layout—Top Layer
Figure 43. Evaluation PCB Layout—Bottom Layer
Rev. A | Page 34 of 36
03277-044
AD9878
03277-045
Figure 44. Evaluation PCB—Power Plane
Figure 45. Evaluation PCB—Ground Plane
Rev. A | Page 35 of 36
AD9878
OUTLINE DIMENSIONS
16.00 BSC SQ
1.60 MAX
0.75
0.60
0.45
14.00 BSC SQ
100
1
76
75
PIN 1
12.00
REF
TOP VIEW
(PINS DOWN)
1.45
1.40
1.35
0.15
0.05
SEATING
PLANE
0.20
0.09
7°
3.5°
0°
0.08 MAX
COPLANARITY
25
51
50
26
VIEW A
0.50
BSC
LEAD PITCH
VIEW A
ROTATED 90° CCW
0.27
0.22
0.17
COMPLIANT TO JEDEC STANDARDS MS-026BED
Figure 46. 100-Lead Low Profile Quad Flat Package [LQFP]
(ST-100)
Dimensions shown in millimeters
ORDERING GUIDE
Model
AD9878BST
AD9878BSTZ1
AD9878-EB
1
Temperature Range
−40°C to +85°C
−40°C to +85°C
Package Description
100-LQFP
100-LQFP
Evaluation Board
Z = Pb-free part.
© 2005 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
C03277–0–3/05(A)
Rev. A | Page 36 of 36
Package Option
ST-100
ST-100
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