ADUC7060

ADUC7060
Preliminary Technical Data
Low-Power, Precision Analog Microcontroller,
Dual Σ-Δ ADCs, Flash/EE, ARM7TDMI
ADuC7060/ADuC7061
FEATURES
Analog input/output
Dual (24-bit) ADCs
Single-ended and differential inputs
Programmable ADC output rate (4 Hz to 8 kHz)
Programmable digital filters
Built-in system calibration
Low power operation mode
Primary (24-bit) ADC channel
Up to 5 input channels
PGA (1 to 512) input stage
Selectable input range, ±2.34 mV to ±1.2 V
30 nV rms noise
Auxiliary (24-bit) ADC: up to 8 buffered input channels
On-chip precision reference (±10 ppm/°C)
Programmable sensor excitation current sources
200 μA to 2 mA current source range
Single 16-bit voltage output DAC
Microcontroller
ARM7TDMI core, 16-/32-bit RISC architecture
JTAG port supports code download and debug
Multiple clocking options
Memory
32 kB (16 kB × 16) Flash/EE memory
4 kB (1 kB × 32) SRAM
Tools
In-circuit download, JTAG based debug
Low cost, QuickStart development system
Communications interfaces
SPI interface (5 Mbps)
4-byte Rx and Tx FIFOs
UART serial I/O and I2C (master/slave)
On-chip peripherals
4× and 2× general-purpose (capture/compare) timers
Wakeup timer
Watchdog timer
Vectored interrupt controller for FIQ and IRQ
8 priority levels for each interrupt type
Interrupt on edge or level external pin inputs
16-bit, 6-channel PWM
General-purpose inputs/outputs
Up to 14 GPIO pins that are fully 3.3 V compliant
Power
AVDD/DVDD specified for 2.5 V (+5%)
All inputs/outputs fully 3.3 V compliant
Active mode: 2.6 mA (@1 MHz, both ADCs active)
10 mA (@10 MHz, both ADCs active)
Packages and temperature range
Fully specified for −40°C to +125°C operation
32-lead LFCSP (5 mm × 5 mm)
48-lead LFCSP and LQFP
Derivatives
32-lead LFCSP, dual ADCs (ADuC7061)
48-lead LQFP and 48-lead LFCSP, dual ADCs (ADuC7060)
APPLICATIONS
Industrial automation and process control
Intelligent, precision sensing systems, 4 mA to 20 mA loopbased smart sensors
GENERAL DESCRIPTION
The ADuC7060/ADuC7061 are fully integrated, 8 kSPS, 24-bit
data acquisition systems incorporating high performance multichannel sigma-delta (Σ-Δ) analog-to-digital converters (ADCs),
16-bit/ 32-bit ARM7TDMI® MCU, and Flash/EE memory on a
single chip.
The ADCs consists of a 5-channel primary ADC and up to an
8-channel auxiliary ADC. The ADCs operate in single-ended or
differential input modes. A single channel buffered voltage output
DAC is available on-chip. The DAC output range is programmable
to one of two voltage ranges.
The devices operate from an on-chip oscillator and a PLL generating an internal high frequency clock up to 10.24 MHz. The
microcontroller core is an ARM7TDMI, 16-bit/32-bit RISC
machine offering up to 10 MIPS peak performance. 4 kB of
SRAM and 32 kB of nonvolatile Flash/EE memory are provided
on-chip. The ARM7TDMI core views all memory and registers
as a single linear array.
The ADuC7060/ADuC7061 contain four timers. Timer 1 is
wake-up timer with the ability to bring the part out of power
saving mode. Timer 2 may be configured as a watchdog timer.
A 16-bit PWM with six output channels is also provided.
The ADuC7060/ADuC7061 contain an advanced interrupt
controller. The vectored interrupt controller (VIC) allows every
interrupt to be assigned a priority level. It also supports nested
interrupts to a maximum level of eight per IRQ and FIQ. When
IRQ and FIQ interrupt sources are combined, a total of 16
nested interrupt levels are supported.On-chip factory firmware
supports in-circuit serial download via the UART serial interface
ports and nonintrusive emulation via the JTAG interface.
The parts operate from 2.375 V to 2.625 V over an industrial
temperature range of −40°C to +125°C.
Rev. PrC
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2008 Analog Devices, Inc. All rights reserved.
ADuC7060/ADuC7061
Preliminary Technical Data
TABLE OF CONTENTS
Features .............................................................................................. 1 IRQ ............................................................................................... 50 Applications ....................................................................................... 1 Fast Interrupt Request (FIQ) .................................................... 51 General Description ......................................................................... 1 Timers .............................................................................................. 57 Revision History ............................................................................... 2 Timer0.......................................................................................... 58 Functional Block Diagram .............................................................. 3 Timer1 or Wake-Up Timer ....................................................... 60 Specifications..................................................................................... 4 Timer2 or Watchdog Timer ...................................................... 62 Electrical Specifications ............................................................... 4 Timer3.......................................................................................... 64 Timing Specifications .................................................................. 8 Pulse-Width Modulator (PWM) .................................................. 66 Absolute Maximum Ratings............................................................ 9 PWM General Overview ........................................................... 66 ESD Caution .................................................................................. 9 UART Serial Interface .................................................................... 71 Pin Configurations and Function Descriptions ......................... 10 Baud Rate Generation ................................................................ 71 Terminology .................................................................................... 14 UART Register Definition ......................................................... 71 Overview of the ARM7TDMI Core ............................................. 15 I C ..................................................................................................... 76 Thumb Mode (T)........................................................................ 15 Serial Clock Generation ............................................................ 77 Multiplier (M) ............................................................................. 15 I2C Bus Addresses ....................................................................... 77 Embedded ICE (I) ...................................................................... 15 I2C Registers ................................................................................ 77 ARM Registers ............................................................................ 15 I2C Common Registers .............................................................. 85 Interrupt Latency ........................................................................ 16 Serial Peripheral Interface ............................................................. 86 Memory Organization ............................................................... 16 MISO (Master In, Slave Out) Pin ............................................. 86 Flash/EE Control Interface........................................................ 17 MOSI (Master Out, Slave In) Pin ............................................. 86 Memory Mapped Registers ....................................................... 20 SCL (Serial Clock I/O) Pin........................................................ 86 Complete MMR Listing ............................................................. 21 Slave Select (SS Input) Pin......................................................... 86 Reset ............................................................................................. 26 Configuring External pins for SPI functionality .................... 86 Oscillator, PLL and Power Control .............................................. 27 SPI Registers ................................................................................ 87 ADC Circuit information .............................................................. 30 General-Purpose I/O ..................................................................... 91 Example Application Circuits ................................................... 46 GPxCON Registers..................................................................... 91 DAC Peripherals ............................................................................. 47 GPxDAT Registers ..................................................................... 92 DAC .............................................................................................. 47 GPxSET Registers ....................................................................... 92 MMR Interface............................................................................ 47 GPxCLR Registers ...................................................................... 92 Nonvolatile Flash/EE Memory ..................................................... 49 GPxPAR Registers ...................................................................... 92 Flash/EE Memory Reliability .................................................... 49 Hardware Design Considerations ................................................ 94 Programming .............................................................................. 49 Power Supplies ............................................................................ 94 Processor Reference Peripherals ................................................... 50 Outline Dimensions ....................................................................... 95 Interrupt System ......................................................................... 50 Ordering Guide .......................................................................... 96 2
REVISION HISTORY
12/08 – Revision PrC: Preliminary Version
Rev. PrC | Page 2 of 96
Preliminary Technical Data
ADuC7060/ADuC7061
FUNCTIONAL BLOCK DIAGRAM
PRECISION ANALOG PERIPHERALS
MUX
PGA
24-BIT
Σ-Δ ADC
ARM7TDMI
MCU
AIN2
AIN3
AIN4
AIN5
AIN6
AIN7
AIN8
AIN9
MUX
BUF
10MHz
ON-CHIP
OSC (3%)
PLL
4× TIMERS
WDT
W/U TIMER
PWM
GPIO PORT
UART PORT
SPI PORT
I2C PORT
24-BIT
Σ-Δ
ADC
PRECISION
REFERENCE
IEXC0
IEXC1
DAC
VREF+
MEMORY
32kB FLASH
4kB RAM
POR
BUF
14-BIT
DAC
TEMP
SENSOR
VREF–
Figure 1.
Rev. PrC | Page 3 of 96
XTAL1
XTAL2
VIC
(VECTORED
INTERRUPT
CONTROLLER)
ADuC7060/
ADuC7061
GND_SW
RESET
07079-001
AIN0
AIN1
ADuC7060/ADuC7061
Preliminary Technical Data
SPECIFICATIONS
ELECTRICAL SPECIFICATIONS
VDD = 2.5 V ± 5%, VREF+ = 1.2 V, VREF− = GND internal reference, fCORE = 10.24 MHz driven from external 32.768 kHz watch crystal or onchip precision oscillator, all specifications TA = −40°C to +125°C, unless otherwise noted.
Table 1. ADuC706x Specifications
Parameter
ADC SPECIFICATIONS
Conversion Rate 1
Main Channel
No Missing Codes1
Integral Nonlinearity 2
Offset Error 3, 4
Offset Error3, 4
Offset Error Drift vs.
Temperature 5
Offset Error Drift vs.
Temperature5
Full Scale Error1, 6, 7, 8
Full Scale Error1, 6, 7, 8
Gain Drift v Temperature 9
PGA Gain Mismatch Error
Output Noise1
Power Supply Rejection
Aux Channel
No Missing Codes1
Integral Nonlinearity
Offset Error4
Offset Error4
Offset Error Drift vs.
Temperature5
Offset Error Drift vs.
Temperature5
Full-Scale Error1, 6, 7, 8
Full-Scale Error1, 6, 8
Gain Drift vs. Temperature9
Output Noise
Power Supply Rejection
Test Conditions/Comments
For all ADC specifications, assume
normal operating mode unless
specifically stated otherwise
Chop off, ADC normal operating
mode
Chop on, ADC normal operating
mode
Chop on, ADC low power mode
Min
Chop off (fADC ≤ 1 kHz)
Chop on (fADC ≤ 666 Hz)
24
24
Typ
Max
Unit
50
8000
Hz
4
2600
Hz
1
650
Hz
±15
±4
Bits
Bits
ppm of FSR
μV
±0.5
650/PGA_GAIN
μV
nV/°C
Chop on (with GAIN ≤ 64)
10
nV/°C
Normal mode
Low power mode
±0.5
±1.0
mV
mV
5
±0.1
ppm/°C
%
80
113
80
dB
dB
dB
Chop off
Chop on
Chop off
±15
±0.5
200
Bits
Bits
ppm of FSR
μV
μV
nV/°C
Chop on
10
nV/°C
Normal mode
Low power mode
±0.5
±1.0
3
mV
mV
ppm/°C
80
dB
Chop off, offset error is in the order
of the noise for the programmed
gain and update rate following
calibration
Chop on
Chop off (with GAIN ≤ 64)
See Table 29
Chop on, ADC = 1 V, (gain = 1)
Chop on, ADC = 7.8 mV, (gain = 128)
Chop off, ADC = 1 V, (gain = 1)
Chop off (fADC ≤ 1 kHz)
Chop on (fADC ≤ 666 Hz)
24
24
±20
See Table 27
Chop on, ADC = 1 V
Rev. PrC | Page 4 of 96
Preliminary Technical Data
Parameter
ADC SPECIFICATIONS: ANALOG
INPUT
Main Channel
Absolute Input Voltage
Range
Input Voltage Range
Input Leakage Current1
Input Offset Current1, 11
Common-Mode Rejection DC1
On ADC
Common-Mode Rejection
50/60 Hz1
Normal-Mode Rejection
50/60 Hz1
On ADC
Aux Channel
Absolute Input Voltage
Range1
Input Voltage Range
Input Current
Common-Mode Rejection DC1
On ADC
Common-Mode Rejection
50/60 Hz1
Normal-Mode Rejection
50/60 Hz1
On ADC
VOLTAGE REFERENCE
ADC Precision Reference
Internal VREF
Initial Accuracy1
Reference Temperature
Coefficient1, 12
Power Supply Rejection
ADuC7060/ADuC7061
Test Conditions/Comments
Chop off, ADC = 1 V
Internal VREF = 1.2 V
Min
Applies to both VIN+ and VIN−
0.1
Typ
80
Max
Unit
dB
VDD − 0.7
V
Gain = 11
Gain = 2 10
Gain = 410
Gain = 8
Gain = 16
Gain = 32
Gain = 64
Gain = 128
1.2
600
300
150
75
37.5
18.75
9.375
V
mV
mV
mV
mV
mV
mV
mV
ADC0/ADC1
ADC2/ADC3/ADC4/ADC5
ADC6/ADC7/ADC8/ADC9
10
15
15
0.5
nA
nA
nA
nA
113 95
dB
dB
ADC = 7.8 mV
ADC = 1 V1
50/60 Hz ± 1 Hz, 16.6 Hz and 50 Hz
update rate, chop on
ADC = 7.8 mV, range ± 20 mV
ADC = 1 V, range ±1.2 V
95 113
95
90
dB
dB
50/60 Hz ± 1 Hz, 16.6Hz fADC, chop
on
50/60 Hz ± 1 Hz, 16.6Hz fADC, chop
off
75
dB
67
dB
Buffer enabled
0.1
Buffer disabled
Range based reference source
AGND
AVDD − 0.1
V
AVDD
0 − 1.2
5.5
V
μA
95
dB
ADC = 1 V1
50/60 Hz ± 1 Hz, 16.6 Hz and 50 Hz
update rate, chop on
ADC = 7.8 mV, range ± 20 mV
ADC = 1 V, range ± 1.2 V
95
90
dB
dB
50/60 Hz ± 1 Hz, 16.6 Hz fADC, chop on
50/60 Hz ± 1 Hz, 16.6 Hz fADC, chop off
75
67
dB
dB
Measured at TA = 25°C
−0.06
−20
1.2
±10
70
Rev. PrC | Page 5 of 96
+0.06
+20
V
%
ppm/°C
dB
ADuC7060/ADuC7061
Parameter
External Reference Input
Range 13
VREF Divide by 2 Initial Error1
DAC CHANNEL SPECIFICATIONS
Voltage Range
12-BIT MODE
DC Specifications 14
Resolution
Relative Accuracy
Differential Nonlinearity
Offset Error
Gain Error
Preliminary Technical Data
Test Conditions/Comments
Min
0.1
Typ
%
0 − VREF
0 − AVDD
V
V
RL = 5 kΩ, CL = 100 pF
12
±2
±0.2
±2
Guaranteed monotonic
1.2 V internal reference
VREF range (reference = 1.2 V)
AVDD range
TEMPERATURE SENSOR 16
Accuracy
Thermal Impedance
POWER-ON RESET (POR)
POR Trip Level
RESET Timeout from POR
EXCITATION CURRENT SOURCES
Output Current
Initial Tolerance at 25°C
Drift
Initial Current matching at
25°C
Drift matching
Line Regulation (AVDD)
Output Compliance1
±1
±15
±1
±1
0.1
14
For 14-bit resolution
Guaranteed monotonic (14 bits)
1.2 V internal reference
VREF range (reference = 1.2 V)
AVDD range
±3
±0.5
±2
Gain Error Mismatch
DAC AC CHARACTERISTICS
Voltage Output Settling Time
Digital-to-Analog Glitch Energy
Unit
V
0.1
Gain Error Mismatch
16-BIT MODE
DC Specifications 15
Resolution
Relative Accuracy
Differential Nonlinearity
Offset Error
Gain Error
Max
AVDD
1 LSB change at major carry (where
maximum number of bits
simultaneously change in the
DACxDAT register)
After user calibration
MCU in power down or standby
mode
32-lead LFCSP
48-lead LFCSP
48-lead LFQFP
Refers to voltage at VDD pin
Power-on level
Power-down level
Maximum supply ramp between
1.8 V to 2.25 V; after POR trip, VDD
must reach 2.25 V within this time
limit
Available from each current source
±1
±15
±1
±1
0.1
Matching between both current
sources
AVDD = 2.5 V ± 5%
AVDD − 0.7
Rev. PrC | Page 6 of 96
Bits
LSB
LSB
mV
%
%
% of full scale
on DAC
10
±20
μs
nV-sec
±4
°C
TBD
TBD
TBD
°C/W
°C/W
°C/W
2.0
2.25
V
V
ms
128
200
Bits
LSB
LSB
mV
%
%
% of full scale
on DAC
1000
±5
200
±0.5
μA
%
ppm/°C
%
20
0.2
ppm/°C
%/V
V
AGND − 30 mV
Preliminary Technical Data
Parameter
WATCHDOG TIMER (WDT)
Timeout Period1
Timeout Step Size
FLASH/EE MEMORY1
Endurance 17
Data Retention 18
DIGITAL INPUTS
Input Leakage Current
Input Pull-up Current
Input Capacitance
Input Leakage Current
Input Pull-Down Current
LOGIC INPUTS1
VINL, Input Low Voltage
VINH, Input High Voltage
CRYSTAL OSCILLATOR1
Logic Inputs, XTAL1 Only
VINL, Input Low Voltage
VINH, Input High Voltage
XTAL1 Capacitance
XTAL2 Capacitance
ON-CHIP OSCILLATORS
Oscillator
Accuracy
MCU CLOCK RATE
MCU START-UP TIME
At Power-On
After Reset Event
From MCU Power-Down
PLL On
Wakeup from Interrupt
PLL Off
Wakeup from Interrupt
Internal PLL Lock Time
POWER REQUIREMENTS
Power Supply Voltages
DVDD (±5%)
AVDD (±5%)
Power Consumption
IDD (MCU Normal Mode) 19
IDD (MCU Powered Down)
IDD (Primary ADC)
IDD (Aux ADC)
ADuC7060/ADuC7061
Test Conditions/Comments
Min
32.768 kHz clock, 256 prescale
0.008
Typ
Max
Unit
512
sec
ms
7.8
10,000
20
All digital inputs except NTRST
Input (high) = DVDD
Input (low) = 0 V
NTRST only: input (low) = 0 V
NTRST only: input (high) = DVDD
All logic inputs
10
30
Cycles
Years
±1
20
10
±1
55
±10
80
±10
100
0.4
V
V
0.8
V
V
pF
pF
2.0
1.7
12
12
32,768
8 programmable core clock
selections within this range (binary
divisions 1, 2, 4, 8 . . . 64, 128)
−3
0.160
Includes kernel power-on execution
time
Includes kernel power-on execution
time
2.375
2.375
MCU clock rate = 10.24 MHz, ADC
on
MCU clock rate = 1.28 MHz, ADC on,
DAC off
PGA enabled, normal mode/low
power mode
Normal mode/low power mode
1
2.56
Rev. PrC | Page 7 of 96
+3
10.24
kHz
%
MHz
134
ms
5
ms
13
μs
100
1
μs
ms
2.5
2.5
2.625
2.625
V
V
10
TBC
mA
2.8
mA
175
μA
mA
120
1.2/0.3
0.3/0.1
These numbers are not production tested, but are guaranteed by design and/or characterization data at production release.
Valid for primary ADC gain setting of PGA = 4 to 64.
3
Tested at gain range = 4 after initial offset calibration.
2
μA
μA
pF
μA
μA
mA
ADuC7060/ADuC7061
Preliminary Technical Data
4
Measured with an internal short. A System zero-scale calibration will remove this error.
Measured with an internal short.
6
These numbers do not include internal reference temperature drift.
7
Factory calibrated at gain = 1.
8
System calibration at specific gain range removes the error at this gain range.
9
Measured using external reference.
10
Limited by minimum absolute input voltage range.
11
Valid for a differential input less than 10 mV.
12
Measured using the box method.
13
References up to AVDD are accommodated by setting ADC0CON Bit 12.
14
Reference DAC linearity is calculated using a reduced code range of 171 to 4095.
15
Reference DAC linearity is calculated using a reduced code range of 2731 to 65,535.
16
Die temperature.
17
Endurance is qualified to 10,000 cycles as per JEDEC Std. 22 Method A117 and measured at −40°C, +25°C, and +125°C. Typical endurance at 25°C is 170,000 cycles.
18
Retention lifetime equivalent at junction temperature (TJ) = 85°C as per JEDEC Std. 22 Method A117. Retention lifetime derates with junction temperature.
19
Typical, additional supply current consumed during Flash/EE memory program and erase cycles is 7 mA and 5 mA, respectively.
5
TIMING SPECIFICATIONS
Data not ready yet.
Rev. PrC | Page 8 of 96
Preliminary Technical Data
ADuC7060/ADuC7061
ABSOLUTE MAXIMUM RATINGS
TA = −40°C to +125°C, unless otherwise noted.
Table 2.
Parameter
AGND to DGND to VSS to IO_VSS
Digital I/O Voltage to DGND
VREF to AGND
ADC Inputs to AGND
ESD (Human Body Model) Rating
All Pins
Storage Temperature
Junction Temperature
Transient
Continuous
Lead Temperature, Soldering
Reflow (15 sec)
Rating
−0.3 V to +0.3 V
−0.3 V to DVDD + 0.3 V
−0.3 V to AVDD + 0.3 V
−0.3 V to AVDD + +0.3 V
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
±2 kV
125°C
ESD CAUTION
150°C
130°C
260°C
Rev. PrC | Page 9 of 96
ADuC7060/ADuC7061
Preliminary Technical Data
48
47
46
45
44
43
42
41
40
39
38
37
TCK
TDI
TDO
NTRST
DVDD
DGND
P2.1/PWM5/IRQ3
P1.6/PWM4
P1.5/PWM3
P1.4/PWM2
P0.2/IRQ2/PWM0
P0.4/PWM1/IRQ0
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
PIN 1
INDICATOR
ADuC7060
TOP VIEW
(Not to Scale)
36
35
34
33
32
31
30
29
28
27
26
25
XTAL2
XTAL1
P0.3/MOSI/SDA
P2.0/MISO
P0.1/SCLK/SCL
P0.0/SS
DVDD
DGND
ADC9
ADC8
ADC7
ADC6
NOTES
1. NC = NO CONNECT.
2. THE LFCSP_VQ HAS AN EXPOSED PADDLE THAT MUST BE CONNECTED TO GND.
07079-002
ADC4/EXT_REF2IN+
ADC3
ADC2
IEXC1
IEXC0
GND_SW
ADC1
ADC0
VREF+
VREF−
AGND
AVDD
13
14
15
16
17
18
19
20
21
22
23
24
RESET 1
TMS 2
P1.0/IRQ1/SIN/T0 3
P1.1/SOUT 4
P1.2/SYNC 5
P1.3/TRIP 6
P0.5 7
P0.6 8
DVDD 9
DGND 10
DAC0 11
ADC5/EXT_REF2IN− 12
Figure 2. 48-Lead LQFP and 48-Lead LFCSP Pin Configuration
Table 3. Pin Function Descriptions (48-Lead LQFP and 48-Lead LFCSP)
Pin No.
1
2
Mnemonic
RESET
TMS
Type1
I
I
3
P1.0/IRQ1/SIN/T0
I/O
4
P1.1/SOUT
I/O
5
P1.2/SYNC
I/O
6
P1.3/TRIP
I/O
7
8
9
10
11
12
P0.5/CTS
P0.6/RTS
DVDD
DGND
DAC0
ADC5/EXT_REF2IN−
I/O
I/O
S
S
O
I
13
ADC4/EXT_REF2IN+
I
14
15
16
17
ADC3
ADC2
IEXC1
IEXC0
I
I
O
O
Description
Reset. Input pin, active low. An external 1 kΩ pull-up resistor is recommended with this pin.
JTAG Test Mode Select. Input pin. Used for debug and download. An external pull-up resistor
(~100 kΩ) should be added this pin.
General-Purpose Input and Output P1/External Interrupt Request 1/Serial Input Pin 0/Timer 0
input. This pin is a multifunction input/output pin offering four functions.
General-Purpose Input and General-Purpose Output P1.1/Serial Output. This is a dual function
input/output pin.
General-Purpose Input and General-Purpose Output P1.2/PWM External Sync Input. This is a dual
function input/output pin.
General-Purpose Input and General-Purpose Output P1.3/PWM External Trip Input. This is a dual
function input/output pin.
General-Purpose Input and General-Purpose Output P0.5/Clear to Send Signal in UART Mode.
General-Purpose Input and General-Purpose Output P0.6. Request to Send Signal in UART Mode.
Digital Supply Pin.
Digital Ground.
DAC Output. Analog output pin.
Single-Ended or Differential Analog Input 5/External Reference Negative Input. This is a dual
function analog input pin. The ADC5 serves as the analog input for the auxiliary ADC. The
EXT_REF2IN− serves as the external reference negative input by ADC for the auxiliary channel.
Multifunction Analog Input Pin. This pin can be used for the single-ended or differential Analog
Input 4, which is the analog input for the auxiliary ADC, or it can be used for the external
reference positive input for the auxiliary channel.
Single-Ended or Differential Analog Input 3. Analog input for the auxiliary ADC.
Single-Ended or Differential Analog Input 2. Analog input for the auxiliary ADC.
Programmable Current Source. Analog output pin.
Programmable Current Source. Analog output pin.
Rev. PrC | Page 10 of 96
Preliminary Technical Data
Pin No.
18
Mnemonic
GND_SW
Type1
I
19
20
21
22
23
24
25
26
27
28
29
30
31
ADC1
ADC0
VREF+
VREF−
AGND
AVDD
ADC6
ADC7
ADC8
ADC9
DGND
DVDD
P0.0/SS
I
I
I
I
S
S
I
I
I
I
S
S
I/O
32
P0.1/SCLK/SCL
I/O
33
P0.2/MISO
I/O
34
P0.3/MOSI/SDA
I/O
35
36
37
XTAL1
XTAL2
P0.4/PWM1/IRQ0
O
I
I/O
38
P2.0/IRQ2/PWM0
I/O
39
P1.4/PWM2
I/O
40
P1.5/PWM3
I/O
41
P1.6/PWM4
I/O
42
P2.1/PWM5/IRQ3
I/O
43
44
45
46
47
DGND
DVDD
NTRST
TDO
TDI
S
S
I
O
I
48
TCK
I
1
ADuC7060/ADuC7061
Description
Switch to Internal Analog Ground Reference. When this input pin is not used, connect it directly
to the AGND system ground.
Positive Differential Input for Primary ADC. Analog input pin.
Negative Differential Input for Primary ADC. Analog input pin.
External Reference Positive Input for the Primary Channel. Analog input pin.
External Reference Negative Input for the Primary Channel. Analog input pin.
Analog Ground.
Analog Supply Pin.
Analog Input 6 for Auxiliary ADC. Analog input pin.
Analog Input 7 for Auxiliary ADC. Analog input pin.
Analog Input 8 for Auxiliary ADC. Analog input pin.
Analog Input 9 for Auxiliary ADC. Analog input pin.
Digital Ground.
Digital Supply Pin.
General-Purpose Input and General-Purpose Output P0.0/SPI slave select pin. Active low. This is a
dual function input/output pin.
General-Purpose Input and General-Purpose Output P0.1/ SPI Clock Pin/ I2C Clock Pin. This is a trifunction input/output pin.
General-Purpose Input and General-Purpose Output P0.2/SPI Master Input or Slave Output. This
is a dual function input/output pin.
General-Purpose Input and General-Purpose Output P0.3/ SPI Master Output or Slave Input/I2C
Data Pin. This is a tri-function input/output pin.
External Crystal Oscillator Output Pin.
External Crystal Oscillator Input Pin.
General-Purpose Input and General-Purpose Output P0.4/ External Interrupt Request 0/PWM1
Output. This is a tri-function input/output pin.
General-Purpose Input and General-Purpose Output P2.0/External Interrupt Request 2/PWM0
Output. This is a tri-function input/output pin.
General-Purpose Input and General-Purpose Output P1.4/PWM2 Output. This is a dual function
input/output pin.
General-Purpose Input and General-Purpose Output P1.5/PWM3 Output. This is a dual function
input/output pin.
General-Purpose Input and General-Purpose Output P1.6/PWM4 Output. This is a dual function
input/output pin.
General-Purpose Input and General-Purpose Output P2.1/ PWM5 Output/External Interrupt
Request 3. This is a tri-function input/output pin.
Digital Ground.
Digital Supply Pin.
JTAG Reset. Input pin used for debug and download only.
JTAG Data Out. Output pin used for debug and download only.
JTAG Data In. Input pin used for debug and download only. Add an external pull-up resistor
(~100 kΩ) to this pin.
JTAG Clock Pin. Input pin used for debug and download only. Add an external pull-up resistor
(~100 kΩ) to this pin.
I = input, O = output, S = supply.
Rev. PrC | Page 11 of 96
Preliminary Technical Data
32
31
30
29
28
27
26
25
TCK
TDI
TDO
NTRST
DVDD
DGND
P2.0/IRQ2/PWM0
P0.4/IRQ0/PWM1
ADuC7060/ADuC7061
1
2
3
4
5
6
7
8
PIN 1
INDICATOR
ADuC7061
TOP VIEW
(Not to Scale)
24
23
22
21
20
19
18
17
XTAL2
XTAL1
P0.3/MOSI/SDA/ADC9
P0.2/MISO/ADC8
P0.1/SCLK/SCL/ADC7
P0.0/SS/ADC6
VREF–
VREF+
NOTES
1. NC = NO CONNECT.
2. THE LFCSP_VQ HAS AN EXPOSED PADDLE THAT MUST BE CONNECTED
TO GND.
07079-003
ADC2
IEXC1
IEXC0
GND_SW
ADC1
ADC0
AGND
AVDD
9
10
11
12
13
14
15
16
RESET
TMS
P1.0/IRQ1/SIN/T0
P1.1/SOUT
DAC0
ADC5/EXT_REF2IN−
ADC4/EXT_REF2IN+
ADC3
Figure 3. 32-Lead LFCSP Pin Configuration
Table 4. Pin Function Descriptions ADuC7061 32-Lead LFCSP
Pin No.
1
2
Mnemonic
RESET
TMS
Type 1
I
I
3
P1.0/IRQ1/SIN/T0
I/O
4
P1.1/SOUT
I/O
5
6
DAC0
ADC5/EXT_REF2IN−
O
I
7
ADC4/EXT_REF2IN+
I
8
9
10
11
12
ADC3
ADC2
IEXC1
IEXC0
GND_SW
I
I
O
O
I
13
14
15
16
17
18
19
ADC1
ADC0
AGND
AVDD
VREF+
VREF−
P0.0/SS/ADC6
I
I
S
S
I
I
I/O
20
P0.1/SCLK/SDA/ADC7
I/O
Description
Reset Pin. Input pin, active low. An external 1 kΩ pull-up resistor is recommended with this pin.
JTAG Test Mode Select. Input pin used for debug and download. An external pull-up resistor
(~100 kΩ) should be added this pin.
Multifunction Input/Output Pin:
General-Purpose Input and General-Purpose Output P1.0.
External interrupt Request 1.
Serial Input.
Timer 0 Input.
Multifunction Input/Output Pin:
General-Purpose Input and General-Purpose Output P1.1.
Serial Output.
DAC Output. Analog output pin.
Multifunction Analog Input Pin:
Single-Ended or Differential Analog Input 5. Analog input for auxiliary ADC.
External Reference Negative Input for the Auxiliary Channel.
Multifunction Analog Input Pin:
Single-ended or Differential Analog Input 4. Analog input for auxiliary ADC.
External Reference Positive Input for the Auxiliary Channel.
Single-Ended or Differential Analog Input 3. Analog input for auxiliary ADC.
Single-Ended or Differential Analog Input 2. Analog input for auxiliary ADC.
Programmable Current Source. Analog output pin.
Programmable Current Source. Analog output pin.
Switch to Internal Analog Ground Reference. When this input pin is not used, connect it directly
to the AGND system ground.
Positive Differential Input for Primary ADC. Analog input pin.
Negative Differential Input for Primary ADC. Analog input pin.
Analog Ground.
Analog Supply Pin.
External Reference Positive Input for the Primary Channel. Analog input pin.
External Reference Negative Input for the Primary Channel. Analog input pin.
Multifunction Input/Output Pin. General-Purpose Input and General-Purpose Output P0.0/ SPI
Slave Select (active low)/Input to Auxiliary ADC6.
Multifunction Input/Output Pin. General-Purpose Input and General-Purpose Output P0.1/SPI
Rev. PrC | Page 12 of 96
Preliminary Technical Data
Pin No.
Mnemonic
Type 1
21
P0.2/MISO/ADC8
I/O
22
P0.3/MOSI/SDA/ADC9
I/O
23
24
25
XTAL1
XTAL2
P0.4/IRQ0/PWM1
O
I
I/O
26
P2.0/IRQ2/PWM0
I/O
27
28
29
30
31
DGND
DVDD
NTRST
TDO
TDI
S
S
I
O
I
32
TCK
I
1
ADuC7060/ADuC7061
Description
clock/ I2C clock/ Input to Auxiliary ADC7.
Multifunction Input/Output Pin. General-Purpose Input and General-Purpose Output P0.2/SPI
master input or slave output/Auxiliary ADC8 input.
Multifunction Input/Output Pin. General-Purpose Input and General-Purpose Output P0.3/SPI
master output or slave input/I2C data pin/Auxiliary ADC ADC9 input.
External Crystal Oscillator Output Pin.
External Crystal Oscillator Input Pin.
Multifunction Input/Output Pin. General-Purpose Input and General-Purpose Output
P0.4/WM1 output.
Multifunction Input/Output Pin. General-Purpose Input and General-Purpose Output
P2.0/External Interrupt Request 2/PWM0 output.
Digital Ground.
Digital Supply Pin.
JTAG Reset. Input pin used for debug and download only.
JTAG Data Out. Output pin used for debug and download only.
JTAG Data In. Input pin used for debug and download only. An external pull-up resistor
(~100 kΩ) should be added this pin.
JTAG Clock. Input pin used for debug and download only. An external pull-up resistor (~100
kΩ) should be added this pin.
I = input, O = output, S = supply.
Rev. PrC | Page 13 of 96
ADuC7060/ADuC7061
Preliminary Technical Data
TERMINOLOGY
Conversion Rate
The conversion rate specifies the rate at which an output result
is available from the ADC, once the ADC has settled.
The sigma-delta (Σ-Δ) conversion techniques used on this part
mean that while the ADC front-end signal is over sampled at a
relatively high sample rate, a subsequent digital filter is used to
decimate the output giving a valid 24-bit data conversion result
at output rates from 1 Hz to 8 kHz.
Note that when software switches from one input to another
(on the same ADC), the digital filter must first be cleared and
then allowed to average a new result. Depending on the configuration of the ADC and the type of filter, this can take
multiple conversion cycles.
Integral Nonlinearity (INL)
INL is the maximum deviation of any code from a straight line
passing through the endpoints of the transfer function. The
endpoints of the transfer function are zero scale, a point ½ LSB
below the first code transition, and full scale, a point ½ LSB
above the last code transition (111 . . . 110 to 111 . . . 111).
The error is expressed as a percentage of full scale.
No Missing Codes
No missing codes is a measure of the differential nonlinearity
of the ADC. The error is expressed in bits and specifies the
number of codes (ADC results) as 2N bits, where is N = no
missing codes, guaranteed to occur through the full ADC
input range.
Offset Error
Offset error is the deviation of the first code transition ADC
input voltage from the ideal first code transition.
Offset Error Drift
Offset error drift is the variation in absolute offset error with
respect to temperature. This error is expressed as LSBs per °C.
Output Noise
The output noise is specified as the standard deviation (or 1 ×
Sigma) of ADC output codes distribution collected when the
ADC input voltage is at a dc voltage. It is expressed as μ rms.
The output, or rms noise, can be used to calculate the effective
resolution of the ADC as defined by the following equation:
Effective Resolution = log2(Full-Scale Range/rms Noise) bits
The peak-to-peak noise is defined as the deviation of codes that
fall within 6.6 × Sigma of the distribution of ADC output codes
collected when the ADC input voltage is at dc. The peak-topeak noise is, therefore calculated as 6.6 × the rms noise.
The peak-to-peak noise can be used to calculate the ADC
(noise free code) resolution for which there is no code flicker
within a 6.6-Sigma limit as defined by the following equation:
Noise Free Code Resolution =
⎛ Full − ScaleRange ⎞
log2 ⎜
⎟ bits
⎝ Peak − to − PeakNoise ⎠
Data Sheet Acronyms
ADC
ARM
JTAG
LSB
LVF
MCU
MMR
MSB
PID
POR
PSM
rms
Gain Error
Gain error is a measure of the span error of the ADC. It is a
measure of the difference between the measured and the ideal
span between any two points in the transfer function.
Rev. PrC | Page 14 of 96
analog-to-digital converter
advanced RISC machine
joint test action group
least significant byte/bit
low voltage flag
microcontroller
memory mapped register
most significant byte/bit
protected identifier
power-on reset
power supply monitor
root mean square
Preliminary Technical Data
ADuC7060/ADuC7061
OVERVIEW OF THE ARM7TDMI CORE
The ARM7 core is a 32-bit, reduced instruction set computer
(RISC), developed by ARM® Ltd. The ARM7TDMI is a
von Neumann-based architecture, meaning that it uses a single
32-bit bus for instruction and data. The length of the data can
be 8, 16, or 32 bits and the length of the instruction word is
either 16 bits or 32 bits, depending on the mode in which the
core is operating.
The ARM7TDMI is an ARM7 core with four additional
features, as listed in Table 5.
Description
Support for the Thumb® (16-bit) instruction set
Support for debug
Enhanced multiplier
Includes the EmbeddedICE™ module to support
embedded system debugging
Attempted execution of an undefined instruction.
Software interrupts (SWI) instruction that can be used to make
a call to an operating system.
An ARM instruction is 32 bits long. The ARM7TDMI processor
supports a second instruction set compressed into 16 bits, the
Thumb instruction set. Faster code execution from 16-bit memory
and greater code density is achieved by using the Thumb instruction set, making the ARM7TDMI core particularly suited for
embedded applications.
However, the Thumb mode has three limitations.
•
•
Normal interrupt or IRQ. This is provided to service generalpurpose interrupt handling of internal and external events.
Note, that the ADuC7060 supports 8 configurable priority levels
for all IRQ sources.
Memory abort (prefetch and data).
THUMB MODE (T)
•
The ARM7 supports five types of exceptions, with a privileged
processing mode associated with each type. The five types of
exceptions are as follows:
Fast interrupt or FIQ. This is provided to service data transfer
or a communication channel with low latency.
FIQ has priority over IRQ. Note, that the ADuC7060 supports 8
configurable priority levels for all FIQ sources.
Table 5. ARM7TDMI
Feature
T
D
M
I
ARM7 Exceptions
Relative to ARM, the Thumb code usually requires more
instructions to perform that same task. Therefore, ARM
code is best for maximizing the performance of timecritical code in most applications.
The Thumb instruction set does not include some
instructions that are needed for exception handling, so
ARM code can be required for exception handling.
When an interrupt occurs, the core vectors to the interrupt
location in memory and executes the code present at that
address. The first command is required to be in ARM code.
MULTIPLIER (M)
The ARM7TDMI instruction set includes an enhanced
multiplier, with four extra instructions to perform 32-bit by
32-bit multiplication with a 64-bit result, and 32-bit by 32-bit
multiplication-accumulation (MAC) with a 64-bit result.
EMBEDDED ICE (I)
The EmbeddedICE module provides integrated on-chip debug
support for the ARM7TDMI. The EmbeddedICE module
contains the breakpoint and watchpoint registers that allow
nonintrusive user code debugging. These registers are controlled through the JTAG test port. When a breakpoint or
watchpoint is encountered, the processor halts and enters the
debug state. Once in a debug state, the processor registers can
be interrogated, as can the Flash/EE, SRAM, and memory
mapped registers.
Typically, the programmer defines interrupts as IRQ, but for
higher priority interrupts, the programmer can define
interrupts as the FIQ type.
The priority of these exceptions and vector address are listed in
Table 6.
Table 6. Exception Priorities and Vector Addresses
Priority
1
2
3
4
5
6
6
1
Exception
Hardware reset
Memory abort (data)
FIQ
IRQ
Memory abort (prefetch)
Software Interrupt1
Undefined Instruction1
Address
0x00
0x10
0x1C
0x18
0x0C
0x08
0x04
A software interrupt and an undefined instruction exception have the same
priority and are mutually exclusive.
The list of exceptions in Table 6 are located from 0x00 to 0x1C,
with a reserved location at 0x14.
ARM REGISTERS
The ARM7TDMI has 16 standard registers. R0 to R12 are for
data manipulation, R13 is the stack pointer, R14 is the link
register, and R15 is the program counter that indicates the
instruction currently being executed. The link register contains
the address from which the user has branched (if the branch
and link command was used) or the command during which an
exception occurred.
The stack pointer contains the current location of the stack.
Generally, on an ARM7TDMI, the stack starts at the top of the
available RAM area and descends using the area as required. A
separate stack is defined for each of the exceptions. The size of
each stack is user configurable and is dependent on the target
application. When programming using high level languages,
Rev. PrC | Page 15 of 96
ADuC7060/ADuC7061
Preliminary Technical Data
such as C, it is necessary to ensure that the stack does not
overflow. This is dependent on the performance of the compiler
that is used.
The minimum latency for FIQ or IRQ interrupts is five cycles.
This consists of the shortest time the request can take through
the synchronizer plus the time to enter the exception mode.
When an exception occurs, some of the standard registers are
replaced with registers specific to the exception mode. All
exception modes have replacement banked registers for the
stack pointer (R13) and the link register (R14) as represented
in Figure 4. The FIQ mode has more registers (R8 to R12)
supporting faster interrupt processing. With the increased
number of noncritical registers, the interrupt can be processed
without the need to save or restore these registers, thereby
reducing the response time of the interrupt handling process.
Note that the ARM7TDMI initially (first instruction) runs in
ARM (32-bit) mode when an exception occurs. The user can
immediately switch from ARM mode to Thumb mode if
required, for example, when executing interrupt service
routines.
MEMORY ORGANIZATION
More information relative to the programmer’s model and the
ARM7TDMI core architecture can be found in ARM7TDMI
technical and ARM architecture manuals available directly from
ARM Ltd.
USABLE IN USER MODE
R0
R1
SYSTEM MODES ONLY
R2
R3
R5
The ADuC706x memory organization is configured in little
endian format: the least significant byte is located in the lowest
byte address and the most significant byte in the highest byte
address. See Figure 6 for details.
R6
R10
R11
R12
R13
R14
R9_FIQ
R10_FIQ
R11_FIQ
R12_FIQ
R13_FIQ
R14_FIQ
R13_SVC
R14_SVC
R13_IRQ
R13_ABT
R14_IRQ
R14_ABT
R13_UND
0xFFFFFFFF
R14_UND
RESERVED
R15 (PC)
USER MODE
0x00087FFF
SPSR_FIQ
SPSR_SVC
FIQ
MODE
SVC
MODE
SPSR_ABT
SPSR_IRQ
FLASH/EE
SPSR_UND
0x00080000
RESERVED
ABORT
MODE
IRQ
MODE
UNDEFINED
MODE
07079-004
CPSR
MMRs
0xFFFF0000
0x00040FFF
SRAM
0x00040000
Figure 4. Register Organization
RESERVED
INTERRUPT LATENCY
0x00007FFF
The worst-case latency for an FIQ consists of the longest time
the request can take to pass through the synchronizer, plus the
time for the longest instruction to complete (the longest
instruction is an LDM) that loads all the registers including the
PC, plus the time for the data abort entry, plus the time for FIQ
entry. At the end of this time, the ARM7TDMI is executing the
instruction at 0x1C (FIQ interrupt vector address). The
maximum total time is 50 processor cycles, or just over 4.88 μs
in a system using a continuous 10.24 MHz processor clock. The
maximum IRQ latency calculation is similar, but must allow for
the fact that FIQ has higher priority and could delay entry into
the IRQ handling routine for an arbitrary length of time. This
time can be reduced to 42 cycles if the LDM command is not
used; some compilers have an option to compile without using
this command. Another option is to run the part in Thumb
mode where this is reduced to 22 cycles.
0x00000000
REMAPPABLE MEMORY SPACE
(FLASH/EE OR SRAM)
07079-005
R9
R8_FIQ
Figure 5. Memory Map
BIT 31
BIT 0
BYTE 3
.
.
.
BYTE 2
.
.
.
BYTE 1
.
.
.
BYTE 0
.
.
.
B
A
9
8
7
6
5
4
0x00000004
3
2
1
0
0x00000000
0xFFFFFFFF
32 BITS
07079-006
R8
The first 30 kB of this memory space is used as an area into
which the on-chip Flash/EE or SRAM can be remapped. Any
access, either reading or writing, to an area not defined in the
memory map results in a data abort exception.
Memory Format
R4
R7
The ARM7, a von Neumann architecture MCU core sees
memory as a linear array of 232-byte locations. As shown in
Figure 5, the ADuC7060 and the ADuC7061 map this into four
distinct user areas, namely: a memory area that can be
remapped, an SRAM area, a Flash/EE area, and a memory
mapped register (MMR) area.
Figure 6. Little Endian Format
SRAM
The ADuC7060/ADuC7061 feature 4 kB of SRAM, organized as
1024 × 32 bits, that is, 1024 words located at 0x40000.
The RAM space can be used as data memory as well as volatile
program space.
Rev. PrC | Page 16 of 96
Preliminary Technical Data
ADuC7060/ADuC7061
ARM code can run directly from SRAM at full clock speed
given that the SRAM array is configured as a 32-bit wide
memory array. SRAM is read/writeable in 8-, 16-, and 32-bit
segments.
Remap
Table 7. REMAP MMR Bit Designations
Bit
7 to 1
0
The ARM exception vectors are all situated at the bottom of the
memory array, from Address 0x00000000 to Address 0x00000020.
Description
Reserved. These bits are reserved and should be written
as 0 by user code.
Remap Bit.
Set by the user to remap the SRAM to 0x00000000.
Cleared automatically after reset to remap the Flash/EE
memory to 0x00000000.
By default, after a reset, the Flash/EE memory is logically
mapped to Address 0x00000000.
FLASH/EE CONTROL INTERFACE
It is possible to logically remap the SRAM to Address 0x00000000
by setting Bit 0 of the SYSMAP0 MMR located at 0xFFFF0220.
To revert Flash/EE to 0x00000000, Bit 0 of REMAP is cleared.
Serial and JTAG programming use the Flash/EE control
interface, which includes the eight MMRs outlined in this
section.
It is sometimes desirable to remap RAM to 0x00000000 to
optimize the interrupt latency of the ADuC706x because code
can run in full 32-bit ARM mode and at maximum core speed.
Note that when an exception occurs, the core defaults to ARM
mode.
FEESTA Register
Remap Operation
When a reset occurs on the ADuC706x, execution starts
automatically in the factory programmed internal configuration
code. This so-called kernel is hidden and cannot be accessed by
user code. If the ADuC706x is in normal mode, it executes the
power-on configuration routine of the kernel and then jumps to
the reset vector, Address 0x00000000, to execute the user’s reset
exception routine. Because the Flash/EE is mirrored at the
bottom of the memory array at reset, the reset routine must
always be written in Flash/EE.
The remap command must be executed from the absolute
Flash/EE address, and not from the mirrored, remapped
segment of memory, as this may be replaced by SRAM. If a
remap operation is executed while operating code from the
mirrored location, prefetch/data aborts can occur or the user
can observe abnormal program operation.
Any kind of reset logically remaps the Flash/EE memory to the
bottom of the memory array.
REMAP Register
FEESTA is a read-only register that reflects the status of the
flash control interface as described in Table 7.
Name:
FEESTA
Address:
0xFFFF0E00
Default value:
0x20
Access:
Read
Table 7. FEESTA MMR Bit Designations
Bit
15:6
5
4
3
2
1
0
Name:
REMAP
Address:
0xFFFF0220
Default value:
Updated by the kernel
Access:
Read/write access
Function:
This 8-bit register allows user code to remap
either RAM or Flash/EE space into the bottom
of the ARM memory space starting at Address
0x00000000.
Description
Reserved.
Reserved.
Reserved.
Flash Interrupt Status Bit. Set automatically when an
interrupt occurs, that is, when a command is complete
and the Flash/EE interrupt enable bit in the FEEMOD
register is set. Cleared when reading FEESTA register.
Flash/EE Controller Busy. Set automatically when the
controller is busy. Cleared automatically when the
controller is not busy.
Command Fail. Set automatically when a command
completes unsuccessfully. Cleared automatically when
reading the FEESTA register.
Command Pass. Set by the MicroConverter® when a
command completes successfully. Cleared
automatically when reading the FEESTA register.
FEEMOD Register
FEEMOD sets the operating mode of the flash control interface.
Table 8 shows FEEMOD MMR bit designations.
Name:
FEEMOD
Address:
0xFFFF0804
Default value:
0x0000
Access:
Read/write
Rev. PrC | Page 17 of 96
ADuC7060/ADuC7061
Preliminary Technical Data
Table 8. FEEMOD MMR Bit Designations
FEECON Register
Bit
15:9
8
7:5
FEECON is an 8-bit command register. The commands are
described in Table 9.
4
3
2:0
Description
Reserved.
Reserved. Always set this bit to 0.
Reserved. Always set these bits to 0 except when
writing keys.
Flash/EE Interrupt Enable.
Set by user to enable the Flash/EE interrupt. The
interrupt occurs when a command is complete.
Cleared by user to disable the Flash/EE interrupt.
Erase/Write Command Protection.
Set by user to enable the erase and write commands.
Cleared to protect the Flash against erase/write
command.
Reserved. Always set these bits to 0.
Name:
Address:
Default value:
Access:
FEECON
0xFFFF0808
0x0
Read/write
Table 9. Command Codes in FEECON
Code
0x001
0x011
0x021
0x031
Command
Null
Single Read
Single Write
Erase/Write
0x041
Single Verify
0x051
0x061
Single Erase
Mass Erase
0x07
0x08
0x09
0x0A
0x0B
Reserved
Reserved
Reserved
Reserved
Signature
0x0C
Protect
0x0D
0x0E
0x0F
Reserved
Reserved
Ping
1
Description
Idle State.
Load FEEDAT with the 16-bit data. Indexed by FEEADR.
Write FEEDAT at the address pointed by FEEADR. This operation takes 50 μs.
Erase the page indexed by FEEADR and write FEEDAT at the location pointed by FEEADR. This
operation takes approximately 24 ms.
Compare the contents of the location pointed by FEEADR to the data in FEEDAT. The
result of the comparison is returned in FEESTA Bit 1.
Erase the page indexed by FEEADR.
Erase 30 kB of user space. The 2 kB of kernel are protected. To prevent accidental
execution, a command sequence is required to execute this instruction. See the
Command Sequence for Executing a Mass Erase section.
Reserved.
Reserved.
Reserved.
Reserved.
This command results in a 24-bit LFSR based signature been generated and loaded into
FEESIG MMR. This operation takes 16,389 clock cycles.
This command can run only once. The value of FEEPRO is saved and removed only with a
mass erase (0x06) or the key.
Reserved.
Reserved.
No operation; interrupt generated.
The FEECON register always reads 0x07 immediately after execution of any of these commands.
Rev. PrC | Page 18 of 96
Preliminary Technical Data
ADuC7060/ADuC7061
FEEDAT Register
FEEHIDE Register
FEEDAT is a 16-bit data register. This register holds the data
value for flash read and write commands.
FEEHIDE MMR provides immediate protection. It does not
require any software key. Note that the protection settings in
FEEHIDE are cleared by a reset (see Table 10).
Name:
Address:
Default value:
Access:
FEEDAT
0xFFFF080C
0xXXXX
Read/write
Name:
Address:
Default value:
Access:
FEEADR Register
Table 10. FEEPRO and FEEHIDE MMR Bit Designations
FEEADR is a 16-bit address register used for accessing
individual pages of the 32 kB flash block. The valid address
range for a user is: 0x0000 − 0x77FF. this represents the 30 kB
flash user memory space. A read or write access outside this
boundary causes a data abort exception to occur.
Bit
31
30
Name
Address
Default value
Access
FEEADR
0xFFFF0810
0x0000
Read/write
29
28:0
FEESIGN Register
The FEESIGN register is a 24-bit MMR. This register is updated
with the 24-bit signature value after the signature command has
been executed. This value is the result of the linear feedback
shift register (LFSR )operation initiated by the signature
command.
Name:
Address:
Default value:
Access:
FEESIGN
0xFFFF0818
0xFFFFFF
Read
FEEPRO Register
FEEPRO MMR provides protection following a subsequent
reset of the MMR. It requires a software key (see Table 10).
Name:
Address:
Default value:
Access:
FEEPRO
0xFFFF081C
0x00000000
Read/write
FEEHIDE
0xFFFF0820
0xFFFFFFFF
Read/write
Description
Read Protection.
Cleared by user to protect all code. – no JTAG read
accesses for protected pages if this bit is set.
Set by user to allow reading the code via JTAG.
Protection for Page 59 (0x00087600 – 0x000877FF. Set
by user to allow writing the Page 59. Cleared to
protect Page 59.
Protection for Page 58 (0x00087400 – 0x000875FF. Set
by user to allow writing the Page 58. Cleared to
protect Page 58.
Write Protection for Page 57 to Page 0. Each bit
represents 2 pages. Each page is 512 bytes in size.
Bit0 is protection for Page 0 and Page 1 (0x00080000 –
0x000803FF. Set by the user to allow writing Page 0
and Page 1. Cleared to protect Page 0 and Page 1.
Bit1 is protection for Page 2 and Page 3 (0x00080400 –
0x000807FF. Set by the user to allow writing Page 2
and Page 3. Cleared to protect Page 2 and Page 3.
…
…
Bit27 is protection for Page 54 and Page 55
(0x00087000 – 0x000873FF. Set by the user to allow
writing Page 54 and Page 55. Cleared to protect
Page 54 and Page 55.
Bit28 is protection for Page 56 and Page 57
(0x00087400 – 0x000877FF. Set by the user to allow
writing Page 56 and Page 57. Cleared to protect
Page 56 and Page 57.
Command Sequence for Executing a Mass Erase
FEEDAT
FEEADR
FEEMOD
FEECON
Rev. PrC | Page 19 of 96
=
=
=
=
0x3CFF;
0x77C3;
FEEMOD|0x8;
0x06;
//Erase key enable
//Mass erase command
Preliminary Technical Data
MEMORY MAPPED REGISTERS
0xFFFFFFFF
The memory mapped register (MMR) space is mapped into the
upper two pages of the memory array, and accessed by indirect
addressing through the ARM7 banked registers.
0xFFFF0FC0
0xFFFF0F80
0xFFFF0E24
0xFFFF0E00
The MMR space provides an interface between the CPU and all
on-chip peripherals. All registers, except the core registers,
reside in the MMR area. All shaded locations shown in 5 are
unoccupied or reserved locations, and should not be accessed
by user software. Figure 7 shows the full MMR memory map.
The access time for reading from or writing to an MMR
depends on the advanced microcontroller bus architecture
(AMBA) bus used to access the peripheral. The processor has
two AMBA busses: advanced high performance bus (AHB)
used for system modules, and advanced peripheral bus (APB)
used for a lower performance peripheral. Access to the AHB is
one cycle, and access to the APB is two cycles. All peripherals
on the ADuC7060/ADuC7061 are on the APB except the
Flash/EE memory, the GPIOs, and the PWM.
0xFFFF0D50
0xFFFF0D00
0xFFFF0A14
0xFFFF0A00
0xFFFF0948
0xFFFF0900
0xFFFF0730
0xFFFF0700
0xFFFF0620
0xFFFF0600
0xFFFF0570
0xFFFF0500
0xFFFF0490
0xFFFF048C
0xFFFF0470
0xFFFF0450
0xFFFF0420
0xFFFF0404
0xFFFF0394
0xFFFF0380
0xFFFF0370
0xFFFF0360
0xFFFF0350
0xFFFF0340
0xFFFF0334
0xFFFF0320
0xFFFF0238
0xFFFF0220
0xFFFF0140
0xFFFF0000
PWM
FLASH CONTROL
INTERFACE
GPIO
SPI
I2C
UART
DAC
ADC
BANDGAP
REFERENCE
SPI/I2C
SELECTION
PLL AND OSCILLATOR
CONTROL
GENERAL PURPOSE
TIMER
WATCHDOG
TIMER
WAKE UP
TIMER
GENERAL PURPOSE
TIMER
REMAP AND
SYSTEM CONTROL
INTERRUPT
CONTROLLER
Figure 7. Memory Mapped Registers
Rev. PrC | Page 20 of 96
07079-007
ADuC7060/ADuC7061
Preliminary Technical Data
ADuC7060/ADuC7061
COMPLETE MMR LISTING
In the following MMR tables, addresses are listed in hex code. Access types include R for read, W for write, and RW for read and write.
Table 11. IRQ Address Base = 0xFFFF0000
Address
0x0000
0x0004
0x0008
0x000C
0x0010
0x0014
Name
IRQSTA
IRQSIG
IRQEN
IRQCLR
SWICFG
IRQBASE
Byte
4
4
4
4
4
4
Access
Type
R
R
RW
W
W
R/W
Default
Value
0x00000000
0x001C
IRQVEC
4
R
0x00000000
0x0020
IRQP0
4
R/W
0x00000000
0x0024
IRQP1
4
R/W
0x00000000
0x0028
IRQP2
4
R/W
0x00000000
0x002C
0x0030
0x0034
RESERVED
IRQCONN
IRQCONE
4
4
4
R/W
R/W
R/W
0x00000000
0x00000000
0x00000000
0x0038
0x003C
IRQCLRE
IRQSTAN
4
4
R/W
R/W
0x00000000
0x00000000
0x0100
0x0104
0x0108
0x010C
0x011C
0x013C
FIQSTA
FIQSIG
FIQEN
FIQCLR
FIQVEC
FIQSTAN
4
4
4
4
4
4
R
R
RW
W
R
R
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
Description
Active IRQ source.
Current state of all IRQ sources (enabled and disabled).
Enabled IRQ sources.
MMR to disable IRQ sources.
Software interrupt configuration MMR.
Base address of all vectors. Points to start of 64-byte memory block which
can contain up to 32 pointers to separate subroutine handlers.
This register contains the subroutine address for the currently active IRQ
source.
Contains the interrupt priority setting for interrupt Source 1 to Source 7.
An interrupt can have a priority setting of 0 to 7. For example:
Bits[7:4] containthe priority level for Interrupt 1.
Bits[11:8] contain the priority level for Interrupt 2.
Bits[31:28] contain the priority level for Interrupt 7.
Contains the interrupt priority setting for Interrupt Source 8 to Interrupt
Source 15. For example:
Bits[7:4] contain the priority level for Interrupt 9.
Bits[11:8] contain the priority level for Interrupt 10.
Bits[31:28] contain the priority level for Interrupt 15.
Contains the interrupt priority setting for Interrupt Source 16 to Interrupt
Source 19.
Reserved.
Used to enable IRQ and FIQ interrupt nesting.
Configures the external interrupt sources as either rising edge, falling
edge, or level triggered.
Used to clear an edge level triggered interrupt source.
This register indicates the priority level of an interrupt that has just
caused an interrupt exception.
Active FIQ source.
Current state of all FIQ sources (enabled and disabled).
Enabled FIQ sources.
MMR to disable FIQ sources.
FIQ interrupt vector.
Indicates the priority level of an FIQ that has just caused an FIQ
exception.
Table 12. System Control Address Base = 0xFFFF0200
Address
0x0220
0x0230
0x0234
1
Name
REMAP1
RSTSTA
RSTCLR
Byte
1
1
1
Access
Type
R/W
R/W
W
Default Value
0x00
0x01
0x00
Description
REMAP control register. See the Remap Operation section.
RSTSTA status MMR. See the Reset section.
RSTCLR MMR for clearing RSTSTA register.
Updated by kernel.
Rev. PrC | Page 21 of 96
ADuC7060/ADuC7061
Preliminary Technical Data
Table 13. Timer Address Base = 0xFFFF0300
Address
0x0320
0x0324
0x0328
0x032C
0x0330
0x0340
0x0344
0x0348
0x034C
0x0360
0x0364
0x0368
0x036C
0x0380
0x0384
0x0388
0x038C
0x0390
Name
T0LD
T0VAL
T0CON
T0CLRI
T0CAP
T1LD
T1VAL
T1CON
T1CLRI
T2LD
T2VAL
T2CON
T2CLRI
T3LD
T3VAL
T3CON
T3CLRI
T3CAP
Byte
4
4
4
1
4
4
4
2
1
2
2
2
1
2
2
4
1
2
Access
Type
RW
R
RW
W
R
RW
R
RW
W
RW
R
RW
W
RW
R
RW
W
R
Default Value
0x00000000
0xFFFFFFFF
0x01000000
N/A
0x00000000
0x00000000
0xFFFFFFFF
0x0000
N/A
0x0040
0x0040
0x0100
N/A
0x0000
0xFFFF
0x00000000
N/A
0x0000
Description
Timer0 load register.
Timer0 value register.
Timer0 control MMR.
Timer0 interrupt clear register.
Timer0 capture register.
Timer1 load register.
Timer1 value register
Timer1 control MMR.
Timer1 interrupt clear register
Timer2 load register.
Timer2 value register.
Timer2 control MMR.
Timer2 interrupt clear register.
Timer3 load register.
Timer3 value register.
Timer3 control MMR.
Timer3 interrupt clear register.
Timer3 capture register.
Table 14. PLL Base Address = 0xFFFF0400
Address
0x0404
0x0408
0x040C
0x0410
0x0414
0x0418
0x0464
0x0468
Name
POWKEY1
POWCON0
POWKEY2
PLLKEY1
PLLCON
PLLKEY2
GP0KEY1
GP0CON1
Byte
2
1
4
4
1
4
4
1
Access
Type
W
RW
W
W
RW
W
R/W
R/W
Default Value
N/A
0x7B
N/A
N/A
0x00
N/A
0x00
0x00
0x046C
GP0KEY2
4
R/W
0x00
Description
POWCON prewrite key
Power control and core speed control register.
POWCON postwrite key.
PLLCON prewrite key.
PLL Clock source selection MMR.
PLLCON postwrite key.
GP0CON1 prewrite key.
Configures P0.0, P0.1, P0.2, and P0.3 as analog inputs or digital I/Os. Also
enables SPI or I2C mode.
GP0CON1 postwrite key.
Rev. PrC | Page 22 of 96
Preliminary Technical Data
ADuC7060/ADuC7061
Table 15. ADC Address Base = 0xFFFF0500
Address
0x0500
0x0504
0x0508
0x050C
0x0510
0x0514
0x0518
0x051C
0x0520
0x0524
0x0528
0x052C
0x0530
Name
ADCSTA
ADCMSKI
ADCMDE
ADC0CON
ADC1CON
ADCFLT
ADCCFG
ADC0DAT
ADC1DAT
ADC0OF1
ADC1OF1
ADC0GN1
ADC1GN1
Byte
2
2
2
2
2
2
2
4
4
2
2
2
2
Access
Type
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Default Value
0x0000
0x0000
0x0003
0x8000
0x0000
0x0007
0x0000
0x00000000
0x00000000
0x0000
0x0000
0x5555
0x5555
0x0534
0x0538
0x053C
0x0540
0x0544
0x0548
0x054C
0x0570
ADCORCR
ADCORCV
ADCOTH
ADCOTHC
ADCOTHV
ADCOACC
ADCOATH
IEXCON
2
2
2
2
2
4
4
1
R/W
R
R/W
R/W
R/W
R/W
R/W
R/W
0x0001
0x0000
0x0000
0x0001
0x0000
0x00000000
0x00000000
0x00
1
Description
ADC status MMR.
ADC interrupt source enable MMR.
ADC mode register.
Primary ADC control MMR.
Auxiliary ADC control MMR.
ADC filter control MMR.
ADC configuration MMR.
Primary ADC result MMR.
Auxiliary ADC result MMR
Primary ADC offset calibration setting.
Auxiliary ADC offset MMR.
Primary ADC offset MMR.
Auxiliary ADC offset MMR. See the ADC operation mode configuration bit
(ADCLPMCFG[1:0]) in Table 35.
Primary ADC Result counter/reload MMR.
Primary ADC Result counter MMR.
Primary ADC 16-bit comparator threshold MMR.
Primary ADC 16-bit comparator threshold counter limit.
Primary ADC accumulator.
Primary ADC 32-bit comparator threshold MMR.
Excitation current sources control register.
Updated by kernel.
Table 16. DAC Control Address Base = 0xFFFF0600
Address
0x0600
0x0604
Name
DAC0CON
DAC0DAT
Byte
2
4
Access
Type
R/W
R/W
Default Value
0x0200
0x00000000
Description
DAC control register.
DAC output data register.
Table 17. UART Base Address = 0xFFFF0700
Address
0x0700
0x0700
0x0700
0x0704
0x0704
0x0708
0x070C
0x0710
0x0714
0x0718
0X072C
Name
COMTX
COMRX
COMDIV0
COMIEN0
COMDIV1
COMIID0
COMCON0
COMCON1
COMSTA0
COMSTA1
COMDIV2
Byte
1
1
1
1
1
1
1
1
1
1
2
Access
Type
W
R
RW
RW
R/W
R
RW
RW
R
R
RW
Default Value
N/A
0x00
0x00
0x00
0x00
0x01
0x03
0x00
0x60
0x00
0x0000
Description
UART transmit register.
UART receive register.
UART Standard Baud Rate Generator Divisor Value 0.
UART Interrupt Enable MMR 0.
UART Standard Baud Rate Generator Divisor Value 1.
UART Interrupt Identification 0.
UART Control Register 0.
UART Control Register 1.
UART Status Register 0.
UART Status Register 1.
UART fractional divider MMR.
Rev. PrC | Page 23 of 96
ADuC7060/ADuC7061
Preliminary Technical Data
Table 18. I2C Base Address = 0xFFFF0900
Address
0x0900
0x0904
0x0908
0x090C
0x0910
Name
I2CMCON
I2CMSTA
I2CMRX
I2CMTX
I2CMCNT0
Byte
2
2
1
1
2
Access
Type
R/W
R
R
W
R/W
Default
Value
0x0000
0x0000
0x00
0x00
0x0000
0x0914
I2CMCNT1
1
R
0x00
0x0918
I2CADR0
1
R/W
0x00
0x091C
I2CADR1
1
R/W
0x00
0x0924
0x0928
0x092C
0x0930
0x0934
0x0938
0x093C
0x0940
0x0944
0x0948
0x094C
I2CDIV
I2CSCON
I2CSSTA
I2CSRX
I2CSTX
I2CALT
I2CID0
I2CID1
I2CID2
I2CID3
I2CFSTA
2
2
2
1
1
1
1
1
1
1
2
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0x1F1F
0x0000
0x0000
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x0000
Description
I2C master control register.
I2C master status register.
I2C master receive register.
I2C master transmit register.
I2C master read count register. Write the number of required bytes into this
register prior to reading from a slave device.
I2C master current read count register. this register contains the number of
bytes already received during a read from slave sequence.
Address byte register. Write the required slave address in here prior to
communications.
Address byte register. Write the required slave address in here prior to
communications. Only used in 10-bit mode.
I2C clock control register. Used to configure the SCLK frequency.
I2C slave control register.
I2C slave status register.
I2C slave receive register.
I2C slave transmit register.
I2C hardware general call recognition register.
I2C Slave ID0 register. Slave bus ID register.
I2C Slave ID1 register. Slave bus ID register.
I2C Slave ID2 register. Slave bus ID register.
I2C Slave ID3 register. Slave bus ID register.
I2C FIFO status register. Used in both master and slave modes.
Table 19. SPI Base Address = 0xFFFF0A00
Address
0x0A00
0x0A04
0x0A08
0x0A0C
0x0A10
Name
SPISTA
SPIRX
SPITX
SPIDIV
SPICON
Byte
4
1
1
1
2
Access Type
R
R
W
RW
RW
Default Value
0x00000000
0x00
0x1B
0x00
Table 20. GPIO Base Address = 0xFFFF0D00
Address
0x0D00
0x0D04
0x0D08
0x0D20
0x0D24
0x0D28
0x0D2C
0x0D30
0x0D34
0x0D38
0x0D3C
0x0D40
0x0D44
0x0D48
0x0D4C
Name
GP0CON
GP1CON
GP2CON
GP0DAT
GP0SET
GP0CLR
GP0PAR
GP1DAT
GP1SET
GP1CLR
GP1PAR
GP2DAT
GP2SET
GP2CLR
GP2PAR
Byte
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
Access
Type
RW
RW
RW
RW
W
W
W
RW
W
W
W
RW
W
W
W
Default Value
0x00000000
0x00000000
0x00000000
0x000000EF
0x000000EF
0x000000EF
0x00000000
0x000000FF
0x000000FF
0x000000FF
0x00000000
0x000000FF
0x000000FF
0x000000FF
0x00000000
Description
GPIO Port0 control MMR.
GPIO Port1 control MMR.
GPIO Port2 control MMR.
GPIO Port0 data control MMR.
GPIO Port0 data set MMR.
GPIO Port0 data clear MMR.
GPIO Port0 pull-up disable MMR.
GPIO Port1 data control MMR.
GPIO Port1 data set MMR.
GPIO Port1 data clear MMR.
GPIO Port1 pull-up disable MMR.
GPIO Port2 data control MMR.
GPIO Port2 data set MMR.
GPIO Port2 data clear MMR.
GPIO Port2 pull-up disable MMR.
Rev. PrC | Page 24 of 96
Description
SPI status MMR.
SPI receive MMR.
SPI transmit MMR.
SPI baud rate select MMR.
SPI control MMR.
Preliminary Technical Data
ADuC7060/ADuC7061
Table 21. Flash/EE Base Address = 0xFFFF0E00
Address
0x0E00
0x0E04
0x0E08
0x0E0C
0x0E10
0x0E18
0x0E1C
0x0E20
Name
FEESTA
FEEMOD
FEECON
FEEDAT
FEEADR
FEESIG
FEEPRO
FEEHID
Byte
1
1
1
2
2
3
4
4
Access
Type
R
RW
RW
RW
RW
R
RW
RW
Default Value
0x20
0x00
0x07
0x0000
0x0000
0xFFFFFF
0x00000000
0xFFFFFFFF
Description
Flash/EE status MMR.
Flash/EE control MMR.
Flash/EE control MMR.
Flash/EE data MMR.
Flash/EE address MMR.
Flash/EE LFSR MMR.
Flash/EE protection MMR.
Flash/EE protection MMR.
Table 22. PWM Base Address = 0xFFFF0F80
Address
0x0F80
Name
PWMCON
Byte
2
Access
Type
R/W
Default Value
0x0000
0x0F84
0x0F88
0x0F8C
0x0F90
0x0F94
0x0F98
0x0F9C
0x0FA0
0x0FA4
0x0FA8
0x0FAC
0x0FB0
0x0FB8
PWM0COM0
PWM0COM1
PWM0COM2
PWM0LEN
PWM1COM0
PWM1COM1
PWM1COM2
PWM1LEN
PWM2COM0
PWM2COM1
PWM2COM2
PWM2LEN
PWMCLRI
2
2
2
2
2
2
2
2
2
2
2
2
2
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
Description
PWM control register. See the Pulse-Width Modulator (PWM) section for
full details.
Compare Register 0 for PWM Output 0 and PWM Output 1.
Compare Register 1 for PWM Output 0 and PWM Output 1.
Compare Register 2 for PWM Output 0 and PWM Output 1.
Frequency control for PWM Output 0 and PWM Output 1.
Compare Register 0 for PWM Output 2 and PWM Output 3.
Compare Register 1 for PWM Output 2 and PWM Output 3.
Compare Register 2 for PWM Output 2 and PWM Output 3.
Frequency Control for PWM Output 2 and PWM Output 3.
Compare Register 0 for PWM Output 4 and PWM Output 5.
Compare Register 1 for PWM Output 4 and PWM Output 5.
Compare Register 2 for PWM Output 4 and PWM Output 5.
Frequency Control for PWM Output 4 and PWM Output 5.
PWM Interrupt Clear Register. Writing any value to this register clears a
PWM interrupt source.
Rev. PrC | Page 25 of 96
ADuC7060/ADuC7061
Preliminary Technical Data
RESET
RSTCLR Register
There are four kinds of reset: external reset, power-on-reset,
watchdog reset, and software reset. The RSTSTA register
indicates the source of the last reset and can be written by user
code to initiate a software reset event.
Name:
Address:
Access:
Function:
The bits in this register can be cleared to 0 by writing to the
RSTCLR MMR at 0xFFFF0234. The bit designations in
RSTCLR mirror those of RSTSTA. These registers can be used
during a reset exception service routine to identify the source of
the reset. The implications of all four kinds of reset events are
tabulated in Table 24.
Table 23. RSTSTA/RSTCLR MMR Bit Designations
Bit
7 to 4
3
RSTSTA Register
Name:
Address:
Default value:
Access:
Function:
RSTSTA
0xFFFF0230
Depends on type of reset
Read/write access
This 8-bit register indicates the source of the
last reset event and can be written by user code
to initiate a software reset.
RSTCLR
0xFFFF0234
Write only
This 8-bit write only register clears the
corresponding bit in RSTSTA.
2
1
0
1
Description
Not used. These bits are not used and always
read as 0.
External reset.
Automatically set to 1 when an external reset
occurs.
This bit is cleared by setting the corresponding bit
in RSTCLR.
Software reset.
This bit is set to 1 by user code to generate a software reset.
This bit is cleared by setting the corresponding bit
in RSTCLR.1
Watchdog timeout.
Automatically set to 1 when a watchdog timeout
occurs.
Cleared by setting the corresponding bit in RSTCLR.
Power-on reset.
Automatically Set when a power-on-reset occurs.
Cleared by setting the corresponding bit in RSTCLR.
If the software reset bit in RSTSTA is set, any write to RSTCLR that does not
clear this bit generates a software reset.
Table 24. Device Reset Implications
RESET
POR
Watchdog
Software
External
Pin
Reset External
Pins to Default
State
Yes
Yes
Yes
Yes
Kernel
Executed
Yes
Yes
Yes
Yes
Reset All
External MMRs
(Excluding
RSTSTA)
Yes
Yes
Yes
Yes
Peripherals
Reset
Yes
Yes
Yes
Yes
Rev. PrC | Page 26 of 96
Watchdog
Timer Reset
Yes
No
No
No
RAM
Valid
Yes/No
Yes
Yes
Yes
RSTSTA (Status
After Reset
Event)
RSTSTA[0] = 1
RSTSTA[1] = 1
RSTSTA[2] = 1
RSTSTA[3] = 1
Preliminary Technical Data
ADuC7060/ADuC7061
OSCILLATOR, PLL AND POWER CONTROL
Clocking System
Each ADuC7060 integrates a 32.768 kHz ±3% oscillator, a clock
divider, and a PLL. The PLL locks onto a multiple of the internal
oscillator or an external 32.768 kHz crystal to provide a stable 10.24
MHz clock (UCLK) for the system. To allow power saving, the core
can operate at this frequency, or at binary submultiples of it. The
actual core operating frequency, UCLK/2CD, is refered to as HCLK.
The default core clock is the PLL clock divided by 8 (CD = 3) or
1.28 MHz.
The selection of the clock source is in the PLLCON register. By
default, the part uses the internal oscillator feeding the PLL.
Power Control System
The core clock frequency is changed by writing to the POWCON0
register. This is a key protected register therefore, registers
POWKEY1 and POWKEY2 must be written to immediately before
and after configuring the POWCON0 register. The following is a
simple example showing how to configure the core clock for
10.24 MHz:
POWKEY1 = 0x1;
INT. 32kHz
OSCILLATOR
WATCHDOG
TIMER
POWCON0 = 0x78;
WAKEUP
TIMER
//Set core to max CPU
//speed of 10.24 MHz
POWKEY2 = 0xF4;
A choice of operating modes is available on the ADuC7060. Table
below describes what part is powered on in the different modes and
indicates the power-up time.
OCLK 32.768kHz
PLL
I2 C
CD
CORE
10.24MHz
UCLK
ANALOG
PERIPHERALS
/2CD
07079-008
HCLK
*32.768kHz ±3%
Table 26 gives some typical values of the total current consumption
(analog + digital supply currents) in the different modes, depending
on the clock divider bits. The ADC is turned off. Note that these
values also include current consumption of the regulator and other
parts on the test board where these values are measured.
Figure 8. Clocking System
Table 25.
POWCON[6:3]
1111
1110
1100
1000
0000
Mode
Active
Pause
Nap
Sleep
Stop
Core
TBD
Peripherals
TBD
TBD
PLL
TBD
TBD
TBD
XTAL/T2/T3
TBD
TBD
TBD
TBD
IRQ0 to IRQ3
TBD
TBD
TBD
TBD
TBD
Start-Up/Power-On Time
Table 26. Typical Current Consumption at 25°C in mA
POWCON[6:3]
1111
1110
1100
1000
0000
Mode
Active
Pause
Nap
Sleep
Stop
CD = 0
TBD
TBD
TBD
TBD
TBD
CD = 1
TBD
TBD
TBD
TBD
TBD
CD = 2
TBD
TBD
TBD
TBD
TBD
Rev. PrC | Page 27 of 96
CD = 3
TBD
TBD
TBD
TBD
TBD
CD = 4
TBD
TBD
TBD
TBD
TBD
CD = 5
TBD
TBD
TBD
TBD
TBD
CD = 6
TBD
TBD
TBD
TBD
TBD
CD = 7
TBD
TBD
TBD
TBD
TBD
ADuC7060/ADuC7061
Preliminary Technical Data
Power and Clock Control Registers
Name:
Address:
Default value:
Access:
Function:
POWKEY1
0xFFFF0404
0xXXXX
Write
When writing to POWCON0, the value of
0x01 must be written to this register in the
instruction immediately before writing to
POWCON0
Name:
Address:
Default value:
Access:
Function:
POWCON0
0xFFFF0408
0x7B
Read/write
This register controls the clock divide bits
controlling the CPU clock (HCLK)
Table 27. POWCON0 MMR Bit Designations
Bit
7
6
Name
Reserved
XPD
5
PLLPD
4
PPD
3
COREPD
2 to 0
CD[2:0]
Description
This bit must always be set to 0.
XTAL power down.
Cleared by the user to power-down the external crystal circuitry.
Set by the user to enable the external crystal circuitry.
PLL power down. Timer peripherals power down if driven from the PLL output clock.
Timers driven from an active clock source remain in normal power mode.
This bit is cleared to 0 to power-down the PLL.
The PLL cannot be powered down if either the core or peripherals are enabled:
Bit 3, Bit 4, and Bit 5 must be cleared simultaneously.
Set by default, and set by hardware on a wake-up event.
Peripherals power down. The peripherals that are powered down by this bit are as follows:
SRAM, Flash/EE memory and GPIO interfaces, and SPI/I2C and UART serial ports.
Cleared to power-down the peripherals. The peripherals cannot be powered down if the core is enabled:
Bit 3 and Bit 4 must be cleared simultaneously.
Set by default, and/or by hardware, on a wake-up event. Wake-up timer (Timer1) can still be active
Core power down. If user code powers down the MCU, include a dummy MCU cycle after the power-down command
is written to POWCON.
Cleared to power-down the ARM core.
Set by default and set by hardware on a wake-up event.
Core clock depends on CD setting:
[000] = 10.24 MHz
[001] = 5.12 MHz
[010] = 2.56 MHz
[011] = 1.28 MHz [default value]
[100] = 640 kHz
[101] = 320 kHz
[110] = 160 kHz
[111] = 80 kHz
Rev. PrC | Page 28 of 96
Preliminary Technical Data
Name:
Address:
Default value:
Access:
Function:
ADuC7060/ADuC7061
POWKEY2
0xFFFF040C
0xXXXX
Write
When writing to POWCON0, the Value 0xF4
must be written to this register in the
instruction immediately after writing to
POWCON0
Name:
PLLKEY1
Address:
0xFFFF0410
Default value:
0xXXXX
Access:
Write
Function:
When writing to the PLLCON register, the
value 0xAA must be written to this register in
the instruction immediately before writing to
PLLCON
Name:
PLLCON
Address:
0xFFFF0414
Default value:
0x00
Access:
Read/Write
Function:
This register selects the clock input to the PLL.
Table 28. PLLCON MMR Bit Designations
Bit
7 to 2
1 to 0
Name
Reserved
OSEL
Description
These bits must always be set to 0.
Oscillator selection bits:
[00] = internal 32,768 Hz oscillator
[01] = internal 32,768 Hz oscillator
[10] = external crystal
[11] = internal 32,768 Hz oscillator
Name:
PLLKEY2
Address:
0xFFFF0418
Default value:
0xXXXX
Access:
Write
Function:
When writing to PLLCON, the Value 0x55 must
be written to this register in the instruction
immediately after writing to PLLCON.
Rev. PrC | Page 29 of 96
ADuC7060/ADuC7061
Preliminary Technical Data
ADC CIRCUIT INFORMATION
AVDD
INTERNAL
REFERENCE
IEXC0
VREF+ VREF–
DAC0
BUF
DAC
CONVERSION
COUNTER
AVDD
IEXC1
50µA O/C
DETECT
AIN0
EXT_REF2IN+
EXT_REF2IN−
OVERRANGE
AIN1
0.5Hz TO 8kHz
Σ-Δ
MODULATOR
PROGRAMMABLE
FILTER
PGA
CHOP
MUX
0.2mA TO 1mA
0.2Hz TO 8kHz
Σ-Δ
MODULATOR
BUF
INTERFACE
AND CONTROL
TO ARM
PROGRAMMABLE
FILTER
AIN2
AIN3
AIN4
AIN5
AIN6
AIN7
INTEGRATOR
ACCUMULATOR
AIN8
AIN9
CHOP
MUX
50Ω
AGND
TEMPERATURE
SENSOR
07079-009
GND_SW
COMPARATORS
Figure 9. Analog Block Diagram
The ADuC706x incorporates two independent multichannel
Σ-Δ ADCs. The primary ADC is a 24-bit, 5-channel ADC. The
auxiliary ADC is a 24-bit Σ-Δ ADC, with up to eight input
channels.
The primary ADC input has a mux and a programmable gain
amplifier on its input stage. The mux on the primary channel
can be configured as two fully differential input channels or
four single-ended input channels.
The auxiliary ADC incorporates a buffer on its input stage.
Digital filtering is present on both ADCs which allows
measurement of a wide dynamic range and low frequency
signals such as those in pressure sensor, temperature sensor,
weigh-scale, or strain-gauge type applications.
The ADuC706x auxiliary ADC can be configured as four fully
differential input channels or as eight single-ended input
channels.
Because of internal buffering, the internal channels can convert
signals directly from sensors without the need for external
signal conditioning.
Rev. PrC | Page 30 of 96
Preliminary Technical Data
ADuC7060/ADuC7061
Table 29. Primary ADC—Typical Output RMS Noise in Normal Mode (μV)
ADC
Register
Status
(Chop
On)
(Chop
Off)
(Chop
Off)
(Chop
Off)
Data
Update
Rate
4 Hz
±1.2 mV
(PGA = 1)
0.62 μV
±600 mV ±300 mV
(PGA = 2) (PGA = 4)
0.648 μV 0.175μV
Input Voltage Noise (mV)
±150 mV ±75 mV
±37.5 mV ±18.75 mV
(PGA = 8) (PGA = 16) (PGA = 32) (PGA = 64)
0.109 μV 0.077 μV
0.041 μV
0.032 μV
±9.375 mV
(PGA = 128)
0.0338 μV
±4.68 mV
±2.34 mV
(PGA = 256) (PGA = 512)
0.032 μV
0.033 μV
50 Hz
1.97 μV
1.89 μV
0.570 μV
0.38 μV
0.27 μV
0.147 μV
0.123 μV
0.12 μV
0.098 μV
0.098 μV
1 kHz
8.54 μV
8.4 μV
2.55 μV
1.6 μV
1.17 μV
0.658 μV
0.53 μV
0.55 μV
0.56 μV
0.52 μV
8 kHz
54.97 μV
55.54 μV
14.30 μV
7.88 μV
4.59 μV
2.5 μV
1.71 μV
1.75 μV
0.915 μV
0.909 μV
Table 30. Primary ADC—Typical Output RMS Effective Number of Bits in Normal Mode (Peak-to-Peak Bits in Parentheses)
Data
Update
Rate
4 Hz
50 Hz
1 kHz
8 kHz
±1.2 V
(PGA = 1)
21.9
(19.1 p-p)
20.2
(17.5 p-p)
18.1
(15.3 p-p)
15.4
(12.7 p-p)
±600 mV
(PGA = 2)
20.8
(18.1 p-p)
19.3
(16.6 p-p)
17.1
(14.4 p-p)
14.4
(11.7 p-p)
±300 mV
(PGA = 4)
21.7
(19.0 p-p)
20.0
(17.3 p-p)
17.8
(15.1 p-p)
15.4
(12.6 p-p)
±150 mV
(PGA = 8)
21.4
(18.7 p-p)
19.6
(16.9 p-p)
17.5
(14.8 p-p)
15.2
(12.5 p-p)
Input Voltage Noise (mV)
±75 mV
±37.5 mV
±18.75 mV
(PGA = 16) (PGA = 32) (PGA = 64)
20.9
20.8
20.2
(18.2 p-p)
(18.1 p-p)
(17.4 p-p)
19.1
19.0
18.2
(16.4 p-p)
(16.2 p-p)
(15.5 p-p)
17.0
16.8
16.1
(14.2 p-p)
(14.1 p-p)
(13.4 p-p)
15.0
14.9
14.4
(12.3 p-p)
(12.2 p-p)
(11.7 p-p)
ADC Register
Chop On
Chop On
Chop Off
Chop Off
±4.68 mV
(PGA = 256)
18.2
(15.4 p-p)
16.6
(13.8 p-p)
14.0
(11.3 p-p)
13.3
(10.6 p-p)
±2.34 mV
(PGA = 512)
17.1
(14.4 p-p)
15.5
(12.8 p-p)
13.1
(10.4 p-p)
12.3
(9.6 p-p)
Note, if an external reference source of greater than 1.35 V is
used for ADC0, the HIGHEXTREF0 bit must be set in
ADC0CON. Similarly, an external reference source of greater
than 1.35 V is used for ADC1, the HIGHEXTREF1 bit must be
set in ADC1CON.
Table 31. Auxilary ADC: Typical Output RMS Noise
Data
Update Rate
4 Hz
10 Hz
1 kHz
8 kHz
±9.375 mV
(PGA = 128)
19.1
(16.4 p-p)
17.3
(14.6 p-p)
15.1
(12.3 p-p)
13.4
(10.7 p-p)
RMS Value
0.633 μV
0.810 μV
7.4 μV
54.18 μV
Diagnostic Current Sources
Reference Sources
Both the primary and secondary ADCs have the option of using
the internal reference voltage or, one of two external differential
reference sources. The first external reference is applied to the
VREF+/VREF− pins. The second external reference is applied
to the ADC4 (EXT_VREF2+) and ADC5 (EXT_VREF2−) pins.
By default, each ADC uses the internal 1.2 V reference source.
For details on how to configure the external reference source for
the primary ADC, see the description of the ADC0REF[1:0]
bits in the ADC0 control register, ADC0CON.
To detect a connection failure to an external sensor, the
ADuC706x incorporates 50 μA constant current sources on the
selected analog input channels to both the primary and
auxiliary ADCs.
The diagnostic current sources for the primary ADC analog
inputs are controlled by the ADC0DIAG[1:0] bits in the
ADC0CON register.
Similarly, the diagnostic current sources for the auxiliary ADC
analog inputs are controlled by the ADC1DIAG[1:0] bits in the
ADC0CON register.
For details on how to configure the external reference source for
the auxiliary ADC, see the description of the ADC1REF[2:0]
bits in the ADC1 control register, ADC1CON.
If an external reference source of greater than 1.35 V is needed
for ADC0, the HIGHEXTREF0 bit must be set in ADC0CON.
Similarly, if an external reference source of greater than 1.35 V
is used for ADC1, set the HIGHEXTREF1 bit in ADC1CON.
Rev. PrC | Page 31 of 96
A
B
AIN0 (+)
R1
AVDD
A
VIN =
AIN0,
AIN1
B
AIN1 (–)
R2
07079-010
ADC
Register
Status
(Chop
On)
(Chop
Off)
(Chop
Off)
(Chop
Off)
Figure 10. Example Circuit Using Diagnostic Current Sources
ADuC7060/ADuC7061
Preliminary Technical Data
Table 32. Example Scenarios for Using Diagnostic Current Sources
Diagnostic Test
Register Setting
ADC0DIAG[1:0] = 0
ADC0DIAG[1:0] = 1
ADC0DIAG[1:0] = 3
Detected
Measurement for Fault
Primary ADC reading ≈0 V
regardless of PGA setting.
Description
Convert ADC0/ADC1 as
normal with diagnostic
currents disabled.
Enable 50 μA diagnostic
current source on ADC0 by
setting ADC0DIAG[1:0] = 1.
Convert ADC0 and ADC1.
Normal Result
Expected differential
result across ADC0/ADC1.
Fault Result
Short circuit
Main ADC changes by
ΔV = +50 μA × R1. For
example, ~100 mV for R1
= 2 kΩ.
Primary ADC reading ≈ 0 V
regardless of PGA setting.
Convert ADC0 in singleended mode with
diagnostic currents
disabled.
Enable 50 μA diagnostic
current source on both
ADC0 and ADC1 by setting
ADC0DIAG[1:0] = 3.
Convert ADC0 and ADC1.
Expected voltage on
ADC0.
Short circuit between
ADC0 and ADC1.
Short circuit between
R1_a and R1_b.
ADC0 open circuit or R1
open circuit
R1 does not match R2
Primary ADC reading > 10
mV
Primary ADC changes by
ΔV = 50 μA × (R1-R2). That
is, ~10 mV for 10%
tolerance.
Sinc3 Filter
The number entered into Bits[6:0] of the ADCFLT register sets
the decimation factor of the Sinc3 filter. See Table 33 and Table 34
for further details on the decimation factor values.
The range of operation of the Sinc3 filter (SF) word depends on
whether the chop function is enabled. With chopping disabled,
the minimum SF word allowed is 3 and the maximum is 127,
giving an ADC throughput range of 50 Hz to 2 kHz.
For details on how to calculate the ADC sampling frequency
based on the value programmed to the SF[6:0] in the ADCFLT
register, refer to Table 33 for more details.
ADC CHOPPING
The ADCs on the ADuC706x implement a chopping scheme
whereby the ADC repeatedly reverses its inputs. Therefore, the
decimated digital output values from the Sinc3 filter have a
positive and negative offset term associated with them. This
results in the ADC including a final summing stage that sums
and averages each value from the filter with previous filter
output values. This new value is then sent to the ADC data
MMR. This chopping scheme results in excellent dc offset and
offset drift specifications and is extremely beneficial in
applications where drift and noise rejection are required.
Programmable Gain Amplifier
The primary ADC incorporates an on-chip programmable gain
amplifier (PGA). The PGA can be programmed through 10
different settings giving a range of 1 to 512. The gain is
controlled by the ADC0PGA[3:0] bits in the ADC0CON MMR.
Excitation Sources
The ADuC706x contains two matched software configurable
current sources. These excitation currents are sourced from
AVDD. They are individually configurable to give a current
range of 200 μA to 1 mA. The current step sizes are 200 μA.
Primary ADC reading =
+full scale, even on the
lowest PGA setting.
These current sources can be used to excite an external resistive
bridge or RTD sensors. The IEXCON MMR controls the
excitation current sources. Bit 6 of IEXCON must be set to
enable Excitation Current Source 0. Similarly, Bit 7 must be set
to enable Excitation Current Source 1. The output current of
each current source is controlled by the IOUT[3:0] bits of this
register.
It is also possible to configure the excitation current sources to
output current to a single output pin, either IEXC0 or IEXC1,
by using the IEXC0_DIR and IEXC1_DIR bits of IEXCON. This
allows up to 2 mA to output current on a single excitation pin.
ADC Low Power Mode
The ADuC706x allows the primary and auxiliary ADCs to be
placed in Low-Power operating mode. When configured for
this mode, the ADC throughput time is reduced but, the power
consumption of the primary ADC is reduced by a factor of
about 4; the auxiliary ADC power consumption is reduced by a
factor of roughly 3. The maximum ADC conversion rate in
Low-Power mode is 2 kHz. The operating mode of the ADC’s is
controlled by the ADCMDE register. This register configures
the part for either normal mode (default), low power mode or
low-power-plus mode. Low-power plus mode is the same as
low-power mode except, the PGA is disabled.
To place the ADCs in low power mode, the following steps must
be completed:
•
•
•
ADCMDE[4:3]—Setting these bits enables normal mode,
low power mode, or low power-plus mode.
ADCMDE[5]—Setting this bit configures the part for low
power mode.
ADCMDE[7]—Clearing this bit further reduces power
consumption by reducing the frequency of the ADC clock.
Rev. PrC | Page 32 of 96
Preliminary Technical Data
ADuC7060/ADuC7061
ADC Comparator and Accumulator
Every primary ADC result can be compared to a preset
threshold level (ADC0TH) as configured via ADCCFG[4:3]. An
MCU interrupt is generated if the absolute (sign independent)
value of the ADC result is greater than the preprogrammed
comparator threshold level. An extended function of this
comparator function allows user code to configure a threshold
counter (ADC0THV) to monitor the number of Primary ADC
results that have occurred above or below the preset threshold
level. Again, an ADC interrupt is generated when the threshold
counter reaches a preset value (ADC0TCL).
Finally, a 32-bit accumulator (ADC0ACC) function can be
configured (ADCCFG[6:5]) allowing the primary ADC to add
(or subtract) multiple primary ADC sample results. User code
can read the accumulated value directly (ADC0ACC) without
any further software processing.
ADC MMR Interface
The ADCs are controlled and configured through a number of
MMRs that are described in detail in the following sections.
In response to an ADC interrupt, user code should interrogate
the ADCSTA MMR to determine the source of the interrupt.
Each ADC interrupt source can be individually masked via the
ADCMSKI MMR described in Table 33.
All primary ADC result ready bits are cleared by a read of the
ADC0DAT MMR. If the Primary Channel ADC is not enabled,
all ADC result ready bits are cleared by a read of the ADC1DAT
MMR. To ensure that primary ADC and auxiliary ADC
conversion data are synchronous, user code should first read
the ADC1DAT MMR and then the ADC0DAT MMR. New
ADC conversion results are not written to the ADCxDAT
MMRs unless the respective ADC result ready bits are first
cleared. The only exception to this rule is the data conversion
result updates when the ARM core is powered down. In this
mode, ADCxDAT registers always contain the most recent
ADC conversion result even though the ready bits have not
been cleared.
ADC Status Register
Name:
ADCSTA
Address:
0xFFFF0500
Default value:
0x0000
Access:
Read only
Function:
This read-only register holds general status
information related to the mode of operation
or current status of the ADuC7060/ADuC7061
ADCs.
Table 33. ADCSTA MMR Bit Designations
Bit
15
Name
ADCCALSTA
14
13
ADC1CERR
12
ADC0CERR
11 to 7
6
ADC0ATHEX
5
Description
ADC calibration status.
This bit is set automatically in hardware to indicate an ADC calibration cycle has been completed.
This bit is cleared after ADCMDE is written to.
Not used.
This bit is reserved for future functionality
Auxiliary ADC conversion error.
This bit is set automatically in hardware to indicate that an auxiliary ADC conversion overrange or underrange has
occurred. The conversion result is clamped to negative full scale (underrange error) or positive full scale (overrange
error) in this case.
This bit is cleared when a valid (in-range) voltage conversion result is written to the ADC1DAT register.
Primary ADC conversion error.
This bit is set automatically in hardware to indicate that a primary ADC conversion overrange or underrange has
occurred. The conversion result is clamped to negative full scale (underrange error) or positive full scale (overrange
error) in this case.
This bit is cleared when a valid (in-range) conversion result is written to the ADC0DAT register.
Not used. These bits are reserved for future functionality and should not be monitored by user code.
ADC0 accumulator comparator threshold exceeded.
This bit is set when the ADC0 Accumulator value in ADC0ACC has exceeded the threshold value programmed in
the ADC0 Comparator Threshold register, ADCOATH.
This bit is cleared when the value in ADC0ATH does not exceed the value in ADC0ATH
Not used. This bit is reserved for future functionality and should not be monitored by user code.
Rev. PrC | Page 33 of 96
ADuC7060/ADuC7061
Bit
4
Name
ADC0THEX
3
ADC0OVR
2
1
ADC1RDY
0
ADC0RDY
Preliminary Technical Data
Description
Primary Channel ADC comparator threshold. This bit is only valid if the Primary Channel ADC comparator is
enabled via the ADCCFG MMR.
This bit is set by hardware if the absolute value of the primary ADC conversion result exceeds the value written in
the ADC0TH MMR. If the ADC threshold counter is used (ADC0TCL), this bit is only set when the specified number
of primary ADC conversions equals the value in the ADC0THV MMR.
Other wise, this bit is clear.
Primary Channel ADC overrange bit. If the overrange detect function is enabled via the ADCCFG MMR, this bit is set
by hardware if the primary ADC input is grossly (>30% approximate) overrange. This bit is updated every 125 μs.
After it is set, this bit can only be cleared by software when ADCCFG[2] is cleared to disable the function, or the
ADC gain is changed via the ADC0CON MMR.
Not used. These bits are reserved for future functionality and should not be monitored by user code.
Auxiliary ADC result ready bit.
If the Auxiliary Channel ADC is enabled, this bit is set by hardware as soon as a valid conversion result is written in
the ADC1DAT MMR. It is also set at the end of a calibration sequence.
This bit is cleared by reading ADC1DAT followed by reading ADC0DAT. ADC0DAT must be read to clear this bit,
even if the primary ADC is not enabled.
Primary ADCresult ready bit.
If the Primary Channel ADC is enabled, this bit is set by hardware as soon as a valid conversion result is written in
the ADC0DAT MMR. It is also set at the end of a calibration sequence.
This bit is cleared by reading ADC0DAT.
ADC Interrupt Mask Register
Name:
ADCMSKI
Address:
0xFFFF0504
Default value:
0x00
Access:
Read/write
Function:
This register allows the ADC interrupt sources to be enabled individually. The bit positions in this register are the
same as the lower eight bits in the ADCSTA MMR. If a bit is set by user code to a 1, the respective interrupt is enabled.
By default, all bits are 0, meaning all ADC interrupt sources are disabled.
Table 34. ADCMSKI MMR Bit Designations
Bit
7
6
Name
ADC0ATHEX_INTEN
5
4
ADC0THEX_INTEN
3
ADC0OVR_INTEN
2
1
ADC1RDY_INTEN
0
ADC0RDY_INTEN
Description
Not used. These bits are reserved for future functionality and should not be monitored by user code.
ADC0 accumulator comparator threshold exceeded interrupt enable bit.
When set to 1, this bit enables an interrupt when the ADC0ATHEX bit in the ADCSTA register is set.
When this bit is cleared, this interrupt source is disabled.
Not used. These bits are reserved for future functionality and should not be monitored by user code.
Primary Channel ADC comparator threshold exceeded interrupt enable bit.
When set to 1, this bit enables an interrupt when the ADC0THEX bit in the ADCSTA register is set.
When this bit is cleared, this interrupt source is disabled.
When set to 1, this bit enables an interrupt when the ADC0OVR bit in the ADCSTA register is set.
When this bit is cleared, this interrupt source is disabled.
Not used. These bits are reserved for future functionality and should not be monitored by user code..
Auxiliary ADC result ready bit.
When set to 1, this bit enables an interrupt when the ADC1RDY bit in the ADCSTA register is set.
When this bit is cleared, this interrupt source is disabled.
Primary ADC result ready bit.
When set to 1, this bit enables an interrupt when the ADC0RDY bit in the ADCSTA register is set.
When this bit is cleared, this interrupt source is disabled.
Rev. PrC | Page 34 of 96
Preliminary Technical Data
ADuC7060/ADuC7061
ADC Mode Register
Name:
ADCMDE
Address:
0xFFFF0508
Default value:
0x00
Access:
Read/write
Function:
The ADC mode MMR is an 8-bit register that configures the mode of operation of the ADC subsystem.
Table 35. ADCMDE MMR Bit Designations
Bit
7
Name
ADCCLKSEL
6
5
ADCLPMEN
4 to 3
ADCLPMCFG[1:0]
2 to 0
ADCMD[2:0]
Description
Set this bit to 1 to enable ADCCLK = 4 MHz. This bit should be set for normal ADC operation.
Clear this bit to enable ADCCLK = 131 kHz. This bit should be cleared for low power ADC operation.
Not Used. These bits are reserved for future functionality and should not be monitored by user code.
Enable low power mode. This bit has no effect if ADCMDE[4:3] = 00.
This bit must be set to 1 in low power mode.
Clearing this bit in low power mode results in erratic ADC results.
This bit has no effect if the ADC is in normal mode.
ADC power mode configuration.
0, 0 = ADC normal mode. If enabled, the ADC operates with normal current consumption yielding optimum
electrical performance.
0, 1 = ADC low power mode.
1, 0 = ADC normal mode, same as [0, 0].
1, 1 = ADC low power plus mode (low power mode and PGA off ).
ADC operation mode configuration.
0, 0, 0 = ADC power-down mode. All ADC circuits and the input amplifier are powered down.
0, 0, 1 = ADC continuous conversion mode. In this mode, any enabled ADC continuously converts at a
frequency equal to fADC. RDY must be cleared to enable new data to be written to ADC0DAT/ADC1DAT
0, 1, 0 = ADC Single conversion mode. In this mode, any enabled ADC performs a single conversion. The ADC
enters idle mode when the single shot conversion is complete. A single conversion takes two to three ADC clock
cycles depending on the chop mode.
0, 1, 1 = ADC idle mode. In this mode, the ADC is fully powered on but is held in reset. The part enters this
mode after calibration.
1, 0, 0 = ADC self-offset calibration. In this mode, an offset calibration is performed on any enabled ADC using
an internally generated 0 V. The calibration is carried out at the user programmed ADC settings; therefore, as
with a normal single ADC conversion, it takes two to three ADC conversion cycles before a fully settled
calibration result is ready. The calibration result is automatically written to the ADCxOF MMR of the respective
ADC. The ADC returns to idle mode and the calibration and conversion ready status bits are set at the end of an
offset calibration cycle.
Note: Always use ADC0 for single-ended self-calibration cycles on the primary ADC. Always use ADC0/ADC1
when self-calibrating for a differential input to the primary ADC.
1, 0, 1 = ADC self-gain calibration. In this mode, a gain calibration against an internal reference voltage is
performed on all enabled ADCs. A gain calibration is a two-stage process and takes twice the time of an offset
calibration. The calibration result is automatically written to the ADCxGN MMR of the respective ADC. The ADC
returns to idle mode and the calibration and conversion ready status bits are set at the end of a gain calibration
cycle. An ADC self-gain calibration should only be carried out on the Primary Channel ADC.
Note that self-gain calibration only works when the gain = 1. It should not be used when the gain > 1.
1, 1, 0 = ADC system zero-scale calibration. In this mode, a zero-scale calibration is performed on enabled ADC
channels against an external zero-scale voltage driven at the ADC input pins. To do this, the channel should be
shorted externally.
1, 1, 1 = ADC system full-scale calibration. In this mode, a full-scale calibration is performed on enabled ADC
channels against an external full-scale voltage driven at the ADC input pins. The ADCxGN register is updated
after a full-scale calibration sequence.
Rev. PrC | Page 35 of 96
ADuC7060/ADuC7061
Preliminary Technical Data
Primary ADC Control Register
Name:
ADC0CON
Address:
0xFFFF050C
Default value:
0x0000
Access:
Read/write
Function:
The Primary Channel ADC control MMR is a 16-bit register. If the primary ADC is reconfigured via ADC0CON, the
auxiliary ADC is also reset.
ADC0CON MMR Bit Designations
Bit
15
Name
ADC0EN
14, 13
ADCODIAG[1:0]
12
HIGHEXTREF0
11
AMP_CM
10
ADC0CODE
9 to 6
ADC0CH[3:0]
5, 4
ADC0REF[1:0]
Description
Primary Channel ADC enable.
This bit is set to 1 by user code to enable the primary ADC.
Clearing this bit to 0 powers down the primary ADC and resets the respective ADC ready bit in the ADCSTA MMR
to 0.
Diagnostic current source enable bits.
0, 0 = current sources off.
0, 1 = enables 50 μA current source on selected positive input (for example, ADC0).
1, 0 = enables 50 μ A current source on selected negative input (for example, ADC1).
1, 1 = enables 50 μ A current source on both selected inputs (for example, ADC0 and ADC1).
This bit must be set high if the external reference for ADC0 exceeds 1.35 V.
Clear this bit when using the internal reference or an external reference of less than 1.35 V.
This bit is set to 1 by user to set the PGA output common-mode voltage to AVDD/2
This bit is cleared to 0 by user code to set the PGA output common-mode voltage to the PGA input commonmode voltage level
Primary Channel ADC output coding.
This bit is set to 1 by user code to configure primary ADC output coding as unipolar.
This bit is cleared to 0 by user code to configure primary ADC output coding as twos complement.
Primary Channel ADC input select.
[0000] = ADC0/ADC1 (differential mode).
[0001] = ADC0/ADC5 (single-ended mode).
[0010] = ADC1/ADC5 (single-ended mode).
[0011] = VREF+, VREF−. Note: This is the reference selected by the ADC0REF bits.
[0100] = Not Used. This bit combination is reserved for future functionality and should not be written.
[0101] = ADC2/ADC3 (differential mode).
[0110] = ADC2/ADC5 (single-ended mode).
[0111] = ADC3/ADC5 (single-ended mode).
[1000] = internal short to ADC0
[1001] = internal short to ADC1
Primary Channel ADC reference select.
0, 0 = internal reference selected. In ADC low power mode, the voltage reference selection is controlled by
ADCMODE[5].
0, 1 = external reference inputs (VREF+, VREF−) selected. Set the HIGHEXTREF0 bit if reference voltage exceeds
1.3 V.
1, 0 = auxiliary external reference inputs (ADC4/EXT_REF2IN+, ADC5/EXT_REF2IN−) selected. Set the
HIGHEXTREF0 bit if the reference voltage exceeds 1.3 V.
1, 1 = (AVDD, AGND) divided-by-two selected. TBC
Rev. PrC | Page 36 of 96
Preliminary Technical Data
Bit
3 to 0
Name
ADC0PGA[3:0].
ADuC7060/ADuC7061
Description
Primary Channel ADC gain select. Note, nominal primary ADC full-scale input voltage = (VREF/gain).
0, 0, 0, 0 = ADC0 gain of 1. Buffer is active.
0, 0, 0, 1 = ADC0 gain of 2.
0, 0, 1, 0 = ADC0 gain of 4 (default value). Enables the in-amp.
0, 0, 1, 1 = ADC0 gain of 8.
0, 1, 0, 0 = ADC0 gain of 16.
0, 1, 0, 1 = ADC0 gain of 32.
0, 1, 1, 0 = ADC0 gain of 64 (maximum PGIA gain setting).
0, 1, 1, 1 = ADC0 gain of 128 (extra gain implemented digitally).
1, 0, 0, 0 = ADC0 gain of 256.
1, 0, 0, 1 = ADC0 gain of 512.
1, x, x, x = ADC0 gain is undefined.
Auxiliary ADC Control Register
Name:
ADC1CON
Address:
0xFFFF0510
Default value:
0x0000
Access:
Read/write
Function:
The auxiliary ADC control MMR is a 16-bit register.
Table 36. ADC1CON MMR Bit Designations
Bit
15
Name
ADC1EN
14, 13
ADC1DIAG
12
HIGHEXTREF1
11
ADC1CODE
10 to 7
ADC1CH[3:0]
Description
Auxiliary Channel ADC enable.
This bit is set to 1 by user code to enable the auxiliary ADC.
Clearing this bit to 0 powers down the auxiliary ADC.
Diagnostic current source enable bits. This is the same current source as that used on ADC0DIAG. The ADCs
cannot enable the diagnostic current sources at the same time.
0, 0 = current sources off.
0, 1 = enables 50 μA current source on selected positive input (for example, ADC2).
1, 0 = enables 50 μ A current source on selected negative input (for example, ADC3).
1, 1 = enables 50 μ A current source on both selected inputs (for example, ADC2 and ADC3).
Must set this bit high if external reference for ADC0 exceeds 1.35 V.
Clear this bit when using the internal reference or an external reference of less than 1.35 V.
Auxiliary Channel ADC output coding.
This bit is set to 1 by user code to configure auxiliary ADC output coding as unipolar.
This bit is cleared to 0 by user code to configure auxiliary ADC output coding as twos complement.
Auxiliary Channel ADC input select. Note: Single-ended channels are selected with respect to ADC5. Bias
ADC5 to a minimum level of 0.1 V.
[0000] = ADC2/ADC3 (Differential mode).
[0001] = ADC4/ADC5 (Differential mode).
[0010] = ADC6/ADC7 (Differential mode).
[0011] = ADC8/ADC9 (Differential mode).
[0100] = ADC2/ADC5 (Single-Ended mode).
[0101] = ADC3/ADC5 (Single-Ended mode).
[0110] = ADC4/ADC5 (Single-Ended mode).
[0111] = ADC6/ADC5 (Single-Ended mode).
[1000] = ADC7/ADC5 (Single-Ended mode).
[1001] = ADC8/ADC5 (Single-Ended mode).
[1010] = ADC9/ADC5 (Single-Ended mode).
[1011] = internal temp sensor+/internal temp sensor−.
Rev. PrC | Page 37 of 96
ADuC7060/ADuC7061
Bit
Name
6 to 4
ADC1REF[2:0]
3, 2
BUF_BYPASS[1:0]
1 to 0
Preliminary Technical Data
Description
[1100] = VREF+, VREF−. Note: This is the reference selected by the ADC1REF bits.
[1101] = DAC_OUT/AGND.
[1110] = Undefined.
[1111] = Internal short to ADC3. TBD
Auxiliary Channel ADC reference select.
[0 00] = internal reference selected. In ADC low power mode, the voltage reference selection is controlled by
ADCMODE[5].
[0 01] = external reference inputs (VREF+, VREF−) selected. Set the HIGHEXTREF1 bit if reference voltage
exceeds 1.3 V.
[010] = auxiliary external reference inputs (ADC4/EXT_REF2IN+, ADC5/EXT_REF2IN−) selected. Set the
HIGHEXTREF1 bit if reference voltage exceeds 1.35 V.
[011] = (AVDD, AGND) divided-by-two selected. If this configuration is selected, the HIGHEXTREF1 bit is set
automatically.
[100] = (AVDD, ADC3). ADC3 can be used as the negative input terminal for the reference source.
[101] to [111] = reserved.
Buffer bypass.
[0 0] = full buffer on. Both positive and negative buffer inputs active.
[0 1] = negative buffer is bypassed, positive buffer is on.
[1 0] = negative buffer is on, positive buffer is bypassed.
[11] = full buffer bypass. Both positive and negative buffer inputs are off.
Digital gain. Select for auxiliary ADC inputs.
[00] = ADC1 gain = 1
[01] = ADC1 gain = 2
[10] = ADC1 gain = 4
[11] = ADC1 gain = 8
ADC Filter Register
Name:
ADCFLT
Address:
0xFFFF0514
Default value:
0x0007
Access:
Read/write
Function:
The ADC filter MMR is a 16-bit register that controls the speed and resolution of both the on-chip ADCs. Note that if
ADCFLT is modified, the primary and auxiliary ADCs are reset.
Table 37. ADCFLT MMR Bit Designations
Bit
15
Name
CHOPEN
14
RAVG2
13 to 8
AF[5:0]
Description
Chop enable. Set by the user to enable system chopping of all active ADCs. When this bit is set, the ADC has very low
offset errors and drift, but the ADC output rate is reduced by a factor of three if AF = 0 (see Sinc3 decimation factor,
Bits[6:0] in this table). If AF > 0, then the ADC output update rate is the same with chop on or off. When chop is
enabled, the settling time is two output periods.
Running average-by-2 enable bit.
Set by the user to enable a running-average-by-two function reducing ADC noise. This function is automatically
enabled when chopping is active. It is an optional feature when chopping is inactive, and if enabled (when chopping
is inactive) does not reduce the ADC output rate but does increase the settling time by one conversion period.
Cleared by the user to disable the running average function.
Averaging factor (AF). The values written to these bits are used to implement a programmable first-order Sinc3 post
filter. The averaging factor can further reduce ADC noise at the expense of output rate as described in Bits[6:0] Sinc3
decimation factor in this table.
Rev. PrC | Page 38 of 96
Preliminary Technical Data
Bit
7
Name
NOTCH2
6 to 0
SF[6:0]
1
2
ADuC7060/ADuC7061
Description
Sinc3 modify. Set by the user to modify the standard Sinc3 frequency response to increase the filter stop band
rejection by approximately 5 dB. This is achieved by inserting a second notch (NOTCH2) at
fNOTCH2 = 1.333 × fNOTCH
where fNOTCH is the location of the first notch in the response.
Sinc3 decimation factor (SF) 1 .The value (SF) written in these bits controls the oversampling (decimation factor) of the
Sinc3 filter. The output rate from the Sinc3 filter is given by
fADC = (512,000/([SF+1] × 64)) Hz 2
when the chop bit (Bit 15, chop enable) = 0 and the averaging factor (AF) = 0. This is valid for all SF values ≤ 125.
For SF = 126, fADC is forced to 60 Hz.
For SF = 127, fADC is forced to 50 Hz.
For information on calculating the fADC for SF (other than 126 and 127) and AF values, refer to Table X.
Due to limitations on the digital filter internal data path, there are some limitations on the combinations of the Sinc3 decimation factor (SF) and averaging factor (AF)
that can be used to generate a required ADC output rate. This restriction limits the minimum ADC update in normal power mode to 4 Hz or 1 Hz in lower power mode.
In low power mode and low power plus mode, the ADC is driven directly by the low power oscillator (131 kHz) and not 512 kHz. All fADC calculations should be divided
by 4 (approx).
Table 38. ADC Conversion Rates and Settling Times
Chop
Enabled
No
Averaging
Factor
No
Running
Average
No
No
No
No
tSETTLING 1
fADC Normal Mode
fADC Low Power Mode
512,000
[SF + 1] × 64
131,072
[SF + 1] × 64
3
f ADC
Yes
512,000
[SF + 1] × 64
131,072
[SF + 1] × 64
4
f ADC
Yes
No
512,000
[SF + 1] × 64 × [3 + AF ]
131,072
[SF + 1]× 64×[3 + AF]
1
f ADC
No
Yes
Yes
512,000
[SF + 1] × 64 × [3 + AF ]
131,072
[SF + 1]× 64 ×[3 + AF]
2
f ADC
Yes
N/A
N/A
512,000
[SF + 1]× 64 ×[3 + AF ] + 3
131,072
[SF + 1]× 64 ×[3 + AF] + 3
2
f ADC
1
An additional time of approximately 60 μs per ADC is required before the first ADC is available.
Table 39. Allowable Combinations of SF and AF
AF Range
SF
0 to 31
32 to 63
64 to 127
0
Yes
Yes
Yes
1 to 7
Yes
Yes
No
8 to 63
Yes
No
No
Rev. PrC | Page 39 of 96
ADuC7060/ADuC7061
Preliminary Technical Data
ADC Configuration Register
Name:
ADCCFG
Address:
0xFFFF0518
Default value:
0x00
Access:
Read/write
Function:
The 8-bit ADC configuration MMR controls extended functionality related to the on-chip ADCs.
Table 40. ADCCFG MMR Bit Designations
Bit
7
Name
GNDSW_EN
6, 5
ADC0ACCEN[1:0]
Description
Analog ground switch enable.
This bit is set to 1 by user software to connect the external GND_SW pin to an internal analog ground reference
point. This bit can be used to connect and disconnect external circuits and components to ground under
program control and thereby minimize dc current consumption when the external circuit or component is not
being used. This bit is used in conjunction with ADCCFG[1] to select a 20 kΩ resistor to ground.
When this bit is cleared, the analog ground switch is disconnected from the external pin.
Primary channel (32-bit) accumulator enable.
[00] = accumulator disabled and reset to 0.
The accumulator must be disabled for a full ADC conversion, (ADCSTA[0] set twice) before the accumulator can
be re-enabled to ensure the accumulator is reset.
[01] = accumulator active.
Positive current values are added to the accumulator total; the accumulator can overflow if allowed to run for
>65,535 conversions.
Negative current values are subtracted from the accumulator total; the accumulator is clamped to a minimum
value of 0.
[10] = accumulator active. Same as [01] except there is no clamp.
Positive current values are added to the accumulator total; the accumulator can overflow if allowed to run for
>65,535 conversions.
The absolute values of negative current are subtracted from the accumulator total; the accumulator in this mode
continues to accumulate negatively, below 0.
4, 3
ADC0CMPEN[1:0]
2
ADC0OREN
1
GNDSW_RES_EN
0
ADCRCEN
[11] = accumulator and comparator active. This causes an ADC0 interrupt if ADCMSK[6] is set.
Primary ADC comparator enable bit.
[00] = comparator disabled.
[01] = comparator active. Interrupt asserted if absolute value of ADC0 conversion result |I| ≥ ADCOTHRESH.
[10] = comparator count mode active. Interrupt asserted if absolute value of an ADC0 conversion result |I| ≥
ADCOTHRESH for the number of ADCOTHCNT conversions. A conversion value |I| < ADCOTHRESH resets the
threshold counter value (ADCOTHVAL) to 0.
[11] = comparator count mode active, interrupt asserted if absolute value of an ADC0 conversion result |I| ≥
ADCOTHRESH for the number of ADCOTHCNT conversions. A conversion value |I| < ADCOTHRESH decrements
the threshold counter value (ADCOTHVAL) towards 0.
ADC0 overrange enable.
Set by user to enable a coarse comparator on the Primary Channel ADC. If the reading is grossly (>30% approx.)
overrange for the active gain setting, then the overrange bit in the ADCSTA MMR is set. The ADC reading must be
outside this range for greater than 125 μs for the flag to be set.
This feature should not be used in ADC low power mode.(TBC)
Set to 1 to enable 20 kΩ resistor in series with the ground switch.
Clear this bit to disable this resistor.
ADC result counter enable.
Set by user to enable the result count mode. ADC interrupts occur if ADCORCR = ADCORCV.
Cleared to disable the result counter. ADC interrupts occur after every conversion.
Rev. PrC | Page 40 of 96
Preliminary Technical Data
ADuC7060/ADuC7061
Primary Channel ADC Data Register
Primary Channel ADC Offset Calibration Register
Name:
ADC0DAT
Name:
ADC0OF
Address:
0xFFFF051C
Address:
0xFFFF0524
Default Value:
0x0000-0000
Default Value:
Part specific, factory programmed
Access:
Read only
Access:
Read/write access
Function:
This ADC Data MMR holds the 24/16-bit
conversion result from the primary ADC. The
ADC does not update this MMR if the ADC0
conversion result ready bit (ADCSTA[0]) is
set. A read of this MMR by the MCU clears
all asserted ready flags (ADCSTA[2:0]).
Function:
This ADC offset MMR holds a 16-bit offset
calibration coefficient for the Primary ADC.
The register is configured at power-on with a
factory default value. However, this register
automatically overwrites if an offset
calibration of the Primary ADC is initiated by
the user via bits in the ADCMDE MMR. User
code can only write to this calibration register
if the ADC is in idle mode. An ADC must be
enabled and in idle mode before being
written to any offset or gain register. The
ADC must be in idle mode for at least 23 μs.
Table 41. ADC0DAT MMR Bit Designations
Bits
23 to 0
Description
ADC0 24-/16-bit conversion result
Auxiliary Channel ADC Data Register
Name:
ADC1DAT
Table 43. ADC0OF MMR Bit Designations
Address:
0xFFFF0520
Bits
15 to 0
Default Value:
0x0000-0000
Access:
Read only
Function:
This ADC Data MMR holds the 24-bit
conversion result from the Auxiliary ADC.
The ADC does not update this MMR if the
ADC0 conversion result ready bit
(ADCSTA[1]) is set. A read of this MMR by
the MCU clears all asserted ready flags
(ADCSTA[2:1]).
Description
ADC0 16-bit calibration offset value.
Auxiliary Channel ADC Offset Calibration Register
Name:
ADC1OF
Address:
0xFFFF0528
Default Value:
Part specific, factory programmed
Access:
Read/write access
Function:
This offset MMR holds a 16-bit offset
calibration coefficient for auxiliary channel.
The register is configured at power-on with a
factory default value. However, this register is
automatically overwritten if an offset
calibration of the auxiliary channel is
initiated by the user via bits in the ADCMDE
MMR. User code can only write to this
calibration register if the ADC is in idle
mode. An ADC must be enabled and in idle
mode before being written to any offset or
gain register. The ADC must be in idle mode
for at least 23 μs.
Table 42. ADC1DAT MMR Bit Designations
Bits
23 to 0
Description
ADC1 24-bit conversion result
Table 44. ADC1OF MMR Bit Designations
Bits
15 to 0
Description
ADC1 16-bit calibration offset value.
Primary Channel ADC Gain Calibration Register
Name:
Rev. PrC | Page 41 of 96
ADC0GAIN
ADuC7060/ADuC7061
Preliminary Technical Data
Address:
0xFFFF052C
Default Value:
0x0001
Default Value:
Part specific, factory programmed
Access:
Read/write
Access:
Read/write
Function:
Function:
This gain MMR holds a 16-bit gain
calibration coefficient for scaling the primary
ADC conversion result. The register is
configured at power-on with a factory default
value. However, this register is automatically
overwritten if a gain calibration of the
primary ADC is initiated by the user via bits
in the ADCMDE MMR. User code can only
write to this calibration register if the ADC is
in idle mode. An ADC must be enabled and
in idle mode before being written to any
offset or gain register. The ADC must be in
idle mode for at least 23 μs.
This 16-bit MMR sets the number of
conversions required before an ADC
interrupt is generated. By default, this
register is set to 0x01. The ADC counter
function must be enabled via the ADC result
counter enable bit in the ADCCFG MMR.
Table 47. ADC0RCR MMR Bit Designations
Bits
15 to 0
Description
ADC0 Result Counter Limit/Re-Load register.
Primary Channel ADC Result Count Register
Name:
ADCORCV
Address:
0xFFFF0538
Table 45. ADC0GAIN MMR Bit Designations
Default Value:
0x0000
Bits
15 to 0
Access:
Read only
Function:
This 16-bit, read only MMR holds the
current number of primary ADC conversion
results. It is used in conjunction with
ADC0RCR to mask Primary Channel ADC
interrupts, generating a lower interrupt rate.
When ADC0RCV = ADC0RCR, the value in
ADC0RCV resets to 0 and recommences
counting. It can also be used in conjunction
with the accumulator (ADC0ACC) to allow
an average calculation to be undertaken. The
result counter is enabled via ADCCFG[0].
This MMR is also reset to 0 when the
Primary-ADC is reconfigured, that is, when
the ADC0CON or ADCMDE are written.
Description
ADC0 16-bit Calibration Gain Value.
Auxiliary Channel Gain Calibration Register
Name:
ADC1GAIN
Address:
0xFFFF0530
Default Value:
Part specific, factory programmed
Access:
Read/write
Function:
This gain MMR holds a 16-bit gain
calibration coefficient for scaling an Auxiliary
channel conversion result. The register is
configured at power-on with a factory default
value. However, this register is automatically
overwritten if a gain calibration of the
Auxiliary channel is initiated by the user via
bits in the ADCMDE MMR. User code can
only write to this calibration register if the
ADC is in idle mode. An ADC must be
enabled and in idle mode before being
written to any offset or gain register. The
ADC must be in idle mode for at least 23 μs.
Table 48. ADCORCV MMR Bit Designations
Bits
15 to 0
Table 46. ADC1GAIN MMR Bit Designations
Bits
15 to 0
Description
ADC1 16-bit Calibration Gain Value.
Primary Channel ADC Result Counter Limit Register
Name:
ADCORCR
Address:
0xFFFF0534
Rev. PrC | Page 42 of 96
Description
ADC0 Result Counter register.
Preliminary Technical Data
ADuC7060/ADuC7061
Primary Channel ADC Threshold Register
Primary Channel ADC Threshold Count Register
Name:
ADCOTHRESH
Name:
ADCOTHVAL
Address:
0xFFFF053C
Address:
0xFFFF0544
Default Value:
0x0000
Default Value:
0x00
Access:
Read/write
Access:
Read only
Function:
This 16-bit MMR sets the threshold against
which the absolute value of the Primary ADC
conversion result is compared. In Unipolar
mode ADC0TH[15:0] are compared, and in
twos complement mode, ADC0TH[14:0] are
compared.
Function:
This 8-bit MMR is incremented every time
the absolute value of a primary ADC
conversion result |Result| ≥ ADC0TH. This
register is decremented or reset to 0 every
time the absolute value of a primary ADC
conversion result |Result| < ADC0TH. The
configuration of this function is enabled via
the Primary Channel ADC comparator bits in
the ADCCFG MMR.
Table 49. ADCOTHRESH MMR Bit Designations
Bits
15 to 0
Description
ADC0 16-bit comparator threshold register.
Table 51. ADCOTHVAL MMR Bit Designations
Name:
ADCOTHCNT
Bits
7 to 0
Address:
0xFFFF0540
Primary Channel ADC Accumulator Register
Default Value:
0x01
Name:
ADC0ACC
Access:
Read/write
Address:
0xFFFF0548
Function:
This 8-bit MMR determines how many
cumulative (values below the threshold
decrement or reset the count to 0) primary
ADC conversion result readings above
ADC0TH must occur before the primary
ADC comparator threshold bit is set in the
ADCSTA MMR generating an ADC
interrupt. The primary ADC comparator
threshold bit is asserted as soon as the
ADC0THV = ADC0TCL.
Default
Value:
0x00000000
Access:
Read only
Function:
This 32-bit MMR holds the primary ADC
accumulator value. The primary ADC ready bit in
the ADCSTA MMR should be used to determine
when it is safe to read this MMR. The MMR value
is reset to 0 by disabling the accumulator in the
ADCCFG MMR or reconfiguring the Primary
Channel ADC.
Primary Channel ADC Threshold Count Limit Register
Table 50. ADCOTHCNT MMR Bit Designations
Bits
7 to 0
Description
ADC0 8-bit threshold counter limit register.
Description
ADC0 8-bit threshold exceeded counter register.
Table 52. ADC0ACC MMR Bit Designations
Bits
31 to 0
Rev. PrC | Page 43 of 96
Description
ADC0 32-bit Threshold Exceeded Counter Register.
ADuC7060/ADuC7061
Preliminary Technical Data
Primary Channel ADC Comparator Threshold Register
Table 53. ADCOATH MMR Bit Designations
Name:
ADCOATH
Bits
31 to 0
Address:
0xFFFF054C
Default
Value:
0x00000000
Access:
Read/Write
Function:
This 32-bit MMR holds the Threshold value for the
accumulator comparator of the primary channel.
When the accumulator value in ADC0ACC
exceeds the value in ADC0ATH, the ADC0ATHEX
bit ADCSTA is set. This causes an interrupt if the
corresponding bit in ADCMSKI is also enabled.
FAST
OVERRANGE
AIN0
AIN1
MAIN
ADC
fADC
Description
ADC0 32-bit comparator threshold register of the
accumulator.
INTERRUPT
(ADC0OR)
16
fADC
(READABLE)
ADC0ACC
ACCUMULATOR
32
≥
INTERRUPT
(ADC0ATHEX)
(READABLE)
ADC0ATH
fADC
ADC0RC
(DEFAULT = 1)
≥
INTERRUPT
(ADC*RDY)
≥
fADC
ADC0TH
ADC0THCNT
UP/DOWN
OPTION: UP/RESET
≥
ADC0THC
Figure 11. Primary ADC Accumulator/Comparator/Counter Block Diagram
Rev. PrC | Page 44 of 96
INTERRUPT
(ADC0THEX)
07079-011
CLEAR
|ABSVAL|
ADC0RC
COUNTER
Preliminary Technical Data
ADuC7060/ADuC7061
Table 54. ADCOTHCNT MMR Bit Designations
Table 56. ADC0ACC MMR Bit Designations
Bits
7 to 0
Bits
31 to 0
Description
ADC0 8-bit threshold counter limit register
Primary Channel ADC Comparator Threshold Register
Primary Channel ADC Threshold Count Register
Name:
ADCOTHVAL
Address:
0xFFFF0544
Default value:
0x00
Access:
Read only
Function:
This 8-bit MMR increments every time the
absolute value of a primary ADC conversion
result attains |Result| ≥ ADC0TH. This register
decrements or resets to 0 every time the
absolute value of a primary ADC conversion
result level is |Result| < ADC0TH. The
configuration of this function is enabled via the
primary channel ADC comparator bits in the
ADCCFG MMR.
Table 55. ADCOTHVAL MMR Bit Designations
Bits
7 to 0
Description
ADC0 32-bit threshold exceeded counter register
Description
ADC0 8-bit threshold exceeded counter
register.
Name:
ADCOATH
Address:
0xFFFF054C
Default value:
0x00000000
Access:
Read/write
Function:
This 32-bit MMR holds the threshold value for
the primary channel accumulator comparator.
When the accumulator value in ADC0ACC
exceeds the value in ADC0ATH, the
ADC0ATHEX bit, ADCSTA, is set causing
an interrupt if the corresponding bit in
ADCMSKI is also enabled.
Table 57. ADCOATH MMR Bit Designations
Bits
31 to 0
Description
ADC0 32-bit accumulator comparator threshold
register.
Excitation Current Sources Control Register
Primary Channel ADC Accumulator Register
Name:
IEXCON
Address:
0xFFFF0570
Name:
ADC0ACC
Address:
0xFFFF0548
Default
Value:
0x00
Default value
0x00000000
Access:
Read/write
Access:
Read only
Function:
Function:
This 32-bit MMR holds the primary ADC
accumulator value. Use the primary ADC ready
bit in the ADCSTA MMR to determine when it
is safe to read this MMR. The MMR value is
reset to 0 by disabling the accumulator in the
ADCCFG MMR or reconfiguring the Primary
Channel ADC.
This 8-bit MMR controls the two excitation current
sources, IEXC0 and IEXC1.
Table 58. IEXCON MMR Bit Designations
Bits
7
Name
IEXC1_EN
6
IEXC0_EN
5
IEXC1_DIR
4
IEXC0_DIR
Description
Enable bit for IEXC1 current source.
Set this bit = 1 to enable Excitation Current Source 1.
Clear this bit to disable Excitation Current Source 1.
Enable bit for IEXC0 current source.
Set this bit = 1 to enable Excitation Current Source 0.
Clear this bit to disable Excitation Current source 0.
Set this bit =1 to direct Excitation Current Source 1 to the IEXC0 pin.
Set this bit = 0 to direct Excitation Current Source 1 to the IEXC1 pin.
Set this bit = 1 to direct Excitation Current Source 0 to the IEXC1 pin.
Set this bit = 0 to direct Excitation Current Source 0 to the IEXC0 pin.
Rev. PrC | Page 45 of 96
ADuC7060/ADuC7061
IOUT[0]
EXAMPLE APPLICATION CIRCUITS
Figure 12 shows a simple bridge sensor interface to the ADuC706x
including the RC filters on the analog input channels. Notice
that the sense lines from the bridge (connecting to the reference
inputs) are wired separately from the excitation lines (going to
VDD and ground). This results in a total of six wires going to
the bridge. This 6-wire connection scheme is a feature of most
off-the-shelf bridge transducers (such as load cells) that helps to
minimize errors that would otherwise result from wire
impedances.
+2.5V
ADuC7060/
ADuC7061/
ADuC7062
VDD
REFIN+
AIN0
AIN1
SPI
I2C
UART
GPIO
ETC.
REFIN–
GND
In Figure 13, AD592 is an external temperature sensor used to
measure the thermocouples cold junction and its output is
connected to the auxiliary channel. ADR280 is an external 1.2 V
reference part—alternatively, the internal reference can be used
also. Here, the thermocouple is connected to the primary ADC
as a differential input to ADC0/ADC1. Note the resistor
between REFIN+ and ADC1 to bias the ADC inputs above
100 mV.
07079-012
0
Description
These bits control the Excitation current level for each source.
IOUT[3:1] = 000, excitation current = 0 μA + (IOUT[0] × 10 μA)
IOUT[3:1] = 001, excitation current = 200 μA + (IOUT[0] × 10 μA)
IOUT[3:1] = 010, excitation current = 400 μA+ (IOUT[0] × 10 μA)
IOUT[3:1] = 011, excitation current = 600 μA+ (IOUT[0] × 10 μA)
IOUT[3:1] = 100, excitation current = 800 μA+ (IOUT[0] × 10 μA)
IOUT[3:1] = 101, excitation current = 1 mA + (IOUT[0] × 10 μA)
All other values are undefined.
Set this bit =1 to enable 10 μA diagnostic current source
Clear this bit =0 to disable 10 μA diagnostic current source.
Figure 12. Bridge Interface Circuit
ADuC7060/
ADuC7061/
ADuC7062
AIN0
AIN1
Figure 14 shows a simple 4-wire RTD interface circuit. As with
the bridge transducer implementation in Figure 12, if a power
supply and a serial connection to the outside world are added,
then Figure 14 represents a complete system.
AD592
ADR280
AIN4
+2.5V
VDD
SPI
I2C
UART
GPIO
ETC.
REFIN+
REFIN–
GND
07079-013
Name
IOUT[3:1]
Figure 13. Example of a Thermocouple Interface Circuit
ADuC7060/
ADuC7061/
ADuC7062
IEXC1
AIN0
RTD
AIN1
+2.5V
VDD
SPI
I2C
UART
GPIO
ETC.
REFIN+
REFIN–
GND
Figure 14. Example of an RTD Interface Circuit
Rev. PrC | Page 46 of 96
07079-014
Bits
3:1
Preliminary Technical Data
Preliminary Technical Data
ADuC7060/ADuC7061
DAC PERIPHERALS
DAC
Op Amp Mode
The ADuC706x incorporates a 12-bit voltage output DAC onchip. The DAC has a rail-to-rail voltage output buffer capable of
driving 5 kΩ/100 pF.
As an option, the DAC may be disabled and its output buffer
used as an op amp.
The DAC has four selectable ranges:
The DAC is configurable through a control register and a data
register.
•
•
•
•
0 V to VREF (internal band gap 1.2 V reference)
VREF− to VREF+
EXT_REF2− to EXT_REF2+
0 V to AVDD
MMR INTERFACE
DAC0CON Register
Name:
DAC0CON
Address:
0xFFFF0600
Default value:
0x0200
Access:
Read/write
The maximum signal range is 0 V to AVDD.
Table 59. DAC0CON MMR Bit Designations
Bit
15:10
9
Value
Name
DACPD
8
DACBUFLP
7
OPAMP
6
DACBUFBYPASS
5
DACCLK
4
/DACCLR
3
DACMODE
2
RATE
1:0
11
10
01
00
DAC Range bits
Description
Reserved.
Set to 1 to power down DAC output (DAC output is tristated).
Clear this bit to enable the DAC.
Set to 1 to place the DAC output buffer in low power mode. See the Normal DAC
Mode and Op Amp Mode sections for further details on electrical specifications.
Clear this bit to enable the DAC buffer.
Set to 1 to place the DAC output buffer in op-amp mode.
Clear this bit to enable the DAC output buffer for normal DAC operation.
Set to 1 to bypass the output buffer and send the DAC output directly to the
output pin.
Clear this bit to buffer the DAC output.
Set to 1 to update the DAC on the negative edge of HCLK.
Set to 0 to update the DAC on the negative edge of Timer1. This mode is ideally
suited for waveform generation where the next value in the waveform is written
to DAC0DAT at regular intervals of Timer1.
Set to 0 to clear the DAC output and DACDATto 0. Writing to this bit has an
immediate effect on the DAC output.
Set to 1 to enable DAC in 16-bit interpolation mode.
Set to 0 to enable DAC in normal 12-bit mode.
Used with Interpolation Mode.
Set to 1 to configure the interpolation clock as UCLK/16.
Set to 0 to configure the interpolation clock as UCLK/32.
0 V to AVDD Range.
EXT_REF2- to EXT_REF2+.
VREF− to VREF+.
0 V to VREF (1.2 V) range. (Internal reference source.)
Rev. PrC | Page 47 of 96
ADuC7060/ADuC7061
Preliminary Technical Data
DAC0DAT Register
Name:
DAC0DAT
Address:
0xFFFF0604
Default value:
0x00000000
Access:
Read/Write
Function:
This 32-bit MMR contains the DAC output
value.
Table 60. DAC0DAT MMR Bit Designations
Bit
31:28
27:16
15:12
11:0
Description
Reserved.
12-Bit Data for DAC0.
Extra four 4 bits used in interpolation mode.
Reserved.
0-to-AVDD mode only, Code 3995 to Code 4095. Linearity
degradation near ground and VDD is caused by saturation of the
output amplifier, and a general representation of its effects
(neglecting offset and gain error) is illustrated in Figure 15. The
dotted line in Figure 15 indicates the ideal transfer function, and
the solid line represents what the transfer function may look
like with endpoint nonlinearities due to saturation of the output
amplifier. Note that Figure 15 represents a transfer function in
0-to-AVDD mode only. In 0-to-VREF or, VRef± and Ext_Ref2±
modes (with VREF < AVDD or Ext_Ref+/Ext_Ref2+ < AVDD), the
lower nonlinearity is similar. However, the upper portion of the
transfer function follows the ideal line right to the end (VREF in this
case, not AVDD), showing no signs of endpoint linearity errors.
AVDD
AVDD – 100mV
Using the DAC
The on-chip DAC architecture consists of a resistor string DAC
followed by an output buffer amplifier. The functional equivalent
is shown in the figure below:
•
•
•
100mV
In 0-to-AVDD mode, the DAC output transfer function
spans from 0 V to the voltage at the AVDD pin.
In VREF± and Ext_Ref2±.modes, the DAC output transfer
function spans from negative input voltage to the voltage
positive input pin. Note that these voltages must never go
below 0 V or above AVDD.
In 0-to-VREF mode, the DAC output transfer function spans
from 0 V to the internal 1.2 V reference, VREF.
The DAC may be configured in three different user modes:
normal mode, DAC interpolation mode, and op-amp mode.
Normal DAC Mode
In this mode of operation, the DAC is configured as a 12-bit
voltage output DAC. By default, the DAC buffer is enabled but,
the output buffer can be disabled. If the DAC output buffer is
disabled, the DAC is only capable of driving a capacitive load of
20 pF. The DAC buffer is disabled by setting the
DACBUFBYPASS bit in DAC0CON.
The DAC output buffer amplifier features a true, rail-to-rail
output stage implementation. This means that when unloaded,
each output is capable of swinging to within less than 5 mV of
both AVDD and ground. Moreover, the DAC’s linearity specification
(when driving a 5 kΩ resistive load to ground) is guaranteed
through the full transfer function except codes 0 to 100, and, in
0x00000000
0x0FFF0000
07079-015
The reference source for the DAC is user-selectable in software. It
can be either AVDD, VREF± or Ext_Ref2±.
Figure 15. Endpoint Nonlinearities Due to Amplifier Saturation
The endpoint nonlinearities conceptually illustrated in Figure 15
worsen as a function of output loading. Most of the ADuC7060/
ADuC7061 data sheet specifications in normal mode assume a
5 kΩ resistive load to ground at the DAC output. As the output
is forced to source or sink more current, the nonlinear regions at
the top or bottom (respectively) of Figure 15 become larger.
With larger current demands, this can significantly limit output
voltage swing.
DAC Interpolation Mode
In interpolation mode, a higher DAC output resolution of 16
bits is achieved with a longer update rate than normal mode.
The update rate is controlled by the interpolation clock rate
selected in the DAC0CON register. In this mode, an external
RC filter is required to create a contstant voltage.
Op Amp Mode
In op amp mode, the DAC output buffer is used as an op-amp
with the DAC itself disabled.
ADC6 is the positive input to the op-amp, ADC7 is the negative
input and ADC8 is the output. In this mode, the DAC should be
powered down by setting Bit 9 of DAC0CON.
Rev. PrC | Page 48 of 96
Preliminary Technical Data
ADuC7060/ADuC7061
NONVOLATILE FLASH/EE MEMORY
Overall, Flash/EE memory represents a step closer to the
ideal memory device that includes nonvolatility, in-circuit
programmability, high density, and low cost. Incorporated in
the ADuC706x, Flash/EE memory technology allows the user
to update program code space in-circuit, without the need to
replace one time programmable (OTP) devices at remote
operating nodes.
Each part contains a 64 kB array of Flash/EE memory. The
lower 62 kB is available to the user and the upper 2 kB contain
permanently embedded firmware, allowing in-circuit serial
download. These 2 kB of embedded firmware also contain a
power-on configuration routine that downloads factorycalibrated coefficients to the various calibrated peripherals
(such as ADC, temperature sensor, and band gap references).
This 2 kB embedded firmware is hidden from user code.
600
0
The Flash/EE memory arrays on the parts are fully qualified for
two key Flash/EE memory characteristics: Flash/EE memory
cycling endurance and Flash/EE memory data retention.
Endurance quantifies the ability of the Flash/EE memory to be
cycled through many program, read, and erase cycles. A single
endurance cycle is composed of four independent, sequential
events, defined as
Initial page erase sequence.
Read/verify sequence a single Flash/EE.
Byte program sequence memory.
Second read/verify sequence endurance cycle.
In reliability qualification, every half word (16-bit wide)
location of the three pages (top, middle, and bottom) in the
Flash/EE memory is cycled 10,000 times from 0x0000 to
0xFFFF. The Flash/EE memory endurance qualification is
carried out in accordance with JEDEC Retention Lifetime
Specification A117 over the industrial temperature range of
−40° to +125°C. The results allow the specification of a
minimum endurance figure over a supply temperature of
10,000 cycles.
300
150
FLASH/EE MEMORY RELIABILITY
•
•
•
•
450
30
40
55
70
85
100
125
JUNCTION TEMPERATURE (°C)
135
150
07079-016
Like EEPROM, flash memory can be programmed in-system
at a byte level, although it must first be erased. The erase is
performed in page blocks. As a result, flash memory is often,
and more correctly referred to as Flash/EE memory.
Retention quantifies the ability of the Flash/EE memory to
retain its programmed data over time. Again, the parts are
qualified in accordance with the formal JEDEC Retention
Lifetime Specification A117 at a specific junction temperature
(TJ = 85°C). As part of this qualification procedure, the
Flash/EE memory is cycled to its specified endurance limit,
described previously, before data retention is characterized.
This means that the Flash/EE memory is guaranteed to retain
its data for its fully specified retention lifetime every time the
Flash/EE memory is reprogrammed. Also note that retention
lifetime, based on activation energy of 0.6 eV, derates with TJ as
shown in Figure 16.
RETENTION (Years)
The ADuC706x incorporates Flash/EE memory technology
on-chip to provide the user with nonvolatile, in-circuit reprogrammable memory space.
Figure 16. Flash/EE Memory Data Retention
PROGRAMMING
The 62 kB of Flash/EE memory can be programmed in-circuit,
using the serial download mode or the provided JTAG mode.
Serial Downloading (In-Circuit Programming)
The ADuC7060/ADuC7061 facilitate code download via the
standard UART serial port. The parts enter serial download
mode after a reset or power cycle if the BM pin is pulled low
through an external 1 kΩ resistor. When in serial download
mode, the user can download code to the full 62 kB of Flash/EE
memory while the device is in-circuit in its target application
hardware. An executable PC serial download is provided as part
of the development system for serial downloading via the
UART.
JTAG Access
The JTAG protocol uses the on-chip JTAG interface to facilitate
code download and debug.
Rev. PrC | Page 49 of 96
ADuC7060/ADuC7061
Preliminary Technical Data
PROCESSOR REFERENCE PERIPHERALS
INTERRUPT SYSTEM
IRQ
There are 15 interrupt sources on the ADuC706x that are
controlled by the interrupt controller. All interrupts are
generated from the on-chip peripherals, except for the software
interrupt (SWI) which is programmable by the user. The
ARM7TDMI CPU core only recognizes interrupts as one of two
types: a normal interrupt request (IRQ) and a fast interrupt
request (FIQ). All the interrupts can be masked separately.
The IRQ is the exception signal to enter the IRQ mode of the
processor. It services general-purpose interrupt handling of
internal and external events.
The control and configuration of the interrupt system is
managed through a number of interrupt-related registers. The
bits in each IRQ and FIQ register represent the same interrupt
source as described in Table 61.
The ADuC706x contains a vectored interrupt controller (VIC)
that supports nested interrupts up to eight levels. The VIC also
allows the programmer to assign priority levels to all interrupt
sources. Interrupt nesting needs to be enabled by setting the
ENIRQN bit in the IRQCONN register. A number of extra
MMRs are used when the full vectored interrupt controller is
enabled.
All 32 bits are logically OR’ed to create a single IRQ signal to the
ARM7TDMI core. The four 32-bit registers dedicated to IRQ
follow.
IRQSIG
IRQSIG reflects the status of the different IRQ sources. If a
peripheral generates an IRQ signal, the corresponding bit in
the IRQSIG is set; otherwise, it is cleared. The IRQSIG bits clear
when the interrupt in the particular peripheral is cleared. All
IRQ sources can be masked in the IRQEN MMR. IRQSIG is
read only.
IRQSIG Register
Name:
IRQSIG
Address:
0xFFFF0004
IRQSTA/FIQSTA should be saved immediately upon entering
the interrupt service routine (ISR) to ensure that all valid
interrupt sources are serviced.
Default value:
0x00000000
Access:
Read only
Table 61. IRQ/FIQ MMRs Bit Designations
IRQEN
Bit
0
IRQEN provides the value of the current enable mask. When a
bit is set to 1, the corresponding source request is enabled
to create an IRQ exception. When a bit is set to 0, the corresponding source request is disabled or masked which does not
create an IRQ exception. The IRQEN register cannot be used to
disable an interrupt.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
Description
All interrupts OR’ed
(FIQ only)
Software Interrupt
Undefined
Timer0
Timer1 or wake-up
timer
Timer2 or watchdog
timer
Timer3 or STI timer
Undefined
Undefined
Undefined
ADC
UART
SPI
XIRQ0 (GPIO IRQ0 )
XIRQ1 (GPIO IRQ1)
I2C Master IRQ
I2C Slave IRQ
PWM
XIRQ2 (GPIO IRQ2 )
XIRQ3 (GPIO IRQ3)
Comments
This bit is set if any FIQ is active
User programmable interrupt
source
This bit is not used
General-Purpose Timer 0
General-Purpose Timer 1 or
wake-up timer
General-Purpose Timer 2 or
watchdog timer
General-Purpose Timer 3
This bit is not used
This bit is not used
This bit is not used
ADC interrupt source bit
UART interrupt source bit
SPI interrupt source bit
External Interrupt 0
External Interrupt 1
I2C master interrupt source bit
I2C slave interrupt source bit
PWM Trip interrupt source bit
External Interrupt 2
External Interrupt 3
IRQEN Register
Name:
IRQEN
Address:
0xFFFF0008
Default value:
0x00000000
Access:
Read/write
IRQCLR
IRQCLR is a write-only register that allows the IRQEN register
to clear in order to mask an interrupt source. Each bit that is set
to 1 clears the corresponding bit in the IRQEN register without
affecting the remaining bits. The pair of registers, IRQEN and
IRQCLR, allows independent manipulation of the enable mask
without requiring an atomic read-modify-write.
Rev. PrC | Page 50 of 96
Preliminary Technical Data
ADuC7060/ADuC7061
IRQCLR Register
FIQSIG RegisterPrC
Name:
IRQCLR
Name:
FIQSIG
Address:
0xFFFF000C
Address:
0xFFFF0104
Default value:
0x00000000
Default value:
0x00000000
Access:
Write only
Access:
Read only
IRQSTA
FIQEN
IRQSTA is a read-only register that provides the current
enabled IRQ source status (effectively a logic AND of the
IRQSIG and IRQEN bits). When set to 1, that source generates
an active IRQ request to the ARM7TDMI core. There is no
priority encoder or interrupt vector generation. This function is
implemented in software in a common interrupt handler
routine.
FIQEN provides the value of the current enable mask. When a
bit is set to 1, the corresponding source request is enabled
to create an FIQ exception. When a bit is set to 0, the corresponding source request is disabled or masked which does not
create an FIQ exception. The FIQEN register cannot be used to
disable an interrupt.
IRQSIG Register
Name:
FIQEN
Address:
0xFFFF0108
Default value:
0x00000000
Access:
Read/write
Name:
IRQSTA
Address:
0xFFFF0000
Default value:
0x00000000
Access:
Read only
FIQEN Register
FIQCLR
FAST INTERRUPT REQUEST (FIQ)
The fast interrupt request (FIQ) is the exception signal to enter
the FIQ mode of the processor. It is provided to service data
transfer or communication channel tasks with low latency. The
FIQ interface is identical to the IRQ interface and provides the
second level interrupt (highest priority). Four 32-bit registers
are dedicated to FIQ: FIQSIG, FIQEN, FIQCLR, and FIQSTA.
FIQCLR is a write-only register that allows the FIQEN register
to clear in order to mask an interrupt source. Each bit that is set
to 1 clears the corresponding bit in the FIQEN register without
affecting the remaining bits. The pair of registers, FIQEN and
FIQCLR, allows independent manipulation of the enable mask
without requiring an atomic read-modify-write.
FIQCLR Register
Bit 31 to Bit 1 of FIQSTA are logically OR’ed to create the FIQ
signal to the core and to Bit 0 of both the FIQ and IRQ registers
(FIQ source).
Name:
FIQCLR
Address:
0xFFFF010C
The logic for FIQEN and FIQCLR does not allow an interrupt
source to be enabled in both IRQ and FIQ masks. A bit set to 1
in FIQEN clears, as a side effect, the same bit in IRQEN.
Likewise, a bit set to 1 in IRQEN clears, as a side effect, the
same bit in FIQEN. An interrupt source can be disabled in both
IRQEN and FIQEN masks.
Default value:
0x00000000
Access:
Write only
FIQSIG
FIQSIG reflects the status of the different FIQ sources. If a
peripheral generates an FIQ signal, the corresponding bit in
the FIQSIG is set, otherwise it is cleared. The FIQSIG bits are
cleared when the interrupt in the particular peripheral is
cleared. All FIQ sources can be masked in the FIQEN MMR.
FIQSIG is read only.
FIQSTA
FIQSTA is a read-only register that provides the current enabled
FIQ source status (effectively a logic AND of the FIQSIG and
FIQEN bits). When set to 1, that source generates an active FIQ
request to the ARM7TDMI core. There is no priority encoder
or interrupt vector generation. This function is implemented in
software in a common interrupt handler routine.
FIQSTA Register
Name:
FIQSTA
Address:
0xFFFF0100
Default value:
0x00000000
Access:
Read only
Rev. PrC | Page 51 of 96
ADuC7060/ADuC7061
Preliminary Technical Data
Programmed Interrupts
enabled for both the FIQ and IRQ and prioritization is
maximized, then it is possible to have 16 separate interrupt
levels.
Programmable interrupt priorities—using the IRQP0 to
IRQP2 registers, an interrupt source can be assigned an
interrupt priority level value between 1 and 8.
Because the programmed interrupts are not maskable, they are
controlled by another register (SWICFG) that writes into both
IRQSTA and IRQSIG registers and/or the FIQSTA and FIQSIG
registers at the same time.
•
The 32-bit register dedicated to software interrupt is SWICFG
described in Table 62. This MMR allows the control of a
programmed source interrupt.
VIC MMRs
Table 62. SWICFG MMR Bit Designations
Bit
31 to 3
2
1
0
Description
Reserved.
Programmed Interrupt FIQ. Setting/clearing this bit
corresponds to setting/clearing Bit 1 of FIQSTA and
FIQSIG.
Programmed Interrupt IRQ. Setting/clearing this bit
corresponds to setting/clearing Bit 1 of IRQSTA and
IRQSIG.
Reserved.
Any interrupt signal must be active for at least the minimum
interrupt latency time, to be detected by the interrupt controller
and to be detected by the user in the IRQSTA/FIQSTA register.
IRQBASE Register
The vector base register, IRQBASE, is used to point to the start
address of memory used to store 32 pointer addresses. These
pointer addresses are the addresses of the individual interrupt
service routines.
Name:
IRQBASE
Address:
0xFFFF0014
Default value:
0x00000000
Access:
Read and write
Table 63. IRQBASE MMR Bit Designations
Bit
31:16
15:0
Type
Read only
R/W
Initial Value
Reserved
0
Description
Always read as 0
Vector base address
IRQVEC Register
The IRQ interrupt vector register, IRQVEC points to a memory
address containing a pointer to the interrupt service routine of
the currently active IRQ. This register should only be read when
an IRQ occurs and IRQ interrupt nesting has been enabled by
setting Bit 0 of the IRQCONN register.
Name:
IRQVEC
Address:
0xFFFF001C
Default value:
0x00000000
Vectored Interrupt Controller (VIC)
Access:
Read only
The ADuC7060 incorporates an enhanced interrupt control
system or vectored interrupt controller. The vectored interrupt
controller for IRQ interrupt sources is enabled by setting Bit 0
of the IRQCONN register. Similarly, Bit 1 of IRQCONN enables
the vectored interrupt controller for the FIQ interrupt sources.
The vectored interrupt controller provides the following
enhancements to the standard IRQ/FIQ interrupts:
Table 64. IRQVEC MMR Bit Designations
Figure 17. Interrupt Structure
•
•
Vectored interrupts—allows a user to define separate
interrupt service routine addresses for every interrupt
source. This is achieved by using the IRQBASE and
IRQVEC registers.
IRQ/FIQ interrupts—can be nested up to eight levels
depending on the priority settings. An FIQ still has a
higher priority than an IRQ. There fore, if the VIC is
Bit
31:23
22:7
Type
Read
only
R/W
Initial
value
0
0
6:2
Read
only
0
1:0
Reserved
0
Rev. PrC | Page 52 of 96
Description
Always read as 0.
IRQBASE register value.
Highest priorityIRQ source. This is
a value between 0 to 19 representing
the possible interrupt sources. For
example, if the highest currently
active IRQ is Timer 1, then these
bits are [01000].
Reserved bits.
Preliminary Technical Data
ADuC7060/ADuC7061
Priority Registers
The IRQ interrupt vector register, IRQVEC points to a memory
address containing a pointer to the interrupt service routine of
the currently active IRQ. This register should only be read when
an IRQ occurs and IRQ interrupt nesting has been enabled by
setting Bit 0 of the IRQCONN register.
IRQP0 Register
Name:
IRQP0
Address:
0xFFFF0020
Default value:
0x00000000
Access:
Read and write
Table 65. IRQP0 MMR Bit Designations
Bit
31:27
26:24
Name
Reserved
T3PI
23
22:20
Reserved
T2PI
19
18:16
Reserved
T1PI
15
14:12
Reserved
T0PI
11:7
6:4
Reserved
SWINTP
3:0
Reserved
Description
Reserved bits.
A priority level of 0 to 7 can be set for Timer
3.
Reserved bit.
A priority level of 0 to 7 can be set for Timer
2.
Reserved bit.
A priority level of 0 to 7 can be set for Timer
1.
Reserved bit.
A priority level of 0 to 7 can be set for Timer
0.
Reserved bits.
A priority level of 0 to 7 can be set for the
software interrupt source.
Interrupt 0 cannot be prioritized.
IRQP1 Register
Name:
IRQP1
Address:
0xFFFF0024
Default value:
0x00000000
Access:
Read and write
Table 66. IRQP1 MMR Bit Designations
Bit
31
30:28
Name
Reserved
I2CMPI
27
26:24
23
22:20
19
18:16
Reserved
IRQ1PI
Reserved
IRQ0PI
Reserved
SPIMPI
15
14:12
11
10:8
Reserved
UARTPI
Reserved
ADCPI
7:0
Reserved
Description
Reserved bit.
A priority level of 0 to 7 can be set for I2C
master.
Reserved bit.
A priority level of 0 to 7 can be set for IRQ1.
Reserved bit.
A priority level of 0 to 7 can be set for IRQ0.
Reserved bit.
A priority level of 0 to 7 can be set for SPI
master.
Reserved bit.
A priority level of 0 to 7 can be set for UART.
Reserved bit.
A priority level of 0 to 7 can be set for the
ADC interrupt source.
Reserved bits.
IRQP2 Register
Name:
IRQP2
Address:
0xFFFF0028
Default value:
0x00000000
Access:
Read and write
Table 67. IRQP2 MMR Bit Designations
Bit
31:15
14:12
11
10:8
7
6:4
Name
Reserved
IRQ3PI
Reserved
IRQ2PI
Reserved
SPISPI
3
2:0
Reserved
I2CSPI
Rev. PrC | Page 53 of 96
Description
Reserved bit.
A priority level of 0 to 7 can be set for IRQ3.
Reserved bit.
A priority level of 0 to 7 can be set for IRQ2.
Reserved bit.
A priority level of 0 to 7 can be set for SPI
slave.
Reserved bit.
A priority level of 0 to 7 can be set for I2C
slave.
ADuC7060/ADuC7061
Preliminary Technical Data
IRQCONN Register
FIQVEC Register
The IRQCONN register is the IRQ and FIQ control register. It
contains two active bits. The first to enable nesting and
prioritization of IRQ interrupts the other to enable nesting and
prioritization of FIQ interrupts.
The FIQ interrupt vector register, FIQVEC points to a memory
address containing a pointer to the interrupt service routine of
the currently active FIQ. This register should only be read when
an FIQ occurs and FIQ interrupt nesting has been enabled by
setting Bit 1 of the IRQCONN register.
If these bits are cleared, then FIQs and IRQs may still be used
but it is not possible to nest IRQs or FIQs. Neither is it possible
to set an interrupt source priority level. In this default state, an
FIQ does have a higher priority than an IRQ.
Name:
FIQVEC
Address:
0xFFFF011C
Name:
IRQCONN
Default value:
0x00000000
Address:
0xFFFF0030
Access:
Read only
Default value:
0x00000000
Table 70. FIQVEC MMR Bit Designations
Access:
Read and write
Bit
31:23
22:7
6:2
Type
Read only
R/W
Initial
Value
0
0
0
1:0
Reserved
0
Table 68. IRQCONN MMR Bit Designations
Bit
31:2
Name
Reserved
1
ENFIQN
0
ENIRQN
Description
These bits are reserved and should not be
written to.
Setting this bit to 1 enables nesting of FIQ
interrupts. Clearing this bit means no nesting
or prioritization of FIQs is allowed.
Setting this bit to 1 enables nesting of IRQ
interrupts. Clearing this bit means no nesting
or prioritization of IRQs is allowed.
IRQSTAN Register
If IRQCONN.0 is asserted and IRQVEC is read then one of
these bits is asserted. The bit that asserts depend on the priority
of the IRQ. If the IRQ is of Priority 0 then Bit 0 asserts, Priority 1
then Bit 1 asserts, and so forth. When a bit is set in this register,
all interrupts of that priority and lower are blocked.
Description
Always read as 0.
IRQBASE register value.
Highest PriorityFIQ Source. This is
a value between 0 to 19 represent
the possible interrupt sources. For
example, if the highest currently
active FIQ is Timer 1, then these
bits are [01000].
Reserved bits.
FIQSTAN Register
If IRQCONN.1 is asserted and FIQVEC is read then one of
these bits assert. The bit that asserts depends on the priority of
the FIQ. If the FIQ is of Priority 0 then Bit 0 asserts, Priority 1
then Bit 1 asserts, and so forth.
When a bit is set in this register all interrupts of that priority
and lower are blocked.
To clear a bit in this register, all bits of a higher priority must be
cleared first. It is only possible to clear one bit at a time. For
example, if this register is set to 0x09 then writing 0xFF changes
the register to 0x08, and writing 0xFF a second time changes
the register to 0x00.
To clear a bit in this register all bits of a higher priority must be
cleared first. It is only possible to clear one bit as a time. For
example if this register is set to 0x09 then writing 0xFF changes
the register to 0x08 and writing 0xFF a second time changes the
register to 0x00.
Name:
IRQSTAN
Name:
FIQSTAN
Address:
0xFFFF003C
Address:
0xFFFF013C
Default value:
0x00000000
Default value:
0x00000000
Access:
Read and write
Access:
Read and write
Table 71. FIQSTAN MMR Bit Designations
Table 69. IRQSTAN MMR Bit Designations
Bit
31:8
7:0
Name
Reserved
Description
These bits are reserved and should not be
written to.
Setting this bit to 1 enables nesting of FIQ
interrupts. Clearing this bit, means no nesting
or prioritization of FIQs is allowed.
Bit
31:8
7:0
Rev. PrC | Page 54 of 96
Name
Reserved
Description
These bits are reserved and should not be
written to.
Setting this bit to 1 enables nesting of FIQ
interrupts. Clearing this bit, means no nesting
or prioritization of FIQs is allowed.
Preliminary Technical Data
ADuC7060/ADuC7061
External Interrupts (IRQ0 to IRQ3)
IRQCONE Register
The ADuC706x provides up to four external interrupt sources.
These external interrupts can be individually configured as level
or rising/falling edge triggered.
Name:
IRQCONE
Address:
0xFFFF0034
To enable the external interrupt source, first of all, the
appropriate bit must be set in the FIQEN or IRQEN register. To
select the required edge or level to trigger on, the IRQCONE
register must be appropriately configured.
Default value:
0x00000000
Access:
Read and write
To properly clear an edge based external IRQ interrupt, set the
appropriate bit in the EDGELEVELCLR register.
Table 72. IRQCONEMMR Bit Designations
Bit
31:8
7:6
5:4
3:2
1:0
Value
11
10
01
00
11
10
01
00
11
10
01
00
11
10
01
00
Name
Reserved
IRQ3SRC[1:0]
IRQ2SRC[1:0]
IRQ1SRC[1:0]
IRQ0SRC[1:0]
Description
These bits are reserved and should not be written to.
External IRQ3 triggers on falling edge
External IRQ3 triggers on rising edge
External IRQ3 triggers on low level
External IRQ3 triggers on high level
External IRQ2 triggers on falling edge
External IRQ2 triggers on rising edge
External IRQ2 triggers on low level
External IRQ2 triggers on high level
External IRQ1 triggers on falling edge
External IRQ1 triggers on rising edge
External IRQ1 triggers on low level
External IRQ1 triggers on high level
External IRQ0 triggers on falling edge
External IRQ0 triggers on rising edge
External IRQ0 triggers on low level
External IRQ0 triggers on high level
Rev. PrC | Page 55 of 96
ADuC7060/ADuC7061
Preliminary Technical Data
IRQCLRE Register
Table 73. IRQCLRE MMR Bit Designations
Name:
IRQCLRE
Bit
31:20
Name
Reserved
Address:
0xFFFF0038
Default value:
0x00000000
19
IRQ3CLRI
Access:
Read and write
18
IRQ2CLRI
17:15
Reserved
14
IRQ1CLRI
13
IRQ0CLRI
12:0
Reserved
Rev. PrC | Page 56 of 96
Description
These bits are reserved and should not be
written to.
A 1 must be written to this bit in the IRQ3
interrupt service routine to clear an edge
triggered IRQ3 interrupt.
A 1 must be written to this bit in the IRQ2
interrupt service routine to clear an edge
triggered IRQ2 interrupt.
These bits are reserved and should not be
written to.
A 1 must be written to this bit in the IRQ1
interrupt service routine to clear an edge
triggered IRQ1 interrupt.
A 1 must be written to this bit in the IRQO
interrupt service routine to clear an edge
triggered IRQ0 interrupt.
These bits are reserved and should not be
written to.
Preliminary Technical Data
ADuC7060/ADuC7061
TIMERS
The ADuC706x features four general-purpose timer/counters.
Table 74. Timer Event Capture
•
•
•
•
Bit
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
Timer0
Timer1 or wake-up timer
Timer2 or watchdog timer
Timer3
The four timers in their normal mode of operation can either be
free running or periodic.
In free running mode, the counter decrements/increments from
the maximum or minimum value until zero/full scale and starts
again at the maximum or minimum value.
In periodic mode, the counter decrements/increments from the
value in the load register (TxLD MMR,) until zero/full scale and
starts again at the value stored in the load register. Note that the
TxLD MMR should be configured before the TxCON MMR.
The value of a counter can be read at any time by accessing its
value register (TxVAL). Timers are started by writing in the
control register of the corresponding timer (TxCON).
In normal mode, an IRQ is generated each time the value of the
counter reaches zero (if counting down) or full scale (if
counting up). An IRQ can be cleared by writing any value to the
clear register of the particular timer (TxCLRI).
Rev. PrC | Page 57 of 96
Description
Reserved
Timer0
Timer1 or wake-up timer
Timer2 or watchdog timer
Timer3
Reserved
Reserved
Reserved
ADC
UART
SPI
XIRQ0
XIRQ1
I2C Master
I2C Slave
PWM
XIRQ2 (GPIO IRQ2)
XIRQ3 (GPIO IRQ3)
ADuC7060/ADuC7061
Preliminary Technical Data
TIMER0
Timer0 reloads the value from T0LD when Timer0 overflows.
Timer0 is a 32-bit general-purpose timer, count down or count
up, with a programmable prescaler. The prescaler source can be
the low power 32.768 kHz oscillator, the core clock, or from one
of two external GPIOs. This source can be scaled by a factor of
1, 16, 256, or 32,768. This gives a minimum resolution of 97.66 ns
with a prescaler of 1 (ignoring the external GPIOs).
Timer0 Load Registers
The counter can be formatted as a standard 32-bit value or as
hours:minutes:seconds:hundredths.
Timer0 has a capture register (T0CAP) that is triggered by a
selected IRQ source initial assertion. When triggered, the current
timer value is copied to T0CAP, and the timer continues to run.
This feature can be used to determine the assertion of an event
with increased accuracy.
Name:
T0LD
Address:
0xFFFF0320
Default value:
0x00000000
Access:
Read/write
Function:
T0LD is a 32-bit register that holds the 32-bit
value that is loaded into the counter.
Timer0 Clear Register
Note: Only peripherals that have their IRQ source enabled can
be used with the Timer capture feature.
The Timer0 interface consists of five MMRS.
Name:
T0CLRI
Address:
0xFFFF032C
Access:
Write only
Function:
This 32-bit, write-only MMR is written
(with any value) by user code to clear the
interrupt.
T0LD, T0VAL, and T0CAP are 32-bit registers and hold 32-bit
unsigned integers. T0VAL and T0CAP are read only.
T0CLRI is an 8-bit register. Writing any value to this register
clears the Timer0 interrupt.
Timer0 Value Register
Name:
T0VAL
Address:
0xFFFF0324
Default value:
0xFFFFFFFF
Access:
Read only
Function:
T0VAL is a 32-bit register that holds the
current value of Timer0.
T0CON is the configuration MMR described in Table 75.
Timer0 features a postscaler allowing the user to count between
1 and 256 the number of Timer0 timeouts. To activate the postscaler, the user sets Bit 18 and writes the desired number to count
into Bits[24:31] of T0CON. When that number of timeouts has
been reached, Timer0 can generate an interrupt if T0CON[18]
is set.
Note that if the part is in a low power mode, and Timer0 is
clocked from the GPIO or low power oscillator source, Timer0
continues to operate.
32-BIT LOAD
32.768kHz OSCILLATOR
CORE CLOCK
FREQUENCY/CD
CORE CLOCK
FREQUENCY
PRESCALER
1, 16, 256, OR 32768
32-BIT
UP/DOWN COUNTER
8-BIT
POSTSCALER
TIMER1 IRQ
GPIO
IRQ[31:0]
CAPTURE
Figure 18. Timer0 Block Diagram
Rev. PrC | Page 58 of 96
07079-017
TIMER1
VALUE
Preliminary Technical Data
ADuC7060/ADuC7061
Timer0 Capture Register
Name:
T0CAP
Address:
0xFFFF0330
Default value:
0x00000000
Access:
Read only
Function:
This 32-bit register holds the 32-bit value captured by an enabled IRQ event.
Timer0 Control Register
Name:
T0CON
Address:
0xFFFF0328
Default value:
0x01000000
Access:
Read/write
Function:
This 32-bit MMR configures the mode of operation of Timer0.
Table 75. T0CON MMR Bit Designations
Bit
31 to 24
Name
T0PVAL
23
T0PEN
22 to 20
19
T0PCF
18
T0SRCI
17
T0CAPEN
16 to 12
11
10 to 9
T0CAPSEL
8
T0DIR
7
T0EN
6
T0MOD
T0CLKSEL
Description
8-Bit Postscaler.
By writing to these eight bits, a value is written to the postscaler. Writing 0 is interpreted as a 1.
By reading these eight bits, the current value of the counter is read.
Timer0 Enable Postscaler.
Set to enable the Timer0 postscaler. If enabled, interrupts are generated after T0CON[31:24] periods
as defined by T0LD.
Cleared to disable the Timer0 postscaler.
Reserved. These bits are reserved and should be written as 0 by user code.
Postscaler Compare Flag. Read only. Set if the number of Timer0 overflows is equal to the number written
to the postscaler.
Timer0 Interrupt Source.
Set to select interrupt generation from the postscaler counter.
Cleared to select interrupt generation directly from Timer0.
Event Enable Bit.
Set by user to enable time capture of an event.
Cleared by user to disable time capture of an event.
Event select Bits[0:31]. The events are described in (Table TBD).
Reserved bit.
Clock Select.
00 = 32.768 kHz
01 = 10.24 MHz/CD
10 = 10.24 MHz
11 = P1.0
Count Up.
Set by user for Timer0 to count up.
Cleared by user for Timer0 to count down (default).
Timer0 Enable Bit.
Set by user to enable Timer0.
Cleared by user to disable Timer0 (default).
Timer0 Mode.
Set by user to operate in periodic mode.
Cleared by user to operate in free running mode (default).
Rev. PrC | Page 59 of 96
ADuC7060/ADuC7061
Bit
5 to 4
Name
T0FORMAT
3 to 0
T0SCALE
Preliminary Technical Data
Description
Format.
00 = binary (default).
01 = reserved.
10 = hours:minutes:seconds:hundredths (23 hours to 0 hours).
11 = hours:minutes:seconds:hundredths (255 hours to 0 hours).
Prescaler.
0000 = source clock/1 (default).
0100 = source clock/16.
1000 = source clock/256.
1111 = source clock/32,768.
Note, 10XX = undefined
Timer1 Load Registers
TIMER1 OR WAKE-UP TIMER
Timer1 is a 32-bit wake-up timer, count down or count up, with
a programmable prescaler. The prescaler is clocked directly from
one of four clock sources, namely, the core clock (which is the
default selection), the low power 32.768 kHz oscillators, external
32.768 kHz watch crystal, or the precision 32.768 kHz oscillator.
The selected clock source can be scaled by a factor of 1, 16, 256,
or 32,768. The wake-up timer continues to run when the core
clock is disabled. This gives a minimum resolution of 97.66 ns
when operating at CD zero, the core is operating at 10.24 MHz,
and with a prescaler of 1 (ignoring the external GPIOs).
The counter can be formatted as a plain 32-bit value or as
hours:minutes:seconds:hundredths.
Timer1 reloads the value from T1LD either when Timer1
overflows or immediately when T1CLRI is written.
The Timer1 interface consists of four MMRS.
Name:
T1LD
Address:
0xFFFF0340
Default value:
0x00000000
Access:
Read/write
Function:
T1LD is a 32-bit register that holds the 32-bit
value that is loaded into the counter.
Timer1 Clear Register
Name:
T1CLRI
Address:
0xFFFF034C
Access:
Write only
Function:
This 32-bit, write only MMR is written (with
any value) by user code to clear the interrupt.
T1LD and T1VAL are 32-bit registers and hold 32-bit unsigned
integers. T1VAL is read only.
T1CLRI is an 8-bit register. Writing any value to this register
clears the Timer1 interrupt.
T1CON is the configuration MMR described in Table 76.
Timer1 Value Register
Name:
T1VAL
Address:
0xFFFF0344
Default value:
0xFFFFFFFF
Access:
Read only
Function:
T1VAL is a 32-bit register that holds the
current value of Timer1.
Rev. PrC | Page 60 of 96
Preliminary Technical Data
ADuC7060/ADuC7061
32-BIT LOAD
32.768kHz OSCILLATOR
CORE
CLOCK
PRESCALER
1, 16, 256, OR 32768
32-BIT
UP/DOWN COUNTER
EXTERNAL 32.768kHz
WATCH CRYSTAL
TIMER2
VALUE
TIMER2 IRQ
07079-018
CORE CLOCK
FREQUENCY/CD
Figure 19. Timer1 Block Diagram
Timer1 Control Register
Name:
T1CON
Address:
0xFFFF0348
Default value:
0x0000
Access:
Read/write
Function:
This 16-bit MMR configures the mode of operation of Timer1.
Table 76. T1CON MMR Bit Designations
Bit
15 to 11
10 to 9
Name
8
T1DIR
7
T1EN
6
T1MOD
5 to 4
T1FORMAT
3 to 0
T1SCALE
T1CLKSEL
Description
Reserved.
Clock Source Select.
00 = 32.768 kHz oscillator
01 = 10.24 MHz/CD
10 = XTAL2
11 = 10.24 MHz
Count Up.
Set by user for Timer1 to count up.
Cleared by user for Timer1 to count down (default).
Timer1 Enable Bit.
Set by user to enable Timer1.
Cleared by user to disable Timer1 (default).
Timer1 Mode.
Set by user to operate in periodic mode.
Cleared by user to operate in free running mode (default).
Format.
00 = binary (default).
01 = reserved.
10 = hours:minutes:seconds:hundredths (23 hours to 0 hours). This is only valid with a 32 kHz clock.
11 = hours:minutes:seconds:hundredths (255 hours to 0 hours). This is only valid with a 32 kHz clock.
Prescaler.
0000 = source clock/1 (default).
0100 = source clock/16.
1000 = source clock/256. This setting should be used in conjunction with Timer1 in the format
hours:minutes:seconds:hundredths. See Format 10 and Format 11 listed with Bits[5:4] in this Table 76.
1111 = source clock/32,768.
Rev. PrC | Page 61 of 96
ADuC7060/ADuC7061
Preliminary Technical Data
TIMER2 OR WATCHDOG TIMER
Timer2 Interface
Timer2 has two modes of operation, normal mode and
watchdog mode. The watchdog timer is used to recover
from an illegal software state. When enabled, it requires
periodic servicing to prevent it from forcing a reset of the
processor.
The Timer2 interface consists of four MMRs.
•
•
•
Timer2 reloads the value from T2LD either when Timer2
overflows or immediately when T2CLRI is written.
Normal Mode
T2CON is the configuration MMR described in (Table
TBD).
T2LD and T2VAL are 16-bit registers (Bit 0 to Bit 15) and
hold 16-bit unsigned integers. T2VAL is read only.
T2CLRI is an 8-bit register. Writing any value to this
register clears the Timer2 interrupt in normal mode or
resets a new timeout period in watchdog mode.
The Timer2 in normal mode is identical to Timer0 in 16-bit
mode of operation, except for the clock source. The clock
source is the low power, 32.768 kHz oscillator scalable by a
factor of 1, 16, or 256.
Timer2 Load Register
Watchdog Mode
Watchdog mode is entered by setting T2CON [5]. Timer2
decrements from the timeout value present in the T2LD register
until zero. The maximum timeout is 512 seconds, using a
maximum prescaler/256 and full scale in T2LD.
User software should not configure a timeout period of less
than 30 ms. This is to avoid any conflict with Flash/EE memory
page erase cycles that require 20 ms to complete a single page
erase cycle and kernel execution.
If T2VAL reaches 0, a reset or an interrupt occurs, depending
on T2CON [1]. To avoid a reset or an interrupt event, any value
must be written to T2CLRI before T2VAL reaches zero. This
reloads the counter with T2LD and begins a new timeout period.
When watchdog mode is entered, T2LD and T2CON are
write protected. These two registers cannot be modified until
a power-on reset event resets the watchdog timer. After any
other reset event, the watchdog timer continues to count. To
avoid an infinite loop of watchdog resets, configure the
watchdog timer in the initial lines of user code. User software
should only configure a minimum timeout period of 30 ms.
Timer2 halts automatically during JTAG debug access and only
recommences counting after JTAG has relinquished control of
the ARM7 core. By default, Timer2 continues to count during
power-down. To disable this, set Bit 0 in T2CON. It is
recommended to use the default value, that is, that the
watchdog timer continues to count during power-down.
Name:
T2LD
Address:
0xFFFF0360
Default value:
0x0040
Access:
Read/write
Function:
This 16-bit MMR holds the Timer2
reload value.
Timer2 Value Register
Name:
T2VAL
Address:
0xFFFF0364
Default value:
0x0040
Access:
Read only
Function:
This 16-bit, read-only MMR holds the
current Timer2 count value.
Timer2 Clear Register
Name:
T2CLRI
Address:
0xFFFF036C
Access:
Write only
Function:
This 16-bit, write-only MMR is written (with
any value) by user code to refresh (reload)
Timer2 in watchdog mode to prevent a
watchdog timer reset event.
16-BIT LOAD
PRESCALER
1, 16, 256
16-BIT
UP/DOWN COUNTER
TIMER3
VALUE
Figure 20. Timer2 Block Diagram
Rev. PrC | Page 62 of 96
WATCHDOG RESET
TIMER3 IRQ
07079-019
32.768kHz
Preliminary Technical Data
ADuC7060/ADuC7061
Timer2 Control Register
Name:
T2CON
Address:
0xFFFF0368
Default value:
0x0000
Access:
Read/write
Function:
The 16-bit MMR configures the mode of operation of Timer2 as is described in detail in Table 77.
Table 77 T2CON MMR Bit Designations
Bit
15 to 9
8
Name
7
T2EN
6
T2MOD
5
WDOGMDEN
T2DIR
4
3 to 2
1
WDOGENI
0
T2PDOFF
Description
Reserved. These bits are reserved and should be written as 0 by user code.
Count Up/Count Down Enable.
Set by user code to configure Timer2 to count up.
Cleared by user code to configure Timer2 to count down.
Timer2 Enable.
Set by user code to enable Timer2.
Cleared by user code to disable Timer2.
Timer2 Operating Mode.
Set by user code to configure Timer2 to operate in periodic mode.
Cleared by user to configure Timer2 to operate in free running mode.
Watchdog Timer Mode Enable.
Set by user code to enable watchdog mode.
Cleared by user code to disable watchdog mode.
Reserved. This bit is reserved and should be written as 0 by user code.
Timer2 Clock (32.768 kHz) Prescaler.
00 = 32.768 kHz (default)
01 = source clock/16.
10 = source clock/256.
11 = reserved.
Watchdog Timer IRQ Enable.
Set by user code to produce an IRQ instead of a reset when the watchdog reaches 0.
Cleared by user code to disable the IRQ option.
Stop Timer2 when Power Down is Enabled.
Set by the user code to stop Timer2 when the peripherals are powered down using Bit 4 in the POWCON MMR.
Cleared by the user code to enable Timer2 when the peripherals are powered down using Bit 4 in the
POWCON MMR.
Rev. PrC | Page 63 of 96
ADuC7060/ADuC7061
Preliminary Technical Data
TIMER3
Timer3 Value Register
Timer3 is a general-purpose, 16-bit, count up/count down
timer with a programmable prescaler. Timer3 can be clocked
from the core clock or the low power 32.768 kHz oscillator with
a prescaler of 1, 16, 256, or 32,768.
Name:
T3VAL
Address:
0xFFFF0384
Default value:
0xFFFF
Access:
Read only
Function:
T3VAL is a 16-bit register that holds the
current value of Timer3.
Timer3 has a capture register (T3CAP) that can be triggered by
a selected IRQ source initial assertion. Once triggered, the
current timer value is copied to T3CAP, and the timer continues
running. This feature can be used to determine the assertion of
an event with increased accuracy.
Timer3 interface consists of five MMRs.
Time3 Capture Register
•
Name:
T3CAP
Address:
0xFFFF0390
Default value:
0x0000
Access:
Read only
Function:
This is a 16-bit register that holds the 32-bit
value captured by an enabled IRQ event.
•
•
T3LD, T3VAL, and T3CAP are 16-bit registers and hold
16-bit unsigned integers. T3VAL and T3CAP are read only.
T3CLRI is an 8-bit register. Writing any value to this
register clears the interrupt.
T3CON is the configuration MMR described in Table 78.
Timer3 Load Registers
Name:
T3LD
Address:
0xFFFF0380
Default value:
0x00000
Name:
T3CON
Access:
Read/write
Address:
0xFFFF0388
Function:
T3LD 16-bit register holds the 16-bit value
that is loaded into the counter.
Default value:
0x00000000
Access:
Read/write
Function:
This 32-bit MMR configures the mode of
operation of Timer3.
Timer3 Control Register
Timer3 Clear Register
Name:
T3CLRI
Address:
0xFFFF038C
Access:
Write only
Function:
This 8-bit, write only MMR is written (with
any value) by user code to clear the
interrupt.
Rev. PrC | Page 64 of 96
Preliminary Technical Data
ADuC7060/ADuC7061
Table 78. T3CON MMR Bit Designations
Bit
31 to 18
17
Name
16 to 12
11
10 to 9
T3CAPSEL
8
T3DIR
7
T3EN
6
T3MOD
5 to 4
3 to 0
T3SCALE
T3CAPEN
T3CLKSEL
Description
Reserved.
Event Enable Bit.
Set by user to enable time capture of an event.
Cleared by user to disable time capture of an event.
Event Select Range, 0 to 31. The events are described in (Table TBD).
Reserved.
Clock Select.
00 = 32.768 kHz oscillator
01 = 10.24 MHz/CD
10 = 10.24 MHz
11 = reserved
Count Up.
Set by user for Timer3 to count up.
Cleared by user for Timer3 to count down (default).
Timer3 Enable Bit.
Set by user to enable Timer3.
Cleared by user to disable Timer3 (default).
Timer3 Mode.
Set by user to operate in periodic mode.
Cleared by user to operate in free running mode. Default mode.
Reserved.
Prescaler.
0000 = source clock/1 (default).
0100 = source clock/16.
1000 = source clock/256.
1111 = source clock/32,768.
Rev. PrC | Page 65 of 96
ADuC7060/ADuC7061
Preliminary Technical Data
PULSE-WIDTH MODULATOR (PWM)
PWM GENERAL OVERVIEW
The ADuC706x integrates a six channel PWM interface. The
PWM outputs can be configured to drive an H-bridge or can be
used as standard PWM outputs. On power up, the PWM
outputs default to H-bridge mode. This ensures that the motor
is turned off by default. In standard PWM mode, the outputs
are arranged as three pairs of PWM pins. Users have control
over the period of each pair of outputs and over the duty cycle
of each individual output.
In all modes, the PWMxCOMx MMRs controls the point at
which the PWM outputs change state. An example of the first
pair of PWM outputs (PWM0 and PWM1) is shown in Figure 21.
HIGH SIDE
(PWM0)
LOW SIDE
(PWM1)
Table 79. PWM MMRs
PWM0COM1
PWM0COM2
PWM0LEN
PWM1COM0
PWM1COM1
PWM1COM2
PWM1LEN
PWM2COM0
PWM2COM1
PWM2COM2
PWM2LEN
PWMICLR
Description
PWM Control.
Compare Register 0 for PWM Output 0 and
Output 1.
Compare Register 1 for PWM Output 0 and
PWM Output 1.
Compare Register 2 for PWM Output 0 and
PWM Output 1
Frequency control for PWM Output 0 and PWM
Output 1.
Compare Register 0 for PWM Output 2 and
PWM Output 3.
Compare Register 1 for PWM Output 2 and
PWM Output 3.
Compare Register 2 for PWM Output 2 and
PWM Output 3.
Frequency Control for PWM Output 2 and PWM
Output 3.
Compare Register 0 for PWM Output 4 and
PWM Output 5.
Compare Register 1 for PWM Output 4 and
PWM Output 5.
Compare Register 2 for PWM Output 4 and
PWM Output 5.
Frequency Control for PWM Output 4 and PWM
Output 5.
PWM interrupt clear.
PWM0COM2
PWM0COM1
PWM0COM0
07079-020
Name
PWMCON
PWM0COM0
PWMLEN0
Figure 21. PWM Timing
The PWM clock is selectable via PWMCON with one of the
following values: UCLK divided by 2, 4, 8, 16, 32, 64, 128, or
256. The length of a PWM period is defined by PWMxLEN.
The PWM waveforms are set by the count value of the 16-bit
timer and the compare registers contents as shown with the
PWM0 and PWM1 waveforms in (Figure TBD).
The low-side waveform, PWM1, goes high when the timer
count reaches PWM0LEN, and it goes low when the timer
count reaches the value held in PWM0COM2 or when the
high-side waveform PWM0 goes low.
The high-side waveform, PWM0, goes high when the timer
count reaches the value held in PWM0COM0, and it goes low
when the timer count reaches the value held in PWM0COM1.
Rev. PrC | Page 66 of 96
Preliminary Technical Data
ADuC7060/ADuC7061
Table 80. PWMCON MMR Bit Designations
Bit
14
Name
SYNC
13
PWM5INV
12
PWM3NV
11
PWM1INV
10
PWMTRIP
9
ENA
8:6
PWMCP[2:0]
5
POINV
4
HOFF
3
LCOMP
2
DIR
1
HMODE
0
PWMEN
1
Description
Enables PWM synchronization.
Set to 1 by the user so that all PWM counters are reset on the next clock edge after the detection of a high-to-low
transition on the SYNC pin.
Cleared by user to ignore transitions on the SYNC pin.
Set to 1 by the user to invert PWM5.
Cleared by user to use PWM5 in normal mode.
Set to 1 by the user to invert PWM3.
Cleared by user to use PWM3 in normal mode.
Set to 1 by the user to invert PWM1.
Cleared by user to use PWM1 in normal mode.
Set to 1 by the user to enable PWM trip interrupt. When the PWMTRIP input is low, the PWMEN bit is cleared and an
interrupt is generated.
Cleared by user to disable the PWMTRIP interrupt.
If HOFF = 0 and HMODE = 1. Note: If not in H-Bridge mode, this bit has no effect.
Set to 1 by the user to enable PWM outputs.
Cleared by user to disable PWM outputs.
If HOFF = 1 and HMODE = 1, see (Table TBD).
PWM clock prescaler bits. Sets UCLK divider.
[000] = UCLK/2.
[001] = UCLK/4.
[010] = UCLK/8.
[011] = UCLK/16.
[100] = UCLK/32.
[101] = UCLK/64.
[110] = UCLK/128.
[111] = UCLK/256.
Set to 1 by the user to invert all PWM outputs.
Cleared by user to use PWM outputs as normal.
High side off.
Set to 1 by the user to force PWM0 and PWM2 outputs high. This also forces PWM1 and PWM3 low.
Cleared by user to use the PWM outputs as normal.
Load compare registers.
Set to 1 by the user to load the internal compare registers with the values in PWMxCOMx on the next transition of
the PWM timer from 0x00 to 0x01.
Cleared by user to use the values previously stored in the internal compare registers.
Direction control.
Set to 1 by the user to enable PWM0 and PWM1 as the output signals while PWM2 and PWM3 are held low.
Cleared by user to enable PWM2 and PWM3 as the output signals while PWM0 and PWM1 are held low.
Enables H-bridge mode.1
Set to 1 by the user to enable H-Bridge mode and Bit 1 to Bit 5 of PWMCON.
Cleared by user to operate the PWMs in standard mode.
Set to 1 by the user to enable all PWM outputs.
Cleared by user to disable all PWM outputs.
In H-bridge mode, HMODE = 1. See Table 81 to determine the PWM outputs.
Rev. PrC | Page 67 of 96
ADuC7060/ADuC7061
Preliminary Technical Data
On power-up, PWMCON defaults to 0x12 (HOFF = 1 and
HMODE = 1). All GPIO pins associated with the PWM are
configured in PWM mode by default (see Table 82). Clear the
PWM trip interrupt by writing any value to the PWMICLR
MMR. Note that when using the PWM trip interrupt, the PWM
interrupt should be cleared before exiting the ISR. This prevents
generation of multiple interrupts.
Table 81. PWM Output Selection
ENA
0
x
1
1
1
1
1
PWMCOM0 MMR
HOFF
POINV
0
x
1
x
0
0
0
0
0
1
0
1
DIR
x
x
0
1
0
1
PWM0
1
1
0
HS1
HS1
1
PWM Outputs1
PWM1
PWMR2
1
1
0
1
0
HS1
LS1
0
LS1
1
1
HS1
HS = high side, LS = low side.
Table 82. Compare Register
Name
PWM0COM0
PWM0COM1
PWM0COM2
PWM1COM0
PWM1COM1
PWM1COM2
PWM2COM0
PWM2COM1
PWM2COM2
Address
0xFFFF0F84
0xFFFF0F88
0xFFFF0F8C
0xFFFF0F94
0xFFFF0F98
0xFFFF0F9C
0xFFFF0FA4
0xFFFF0FA8
0xFFFF0FAC
Default Value
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
Rev. PrC | Page 68 of 96
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
PWM3
1
0
LS1
0
1
LS1
Preliminary Technical Data
ADuC7060/ADuC7061
PWM0COM0 Compare Register
PWM1COM0 Compare Register
Name:
PWM0COM0
Name:
PWM1COM0
Address:
0xFFFFF84
Address:
0xFFFFF94
Default value:
0x00
Default value:
0x00
Access:
Read/write
Access:
Read/write
Function:
PWM0 output pin goes high when the PWM
timer reaches the count value stored in this
register.
Function:
PWM2 output pin goes high when the PWM
timer reaches the count value stored in this
register.
PWM0COM1 Compare Register
PWM1COM1 Compare Register
Name:
PWM0COM1
Name:
PWM1COM1
Address:
0xFFFFF88
Address:
0xFFFFF98
Default value:
0x00
Default value:
0x00
Access:
Read/Write
Access:
Read/write
Function:
PWM0 output pin goes low when the PWM
timer reaches the count value stored in this
register.
Function:
PWM2 output pin goes low when the PWM
timer reaches the count value stored in this
register.
PWM0COM2 Compare Register
PWM1COM2 Compare Register
Name:
PWM0COM2
Name:
PWM1COM2
Address:
0xFFFFF8C
Address:
0xFFFFF9C
Default value:
0x00
Default value:
0x00
Access:
Read/write
Access:
Read/write
Function:
PWM1 output pin goes low when the PWM
timer reaches the count value stored in this
register.
Function:
PWM3 output pin goes low when the PWM
timer reaches the count value stored in this
register.
PWM0LEN Register
PWM1LEN Register
Name:
PWM0LEN
Name:
PWM1LEN
Address:
0xFFFFF90
Address:
0xFFFFFA0
Default value:
0x00
Default value:
0x00
Access:
Read/write
Access:
Read/write
Function:
PWM1 output pin goes high when the PWM
timer reaches the value stored in this register.
Function:
PWM3 output pin goes high when the PWM
timer reaches the value stored in this register.
Rev. PrC | Page 69 of 96
ADuC7060/ADuC7061
Preliminary Technical Data
PWM2COM0 Compare Register
PWM1LEN Register
Name:
PWM2COM0
Name:
PWM2LEN
Address:
0xFFFFFA4
Address:
0xFFFFFB0
Default value:
0x00
Default value:
0x00
Access:
Read/write
Access:
Read/write
Function:
PWM4 output pin goes high when the PWM
timer reaches the count value stored in this
register.
Function:
PWM5 output pin goes high when the PWM
timer reaches the value stored in this register.
PWMCLRI Register
PWM2COM1 Compare Register
Name:
PWM2COM1
Address:
0xFFFFFA8
Default value:
0x00
Access:
Read/write
Function:
PWM4 output pin goes low when the PWM
timer reaches the count value stored in this
register.
Name:
PWMCLRI
Address:
0xFFFFFB8
Default value:
0x0000
Access:
Write only
Function:
Write any value to this register to clear a
PWM interrupt source. This register must be
written to before exiting a PWM interrupt
service routine, otherwise, multiple interrupts
occur.
PWM2COM2 Compare Register
Name:
PWM2COM2
Address:
0xFFFFFAC
Default value:
0x00
Access:
Read/write
Function:
PWM5 output pin goes low when the PWM
timer reaches the count value stored in this
register.
Rev. PrC | Page 70 of 96
Preliminary Technical Data
ADuC7060/ADuC7061
UART SERIAL INTERFACE
The ADuC7060 features a 16450-compatible UART. The UART
is a full-duplex, universal, asynchronous receiver/transmitter.
A UART performs serial-to-parallel conversion on data characters received from a peripheral device, and parallel-to-serial
conversion on data characters received from the ARM7TDMI.
The UART features a fractional divider that facilitates high
accuracy baud rate generation and a network addressable mode.
The UART functionality is available on the P1.0/RxD and
P1.1/TxD pins of the ADuC7060.
The serial communication adopts an asynchronous protocol
that supports various word length, stop bits, and parity generation options selectable in the configuration register.
Calculation of the baud rate using a fractional divider is as
follows:
Baud rate =
M+
10.24 MHz
16 × DL × 2 × ( M +
(2)
N
)
2048
10.24 MHz
N
=
2048 Baud rate × 16 × DL × 2
Table 84 lists common baud rate values.
Table 84. Baud Rate Using the Fractional Baud Rate Generator
Baud
Rate
9600
CD
0
DL
0x21
M
1
N
21
Actual
Baud Rate
9598.55
% Error
0.015%
The ADuC7060 features two methods of generating the UART
baud rate: normal 450 UART baud rate generation and
ADuC7060 fractional divider.
19,200
0
0x10
1
85
19,203
0.015%
115,200
0
0x2
1
796
115,218
0.015%
Normal 450 UART Baud Rate Generation
UART REGISTER DEFINITION
BAUD RATE GENERATION
The baud rate is a divided version of the core clock using the
value in COMDIV0 and COMDIV1 MMRs (16-bit value, DL).
The standard baud rate generator formula is
Baud rate =
10.24 MHz
(1)
16 × 2 × DL
Table 83 lists common baud rate values.
Table 83. Baud Rate Using the Standard Baud Rate Generator
Baud Rate
9600
19,200
115,200
9600
19,200
CD
0
0
0
3
3
DL
0x21
0x11
0x3
0x4
0x2
Actual Baud Rate
9696
18,824
106,667
10,000
20,000
% Error
1.01%
1.96%
7.41%
4.17%
4.17%
The UART interface consists of the following nine registers:
COMTX: 8-bit transmit register
COMRX: 8-bit receive register
COMDIV0: divisor latch (low byte)
COMDIV1: divisor latch (high byte)
COMCON0: line control register
COMSTA0: line status register
COMIEN0: interrupt enable register
COMIID0: interrupt identification register
COMDIV2: 16-bit fractional baud divide register
COMTX, COMRX, and COMDIV0 share the same address
location. COMTX and COMRX can be accessed when Bit 7 in
the COMCON0 register is cleared. COMDIV0 can be accessed
when Bit 7 of COMCON0 is set.
ADuC706x Fractional Divider
The fractional divider combined with the normal baud rate
generator allows the generation of accurate, high speed baud rates.
/2
FBEN
/16DL
UART
/(M + N/2048)
07079-021
CORE
CLOCK
Figure 22. Fractional Divider Baud Rate Generation
Rev. PrC | Page 71 of 96
ADuC7060/ADuC7061
Preliminary Technical Data
UART TX Register
UART Divisor Latch Register 1
Write to this 8-bit register to transmit data using the UART.
Name:
COMTX
This 8-bit register contains the most significant byte of the
divisor latch that controls the baud rate at which the UART
operates.
Address:
0xFFFF0700
Name:
COMDIV1
Access:
Write only
Address:
0xFFFF0704
UART RX Register
Default value:
0x00
This 8-bit register is read from to receive data transmitted using
the UART.
Access:
Read/write
Name:
COMRX
UART Control Register 0
Address:
0xFFFF0700
This 8-bit register controls the operation of the UART in
conjunction with COMCON1.
Default value:
0x00
Name:
COMCON0
Access:
Read only
Address:
0xFFFF070C
UART Divisor Latch Register 0
Default value:
0x00
This 8-bit register contains the least significant byte of the
divisor latch that controls the baud rate at which the UART
operates.
Access:
Read/write
Name:
COMDIV0
Address:
0xFFFF0700
Default value:
0x00
Access:
Read/write
Rev. PrC | Page 72 of 96
Preliminary Technical Data
ADuC7060/ADuC7061
Table 85. COMCON0 MMR Bit Designations
Bit
7
Name
DLAB
6
BRK
5
SP
4
EPS
3
PEN
2
STOP
1 to 0
WLS
Description
Divisor Latch Access.
Set by user to enable access to COMDIV0 and COMDIV1 registers.
Cleared by user to disable access to COMDIV0 and COMDIV1 and enable access to COMRX,
COMTX, and COMIEN0.
Set Break.
Set by user to force TxD to 0.
Cleared to operate in normal mode.
Stick Parity. Set by user to force parity to defined values.
1 if EPS = 1 and PEN = 1.
0 if EPS = 0 and PEN = 1.
Even Parity Select Bit.
Set for even parity.
Cleared for odd parity.
Parity Enable Bit.
Set by user to transmit and check the parity bit.
Cleared by user for no parity transmission or checking.
Stop Bit.
Set by the user to transmit 1.5 stop bits if the word length is 5 bits, or 2 stop bits if the word length
is 6, 7, or 8 bits. The receiver checks the first stop bit only, regardless of the number of stop bits
selected.
Cleared by the user to generate one stop bit in the transmitted data.
Word Length Select.
00 = 5 bits.
01 = 6 bits.
10 = 7 bits.
11 = 8 bits.
Rev. PrC | Page 73 of 96
ADuC7060/ADuC7061
Preliminary Technical Data
UART Control Register 1
Table 86. COMCON1 MMR Bit Designations
This 8-bit register controls the operation of the UART in
conjunction with COMCON0.
Bit
7:5
4
Name:
COMCON1
Address:
0xFFFF0710
Default value:
0x00
Access:
Read/write
Name
LOOPBACK
3:2
1
RTS
0
DTR
Description
Reserved bits. Not used.
Loopback. Set by user to enable
loopback mode. In loopback mode,
the TxD is forced high.
Reserved bits. Not used.
Request to Send.
Set by user to force the RTS output to 0.
Cleared by user to force the RTS
output to 1.
Data Terminal Ready.
Set by user to force the DTR output to 0.
Cleared by user to force the DTR
output to 1.
UART Status Register 0
Name:
COMSTA0
Address:
0xFFFF0714
Default value:
0x60
Access:
Read only
Function:
This 8-bit read-only register reflects the current status on the UART.
Table 87. COMSTA0 MMR Bit Designations
Bit
7
6
Name
5
THRE
4
BI
3
FE
2
PE
1
OE
0
DR
TEMT
Description
Reserved.
COMTX and Shift Register Empty Status Bit.
Set automatically if COMTX and the shift register are empty. This bit indicates that the data has
been transmitted, that is, no more data is present in the shift register.
Cleared automatically when writing to COMTX.
COMTX Empty Status Bit.
Set automatically if COMTX is empty. COMTX can be written as soon as this bit is set, the previous
data might not have been transmitted yet and can still be present in the shift register.
Cleared automatically when writing to COMTX.
Break Indicator.
Set when SIN is held low for more than the maximum word length.
Cleared automatically.
Framing Error.
Set when the stop bit is invalid.
Cleared automatically.
Parity Error.
Set when a parity error occurs.
Cleared automatically.
Overrun Error.
Set automatically if data are overwritten before being read.
Cleared automatically.
Data Ready.
Set automatically when COMRX is full.
Cleared by reading COMRX.
Rev. PrC | Page 74 of 96
Preliminary Technical Data
ADuC7060/ADuC7061
COMSTA1 Register
UART Interrupt Identification Register 0
Name:
COMSTA1
Name:
COMIID0
Address:
0xFFFF0718
Address:
0xFFFF0708
Default value:
0x00
Default value:
0x01
Access:
Read only
Access:
Read only
Function:
COMSTA1 is a modem status register
Function:
This 8-bit register reflects the source of the
UART interrupt.
Table 88. COMSTA1 MMR Bit Descriptions
Bit
7:5
4
3:1
0
Name
CTS
DCTS
Description
Reserved. Not used.
Clear to Send.
Reserved. Not used.
Delta CTS. Set automatically if CTS changed state
since COMSTA1 last read. Cleared automatically
by reading COMSTA1.
UART Interrupt Enable Register 0
Name:
COMIEN0
Address:
0xFFFF0704
Default value:
0x00
Access:
Read/write
Function:
The 8-bit register enables and disables the
individual UART interrupt sources.
2
Name
EDSSI
ELSI
1
ETBEI
0
ERBFI
Bits[2:1]
Status
Bits
00
11
Bit 0
NINT
1
0
1
10
0
2
01
0
3
00
0
4
Priority
Definition
No interrupt
Receive line
status
interrupt
Receive
buffer full
interrupt
Transmit
buffer empty
interrupt
Modem
status
interrupt
Clearing
Operation
Read
COMSTA0
Read COMRX
Write data to
COMTX or
read COMIID0
Read
COMSTA1
register
UART Fractional Divider Register
This 16-bit register controls the operation of the fractional
divider for the ADuC706x.
Table 89. COMIEN0 MMR Bit Designations
Bit
7 to 4
3
Table 90. COMIID0 MMR Bit Designations
Description
Reserved. Not used.
Modem Status Interrupt Enable Bit.
Set by user to enable generation of an
interrupt if any of COMSTA1[3:1] are set.
Cleared by user.
RxD Status Interrupt Enable Bit.
Set by the user to enable generation of
an interrupt if any of the COMSTA0[3:1]
register bits are set.
Cleared by the user.
Enable Transmit Buffer Empty Interrupt.
Set by the user to enable an interrupt
when the buffer is empty during a
transmission, that is, when COMSTA[5]
is set.
Cleared by the user.
Enable Receive Buffer Full Interrupt.
Set by the user to enable an interrupt
when the buffer is full during a
reception.
Cleared by the user.
Name:
COMDIV2
Address:
0xFFFF072C
Default value:
0x0000
Access:
Read/write
Table 91. COMDIV2 MMR Bit Designations
Bit
15
Name
FBEN
14:13
12:11
FBM[1:0]
10:0
FBN[10:0]
Rev. PrC | Page 75 of 96
Description
Fractional Baud Rate Generator Enable Bit.
Set by the user to enable the fractional
baud rate generator.
Cleared by the user to generate the baud
rate using the standard 450 UART baud rate
generator.
Reserved.
M. If FBM = 0, M = 4. See Equation 2 for the
calculation of the baud rate using a
fractional divider and (Table TBD) for
common baud rate values.
N. See Equation 2 for the calculation of the
baud rate using a fractional divider and
(Table TBD) for common baud rate values.
ADuC7060/ADuC7061
Preliminary Technical Data
I2C
The ADuC7060 incorporates an I2C peripheral that may
configured as a fully I2C-compatible I2C bus master device or, as
a fully I2C bus-compatible slave device. The two pins used for
data transfer, SDA and SCL, are configured in a wired-AND
format that allows arbitration in a multimaster system. These
pins require external pull-up resistors. Typical pull-up values
are between 4.7 kΩ and10 kΩ.
The I2C bus peripheral is address in the I2C bus system is
programmed by the user. This ID can be modified any time a
transfer is not in progress. The user can configure the interface
to respond to four slave addresses.
2
The transfer sequence of an I C system consists of a master
device initiating a transfer by generating a start condition while
the bus is idle. The master transmits the slave device address
and the direction of the data transfer (read or /write) during the
initial address transfer. If the master does not lose arbitration
and the slave acknowledges, the data transfer is initiated. This
continues until the master issues a stop condition and the bus
becomes idle.
The I2C peripheral can only be configured as a master or slave
at any given time. The same I2C channel cannot simultaneously
support master and slave modes.
The I2C interface on the ADuC7060 includes the following
features:
•
Support for repeated start conditions. In master mode, the
ADuC7060 can be programmed to generate a repeated
start. In slave mode, the ADuC7060 recognizes repeated
start conditions.
•
•
•
•
•
•
•
In master and slave mode, the part recognizes both 7-bit
and 10-bit bus addresses.
In I2C master mode, the ADuC7060 supports continuous
reads from a single slave up to 512 bytes in a single transfer
sequence.
Clock stretching is supported in both master and slave
modes.
In slave mode, the ADuC7060 can be programmed to
return a no acknowledge (NACK). This allows the
validiation of checksum bytes at the end of I2C transfers.
Bus arbitration in master mode is supported.
Internal and external loopback modes are supported for
I2C hardware testing. In loopback mode.
The transmit and receive circuits in both master and slave
mode contain 2-byte FIFOs. Status bits are available to the
user to control these FIFOs.
Configuring External pins for I2C functionality
The I2C pins of the ADuC7060 device are P0.1 and P0.3. P0.1 is
the I2C clock signal and P0.3 is the I2C data signal. To configure
P0.1 and P0.3 for I2C mode, Bit 1 and Bit 3 of the GP0CON0
register must be set to 1. Bit 1 of the GP0CON1 register must
also be set to 1 to enable I2C mode.
Note that to write to GP0CON1, the GP0KEY1 register must be
set to 0x7 immediatley before writing to GP0CON1. Also, the
GP0KEY2 register must be set to 0x13 immediatley after
writing to GP0CON1. The following code example shows this
in detail:
GP0CON0 = BIT4 + BIT12;
// Select SPI/I2C alternative function for P0.1 and P0.3
GP0KEY1 = 0x7;
// Write to GP0KEY1
GP0CON1 = BIT1;
GP0KEY2 = 0x13;
// Select I2C functionality for P0.1 and P0.3
// Write to GP0KEY2
Rev. PrC | Page 76 of 96
Preliminary Technical Data
ADuC7060/ADuC7061
SERIAL CLOCK GENERATION
The I2C master in the system generates the serial clock for a
transfer. The master channel can be configured to operate in
fast mode (400 kHz) or standard mode (100 kHz).
The bit rate is defined in the I2CDIV MMR as follows:
fUCLK
(2 + DIVH ) + (2 + DIVL)
f SERIAL CLOCK =
The ADuC7060 also supports 10-bit addressing mode. When
Bit 1 of I2CSCON (ADR10EN bit) is set to 1, then one 10-bit
address is supported in slave mode and is stored in registers
I2CID0 and I2CID1. The 10-bit address is derived as follows:
I2CID0[0] is the read/write bit and is not part of the I2C
address.
I2CID0[7:1] = Address Bits[6:0].
I2CID1[2:0] = Address Bits[9:7].
where:
fUCLK = clock before the clock divider.
DIVH = the high period of the clock.
DIVL = the low period of the clock.
I2CID1[7:3] must be set to 11110b
Master Mode
In master mode, the I2CADR0 register is programmed with the
I2C address of the device.
Thus, for 100 kHz operation
In 7-bit address mode, I2CADR0[7:1] are set to the device
address. I2CADR0[0] is the read/write bit.
DIVH = DIVL = 0x33
and for 400 kHz
In 10-bit address mode, the 10-bit address is created as follows:
DIVH = 0x0A, DIVL = 0x0F
I2CADR0[7:3] must be set to 11110b.
The I2CDIV register corresponds to DIVH:DIVL.
I2CADR0[2:1] = Address Bits[9:8].
I2C BUS ADDRESSES
I2CADR1[7:0] = Address Bits[7:0].
Slave Mode
In slave mode, the registers I2CID0, I2CID1, I2CID2, and
I2CID3 contain the device IDs. The device compares the four
I2CIDx registers to the address byte received from the bus
master. To be correctly addressed, the 7 MSBs of either ID
register must be identical to that of the 7 MSBs of the first
received address byte. The LSB of the ID registers (the transfer
direction bit) is ignored in the process of address recognition.
I2CADR0[0] is the read/write bit.
I2C REGISTERS
The I2C peripheral interface consists overall of 19 MMRs. 10 of
these are master related only, 7 are slave related only, and there
are 2 MMRs common to both master and slave modes.
I2C Master Registers
I2C Master Control Register
Name:
I2CMCON
Address:
0xFFFF0900
Default value:
0x0000
Access:
Read/write
Function:
This 16-bit MMR configures I2C peripheral in master mode.
Table 92. I2CMCON MMR Bit Designations
Bit
15 to 9
8
Name
7
I2CNACKENI
6
I2CALENI
I2CMCENI
Description
Reserved. These bits are reserved and should not be written to.
I2C transmission complete interrupt enable bit.
Set this bit to enable an interrupt on detecting a Stop condition on the I2C bus.
Clear this interrupt source.
I2C no acknowledge (NACK) received Interrupt enable bit.
Set this bit to enable interrupts when the I2C master receives a no acknowledge.
Clear this interrupt source.
I2C Arbitration Lost Interrupt Enable bit.
Set this bit to enable interrupts when the I2C master has lost in trying to gain control of the I2C bus.
Clear this interrupt source.
Rev. PrC | Page 77 of 96
ADuC7060/ADuC7061
Bit
5
Name
I2CMTENI
4
I2CMRENI
3
I2CMSEN
2
I2CILEN
1
I2CBD
0
I2CMEN
Preliminary Technical Data
Description
I2C Transmit Interrupt Enable bit.
Set this bit to enable interrupts when the I2C master has transmitted a byte.
Clear this interrupt source.
I2C Receive Interrupt Enable bit.
Set this bit to enable interrupts when the I2C master receives data.
Cleared by user to disable interrupts when the I2C master is receiving data.
I2C Master SCL stretch Enable bit.
Set this bit to 1 to enable Clock stretching. When SCL is low, setting this bit will force the device to hold SCL low
until I2CMSEN is cleared. If SCLis high, setting this bit forces the device to hold SCL low after the next falling edge.
Clear this bit to disable clock stretching.
I2C Internal Loopback Enable.
Set this bit to enable loopback test mode. In this mode, the SCL and SDA signals are connected internally to their
respective input signals.
Cleared by user to disable Loopback mode.
I2C Master Backoff Disable bit.
Set this bit to allow the device to compete for control of the bus even if another device is currently driving a Start
Condition.
Clear this bit to back off until the I2C bus becomes free.
I2C Master Enable bit.
Set by user to enable I2C master mode.
Cleared disable I2C master mode.
Rev. PrC | Page 78 of 96
Preliminary Technical Data
ADuC7060/ADuC7061
I2C Master Status Register
Name:
I2CMSTA
Address:
0xFFFF0904
Default value:
0x0000
Access:
Read
Function:
This 16-bit MMR is I2C status register in master mode.
Table 93 I2CMSTA MMR Bit Designations
Bit
15 to 11
10
Name
9
I2CMRxFO
8
I2CMTC
7
I2CMNA
6
I2CMBUSY
5
I2CAL
4
I2CMNA
3
I2CMRXQ
2
I2CMTXQ
1 to 0
I2CMTFSTA
I2CBBUSY
Description
Reserved. These bits are reserved.
I2C Bus Busy Status Bit.
This bit is set to 1 when a start condition is detected on the I2C bus.
This bit is cleared when a stop condition is detected on the bus.
Master Rx FIFO Overflow.
This bit is set to 1 when a byte is written to the Rx FIFO when it is already full.
This bit is cleared in all other conditions.
I2C Transmission Complete Status Bit.
This bit is set to 1 when a transmission is complete between the master and the slave it was communicating with.
If the I2CMCENI bit in I2CMCON is set, an interrupt is generated when this bit is set.
Clear this interrupt source.
I2C Master No Acknowledge (NACK). Data Bit
This bit is set to 1 when a no acknowledge (NACK). condition is received by the master in response to a data write
transfer.
If the I2CNACKENI bit in I2CMCON is set, an interrupt is generated when this bit is set.
This bit is cleared in all other conditions.
I2C Master Busy Status Bit.
Set to 1 when the master is busy processing a transaction.
Cleared if the master is ready or if another master device has control of the bus.
I2C Arbitration Lost Status Bit.
This bit is set to 1 when the I2C master has lost in trying to gain control of the I2C bus.
If the I2CALENI bit in I2CMCON is set, an interrupt is generated when this bit is set.
This bit is cleared in all other conditions.
I2C Master No acknowledge (NACK) Address Bit.
This bit is set to 1 when a no acknowledge (NACK) condition is received by the master in response to an Address.
If the I2CNACKENI bit in I2CMCON is set, an interrupt is generated when this bit is set.
This bit clears in all other conditions.
I2C Master Receive Request Bit.
This bit is set to 1 when data enters the Rx FIFO. If the I2CMRENI in I2CMCON is set, an interrupt is generated.
This bit is cleared in all other conditions.
I2C Master Transmit Request bit.
This bit goes high if the Tx FIFO is empty or only contains 1byte and the master has transmitted an
Address + write. If the I2CMTENI bit in I2CMCON is set, an interrupt is generated when this bit is set.
This bit is cleared in all other conditions.
I2C Master Tx FIFO Status Bits.
00 = I2C Master Tx FIFO empty
01 = 1 byte in Master Tx FIFO
10 = 1 byte in Master Tx FIFO
11 = I2C Master Tx FIFO Ffull.
Rev. PrC | Page 79 of 96
ADuC7060/ADuC7061
Preliminary Technical Data
I2C Master Receive Register
I2C Master Current Read Count Register
Name:
I2CMRX
Name:
I2CMCNT1
Address:
0xFFFF0908
Address:
0xFFFF0914
Default value:
0x00
Default value:
0x00
Access:
Read only
Access:
Read
Function:
This 8-bit MMR is the I2C master receive
register.
Function:
This 8-bit MMR holds the number of bytes
received so far during a read sequence with a
slave device.
I2C Master Transmit Register
Name:
I2CMTX
Address:
0xFFFF090C
Default value:
0x00
Access:
Write only
Function:
This 8-bit MMR is the I2C master transmit
register.
I2C Address 0 Register
Name:
I2CADR0
Address:
0xFFFF0918
Default value:
0x00
Access:
Read/write
Function:
This 8-bit MMR holds the 7-bit slave address
and the read/write bit when the master begins
communicating with a slave.
I2C Master Read Count Register
Table 95. I2CADR0 MMR in 7-Bit Address Mode
Name:
I2CMCNT0
Address:
0xFFFF0910
Bit
7:1
Name
I2CADR
Default value:
0x0000
0
R/W
Access:
Read/write
Function:
This 16-bit MMR holds the required number
of bytes when the master begins a read
sequence from a slave device.
Table 94. I2CMCNT0 MMR Bit Descriptions
Bit
15:9
8
Name
7:0
I2CRCNT
I2CRECNT
Description
Reserved.
Set this bit if greater than 256 bytes are
required from the slave.
Clear this bit when reading 256 bytes or less.
These 8 bits hold the number of bytes
required during a slave read sequence,
minus 1. If only a single byte is required,
these bits should be set to 0.
Description
These bits contain the 7-bit address of the
required slave device.
Bit 0 is the read/write bit.
When this bit = 1, a read sequence is requested.
When this bit = 0, a write sequence is requested.
Table 96. I2CADR0 MMR in 10-Bit Address Mode
Bit
7:3
Name
2:1
I2CMADR
0
R/W
Rev. PrC | Page 80 of 96
Description
These bits must be set to [11110b] in 10-bit
address mode.
These bits contain ADDR[9:8] in 10-bit
addressing mode.
Read/Write Bit.
When this bit = 1, a read sequence is
requested.
When this bit = 0, a write sequence is
requested.
Preliminary Technical Data
ADuC7060/ADuC7061
I2C Address 1 Register
I2C Master Clock Control Register
Name:
I2CADR1
Name:
I2CDIV
Address:
0xFFFF091C
Address:
0xFFFF0924
Default value:
0x00
Default value:
0x1F1F
Access:
Read/write
Access:
Read/write
Function:
This 8-bit MMR is used in 10-bit addressing
mode only. This register contains the least
significant byte of the address.
Function:
This MMR controls the frequency of the I2C
clock generated by the master on to the SCL
pin. For further details, see the Serial Clock
Generation section.
Table 97. I2CADR1 MMR in 10-Bit Address Mode
Bit
7:0
Name
I2CLADR
Description
These bits contain ADDR[7:0] in 10-bit
addressing mode.
Table 98. I2CDIV MMR
Bit
15:8
Name
DIVH
7:0
DIVL
Rev. PrC | Page 81 of 96
Description
These bits control the duration of the high
period of SCL.
These bits control the duration of the low period
of SCL.
ADuC7060/ADuC7061
Preliminary Technical Data
I2C Slave Registers
I2C Slave Control Register
Name:
I2CSCON
Address:
0xFFFF0928
Default value:
0x0000
Access:
Read/write
Function:
This 16-bit MMR configures the I2C peripheral in slave mode.
Table 99. I2CSCON MMR Bit Designations
Bit
15 to 11
10
Name
9
I2CSRXENI
8
I2CSSENI
7
I2CNACKEN
6
I2CSSEN
5
I2CSETEN
4
I2CGCCLR
3
I2CHGCEN
2
I2CGCEN
1
0
RESERVED
I2CSEN
I2CSTXENI
Description
Reserved bits.
Slave transmit interrupt enable bit.
Set this bit to enable an interrupt after a slave transmits a byte.
Clear this interrupt source.
Slave receive interrupt enable bit.
Set this bit to enable an interrupt after the slave receives data.
Clear this interrupt source.
I2C Stop Condition detected interrupt enable bit.
Set this bit to enable an interrupt on detecting a stop condition on the I2C bus.
Clear this interrupt source.
I2C no acknowledge (NACK) enable bit.
Set this bit to no acknowledge (NACK) the next byte in the transmission sequence.
Clear this bit to let the Hardware control the acknowledge/no acknowledge (NACK) sequence.
I2C Slave SCL stretch Enable bit.
Set this bit to 1 to enable clock stretching. When SCL is low, setting this bit forces the device to hold SCL low until
I2CSSEN is cleared. If SCL is high, setting this bit forces the device to hold SCL low after the next falling edge.
Clear this bit to disable clock stretching.
I2C early transmit interrupt enable bit.
Setting this bit enables a transmit request interrupt just after the positive edge of SCL during the read bit
transmission.
Clear this bit to enable a transmit request interrupt just after the negative edge of SCL during the read bit
transmission.
I2C general call status and ID clear bit.
Writing a 1 to this bit clears the general call status and ID bits in the I2CSSTA register.
Clear this bit at all other times.
I2C Hardware General Call Enable. See I2C General Call section for further details.
Set this bit and I2CGCEN to enable Hardware General call recognition in slave mode.
Clear to disable recognition of Hardware General Call commands.
I2C General Call Enable. See the I2C General Call section for further details.
Set this bit to allow the slave acknowledge I2C general call commands.
Clear to disable recognition of general call commands.
Always set this bit = 0.
I2C slave enable bit.
Set by user to enable I2Cslave mode.
Clear to disable I2C slave mode.
Rev. PrC | Page 82 of 96
Preliminary Technical Data
ADuC7060/ADuC7061
I2C Slave Status Register
Name:
I2CSSTA
Address:
0xFFFF092C
Default value:
0x0000
Access:
Read/write
Function:
This 16-bit MMR is the I2C status register in slave mode.
Table 100. I2CSSTA MMR Bit Designations
Bit
15
14
13
Name
I2CSTA
I2CREPS
12 to 11
I2CID[1:0]
10
I2CSS
9 to 8
I2CGCID[1:0]
7
I2CGC
6
I2CSBUSY
5
I2CSNA
Description
Reserved bit.
This bit is set to 1 if:
a) a start condition followed by a matching address is detected.
b) a start byte (0x01) is received.
c) general calls are enabled and a general call code of 0x00 is received.
This bit is cleared on receiving a stop condition
This bit is set to 1 if a repeated start condition is detected.
This bit is cleared on receiving a stop condition
I2C address matching register. These bits indicate which I2CIDx register matches the received address.
[00] = received address matches I2CID0,
[01] = received address matches I2CID1
[10] = received address matches I2CID2
[11] = received address matches I2CID3
I2C stop condition after start detected bit.
This bit is set to 1 when a stop condition is detected after a previous start and matching address.
When the I2CSSENI bit in I2CSCON is set, an interrupt is generated.
This bit is cleared by reading this register.
I2C general call ID bits.
[00] = no general call received.
[01] = general call reset and program address.
[10] = general program address.
[11] = general call matching alternative ID
Note that these bits are not cleared by a general call reset command.
Clear these bits by writing a 1 to the I2CGCCLR bit in I2CSCON.
I2C general call status bit.
This bit is set to 1 if the slave receives a general call command of any type.
If the command received was a reset command, then all registers return to their default state.
If the command received was a hardware general call, the Rx FIFO holds the 2nd byte of the command and this
can be compared with the I2CALT register.
Clear this bit by writing a 1 to the I2CGCCLR bit in I2CSCON.
I2C slave busy status bit.
Set to 1 when the slave receives a start condition.
Cleared by hardware if:
a) the received address does not match any of the I2CSIDx registers.
b) the slave device receives a stop condition.
c) a repeated start address does not match any of the I2CSIDx registers.
I2C slave no acknowledge (NACK) data bit.
This bit is set to 1 when the slave responds to a bus address with a no acknowledge (NACK). This bit is asserted
under the following conditions:
a) if no acknowledge (NACK) was returned because there was no data in the Tx FIFO.
b) if the I2CNACKEN bit was set in the I2CSCON register.
This bit is cleared in all other conditions.
Rev. PrC | Page 83 of 96
ADuC7060/ADuC7061
Bit
4
Name
I2CSRxFO
3
I2CSRXQ
2
I2CSTXQ
1
I2CSTFE
0
I2CETSTA
Preliminary Technical Data
Description
Slave Rx FIFO overflow.
This bit is set to 1 when a byte is written to the Rx FIFO when it is already full.
This bit is cleared in all other conditions.
I2C slave receive request bit.
This bit is set to 1 when the Rx FIFO of the slave is not empty.
This bit causes an interrupt to occur if the I2CSRXENI bit in I2CSCON is set.
The Rx FIFO must be read or flushed to clear this bit.
I2C slave transmit request bit.
This bit is set to 1 when the slave receives a matching address followed by a read.
If the I2CSETEN bit in I2CSCON is =0, This bit goes high just after the negative edge of SCL during the read bit
transmission.
If the I2CSETEN bit in I2CSCON is =1, this bit goes high just after the positive edge of SCL during the read bit
transmission.
This bit causes an interrupt to occur if the I2CSTXENI bit in I2CSCON is set.
This bit is cleared in all other conditions.
I2C Slave FIFO underflow status bit.
This bit goes high if the Tx FIFO is empty when a master requests data from the slave. This bit is asserted at the
rising edge of SCL during the read bit.
This bit is cleared in all other conditions.
I2C Slave Early Transmit FIFO status bit.
If the I2CSETEN bit in I2CSCON is =0, this bit goes high of the slave Tx FIFO is empty.
If the I2CSETEN bit in I2CSCON is =1, this bit goes high just after the positive edge of SCL during the write bit
transmission.
This bit asserts once only for a transfer.
This bit is cleared after being read.
Rev. PrC | Page 84 of 96
Preliminary Technical Data
ADuC7060/ADuC7061
I2C Slave Receive Register
I2C COMMON REGISTERS
Name:
I2CSRX
I2C FIFO Status Register
Address:
0xFFFF0930
Default value:
0x00
Access:
Read
Function:
This 8-bit MMR is the I2C slave receive register.
Name:
I2CFSTA
Address:
0xFFFF094C
Default value:
0x0000
Access:
Read/write
Function:
These 16-bit MMRs contain the status of the
Rx/Tx FIFOs in both master and slave modes.
I2C Slave Transmit Register
Name:
I2CSTX
Address:
0xFFFF0934
Default value:
0x00
Access:
Write
Function:
This 8-bit MMR is the I2C slave transmit
register.
Table 101. I2CFSTA MMR Bit Designations
Bit
15:10
9
8
7:6
Name
5:4
I2CMTXSTA
3:2
I2CSRXSTA
1:0
I2CSTXSTA
I2CFMTX
I2CFSTX
I2CMRXSTA
I2C Hardware General Call Recognition Register
Name:
I2CALT
Address:
0xFFFF0938
Default value:
0x00
Access:
Read/write
Function:
This 8-bit MMR is used with hardware general
calls when I2CSCON bit 3 is set to 1. This
register is used in cases where a master is
unable to generate an address for a slave, and
instead, the slave must generate the address for
the master.
I2C Slave Device ID Registers
Name:
I2CIDx
Addresses:
0xFFFF093C = I2CID0
0xFFFF0940 = I2CID1
0xFFFF0944 = I2CID2
0xFFFF0948 = I2CID3
Default value:
0x00
Access:
Read/write
Function:
These 8-bit MMRs are programmed with I2C
bus IDs of the slave. See the I2C Bus Addresses
section for further details.
Rev. PrC | Page 85 of 96
Description
Reserved Bits.
Set this bit to 1 to flush the master Tx FIFO.
Set this bit to 1 to flush the slave Tx FIFO.
I2C Master Receive FIFO Status Bits.
[00] = FIFO empty.
[01] = byte written to FIFO.
[10] = 1 byte in FIFO.
[11] = FIFO full.
I2C Master Transmit FIFO Status Bits.
[00] = FIFO empty.
[01] = byte written to FIFO.
[10] = 1 byte in FIFO.
[11] = FIFO full.
I2C Slave Receive FIFO Status Bits.
[00] = FIFO empty
[01] = byte written to FIFO
[10] = 1 byte in FIFO
[11] = FIFO full
I2C Slave Transmit FIFO Status Bits.
[00] = FIFO empty.
[01] = byte written to FIFO.
[10] = 1 byte in FIFO.
[11] = FIFO full.
ADuC7060/ADuC7061
Preliminary Technical Data
SERIAL PERIPHERAL INTERFACE
The ADuc7060 integrates a complete hardware serial peripheral
interface (SPI) on-chip. SPI is an industry standard, synchronous
serial interface that allows eight bits of data to be synchronously
transmitted and simultaneously received, that is, full duplex up
to a maximum bit rate of 5.12 Mb.
In slave mode, the SPICON register must be configured with
the phase and polarity of the expected input clock. The slave
accepts data from an external master up to 5.12 Mb.
The SPI port can be configured for master or slave operation
and typically consists of four pins: MISO, MOSI, SCL, and SS.
In both master and slave modes, data are transmitted on one
edge of the SCL signal and sampled on the other. Therefore, it is
important that the polarity and phase are configured the same
for the master and slave devices.
MISO (MASTER IN, SLAVE OUT) PIN
SLAVE SELECT (SS INPUT) PIN
The MISO pin is configured as an input line in master mode
and an output line in slave mode. The MISO line on the master
(data in) should be connected to the MISO line in the slave
device (data out). The data is transferred as byte wide (8-bit)
serial data, MSB first.
In SPI slave mode, a transfer is initiated by the assertion of SS,
which is an active low input signal. The SPI port then transmits
and receives 8-bit data until the transfer is concluded by
deassertion of SS. In slave mode, SS is always an input.
MOSI (MASTER OUT, SLAVE IN) PIN
The MOSI pin is configured as an output line in master mode
and an input line in slave mode. The MOSI line on the master
(data out) should be connected to the MOSI line in the slave
device (data in). The data is transferred as byte wide (8-bit)
serial data, MSB first.
SCL (SERIAL CLOCK I/O) PIN
The master serial clock (SCL) synchronizes the data being
transmitted and received through the MOSI SCL period.
Therefore, a byte is transmitted/received after eight SCL
periods. The SCL pin is configured as an output in master mode
and as an input in slave mode.
In master mode, polarity and phase of the clock are controlled
by the SPICON register, and the bit rate is defined in the
SPIDIV register as follows:
f SERIAL CLOCK =
f UCLK
2 × (1 + SPIDIV)
The maximum speed of the SPI clock is independent on the
clock divider bits.
GP0CON0 = BIT0 + BIT4 + BIT8 + BIT12;
In SPI master mode, the SS is an active low output signal.It
asserts itself automatically at the beginning of a transfer and
deasserts itself upon completion.
CONFIGURING EXTERNAL PINS FOR SPI
FUNCTIONALITY
The SPI pins of the ADuC7060 device are P0[0:3].
P0.0 is the slave chip select pin. In slave mode, this pin is an
input and must be driven low by the master. In master mode,
this pin is an output and goes low at the beginning of a transfer
and high at the end of a transfer.
P0.1 is the SCL pin.
P0.2 is the master In, slave out (MISO) pin.
P0.3 is the master Out, slave in (MOSI) pin.
To configure P0[0:3] for SPI mode, Bit 0 to Bit 3 of the
GP0CON0 register must be set to 1. Bit 1 of the GP0CON1
Note that to write to GP0CON1, the GP0KEY1 register must be
set to 0x7 immediatley before writing to GP0CON1. Also, the
GP0KEY2 register must be set to 0x13 immediatley after
writing to GP0CON1. The following code example shows this
in detail:
// Select SPI/I2C alternative function for P0[0...3]
GP0KEY1 = 0x7;
//Write to GP0KEY1
GP0CON1 &=~ BIT1;
// Select SPI functionality for P0.0 to
GP0KEY2 = 0x13;
//Write to GP0KEY2
Rev. PrC | Page 86 of 96
P0.3
Preliminary Technical Data
ADuC7060/ADuC7061
SPI REGISTERS
The following MMR registers control the SPI interface: SPISTA, SPIRX, SPITX, SPIDIV, and SPICON.
SPI Status Register
Name:
SPISTA
Address:
0xFFFF0A00
Default value:
0x00000000
Access:
Read/write
Function:
This 32-bit MMR contains the status of the SPI interface in both master and slave modes.
Table 102. SPISTA MMR Bit Designations
Bit
15:12
11
Name
10:8
SPIRXFSTA[2:0]
7
SPIFOF
6
SPIRXIRQ
5
SPITXIRQ
SPIREX
4
SPITXUF
3:1
SPITXFSTA[2:0]
0
SPIISTA
Description
Reserved bits.
SPI Rx FIFO excess bytes present. This bit is set when there are more bytes in the Rx FIFO than indicated in the
SPIRXMDE bits in SPICON
This bit is cleared when the number of bytes in the FIFO is equal or less than the number in SPIRXMDE.
SPI Rx FIFO status bits.
[000] = Rx FIFO is empty
[001] = 1 valid byte in the FIFO
[010] = 2 valid byte in the FIFO
[011] = 3 valid byte in the FIFO
[100] = 4 valid byte in the FIFO
SPI Rx FIFO overflow status bit.
Set when the Rx FIFO was already full when new data was loaded to the FIFO. This bit generates an interrupt
except when SPIRFLH is set in SPICON.
Cleared when the SPISTA register is read.
SPI Rx IRQ status bit.
Set when a receive interrupt occurs. This bit is set when SPITMDE in SPICON is cleared and the required
number of bytes have been received.
Cleared when the SPISTA register is read.
SPI Tx IRQ status bit.
Set when a transmit interrupt occurs. This bit is set when SPITMDE in SPICON is set and the required number
of bytes have been transmitted.
Cleared when the SPISTA register is read.
SPI Tx FIFO underflow.
This bit is set when a transmit is initiated without any valid data in the Tx FIFO. This bit generates an interrupt
except when SPITFLH is set in SPICON.
Cleared when the SPISTA register is read.
SPI Tx FIFO status bits.
[000] = Tx FIFO is empty.
[001] = 1 valid byte in the FIFO.
[010] = 2 valid byte in the FIFO.
[011] = 3 valid byte in the FIFO.
[100] = 4 valid byte in the FIFO.
SPI interrupt status bit.
Set to 1 when an SPI based interrupt occurs.
Cleared after reading SPISTA.
Rev. PrC | Page 87 of 96
ADuC7060/ADuC7061
Preliminary Technical Data
SPIDIV Register
SPIRX Register
Name:
SPIRX
Name:
SPIDIV
Address:
0xFFFF0A04
Address:
0xFFFF0A0C
Default value:
0x00
Default value:
0x1B
Access:
Read
Access:
Write
Function:
This 8-bit MMR is the SPI receive register.
Function:
This 8-bit MMR is the SPI baud rate selection
register.
SPITX Register
SPI Control Register
Name:
SPITX
Address:
0xFFFF0A08
Default value:
0x00
Access:
Write
Function:
This 8-bit MMR is the SPI transmit register.
Name:
SPICON
Address:
0xFFFF0A10
Default value:
0x0000
Access:
Read/write
Function:
This 16-bit MMR configures the SPI peripheral
in both master and slave modes.
Rev. PrC | Page 88 of 96
Preliminary Technical Data
ADuC7060/ADuC7061
Table 103. SPICON MMR Bit Designations
Bit
15 to 14
Name
SPIMDE
13
SPITFLH
12
SPIRFLH
11
SPICONT
10
SPILP
9
SPIOEN
8
SPIROW
7
SPIZEN
6
SPITMDE
5
SPILF
4
SPIWOM
3
SPICPO
2
SPICPH
Description
SPI IRQ mode bits. These bits configure when the Tx/Rx interrupts occur in a transfer.
[00] = Tx interrupt occurs when 1 byte has been transferred. Rx interrupt occurs when 1 or more bytes have been
received into the FIFO.
[01] = Tx interrupt occurs when 2 bytes has been transferred. Rx interrupt occurs when 1 or more bytes have been
received into the FIFO.
[10] = Tx interrupt occurs when 3 bytes has been transferred. Rx interrupt occurs when 3 or more bytes have been
received into the FIFO.
[11] = Tx interrupt occurs when 4 bytes has been transferred. Rx interrupt occurs when the Rx FIFO is full, or 4 bytes
present.
SPI Tx FIFO flush enable bit.
Set this bit to flush the Tx FIFO. This bit does not clear itself and should be toggled if a single flush is required.
If this bit is left high, then either the last transmitted value or 0x00 is transmitted depending on the SPIZEN bit.
Any writes to the Tx FIFO are ignored while this bit is set.
Clear this bit to disable Tx FIFO flushing.
SPI Rx FIFO flush enable bit.
Set this bit to flush the Rx FIFO. This bit does not clear itself and should be toggled if a single flush is required.
If this bit is set all incoming data is ignored and no interrupts are generated.
If set and SPITMDE = 0, a read of the Rx FIFO initiates a transfer.
Clear this bit to disable Rx FIFO flushing.
Continuous transfer enable.
Set by user to enable continuous transfer. In master mode, the transfer continues until no valid data is available in the
Tx register. .SS is asserted and remains asserted for the duration of each 8-bit serial transfer until Tx is empty.
Cleared by user to disable continuous transfer. Each transfer consists of a single 8-bit serial transfer.
If valid data exists in the SPITX register, then a new transfer is initiated after a stall period of 1 serial clock cycle.
Loop back enable bit.
Set by user to connect MISO to MOSI and test software.
Cleared by user to be in normal mode.
Slave MISO output enable bit.
Set this bit for MISO to operate as normal.
Clear this bit to disable the output driver on the MISO pin. The MISO pin is Open-Drain when this bit is clear.
SPIRX Overflow Overwrite Enable.
Set by user, the valid data in the Rx register is overwritten by the new serial byte received.
Cleared by user, the new serial byte received is discarded.
SPI transmit zeros when Tx FIFO is empty.
Set this bit to transmit “0x00” when there is no valid data in the Tx FIFO.
Clear this bit to transmit the last transmitted value when there is no valid data in the Tx FIFO.
SPI transfer and interrupt mode.
Set by user to initiate transfer with a write to the SPITX register. Interrupt only occurs when Tx is empty.
Cleared by user to initiate transfer with a read of the SPIRX register. Interrupt only occurs when Rx is full.
LSB first transfer enable bit.
Set by user, the LSB is transmitted first.
Cleared by user, the MSB is transmitted first.
SPI wired or mode enable bit
Set to 1 enable Open Drain data Output enable. External pull-ups required on data out pins.
Clear for normal output levels.
Serial clock polarity mode bit.
Set by user, the serial clock idles high.
Cleared by user, the serial clock idles low.
Serial clock phase mode bit.
Set by user, the serial clock pulses at the beginning of each serial bit transfer.
Cleared by user, the serial clock pulses at the end of each serial bit transfer.
Rev. PrC | Page 89 of 96
ADuC7060/ADuC7061
Bit
1
Name
SPIMEN
0
SPIEN
Preliminary Technical Data
Description
Master mode enable bit.
Set by user to enable master mode.
Cleared by user to enable slave mode.
SPI enable bit.
Set by user to enable the SPI.
Cleared by user to disable the SPI.
Rev. PrC | Page 90 of 96
Preliminary Technical Data
ADuC7060/ADuC7061
GENERAL-PURPOSE I/O
The ADuC706x features up to sixteen general-purpose
bidirectional input/output (GPIO) pins. In general, many of the
GPIO pins have multiple functions that are configurable by user
code. By default, the GPIO pins are configured in GPIO mode.
All GPIO pins have an internal pull-up resistor with a drive
capability of 1.6 mA.
All I/O pins are 3.3 V tolerant, meaning the GPIOs support an
input voltage of 3.3 V.
When the ADuC706x enters a power-saving mode, the GPIO
pins retain their state.
The GPIO pins are grouped into three port busses.
Table 104 lists all the GPIO pins and their alternative functions.
A GPIO pin alternative function can be selected by writing to
the correct bits of the GPxCON register.
Table 104. GPIO Pin Function Descriptions
Port
0
Pin
P0.0
P0.1
P0.2
P0.3
P0.4
P0.5
P0.6
00
GPIO
GPIO
GPIO
GPIO
GPIO/IRQ0
GPIO
GPIO
Configuration via GPxCON
01
SS (SPI slave select)
SCLK/SCL (Serial clock/SPI clock)
MISO (SPI—master in/slave out)
MOSI (SPI—master out/slave in)
PWM1 (PWM Input 1)
CTS. UART clear to send pin.
RTS. UART request to send pin.
1
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
GPIO/IRQ1
GPIO
GPIO
GPIO
GPIO
GPIO/IRQ3
GPIO
SIN (serial input)
SOUT (serial output)
PWMsync (PWM sync input pin)
PWMtrip (PWM trip input pin)
PWM2 (PWM Input 2)
PWM3 (PWM Input 3)
PWM4 (PWM Input 4)
2
P2.0
P2.1
GPIO/IRQ2
GPIO/IRQ3
PWM0 (PWM Input 0)
PWM5 (PWM Input 5)
GPxCON REGISTERS
GPxCON are the Port x control registers, which select the function of each pin of Port x as described in Table 106.
Table 105.GPXCON Registers
Name
GP0CON0
GP1CON
GP2CON
Address
0xFFFF0D00
0xFFFF0D04
0xFFFF0D08
Default Value
0x00000000
0x00000000
0x00000000
Rev. PrC | Page 91 of 96
Access
R/W
R/W
R/W
ADuC7060/ADuC7061
Preliminary Technical Data
Table 106. GPxCON MMR Bit Descriptions
Table 110. GPxSET MMR Bit Descriptions
Bit
31:30
29:28
27:26
25:24
23:22
21:20
19:18
17:16
15:14
13:12
11:10
9:8
7:6
5:4
3:2
1:0
Bit
31:24
23:16
Description
Reserved.
Reserved.
Reserved.
Select function of Px.6 pin.
Reserved.
Select function of Px.5 pin.
Reserved.
Select function of Px.4 pin.
Reserved.
Select function of Px.3 pin.
Reserved.
Select function of Px.2 pin.
Reserved.
Select function of Px.1 pin.
Reserved.
Select function of Px.0 pin.
15:0
Description
Reserved.
Data Port x Set Bit.
Set to 1 by user to set bit on Port x; also sets the
corresponding bit in the GPxDAT MMR.
Cleared to 0 by user; does not affect the data output.
Reserved.
GPXCLR REGISTERS
GPxCLR are data clear Port x registers.
Table 111. GPxCLR Registers
Name
Address
GP0CLR
GP1CLR
GP2CLR
0xFFFF0D28
0xFFFF0D38
0xFFFF0D48
Default
Value
0x000000XX
0x000000XX
0x000000XX
Access
W
W
W
GPXDAT REGISTERS
GPxPAR REGISTERS
GPxDAT are Port x configuration and data registers. They
configure the direction of the GPIO pins of Port x, set the
output value for the pins that are configured as output, and
store the input value of the pins that are configured as input.
The GPxPAR registers program the parameters for Port 0 and
Port 1. Note that the GPxDAT MMR must always be written
after changing the GPxPAR MMR.
Table 107. GPxDAT Registers
Name
GP0PAR
GP1PAR
GP2PAR
Name
GP0DAT
GP1DAT
GP2DAT
Address
0xFFFF0D20
0xFFFF0D30
0xFFFF0D40
Default Value
0x000000XX
0x000000XX
0x000000XX
Access
R/W
R/W
R/W
Table 108. GPxDAT MMR Bit Descriptions
Bit
31:24
23:16
15:8
7:0
Description
Direction of the Data.
Set to 1 by user to configure the GPIO pin as an
output.
Cleared to 0 by user to configure the GPIO pin as an
input.
Port x Data Output.
Reflect the State of Port x Pins at Reset (Read Only).
Port x Data Input (Read Only).
Table 112. GPxPAR Registers
Address
0xFFFF0D2C
0xFFFF0D3C
0xFFFF0D4C
Bit
31:15
23:16
Name
15:8
GPDS[7:0]
7:0
GPPD[7:0]
GPL[7:0]
GPxSET are data set Port x registers.
Name
GP0SET
GP1SET
GP2SET
Address
0xFFFF0D24
0xFFFF0D34
0xFFFF0D44
Default Value
0x000000XX
0x000000XX
0x000000XX
Access
R/W
R/W
R/W
Table 113. GPxPAR MMR Bit Descriptions
GPXSET REGISTERS
Table 109. GPxSET Registers
Default Value
0x00000000
0x00000000
0x00000000
Access
W
W
W
Rev. PrC | Page 92 of 96
Description
Reserved.
General I/O Port Pin Functionality Lock
Registers.
GPL[7:0] = 0, normal operation.
GPL[7:0] = 1, for each GPIO pin, if this bit is
set, writing to the corresponding bit in
GPxCON or GPxDAT register bit will have
no effect.
Drive Strength Configuration. This bit is
configurable.
GPDS[x] = 0, maximum source current is
2 mA.
GPDS[x] = 1, maximum source current is
4 mA.
Pull-Up Disable Px[7:0].
GPPD[x] = 0, pull-up resistor is active.
GPPD[x] = 1, pull-up resistor is disabled.
Preliminary Technical Data
ADuC7060/ADuC7061
GP0CON1 Control Registers
GP0CON1 Write Sequence
Note: GP0CON1 only needs to be written when using the
ADuC7061 part. It has no affect on the ADuC7060. The
GP0CON1 write values are as follows: GP0KEY1 = 0x7,
GP0CON1 = user value, and GP0KEY2 = 0x13.
Name:
Address:
Default value:
Access:
Function:
Name
GP0KEY1
GP0CON1
GP0KEY2
GP0KEY1
0xFFFF0464
0xXXXX
Write
When writing to GP0CON1, the value of 0x07
must be written to this register in the
instruction immediately before writing to
GP0CON1
Name:
Address:
Default value:
Access:
Function:
Value
0x7
User value
0x13
GP0CON1
0xFFFF0468
0x00
Read/write
This register controls the functionality of P0.0,
P0.1, P0.2 and P0.3 on the ADuC7061/62
parts.
Table 114. GPxCLR MMR Bit Descriptions
Bit
31:24
23:16
15:0
Description
Reserved.
Data Port x Clear Bit.
Set to 1 by user to clear the bit on Port x; also clears
the corresponding bit in the GPxDAT MMR.
Cleared to 0 by user; does not affect the data output.
Reserved.
Table 115. GP0CON1 MMR Bit Designations
Bit
7-2
Name
Reserved
1
SPII2CSEL
0
ADCSEL
Name:
Address:
Default Value:
Access:
Function:
Description
These bits must always be set to 0.
On the ADuC7061/62 parts only, this bit configures P0.0 to P0.3 in I2C or SPI mode. Note Bit 0 of GP0CON1 must be
set to 0 for this bit to work.
This bit is cleared to 0 to select P0.0, P0.1,P0.2 and P0.3 in SPI mode.
This bit is set to 1 to select P0.0, P0.1,P0.2 and P0.3 in I2C mode.
This bit is Cleared by default,
On the ADuC7061/62 parts only, this bit configures P0.0 to P0.3 as GPIO pins or, as ADC input pins.
Set this bit to 1 to enable P0.0/P0.1/P0.2 and P0.3 as ADC inputs.
Clear this bit to 0 to enable P0.0/P0.1/P0.2 and P0.3 as digital I/O.
This bit is Cleared by default,
GP0KEY2
0xFFFF046C
0xXXXX
Write
When writing to GP0CON1, the value 0x13 must be written to this register in the instruction immediately
after writing to POWCON0
Rev. PrC | Page 93 of 96
ADuC7060/ADuC7061
Preliminary Technical Data
HARDWARE DESIGN CONSIDERATIONS
POWER SUPPLIES
DIGITAL
SUPPLY
The ADuC7060/ADuC7061 operational power supply voltage
range is 2.375 V to 2.625 V. Separate analog and digital power
supply pins (AVDD and DVDD, respectively) allow AVDD to be
kept relatively free of noisy digital signals often present on the
system DVDD line. In this mode, the part can also operate with
split supplies, that is, it can use different voltage levels for each
supply. For example, the system can be designed to operate
with an DVDD voltage level of 2.6 V while the AVDD level can be
at 2.5 V, or vice versa. A typical split supply configuration is
shown in Figure 23.
+
–
+
–
10µF
10µF
9
30
9
DVDD
AVDD 24
0.1µF
0.1µF
AGND 23
43
DGND
0.1µF
44
0.1µF
10
43
DGND
07079-023
AGND 23
29
Note that the analog and digital ground pins on the ADuC7060/
ADuC7061 must be referenced to the same system ground
reference point at all times.
07079-022
10
AVDD 24
Notice that in both Figure 23 and Figure 24, a large value (10 μF)
reservoir capacitor sits on DVDD, and a separate 10 μF capacitor
sits on AVDD. In addition, local small value (0.1 μF) capacitors are
located at each AVDD and DVDD pin of the chip. As per standard
design practice, be sure to include all of these capacitors and ensure
the smaller capacitors are close to each AVDD pin with trace
lengths as short as possible. Connect the ground terminal of
each of these capacitors directly to the underlying ground plane.
+
–
44
29
DVDD
Figure 24. External Single Supply Connections
ADuC7060/
ADuC7061
30
10µF
10µF
ADuC7060/
ADuC7061
ANALOG
SUPPLY
DIGITAL
SUPPLY
ANALOG
SUPPLY
BEAD
Figure 23. External Dual Supply Connections
As an alternative to providing two separate power supplies, the
user can reduce noise on AVDD by placing a small series resistor
and/or ferrite bead between AVDD and DVDD, and then decoupling
AVDD separately to ground. An example of this configuration is
shown in Figure 24. With this configuration, other analog circuitry
(such as op amps, voltage reference, and others) can be powered
from the AVDD supply line as well.
Finally, note that once the DVDD supply reaches 1.8 V, it must
ramp to 2.25 V in less than 128 ms. This is a requirement of the
internal power-on-reset circuitry.
Rev. PrC | Page 94 of 96
Preliminary Technical Data
ADuC7060/ADuC7061
OUTLINE DIMENSIONS
0.60 MAX
5.00
BSC SQ
0.60 MAX
PIN 1
INDICATOR
25
24
PIN 1
INDICATOR
TOP
VIEW
0.50
BSC
4.75
BSC SQ
1
EXPOSED
PAD
(BOTTOM VIEW)
0.50
0.40
0.30
17
16
3.65
3.50 SQ
3.35
9
8
0.25 MIN
3.50 REF
0.80 MAX
0.65 TYP
12° MAX
1.00
0.85
0.80
32
0.05 MAX
0.02 NOM
SEATING
PLANE
0.30
0.23
0.18
COPLANARITY
0.08
0.20 REF
COMPLIANT TO JEDEC STANDARDS MO-220-VHHD-2
Figure 25. 32-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
5 mm × 5 mm Body, Very Thin Quad
(CP-32-4)
Dimensions shown in millimeters
7.00
BSC SQ
0.60 MAX
37
36
PIN 1
INDICATOR
TOP
VIEW
12° MAX
48
25
24
4.25
4.10 SQ
3.95
12
13
0.25 MIN
5.50
REF
0.80 MAX
0.65 TYP
0.50 BSC
1
(BOTTOM VIEW)
0.05 MAX
0.02 NOM
SEATING
PLANE
PIN 1
INDICATOR
EXPOSED
PAD
6.75
BSC SQ
0.50
0.40
0.30
1.00
0.85
0.80
0.30
0.23
0.18
0.60 MAX
0.20 REF
COPLANARITY
0.08
COMPLIANT TO JEDEC STANDARDS MO-220-VKKD-2
Figure 26. 48-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
7 mm × 7 mm Body, Very Thin Quad
(CP-48-3)
Dimensions shown in millimeters
Rev. PrC | Page 95 of 96
ADuC7060/ADuC7061
Preliminary Technical Data
9.20
9.00 SQ
8.80
1.60
MAX
37
48
36
1
PIN 1
0.15
0.05
7.20
7.00 SQ
6.80
TOP VIEW
1.45
1.40
1.35
0.20
0.09
7°
3.5°
0°
0.08
COPLANARITY
SEATING
PLANE
VIEW A
(PINS DOWN)
25
12
13
VIEW A
0.50
BSC
LEAD PITCH
24
0.27
0.22
0.17
ROTATED 90° CCW
COMPLIANT TO JEDEC STANDARDS MS-026-BBC
051706-A
0.75
0.60
0.45
Figure 27. 48-Lead Low Profile Quad Flat Package [LQFP]
(ST-48)
Dimensions shown in millimeters
ORDERING GUIDE
Model
ADuC7060BCPZ32 1
ADuC7060BSTZ321
ADuC7061BCPZ321
1
Temperature Range
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
Package Description
48-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
48-Lead Low Profile Quad Flat Package [LQFP]
32-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
Z = RoHS Compliant Part.
©2008 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
Pr07079-0-12/08(PrC)
Rev. PrC | Page 96 of 96
Package Option
CP-48-1
ST-48
CP-32-2
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