MAX7321

MAX7321

19-3738; Rev 1; 4/06

EVALUATION KIT

AVAILABLE

I

2

C Port Expander with 8 Open-Drain I/Os

General Description

The MAX7321 2-wire serial-interfaced peripheral features eight open-drain I/O ports with selectable internal pullups and transition detection. Any port may be used as a logic input or an open-drain output. Ports are overvoltage protected to +6V independent of supply voltage.

All I/O ports configured as inputs are continuously monitored for state changes (transition detection).

State changes are indicated by the open-drain INT output. The interrupt is latched, allowing detection of transient changes. When the MAX7321 is subsequently accessed through the serial interface, any pending interrupt is cleared.

The open-drain outputs are rated to sink 20mA and are capable of driving LEDs.

The RST input clears the serial interface, terminating any I

2

C* communication to or from the MAX7321.

The MAX7321 uses two address inputs with four-level logic to allow 16 I

2

C slave addresses. The slave address also determines the power-up logic state for the I/O ports, and enables or disables internal 40k

Ω pullups in groups of four ports.

The MAX7321 is one device in a family of pin-compatible port expanders with a choice of input ports, open-drain

I/O ports, and push-pull output ports (see Table 1).

The MAX7321 is available in 16-pin QSOP and TQFN packages, and is specified over the automotive temperature range (-40°C to +125°C).

Applications

Cell Phones

SAN/NAS

Servers

+

AD0

1

RST 2

AD2 3

P0 4

P1 5

P2 6

P3 7

GND 8

+

MAX7321

QSOP

Notebooks

Satellite Radio

Automotive

Pin Configurations

16 V+

15 SDA

14 SCL

13 INT

12 P7

11 P6

10 P5

9 P4

Features

400kHz I

2

C Serial Interface

+1.71V to +5.5V Operating Voltage

8 Open-Drain I/O Ports Rated to 20mA Sink Current

I/O Ports Are Overvoltage Protected to +6V

Any Port Can Be a Logic Input or an Open-Drain

Output

Selectable I/O Port Power-Up Default Logic States

Transient Changes Are Latched, Allowing Detection

Between Read Operations

♦ INT Output Alerts Change on Inputs

AD0 and AD2 Inputs Select from 16 Slave

Addresses

Low 0.6µA (typ) Standby Current

-40°C to +125°C Operating Temperature

Ordering Information

PART

TEMP

RANGE

PIN-

PACKAGE

TOP

MARK

PKG

CODE

MAX7321AEE+

-40°C to

+125°C

16 QSOP — E16-4

MAX7321ATE+

-40°C to

+125°C

**EP = Exposed paddle.

+Denotes lead-free package.

16 TQFN-EP** ADC T1633-4

Selector Guide

PART INPUTS

INTERRUPT

MASK

OPEN-

DRAIN

OUTPUTS

PUSH-PULL

OUTPUTS

MAX7319

MAX7320

8

MAX7321 Up to 8

MAX7322 4

MAX7323 Up to 4

MAX7328 Up to 8

MAX7329 Up to 8

Yes

Yes

Up to 8

Up to 4

Up to 8

Up to 8

4

8

4

*Purchase of I

2

C components from Maxim Integrated Products,

Inc., or one of its sublicensed Associated Companies, conveys a license under the Philips I

2

C Patent Rights to use these components in an I

2

C system, provided that the system conforms to the I

2

C Standard Specification as defined by Philips.

Pin Configurations are continued at end of data sheet.

Typical Application Circuit and Functional Diagram appear at end of data sheet.

________________________________________________________________ Maxim Integrated Products 1

For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at

1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.

I

2

C Port Expander with 8 Open-Drain I/Os

ABSOLUTE MAXIMUM RATINGS

(All voltages referenced to GND.)

Supply Voltage V+....................................................-0.3V to +6V

SCL, SDA, AD0, AD2, RST, INT, P0–P7 ...................-0.3V to +6V

P0–P7 Sink Current ............................................................ 25mA

SDA Sink Current ............................................................... 10mA

INT Sink Current..................................................................10mA

Total V+ Current..................................................................50mA

Total GND Current ...........................................................100mA

Continuous Power Dissipation (T

A

= +70°C)

16-Pin QSOP (derate 8.3mW/°C above +70°C)...........667mW

16-Pin TQFN (derate 15.6mW/°C above +70°C) .......1250mW

Operating Temperature Range .........................-40°C to +125°C

Junction Temperature ......................................................+150°C

Storage Temperature Range .............................-65°C to +150°C

Lead Temperature (soldering, 10s) .................................+300°C

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

ELECTRICAL CHARACTERISTICS

(V+ = +1.71V to +5.5V, T

A

= -40°C to +125°C, unless otherwise noted. Typical values are at V+ = +3.3V, T

A

= +25°C.) (Note 1)

CONDITIONS PARAMETER

Operating Supply Voltage

Power-On Reset Voltage

Standby Current

(Interface Idle)

SYMBOL

V+

V

POR

I

STB

V+ falling

SCL and SDA and other digital inputs at V+

MIN TYP MAX UNITS

1.71 5.50

V

1.6

V

0.6

1.5

µA

Supply Current

(Interface Running)

Input High Voltage

SDA, SCL, AD0, AD2, RST, P0–P7

Input Low Voltage

SDA, SCL, AD0, AD2, RST, P0–P7

Input Leakage Current

SDA, SCL, AD0, AD2, RST, P0–P7

Input Capacitance

SDA, SCL, AD0, AD2, RST, P0–P7

I

+

V

IH

V

IL

I

IH

, I

IL f

SCL

= 400kHz; other digital inputs at V+

V+ < 1.8V

V+

≥ 1.8

V+ < 1.8V

V+

≥ 1.8V

SDA, SCL, AD0, AD2, RST, P0–P7 at V+ or

GND, internal pullup disabled

0.8 x V+

0.7 x V+

-0.2

23

10

55

0.2 x V+

0.3 x V+

+0.2

µA

V

V

µA pF

Output Low Voltage

P0–P7

V

OL

V+ = +1.71V, I

SINK

= 5mA

V+ = +2.5V, I

SINK

= 10mA

V+ = +3.3V, I

SINK

= 15mA

V+ = +5V, I

SINK

= 20mA

90

110

130

140

180

210

230

250 mV

Output Low Voltage

SDA

Output Low Voltage

INT

Port Input Pullup Resistor

V

OLSDA

I

SINK

= 6mA

V

OLINT

I

SINK

= 5mA

R

PU

25

130

40

250

250

55 mV mV k

Ω

2 _______________________________________________________________________________________

I

2

C Port Expander with 8 Open-Drain I/Os

PORT AND INTERRUPT

INT TIMING CHARACTERISTICS

(V+ = +1.71V to +5.5V, T

A

= -40°C to +125°C, unless otherwise noted. Typical values are at V+ = +3.3V, T

A

= +25°C.) (Note 1)

PARAMETER

Port Output Data Valid

Port Input Setup Time

Port Input Hold Time

INT Input Data Valid Time

INT Reset Delay Time from STOP

INT Reset Delay Time from

Acknowledge

SYMBOL

t

PPV t

PSU t

PH t

IV t

IP t

IR

C

L

≤ 100pF

C

L

≤ 100pF

C

L

≤ 100pF

C

L

≤ 100pF

C

L

≤ 100pF

C

L

≤ 100pF

CONDITIONS MIN

0

4

TYP MAX

4

4

4

4

TIMING CHARACTERISTICS

(V+ = +1.71V to +5.5V, T

A

= -40°C to +125°C, unless otherwise noted. Typical values are at V+ = +3.3V, T

A

= +25°C.) (Note 1)

UNITS

µs

µs

µs

µs

µs

µs

SYMBOL

f

SCL

CONDITIONS MIN TYP MAX

400

UNITS

kHz

PARAMETER

Serial-Clock Frequency

Bus Free Time Between a STOP and a START Condition

Hold Time (Repeated) START

Condition

Repeated START Condition

Setup Time

STOP Condition Setup Time

Data Hold Time

Data Setup Time

SCL Clock Low Period

SCL Clock High Period

Rise Time of Both SDA and SCL

Signals, Receiving t

BUF t

HD, STA t

SU, STA t

SU, STO t

HD, DAT

(Note 2) t

SU, DAT t

LOW t

HIGH t

R

(Notes 3, 4)

1.3

0.6

0.6

0.6

100

1.3

0.7

0.9

300

µs

µs

µs ns

Fall Time of Both SDA and SCL

Signals, Receiving

Fall Time of SDA, Transmitting t

F t

F,TX

(Notes 3, 4)

(Notes 3, 4)

20 +

0.1C

b

20 +

0.1C

b

20 +

0.1C

b

300

250

µs

µs ns

µs

µs ns ns

Pulse Width of Spike Suppressed t

SP

(Note 5) 50 ns

Capacitive Load for Each Bus

Line

RST Pulse Width

RST Rising to START Condition

Setup Time t t

C b

W

RST

(Note 3)

500

1

400 pF ns

µs

Note 1: All parameters tested at T

A

= +25°C. Specifications over temperature are guaranteed by design.

Note 2: A master device must provide a hold time of at least 300ns for the SDA signal (referred to V

IL of the SCL signal) in order to bridge the undefined region of SCL’s falling edge.

Note 3: Guaranteed by design.

Note 4: C b

= total capacitance of one bus line in pF. I

SINK

≤ 6mA. t

R and t

F measured between 0.3 x V+ and 0.7 x V+.

Note 5: Input filters on the SDA and SCL inputs suppress noise spikes less than 50ns.

_______________________________________________________________________________________ 3

I

2

C Port Expander with 8 Open-Drain I/Os

(T

A

= +25°C, unless otherwise noted.)

STANDBY CURRENT vs. TEMPERATURE

2.0

1.8

1.6

1.4

1.2

1.0

0.8

V+ = +2.5V

V+ = +3.3V

f

SCL

= 0kHz

V+ = +5.0V

0.6

0.4

0.2

V+ = +1.71V

0

-40 -25 -10 5 20 35 50 65 80 95 110 125

TEMPERATURE (

°C)

Typical Operating Characteristics

60

50

SUPPLY CURRENT vs. TEMPERATURE

f

SCL

= 400kHz

V+ = +5.0V

40

30

V+ = +3.3V

20

V+ = +2.5V

10

V+ = +1.71V

0

-40 -25 -10 5 20 35 50 65 80 95 110 125

TEMPERATURE (

°C)

OUTPUT VOLTAGE LOW vs. TEMPERATURE

0.40

0.35

0.30

0.25

I

V+ = +3.3V

SINK

= 15mA

V+ = +2.5V

I

SINK

= 10mA

V+ = +5.0V

I

SINK

= 20mA

0.20

0.15

0.10

0.05

V+ = +1.71V

I

SINK

= 5mA

0

-40 -25 -10 5 20 35 50 65 80 95 110 125

TEMPERATURE (

°C)

8

13

14

15

16

Pin Description

QSOP

1, 3

2

4–7, 9–12

PIN

TQFN

15, 1

16

NAME

AD0,

AD2

FUNCTION

Address Inputs. Select device slave address with AD0 and AD2. Connect AD0 and

AD2 to either GND, V+, SCL, or SDA to give four logic combinations (see Table 3).

RST

Reset Input, Active Low. Drive RST low to clear the 2-wire interface.

2–5, 7–10 P0–P7 Input/Output Ports. P0 to P7 are open-drain I/Os.

6

11

12

13

14

EP

GND Ground

INT

Interrupt Output. INT is an open-drain output.

SCL I

2

C-Compatible Serial Clock Input

SDA I

2

C-Compatible Serial Data I/O

V+

EP

Positive Supply Voltage. Bypass V+ to GND with a ceramic capacitor of at least

0.047µF as close to the device as possible.

Exposed Pad. Connect exposed pad to GND.

4 _______________________________________________________________________________________

I

2

C Port Expander with 8 Open-Drain I/Os

Detailed Description

MAX7319–MAX7329 Family Comparison

The MAX7319–MAX7323 family consists of five pincompatible, eight-port expanders. Each version is optimized for different applications. The MAX7328 and

MAX7329 are industry standard parts.

The MAX7324–MAX7327 family consists of four pincompatible, 16-port expanders that integrate the functions of the MAX7320 and one of either the MAX7319,

MAX7321, MAX7322, or MAX7323.

Functional Overview

The MAX7321 is a general-purpose port expander operating from a +1.71V to +5.5V supply that provides eight open-drain I/O ports. Each open-drain output is rated to sink 20mA, and the entire device is rated to sink 100mA into all ports combined. The outputs drive loads connected to supplies up to +5.5V, independent of the MAX7321’s supply voltage.

The MAX7321 is set to one of 16 I

2

C slave addresses

(0x60 to 0x6F) using the address select inputs AD0 and

AD2, and is accessed over an I

2

C serial interface up to

400kHz. The RST input clears the serial interface in

Table 1. MAX7319–MAX7329 Family Comparison

PART

I

2

C

SLAVE

ADDRESS

8-PORT EXPANDERS

INPUTS

INPUT

INTERRUPT

MASK

OPEN-

DRAIN

OUTPUTS

PUSH-

PULL

OUTPUTS

APPLICATION

Input-only versions:

8 input ports with programmable latching transition detection interrupt and selectable pullups.

MAX7319 110xxxx 8 Yes — —

MAX7320 101xxxx

MAX7321 110xxxx Up to 8

MAX7322 110xxxx

4

Yes

Up to 8

8

4

Offers maximum versatility for automatic input monitoring. An interrupt mask selects which inputs cause an interrupt on transitions, and transition flags identify which inputs have changed (even momentarily) since the ports were last read.

Output-only versions:

8 push-pull outputs with selectable power-up default levels.

Push-pull outputs offer faster rise time than opendrain outputs, and require no pullup resistors.

I/O versions:

8 open-drain I/O ports with latching transition detection interrupt and selectable pullups.

Open-drain outputs can level shift the logic-high state to a higher or lower voltage than V+ using external pullup resistors. Any port can be used as an input by setting the open-drain output to logic-high.

Transition flags identify which inputs have changed

(even momentarily) since the ports were last read.

4 input-only, 4 output-only versions:

4 input ports with programmable latching transition detection interrupt and selectable pullups;

4 push-pull outputs with selectable power-up default levels.

_______________________________________________________________________________________ 5

I

2

C Port Expander with 8 Open-Drain I/Os

Table 1. MAX7319–MAX7329 Family Comparison (continued)

PART

I

2

C

SLAVE

ADDRESS

INPUTS

INPUT

INTERRUPT

MASK

OPEN-

DRAIN

OUTPUTS

PUSH-

PULL

OUTPUTS

MAX7323 110xxxx Up to 4

MAX7328

MAX7329

0100xxx

0111xxx

Up to 8

Up to 4

Up to 8

4

APPLICATION

4 I/O, 4 output-only versions:

4 open-drain I/O ports with latching transition detection interrupt and selectable pullups.

4 push-pull outputs with selectable power-up default levels.

8 open-drain I/O ports with nonlatching transition detection interrupt and pullups on all ports.

All ports power up as inputs (or logic-high outputs).

Any port can be used as an input by setting the open-drain output to logic-high.

16-PORT EXPANDERS

MAX7324

MAX7325

MAX7326

101xxxx and

110xxxx

MAX7327

8

Up to 8

4

Up to 4

Yes

Yes

Up to 8

Up to 4

8

8

12

12

Software equivalent to a MAX7320 plus a MAX7319.

Software equivalent to a MAX7320 plus a MAX7321.

Software equivalent to a MAX7320 plus a MAX7322.

Software equivalent to a MAX7320 plus a MAX7323.

case of a bus lockup, terminating any serial transaction to or from the MAX7321.

Any port can be configured as a logic input by setting the port output logic-high (logic-high for an open-drain output is high impedance). When the MAX7321 is read through the serial interface, the actual logic levels at the ports are read back.

The open-drain ports offer latching transition detection when used as inputs. All input ports are continuously monitored for changes. An input change sets 1 of 8 flag bits that identify changed input(s). All flags are cleared upon a subsequent read or write transaction to the

MAX7321.

A latching interrupt output, INT, is programmed to flag logic changes on ports used as inputs. Data changes on any input port forces INT to a logic-low. Changing the I/O port level through the serial interface does not cause an interrupt. The interrupt output INT is deasserted when the MAX7321 is next accessed through the serial interface.

Internal pullup resistors to V+ are selected by the address select inputs, AD0 and AD2. Pullups are enabled on the input ports in groups of four (see Table 3).

Use the slave address selection to ensure that I/O ports used as inputs are logic-high on power-up. I/O ports with internal pullups enabled default to a logic-high output state. Ports with internal pullups disabled default to a logic-low output state. Output port power-up logic states are selected by the address select inputs AD0 and AD2. Ports default to logic-high or logic-low on power-up in groups of four (see Table 3).

Initial Power-Up

On power-up, the transition detection logic is reset, and

INT is deasserted. The transition flags are cleared to indicate no data changes. The power-up default states of the eight I/O ports are set according to the I

2

C slave address selection inputs, AD0 and AD2 (Table 3). For

I/O ports used as inputs, ensure that the default states are logic-high so that the I/O ports power up in the high-impedance state. All I/O ports configured with pullups enabled also have a logic-high powerup state.

Power-On Reset

The MAX7321 contains an integral power-on reset

(POR) circuit that ensures all registers are reset to a known state on power-up. When V+ rises above V

POR

(1.6V max), the POR circuit releases the registers and

2-wire interface for normal operation. When V+ drops to less than V

POR

, the MAX7321 resets all register contents to the POR defaults (Table 3).

6 _______________________________________________________________________________________

I

2

C Port Expander with 8 Open-Drain I/Os

Table 2. Read and Write Access to Eight-Port Expander Family

PART

MAX7319

MAX7320

MAX7321

MAX7322

MAX7323

MAX7328

MAX7329

I

2

C SLAVE

ADDRESS

INPUTS

INTERRUPT

MASK

110xxxx

101xxxx

110xxxx

110xxxx

110xxxx

0100xxx

0111xxx

8

Up to 8

4

Up to 4

Up to 8

Up to 8

Yes

Yes

OPEN-

DRAIN

OUTPUTS

Up to 8

Up to 4

Up to 8

Up to 8

PUSH-

PULL

OUTPUTS

I

2

C DATA WRITE

8

4

<I7–I0 interrupt mask>

<O7–O0 port outputs>

<P7–P0 port outputs>

<O7, O6 outputs,

I5–I2 interrupt mask, O1, O0 outputs>

4 <port outputs>

I

2

C DATA READ

<I7–I0 port inputs>

<I7–I0 transition flags>

<O7-O0 port inputs>

<P7–P0 port inputs>

<P7–P0 transition flags>

<O7, O6, I5–I2, O1, O0 port inputs>

<0, 0, I5–I2 transition flags,

0, 0>

<O7, O6, P5–P2, O1, O0 port inputs>

<0, 0, P5–P2 transition flags,

0, 0>

<P7–P0 port outputs>

<P7–P0 port outputs>

<P7–P0 port inputs>

<P7–P0 port inputs>

RST Input

The RST input voids any I

2

C transaction involving the

MAX7321, forcing the MAX7321 into the I

2

C STOP condition. A reset does not affect the interrupt output (INT).

Standby Mode

When the serial interface is idle, the MAX7321 automatically enters standby mode, drawing minimal supply current.

Slave Address, Power-Up Default Logic

Levels, and Input Pullup Selection

Address inputs AD0 and AD2 determine the MAX7321 slave address, set the power-up I/O state for the ports, and select which inputs have pullup resistors. Internal pullups and power-up default states are set in groups of four ( Table 3). The MAX7319, MAX7321, MAX7322, and MAX7323 use a different range of slave addresses

(110xxxx) than the MAX7320 (101xxxx) (Table 2).

The MAX7321 slave address is determined on each I

2

C transmission, regardless of whether the transmission is actually addressing the MAX7321. The MAX7321 distinguishes whether address inputs AD2 and AD0 are connected to SDA or SCL instead of fixed logic levels V+ or

GND during this transmission. This means that the

MAX7321 slave address can be configured dynamically in the application without cycling the device supply.

On initial power-up, the MAX7321 cannot decode address inputs AD0 and AD2 fully until the first I

2

C transmission. AD0 and AD2 initially appear to be connected to V+ or GND. This is important because the address selection is used to determine the power-up logic state and whether pullups are enabled. However, at power-up, the I

2

C SDA and SCL bus interface lines are high impedance at the pins of every device (master or slave) connected to the bus, including the MAX7321.

This is guaranteed as part of the I

2

C specification.

Therefore, address inputs AD2 and AD0 that are connected to SDA or SCL normally appear at power-up to be connected to V+. The power-up logic uses AD0 to select the power-up state and whether pullups are enabled for ports P3–P0, and AD2 for ports P7–P4. The rule is that a logic-high, SDA, or SCL connection selects the pullups and sets the default logic state to high. A logic-low deselects the pullups and sets the default logic state to low (Table 3). The port configuration is correct on power-up for a standard I

2

C configuration, where SDA or SCL are pulled up to V+ by the external I

2

C pullup resistors.

_______________________________________________________________________________________ 7

I

2

C Port Expander with 8 Open-Drain I/Os

Table 3. MAX7321 Address Map

PIN CONNECTION

AD2 AD0

SCL

SCL

SCL

SCL

SDA

SDA

SDA

SDA

GND

GND

GND

GND

V+

GND

V+

SCL

SDA

GND

V+

SCL

SDA

GND

V+

SCL

SDA

GND

V+

V+

V+

V+

SCL

SDA

A6

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

A5

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

DEVICE ADDRESS

A4 A3 A2

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

1

1

1

1

1

1

1

1

1

0

0

0

0

0

0

0

0

1

0

0

0

1

1

1

1

1

1

A1

1

1

0

0

1

1

0

0

1

1

0

0

0

0

1

1

There are circumstances where the assumption that

SDA = SCL = V+ on power-up is not true—for example, in applications in which there is legitimate bus activity during power-up. Also, if SDA and SCL are terminated with pullup resistors to a different supply voltage than the MAX7321’s supply voltage, and if that pullup supply rises later than the MAX7321’s supply, then SDA or

SCL may appear at power-up to be connected to GND.

In such applications, use the four address combinations that are selected by connecting address inputs

AD2 and AD0 to V+ or GND (shown in bold in Table 3).

These selections are guaranteed to be correct at power-up, independent of SDA and SCL behavior. If one of the other 12 address combinations is used, an unexpected combination of pullups might be asserted until the first I

2

C transmission (to any device, not necessarily the MAX7321) is put on the bus, and an unexpected combination of ports may initialize as logic-low outputs instead of inputs or logic-high outputs.

A0

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

I7

Y

Y

Y

Y

Y

Y

Y

Y

Y

Y

Y

Y

Y

Y

Y

I6

40k

Ω INPUT PULLUP ENABLES

I5 I4 I3 I2 I1

Y

Y

Y

Y

Y

Y

Y

Y

Y

Y

Y

Y

Y

Y

Y

Y

Y

Y

Y

Y

Y

Y

Y

Y

Y

Y

Y

Y

Y

Y

Y

Y

Y

Y

Y

Y

Y

Y

Y

Y

Y

Y

Y

Y

Y

Y

Y

Y

Y

Y

Y

Y

Y

Y

Y

Y

Y

Y

Y

Y

Y

Y

Y

Y

Y

Y

Y

Y

Y

Port Inputs

I/O port inputs switch at the CMOS-logic levels as determined by the expander’s supply voltage, and are overvoltage tolerant to +6V, independent of the expander’s supply voltage.

I/O Port Input Transition Detection

All I/O ports configured as inputs are monitored for changes since the expander was last accessed through the serial interface. The state of the input ports is stored in an internal “snapshot” register for transition monitoring. The snapshot is continuously compared with the actual input conditions, and if a change is detected for any port, INT is asserted to signal a state change. An internal transition flag is set for that port.

The input is sampled (internally latched into the snapshot register) and the old transition flags cleared during the I

2

C acknowledge of every MAX7321 read and write access. The previous port transition flags are read through the serial interface as the second byte of a

2-byte read sequence.

I0

Y

Y

Y

Y

Y

Y

Y

Y

Y

Y

Y

Y

8 _______________________________________________________________________________________

I

2

C Port Expander with 8 Open-Drain I/Os

SDA t

HD,DAT t

SU,STA t

BUF t

LOW t

SU,DAT t

HIGH t

HD,STA t

SU,STO

SCL t

HD,STA t

R t

F

START CONDITION REPEATED START CONDITION

Figure 1. 2-Wire Serial Interface Timing Details

Serial Interface

Serial Addressing

The MAX7321 operates as a slave that sends and receives data through an I

2

C interface. The interface uses a serial data line (SDA) and a serial clock line (SCL) to achieve bidirectional communication between master(s) and slave(s). The master initiates all data transfers to and from the MAX7321 and generates the SCL clock that synchronizes the data transfer (Figure 1).

SDA operates as both an input and an open-drain output. A pullup resistor, typically 4.7k

Ω, is required on

SDA. SCL operates only as an input. A pullup resistor, typically 4.7k

Ω, is required on SCL if there are multiple masters on the 2-wire interface, or if the master in a single-master system has an open-drain SCL output.

Each transmission consists of a START condition sent by a master, followed by the MAX7321’s 7-bit slave address plus R/W bit, 1 or more data bytes, and finally a STOP condition (Figure 2).

START and STOP Conditions

Both SCL and SDA remain high when the interface is not busy. A master signals the beginning of a transmission with a START (S) condition by transitioning SDA from high to low while SCL is high. When the master has finished communicating with the slave, the master issues a STOP (P) condition by transitioning SDA from low to high while SCL is high. The bus is then free for another transmission (Figure 2).

Bit Transfer

One data bit is transferred during each clock pulse.

The data on SDA must remain stable while SCL is high

(Figure 3).

STOP

CONDITION

START

CONDITION

SDA

SCL

S

START

CONDITION

P

STOP

CONDITION

Figure 2. START and STOP Conditions

Acknowledge

The acknowledge bit is a clocked 9th bit the recipient uses to acknowledge receipt of each byte of data

(Figure 4). Each byte transferred effectively requires 9 bits. The master generates the 9th clock pulse, and the recipient pulls down SDA during the acknowledge clock pulse, such that the SDA line is stable low during the high period of the clock pulse. When the master is transmitting to the MAX7321, the MAX7321 generates the acknowledge bit because the device is the recipient. When the MAX7321 is transmitting to the master, the master generates the acknowledge bit because the master is the recipient.

Slave Address

The MAX7321 has a 7-bit-long slave address (Figure

5). The eighth bit following the 7-bit slave address is the R/W bit. It is low for a write command, and high for a read command.

The first (A6), second (A5), and third (A4) bits of the

MAX7321 slave address are always 1, 1, and 0.

Connect AD2 and AD0 to GND, V+

,

SDA, or SCL to select slave address bits A3, A2, A1, and A0. The

MAX7321 has 16 possible slave addresses ( Table 3), allowing up to 16 MAX7321 devices on an I

2

C bus.

_______________________________________________________________________________________ 9

I

2

C Port Expander with 8 Open-Drain I/Os

Accessing the MAX7321

The MAX7321 is accessed through an I

2

C interface. The transition flags are cleared, and INT is deasserted each time the device acknowledges the I

2

C slave address.

A single-byte read from the MAX7321 returns the status of the eight I/O ports.

A 2-byte read returns first the status of the eight I/O ports (as for a single-byte read), followed by the transition flags.

A multibyte read (more than 2 bytes before the I

2

C

STOP bit) repeatedly returns the port data, alternating with the transition flags. As the port data is resampled for each transmission, and the transition flags are reset each time, a multibyte read continuously returns the current data and identifies any changing ports.

If a port data change occurs during the read sequence,

INT is reasserted after the I

2

C STOP bit. The MAX7321 does not generate another interrupt during a singlebyte or multibyte read.

Port data is sampled during the preceding I

2

C acknowledge bit (the acknowledge bit for the I

2

C slave address in the case of a single-byte or 2-byte read).

A single-byte write to the MAX7321 sets the logic state of all eight I/O ports.

A multibyte write to the MAX7321 repeatedly sets the logic state of all eight I/O ports.

Reading from the MAX7321

A read from the MAX7321 starts with the master transmitting the MAX7321’s slave address with the R/W bit set high. The MAX7321 acknowledges the slave address, and samples the ports during the acknowledge bit. INT deasserts during the slave address acknowledge.

Typically, the master reads 1 or 2 bytes from the

MAX7321, each byte being acknowledged by the master upon reception with the exception of the last byte.

When the master reads 1 byte from the MAX7321 and subsequently issues a STOP condition (Figure 6), the

MAX7321 transmits the current port data, clears the change flags, and resets the transition detection. INT deasserts during the slave acknowledge. The new snapshot data is the current port data transmitted to the master; therefore, port changes ocurring during the

SDA

SCL

DATA LINE STABLE;

DATA VALID

CHANGE OF DATA

ALLOWED

Figure 3. Bit Transfer

START

CONDITION

SCL

SDA BY

TRANSMITTER

SDA BY

RECEIVER S

1 2

CLOCK PULSE

FOR ACKNOWLEDGMENT

8 9

Figure 4. Acknowledge

transmission are detected. INT remains high until the

STOP condition.

The master can read 2 bytes from the MAX7321 and then issue a STOP condition ( Figure 7). In this case, the

MAX7321 transmits the current port data, followed by the change flags. The change flags are then cleared, and transition detection resets. INT goes high (high impedance if an external pullup resistor is not fitted) during the slave acknowledge. The new snapshot data is the current port data transmitted to the master; therefore, port changes occurring during the transmission are detected.

INT remains high until the STOP condition.

10 ______________________________________________________________________________________

I

2

C Port Expander with 8 Open-Drain I/Os

.

SDA

1

MSB

SCL

Figure 5. Slave Address

1

0

A3 A2 A1 A0

LSB

R/W

ACK

P7 P6 P5

PORT I/O

P4

DATA

P3 P2 P1 P0 t

IV

S 1 1 0 MAX7321 SLAVE ADDRESS

R/W

1 A

D7 D6 D5 D4 D3 D2 D1 D0

PORT SNAPSHOT PORT SNAPSHOT

N P

SCL t

PH

PORT I/O

INT OUTPUT t

IR t

PSU

INT REMAINS HIGH UNTIL STOP CONDITION t

IP

Figure 6. Reading the MAX7321 (1 Data Byte)

I7 I6 I5

PORT I/O

I4 I3 I2 I1 I0

INTERRUPT FLAGS

F7

F6

F5 F4 F3 F2

F1

F0

S 1 1 0 MAX7321 SLAVE ADDRESS 1

A

R/W

D7 D6 D5 D4 D3 D2 D1 D0

PORT SNAPSHOT PORT SNAPSHOT

A D7 D6 D5 D4 D3 D2 D1 D0 N

PORT SNAPSHOT

P

SCL t

PH

PORTS t

IV

INT OUTPUT t

IR t

PSU

INT REMAINS HIGH UNTIL STOP CONDITION t

IP

S = START CONDITION

P = STOP CONDITION

SHADED = SLAVE TRANSMISSION

N = NOT ACKNOWLEDGE

Figure 7. Reading the MAX7321 (2 Data Bytes)

______________________________________________________________________________________ 11

I

2

C Port Expander with 8 Open-Drain I/Os

INTERNAL WRITE

TO PORT

DATA OUT

FROM PORT

SCL

SDA

S

1 2 3 4 5 6 7 8

SLAVE ADDRESS

0 A

START CONDITION R/W

DATA TO PORT

DATA 1 t

PV

Figure 8. Writing to the MAX7321

S = START CONDITION

P = STOP CONDITION

SHADED = SLAVE TRANSMISSION

N = NOT ACKNOWLEDGE t

PV

A

DATA TO PORT

DATA 2 t

PV

DATA 1 VALID t

PV

A

DATA 2 VALID

Writing to the MAX7321

A write to the MAX7321 starts with the master transmitting the MAX7321’s slave address with the R/W bit set low. The MAX7321 acknowledges the slave address, and samples the ports (takes a snapshot) during acknowledge. INT goes high (high impedance if an external pullup resistor is not fitted) during the slave acknowledge. Typically, the master proceeds to transmit 1 or more bytes of data. The MAX7321 acknowledges these subsequent bytes of data and updates the

I/O ports with each new byte until the master issues a

STOP condition ( Figure 8).

Applications Information

Port Input and I

2

C Interface Level

Translation from Higher or Lower

Logic Voltages

The MAX7321’s SDA, SCL, AD0, AD2, RST, INT, and I/O ports P0–P7 are overvoltage protected to +6V independent of V+. This allows the MAX7321 to operate from a lower supply voltage, such as +3.3V, while the I

2

C interface and/or any of the eight I/O ports are driven as inputs driven from a higher logic level, such as +5V.

The MAX7321 can operate from a higher supply voltage, such as +3V, while the I

2

C interface and/or some of the I/O ports P0–P7 are driven from a lower logic level, such as +2.5V. Apply a minimum voltage of 0.7 x

V+ to assert a logic-high on any I/O port. For example, a MAX7321 operating from a +5V supply may not recognize a +3.3V nominal logic-high. One solution for input-level translation is to drive MAX7321 I/Os from open-drain outputs. Use a pullup resistor to V+ or a higher supply to ensure a high logic voltage greater than 0.7 x V+.

Port-Output Port-Level Translation

The open-drain output architecture allows for level translation to higher or lower voltages than the

MAX7321’s supply. Use an external pullup resistor on any output to convert the high-impedance logic-high condition to a positive voltage level. The resistor can be connected to any voltage up to +6V, and the resistor value chosen to ensure no more than 20mA is sunk in the logic-low condition. For interfacing CMOS inputs, a pullup resistor value of 220k

Ω is a good starting point.

Use a lower resistance to improve noise immunity, in applications where power consumption is less critical, or where a faster rise time is needed for a given capacitive load.

Each of the I/O ports P0–P7 has a protection diode to

GND (Figure 9). When a port is driven to a voltage lower than GND, the protection diode clamps the voltage to a diode drop below GND.

Each of the I/O ports P0–P7 also has a 40k

Ω (typ) pullup resistor that can be enabled or disabled. When a port is driven to a voltage higher than V+

, the body diode of the pullup enable switch conducts and the 40k

Ω pullup resistor is enabled. When the MAX7321 is powered down (V+ = 0), each I/O port appears as a 40k

Ω resistor in series with a diode connected to zero. I/O ports are protected to +6V under any of these circumstances

(Figure 9).

12 ______________________________________________________________________________________

I

2

C Port Expander with 8 Open-Drain I/Os

Functional Diagram

AD0

AD2

SCL

SDA

INPUT

FILTER

I

2

C

CONTROL

I/O

PORTS

P7

P6

P5

P4

P3

P2

P1

P0

INT

RST

POWER-

ON RESET

MAX7321

Driving LED Loads

When driving LEDs, a resistor must be fitted in series with the LED to limit the LED current to no more than

20mA. Connect the LED cathode to the MAX7321 port, and the LED anode to V+ through the series currentlimiting resistor, R

LED

. Set the port output low to illuminate the LED. Choose the resistor value according to the following formula:

R

LED

= (V

SUPPLY

- V

LED

- V

OL

) / I

LED where:

R

LED is the resistance of the resistor in series with the

LED (

Ω).

V

SUPPLY is the supply voltage used to drive the LED (V).

V

LED is the forward voltage of the LED (V).

V

OL is the output-low voltage of the MAX7321 when sinking I

LED

(V).

I

LED is the desired operating current of the LED (A).

For example, to operate a 2.2V red LED at 10mA from a

+5V supply:

R

LED

= (5 - 2.2 - 0.07) / 0.010 = 270

Ω.

PULLUP

ENABLE

INPUT

OUTPUT

V+

V+

Figure 9. MAX7321 I/O Structure

40k

Ω

MAX7321

P0–P7

______________________________________________________________________________________ 13

I

2

C Port Expander with 8 Open-Drain I/Os

Driving Load Currents Higher than 20mA

The MAX7321 can be used to drive loads, such as relays, that draw more than 20mA by paralleling outputs. Use at least one output per 20mA of load current; for example, a 5V, 330mW relay draws 66mA, and therefore, requires four paralleled outputs. Any combination of outputs can be used as part of a load-sharing design because any combination of ports can be set or cleared at the same time by writing the MAX7321. Do not exceed a total sink current of 100mA for the device.

The MAX7321 must be protected from the negative voltage transient generated when switching off inductive loads (such as relays), by connecting a reversebiased diode across the inductive load. Choose the peak current for the diode to be greater than the inductive load’s operating current.

Power-Supply Considerations

The MAX7321 operates with a supply voltage of +1.71V

to +5.5V over the -40°C to +125°C temperature range.

Bypass the supply to GND with a ceramic capacitor of at least 0.047µF as close to the device as possible. For the TQFN version, additionally connect the exposed pad to GND.

Pin Configurations (continued)

TOP VIEW

12 11 10

SDA 13

V+

14

AD0 15

RST

16

MAX7321

+

*EP

1 2 3

9

4

8

P5

7 P4

6

GND

5 P3

TQFN

*EXPOSED PADDLE, CONNECTED TO GND

+

μC

SCL

SDA

RST

INT

Typical Application Circuit

+5V

+3.3V

0.047

μF

V+

SCL

SDA

RST

INT

MAX7321

AD0

AD2

P4

P3

P2

P1

P0

P7

P6

P5

GND

I/O

I/O

I/O

I/O

14 ______________________________________________________________________________________

I2C Port Expander with 8 Open-Drain I/Os

Package Information

(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.)

______________________________________________________________________________________ 15

I2C Port Expander with 8 Open-Drain I/Os

Package Information (continued)

(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.)

MARKING

E/2

E

D

D/2

AAAA

(NE - 1) X e

(ND - 1) X e e

D2/2

D2 k

L

E2

E2/2 b

0.10 M C A B

0.10 C 0.08 C

A

A2

A1

L L e e

PACKAGE OUTLINE

8, 12, 16L THIN QFN, 3x3x0.8mm

21-0136 I

1

2

16 ______________________________________________________________________________________

I2C Port Expander with 8 Open-Drain I/Os

Package Information (continued)

(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.)

PKG

REF.

A b

L

N

ND

D

E e

NE

A1

A2 k

8L 3x3

MIN.

NOM. MAX.

0.70

0.75

0.80

0.25

0.30

0.35

2.90

3.00

3.10

2.90

3.00

3.10

0.65 BSC.

0.35

0.55

0.75

8

2

0

2

0.02

0.25

0.20 REF

-

0.05

-

MIN.

12L 3x3

NOM. MAX.

0.70

0.20

0.75

0.25

0.80

0.30

2.90

3.00

3.10

2.90

3.00

0.50 BSC.

3.10

0.45

0.55

0.65

12

3

0

3

0.02

0.25

0.20 REF

-

0.05

-

MIN.

16L 3x3

NOM.

MAX.

0.70

0.20

0.75

0.25

0.80

0.30

2.90

3.00

3.10

2.90

3.00

0.50 BSC.

3.10

0.30

0.40

0.50

16

4

0

4

0.02

0.25

0.20 REF

-

0.05

-

PKG.

CODES

TQ833-1

T1233-1

T1233-3

T1233-4

T1633-2

T1633F-3

T1633FH-3

T1633-4

T1633-5

0.95

0.95

0.65

0.65

0.95

0.95

MIN.

0.25

0.95

0.95

EXPOSED PAD VARIATIONS

D2

NOM.

0.70

1.10

1.10

1.10

1.10

0.80

0.80

1.10

1.10

MAX.

1.25

1.25

1.25

1.25

1.25

0.95

0.95

1.25

1.25

MIN.

0.25

0.95

0.95

0.95

0.95

0.65

0.65

0.95

0.95

E2

NOM.

0.70

1.10

1.10

1.10

1.10

0.80

0.80

1.10

1.10

MAX.

1.25

1.25

1.25

1.25

1.25

0.95

0.95

1.25

1.25

PIN ID

0.35 x 45

°

0.35 x 45

°

0.35 x 45

°

0.35 x 45

°

0.35 x 45

°

0.225 x 45

°

0.225 x 45

°

0.35 x 45

°

0.35 x 45

°

JEDEC

WEEC

WEED-1

WEED-1

WEED-1

WEED-2

WEED-2

WEED-2

WEED-2

WEED-2

NOTES:

1. DIMENSIONING & TOLERANCING CONFORM TO ASME Y14.5M-1994.

2. ALL DIMENSIONS ARE IN MILLIMETERS. ANGLES ARE IN DEGREES.

3. N IS THE TOTAL NUMBER OF TERMINALS.

4. THE TERMINAL #1 IDENTIFIER AND TERMINAL NUMBERING CONVENTION SHALL CONFORM TO

JESD 95-1 SPP-012. DETAILS OF TERMINAL #1 IDENTIFIER ARE OPTIONAL, BUT MUST BE LOCATED

WITHIN THE ZONE INDICATED. THE TERMINAL #1 IDENTIFIER MAY BE EITHER A MOLD OR

MARKED FEATURE.

5. DIMENSION b APPLIES TO METALLIZED TERMINAL AND IS MEASURED BETWEEN 0.20 mm AND 0.25 mm

FROM TERMINAL TIP.

6. ND AND NE REFER TO THE NUMBER OF TERMINALS ON EACH D AND E SIDE RESPECTIVELY.

7. DEPOPULATION IS POSSIBLE IN A SYMMETRICAL FASHION.

8. COPLANARITY APPLIES TO THE EXPOSED HEAT SINK SLUG AS WELL AS THE TERMINALS .

9. DRAWING CONFORMS TO JEDEC MO220 REVISION C.

10. MARKING IS FOR PACKAGE ORIENTATION REFERENCE ONLY.

11. NUMBER OF LEADS SHOWN ARE FOR REFERENCE ONLY.

12. WARPAGE NOT TO EXCEED 0.10mm.

PACKAGE OUTLINE

8, 12, 16L THIN QFN, 3x3x0.8mm

21-0136 I

2

2

Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.

17 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600

© 2006 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products, Inc.

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