MAX5073

MAX5073
19-3504; Rev 2; 2/06
2.2MHz, Dual-Output Buck or Boost Converter
with Internal Power MOSFETs
♦ 0.8V (Buck) to 28V (Boost) Output Voltage
♦ Two Independent Output DC-DC Converters
with Internal Power MOSFETs
♦ Each Output can be Configured in Buck or Boost
Mode
♦ IOUT1 and IOUT2 of 2A and 1A (Respectively) in
Buck Mode
♦ 180° Out-of-Phase Operation
♦ Clock Output for Four Phase Operation
♦ Switching Frequency Programmable from 200kHz
to 2.2MHz
♦ Digital Soft-Start and Sync Input
♦ Individual Converter Shutdown and Power-Good
Output
♦ Short-Circuit Protection (Buck)/Maximum DutyCycle Limit (Boost)
♦ Thermal Shutdown
♦ Thermally Enhanced 28-Pin Thin QFN Package
Dissipates up to 2.7W at +70°C
-40°C to +85°C
28 Thin QFN-EP*
T2855-6
(5mm x 5mm)
MAX5073ETI+
-40°C to +85°C
28 Thin QFN-EP*
T2855-6
(5mm x 5mm)
*EP = Exposed pad.
+Denotes lead-free package.
Ordering Information continued at end of data sheet.
EN1
FB1
COMP1
16
15
PGOOD2
22
14
BYPASS
SOURCE1
23
13
VL
SOURCE1
24
12
VL
SGND
25
11
V+
PGND
26
10
OSC
SOURCE2
27
9
N.C.
SOURCE2
28
8
SYNC
MAX5073
1
2
3
4
5
6
7
COMP2
MAX5073ETI
17
FB2
PIN-PACKAGE
18
EN2
TEMP RANGE
19
DRAIN2
PART
20
DRAIN2
PKG
CODE
21
BST2/VDD2
Ordering Information
DRAIN1
Applications
Automotive Radio Power Supply
Point-of-Load DC-DC Converters
Telecom Line Card
Networking Line Card
Power-Over-Ethernet Postregulation for PDs
DRAIN1
TOP VIEW
BST1/VDD1
Pin Configuration
PGOOD1
The MAX5073 is available in a thermally enhanced 28pin thin QFN package that can dissipate 2.7W at +70°C
ambient temperature. The device is rated for operation
over the -40°C to +85°C extended, or -40°C to +125°C
automotive temperature range.
♦ 4.5V to 5.5V or 5.5V to 23V Input Supply
Voltage Range
CLKOUT
The MAX5073 is a dual-output DC-DC converter with integrated high-side n-channel power MOSFETs. Each output
can be configured either as a buck converter or a boost
converter. The device is capable of operating from a wide
5.5V to 23V input voltage range. Each output is programmable down to 0.8V in the buck mode and up to 28V in
the boost mode with an output voltage accuracy of ±1%.
In the buck mode, converter 1 and converter 2 can deliver 2A and 1A, respectively. The output switching frequency of each converter can be programmed from 200kHz to
2.2MHz to avoid harmonics in a radio power supply or to
reduce the size of the power supply. Each output operates 180° out-of-phase thus reducing input-capacitor ripple current, size, and cost. A SYNC input facilitates
external frequency synchronization. Moreover, a CLKOUT
output provides out-of-phase clock signal with respect to
converter 2, allowing four-phase operation using two
MAX5073 ICs in master-slave configuration.
The MAX5073 includes an internal digital soft-start that
reduces inrush current, eliminates output-voltage overshoot, and ensures monotonic rise in output voltage
during power-up. The device includes individual shutdown and a power-good output for each converter.
Protection features include output short-circuit protection for buck mode and maximum duty-cycle limit for
boost operation, as well as thermal shutdown.
Features
THIN QFN
________________________________________________________________ Maxim Integrated Products
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
1
MAX5073
General Description
MAX5073
2.2MHz, Dual-Output Buck or Boost Converter
with Internal Power MOSFETs
ABSOLUTE MAXIMUM RATINGS
V+ to PGND............................................................-0.3V to +25V
SGND to PGND .....................................................-0.3V to +0.3V
VL to SGND...................-0.3V to the lower of +6V or (V+ + 0.3V)
BST1/VDD1, BST2/VDD2, DRAIN_, PGOOD2, PGOOD1 to
SGND .................................................................-0.3V to +30V
BST1/VDD1 to SOURCE1,
BST2/VDD2 to SOURCE2 ....................................-0.3V to +6V
SOURCE_ to SGND................................................-0.6V to +25V
EN_ to SGND .............................................-0.3V to (VL to +0.3V)
CLKOUT, BYPASS, OSC, COMP1,
COMP2, SYNC, FB_ to SGND ..................-0.3V to (VL + 0.3V)
SOURCE1, DRAIN1 Peak Current ..............................5A for 1ms
SOURCE2, DRAIN2 Peak Current ..............................3A for 1ms
VL, BYPASS to SGND Short Circuit............................Continuous
Continuous Power Dissipation (TA = +70°C)
28-Pin Thin QFN (derate 21.3mW/°C above +70°C).....2758mW*
Package Junction-to-Case Thermal Resistance (θJC).......2°C/W
Operating Temperature Ranges:
MAX5073ETI (TMIN to TMAX)............................-40°C to +85°C
MAX5073ATI (TMIN to TMAX) .........................-40°C to +125°C
Junction Temperature ......................................................+150°C
Storage Temperature Range .............................-65°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
*As per JEDEC51 standard.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(V+ = VL = 5.2V or V+ = 5.5V to 23V, EN_ = VL, SYNC = GND, IVL = 0mA, PGND = SGND, CBYPASS = 0.22µF, CVL = 4.7µF (ceramic), ROSC = 10kΩ (circuit of Figure 1), TA = TJ = TMIN to TMAX, unless otherwise noted.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
SYSTEM SPECIFICATIONS
Input Voltage Range
V+
Operating Supply Current
IQ
V+ Standby Supply Current
Efficiency
ISTBY
η
(Note 2)
5.5
23.0
VL = V+
4.5
5.5
VL unloaded, no switching, VFB_ = 1V, V+ =
12V, ROSC = 60kΩ
2.2
4
EN_ = 0, PGOOD_ floating, V+ = 12V,
ROSC = 60kΩ (MAX5073ETI)
0.6
1.2
EN_ = 0, PGOOD_ floating, V+ = 12V,
ROSC = 60kΩ (MAX5073ATI)
0.6
VOUT1 = 3.3V at 1.5A,
VOUT2 = 2.5V at 0.75A
(fSW = 1.25MHz)
V
mA
mA
V+ = VL = 5V
82
V+ = 12V
80
V+ = 16V
78
1.4
%
STARTUP/VL REGULATOR
VL Undervoltage Lockout Trip
Level
UVLO
VL falling
3.95
VL Undervoltage Lockout
Hysteresis
VL Output Voltage
4.1
4.25
175
VL
V+ = 5.5V to 23V, ISOURCE = 0 to 40mA
V
mV
4.9
5.2
5.5
IBYPASS = 0, ROSC = 60kΩ (MAX5073ETI)
1.98
2.00
2.02
IBYPASS = 0, ROSC = 60kΩ (MAX5073ATI)
1.975
2.00
2.025
0
2
10
V
BYPASS OUTPUT
BYPASS Voltage
BYPASS Load Regulation
VBYPASS
∆VBYPASS
0 ≤ IBYPASS ≤ 50µA, ROSC = 60kΩ
V
mV
SOFT-START
Digital Ramp Period
Soft-Start Steps
2
Internal 6-bit DAC
2048
fOSC
clock
cycles
64
steps
_______________________________________________________________________________________
2.2MHz, Dual-Output Buck or Boost Converter
with Internal Power MOSFETs
(V+ = VL = 5.2V or V+ = 5.5V to 23V, EN_ = VL, SYNC = GND, IVL = 0mA, PGND = SGND, CBYPASS = 0.22µF, CVL = 4.7µF (ceramic), ROSC = 10kΩ (circuit of Figure 1), TA = TJ = TMIN to TMAX, unless otherwise noted.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
250
nA
VOLTAGE-ERROR AMPLIFIER
FB_ Input Bias Current
IB(EA)
FB_ Input Voltage Set Point
FB_ to COMP_
Transconductance
gM
0°C ≤ TA ≤ +70°C
0.792
0.8
0.808
-40°C ≤ TA ≤ +85°C
0.788
0.8
0.812
-40°C ≤ TJ ≤ +125°C (MAX5073ATI only)
0.788
0.8
0.812
0°C to +85°C
1.25
2
2.70
-40°C to +85°C
1.2
2
2.9
-40°C to +125°C (MAX5073ATI only)
1.2
2
2.9
ISWITCH = 100mA,
VBST1/VDD1 to VSOURCE1 = 5.2V
(MAX5073ETI)
195
290
ISWITCH = 100mA,
VBST1/VDD1 to VSOURCE1 = 5.2V
(MAX5073ATI)
195
330
ISWITCH = 100mA,
VBST1/VDD1 to VSOURCE1 = 4.5V
(MAX5073ETI)
200
315
ISWITCH = 100mA,
VBST1/VDD1 to VSOURCE1 = 4.5V
(MAX5073ATI)
200
350
ISWITCH = 100mA,
VBST2/VDD2 to VSOURCE2 = 5.2V
330
630
ISWITCH = 100mA,
VBST2/VDD2 to VSOURCE2 = 4.5V
350
690
V
mS
INTERNAL PMOSFETS
On-Resistance Converter 1
RON1
On-Resistance Converter 2
RON2
mΩ
mΩ
Minimum Converter 1 Output Current
IOUT1
VOUT1 = 3.3V, V+ = 12V (Note 3)
2
A
Minimum Converter 2 Output Current
IOUT2
VOUT2 = 2.5V, V+ = 12V (Note 3)
1
A
Converter 1 MOSFET Leakage
Current
ILK1
EN1 = 0V, VDS = 23V
10
µA
Converter 2 MOSFET Leakage
Current
ILK2
EN2 = 0V, VDS = 23V
10
µA
INTERNAL SWITCH CURRENT LIMIT
Current-Limit Converter 1
ICL1
Current-Limit Converter 2
ICL2
V+ = 12V (MAX5073ETI)
2.3
3
4.3
V+ = 12V (MAX5073ATI)
2.3
3
4.6
MAX5073ETI
1.38
1.8
2.10
MAX5073ATI
1.38
1.8
2.20
A
A
_______________________________________________________________________________________
3
MAX5073
ELECTRICAL CHARACTERISTICS (continued)
MAX5073
2.2MHz, Dual-Output Buck or Boost Converter
with Internal Power MOSFETs
ELECTRICAL CHARACTERISTICS (continued)
(V+ = VL = 5.2V or V+ = 5.5V to 23V, EN_ = VL, SYNC = GND, IVL = 0mA, PGND = SGND, CBYPASS = 0.22µF, CVL = 4.7µF (ceramic), ROSC = 10kΩ (circuit of Figure 1), TA = TJ = TMIN to TMAX, unless otherwise noted.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
INTERNAL OSCILLATOR/SYNC
Maximum Duty Cycle
DMAX
Switching Frequency Range
fSW
Switching Frequency
fSET
Switching Frequency Accuracy
SYNC Frequency Range
fSYNC
SYNC High Threshold
VSYNCH
SYNC Low Threshold
VSYNCL
SYNC Input Min Pulse Width
tSYNCIN
Clock Output Phase Delay
CLKOUT
PHASE
SYNC to SOURCE1 Phase Delay
SYNC = SGND, fSW = 1.25MHz
84
86
95
SYNC = SGND, fSW = 2.2MHz
84
86
95
Each converter
200
ROSC = 10kΩ, each converter
1125
1250
%
2200
kHz
1375
kHz
5.6kΩ ≤ ROSC ≤ 56kΩ, 1% each converter
-15
+15
%
SYNC input frequency is twice the
individual converter frequency
400
4400
kHz
2.4
V
0.8
ROSC = 60kΩ, 1%, with respect to converter
2 / SOURCE2 waveform
SYNCPHASE ROSC = 60kΩ, 1%
Clock Output High Level
VCLKOUTH
VL = 5.2V, sourcing 5mA
Clock Output Low Level
VCLKOUTL
VL = 5.2V, sinking 5mA
V
100
ns
45
degrees
45
degrees
4
V
0.4
V
EN_ INPUTS
EN_ Input High Threshold
EN_ Input Low Threshold
EN_ Bias Current
VIH
V+ = VL = 5.2V
VIL
V+ = VL = 5.2V
2.4
1.8
1.2
IB(EN)
V
0.8
V
250
nA
95
% VOUT
POWER-GOOD OUTPUT (PGOOD_)
PGOOD_ Threshold
PGOODVTH_
PGOOD_ Output Voltage
VPGOOD_
PGOOD_ Output Leakage Current
ILKPGOOD_
PGOOD goes high after VOUT crosses
PGOOD_ threshold
90
92.5
ISINK = 3mA (MAX5073ETI)
0.4
ISINK = 3mA (MAX5073ATI)
0.52
V+ = VL = 5.2V, VPGOOD_ = 23V, VFB_ = 1V
1
V
µA
THERMAL MANAGEMENT
Thermal Shutdown
TSHDN
Junction temperature
+150
°C
Thermal Hysteresis
THYST
Junction temperature
30
°C
Note 1: Specifications at -40°C are guaranteed by design and not production tested.
Note 2: Operating supply range (V+) is guaranteed by VL line regulation test. Connect V+ to VL for 5V operation.
Note 3: Output current may be limited by the power dissipation of the package, refer to the Power Dissipation section in the
Applications Information.
4
_______________________________________________________________________________________
2.2MHz, Dual-Output Buck or Boost Converter
with Internal Power MOSFETs
VIN = 12.0V
60
VIN = 16.0V
50
40
70
60
20
20
VOUT = 3.3V
fSW = 2.2MHz
80
70
VIN = 3.3V
60
50
40
20
VOUT = 2.5V
fSW = 2.2MHz
VOUT = 12V
fSW = 2.2MHz
10
0
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
VIN = 5V
90
30
10
0
0
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9 1.0
0.02
0.08
0.14
0.20
LOAD (A)
LOAD (A)
LOAD (A)
OUTPUT1 VOLTAGE (BUCK CONVERTER)
vs. LOAD CURRENT
OUTPUT2 VOLTAGE (BUCK CONVERTER)
vs. LOAD CURRENT
VL OUTPUT VOLTAGE
vs. CONVERTER SWITCHING FREQUENCY
3.30
MAX5073 toc06
BOTH CONVERTERS SWITCHING
5.45
5.40
5.35
2.55
VL (V)
OUTPUT2 VOLTGE (V)
3.35
5.50
MAX5073 toc05
2.60
MAX5073 toc04
3.40
OUTPUT1 VOLTAGE (V)
VIN = 16.0V
40
30
10
VIN = 12.0V
50
30
100
EFFICIENCY (%)
70
VIN = 5V
80
EFFICIENCY (%)
EFFICIENCY (%)
80
90
OUTPUT2 EFFICIENCY (BOOST CONVERTER)
vs. LOAD CURRENT
MAX5073 toc02
VIN = 5V
90
100
MAX5073 toc01
100
OUTPUT2 EFFICIENCY (BUCK CONVERTER)
vs. LOAD CURRENT
MAX5073 toc03
OUTPUT1 EFFICIENCY (BUCK CONVERTER)
vs. LOAD CURRENT
5.30
VIN = 23V
5.25
5.20
2.50
5.15
3.25
5.10
VIN = 5.5V
5.05
3.20
2.45
0
0.5
1.0
1.5
5.00
0
0.25
0.50
0.75
1.00
0.1
0.6
1.1
1.6
2.1
2.6
LOAD (A)
LOAD (A)
SWITCHING FREQUENCY (fSW) (MHz)
VL DROPOUT VOLTAGE vs. EACH CONVERTER
SWITCHING FREQUENCY
EACH CONVERTER SWITCHING FREQUENCY
vs. ROSC
EACH CONVERTER SWITCHING FREQUENCY
vs. TEMPERATURE
0.25
0.20
VIN = 5V
0.15
0.10
VIN = 4.5V
0.05
0
1
0.1
0
0.5
1.0
1.5
2.0
SWITCHING FREQUENCY (fSW) (MHz)
2.5
MAX5073 toc09
10
SWITCHING FREQUENCY (fSW) (MHz)
0.30
10
MAX5073 toc08
VIN = 5.5V
SWITCHING FREQUENCY (fSW) (MHz)
MAX5073 toc07
0.35
DROPOUT VOLTAGE (V)
2.0
2.2MHz
1.25MHz
1
0.6MHz
0.3MHz
0.1
0
20
40
ROSC (kΩ)
60
80
-50
0
50
100
150
TEMPERATURE (°C)
_______________________________________________________________________________________
5
MAX5073
Typical Operating Characteristics
(V+ = VL = 5.2V, TA = +25°C, unless otherwise noted.)
MAX5073
2.2MHz, Dual-Output Buck or Boost Converter
with Internal Power MOSFETs
Typical Operating Characteristics (continued)
(V+ = VL = 5.2V, TA = +25°C, unless otherwise noted.)
CONVERTER 1 LOAD-TRANSIENT RESPONSE
(BUCK CONVERTER)
LINE-TRANSIENT RESPONSE
(BUCK CONVERTER)
MAX5073 toc11
MAX5073 toc10
VIN
5V/div
VOUT1 = 3.3V
AC-COUPLED
200mV/div
0V
VOUT1 = 3.3V/1.5A
AC-COUPLED
200mV/div
IOUT1
1A/div
VOUT2 = 2.5V/0.75A
AC-COUPLED
200mV/div
0A
100µs/div
1ms/div
CONVERTER 2 LOAD-TRANSIENT RESPONSE
(BUCK CONVERTER)
SOFT-START/SOFT-STOP
MAX5073 toc12
MAX5073 toc13
VOUT1 = 3.3V
AC-COUPLED
100mV/div
ENABLE
5V/div
0V
VOUT2 = 2.5V
AC-COUPLED
100mV/div
VOUT1 = 3.3V/1A
2V/div
0V
VOUT2 = 2.5V/0.5A
2V/div
IOUT2
500mA/div
0A
100µs/div
0V
2ms/div
LOAD-TRANSIENT RESPONSE
(BOOST CONVERTER)
OUT-OF-PHASE OPERATION
MAX5073 toc15
MAX5073 toc14
VOUT1 = 3.3V
AC-COUPLED
200mV/div
SOURCE2
5V/div
0V
VOUT2 = 12V
AC-COUPLED
200mV/div
SOURCE1
5V/div
0V
INPUT RIPPLE
AC-COUPLED
20mV/div
CLKOUT
5V/div
0V
IOUT2
50mA/div
0A
100µs/div
6
100ns/div
_______________________________________________________________________________________
2.2MHz, Dual-Output Buck or Boost Converter
with Internal Power MOSFETs
V+ STANDBY SUPPLY CURRENT (ISTBY)
vs. TEMPERATURE
EXTERNAL SYNCHRONIZATION
MAX5073 toc16
MAX5073 toc17
1.8
SYNC
5V/div
0V
ROSC = 10kΩ
1.4
ISTBY (mA)
SOURCE1
5V/div
0V
VOUT1 RIPPLE
AC-COUPLED
20mV/div
CLKOUT
5V/div
0V
1.0
ROSC = 60kΩ
0.6
0.2
-40
200ns/div
-7
26
59
92
125
TEMPERATURE (°C)
V+ SWITCHING SUPPLY CURRENT (ISUPPLY)
vs. TEMPERATURE
30
3.38
3.36
OUTPUT1 VOLTAGE (V)
fSW = 2.2MHz
25
fSW = 1.25MHz
20
fSW = 600kHz
15
fSW = 300kHz
NO LOAD
3.34
3.32
50% LOAD
3.30
3.28
3.26
3.24
10
3.22
5
-40
-7
26
59
92
3.20
125
-50
TEMPERATURE (°C)
0
50
100
150
TEMPERATURE (°C)
OUTPUT2 VOLTAGE (BUCK CONVERTER)
vs. TEMPERATURE
MAX5073 toc20
2.60
50% LOAD
OUTPUT2 VOLTAGE (V)
ISUPPLY (mA)
MAX5073 toc19
3.40
MAX5073 toc18
35
OUTPUT1 VOLTAGE (BUCK CONVERTER)
vs. TEMPERATURE
2.55
NO LOAD
2.50
2.45
2.40
-50
0
50
100
150
TEMPERATURE (°C)
_______________________________________________________________________________________
7
MAX5073
Typical Operating Characteristics (continued)
(V+ = VL = 5.2V, TA = +25°C, unless otherwise noted.)
Typical Operating Characteristics (continued)
(V+ = VL = 5.2V, TA = +25°C, unless otherwise noted.)
OUTPUT LOAD CURRENT LIMIT
vs. TEMPERATURE
VIN = 5.5V
fSW = 2.2MHz
2.75
FOUR-PHASE OPERATION
(SEE FIGURE 3)
MAX5073 toc22
MAX5073 toc21
3.00
OUTPUT CURRENT LIMIT (A)
MAX5073
2.2MHz, Dual-Output Buck or Boost Converter
with Internal Power MOSFETs
SOURCE1
(MASTER)
0V
2.50
OUTPUT1
2.25
SOURCE2
(MASTER)
0V
2.00
OUTPUT2
1.75
SOURCE1
(SLAVE)
0V
1.50
1.25
SOURCE2
(SLAVE)
1.00
-40
-5
30
65
100
400ns/div
TEMPERATURE (°C)
Pin Description
PIN
NAME
1
CLKOUT
2
8
FUNCTION
Clock Output. CLKOUT is 45° phase-shifted with respect to converter 2 (SOURCE2, Figure 3). Connect
CLKOUT (master) to the SYNC of a second MAX5073 (slave) for a four-phase converter.
Buck Converter Operation—Bootstrap Flying-Capacitor Connection for Converter 2. Connect BST2/VDD2
to an external ceramic capacitor and diode according to the standard application circuit (Figure 1).
BST2/VDD2
Boost Converter Operation—Driver Bypass Capacitor Connection. Connect a low-ESR 0.1µF ceramic
capacitor from BST2/VDD2 to PGND (Figure 8).
3, 4
DRAIN2
Connection to Converter 2 Internal MOSFET Drain. Buck converter operation—use the MOSFET as a
high-side switch and connect DRAIN2 to the input supply. Boost converter operation—use the MOSFET
as a low-side switch and connect DRAIN2 to the inductor and diode junction (Figure 8).
5
EN2
Active-High Enable Input for Converter 2. Drive EN2 low to shut down converter 2, drive EN2 high for normal
operation. Use EN2 in conjunction with EN1 for supply sequencing. Connect to VL for always-on operation.
6
FB2
Feedback Input for Converter 2. Connect FB2 to a resistive divider between converter 2’s output and SGND
to adjust the output voltage. To set the output voltage below 0.8V, connect FB2 to a resistive voltage-divider
from BYPASS to regulator 2’s output (Figure 5). See the Setting the Output Voltage section.
7
COMP2
Compensation Connection for Converter 2. See the Compensation section to compensate converter 2’s
control loop.
8
SYNC
9
N.C.
External Clock Synchronization Input. Connect SYNC to a 400kHz to 4400kHz clock to synchronize the
switching frequency with the system clock. Each converter frequency is one half the frequency applied to
SYNC. Connect SYNC to SGND when not used.
No Connection. Not internally connected.
_______________________________________________________________________________________
2.2MHz, Dual-Output Buck or Boost Converter
with Internal Power MOSFETs
PIN
NAME
FUNCTION
Oscillator Frequency Set Input. Connect a resistor from OSC to SGND (ROSC) to set the switching
frequency (see the Oscillator section). Set ROSC for equal to or lower oscillator frequency than the SYNC
input frequency when using external synchronization (0.2fSYNC < fOSC < 1.2fSYNC). ROSC is still required
when an external clock is connected to the SYNC input.
10
OSC
11
V+
Input Supply Voltage. V+ voltage range from 5.5V to 23V. Connect the V+ and VL together for 4.5V to
5.5V input operation. Bypass with a minimum 0.1µF ceramic capacitor to SGND.
12, 13
VL
Internal 5.2V Linear Regulator Output. Use VL to drive the high-side switch at BST1/VDD1 and
BST2/VDD2. Bypass VL with a 0.1µF capacitor to PGND and a 4.7µF ceramic capacitor to SGND.
14
BYPASS
2.0V Output. Bypass to SGND with a 0.22µF or greater ceramic capacitor.
15
COMP1
Compensation Connection for Converter 1 (See the Compensation Section)
16
FB1
Feedback Input for Converter 1. Connect FB1 to a resistive divider between converter 1’s output and SGND
to program the output voltage. To set the output voltage below 0.8V, connect FB1 to a resistive voltagedivider from BYPASS to regulator 1’s output (Figure 5). See the Setting the Output Voltage section.
17
EN1
Active-High Enable Input for Converter 1. Drive EN1 low to shut down converter 1, drive EN1 high for normal
operation. Use EN1 in conjunction with EN2 for supply sequencing. Connect to VL for always-on operation.
DRAIN1
Connection to the Converter 1 Internal MOSFET Drain.
Buck converter operation—use the MOSFET as a high-side switch and connect DRAIN1 to the input supply.
Boost converter operation—use the MOSFET as a low-side switch and connect DRAIN1 to the inductor
and diode junction.
18, 19
20
Buck Converter Operation—Bootstrap Flying-Capacitor Connection for Converter 1. Connect BST1/VDD1
to an external ceramic capacitor and diode according to the Standard Application Circuit (Figure 1).
BST1/VDD1
Boost Converter Operation—Driver Bypass Capacitor Connection. Connect a low-ESR 0.1µF ceramic
capacitor from BST1/VDD1 to PGND.
21
PGOOD1
Converter 1 Power-Good Output. Open-drain output goes low when converter 1’s output falls below
92.5% of its set regulation voltage. Use PGOOD1, PGOOD2, EN1, and EN2 to sequence the converters.
22
PGOOD2
Converter 2 Power-Good Output. Open-drain output goes low when converter 2’s output falls below
92.5% of its set regulation voltage.
23, 24
SOURCE1
Connection to the Converter 1 Internal MOSFET Source.
Buck converter operation—connect SOURCE1 to the switched side of the inductor as shown in Figure 1.
Boost converter operation—connect SOURCE1 to PGND.
25
SGND
Signal Ground. Connect SGND to the exposed pad. Connect SGND and PGND together at a single point.
26
PGND
Power Ground. Connect rectifier diode anode, input capacitor negative, output capacitor negative, and
VL bypass capacitor returns to PGND.
27, 28
SOURCE2
Connection to the Converter 2 Internal MOSFET Source.
Buck converter operation—connect SOURCE2 to the switched side of the inductor as shown in Figure 1.
Boost converter operation—connect SOURCE2 to PGND (Figure 8).
EP
SGND
Exposed Paddle. Connect to SGND. Solder EP to the SGND plane for better thermal performance.
_______________________________________________________________________________________
9
MAX5073
Pin Description (continued)
MAX5073
2.2MHz, Dual-Output Buck or Boost Converter
with Internal Power MOSFETs
PGOOD2
OUTPUT2
2.5V/1A
OUTPUT1
3.3V/2A
VL
CLOCK
OUT
28
27
26
25
24
23
22
SOURCE2 PGND SGND SOURCE1 PGOOD2
PGOOD1 21
1 CLKOUT
2 BST2/VDD2
INPUT
ON
OFF
SGND
EP
BST1/VDD1 20
3 DRAIN2
DRAIN1 19
4 DRAIN2
DRAIN1 18
5 EN2
MAX5073
EN1 17
6 FB2
INPUT
ON
OFF
FB1 16
COMP1 15
7 COMP2
SYNC N.C. OSC
8
9
10
VL
V+
11
VL
12
VL BYPASS
13 14
SGND
SYSTEM
CLOCK
VIN = 5.5V TO 23V
*CONNECT PGND AND SGND TOGETHER AT ONE POINT NEAR THE
RETURN TERMINALS OF THE V+ AND VL BYPASS CAPACITORS.
SGND
PGND
Figure 1. MAX5073 Dual Buck Regulator Application Circuit
Detailed Description
PWM Controller
The MAX5073 converter uses a pulse-width modulation
(PWM) voltage-mode control scheme for each out-ofphase controller. It is nonsynchronous rectification and
uses an external low-forward-drop Schottky diode for
rectification. The controller generates the clock signal
by dividing down the internal oscillator or the SYNC
input when driven by an external clock, so each controller’s switching frequency equals half the oscillator
frequency (fSW = fOSC / 2). An internal transconductance error amplifier produces an integrated error voltage at the COMP pin, providing high DC accuracy. The
voltage at COMP sets the duty cycle using a PWM
comparator and a ramp generator. At each rising edge
of the clock, converter 1’s high-side n-channel MOSFET
turns on and remains on until either the appropriate or
maximum duty cycle is reached, or the maximum current limit for the switch is detected. Converter 2 operates out-of-phase, so the second high-side MOSFET
turns on at each falling edge of the clock.
rent ramps up. During the second half of the switching
cycle, the high-side MOSFET turns off and forward biases
the Schottky rectifier. During this time, the SOURCE voltage is clamped to 0.4V (VD) below ground. The inductor
releases the stored energy as its current ramps down,
and provides current to the output. The bootstrap capacitor is also recharged from the inductance energy when
the MOSFET turns off. The circuit goes in discontinuous
conduction mode operation at light load, when the inductor current completely discharges before the next cycle
commences. Under overload conditions, when the inductor current exceeds the peak current limit of the respective switch, the high-side MOSFET turns off quickly and
waits until the next clock cycle.
In the case of boost operation, the MOSFET is a lowside switch (Figure 8). During each on-time, the inductor current ramps up. During the second half of the
switching cycle, the low-side switch turns off and forward biases the Schottky diode. During this time, the
DRAIN voltage is clamped to 0.4V (VD) above VOUT_
and the inductor provides energy to the output as well
as replenishes the output capacitor charge.
In the case of buck operation (Figure 1), during each
high-side MOSFET’s on-time, the associated inductor cur10
______________________________________________________________________________________
2.2MHz, Dual-Output Buck or Boost Converter
with Internal Power MOSFETs
ROSC =
25 × 10
fOSC
9
where fOSC is the internal oscillator frequency in hertz
and ROSC in ohms.
The two independent regulators in the MAX5073 switch
180° out-of-phase to reduce input filtering requirements, to reduce electromagnetic interference (EMI),
and to improve efficiency. This effectively lowers component cost and saves board space, making the
MAX5073 ideal for cost-sensitive applications.
With dual synchronized out-of-phase operation, the
MAX5073’s high-side MOSFETs turn on 180° out-ofphase. The instantaneous input current peaks of both
regulators do not overlap, resulting in reduced RMS ripple current and input voltage ripple. This reduces the
required input capacitor ripple current rating, allows for
fewer or less expensive capacitors, and reduces
shielding requirements for EMI. The out-of-phase waveforms in the Typical Operating Characteristics demonstrate synchronized 180° out-of-phase operation.
Synchronization (SYNC)/
Clock Output (CLKOUT)
The main oscillator can be synchronized to the system
clock by applying an external clock (fSYNC) at SYNC.
The fSYNC frequency must be twice the required operating frequency of an individual converter. Use a TTL
logic signal for the external clock with at least a 100ns
pulse width. ROSC is still required when using external
synchronization. Program the internal oscillator frequency so 0.2f SYNC < f OSC < 1.2f SYNC . The rising
edge of fSYNC synchronizes the turn-on edge of the
internal MOSFET (see Figure 3).
ROSC =
25 × 109
fOSC
where fOSC is the internal oscillator frequency in hertz
and ROSC in ohms, fOSC = 2 x fSW.
Two MAX5073s can be connected in the master-slave
configuration for four ripple-phase operation. The
MAX5073 provides a clock output (CLKOUT) that is 45°
phase-shifted with respect to the internal switch turn-on
edge. Feed the CLKOUT of the master to the SYNC
input of the slave. The effective input ripple switching
frequency shall be four times the individual converter’s
switching frequency. When driving the master converter using external clock at SYNC, set the clock duty
cycle to 50% for a 90° phase-shifted operation.
Input Voltage (V+)/Internal Linear
Regulator (VL)
All internal control circuitry operates from an internally
regulated nominal voltage of 5.2V (VL). At higher input
voltages (V+) of 5.5V to 23V, VL is regulated to 5.2V.
At 5.5V or below, the internal linear regulator operates
in dropout mode, where VL follows V+. Depending on
the load on VL, the dropout voltage can be high
enough to reduce VL below the undervoltage lockout
(UVLO) threshold.
For input voltages of less than 5.5V, connect V+ and VL
together. The load on VL is proportional to the switching frequency of converter 1 and converter 2. See the
Dropout Voltage vs. Switching Frequency graph in the
Typical Operating Characteristics. For input voltage
ranges higher than 5.5V, use the internal regulator.
Bypass V+ to SGND with a low-ESR, 0.1µF or greater
ceramic capacitor placed close to the MAX5073. Current
spikes from VL may disturb internal circuitry powered by
VL. Bypass VL with a low-ESR, ceramic 0.1µF capacitor
to PGND and 4.7µF capacitor to SGND.
Undervoltage Lockout/Soft-Start
The MAX5073 includes an undervoltage lockout with
hysteresis and a power-on-reset circuit for converter
turn-on and monotonic rise of the output voltage. The
rising UVLO threshold is internally set to 4.3V with a
175mV hysteresis. Hysteresis at UVLO eliminates “chattering” during startup. When VL drops below UVLO, the
internal switches are turned off.
Digital soft-start is provided internally to reduce input
surge currents and glitches at the input during turn-on.
When UVLO is cleared and EN_ is high, digital softstart slowly ramps up the internal reference voltage in
64 steps. The total soft-start period is 2048 switching
cycles of the internal oscillator.
To calculate the soft-start period, use the following
equation:
t SS =
2048
fOSC
where fOSC is the internal oscillator frequency in hertz,
which is twice the switching frequency of each converter.
______________________________________________________________________________________
11
MAX5073
Internal Oscillator/Out-of-Phase Operation
The internal oscillator generates the 180° out-of-phase
clock signal required by each regulator. The internal
oscillator frequency is programmable from 400kHz to
4.4MHz using a single 1% resistor at ROSC. Use the following equation to calculate ROSC:
MAX5073
2.2MHz, Dual-Output Buck or Boost Converter
with Internal Power MOSFETs
V+
LDO
MAX5073
CONVERTER 1
VL
VL
DEAD-TIME
CONTROL
OSCILLATOR
BST1/VDD1
FREQUENCY
FOLDBACK
DRAIN1
BYPASS
Q
N
Q
SOURCE1
Q
PGOOD1
fSW / 4
VREF
VREF
DIGITAL
SOFT-START
EN1
FB1
COMP1
0.5VREF
0.92VREF
SYNC
CKO
OSC
MAIN
OSCILLATOR
VL
OSCILLATOR
PGOOD2
BST2/VDD2
DRAIN2
VDD2
CONVERTER 2
EN2
SOURCE2
FB2
COMP2
Figure 2. Functional Diagram
12
______________________________________________________________________________________
2.2MHz, Dual-Output Buck or Boost Converter
with Internal Power MOSFETs
MAX5073
VIN
CIN
V+
V+
OUTPUT2
DRAIN2
DRAIN1
SOURCE2
DUTY CYCLE = 50% CLKIN
SYNC
OUTPUT1
SOURCE1
OUTPUT4
DRAIN2
DRAIN1
SOURCE2
CLKOUT
OUTPUT3
SOURCE1
SYNC
MASTER
SLAVE
SYNC
CLKOUT
(MASTER)
CLKOUT
(SLAVE)
SOURCE1
(MASTER)
CLKOUTPHASE
SYNCPHASE
SOURCE2
(MASTER)
SOURCE1
(SLAVE)
SOURCE2
(SLAVE)
CIN (RIPPLE)
Figure 3. Synchronized Controllers
______________________________________________________________________________________
13
MAX5073
2.2MHz, Dual-Output Buck or Boost Converter
with Internal Power MOSFETs
Enable
Current Limit
The MAX5073 dual converter provides separate enable
inputs EN1 and EN2 to individually control or sequence
the output voltages. These active-high enable inputs are
TTL compatible. Pulling EN_ high ramps up the reference
slowly, which provides soft-start at the outputs. Forcing
the EN_ low externally disables the individual output and
generates a PGOOD_ signal. Use EN1, EN2, and
PGOOD1 for sequencing (see Figure 4). Connect
PGOOD1 to EN2 to make sure converter 1’s output is
within regulation before converter 2 starts. Add an RC
network from VL to EN1 and EN2 to delay the individual
converter. A larger RC time constant means a more
delayed output. Sequencing reduces input inrush current
and possible chattering. Connect the EN_ to VL for
always-on operation.
The internal switch current of each converter is sensed
using an internal current mirror. Converter 1 and converter 2 have 2A and 1A internal switches. When the
peak switch current crosses the current-limit threshold
of 3A (typ) and 1.8A (typ) for converter 1 and converter
2, respectively, the on cycle is terminated immediately
and the inductor is allowed to discharge. The next
cycle resumes at the next clock pulse.
In deep overload or short-circuit conditions when the
FB voltage drops below 0.4V, the switching frequency
is reduced to 1/4 x fSW to provide sufficient time for the
inductor to discharge. During overload conditions, if the
voltage across the inductor is not high enough to allow
for the inductor current to properly discharge, current
runaway may occur. Current runaway can destroy the
device in spite of internal thermal-overload protection.
Reducing the switching frequency during overload conditions prevents current runaway.
PGOOD_
Converter 1 and converter 2 includes a power-good flag,
PGOOD1 and PGOOD2, respectively. Since PGOOD is
an open-drain output and can sink 3mA while providing
the TTL logic-low signal, pull PGOOD to a logic voltage
to provide a logic-level output. PGOOD goes low when
converter 1’s output drops to 92.5% of its nominal regulated voltage. Connect PGOOD to SGND or leave unconnected if not used.
Thermal-Overload Protection
During continuous short circuit or overload at the output,
the power dissipation in the IC can exceed its limit.
Internal thermal shutdown is provided to avoid irreversible
damage to the device. When the die temperature or junction temperature exceeds +150°C, an on-chip thermal
sensor shuts down the device, forcing the internal switches to turn off, allowing the IC to cool. The thermal sensor
turns the part on again after the junction temperature
cools by +30°C. During thermal shutdown, both regulators shut down, PGOOD_ go low, and soft-start resets.
VIN
VIN
VL
OUTPUT2
VL
VL
DRAIN2
V+
DRAIN1
SOURCE2
SOURCE1
OUTPUT1
OUTPUT2
VL
DRAIN2
V+
DRAIN1
SOURCE2
SOURCE1
MAX5073
FB2
OUTPUT1
MAX5073
FB1
FB2
FB1
EN2
EN1
R2
VL
EN2
EN1
VL
PGOOD1
SEQUENCING—OUTPUT 2 DELAYED WITH RESPECT TO OUTPUT 1.
R1
VL
C2
R1/C1 AND R2/C2 ARE SIZED FOR REQUIRED SEQUENCING.
Figure 4. Power-Supply Sequencing Configurations
14
______________________________________________________________________________________
VL
C1
2.2MHz, Dual-Output Buck or Boost Converter
with Internal Power MOSFETs
Setting the Switching Frequency
The controller generates the clock signal by dividing
down the internal oscillator or the SYNC input signal when
driven by an external oscillator. The switching frequency
equals half the oscillator frequency (fSW = fOSC / 2). The
internal oscillator frequency is set by a resistor (ROSC)
connected from OSC to SGND. The relationship
between fSW and ROSC is:
ROSC =
12.5 × 109
fSW
where fSW and fOSC are in hertz, and ROSC is in ohms.
For example, a 1250kHz switching frequency is set with
ROSC = 10kΩ. Higher frequencies allow designs with
lower inductor values and less output capacitance.
Consequently, peak currents and I2R losses are lower
at higher switching frequencies, but core losses, gatecharge currents, and switching losses increase.
A rising clock edge on SYNC is interpreted as a synchronization input. If the SYNC signal is lost, the internal oscillator takes control of the switching rate,
returning the switching frequency to that set by ROSC.
This maintains output regulation even with intermittent
SYNC signals. When an external synchronization signal
is used, ROSC should be set for the oscillator frequency
to be lower than or equal to the SYNC rate (fSYNC).
where VDROP1 is the total parasitic voltage drops in the
inductor discharge path, which includes the forward
voltage drop (VD) of the rectifier, the series resistance of
the inductor, and the PC board resistance. VDROP2 is
the total resistance in the charging path, which includes
the on-resistance of the high-side switch, the series
resistance of the inductor, and the PC board resistance.
Setting the Output Voltage
For 0.8V or greater output voltages, connect a voltagedivider from OUT_ to FB_ to SGND (Figure 5). Select
RB (FB_ to SGND resistor) to between 1kΩ and 10kΩ.
Calculate RA (OUT_ to FB_ resistor) with the following
equation:
⎡⎛ V
⎞ ⎤
RA = RB ⎢⎜ OUT ⎟ − 1⎥
⎢⎣⎝ VFB ⎠ ⎥⎦
where VFB_ = 0.8V (see the Electrical Characteristics
table) and VOUT_ can range from VFB_ to 28V (boost
operation).
For output voltages below 0.8V, set the MAX5073 output voltage by connecting a voltage-divider from the
output to FB_ to BYPASS (Figure 5). Select RC (FB to
BYPASS resistor) higher than a 50kΩ range. Calculate
RA with the following equation:
⎡ V −V
⎤
OUT ⎥
RA = RC ⎢ FB
⎢⎣ VBYPASS − VFB ⎥⎦
Buck Converter
Effective Input Voltage Range
Although the MAX5073 converters can operate from
input supplies ranging from 5.5V to 23V, the input voltage range can be effectively limited by the MAX5073
duty-cycle limitations for a given output voltage. The
maximum input voltage is limited by the minimum ontime (tON(MIN)):
VIN(MAX) ≤
where VFB = 0.8V, VBYPASS = 2V (see the Electrical
Characteristics table), and VOUT_ can range from 0V
to VFB_.
LX_
VOUT
t ON(MIN) × fSW
BYPASS
RA
RC
FB_
where tON(MIN) is 100ns. The minimum input voltage is
limited by the maximum duty cycle (DMAX = 0.88):
RB
MAX5073
+ VDROP1 ⎤
⎡V
VIN(MIN) = ⎢ OUT
⎥ + VDROP2 − VDROP1
0.88
⎣
⎦
FB_
RA
MAX5073
LX_
VOUT_ > 0.8V
VOUT_ < 0.8V
Figure 5. Adjustable Output Voltage
______________________________________________________________________________________
15
MAX5073
Applications Information
MAX5073
2.2MHz, Dual-Output Buck or Boost Converter
with Internal Power MOSFETs
Inductor Selection
Three key inductor parameters must be specified for
operation with the MAX5073: inductance value (L), peak
inductor current (IL), and inductor saturation current
(ISAT). The minimum required inductance is a function of
operating frequency, input-to-output voltage differential
and the peak-to-peak inductor current (∆IL). Higher ∆IL
allows for a lower inductor value while a lower ∆I L
requires a higher inductor value. A lower inductor value
minimizes size and cost, improves large-signal transient
response, but reduces efficiency due to higher peak currents and higher peak-to-peak output ripple voltage for
the same output capacitor. On the other hand, higher
inductance increases efficiency by reducing the ripple
current. However, resistive losses due to extra wire turns
can exceed the benefit gained from lower ripple current
levels, especially when the inductance is increased without also allowing for larger inductor dimensions. A good
compromise is to choose ∆IL equal to 30% of the full load
current. To calculate the inductance use the following
equation:
L=
ESRIN =
VIN × fSW × ∆IL
Input Capacitors
The discontinuous input current waveform of the buck
converter causes large ripple currents at the input. The
switching frequency, peak inductor current, and the
allowable peak-to-peak voltage ripple dictate the input
capacitance requirement. Increasing the switching frequency or the inductor value lowers the peak to average current ratio, yielding a lower input capacitance
requirement. Note that two converters of MAX5073 run
180° out-of-phase, thereby effectively doubling the
switching frequency at the input.
∆VESR
∆IL ⎞
⎛
⎜IOUT +
⎟
⎝
2 ⎠
where
VOUT (VIN − VOUT )
where VIN and VOUT are typical values (so that efficiency is optimum for typical conditions). The switching frequency is set by ROSC (see the Setting the Switching
Frequency section). The peak-to-peak inductor current,
which reflects the peak-to-peak output ripple, is worse
at the maximum input voltage. See the Output Capacitor
Selection section to verify that the worst-case output ripple is acceptable. The inductor saturating current is also
important to avoid runaway current during output overload and continuous short circuit. Select the ISAT to be
higher than the maximum peak current limits of 4.5A
and 2.2A for converter 1 and converter 2.
16
The input ripple waveform would be unsymmetrical due
to the difference in load current and duty cycle
between converter 1 and converter 2. The input ripple
is comprised of ∆V Q (caused by the capacitor discharge) and ∆VESR (caused by the ESR of the capacitor). A higher load converter dictates the ESR
requirement, while the capacitance requirement is a
function of the loading mismatch between the two converters. The worst-case mismatch is when one converter
is at full load while the other is at no load or in shutdown.
Use low-ESR ceramic capacitors with high ripple-current capability at the input. Assume the contribution
from the ESR and capacitor discharge equal to 50%.
Calculate the input capacitance and ESR required for a
specified ripple using the following equations:
∆IL =
(VIN − VOUT )
× VOUT
VIN × fSW × L
and
CIN =
IOUT × D(1 − D)
∆VQ × fSW
where
V
D = OUT
VIN
where IOUT is the maximum output current from either
converter 1 or converter 2, and D is the duty cycle for
that converter. fSW is the frequency of each individual
converter. For example, at VIN = 12V, VOUT = 3.3V at
I OUT = 2A, and with L = 3.3µH, the ESR and input
capacitance are calculated for a peak-to-peak input
ripple of 100mV or less, yielding an ESR and capacitance value of 20mΩ and 6.8µF for 1.25MHz frequency.
Use a 100µF capacitor at low input voltages to avoid
possible undershoot below the undervoltage lockout
threshold during power-on and transient loading.
______________________________________________________________________________________
2.2MHz, Dual-Output Buck or Boost Converter
with Internal Power MOSFETs
ESROUT =
COUT =
∆VESR
∆IL
∆IL
8 × ∆VQ × fSW
where
∆VO _ RIPPLE ≅ ∆VESR + ∆VQ
where ∆IL is the peak-to-peak inductor current as calculated above and fSW is the individual converter’s
switching frequency.
The allowable deviation of the output voltage during
fast transient loads also determines the output capacitance and its ESR. The output capacitor supplies the
step load current until the controller responds with a
greater duty cycle. The response time (t RESPONSE)
depends on the closed-loop bandwidth of the converter. The high switching frequency of MAX5073 allows for
higher closed-loop bandwidth, reducing t RESPONSE
and the output capacitance requirement. The resistive
drop across the output capacitor ESR and the capacitor discharge causes a voltage droop during a step
load. Use a combination of low-ESR tantalum and
ceramic capacitors for better transient load and
ripple/noise performance. Keep the maximum output voltage deviation above the tolerable limits of the electronics
being powered. When using a ceramic capacitor,
assume 80% and 20% contribution from the output
capacitance discharge and the ESR drop, respectively.
Use the following equations to calculate the required ESR
and capacitance value:
ESROUT =
∆VESR
ISTEP
I
× t RESPONSE
COUT = STEP
∆VQ
where I STEP is the load step and t RESPONSE is the
response time of the controller. Controller response
time depends on the control-loop bandwidth.
Boost Converter
The MAX5073 can be configured for step-up conversion
since the internal MOSFET can be used as a low-side
switch. Use the following equations to calculate the
inductor (LMIN), input capacitor (CIN), and output capacitor (COUT) when using the converter in boost operation.
Inductor
Choose the minimum inductor value so the converter
remains in continuous mode operation at minimum output current (IOMIN).
LMIN =
V2IN × D × η
2 × fSW × VO × IOMIN
where
V + VD − VIN
D= O
VO + VD − VDS
and IOMIN = 0.25 x IO
The VD is the forward voltage drop of the external Schottky
diode, D is the duty cycle, and VDS is the voltage drop
across the internal switch. Select the inductor with low DC
resistance and with a saturation current (ISAT) rating higher than the peak switch current limit of 4.5A and 2.2A of
converter 1 and converter 2, respectively.
______________________________________________________________________________________
17
MAX5073
Output Capacitors
The allowable output ripple voltage and the maximum
deviation of the output voltage during step load currents
determines the output capacitance and its ESR.
The output ripple is comprised of ∆VQ (caused by the
capacitor discharge) and ∆VESR (caused by the ESR
of the capacitor). Use low-ESR ceramic or aluminum
electrolytic capacitors at the output. For aluminum
electrolytic capacitors, the entire output ripple is contributed by ∆VESR. Use the ESROUT equation to calculate the ESR requirement and choose the capacitor
accordingly. If using ceramic capacitors, assume the
contribution to the output ripple voltage from the ESR
and the capacitor discharge are equal. Calculate the
output capacitance and ESR required for a specified ripple using the following equations:
MAX5073
2.2MHz, Dual-Output Buck or Boost Converter
with Internal Power MOSFETs
Input Capacitor
The input current for the boost converter is continuous
and the RMS ripple current at the input is low. Calculate
the capacitor value and ESR of the input capacitor
using the following equations.
CIN =
∆IL × D
4 × fSW × ∆VQ
ESR =
the following equations to calculate the RMS current,
DC loss, and switching loss of each converter. The
MAX5073 device is available in a thermally enhanced
package and can dissipate up to 2.7W at +70°C ambient
temperature. The total power dissipation in the package
must be limited so the junction temperature does
not exceed its absolute maximum rating of +150°C at
maximum ambient temperature.
For the buck converter:
∆VESR
∆IL
D
IRMS = (I2DC +I2PK +(IDC × IPK )) × MAX
3
where
∆IL =
(VIN − VDS )
PDC = I2RMS × RDS(ON)MAX
× D
L × fSW
where VDS is the total voltage drop across the internal
MOSFET plus the voltage drop across the inductor
ESR. ∆IL is the peak-to-peak inductor ripple current as
calculated above. ∆VQ is the portion of input ripple due
to the capacitor discharge and ∆VESR is the contribution due to ESR of the capacitor.
Output Capacitor
For the boost converter, the output capacitor supplies
the load current when the main switch is ON. The
required output capacitance is high, especially at higher duty cycles. Also, the output capacitor ESR needs to
be low enough to minimize the voltage drop due to the
ESR while supporting the load current. Use the following equation to calculate the output capacitor for a
specified output ripple tolerance.
∆VESR
ESR =
IO
I × DMAX
COUT = O
∆VQ × fSW
IO is the load current, ∆VQ is the portion of the ripple
due to the capacitor discharge and ∆VESR is the contribution due to the ESR of the capacitor. DMAX is the
maximum duty cycle at minimum input voltage.
Power Dissipation
The MAX5073 includes a high-frequency, low RDS_ON
switching MOSFET. At +85°C, the RDS_ON of the internal switch for converter 1 and converter 2 are 290mΩ
and 630mΩ, respectively. The DC loss is a function of
the RMS current in the switch while the switching loss is
a function of switching frequency and input voltage. Use
18
where
IDC = IO −
∆IL
2
IPK = IO +
∆IL
2
See the Electrical Characteristics table for the
RDS(ON)MAX value.
V
× I × (t R + t F ) × fSW
PSW = INMAX O
4
For the boost converter:
D
IRMS = (I2DC +I2PK +(IDC × IPK )) × MAX
3
V ×I
IIN = O O
VIN × η
∆IL =
(VIN − VDS ) × D
L × fSW
IDC = IIN −
∆IL
2
IPK = IIN +
∆IL
2
______________________________________________________________________________________
2.2MHz, Dual-Output Buck or Boost Converter
with Internal Power MOSFETs
PDC = I RMS × RDS(ON)MAX
where VDS is the drop across the internal MOSFET. See
the Electrical Characteristics for the RDS(ON)MAX value.
V × I × (tR + tF ) × fSW
PSW = O IN
4
where tR and tF are rise and fall times of the internal
MOSFET. The tR and tF are typically 20ns, and can be
measured in the actual application.
The supply current in the MAX5073 is dependent on
the switching frequency. See the Typical Operating
Characteristics to find the supply current of the
MAX5073 at a given operating frequency. The power
dissipation (PS) in the device due to supply current (IS)
is calculated using following equation.
PS = VINMAX × ISUPPLY
The total power dissipation PT in the device is:
PT = PDC1 + PDC2 + PSW1 + PSW2 + PS
where PDC1 and PDC2 are DC losses in converter 1 and
converter 2, respectively. PSW1 and PSW2 are switching
losses in converter 1 and converter 2.
Calculate the temperature rise of the die using the
following equation:
TJ = TC + (PT x θJC)
where, θJC is the junction-to-case thermal impedance of
the package equal to +2°C/W. Solder the exposed pad of
the package to a large copper area to minimize the caseto-ambient thermal impedance. Measure the temperature
of the copper area near the device at a worst-case condition of power dissipation and use +2°C/W as θJC thermal
impedance. The case-to-ambient thermal impedance
(θC-A) is dependent on how well the heat is transferred
from the PC board to the ambient. Use a large copper
area to keep the PC board temperature low. The θC-A is
usually in the +20°C/W to +40°C/W range .
Compensation
The MAX5073 provides an internal transconductance
amplifier with its inverting input and its output available
to the user for external frequency compensation. The
flexibility of external compensation for each converter
offers wide selection of output filtering components,
especially the output capacitor. For cost-sensitive
applications, use high-ESR aluminum electrolytic
capacitors; for component size-sensitive applications,
use low-ESR tantalum or ceramic capacitors at the out-
put. The high switching frequency of MAX5073 allows
use of ceramic capacitors at the output.
Choose all the passive power components that meet
the output ripple, component size, and component cost
requirements. Choose the small-signal components for
the error amplifier to achieve the desired closed-loop
bandwidth and phase margin. Use a simple pole-zero
pair (Type II) compensation if the output capacitor ESR
zero frequency is below the unity-gain crossover frequency (fC). Type III compensation is necessary when
the ESR zero frequency is higher than fC or when compensating for a continuous mode boost converter that
has a right-half-plane zero.
Use the following procedure 1 to calculate the compensation network components when fZERO,ESR < fC.
Buck Converter Compensation
Procedure 1 (See Figure 6)
1) Calculate the fZERO,ESR and LC double pole:
fZERO, ESR =
fLC =
1
2π × ESR × COUT
1
2π × LOUT × COUT
2) Calculate the unity-gain crossover frequency as:
f
fC = SW
20
If the fZERO,ESR is lower than fC and close to fLC, use a
Type II compensation network where RFCF provides a
midband zero fmid,zero, and RFCCF provides a high-frequency pole.
3) Calculate modulator gain GM at the crossover frequency.
VOUT
R1
-
COMP
gM
R2
VREF
+
RF
CF
CCF
Figure 6. Type II Compensation Network
______________________________________________________________________________________
19
MAX5073
2
MAX5073
2.2MHz, Dual-Output Buck or Boost Converter
with Internal Power MOSFETs
GM =
VIN
VOSC
×
ESR
ESR + (2π × fC × LOUT )
×
0.8
VOUT
VOUT
CCF
where VOSC is a peak-to-peak ramp amplitude equal
to 1V.
RI
The transconductance error amplifier gain is:
CI
CF
RF
R1
-
GE / A = gm × RF
COMP
gM
R2
+
VREF
The total loop gain at fC should be equal to 1
GM × GE / A = 1
Figure 7. Type III Compensation Network
or
RF =
VOSC (ESR + 2π × fC × L OUT )VOUT
0.8 × VIN × gm × ESR
where:
CF =
4) Place a zero at or below the LC double pole:
CF =
1
2π × RF × fLC
and RF ≥ 10kΩ.
4) Calculate CI for a target unity crossover frequency, fC:
5) Place a high-frequency pole at fP = 0.5 x fSW.
CI =
Procedure 2 (see Figure 7)
If the output capacitor used is a low-ESR ceramic type,
the ESR frequency is usually far away from the targeted
unity crossover frequency (fC). In this case, Type III compensation is recommended. Type III compensation provides two-pole zero pairs. The locations of the zero and
poles should be such that the phase margin peaks at fC.
fC
f
= P =5
fC
The fZ
is a good number to get about 60°
phase margin at fC. However, it is important to place
the two zeros at or below the double pole to avoid the
conditional stability issue.
1) Select a crossover frequency:
fC ≤
fSW
VIN × RF
(fP1 =
5) Place a pole
RI =
1
2π × R F × C F
1
)
2π × RI × CI
at fZERO,ESR.
1
2π × fZERO, ESR × CI
6) Place a second zero, f Z2 , at 0.2 x f C or at f LC ,
whichever is lower.
R1 =
1
2π × fZ2 × CI
(fP2 =
7) Place a second pole
the switching frequency.
CCF =
3) Place a zero
20
2π × fC × LOUT × COUT × VOSC
− RI
20
2) Calculate the LC double-pole frequency, fLC:
1
fLC =
2π × LOUT × COUT
fZ =
1
2π × 0.75 × fLC × RF
1
)
2π × RF × CCF
CF
(2π × 0.5 × fSW × RF × CF ) − 1
at 0.75 × fLC
______________________________________________________________________________________
at 1/2
2.2MHz, Dual-Output Buck or Boost Converter
with Internal Power MOSFETs
PGOOD2
OUTPUT1
PGOOD1
PGND
SGND
OUTPUT1
3.3V/2A
VL
CLOCK
OUT
OUTPUT2
12V/0.2A
28
27
26
25
24
23
22
SOURCE2 PGND SGND SOURCE1 PGOOD2
PGOOD1 21
1 CLKOUT
SGND
2 BST2/VDD2
BST1/VDD1 20
EP
3 DRAIN2
5 EN2
DRAIN1 18
MAX5073
ON
OFF
EN1 17
6 FB2
FB1 16
COMP1 15
7 COMP2
SYNC N.C. OSC
8
9
10
INPUT
DRAIN1 19
4 DRAIN2
ON
OFF
VL
V+
11
VL
12
VL BYPASS
13 14
SYSTEM
CLOCK
INPUT
*CONNECT PGND AND SGND TOGETHER AT ONE POINT NEAR
THE RETURN TERMINALS OF THE V+ AND VL BYPASS CAPACITORS.
Figure 8. Buck-Boost Application
Boost Converter Compensation
The boost converter compensation gets complicated
due to the presence of a right-half-plane zero fZERO,RHP.
The right-half-plane zero causes a drop in-phase while
adding positive (+1) slope to the gain curve. It is important to drop the gain significantly below unity before the
RHP frequency. Use the following procedure to calculate the compensation components.
1) Calculate the LC double-pole frequency, FLC, and
the right half plane zero frequency.
fLC =
where:
D =1−
VOUT
VOUT
R(MIN) =
IOUT(MAX)
Target the unity-gain crossover frequency for:
fC ≤
1− D
2π × LOUTCOUT
2
fZERO, RHP =
(1 − D) R(MIN)
VIN
(fZ1 =
2) Place a zero
2π × LOUT
CF =
fZERO, RHP
5
1
2π × R F × C F
)
at 0.75 x fLC.
1
2π × 0.75 × fLC × RF
where RF ≥ 10kΩ.
______________________________________________________________________________________
21
MAX5073
OUTPUT2
MAX5073
2.2MHz, Dual-Output Buck or Boost Converter
with Internal Power MOSFETs
3) Calculate CI for a target crossover frequency, fC:
2
VOSC ⎡⎢(1 − D) + ω C2 LOCO ⎤⎥
⎣
⎦
CI =
ω CRF VIN
2) Isolate the power components and high-current
path from the sensitive analog circuitry.
3) Keep the high-current paths short, especially at the
ground terminals. This practice is essential for stable, jitter-free operation.
where ωC = 2π fC
(fP1 =
4) Place a pole
RI =
1
)
2π × RI × CI at fZERO,RHP.
1
5) Place the second zero
6) Place the second pole
the switching frequency.
)
2π × R1 × CI
2π × fLC × CI
(fP2 =
CCF =
1
1
4) Connect SGND and PGND together close to the IC
at the ground terminals of VL and V+ bypass capacitors. Do not connect them together anywhere else.
5) Keep the power traces and load connections short.
This practice is essential for high efficiency. Use
thick copper PC boards (2oz vs. 1oz) to enhance
full-load efficiency.
2π × fZERO, RHP × CI
(fZ2 =
R1 =
on the top and bottom side of the PC board. Do not
make a direct connection from the exposed pad
copper plane to SGND (pin 25) underneath the IC.
at fLC.
− RI
1
2π × RF × CCF at 1/2
6) Ensure that the feedback connection to COUT is
short and direct.
7) Route high-speed switching nodes (BST_/VDD_,
SOURCE_) away from the sensitive analog areas
(BYPASS, COMP_, and FB_). Use the internal PC
board layer for SGND as EMI shields to keep radiated noise away from the IC, feedback dividers, and
analog bypass capacitors.
CF
(2π × 0.5 × fSW × RF × CF) − 1
Improving Noise Immunity
In applications where the MAX5073 are subject to noisy
environments, adjust the controller’s compensation to
improve the system’s noise immunity. In particular,
high-frequency noise coupled into the feedback loop
causes jittery duty cycles. One solution is to lower the
crossover frequency (see the Compensation section).
PC Board Layout Guidelines
Careful PC board layout is critical to achieve low
switching losses and clean, stable operation. This is
especially true for dual converters where one channel
can affect the other. Refer to the MAX5073 EV kit data
sheet for a specific layout example. Use a multilayer
board whenever possible for better noise immunity.
Follow these guidelines for good PC board layout:
1) For SGND, use a large copper plane under the IC
and solder it to the exposed paddle. To effectively
use this copper area as a heat exchanger between
the PC board and ambient, expose this copper area
22
______________________________________________________________________________________
2.2MHz, Dual-Output Buck or Boost Converter
with Internal Power MOSFETs
2) Group the gate-drive components (bootstrap
diodes and capacitors, and VL bypass capacitor)
together near the controller IC.
3) Make the DC-DC controller ground connections as
follows:
Ordering Information (continued)
PIN-PACKAGE
PKG
CODE
PART
TEMP RANGE
MAX5073ATI
-40°C to +125°C
28 Thin QFN-EP*
T2855-6
(5mm x 5mm)
MAX5073ATI+ -40°C to +125°C
28 Thin QFN-EP*
T2855-6
(5mm x 5mm)
a) Create a small-signal ground plane underneath
the IC.
b) Connect this plane to SGND and use this plane
for the ground connection for the reference
(BYPASS), enable, compensation components,
feedback dividers, and OSC resistor.
c) Connect SGND and PGND together near the
input bypass capacitors and the IC (this is the
only connection between SGND and PGND).
Chip Information
TRANSISTOR COUNT: 5994
PROCESS: BiCMOS
*EP = Exposed pad.
+Denotes lead-free package.
______________________________________________________________________________________
23
MAX5073
Layout Procedure
1) Place the power components first, with ground terminals adjacent (inductor, CIN_, and COUT_). Make
all these connections on the top layer with wide,
copper-filled areas (2oz copper recommended).
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information
go to www.maxim-ic.com/packages.)
QFN THIN.EPS
MAX5073
2.2MHz, Dual-Output Buck or Boost Converter
with Internal Power MOSFETs
24
______________________________________________________________________________________
2.2MHz, Dual-Output Buck or Boost Converter
with Internal Power MOSFETs
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 25
© 2006 Maxim Integrated Products
Printed USA
is a registered trademark of Maxim Integrated Products, Inc.
MAX5073
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information
go to www.maxim-ic.com/packages.)
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