TPA3101D2

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TPA3101D2

QFN

HTQFP

SLOS473B – DECEMBER 2005 – REVISED SEPTEMBER 2007

10-W STEREO CLASS-D AUDIO POWER AMPLIFIER

1

FEATURES

10-W/ch into an 8-

Load From a 13-V Supply

9.2-W/ch into an 8-

Load From a 12-V Supply

Operates from 10 V to 26 V

87% Efficient Class-D Operation Eliminates

Need for Heat Sinks

Four Selectable, Fixed Gain Settings

Differential Inputs

Thermal and Short-Circuit Protection With

Auto Recovery Feature

Clock Output for Synchronization With

Multiple Class-D Devices

Surface Mount 7 mm

×

7 mm, 48-pin QFN

Package

Surface Mount 7 mm

×

7 mm, 48-pin HTQFP

Package

APPLICATIONS

Televisions

DESCRIPTION

The TPA3101D2 is a 10-W (per channel) efficient,

Class-D audio power amplifier for driving bridged-tied stereo speakers. The TPA3101D2 can drive stereo speakers as low as 4 Ω . The high efficiency of the

TPA3101D2, 87%, eliminates the need for an external heat sink when playing music.

The gain of the amplifier is controlled by two gain select pins. The gain selections are 20, 26, 32,

36 dB.

The outputs are fully protected against shorts to

GND, V

CC

, and output-to-output shorts with an auto recovery feature and monitor output.

TV Audio

Processor

Shutdown

Control

Mute Control

Gain Select

Sync Control

Fault Flag

10 V to 26 V

Simplified Application Circuit

RINP

RINN

LINN

TPA3101D2

BSRN

ROUTN

ROUTP

BSRP

LINP

SHUTDOWN

MUTE

VCLAMPR

PGNDR

VREG

VBYP

ROSC

GAIN0

GAIN1

MSTR/SLV

SYNC

FAULT

PVCCR

PVCCL

AVCC

AGND

BSLN

LOUTN

LOUTP

BSLP

VCLAMPL

PGNDL

100 kW

10 nF

1

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

Copyright © 2005–2007, Texas Instruments Incorporated

TPA3101D2 www.ti.com

SLOS473B – DECEMBER 2005 – REVISED SEPTEMBER 2007

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.

ABSOLUTE MAXIMUM RATINGS

over operating free-air temperature range (unless otherwise noted)

(1)

V

V

T

T

T

R

CC

I

A

J stg

(Load)

Supply voltage AVCC, PVCC

SHUTDOWN, MUTE

Input voltage

GAIN0, GAIN1, RINN, RINP, LINN, LINP, MSTR/SLV,

SYNC

Continuous total power dissipation

Operating free-air temperature range

Operating junction temperature range

(2)

Storage temperature range

Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds

Load Resistance

Electrostatic discharge

Human body model

(3)

(all pins)

Machine model

(4)

(all pins)

Charged-device model

(5)

(all pins)

UNIT

–0.3 V to 30 V

–0.3 V to V

CC

+ 0.3 V

–0.3 V to VREG + 0.5 V

See Dissipation Rating Table

–40

°

C to 85

°

C

–40

°

C to 150

°

C

–65

°

C to 150

°

C

260

°

C

3.2

Ω Minimum

±2 kV

±200 V

±500 V

(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operations of the device at these or any other conditions beyond those indicated under recommended operating

conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) The TPA3101D2 incorporates an exposed thermal pad on the underside of the chip. This acts as a heatsink, and it must be connected to a thermally dissipating plane for proper power dissipation. Failure to do so may result in the device going into thermal protection shutdown. See TI Technical Briefs SCBA017D and SLUA271 for more information about using the QFN thermal pad. See TI Technical

Briefs SLMA002 for more information about using the HTQFP thermal pad.

(3) In accordance with JEDEC Standard 22, Test Method A114-B.

(4) In accordance with JEDEC Standard 22, Test Method A115-A

(5) In accordance with JEDEC Standard 22, Test Method C101-A

TYPICAL DISSIPATION RATINGS

PACKAGE

48-pin RGZ (QFN)

48-pin PHP (HTQFP)

T

A

≤ 25

°

C

4.39 W

4.82 W

DERATING FACTOR

35.1 mW/

°

C

(1)

38.6 mW/

°

C

(2)

T

A

= 70

°

C

2.81 W

3.09 W

T

A

= 85

°

C

2.28 W

2.51 W

(1) This data was taken using 1 oz trace and copper pad that is soldered directly to a JEDEC standard high-k PCB. The thermal pad must be soldered to a thermal land on the printed-circuit board. See TI Technical Briefs SCBA017D and SLUA271 for more information about using the QFN thermal pad.

(2) This data was taken using 1 oz trace and copper pad that is soldered directly to a JEDEC standard high-k PCB. The thermal pad must be soldered to a thermal land on the printed-circuit board. See TI Technical Briefs SLMA002 for more information about using the

HTQFP thermal pad.

RECOMMENDED OPERATING CONDITIONS

over operating free-air temperature range (unless otherwise noted)

V

CC

V

IH

V

IL

I

IH

PARAMETER

Supply voltage

High-level input voltage

Low-level input voltage

High-level input current

TEST CONDITIONS

PVCC, AVCC

SHUTDOWN, MUTE, GAIN0, GAIN1, MSTR/SLV,

SYNC

SHUTDOWN, MUTE, GAIN0, GAIN1, MSTR/SLV,

SYNC

SHUTDOWN, V

I

= V

CC

, V

CC

= 24 V

MUTE, V

I

= V

CC

, V

CC

= 24 V

GAIN0, GAIN1, MSTR/SLV, SYNC, V

I

V

CC

= 24 V

= VREG,

MIN

10

2

MAX UNIT

26 V

V

0.8

125

75

2

V

µA

2

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TPA3101D2

Copyright © 2005–2007, Texas Instruments Incorporated

TPA3101D2 www.ti.com

SLOS473B – DECEMBER 2005 – REVISED SEPTEMBER 2007

RECOMMENDED OPERATING CONDITIONS (continued)

over operating free-air temperature range (unless otherwise noted)

PARAMETER

I

IL

V

OH

V

OL f

OSC

T

A

Low-level input current

High-level output voltage

Low-level output voltage

Oscillator frequency

Operating free-air temperature

TEST CONDITIONS

SHUTDOWN, V

I

= 0, V

CC

= 24 V

SYNC, MUTE, GAIN0, GAIN1, MSTR/SLV, V

I

V, V

CC

= 24 V

= 0

FAULT, I

OH

= 1 mA

FAULT, I

OL

= -1 mA

R osc

Resistor = 100 k Ω , MSTR/SLV = 2 V

MIN

VREG - 0.6

200

–40

MAX UNIT

2

1

µA

AGND + 0.4

300

85

V

V kHz

°

C

DC CHARACTERISTICS

T

A

= 25

°

C, V

CC

= 24 V, R

L

= 8 Ω (unless otherwise noted)

| V

OS

|

PSRR

I

CC

I

CC(SD)

I

CC(MUTE) r

DS(on)

G t

ON t

OFF

PARAMETER

Class-D output offset voltage (measured differentially)

Bypass reference for input amplifier

4-V internal supply voltage

DC Power supply rejection ratio

Quiescent supply current

V

I

= 0 V, Gain = 36 dB

VBYP, no load

TEST CONDITIONS

VREG, no load, V

CC

= 10 V to 26 V

V

CC

= 12 V to 24 V, inputs ac coupled to AGND,

Gain = 36 dB

SHUTDOWN = 2 V, MUTE = 0 V, no load, filter or snubber

Quiescent supply current in shutdown mode SHUTDOWN = 0.8 V, no load, filter or snubber

Quiescent supply current in mute mode MUTE = 2 V, no load, filter or snubber

Drain-source on-state resistance

Gain

Gain matching

Turn-on time

Turn-off time

V

T

CC

J

= 12 V, I

= 25

°

C

O

GAIN1 = 0.8 V

= 500 mA,

High Side

Low side

Total

GAIN0 = 0.8 V

GAIN0 = 2 V

GAIN1 = 2 V

GAIN0 = 0.8 V

GAIN0 = 2 V

Between channels

C

(VBYP)

= 1 µF, SHUTDOWN = 2 V

C

(VBYP)

= 1 µF, SHUTDOWN = 0.8 V

MIN TYP MAX UNIT

5 50 mV

1.1

1.25

1.45

3.75

4 4.25

V

V

-70 dB

22 26.5

mA

19

25

31

35

300 400

8 10

µA mA

370

370 m Ω

780 950

20

26

21

27

32

36

33

37

2%

25

0.1

dB dB ms ms

DC CHARACTERISTICS

T

A

= 25

°

C, V

CC

= 12 V, R

L

= 8 Ω (unless otherwise noted)

| V

OS

|

PSRR

I

CC

I

CC(SD)

I

CC(MUTE) r

DS(on)

PARAMETER

Class-D output offset voltage (measured differentially)

Bypass reference for input amplifier

4-V internal supply voltage

DC Power supply rejection ratio

Quiescent supply current

V

I

TEST CONDITIONS

= 0 V, Gain = 36 dB

VBYP, no load

VREG, no load

V

CC

= 12 V to 24 V, Inputs ac coupled to AGND,

Gain = 36 dB

SHUTDOWN = 2 V, MUTE = 0 V, no load, filter or snubber

Quiescent supply current in shutdown mode SHUTDOWN = 0.8 V, no load, filter or snubber

Quiescent supply current in mute mode MUTE = 2 V, no load, filter or snubber

Drain-source on-state resistance

V

T

CC

J

= 12 V, I

= 25

°

C

O

= 500 mA,

High Side

Low side

Total

MIN TYP MAX UNIT

5 50 mV

1.1

1.25

1.45

3.75

4 4.25

-70

V

V dB

18 22.5

mA

180 300

7 9

µA mA

370

370

780 950 m

Copyright © 2005–2007, Texas Instruments Incorporated

Product Folder Link(s):

TPA3101D2

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3

TPA3101D2

SLOS473B – DECEMBER 2005 – REVISED SEPTEMBER 2007

DC CHARACTERISTICS (continued)

T

A

= 25

°

C, V

CC

= 12 V, R

L

= 8 Ω (unless otherwise noted)

PARAMETER

G t

ON t

OFF

Gain

Turn-on time

Turn-off time

GAIN1 = 0.8 V

TEST CONDITIONS

GAIN0 = 0.8 V

GAIN0 = 2 V

GAIN1 = 2 V

GAIN0 = 0.8 V

GAIN0 = 2 V

C

(VBYP)

= 1 µF, SHUTDOWN = 2 V

C

(VBYP)

= 1 µF, SHUTDOWN = 0.8 V

AC CHARACTERISTICS

T

A

= 25

°

C, V

CC

= 24 V, R

L

= 8 Ω (unless otherwise noted)

PARAMETER

K

SVR

Supply ripple rejection

P

O

Continuous output power

THD+N Total harmonic distortion + noise

TEST CONDITIONS

200 mV

PP ripple from 20 Hz–1 kHz,

Gain = 20 dB, Inputs ac-coupled to AGND

THD+N = 0.09%, f = 1 kHz (thermally limited) f = 1 kHz, P

O

= 5 W (half-power)

V n

Output integrated noise 20 Hz to 22 kHz, A-weighted filter, Gain = 20 dB

SNR

Crosstalk

Signal-to-noise ratio

Thermal trip point

Thermal hysteresis

V

O

= 1 Vrms, Gain = 20 dB, f = 1 kHz

Maximum output at THD+N < 1%, f = 1 kHz,

Gain = 20 dB, A-weighted

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MIN TYP MAX UNIT

19 20 21 dB

25 26 27

31

35

32

36

33

37 dB

25

0.1

ms ms

MIN TYP MAX UNIT

–70 dB

10

0.09%

100

–80

–92

W

102

150

30

µV dBV dB dB

°

C

°

C

AC CHARACTERISTICS

T

A

= 25

°

C, V

CC

= 12 V, R

L

= 8 Ω (unless otherwise noted)

PARAMETER

K

SVR

P

O

Supply ripple rejection

Continuous output power

THD+N Total harmonic distortion + noise

TEST CONDITIONS

200 mV

PP ripple from 20 Hz–1 kHz,

Gain = 20 dB, Inputs ac-coupled to AGND

THD+N = 7%, f = 1 kHz

THD+N = 10%, f = 1 kHz

THD+N = 10%, f = 1 kHz, V

CC

= 13 V

THD+N = 0.26%, f = 1 kHz, R

L limited)

= 4 Ω (thermally

R

L

= 8 Ω , f = 1 kHz, P

O

= 4.5 W (half-power)

R

L

= 4 Ω , f = 1 kHz, P

O

= 5 W (half-power)

V n

Output integrated noise 20 Hz to 22 kHz, A-weighted filter, Gain = 20 dB

SNR

Crosstalk

Signal-to-noise ratio

Thermal trip point

Thermal hysteresis

P o

= 1 W, Gain = 20 dB, f = 1 kHz

Maximum output at THD+N < 1%, f = 1 kHz,

Gain = 20 dB, A-weighted

MIN TYP MAX UNIT

–70 dB

8.7

9.2

10

10

W

0.08%

0.11%

100

–80

–94

98

150

30

µV dBV dB dB

°

C

°

C

4

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TPA3101D2

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48 PIN, QFN PACKAGE

(TOP VIEW)

TPA3101D2

SLOS473B – DECEMBER 2005 – REVISED SEPTEMBER 2007

48 PIN, HTQFP PACKAGE

(TOP VIEW)

NC

RINN

RINP

AGND

LINP

LINN

NC

GAIN0

GAIN1

MSTR/SLV

SYNC

NC

6

7

1

2

3

4

5

8

9

10

11

12

48 47 46 45 44 43 42 41 40 39 38 37

Exposed

Thermal Pad

13 14 15 16 17 18 19 20 21 22 23 24

36

35

29

28

27

26

25

34

33

32

31

30

NC

PVCCR

PVCCR

PGNDR

PGNDR

VCLAMPR

VCLAMPL

PGNDL

PGNDL

PVCCL

PVCCL

NC

GND

RINN

RINP

AGND

LINP

LINN

GAIN0

GAIN0

GAIN1

MSTR/SLV

SYNC

GND

48

47 46 45 44 43 42 41 40 39 38 37

8

9

10

11

12

1

4

5

2

3

6

7

Exposed

Thermal Pad

13 14 15 16 17 18 19 20 21 22 23 24

36

35

34

33

32

31

30

29

28

27

26

25

GND

PVCCR

PVCCR

PGNDR

PGNDR

VCLAMPR

VCLAMPL

PGNDL

PGNDL

PVCCL

PVCCL

GND

TERMINAL FUNCTIONS

MUTE

FAULT

BSLP

PVCCL

LOUTP

PGNDL

LOUTN

BSLN

VCLAMPL

VCLAMPR

BSRN

ROUTN

PGNDR

NAME

SHUTDOWN

RINN

RINP

LINN

LINP

GAIN0

GAIN1

GND

TERMINAL

QFN

NO.

44

2

3

6

5

8

9

45

46

18

26, 27

19, 20

28, 29

21, 22

23

30

31

38

39, 40

32, 33

HTQFP

NO.

44

2

3

6

5

7, 8

9

1, 12, 13,

24, 25, 36,

37

45

46

18

26, 27

19, 20

28, 29

21, 22

23

30

31

38

39, 40

32, 33

Copyright © 2005–2007, Texas Instruments Incorporated

I/O DESCRIPTION

I

I

I

I

I

I

I

I

O

I/O

O

O

I/O

I/O

O

Shutdown signal for IC (LOW = disabled, HIGH = operational). TTL logic levels with compliance to AVCC.

Negative audio input for right channel. Biased at VREG/2.

Positive audio input for right channel. Biased at VREG/2.

Negative audio input for left channel. Biased at VREG/2.

Positive audio input for left channel. Biased at VREG/2.

Gain select least significant bit. TTL logic levels with compliance to VREG.

Gain select most significant bit. TTL logic levels with compliance to VREG.

Connect to the thermal pad.

Mute signal for quick disable/enable of outputs (HIGH = outputs high-Z,

LOW = outputs enabled). TTL logic levels with compliance to AVCC.

TTL compatible output. HIGH = short-circuit fault. LOW = no fault. Only reports short-circuit faults. Thermal faults are not reported on this terminal.

Bootstrap I/O for left channel, positive high-side FET.

Power supply for left channel H-bridge, not internally connected to PVCCR or AVCC.

Class-D 1/2-H-bridge positive output for left channel.

Power ground for left channel H-bridge.

Class-D 1/2-H-bridge negative output for left channel.

Bootstrap I/O for left channel, negative high-side FET.

Internally generated voltage supply for left channel bootstrap capacitor.

Internally generated voltage supply for right channel bootstrap capacitor.

Bootstrap I/O for right channel, negative high-side FET.

Class-D 1/2-H-bridge negative output for right channel.

Power ground for right channel H-bridge.

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TPA3101D2

TPA3101D2

NAME

ROUTP

PVCCR

BSRP

AGND

ROSC

MSTR/SLV

SYNC

VBYP

VREG

AVCC

NC

10

11

16

15

10

11

16

15

47, 48

I

I/O

O

O

Not internally connected.

DESCRIPTION www.ti.com

SLOS473B – DECEMBER 2005 – REVISED SEPTEMBER 2007

TERMINAL FUNCTIONS (continued)

TERMINAL

QFN

NO.

41, 42

34, 35

43

4, 17

14

HTQFP

NO.

41, 42

34, 35

43

4, 17

14

I/O

O

I/O

I/O

Class-D 1/2-H-bridge positive output for right channel.

Power supply for right channel H-bridge, not connected to PVCCL or AVCC.

Bootstrap I/O for right channel, positive high-side FET.

Analog ground for digital/analog cells in core.

I/O for current setting resistor of ramp generator.

Master/Slave select for determining direction of SYNC terminal.

HIGH=Master mode, SYNC terminal is an output; LOW = slave mode,

SYNC terminal accepts a clock input. TTL logic levels with compliance to

VREG.

Clock input/output for synchronizing multiple class-D devices. Direction determined by MSTR/SLV terminal. Input signal not to exceed VREG.

Reference for preamplifier. Nominally equal to 1.25 V. Also controls start-up time via external capacitor sizing.

4-V regulated output for use by internal cells, GAINx, MUTE, and

MSTR/SLV pins only. Not specified for driving other external circuitry.

High-voltage analog power supply. Not internally connected to PVCCR or

PVCCL.

48

1, 7, 12,

13, 24, 25,

36, 37, 47

Thermal Pad -

Connect to AGND and PGND – should be star point for both grounds.

Internal resistive connection to AGND and PGND. Thermal vias on the PCB should connect this pad to a large copper area on an internal or bottom layer for the best thermal performance. The Thermal Pad must be soldered

to the PCB for mechanical reliability.

6

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VBYP

AVCC

VBYP

AVCC

RINN

RINP

VBYP

Gain

Control

GAIN0

GAIN1

FAULT

ROSC

SYNC

MSTR/SLV

VREG

SHUTDOWN

Gain

Control

8

To Gain Adj.

Blocks and

Startup Logic

MUTE

TLL Input

Buffer

(VCC Compliant)

TLL Input

Buffer

(VCC Compliant)

Ramp

Generator

VREG

LINN

LINP

VBYP

Gain

Control

4V Reg

Gain

Gain

TPA3101D2

SLOS473B – DECEMBER 2005 – REVISED SEPTEMBER 2007

FUNCTIONAL BLOCK DIAGRAM

PVCCR

PVCCR

PVCCR

VCLAMPR

BSRN

Gain

Gate

Drive

ROUTN

PWM

Logic

VClamp

Gen

PVCCR

BSRP

Gate

Drive

VBYP

AVCC

Biases and

References

Startup

Protection

Logic

SC

Detect

Thermal

VREG

VREGok

AVCC

VCCok

PWM

Logic

Gate

Drive

Gate

Drive

PVCCL

VClamp

Gen

PVCCL

ROUTP

PGNDR

PVCCL

PVCCL

VCLAMPL

BSLN

LOUTN

BSLP

LOUTP

Gain PGNDL

AGND

TYPICAL CHARACTERISTICS

TABLE OF GRAPHS

(1)

THD+N

THD+N

V

CC k

SVR

Total harmonic distortion + noise

Total harmonic distortion + noise

Closed-loop response

Output power

Efficiency

Supply current

Crosstalk

Supply ripple rejection ratio

(1) All graphs were measured using the TPA3101D2 EVM.

vs Frequency vs Output power vs Frequency vs Supply voltage vs Output power vs Total output power vs Frequency vs Frequency

FIGURE

1, 2, 3, 4

5, 6, 7, 8

9, 10

11. 12

13, 14

15, 16

17, 18

19, 20

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TPA3101D2

SLOS473B – DECEMBER 2005 – REVISED SEPTEMBER 2007

TOTAL HARMONIC DISTORTION + NOISE vs

FREQUENCY

10

5

2

V

CC

= 12 V,

R = 8

W

,

Gain = 20 dB

1

P

O

= 2.5 W

0.5

0.2

0.1

P

O

= 5 W

0.05

0.02

0.01

0.005

0.003

20

P

O

= 1 W

50 100 200 500 1k 2k f - Frequency - Hz

5k 10k 20k

NOTE: Power above 10 W may require increased heatsinking.

Figure 1.

TOTAL HARMONIC DISTORTION + NOISE vs

FREQUENCY

10

5

2

V

CC

= 24 V,

R = 8

W

,

Gain = 20 dB

1

0.5

0.2

0.1

P

O

= 10 W

0.05

P

O

= 1 W

P

O

= 5 W

0.02

0.01

0.005

0.003

20 50 100 200 500 1k 2k f - Frequency - Hz

5k 10k 20k

NOTE: Power above 10 W may require increased heatsinking.

Figure 3.

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TOTAL HARMONIC DISTORTION + NOISE vs

FREQUENCY

10

5

2

1

V

CC

= 18 V,

R = 8

W

,

Gain = 20 dB

0.5

0.2

0.1

P

O

= 10 W

0.05

0.02

0.01

0.005

0.003

20

P

O

= 1 W

P

O

= 2.5 W

50 100 200 500 1k 2k f - Frequency - Hz

5k 10k 20k

NOTE: Power above 10 W may require increased heatsinking.

Figure 2.

TOTAL HARMONIC DISTORTION + NOISE vs

FREQUENCY

10

5

V

CC

= 12 V,

R = 4

W

,

Gain = 20 dB

2

1

0.5

P

O

= 2.5 W

0.2

0.1

0.05

0.02

0.01

0.005

0.003

20

P

O

= 1 W

50 100 200 500 1k 2k f - Frequency - Hz

5k 10k 20k

NOTE: Power above 10 W may require increased heatsinking.

Figure 4.

8

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TOTAL HARMONIC DISTORTION + NOISE vs

OUTPUT POWER

10

5

V

CC

= 12 V,

R = 8

W

,

Gain = 32 dB

2

1

0.5

1 kHz

10 kHz

0.2

0.1

0.05

0.02

20 Hz

0.01

10m 50m 100m 200m 1 2 5 10 20

P

O

- Output Power - W

40

NOTE: Power above 10 W may require increased heatsinking.

Figure 5.

TOTAL HARMONIC DISTORTION + NOISE vs

OUTPUT POWER

10

5

V

CC

= 24 V,

R = 8

W

,

Gain = 32 dB

2

1

0.5

1 kHz

0.2

0.1

10 kHz

0.05

0.02

20 Hz

0.01

10m 50m 100m 200m 1 2 5 10 20

P

O

- Output Power - W

40

NOTE: Power above 10 W may require increased heatsinking.

Figure 7.

TPA3101D2

SLOS473B – DECEMBER 2005 – REVISED SEPTEMBER 2007

TOTAL HARMONIC DISTORTION + NOISE vs

OUTPUT POWER

10

5

V

CC

= 18 V,

R = 8

W

,

Gain = 32 dB

2

1

0.5

1 kHz

10 kHz

0.2

0.1

0.05

0.02

20 Hz

0.01

10m 50m 100m 200m 1 2 5 10 20

P

O

- Output Power - W

40

NOTE: Power above 10 W may require increased heatsinking.

Figure 6.

TOTAL HARMONIC DISTORTION + NOISE vs

OUTPUT POWER

10

5

V

CC

= 12 V,

R = 4

W

,

Gain = 32 dB

2

1

0.5

1 kHz

10 kHz

0.2

0.1

20 Hz

0.05

0.02

0.01

10m 50m 100m 200m 1 2 5 10 20

P

O

- Output Power - W

40

NOTE: Power above 10 W may require increased heatsinking.

Figure 8.

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TPA3101D2

SLOS473B – DECEMBER 2005 – REVISED SEPTEMBER 2007

CLOSED LOOP RESPONSE vs

FREQUENCY

40

35

200

150

Gain

30 100

25 50

Phase

20 0

15

10

V

CC

= 12 V

W

V = 0.1 V rms

-50

-100

5

Gain = 32 dB

RC filter = 100

W

, 10 nF

-150

0

10 100 1 k f - Frequency - Hz

Figure 9.

10 k

-200

100 k

OUTPUT POWER vs

SUPPLY VOLTAGE

37.5

35

32.5

30

27.5

25

22.5

20

17.5

15

12.5

10

7.5

5

10 12

W

Gain = 20 dB

THD+N = 10%

THD+N = 1%

Power Beyond 10 W

May Require More

Heatsinking.

14 16 18 20

V

CC

- Supply Voltage - V

Figure 11.

22 24 26 www.ti.com

CLOSED LOOP RESPONSE vs

FREQUENCY

40

35

200

150

Gain

30 100

25 50

Phase

20 0

15

10

V

CC

= 24 V

W

V = 0.1 V rms

-50

-100

14

12

10

8

6

4

5

0

10

Gain = 32 dB

RC filter = 100

W

, 10 nF

100 1 k f - Frequency - Hz

Figure 10.

10 k

OUTPUT POWER vs

SUPPLY VOLTAGE

20

18

16

W

Gain = 20 dB

THD+N = 10%

THD+N = 1%

2

0

10

Power Beyond 10 W

May Require More

Heatsinking.

-150

-200

100 k

13 11 12

V

CC

- Supply Voltage - V

Figure 12.

10

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EFFICIENCY vs

OUTPUT POWER

100

90

80

70

60

V

CC

= 12 V

V

CC

= 18 V

50

40

V

CC

= 24 V

30

20

10

R

L

= 8 W

Gain = 20 dB

0

0 2 4 6 8 10 12 14 16 18 20

P

O

− Output Power (Per Channel) − W

Figure 13.

SUPPLY CURRENT vs

TOTAL OUTPUT POWER

2.5

R

L

= 8 Ω

Gain = 32 dB

V

CC

= 18 V

2

V

CC

= 12 V

1.5

V

CC

= 24 V

1

0.5

0

0

Power Beyond 10 W

May Require More

Heatsinking.

10 20 30

P

O

− Total Output Power − W

Figure 15.

40

1

0.5

0

0

TPA3101D2

SLOS473B – DECEMBER 2005 – REVISED SEPTEMBER 2007

EFFICIENCY vs

OUTPUT POWER

100

90

80

70

60

V

CC

= 12 V

50

40

30

20

10

0

0

R

L

= 4 Ω

Gain = 32 dB

2 4 6 8 10 12 14 15

P

O

− Output Power (Per Channel) − W

Figure 14.

SUPPLY CURRENT vs

TOTAL OUTPUT POWER

2.5

R

L

= 4 Ω

Gain = 32 dB

2

V

CC

= 12 V

1.5

Power Beyond 10 W

May Require More

Heatsinking.

10 20 30

P

O

− Total Output Power − W

Figure 16.

40

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SLOS473B – DECEMBER 2005 – REVISED SEPTEMBER 2007

-40

−60

V

CC

R

L

= 12 V

= 8 Ω

Gain = 20 dB

CROSSTALK vs

FREQUENCY

−80

R to L

−100

L to R

−120

−50

−60

−70

−80

−140

20 100 1k f − Frequency − Hz

Figure 17.

SUPPLY RIPPLE REJECTION RATIO vs

FREQUENCY

0

−10

−20

V

CC

= 12 V

W

Gain = 20 dB

V

(RIPPLE)

= 200 mV

PP

−30

10k 20k

−40

−90

−100

20 10k 20k 100 1k f − Frequency − Hz

Figure 19.

www.ti.com

-40

−60

V

CC

R

L

= 24 V

= 8 Ω

Gain = 20 dB

CROSSTALK vs

FREQUENCY

L to R

−80

−100

R to L

−120

−50

−60

−70

−80

−140

20 100 1k f − Frequency − Hz

Figure 18.

SUPPLY RIPPLE REJECTION RATIO vs

FREQUENCY

0

−10

−20

V

CC

= 18 V

W

Gain = 20 dB

V

(RIPPLE)

= 200 mV

PP

−30

10k 20k

−40

−90

−100

20 10k 20k 100 1k f − Frequency − Hz

Figure 20.

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TPA3101D2

SLOS473B – DECEMBER 2005 – REVISED SEPTEMBER 2007

APPLICATION INFORMATION

470pF

20 W

470pF

8 W

10 V - 26 V

220nF 220nF

Differential

Analog

Inputs

4-Step

Gain Control

Synchronize Multiple

Class-D Devices

NC

RINN

RINP

AGND

LINP

LINN

NC

GAIN0

GAIN1

MSTR/SLV

SYNC

NC

TPA3101D2

100 kW

10 nF

220nF

470pF

20 W

220nF

470pF

20 W

Figure 21. Stereo Class-D With Differential Inputs (QFN)

NC

10 V - 26 V

PVCCR

PVCCR

PGNDR

PGNDR

VCLAMPR

VCLAMPL

PGNDL

PGNDL

PVCCL

PVCCL

NC

10 V - 26 V

8 W

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10 V - 26 V

470pF

20 W

470pF

20 W

220nF 220nF

Single-Ended

Analog

Inputs

4-Step

Gain Control

Synchronize Multiple

Class-D Devices

NC

RINN

RINP

AGND

LINP

LINN

NC

GAIN0

GAIN1

MSTR/SLV

SYNC

NC

TPA3101D2

100 kW

10 nF

220nF

470pF

20 W

470pF

220nF

20 W

Figure 22. Stereo Class-D With Single-Ended Inputs (QFN)

NC

10 V - 26 V

PVCCR

PVCCR

PGNDR

PGNDR

VCLAMPR

VCLAMPL

PGNDL

PGNDL

PVCCL

PVCCL

NC

10 V - 26 V

8 W

8 W

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10 V - 26 V

TPA3101D2

SLOS473B – DECEMBER 2005 – REVISED SEPTEMBER 2007

470pF

20 W

470pF

20 W

220nF 220nF

8 W

Differential

Analog

Inputs

4-Step

Gain Control

Synchronize Multiple

Class-D Devices

GND

RINN

RINP

AGND

LINP

LINN

GAIN0

GAIN0

GAIN1

MSTR/SLV

SYNC

GND

TPA3101D2

100 kW

10 nF

220nF

470pF

20 W

20 W

470pF

220nF

Figure 23. Stereo Class-D With Differential Inputs (HTQFP)

10 V - 26 V

GND

PVCCR

PVCCR

PGNDR

PGNDR

VCLAMPR

VCLAMPL

PGNDL

PGNDL

PVCCL

PVCCL

GND

10 V - 26 V

8 W

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SLOS473B – DECEMBER 2005 – REVISED SEPTEMBER 2007

www.ti.com

10 V - 26 V

470pF

20 W

470pF

20 W

220nF

220nF

Single-Ended

Analog

Inputs

4-Step

Gain Control

Synchronize Multiple

Class-D Devices

GND

RINN

RINP

AGND

LINP

LINN

GAIN0

GAIN0

GAIN1

MSTR/SLV

SYNC

GND

TPA3101D2

100 kW

10 nF

220nF

470pF

20 W

470pF

220nF

20 W

Figure 24. Stereo Class-D With Single-Ended Inputs (HTQFP)

10 V - 26 V

GND

PVCCR

PVCCR

PGNDR

PGNDR

VCLAMPR

VCLAMPL

PGNDL

PGNDL

PVCCL

PVCCL

GND

10 V - 26 V

8 W

8 W

16

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SLOS473B – DECEMBER 2005 – REVISED SEPTEMBER 2007

CLASS-D OPERATION

This section focuses on the class-D operation of the TPA3101D2.

Traditional Class-D Modulation Scheme

The traditional class-D modulation scheme, which is used in the TPA032D0x family, has a differential output where each output is 180 degrees out of phase and changes from ground to the supply voltage, V

CC the differential prefiltered output varies between positive and negative V

CC

. Therefore,

, where filtered 50% duty cycle yields

0 V across the load. The traditional class-D modulation scheme with voltage and current waveforms is shown in

Figure 25

. Note that even at an average of 0 V across the load (50% duty cycle), the current to the load is high, causing high loss and thus causing a high supply current.

OUTP

OUTN

Differential Voltage

Across Load

+12 V

0 V

-12 V

Current

Figure 25. Traditional Class-D Modulation Scheme's Output Voltage and Current Waveforms into an

Inductive Load With No Input

TPA3101D2 Modulation Scheme

The TPA3101D2 uses a modulation scheme that still has each output switching from 0 to the supply voltage.

However, OUTP and OUTN are now in phase with each other with no input. The duty cycle of OUTP is greater than 50% and OUTN is less than 50% for positive output voltages. The duty cycle of OUTP is less than 50% and

OUTN is greater than 50% for negative output voltages. The voltage across the load sits at 0 V throughout most of the switching period, greatly reducing the switching current, which reduces any I

2

R losses in the load.

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TPA3101D2

SLOS473B – DECEMBER 2005 – REVISED SEPTEMBER 2007

OUTP

Differential

Voltage

Across

Load

OUTN

+12 V

0 V

-12 V

Current www.ti.com

Output = 0 V

OUTP

Differential

Voltage

Across

Load

OUTN

+12 V

0 V

-12 V

Output > 0 V

Current

Figure 26. The TPA3101D2 Output Voltage and Current Waveforms Into an Inductive Load

Efficiency: LC Filter Required With the Traditional Class-D Modulation Scheme

The main reason that the traditional class-D amplifier needs an output filter is that the switching waveform results in maximum current flow. This causes more loss in the load, which causes lower efficiency. The ripple current is large for the traditional modulation scheme, because the ripple current is proportional to voltage multiplied by the time at that voltage. The differential voltage swing is 2 x V

CC

, and the time at each voltage is half the period for the traditional modulation scheme. An ideal LC filter is needed to store the ripple current from each half cycle for the next half cycle, while any resistance causes power dissipation. The speaker is both resistive and reactive, whereas an LC filter is almost purely reactive.

The TPA3101D2 modulation scheme has little loss in the load without a filter because the pulses are short and the change in voltage is V

CC instead of 2 x V

CC

. As the output power increases, the pulses widen, making the ripple current larger. Ripple current could be filtered with an LC filter for increased efficiency, but for most applications the filter is not needed.

An LC filter with a cutoff frequency less than the class-D switching frequency allows the switching current to flow through the filter instead of the load. The filter has less resistance but higher impedance at the switching frequency than the speaker, which results in less power dissipation, therefore increasing efficiency.

When to Use an Output Filter for EMI Suppression

Design the TPA3101D2 without the filter if the traces from amplifier to speaker are short (< 10 cm). Powered speakers, where the speaker is in the same enclosure as the amplifier, is a typical application for class-D without a filter.

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SLOS473B – DECEMBER 2005 – REVISED SEPTEMBER 2007

Most applications require a ferrite bead filter. The ferrite filter reduces EMI around 1 MHz and higher (FCC and

CE only test radiated emissions greater than 30 MHz). When selecting a ferrite bead, choose one with high impedance at high frequencies, but low impedance at low frequencies.

Use an LC output filter if there are low frequency (<1 MHz) EMI-sensitive circuits and/or there are long wires from the amplifier to the speaker.

When both an LC filter and a ferrite bead filter are used, the LC filter should be placed as close as possible to the IC followed by the ferrite bead filter.

OUTP

33

m

H

L1

C2

1 mF

OUTN

33 mH

L2

C3

1 mF

Figure 27. Typical LC Output Filter, Cutoff Frequency of 28 kHz, Speaker Impedance = 8

OUTP

15

m

H

L1

C2

2.2 mF

OUTN

15 mH

L2

C3

2.2 mF

Figure 28. Typical LC Output Filter, Cutoff Frequency of 28 kHz, Speaker Impedance = 4

Ferrite

Chip Bead

OUTP

1 nF

Ferrite

Chip Bead

OUTN

1 nF

Figure 29. Typical Ferrite Chip Bead Filter (Chip Bead Example: Fair-Rite 2512067007Y3)

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SLOS473B – DECEMBER 2005 – REVISED SEPTEMBER 2007

Using the LC filter in

Figure 27 , the TPA3101D2 EVM passed the FCC Part 15 Class B radiated emissions test

with 21 inch speaker wires. Quasi-peak measurements were taken for the 4 standard test configurations, and the

TPA3101D2 EVM passed with at least 14-dB margin. A plot of the peak measurement for the horizontal rear configuration is shown in

Figure 30

.

National Technical Systems, Plano Tx

Radiated Emissions 30 MHz - 1000 MHz

FCC B Limits

70

30

20

60

50

40

10

0

-10

30 M

FCC B Limit

Peak dB

230 M 430 M f − Frequency − Hz

630 M

Figure 30. Radiated Emissions Prescan 30 MHz - 1000 MHz

830 M

Inductors used in LC filters must be chosen carefully. A significant change in inductance at the peak output current of the TPA3101D2 will cause increased distortion. The change of inductance at currents up to the peak output current must be less than 0.1

μ H per amp to avoid this. Also note that smaller inductors than 33 μ H may cause an increase in distortion above what is shown in preceding graphs of THD versus frequency and output power.

Capacitors used in LC filters must also be chosen carefully. A significant change in capacitance at the peak output voltage of the TPA3101D2 will cause increased distortion. LC filter capacitors should have DC-voltage ratings of at least twice the peak application voltage (the power supply voltage) and should be made of X5R or better material. In all cases, avoid using capacitors with loose temperature ratings like Y5V.

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Adaptive Dynamic Range Control

TPA3101D2

Closest Competitor

TPA3101D2

SLOS473B – DECEMBER 2005 – REVISED SEPTEMBER 2007

TPA3101D2

Closest Competitor

Figure 31. 1-kHz Sine Output at 10% THD+N Figure 32. 8-kHz Sine Output at 10% THD+N

The Texas Instruments patent-pending adaptive dynamic range control (ADRC) technology removes the notch inherent in class-D audio power amplifiers when they come out of clipping. This effect is more severe at higher frequencies as shown in

Figure 32 .

Gain setting via GAIN0 and GAIN1 inputs

The gain of the TPA3101D2 is set by two input terminals, GAIN0 and GAIN1.

The gains listed in

Table 1

are realized by changing the taps on the input resistors and feedback resistors inside the amplifier. This causes the input impedance (Z

I

) to be dependent on the gain setting. The actual gain settings are controlled by ratios of resistors, so the gain variation from part-to-part is small. However, the input impedance from part-to-part at the same gain may shift by ±20% due to shifts in the actual resistance of the input resistors.

For design purposes, the input network (discussed in the next section) should be designed assuming an input impedance of 12.8 k Ω , which is the absolute minimum input impedance of the TPA3101D2. At the lower gain settings, the input impedance could increase as high as 38.4 k

GAIN1

0

0

1

1

Table 1. Gain Setting

GAIN0

0

1

0

1

AMPLIFIER GAIN (dB)

TYP

20

26

32

36

INPUT IMPEDANCE

(k Ω )

TYP

32

16

16

16

INPUT RESISTANCE

Changing the gain setting can vary the input resistance of the amplifier from its smallest value, 16 k Ω ±20%, to the largest value, 32 k Ω ±20%. As a result, if a single capacitor is used in the input high-pass filter, the -3 dB or cutoff frequency may change when changing gain steps.

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TPA3101D2

SLOS473B – DECEMBER 2005 – REVISED SEPTEMBER 2007

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Z f

Input

Signal

C i

IN

Z i

The -3-dB frequency can be calculated using

Equation 1

. Use the Z

I

1 f =

2 p

Z C i i values given in

Table 1

.

(1)

INPUT CAPACITOR, C

I

In the typical application, an input capacitor (C

I

) is required to allow the amplifier to bias the input signal to the proper dc level for optimum operation. In this case, C

I and the input impedance of the amplifier (Z

I

) form a high-pass filter with the corner frequency determined in

Equation 2 .

-3 dB f = c

1

2

p

Z C i i f c

(2)

The value of C

I is important, as it directly affects the bass (low-frequency) performance of the circuit. Consider the example where Z

I is 20 k Ω and the specification calls for a flat bass response down to 20 Hz.

Equation 2

is reconfigured as

Equation 3

.

1

C = i

2 p

Z f i c

(3)

In this example, C

I is 0.4 µF; so, one would likely choose a value of 0.47

the gain is known and is constant, use Z

I from

Table 1

to calculate C

I

μ

F as this value is commonly used. If

. A further consideration for this capacitor is the leakage path from the input source through the input network (C

I

) and the feedback network to the load. This leakage current creates a dc offset voltage at the input to the amplifier that reduces useful headroom, especially in high gain applications. For this reason, a low-leakage tantalum or ceramic capacitor is the best choice. When polarized capacitors are used, the positive side of the capacitor should face the amplifier input in most applications as the dc level there is held at 2 V, which is likely higher than the source dc level. Note that it is important to confirm the capacitor polarity in the application. Additionally, lead-free solder can create dc offset voltages and it is important to ensure that boards are cleaned properly.

Power Supply Decoupling, C

S

The TPA3101D2 is a high-performance CMOS audio amplifier that requires adequate power supply decoupling to ensure that the output total harmonic distortion (THD) is as low as possible. Power supply decoupling also prevents oscillations for long lead lengths between the amplifier and the speaker. The optimum decoupling is achieved by using two capacitors of different types that target different types of noise on the power supply leads.

For higher frequency transients, spikes, or digital hash on the line, a good low equivalent-series-resistance (ESR) ceramic capacitor, typically 0.1

μ

F to 1 µF placed as close as possible to the device V

CC lead works best. For filtering lower frequency noise signals, a larger aluminum electrolytic capacitor of 220 μ F or greater placed near the audio power amplifier is recommended. The 220

μ

F capacitor also serves as local storage capacitor for supplying current during large signal transients on the amplifier outputs. The PVCC terminals provide the power to the output transistors, so a 220 µF or larger capacitor should be placed on each PVCC terminal. A 10 µF capacitor on the AVCC terminal is adequate.

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SLOS473B – DECEMBER 2005 – REVISED SEPTEMBER 2007

IC Output Snubbers

In

Figure 33 , the 470-pF capacitors in series with 20-

Ω resistors from the outputs of the TPA3101D2 IC to ground are switching snubbers. They linearize switching transitions and reduce overshoot and ringing. By doing so they improve THD+N at lower power levels and they improve EMC by 2 to 4 dB at middle frequencies. They increase quiescent current by 3 to 12 mA depending on power supply voltage.

OUTP

OUTN

470 pF

20 W

470 pF

20 W

Figure 33. IC Output Snubbers

BSN and BSP Capacitors

The full H-bridge output stages use only NMOS transistors. Therefore, they require bootstrap capacitors for the high side of each output to turn on correctly. A 220-nF ceramic capacitor, rated for at least 25 V, must be connected from each output to its corresponding bootstrap input. Specifically, one 220-nF capacitor must be connected from xOUTP to BSxx, and one 220-nF capacitor must be connected from xOUTN to BSxx. (See the application circuit diagram in

Figure 21

.)

The bootstrap capacitors connected between the BSxx pins and corresponding output function as a floating power supply for the high-side N-channel power MOSFET gate drive circuitry. During each high-side switching cycle, the bootstrap capacitors hold the gate-to-source voltage high enough to keep the high-side MOSFETs turned on.

VCLAMP Capacitors

To ensure that the maximum gate-to-source voltage for the NMOS output transistors is not exceeded, two internal regulators clamp the gate voltage. Two 1μ F capacitors must be connected from VCLAMPL (pin 30) and

VCLAMPR (pin 31) to ground and must be rated for at least 16 V. The voltages at the VCLAMP terminals may vary with V

CC and may not be used for powering any other circuitry.

Internal Regulated 4-V Supply (VREG)

The VREG terminal (pin 15) is the output of an internally generated 4-V supply, used for the oscillator, preamplifier, and gain control circuitry. It requires a 10-nF capacitor, placed close to the pin, to keep the regulator stable.

This regulated voltage can be used to control GAIN0, GAIN1, MSTR/SLV, and MUTE terminals, but should not be used to drive external circuitry.

VBYP Capacitor Selection

The internal bias generator (VBYP) nominally provides a 1.25-V internal bias for the preamplifier stages. The external input capacitors and this internal reference allow the inputs to be biased within the optimal common-mode range of the input preamplifiers.

The selection of the capacitor value on the VBYP terminal is critical for achieving the best device performance.

During power up or recovery from the shutdown state, the VBYP capacitor determines the rate at which the amplifier starts up. When the voltage on the VBYP capacitor equals VBYP, the device starts a 16.4-ms timer.

When this timer completes, the outputs start switching. The charge rate of the capacitor is calculated using the standard charging formula for a capacitor, I = C x dV/dT. The charge current is nominally equal to 250µA and dV is equal to VBYP. For example, a 1-µF capacitor on VBYP would take 5 ms to reach the value of VBYP and begin a 16.4-ms count before the outputs turn on. This equates to a turn-on time of <30 ms for a 1-µF capacitor on the VBYP terminal.

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SLOS473B – DECEMBER 2005 – REVISED SEPTEMBER 2007

A secondary function of the VBYP capacitor is to filter high-frequency noise on the internal 1.25-V bias generator.

A value of at least 0.47µF is recommended for the VBYP capacitor. For the best power-up and shutdown pop performance, the VBYP capacitor should be greater than or equal to the input capacitors.

ROSC Resistor Selection

The resistor connected to the ROSC terminal controls the class-D output switching frequency using

Equation 4 :

1

F

OSC

=

2 x ROSC x COSC

(4)

COSC is an internal capacitor that is nominally equal to 20 pF. Variation over process and temperature can result in a ±15% change in this capacitor value.

For example, if ROSC is fixed at 100 k Ω , the frequency from device to device with this fixed resistance could vary from 217 kHz to 294 kHz with a 15% variation in the internal COSC capacitor. The tolerance of the ROSC resistor should also be considered to determine the range of expected switching frequencies from device to device. It is recommended that 1% tolerance resistors be used.

Differential Input

The differential input stage of the amplifier cancels any noise that appears on both input lines of the channel. To use the TPA3101D2 with a differential source, connect the positive lead of the audio source to the INP input and the negative lead from the audio source to the INN input. To use the TPA3101D2 with a single-ended source, ac ground the INP or INN input through a capacitor equal in value to the input capacitor on INN or INP and apply the audio source to either input. In a single-ended input application, the unused input should be ac grounded at the audio source instead of at the device input for best noise performance.

SHUTDOWN OPERATION

The TPA3101D2 employs a shutdown mode of operation designed to reduce supply current (I

CC

) to the absolute minimum level during periods of nonuse for power conservation. The SHUTDOWN input terminal should be held high (see specification table for trip point) during normal operation when the amplifier is in use. Pulling

SHUTDOWN low causes the outputs to mute and the amplifier to enter a low-current state. Never leave

SHUTDOWN unconnected, because amplifier operation would be unpredictable.

For the best power-off pop performance, place the amplifier in the shutdown or mute mode prior to removing the power supply voltage.

MUTE Operation

The MUTE pin is an input for controlling the output state of the TPA3101D2. A logic high on this terminal disables the outputs. A logic low on this pin enables the outputs. This terminal may be used as a quick disable/enable of outputs when changing channels on a television or transitioning between different audio sources.

The MUTE terminal should never be left floating. For power conservation, the SHUTDOWN terminal should be used to reduce the quiescent current to the absolute minimum level.

The MUTE terminal can also be used with the FAULT output to automatically recover from a short-circuit event.

When a short-circuit event occurs, the FAULT terminal transitions high indicating a short-circuit has been detected. When directly connected to MUTE, the MUTE terminal transitions high, and clears the internal fault flag. This causes the FAULT terminal to cycle low, and normal device operation resumes if the short-circuit is removed from the output. If a short remains at the output, the cycle continues until the short is removed.

If external MUTE control is desired, and automatic recovery from a short-circuit event is also desired, an OR gate can be used to combine the functionality of the FAULT output and external MUTE control, see

Figure 34 .

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External GPIO

Control

TPA3101D2

SLOS473B – DECEMBER 2005 – REVISED SEPTEMBER 2007

TPA3101D2

MUTE

FAULT

Figure 34. External MUTE Control

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SLOS473B – DECEMBER 2005 – REVISED SEPTEMBER 2007

MSTR/SLV and SYNC operation

The MSTR/SLV and SYNC terminals can be used to synchronize the frequency of the class-D output switching.

When the MSTR/SLV terminal is high, the output switching frequency is determined by the selection of the resistor connected to the ROSC terminal (see ROSC Resistor Selection). The SYNC terminal becomes an output in this mode, and the frequency of this output is also determined by the selection of the ROSC resistor. This TTL compatible, push-pull output can be connected to another TPA3101D2, configured in the slave mode. The output switching is synchronized to avoid any beat frequencies that could occur in the audio band when two class-D amplifiers in the same system are switching at slightly different frequencies.

When the MSTR/SLV terminal is low, the output switching frequency is determined by the incoming square wave on the SYNC input. The SYNC terminal becomes an input in this mode and accepts a TTL compatible square wave from another TPA3101D2 configured in the master mode or from an external GPIO. If connecting to an external GPIO, recommended frequencies are 200 kHz to 300 kHz for proper device operation, and the maximum amplitude is 4 V.

USING LOW-ESR CAPACITORS

Low-ESR capacitors are recommended throughout this application section. A real (as opposed to ideal) capacitor can be modeled simply as a resistor in series with an ideal capacitor. The voltage drop across this resistor minimizes the beneficial effects of the capacitor in the circuit. The lower the equivalent value of this resistance, the more the real capacitor behaves like an ideal capacitor.

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SLOS473B – DECEMBER 2005 – REVISED SEPTEMBER 2007

SHORT-CIRCUIT PROTECTION AND AUTOMATIC RECOVERY FEATURE

The TPA3101D2 has short-circuit protection circuitry on the outputs that prevents damage to the device during output-to-output shorts, output-to-GND shorts, and output-to-V

CC shorts. When a short circuit is detected on the outputs, the part immediately disables the output drive. This is a latched fault and must be reset by cycling the voltage on the SHUTDOWN pin or MUTE pin. This clears the short-circuit flag and allows for normal operation if the short was removed. If the short was not removed, the protection circuitry again activates.

The FAULT terminal can be used for automatic recovery from a short-circuit event, or used to monitor the status with an external GPIO. For automatic recovery from a short-circuit event, connect the FAULT terminal directly to the MUTE terminal. When a short-circuit event occurs, the FAULT terminal transitions high indicating a short-circuit has been detected. When directly connected to MUTE, the MUTE terminal transitions high, and clears the internal fault flag. This causes the FAULT terminal to cycle low, and normal device operation resumes if the short-circuit is removed from the output. If a short remains at the output, the cycle continues until the short is removed. If external MUTE control is desired, and automatic recovery from a short-circuit event is also desired, an OR gate can be used to combine the functionality of the FAULT output and external MUTE control, see

Figure 34 .

THERMAL PROTECTION

Thermal protection on the TPA3101D2 prevents damage to the device when the internal die temperature exceeds 150

°

C. There is a ±15

°

C tolerance on this trip point from device to device. Once the die temperature exceeds the thermal set point, the device enters into the shutdown state and the outputs are disabled. This is not a latched fault. The thermal fault is cleared once the temperature of the die is reduced by 30

°

C. The device begins normal operation at this point with no external system interaction.

PRINTED-CIRCUIT BOARD (PCB) LAYOUT

Because the TPA3101D2 is a class-D amplifier that switches at a high frequency, the layout of the printed-circuit board (PCB) should be optimized according to the following guidelines for the best possible performance.

Decoupling capacitors—The high-frequency 1µF decoupling capacitors should be placed as close to the

PVCC (pins 26, 27, 34, and 35) and AVCC (pin 48) terminals as possible. The VBYP (pin 16) capacitor,

VREG (pin 15) capacitor, and VCLAMP (pins 30 and 31) capacitor should also be placed as close to the device as possible. Large (220 µF or greater) bulk power supply decoupling capacitors should be placed near the TPA3101D2 on the PVCCL, PVCCR, and AVCC terminals.

Grounding—The AVCC (pin 48) decoupling capacitor, VREG (pin 15) capacitor, VBYP (pin 16) capacitor, and

ROSC (pin 14) resistor should each be grounded to analog ground (AGND, pin 17). The PVCC decoupling capacitors and VCLAMP capacitors should each be grounded to power ground (PGND, pins 28, 29, 32, and

33). Analog ground and power ground should be connected at the thermal pad, which should be used as a central ground connection or star ground for the TPA3101D2.

Output filter—The ferrite EMI filter ( Figure 29

) should be placed as close to the output terminals as possible

for the best EMI performance. The LC filter ( Figure 27

and

Figure 28 ) should be placed close to the outputs.

The capacitors used in both the ferrite and LC filters should be grounded to power ground. If both filters are used, the LC filter should be placed first, following the outputs.

Thermal Pad—The thermal pad must be soldered to the PCB for proper thermal performance and optimal reliability. The dimensions of the thermal pad and thermal land should be 5,1 mm by 5,1 mm. Five rows of solid vias (five vias per row, 0,3302 mm or 13 mils diameter) should be equally spaced underneath the thermal land. The vias should connect to a solid copper plane, either on an internal layer or on the bottom layer of the PCB. The vias must be solid vias, not thermal relief or webbed vias. See TI Technical Briefs

SCBA017D and SLUA271 for more information about using the QFN thermal pad. See TI Technical Briefs

SLMA002 for more information about using the HTQFP thermal pad. For recommended PCB footprints, see figures at the end of this data sheet.

For an example layout, see the TPA3101D2 Evaluation Module (TPA3101D2EVM) User Manual, (SLOU179).

Both the EVM user manual and the thermal pad application note are available on the TI Web site at http://www.ti.com.

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SLOS473B – DECEMBER 2005 – REVISED SEPTEMBER 2007

BASIC MEASUREMENT SYSTEM

This application note focuses on methods that use the basic equipment listed below:

Audio analyzer or spectrum analyzer

Digital multimeter (DMM)

Oscilloscope

Twisted-pair wires

Signal generator

Power resistor(s)

Linear regulated power supply

Filter components

EVM or other complete audio circuit

Figure 35

shows the block diagrams of basic measurement systems for class-AB and class-D amplifiers. A sine wave is normally used as the input signal because it consists of the fundamental frequency only (no other harmonics are present). An analyzer is then connected to the APA output to measure the voltage output. The analyzer must be capable of measuring the entire audio bandwidth. A regulated dc power supply is used to reduce the noise and distortion injected into the APA through the power pins. A System Two audio measurement system (AP-II) (Reference 1) by Audio Precision includes the signal generator and analyzer in one package.

The generator output and amplifier input must be ac-coupled. However, the EVMs already have the ac-coupling capacitors, (C

IN

), so no additional coupling is required. The generator output impedance should be low to avoid attenuating the test signal, and is important because the input resistance of APAs is not high. Conversely, the analyzer-input impedance should be high. The output resistance, R

OUT milliohms and can be ignored for all but the power-related calculations.

, of the APA is normally in the hundreds of

Figure 35 (a) shows a class-AB amplifier system. It takes an analog signal input and produces an analog signal

output. This amplifier circuit can be directly connected to the AP-II or other analyzer input.

This is not true of the class-D amplifier system shown in

Figure 35

(b), which requires low-pass filters in most cases in order to measure the audio output waveforms. This is because it takes an analog input signal and converts it into a pulse-width modulated (PWM) output signal that is not accurately processed by some analyzers.

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Power Supply

TPA3101D2

SLOS473B – DECEMBER 2005 – REVISED SEPTEMBER 2007

Signal

Generator

APA R

L

Analyzer

20 Hz - 20 kHz

Signal

Generator

Power Supply

(a) Basic Class-AB

Class-D APA

R

L

(See note A)

Low-Pass RC

Filter

Low-Pass RC

Filter

Analyzer

20 Hz - 20 kHz

(b) Filter-Free and Traditional Class-D

A.

For efficiency measurements with filter-free Class-D, R

L should be an inductive load like a speaker.

Figure 35. Audio Measurement Systems

The TPA3101D2 uses a modulation scheme that does not require an output filter for operation, but they do sometimes require an RC low-pass filter when making measurements. This is because some analyzer inputs cannot accurately process the rapidly changing square-wave output and therefore record an extremely high level of distortion. The RC low-pass measurement filter is used to remove the modulated waveforms so the analyzer can measure the output sine wave.

DIFFERENTIAL INPUT AND BTL OUTPUT

All of the class-D APAs and many class-AB APAs have differential inputs and bridge-tied load (BTL) outputs.

Differential inputs have two input pins per channel and amplify the difference in voltage between the pins.

Differential inputs reduce the common-mode noise and distortion of the input circuit. BTL is a term commonly used in audio to describe differential outputs. BTL outputs have two output pins providing voltages that are 180 degrees out of phase. The load is connected between these pins. This has the added benefits of quadrupling the output power to the load and eliminating a dc blocking capacitor.

A block diagram of the measurement circuit is shown in

Figure 36 . The differential input is a balanced input,

meaning the positive (+) and negative (-) pins have the same impedance to ground. Similarly, the BTL output equates to a balanced output.

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TPA3101D2

SLOS473B – DECEMBER 2005 – REVISED SEPTEMBER 2007

Generator

V

GEN

R

GEN

R

GEN

C

IN

Evaluation Module

Audio Power

Amplifier

C

IN

R

IN

R

OUT

R

IN

R

OUT

R

L

Low-Pass

RC Filter

Low-Pass

RC Filter

R

ANA

R

ANA

Analyzer

C

ANA

C

ANA www.ti.com

Twisted-Pair Wire Twisted-Pair Wire

Figure 36. Differential Input, BTL Output Measurement Circuit

The generator should have balanced outputs, and the signal should be balanced for best results. An unbalanced output can be used, but it may create a ground loop that affects the measurement accuracy. The analyzer must also have balanced inputs for the system to be fully balanced, thereby cancelling out any common-mode noise in the circuit and providing the most accurate measurement.

The following general rules should be followed when connecting to APAs with differential inputs and BTL outputs:

Use a balanced source to supply the input signal.

Use an analyzer with balanced inputs.

Use twisted-pair wire for all connections.

Use shielding when the system environment is noisy.

Ensure that the cables from the power supply to the APA, and from the APA to the load, can handle the large currents (see

Table 2

).

Table 2

shows the recommended wire size for the power supply and load cables of the APA system. The real concern is the dc or ac power loss that occurs as the current flows through the cable. These recommendations are based on 12-inch long wire with a 20-kHz sine-wave signal at 25

°

C.

P

OUT

(W)

10

2

1

< 0.75

Table 2. Recommended Minimum Wire Size for Power Cables

R

L

( Ω )

8

8

4

4

18

18

22

22

AWG Size

22

22

28

28

DC POWER LOSS

(MW)

16 40

3.2

2

1.5

8

8

6.1

AC POWER LOSS

(MW)

18 42

3.7

2.1

1.6

8.5

8.1

6.2

CLASS-D RC LOW-PASS FILTER

An RC filter is used to reduce the square-wave output when the analyzer inputs cannot process the pulse-width modulated class-D output waveform. This filter has little effect on the measurement accuracy because the cutoff frequency is set above the audio band. The high frequency of the square wave has negligible impact on measurement accuracy because it is well above the audible frequency range, and the speaker cone cannot respond at such a fast rate. The RC filter is not required when an LC low-pass filter is used, such as with the class-D APAs that employ the traditional modulation scheme (TPA032D0x, TPA005Dxx).

The component values of the RC filter are selected using the equivalent output circuit as shown in

Figure 37 . R

L is the load impedance that the APA is driving for the test. The analyzer input impedance specifications should be available and substituted for R

ANA and C

ANA

. The filter components, R

FILT and C

FILT

, can then be derived for the system. The filter should be grounded to the APA near the output ground pins or at the power supply ground pin to minimize ground loops.

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TPA3101D2

SLOS473B – DECEMBER 2005 – REVISED SEPTEMBER 2007

R

L

Load

V

L

= V

IN

C

ANA

R

ANA

C

ANA

R

ANA

AP Analyzer Input RC Low-Pass Filters

R

FILT

C

FILT

V

OUT

R

FILT

C

FILT

To APA

GND

Figure 37. Measurement Low-Pass Filter Derivation Circuit-Class-D APAs

The transfer function for this circuit is shown in

Equation 5

where

ω

C

EQ

= (C

FILT

+ C

ANA

). The filter frequency should be set above f

MAX

O

= R

EQ

C

EQ

, R

EQ

= R

FILT

|| R

ANA and

, the highest frequency of the measurement bandwidth, to avoid attenuating the audio signal.

Equation 6

provides this cutoff frequency, f

C

. The value of R

FILT must be chosen large enough to minimize current that is shunted from the load, yet small enough to minimize the attenuation of the analyzer-input voltage through the voltage divider formed by R

FILT that R

FILT should be small (~100 Ω ) for most measurements. This reduces the measurement error to less than

1% for R

ANA

10 k

.

and R

ANA

. A general rule is

(

V

OUT

V

IN

)

=

(

R

ANA

R

ANA

1 + j

(

+ R

FILT w

)

)

(5) w

O f = c

Ö

2 x f max

(6)

An exception occurs with the efficiency measurements, where R

FILT must be increased by a factor of ten to reduce the current shunted through the filter. C

FILT must be decreased by a factor of ten to maintain the same cutoff frequency. See

Table 3

for the recommended filter component values.

Once f

C is determined and R

FILT is selected, the filter capacitance is calculated using . When the calculated value is not available, it is better to choose a smaller capacitance value to keep f

C above the minimum desired value calculated in

Equation 7

.

C

FILT

=

1

2 p x f x R c FILT

(7)

Table 3

shows recommended values of R

FILT and C was originally calculated to be 28 kHz for an f

MAX

FILT based on common component values. The value of f

C of 20 kHz. C

FILT

, however, was calculated to be 57,000 pF, but the nearest values of 56,000 pF and 51,000 pF were not available. A 47,000-pF capacitor was used instead, and f

C is 34 kHz, which is above the desired value of 28 kHz.

Table 3. Typical RC Measurement Filter Values

MEASUREMENT

Efficiency

All other measurements

R

FILT

1000 Ω

100 Ω

C

FILT

5,600 pF

56,000 pF

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PACKAGE OPTION ADDENDUM

20-Aug-2007

PACKAGING INFORMATION

Orderable Device

TPA3101D2PHP

TPA3101D2PHPG4

TPA3101D2PHPR

TPA3101D2PHPRG4

TPA3101D2RGZR

TPA3101D2RGZRG4

TPA3101D2RGZT

TPA3101D2RGZTG4

Status

(1)

ACTIVE

ACTIVE

ACTIVE

ACTIVE

ACTIVE

ACTIVE

ACTIVE

ACTIVE

Package

Type

HTQFP

HTQFP

HTQFP

HTQFP

QFN

QFN

QFN

QFN

Package

Drawing

PHP

PHP

PHP

PHP

RGZ

RGZ

RGZ

RGZ

Eco Plan

(2)

Pins Package

Qty

48 250 Green (RoHS & no Sb/Br)

Lead/Ball Finish MSL Peak Temp

(3)

CU NIPDAU Level-3-260C-168 HR

48 CU NIPDAU Level-3-260C-168 HR

48

250 Green (RoHS & no Sb/Br)

1000 Green (RoHS & no Sb/Br)

CU NIPDAU Level-3-260C-168 HR

48 CU NIPDAU Level-3-260C-168 HR

48

48

48

48

1000 Green (RoHS & no Sb/Br)

2500 Green (RoHS & no Sb/Br)

2500 Green (RoHS & no Sb/Br)

250 Green (RoHS & no Sb/Br)

250 Green (RoHS & no Sb/Br)

CU NIPDAU

CU NIPDAU

CU NIPDAU

CU NIPDAU

Level-3-260C-168 HR

Level-3-260C-168 HR

Level-3-260C-168 HR

Level-3-260C-168 HR

(1)

The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2)

Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

(3)

MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 1

www.ti.com

TAPE AND REEL INFORMATION

PACKAGE MATERIALS INFORMATION

11-Mar-2008

*All dimensions are nominal

Device

TPA3101D2PHPR

TPA3101D2RGZR

TPA3101D2RGZT

Package

Type

Package

Drawing

HTQFP

QFN

QFN

PHP

RGZ

RGZ

Pins

48

48

48

SPQ

1000

2500

250

Reel

Diameter

(mm)

Reel

Width

W1 (mm)

330.0

16.4

330.0

180.0

16.4

16.4

A0 (mm)

9.6

7.3

7.3

B0 (mm)

9.6

7.3

7.3

K0 (mm) P1

(mm)

W

(mm)

Pin1

Quadrant

1.5

1.5

1.5

12.0

16.0

12.0

16.0

12.0

16.0

Q2

Q2

Q2

Pack Materials-Page 1

www.ti.com

PACKAGE MATERIALS INFORMATION

11-Mar-2008

*All dimensions are nominal

Device

TPA3101D2PHPR

TPA3101D2RGZR

TPA3101D2RGZT

Package Type Package Drawing Pins

HTQFP

QFN

QFN

PHP

RGZ

RGZ

48

48

48

SPQ

1000

2500

250

Length (mm) Width (mm) Height (mm)

346.0

346.0

190.5

346.0

346.0

212.7

33.0

33.0

31.8

Pack Materials-Page 2

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