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SLOS559 – JUNE 2008
20-W STEREO DIGITAL AUDIO POWER AMPLIFIER
1
FEATURES
•
Audio Input/Output
– 20-W Into an 8Ω Load From an 18-V Supply
– Wide PVDD Range (0 V to 21 V)
– Efficient Class-D Operation Eliminates
Need for Heat Sinks
– Two Serial Audio Inputs (3 Audio channels)
– Supports 32-kHz to 192-kHz Sample Rates
(LJ/RJ/I
2
S)
– Line-Level Subwoofer PWM Outputs
•
Audio/PWM Processing
– BD (Filter-free) Modulation Supporting
Bridge-Tied Loads ONLY
– 4-Step Volume Control (0 dB, 6 dB, 12 dB,
18 dB)
– All Channels Share Same Control
– Soft Mute (50% Duty Cycle)
– DC Blocking Filters
– Fixed Maximum Modulation Limit At 97.7%
– ≥100-dB SNR – Measured at Maximum
Output With THD+N = 1%, 1 kHz,
A-Weighted Noise, Gain = 0 dB
– THD < 0.1% at 1/2 Rated Power
•
General Features
– 5-V Tolerant Inputs (See pin list for details on which inputs are 5-V tolerant)
– Shutdown Mode for Low Power
Consumption
– Thermal and Short-Circuit Protection
– Autodetect: Automatically Detect
Sample-Rate Changes – No Need for
External Microprocessor Intervention
DESCRIPTION
The TAS5701 is a 20-W efficient, digital audio power amplifier for driving stereo bridge-tied speakers. Two serial data inputs support up to 3 discrete audio channels. The SDIN1 input is routed to the internal left and right outputs. The SDIN2 input is dedicated to the SUB_PWM± outputs.
The TAS5701 is a clock slave-only device receiving clocks from external sources. The TAS5701 operates at a 384-kHz switching rate for 32-, 48-, 96-, and
192-kHz data and 352.8-kHz switching rate
44.1-,88.2-, and 176.4-kHz data.
The 8× oversampling combined with the fourth-order noise shaper provides a flat noise floor and excellent dynamic range from 20 Hz to 20 kHz.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Copyright © 2008, Texas Instruments Incorporated
TAS5701
SLOS559 – JUNE 2008 ......................................................................................................................................................................................................
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These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.
SIMPLIFIED APPLICATION DIAGRAM
3.3 V 12 V 0 V–21 V
DVDD
GVDD
PVDD
Digital
Audio
Source
Control
Inputs
LRCLK
SCLK
MCLK_IN
SDIN1
SDIN2
GAINx (2 pins)
FORMATx (3 pins)
MUTE
RESET
PDN
OUT_A
BSA
BSB
OUT_B
OUT_C
BSC
BSD
OUT_D
TAS5132
12 V
Left
Right
0 V–21 V
Loop
Filter
PLL_FLTP
PLL_FLTM
SUB_PWM+
SUB_PWM–
BKND_ERR
VALID
SOUT+
SIN+
SIN–
FAULT
RESET
SOUT–
Subwoofer
B0264-08
2
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SLOS559 – JUNE 2008
FUNCTIONAL BLOCK DIAGRAM
SDIN1
SDIN2
Serial
Audio
Port
L
R
Sub
Gain
Control
S
R
C
4 th
Order
Noise
Shaper and
PWM
´
FET Out
OUT_A
OUT_B
´
FET Out
OUT_C
OUT_D
Protection
Logic
Click and Pop Control
Inter-Channel Delay
MCLK
SCLK
LRCLK
Sample Rate
Autodetect and PLL
Trimmed
On-Chip OSC
Terminal Control
Microcontroller
Based
System
Control
SUB_PWM+
SUB_PWM–
B0262-04
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FAULT
Undervoltage
Protection
4
4
Internal Pullup
Resistors to VREG
FAULT
Power
On
Reset
VREG
Protection and
I/O Logic
AGND
Temp.
Sense
GND
VALID
Overcurrent
Protection
I sense
OC_ADJ
PWM_D
PWM
Rcv
PWM_C
PWM
Rcv
PWM_B
PWM
Rcv
PWM_A
PWM
Rcv
Ctrl
Ctrl
Ctrl
Ctrl
Timing
Gate
Drive
GVDD_CD
Regulator
Timing
Timing
Gate
Drive
GVDD_AB
Regulator
Timing
Gate
Drive
Gate
Drive
BTL-Configuration
Pulldown Resistor
BTL-Configuration
Pulldown Resistor
BTL-Configuration
Pulldown Resistor
BTL-Configuration
Pulldown Resistor
BST_D
PVDD_D
OUT_D
PGND_CD
GVDD_CD
BST_C
PVDD_C
OUT_C
PGND_CD
BST_B
PVDD_B
OUT_B
PGND_AB
GVDD_AB
BST_A
PVDD_A
OUT_A
PGND_AB
B0034-04
Figure 1. Power Stage Functional Block Diagram
4
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SLOS559 – JUNE 2008
64-PIN, HTQFP PACKAGE (TOP VIEW)
PAP Package
(Top View)
OUT_A
PVDD_A
PVDD_A
BST_A
GVDD_AB
VDD
TEST1
OC_ADJ
FAULT
AVDD
AVSS
PLL_FLTM
PLL_FLTP
VR_ANA
DVDD
RESET
9
10
11
12
13
14
15
16
7
8
5
6
3
4
1
2
64 63 62 61 60 59 58 57 56 55
54
53 52 51 50 49
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
40
39
38
37
36
35
34
33
44
43
42
41
48
47
46
45
OUT_D
PVDD_D
PVDD_D
BST_D
GVDD_CD
VREG
GND
GND
SUB_PWM+
SUB_PWM–
VALID
BKND_ERR
MCLK
DVDD
CONFIG_1
CONFIG_2
TERMINAL
NAME NO.
AVDD
AVSS
BKND_ERR
10
11
37
P0071-03
I/O
(1)
P
P
DI
P
P
5-V
TOLERANT
TERMINAL FUNCTIONS
TERMINATION
(2) (3)
Pullup
DESCRIPTION
3.3-V Analog power supply
Analog 3.3-V supply ground
Active low. A back-end error sequence is initiated by applying a logic low to this pin. Connect to an external power stage. If no external power stage is used, connect directly to DVDD.
High-side bootstrap supply for half-bridge A
High-side bootstrap supply for half-bridge B
BST_A
BST_B
4
57
(1) TYPE: A = analog; D = 3.3-V digital; P = power/ground/decoupling; I = input; O = output
(2) All pullups are 20-
µ
A weak pullups and all pulldowns are 20-
µ
A weak pulldowns. The pullups and pulldowns are included to assure proper input logic levels if the terminals are left unconnected (pullups → logic 1 input; pulldowns → logic 0 input). Devices that drive inputs with pullups must be able to sink 50
µ
A while maintaining a logic-0 drive level. Devices that drive inputs with pulldowns must be able to source 50
µ
A while maintaining a logic-1 drive level.
(3) If desired, low-ESR capacitance values can be implemented by paralleling two or more ceramic capacitors of equal value. Paralleling capacitors of equal value provides an extended high-frequency supply decoupling. This approach avoids the potential of producing parallel resonance circuits that have been observed when paralleling capacitors of different values.
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TERMINAL
NAME NO.
BST_C
BST_D
56
45
CONFIG_2
CONFIG_1
DVDD
DVSS
DVSSO
FAULT
33
34
15, 35
26
20
9
FORMAT2
FORMAT1
FORMAT0
GAIN_1
GAIN_0
GND
GVDD_AB
GVDD_CD
LRCLK
MCLK
MUTE
OC_ADJ
OSC_RES
OUT_A
OUT_B
OUT_C
OUT_D
PDN
PGND_AB
PGND_CD
PLL_FLTM
PLL_FLTP
PVDD_A
PVDD_B
PVDD_C
PVDD_D
41, 42
5
44
22
36
1, 64
60, 61
52, 53
48, 49
17
62, 63
50, 51
12
13
2, 3
58, 59
54, 55
46, 47
30
31
32
28
29
21
8
19
DI
DI
DI
DI
DI
O
O
O
O
DI
P
P
P
DI
DI
P
P
P
P
P
P
P
DO
AO
AI
P
P
P
P
P
P
I/O
(1)
DI
AO
AO
TERMINAL FUNCTIONS (continued)
5-V
TOLERANT
TERMINATION
(2) (3)
5-V
5-V
5-V
5-V
5-V
5-V
Pulldown
Pulldown
Pulldown
Pulldown
Pulldown
Pullup
Pullup
DESCRIPTION
High-side bootstrap supply for half-bridge C
High-side bootstrap supply for half-bridge D
Input/output configuration. Connect this terminal directly to GND.
Input/output configuration. Connect this terminal directly to DVDD.
3.3-V Digital power supply
Digital ground
Oscillator ground
Overtemperature, undervoltage, and overcurrent fault reporting.
Active low indicates fault. If high, normal operation.
Digital data format select MSB.
Digital data format select LSB.
Digital data format select.
MSB of gain select.
LSB of gain select. GAIN_0 and GAIN_1 allow 4 possible gain selections.
Analog ground for power stage.
Gate drive voltage for half-bridges A and B (10.8 V to 13.2 V)
Gate drive voltage for half-bridges C and D (10.8 V to 13.2 V)
Input serial audio data left/right clock (sampling rate clock)
Clock master input. The input frequency of this clock can range from
4.9 MHz to 49 MHz.
Performs a soft mute of outputs, active-low. A logic low on this pin sets the outputs equal to 50% duty cycle. A logic high on this pin allows normal operation. The mute control provides a noiseless volume ramp to silence. Releasing mute provides a noiseless ramp to previous volume.
Analog overcurrent programming. Requires 22-k Ω resistor to ground.
Oscillator trim resistor. Connect an 18.2-k Ω (1% tolerance is required) resistor to DVSSO.
Output, half-bridge A
Output, half-bridge B
Output, half-bridge C
Output, half-bridge D
Power down, active-low. PDN stops all clocks, and outputs stop switching whenever a logic low is applied. When PDN is released, the device powers up all logic, starts all clocks, and performs a soft start that returns to the previous configuration changes to FORMATx and
GAINx pins are ignored on PDN cycling.
Power ground for half-bridges A and B
Power ground for half-bridges C and D
PLL negative loop filter terminal
PLL positive loop filter terminal
Power supply input for half-bridge output A (0 V–21 V)
Power supply input for half-bridge output B (0 V–21 V)
Power supply input for half-bridge output C (0 V–21 V)
Power supply input for half-bridge output D(0 V–21 V)
6
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SLOS559 – JUNE 2008
TERMINAL
NAME NO.
RESET 16
SCLK
SDIN1
SDIN2
SUB_PWM–
SUB_PWM+
TEST1
VALID
VDD
VR_ANA
VR_DIG
VREG
VREG_EN
23
25
24
39
40
7
38
6
14
27
43
18
I/O
(1)
DI
DI
DI
DI
DO
DO
DI
DO
P
P
P
P
DI
TERMINAL FUNCTIONS (continued)
5-V
TOLERANT
5-V
TERMINATION
(2) (3)
Pullup
5-V
5-V
5-V
Pulldown
DESCRIPTION
Reset, active-low. A system reset is generated by applying a logic low to this terminal. RESET is an asynchronous control signal that sets the VALID outputs low, and places the PWM in the hard mute state (stop switching). Gain is immediately set to full attenuation.
Upon the release of RESET, if PDN is high, the system performs a
4-ms to 5-ms device initialization and sets the gain and format to the settings determined by the hardware pins.
Serial audio data clock (shift clock). SCLK is the serial audio port input data bit clock.
Serial audio data 1 input is one of the serial data input ports. SDIN1 supports three discrete (stereo) data formats.
Serial audio data 2 input is one of the serial data input ports. SDIN2 supports three discrete (stereo) data formats.
Subwoofer negative PWM output. BD modulated signal.
Subwoofer positive PWM output. BD modulated signal.
Test pin. Connect directly to GND.
Output indicating validity of ALL PWM channels, active-high. This pin is connected to an external power stage. If no external power stage is used, leave this pin floating.
Power supply for VREG (10.8 V to 13.2 V)
Internally regulated 1.8-V analog supply voltage. This terminal must not be used to power external devices.
Internally regulated 1.8-V analog supply voltage. This terminal must not be used to power external devices.
Digital regulator output. Not to be used for powering external circuitry.
Voltage regulator enable. Connect directly to GND.
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted)
(1)
Supply voltage
GVDD, VDD
PVDD
DVDD
AVDD
OUT_X to GND_X
BST_X to GND_X
Input voltage
3.3-V digital input
5-V tolerant
(2) digital input
Input clamp current, I
IK
(V
I
< 0 or V
I
> 1.8 V)
Output clamp current, I
OK
(V
O
< 0 or V
O
> 1.8 V)
Operating free-air temperature
Operating junction temperature range
Storage temperature range, T stg
VALUE
–0.3 to 13.2
–0.3 to 23
–0.3 to 3.6
–0.3 to 3.6
–0.3 to 30
–0.3 to 43.2
–0.5 to DVDD + 0.5
–0.5 to DVDD + 2.5
±20
±20
0 to 85
0 to 150
–40 to 125
UNIT
V
V mA mA
°C
°C
°C
(1) Stresses beyond those listed under absolute ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under recommended operation conditions are not implied. Exposure to absolute-maximum conditions for extended periods may affect device reliability.
(2) 5-V tolerant inputs are PDN, RESET, MUTE, SCLK, LRCLK, MCLK, SDIN1, SDIN2.
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DISSIPATION RATINGS
PACKAGE
(1)
10 × 10 QFP
T
A
≤ 25°C
POWER RATING
5 W
DERATING FACTOR
ABOVE T
A
= 25°C
40 mW/°C
(2)
T
A
= 45°C
POWER RATING
3.2 W
T
A
= 70°C
POWER RATING
2.6 W
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI website at www.ti.com
(2) This data was taken using 1 oz trace and copper pad that is soldered directly to a JEDEC standard high-k PCB. The thermal pad must be soldered to a thermal land on the printed-circuit board. See TI Technical Briefs SLMA002 for more information about using the
HTQFP thermal pad.
RECOMMENDED OPERATING CONDITIONS
over operating free-air temperature range (unless otherwise noted)
V
IH
V
IL
T
A
T
J
R
L
(BTL)
R
L
(SE)
R
L
(PBTL)
L
O
(BTL)
L
O
(SE)
L
O
(PBTL)
Gate drive supply voltage
Output bridge supply voltage
Digita supply voltage
Analog supply voltage
High-level input voltage
Low-level input voltage
Operating ambient temperature range
Operating junction temperature range
Load impedance
Output-filter inductance
GVDD, VDD
PVDD
DVDD
AVDD
3.3-V TTL, 5-V tolerant
3.3-V TTL, 5-V tolerant
Output filter: L = 22
µ
H, C = 680 nF.
Minimum output inductance under short-circuit condition
0
0
6.0
3.2
3.2
MIN NOM MAX
10.8
12 13.2
0
3
3
2
3.3
3.3
21
3.6
3.6
0.8
85
150
10
10
8
4
4
10
UNIT
V
V
V
V
V
V
°C
°C
Ω
µ
H
PWM OPERATION AT RECOMMENDED OPERATING CONDITIONS
PARAMETER
Output sample rate 2×–1× oversampled
TEST CONDITIONS
32–kHz data rate ±2%
44.1-, 88.2-, 176.4-kHz data rate ±2%
48-, 96-, 192-kHz data rate ±2%
MODE
12× sample rate
8×, 4×, and 2× sample rates
8×, 4×, and 2× sample rates
VALUE
384
352.8
384
UNIT
kHz kHz kHz
PLL INPUT PARAMETERS AND EXTERNAL FILTER COMPONENTS
TEST CONDITIONS
f
MCLKI
PARAMETER
Frequency, MCLK (1 / t cyc2
)
MCLK duty cycle
MCLK minimum high time
MCLK minimum low time
≥2-V MCLK = 49.152 MHz, within the min and max duty cycle constraints
≤0.8-V MCLK = 49.152 MHz, within the min and max duty cycle constraints
LRCLK allowable drift before LRCLK reset
External PLL filter capacitor C1
External PLL filter capacitor C2
External PLL filter resistor R
SMD 0603 Y5V
SMD 0603 Y5V
SMD 0603, metal film
MIN TYP
4.9
40% 50%
8
8
47
4.7
470
MAX UNIT
49.2
MHz
60% ns ns
4 MCLKs nF nF
Ω
8
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SLOS559 – JUNE 2008
ELECTRICAL CHARACTERISTICS
DC Characteristics
T
A
= 25 °C, PVCC_X = 18 V, DVDD = AVDD = 3.3 V, R
L
= 8 Ω (unless otherwise noted)
I
I
I
I
V
V
OH
OL
IL
IH
PARAMETER
High-level output voltage 3.3-V TTL and 5-V tolerant
(1)
Low-level output voltage 3.3-V TTL and 5-V tolerant
(1)
Low-level input current
High-level input current
LRCLK, SCLK, SDINx, MCLK,
GAIN_x, VREG_EN,
FORMATx, CONFIG_x
BKND_ERR, RESET, PDN,
MUTE
RESET, PDN, MUTE, GAIN_x,
BKND_ERR
VREG_EN, FORMAT_x,
CONFIG_x, LRCLK, SCLK,
SDINx, MCLK
TEST CONDITIONS
I
OH
= –4 mA
I
OL
= 4 mA
V
V
V
V
I
I
I
I
= 0 V, DVDD = 3.6 V
= 0 V, DVDD = 3.6 V
= 3.6 V, DVDD = 3.6 V
= 3.6 V, DVDD = 3.6 V
I
I
DD
GVDD
RESET, PDN, MUTE, LRCLK,
SCLK, SDINx, MCLK, GAIN_x
V
I
= 5.5 V, DVDD = 3.6 V
Normal mode, 50% duty cycle
Input digital supply current Supply voltage (DVDD, AVDD) Power down (PDN = low)
Reset (RESET = low)
Normal mode, 50% duty cycle
Gate supply current per
GVDD_xx input
RESET = 0
PDN = 0
No load I
PVDD
I
PVDD
(PDN)
Input power supply current
Power-down current
I
PVDD
(RESET) Reset current
Drain-to-source resistance, LS r
DS(on)
Drain-to-source resistance, HS
I/O Protection
T
J
= 25°C, includes metallization resistance
T
J
= 25°C, includes metallization resistance
No load, PDN = 0
No load, RESET = 0
V
V
R
R uvp uvp,hyst
OTE
OTE
OC
OCT
OCP
PD
(2)
HYST
OLPC
(2)
Undervoltage protection limit
Undervoltage protection limit
Overtemperature error
Extra temperature drop required to recover from error
Overload protection counter
Overcurrent limit protection
Overcurrent response time f
PVDD falling
PVDD rising
PWM
R
OCP
= 384 kHz
= 22 k Ω
Resistor tolerance = 5% for
OC programming resistor typical value; the minimum range resistance should not be less than 20 k Ω.
Internal pulldown resistor Connected when RESET is at the output of each active to provide bootstrap half-bridge capacitor charge.
(1) 5-V tolerant inputs are PDN, RESET, MUTE, SCLK, LRCLK, MCLK, SDIN1, SDIN2, GAIN_0, and GAIN_1.
(2) Specified by design.
MIN TYP MAX UNIT
2.4
V
0.5
V
20
65
8
23
5
80
16
33
10 mA
2.2
4 mA
2.2
4
30 60 mA
1 100
µ
A
1 100
µ
A
140
140
9.2
9.6
150
30
1.25
4.5
150
22
3
±2
±50
±2
±50
µ
A
±50
µ
A m Ω
V
V
°C
°C ms
A ns k
Ω k Ω
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AC Characteristics (BTL)
PVDD_X = 18 V, BTL mode, R
L
T
A
= 8 Ω, R
OC
= 22 k Ω, C
BST
= 33-nF, audio frequency = 1 kHz, AES17 filter, F
PWM
= 384 kHz,
= 25°C (unless otherwise noted). All performance is I naccordance with recommended operating conditions, unless otherwise specified.
MIN TYP MAX UNIT
P
V
O
THD+N n
SNR
Output integrated noise
Crosstalk
PARAMETER
Power output per channel
Total harmonic distortion + noise
Signal-to-noise ratio
(1)
TEST CONDITIONS
PVDD = 18 V, 10% THD, 1-kHz input signal
PVDD = 18 V, 7% THD, 1-kHz input signal
PVDD = 12 V, 10% THD, 1-kHz input signal
PVDD = 12 V, 7% THD, 1-kHz input signal
PVDD = 18 V, P
O
= 10 W (half-power)
PVDD = 12 V, P
O
= 4.5 W (half-power)
1 W
A-weighted
P
O
= 1 W, f = 1 kHz
A-weighted, f = 1 kHz, maximum power at
THD < 1%
P
O
= 0 W, 4 channels switching
(2)
P
D
Power dissipation due to idle losses (I
PVDD_X
)
(1) SNR is calculated relative to 0-dBFS input level.
(2) Actual system idle losses are affected by core losses of output inductors.
20.0
18.6
9
8.3
0.1%
0.08%
0.05%
50
–73
101
0.6
W
µ
V dB dB
W
10
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SLOS559 – JUNE 2008
SERIAL AUDIO PORTS SLAVE MODE
Serial audio ports slave mode over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST
CONDITIONS
C
L
= 30 pF
MIN
f
SCLKIN t su1 t h1 t su2 t h2
Frequency, SCLK 32 × f
S
, 48 × f
S
, 64 × f
S
Setup time, LRCLK to SCLK rising edge
Hold time, LRCLK from SCLK rising edge
Setup time, SDIN to SCLK rising edge
Hold time, SDIN from SCLK rising edge
LRCLK frequency
SCLK duty cycle
LRCLK duty cycle
1.024
10
10
10
10
32
40%
40%
SCLK rising edges between LRCLK rising edges 32 t
(edge)
LRCLK clock edge with respect to the falling edge of SCLK –1/4
TYP MAX
12.288
48
50%
50%
192
60%
60%
64
1/4
UNIT
MHz ns ns ns ns kHz
SCLK edges
SCLK period
SCLK
(Input) t
(edge) t h1 t su1
LRCLK
(Input) t su2 t h2
SDIN
T0026-03
Figure 2. Slave Mode Serial Data Interface Timing
HARDWARE SELECT PINS
over recommended operating conditions (unless otherwise noted) t su
PARAMETER
Setup time, FORMATx, CONFIG_x, GAIN_x to RESET rising edge
MIN TYP MAX UNIT
100
µ s t su
FORMATx,
CONFIG_x,
GAIN_x,
RESET
Figure 3. Mode Pins Setup Time
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RESET TIMING (RESET) AND POWER-ON RESET
Control signal parameters over recommended operating conditions (unless otherwise noted) t d(VALID_LOW) t w(RESET) t d(START)
PARAMETER
Time to assert VALID (reset to power stage) low
Pulse duration, RESET active
Time to start-up
MIN TYP MAX UNIT
100 ns
100 200
3.6
ms ms
RESET
Earliest time that hard mute could be exited t w(RESET)
VALID t d(VALID_LOW) t d(START)
Start system
T0029-05
Figure 4. Reset Timing
When power is applied to DVDD, RESET must be held low for at least 100
µ s after DVDD reaches 3.0 V.
3.6 V
3.0 V
DVDD
0 V
RESET
100 m s
Figure 5. Power-On Reset Timing
POWER-DOWN (PDN) TIMING
Control signal parameters over recommended operating conditions (unless otherwise noted) t d(VALID_LOW) t d(STARTUP) t w
PARAMETER
Time to assert VALID (reset to power stage) low
Device start-up time
Minimum pulse duration required
MIN
1
TYP MAX UNIT
725
650
µ s
µ s
µ s
PDN t w
VALID t d(VALID_LOW) t d(STARTUP)
Figure 6. Power-Down Timing
T0030-04
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BACK-END ERROR (BKND_ERR)
Control signal parameters over recommended operating conditions (unless otherwise noted) t w(ER) t p(valid_high) t p(valid_low)
PARAMETER
Pulse duration, BKND_ERR active (active-low)
Time to stay in the OUT_x low state. After t p(valid_high)
, the TAS5701 attempts to bring the system out of the OUT_x low state if BKND_ERR is high.
Time TAS5701 takes to bring OUT_x low after BKND_ERR assertion.
t w(ER)
MIN
350
TYP MAX UNIT
ns
300 ms
350 ns
BKND_ERR
VALID
Normal
Operation
Normal
Operation t p(valid_high) t p(valid_low)
Figure 7. Error Recovery Timing
T0031-04
MUTE TIMING (MUTE)
Control signal parameters over recommended operating conditions (unless otherwise noted) t d(VOL)
PARAMETER
Volume ramp time. Ramp time = Number of steps × stepsize
(1)
MIN TYP
1024
MAX UNIT
steps
(1) Stepsize = 4 LRCLKs (for 32–48 kHz sample rate); 8 LRCLKs (for 88.2–96 kHz sample rate); 16 LRCLKs (for 176.4–192 kHz sample rate)
MUTE
VOLUME
Normal
Operation
Normal
Operation t d(VOL)
50-50
Duty Cycle
Figure 8. Mute Timing
t d(VOL)
T0032-03
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TYPICAL CHARACTERISTICS, BTL CONFIGURATION
TOTAL HARMONIC DISTORTION + NOISE vs
OUTPUT POWER
TOTAL HARMONIC DISTORTION + NOISE vs
OUTPUT POWER
10 10
PVDD = 18 V
8 W
PVDD = 18 V
W
1
1
0.1
1 kHz
10 kHz
0.1
1 kHz
10 kHz
0.01
20 Hz
0.001
0.01
0.1
1
P
O
- Output Power - W
10
Figure 9.
TOTAL HARMONIC DISTORTION + NOISE vs
FREQUENCY
10
PVDD = 18 V
R
L
= 8
Ω
100
1
P = 5 W
0.1
0.01
20 Hz
0.001
0.01
0.1
1
P
O
- Output Power - W
10
Figure 10.
TOTAL HARMONIC DISTORTION + NOISE vs
FREQUENCY
10
PVDD = 18 V
R
L
= 6
Ω
1
100
P = 5 W
0.1
0.01
0.001
20
P = 2.5 W
100
P = 0.5 W
1k f − Frequency − Hz
Figure 11.
0.01
10k 20k
G001
0.001
20
P = 0.5 W
P = 2.5 W
100 1k f − Frequency − Hz
Figure 12.
10k 20k
G002
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TYPICAL CHARACTERISTICS, BTL CONFIGURATION (continued)
SYSTEM EFFICIENCY vs
OUTPUT POWER
100
90
80
70
60
50
40
30
20
10
0
0
R
L
= 8
Ω
R
L
= 6
Ω
PVDD = 18 V
4 8 12 16
P
O
− Output Power (Per Channel) − W
Figure 13.
OUTPUT POWER vs
SUPPLY VOLTAGE
40
35
R
L
= 8
Ω
20
G005
30
25
20
15
THD+N = 10%
10
5
THD+N = 1%
0
10 11 12 13 14 15 16 17 18 19 20 21
PVDD − Supply Voltage − V
G007
Figure 15.
3.0
2.5
2.0
1.5
1.0
0.5
PVDD = 18 V
SUPPLY CURRENT vs
OUTPUT POWER
R
L
= 6
Ω
R
L
= 8
Ω
0.0
0
40
35
R
L
= 6
Ω
10 20 30
P
O
− Output Power − W
Figure 14.
OUTPUT POWER vs
SUPPLY VOLTAGE
40
30
50
G006
25
20
15
THD+N = 10%
THD+N = 1%
10
5
0
10 11 12 13 14 15 16 17 18 19 20 21
PVDD − Supply Voltage − V
G008
Figure 16.
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TYPICAL CHARACTERISTICS, BTL CONFIGURATION (continued)
−80
−90
−100
−40
−50
PVDD = 18 V
R
L
= 8
Ω
−60
CROSSTALK vs
FREQUENCY
−70
Left to Right
Right to Left
−110
−120
20 100 1k f − Frequency − Hz
Figure 17.
DETAILED DESCRIPTION
10k 20k
G010
POWER SUPPLY
The digital portion of the chip requires 3.3 V, and the analog portion can work with a variable range up to 12 V.
PVDD has a maximum operational range up to 22 V.
To facilitate system design, the TAS5701 needs only a 12-V supply in addition to the (typical) 18-V power-stage supply. An internal voltage regulator provides suitable voltage levels for the digital and low-voltage analog circuitry. Additionally, all circuitry requiring a floating voltage supply, e.g., the high-side gate drive, is accommodated by built-in bootstrap circuitry requiring only a few external capacitors.
In order to provide outstanding electrical and acoustical characteristics, the PWM signal path including gate drive and output stage is designed as identical, independent half-bridges. For this reason, each half-bridge has separate gate drive supply (GVDD_X), bootstrap pins (BST_X), and power-stage supply pins (PVDD_X). Special attention should be paid to placing all decoupling capacitors as close to their associated pins as possible. In general, inductance between the power supply pins and decoupling capacitors must be avoided.
For a properly functioning bootstrap circuit, a small ceramic capacitor must be connected from each bootstrap pin
(BST_X) to the power-stage output pin (OUT_X). When the power-stage output is low, the bootstrap capacitor is charged through an internal diode connected between the gate-drive power-supply pin (GVDD_X) and the bootstrap pin. When the power-stage output is high, the bootstrap capacitor potential is shifted above the output potential and thus provides a suitable voltage supply for the high-side gate driver. In an application with PWM switching frequencies in the range from 352 kHz to 384 kHz, it is recommended to use 33-nF ceramic capacitors, size 0603 or 0805, for the bootstrap supply. These 33-nF capacitors ensure sufficient energy storage, even during minimal PWM duty cycles, to keep the high-side power stage FET (LDMOS) fully turned on during the remaining part of the PWM cycle. In an application running at a reduced switching frequency, generally 192 kHz, the bootstrap capacitor might need to be increased in value.
Special attention should be paid to the power-stage power supply; this includes component selection, PCB placement, and routing. As indicated, each half-bridge has independent power-stage supply pins (PVDD_X). For optimal electrical performance, EMI compliance, and system reliability, it is important that each PVDD_X pin is decoupled with a 100-nF ceramic capacitor placed as close as possible to each supply pin.
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The 12-V supply should be from a low-noise, low-output-impedance voltage regulator. Likewise, the 18-V power-stage supply is assumed to have low output impedance and low noise. The power-supply sequence is not critical as facilitated by the internal power-on-reset circuit. Moreover, the TAS5701 is fully protected against erroneous power-stage turnon due to parasitic gate charging.
Clock, Auto Detection, and PLL
The TAS5701 digital audio processor (DAP) is a clock slave device. It accepts MCLK, SCLK, and LRCLK.
The TAS5701 checks to verify that SCLK is a specific value of 32-f s
, 48- f s
, or 64-f s
. The DAP only supports a 1 × f s
LRCLK. The timing relationship of these clocks to SDIN1and SIN2 is shown in subsequent sections. The clock section uses MCLK or the internal oscillator clock (when MCLK is unstable or absent) to produce the internal clock.
The DAP can auto-detect and set the internal clock control logic to the appropriate settings for the frequencies of
32 kHz, normal speed (44.1 or 48 kHz), double speed (88.2 kHz or 96 kHz), and quad speed (176.4 kHz or 192 kHz).
SERIAL DATA INTERFACE
Serial data is input on SDIN1 and SIN2. The PWM outputs are derived from SDIN1 ands SIN2. The TAS5701
DAP accepts 32-, 44.1-, 48-, 88.2-, 96-, 176.4-, and 192-kHz serial data in 16-, 18-, 20-, or 24-bit data in left-justified, right-justified, and I
2
S serial data formats. See
for format control settings.
SDIN1 left channel data is sent to OUTA/OUTB configured in BTL. SDIN1 right channel data is sent to
OUTC/OUTD. SDIN2 left channel data is sent to SUB_PWM+/–. The right channel data of SDIN2 is ignored.
PWM SECTION
The DAP (digital audio processor) has three channels of high-performance digital PWM modulators that are designed to drive bride-tied output H-bridge configurations with BD modulation.
The DAP uses noise-shaping and sophisticated error correction algorithms to achieve high power efficiency and high-performance digital audio reproduction. The DAP uses a fourth-order noise shaper to provide >100-dB SNR performance from 20 Hz to 20 kHz.
The PWM section accepts 24-bit PCM data from the DAP and outputs three PWM audio output channels. The
PWM section output supports bridge-tied loads ONLY.
The PWM section has individual channel dc blocking filters that are ALWAYS enabled. The filter cutoff frequency is less than 1 Hz.
Finally, the PWM section has a fixed maximum modulation limit of 97.7%.
SERIAL INTERFACE CONTROL AND TIMING
I
2
S Timing
I
2
S timing uses LRCLK to define when the data being transmitted is for the left channel and when it is for the right channel. LRCLK is low for the left channel and high for the right channel. A system clock (SCLK) running at
32, 48, or 64 × f s is used to clock in the data. There is a delay of one bit clock from the time the LRCLK signal changes state to the first bit of data on the data lines. The data is written MSB first and is valid on the rising edge of the bit clock. The DAP masks unused trailing data bit positions.
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1/f
S
LRCK
SCLK
(= 32 f
S
, 48 f
S
or 64 f
S
)
L-Channel R-Channel
DATA
N−1 N−2 N−3
MSB
2 1 0
N–1 N–2 N–3
LSB MSB
Figure 18. I
2
S Format
2 1 0
LSB
N−1 N−2
Left-Justified
Left-justified (LJ) timing uses LRCLK to define when the data being transmitted is for the left channel and when it is for the right channel. LRCLK is high for the left channel and low for the right channel. A bit clock running at 32,
48, or 64 × f s is used to clock in the data. The first bit of data appears on the data lines at the same time LRCLK toggles. The data is written MSB first and is valid on the rising edge of the bit clock. The DAP masks unused trailing data bit positions.
1/f
S
LRCK L-Channel R-Channel
SLCK
(= 32 f
S
, 48 f
S,
or 64 f
S
)
DATA
N−1 N−2 N−3
MSB
2 1 0
N−1 N−2 N−3
LSB MSB
Figure 19. Left-Justified Format
2 1 0
LSB
N–1
N–2
Right-Justified
Right-justified (RJ) timing uses LRCLK to define when the data being transmitted is for the left channel and when it is for the right channel. LRCLK is high for the left channel and low for the right channel. A bit clock running at
32, 48, or 64 × f s is used to clock in the data. The first bit of data appears on the data 8 bit-clock periods (for
24-bit data) after LRCLK toggles. In RJ mode the LSB of data is always clocked by the last bit clock before
LRCLK transitions. The data is written MSB first and is valid on the rising edge of the bit clock. The DAP masks unused leading data bit positions.
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1/f
S
LRCK L-Channel
SCLK
(= 32 f
S
, 48 f
S,
or 64 f
S
)
16-Bit Right-Justified, SCLK = 48 f
S
or 64 f
S
DATA 2 1 0 15 14 13
MSB
16-Bit Right-Justified, SCLK = 32 f
S
DATA 2 1 0 15 14 13
MSB
18-Bit Right-Justified, SCLK = 48 f
S
or 64 f
S
DATA 2 1 0 17 16 15
MSB
20-Bit Right-Justified, SCLK = 48 f
S
or 64 f
S
DATA 2 1 0 19 18 17
MSB
24-Bit Right-Justified, SCLK = 48 f
S
DATA 2 1 0 23 22 21
24-Bit Right-Justified, SCLK = 64 f
S
DATA 2 1 0
MSB
23 22 21
MSB
2 1 0
LSB
2 1 0 15 14 13
LSB MSB
2 1 0
LSB
2 1 0
LSB
2 1 0 23 22 21
LSB MSB
2 1 0
LSB
19 18 17
MSB
Figure 20. Right-Justified Format
R-Channel
15 14 13
MSB
17 16 15
MSB
23 22 21
MSB
2 1 0
LSB
2 1 0
LSB
2 1 0
LSB
2 1 0
LSB
2 1 0
LSB
2 1 0
LSB
Format Control
The digital data input format is selected via three external terminals (FORMAT0, FORMAT1, and FORMAT2).
lists the corresponding data format for SDIN1 and SDIN2. LRCLK and SCLK are shared clocks for
SDIN1 and SDIN2. Changes to the FORMATx terminals are latched in immediately on a rising edge of RESET.
Changes to the FORMATx terminals while RESET is high are not allowed.
FORMAT2
0
0
0
0
1
1
1
1
Table 1. Format Control
FORMAT1
0
0
1
1
0
0
1
1
FORMAT0
0
1
0
1
0
1
0
1
SERIAL DIGITAL DATA
FORMAT
16-Bit right-justifed
18-Bit right-justified
20-Bit right-justified
24-Bit right-justified
16-, 24-Bit I
2
S
16-, 24-Bit left-justified
Reserved. Setting is not allowed.
Reserved. Setting is not allowed.
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Gain Control
The gain of the DAP is selected via two external gain pins (GAIN_0 and GAIN_1).
lists the corresponding channel gain (for ALL channels) for GAIN_0 and GAIN_1 settings. Individual channel gain is not possible.
Changes to the GAIN_x terminals are latched in immediately on a rising edge of RESET. Changes to the
GAIN_x terminals while RESET is high are not allowed.
GAIN_1
0
0
1
1
Table 2. Gain Control
GAIN_0
0
1
0
1
CHANNEL GAIN (dB)
0
6
12
18
DEVICE PROTECTION SYSTEM
The TAS5701 contains advanced protection circuitry carefully designed to facilitate system integration and ease of use, as well as to safeguard the device from permanent failure due to a wide range of fault conditions such as short circuits, overtemperature, and undervoltage. The TAS5701 responds to a fault by immediately setting the power stage in a high-impedance (Hi-Z) state and reporting the error on the FAULT pin (FAULT = 0); the device automatically recovers when the fault condition has been removed.
Short-Circuit Protection
The device has independent, fast-reacting current detectors on all high-side and low-side power-stage FETs. The detector outputs are closely monitored by a protection system. If a high-current condition situation exists, i.e., the power stage outputs are shorted, the protection system triggers a latching shutdown, resulting in the power stage being set in the high-impedance (Hi-Z) state and FAULT going low. Overcurrent protection is not independent for half-bridges A and B and, respectively, C and D. That is, if the bridge-tied load between half-bridges A and B causes an overcurrent fault, half-bridges A, B, C, and D are shut down.
Overtemperature Protection
If the device junction temperature exceeds 150°C (nominal), the device is put into thermal shutdown, resulting in all half-bridge outputs being set in the high-impedance (Hi-Z) state and FAULT going low. Once the temperature decreases 30°C (typical), the device resumes normal operation.
Undervoltage Protection (UVP) and Power-On Reset (POR)
The UVP and POR circuits of the TAS5701 fully protect the device in any power-up/down and brownout situation.
While powering up, the POR circuit resets the protection circuitry and ensures that all circuits are fully operational when the VDD and GVDD_X supply voltages reach 9.6 V (typical). Although GVDD_x and VDD pins are independently monitored, a supply voltage drop below the UVP threshold on any VDD or GVDD_x pin results in all outputs immediately being set in the high-impedence (Hi-Z) state and FAULT pin being asserted low. The device automatically resumes operation when all supply voltages have increased above the UVP threshold.
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PACKAGE OPTION ADDENDUM
11-Jul-2008
PACKAGING INFORMATION
Orderable Device
TAS5701PAP
TAS5701PAPG4
TAS5701PAPR
TAS5701PAPRG4
Status
(1)
ACTIVE
ACTIVE
ACTIVE
ACTIVE
Package
Type
HTQFP
HTQFP
HTQFP
HTQFP
Package
Drawing
PAP
PAP
PAP
PAP
Eco Plan
(2)
Pins Package
Qty
64 160 Green (RoHS & no Sb/Br)
Lead/Ball Finish MSL Peak Temp
(3)
CU NIPDAU Level-3-260C-168 HR
64 CU NIPDAU Level-3-260C-168 HR
64
160 Green (RoHS & no Sb/Br)
1000 Green (RoHS & no Sb/Br)
CU NIPDAU Level-3-260C-168 HR
64 1000 Green (RoHS & no Sb/Br)
CU NIPDAU Level-3-260C-168 HR
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
www.ti.com
TAPE AND REEL INFORMATION
PACKAGE MATERIALS INFORMATION
24-Jul-2008
*All dimensions are nominal
Device
TAS5701PAPR
Package
Type
Package
Drawing
HTQFP PAP
Pins
64
SPQ
1000
Reel
Diameter
(mm)
Reel
Width
W1 (mm)
330.0
24.4
A0 (mm)
13.0
B0 (mm)
13.0
K0 (mm) P1
(mm)
W
(mm)
Pin1
Quadrant
1.4
16.0
24.0
Q2
Pack Materials-Page 1
www.ti.com
PACKAGE MATERIALS INFORMATION
24-Jul-2008
*All dimensions are nominal
Device
TAS5701PAPR
Package Type Package Drawing Pins
HTQFP PAP 64
SPQ
1000
Length (mm) Width (mm) Height (mm)
346.0
346.0
41.0
Pack Materials-Page 2
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Table of contents
- 1 FEATURES
- 1 DESCRIPTION
- 2 SIMPLIFIED APPLICATION DIAGRAM
- 3 FUNCTIONAL BLOCK DIAGRAM
- 5 64-PIN, HTQFP PACKAGE (TOP VIEW)
- 7 ABSOLUTE MAXIMUM RATINGS
- 8 DISSIPATION RATINGS
- 8 RECOMMENDED OPERATING CONDITIONS
- 8 PWM OPERATION AT RECOMMENDED OPERATING CONDITIONS
- 8 PLL INPUT PARAMETERS AND EXTERNAL FILTER COMPONENTS
- 9 ELECTRICAL CHARACTERISTICS
- 9 DC Characteristics
- 10 AC Characteristics (BTL)
- 11 SERIAL AUDIO PORTS SLAVE MODE
- 11 HARDWARE SELECT PINS
- 12 RESET TIMING (RESET) AND POWER-ON RESET
- 12 POWER-DOWN (PDN) TIMING
- 13 BACK-END ERROR (BKND_ERR)
- 13 MUTE TIMING (MUTE)
- 14 TYPICAL CHARACTERISTICS, BTL CONFIGURATION
- 16 DETAILED DESCRIPTION
- 16 POWER SUPPLY
- 17 SERIAL DATA INTERFACE
- 17 PWM SECTION
- 17 SERIAL INTERFACE CONTROL AND TIMING
- 17 I2S Timing
- 18 Left-Justified
- 18 Right-Justified
- 19 Format Control
- 20 Gain Control
- 20 DEVICE PROTECTION SYSTEM
- 20 Short-Circuit Protection
- 20 Overtemperature Protection
- 20 Undervoltage Protection (UVP) and Power-On Reset (POR)