THS3092

THS3092
THS3096
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SLOS428B – DECEMBER 2003 – REVISED FEBRUARY 2006
HIGH-VOLTAGE, LOW-DISTORTION, CURRENT-FEEDBACK
OPERATIONAL AMPLIFIERS
FEATURES
•
•
•
•
•
•
•
DESCRIPTION
Low Distortion
– 66 dBc HD2 at 10 MHz, RL = 100 Ω
– 76 dBc HD3 at 10 MHz, RL = 100 Ω
Low Noise
– 13 pA/√Hz Noninverting Current Noise
– 13 pA/√Hz Inverting Current Noise
– 2 nV/√Hz Voltage Noise
High Slew Rate: 5700 V/µs (G = 5, VO = 20 VPP)
Wide Bandwidth: 160 MHz (G = 5, RL = 100 Ω)
High Output Current Drive: ±250 mA
Wide Supply Range: ±5 V to ±15 V
Power-Down Feature: (THS3096 Only)
APPLICATIONS
•
•
•
•
High-Voltage Arbitrary Waveform
Power FET Driver
Pin Driver
VDSL Line Driver
Total Harmonic Distortion − dBc
−30
−40
G = 5,
RF = 715 Ω,
RL = 100 Ω,
VS = ±15 V
−50
The THS3096 features a power-down pin (PD) that
puts the amplifier in low power standby mode, and
lowers the quiescent current from 9.5 mA to 500 µA.
The wide supply range combined with total harmonic
distortion as low as -66 dBc at 10 MHz, in addition, to
the high slew rate of 5700 V/µs makes the
THS3092/6 ideally suited for high-voltage arbitrary
waveform driver applications. Moreover, having the
ability to handle large voltage swings driving into
high-resistance and high-capacitance loads while
maintaining good settling time performance makes
the THS3092/6 ideal for Pin driver and PowerFET
driver applications.
The THS3092 is offered in an 8-pin SOIC (D), and
the 8-pin SOIC (DDA) packages with PowerPAD™.
The THS3096 is offered in the 8-pin SOIC (D) and
the 14-pin TSSOP (PWP) packages with PowerPAD.
TYPICAL ARBITARY WAVEFORM
GENERATOR OUTPUT DRIVE CIRCUIT
TOTAL HARMONIC DISTORTION
vs
FREQUENCY
−20
The THS3092 and THS3096 are dual high-voltage,
low-distortion,
high
speed,
current-feedback
amplifiers designed to operate over a wide supply
range of ±5 V to ±15 V for applications requiring
large, linear output signals such as Pin, Power FET,
and VDSL line drivers.
VO = 20 VPP
VOUT
IOUT1
DAC5686
IOUT2
VO = 10 VPP
−
+
−
+
THS3092
THS4271
−60
−70
VO = 5 VPP
−
+
−80
VO = 2 VPP
−90
100 k
1M
10 M
THS3092
100 M
f − Frequency − Hz
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PowerPAD is a trademark of Texas Instruments.
UNLESS OTHERWISE NOTED this document contains
PRODUCTION DATA information current as of publication date.
Products conform to specifications per the terms of Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2003–2006, Texas Instruments Incorporated
THS3092
THS3096
www.ti.com
SLOS428B – DECEMBER 2003 – REVISED FEBRUARY 2006
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
TOP VIEW
D, DDA
TOP VIEW
D, PWP
THS3096
THS3092
1VOUT
1VIN −
1VIN +
VS−
1
8
2
7
3
6
4
5
1VOUT
1VIN−
1VIN+
VS−
NC
REF
NC
VS+
2VOUT
2VIN−
2VIN+
NC = No Internal Connection
1
14
2
13
3
12
4
11
5
10
6
9
7
8
VS+
2VOUT
2VIN−
2VIN+
NC
PD
NC
NC = No Internal Connection
See Note A.
Note A: The devices with the power down option defaults to the ON state if no signal is applied to the PD pin. Additionallly, the REF pin
functional range is from VS− to (VS+ − 4 V).
ORDERING INFORMATION
PART NUMBER
THS3092D
PACKAGE TYPE
SOIC-8
THS3092DR
THS3092DDA
SOIC-8-PP (1)
THS3092DDAR
TRANSPORT MEDIA, QUANTITY
Rails, 75
Tape and Reel, 2500
Rails, 75
Tape and Reel, 2500
Power-down
THS3096D
SOIC-8
THS3096DR
THS3096PWP
TSSOP-14-PP (1)
THS3096PWPR
(1)
Rails, 75
Tape and Reel, 2500
Rails, 90
Tape and Reel, 2000
The PowerPAD is electrically isolated from all other pins.
DISSIPATION RATING TABLE
(1)
(2)
(3)
2
POWER RATING (2)
PACKAGE
ΘJC (°C/W)
ΘJA (°C/W) (1)
TA≤ 25°C
TA = 85°C
D-8
38.3
97.5
1.02 W
410 mW
DDA-8 (3)
9.2
45.8
2.18 W
873 mW
PWP-14 (3)
2.07
37.5
2.67 W
1.07 W
This data was taken using the JEDEC standard High-K test PCB.
Power rating is determined with a junction temperature of 125°C. This is the point where distortion starts to substantially increase.
Thermal management of the final PCB should strive to keep the junction temperature at or below 125°C for best performance and long
term reliability.
The THS3092 and THS3096 may incorporate a PowerPAD™ on the underside of the chip. This acts as a heatsink and must be
connected to a thermally dissipating plane for proper power dissipation. Failure to do so may result in exceeding the maximum junction
temperature which could permanently damage the device. See TI Technical Brief SLMA002 for more information about utilizing the
PowerPAD™ thermally enhanced package.
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THS3096
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SLOS428B – DECEMBER 2003 – REVISED FEBRUARY 2006
RECOMMENDED OPERATING CONDITIONS
Supply voltage
MIN
MAX
Dual supply
±5
±15
Single supply
10
30
-40
85
Operating free-air temperature, TA
UNIT
V
°C
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature (unless otherwise noted) (1)
UNIT
Supply voltage, VS- to VS+
33 V
Input voltage, VI
± VS
Differential input voltage, VID
±4V
Output current, IO
350 mA
Continuous power dissipation
See Dissipation Ratings Table
Maximum junction temperature, TJ
150°C
Maximum junction temperature, continuous operation, long term reliability, TJ (2)
125°C
Storage temperature, Tstg
-65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds
300°C
ESD ratings:
(1)
(2)
HBM
2000
CDM
1500
MM
150
The absolute maximum ratings under any condition is limited by the constraints of the silicon process. Stresses above these ratings may
cause permanent damage. Exposure to absolute maximum conditions for extended periods may degrade device reliability. These are
stress ratings only, and functional operation of the device at these or any other conditions beyond those specified is not implied.
The maximum junction temperature for continuous operation is limited by package constraints. Operation above this temperature may
result in reduced reliability and/or lifetime of the device.
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THS3096
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SLOS428B – DECEMBER 2003 – REVISED FEBRUARY 2006
ELECTRICAL CHARACTERISTICS
VS = ±15 V, RF = 909 Ω, RL = 100 Ω, and G = 2 (unless otherwise noted)
TYP
PARAMETER
TEST CONDITIONS
25°C
OVER TEMPERATURE
25°C
0°C to
70°C
-40°C to
85°C
UNIT
MIN/TYP/
MAX
MHz
TYP
V/µs
TYP
ns
TYP
ns
TYP
dBc
TYP
AC PERFORMANCE
Small-signal bandwidth, -3 dB
G = 1, RF = 1.1 kΩ, VO = 200 mVPP
135
G = 2, RF = 909 Ω, VO = 200 mVPP
145
G = 5, RF = 715 Ω, VO = 200 mVPP
160
G = 10, RF = 604 Ω, VO = 200 mVPP
145
0.1 dB bandwidth flatness
G = 2, RF = 909 Ω, VO = 200 mVPP
50
Large-signal bandwidth
G = 5, RF = 715 Ω , VO = 5 VPP
150
G = 2, VO = 10-V step, RF = 909 Ω
4000
G = 5, VO = 20-V step, RF = 715 Ω
5700
Slew rate (25% to 75% level)
Rise and fall time
G = 2, VO = 5-VPP, RF = 909 Ω
5
Settling time to 0.1%
G = -2, VO = 2 VPP step
42
Settling time to 0.01%
G = -2, VO = 2 VPP step
72
Harmonic distortion
2nd Harmonic distortion
RL = 100Ω
66
RL = 1 kΩ
66
RL = 100Ω
76
RL = 1 kΩ
78
3rd Harmonic distortion
G = 2,
RF = 909 Ω ,
VO = 2 VPP,
f = 10 MHz
Input voltage noise
f > 10 kHz
2
nV / √Hz
TYP
Noninverting input current noise
f > 10 kHz
13
pA / √Hz
TYP
Inverting input current noise
f > 10 kHz
13
pA / √Hz
TYP
Differential gain
Differential phase
Crosstalk
G = 2,
RL = 150 Ω,
RF = 909 Ω
G = 2,
RL = 100 Ω,
f = 10 MHz
NTSC
0.013%
PAL
0.011%
NTSC
0.020°
PAL
0.026°
Ch 1 to 2
60
Ch 2 to 1
56
TYP
dB
DC PERFORMANCE
Transimpedance
VO = ±7.5 V, Gain = 1
Input offset voltage
850
350
300
300
kΩ
MIN
0.9
3
4
4
mV
MAX
±10
±10
µV/°C
TYP
4
15
20
20
µA
MAX
±20
±20
µA/°C
TYP
3.5
15
20
20
µA
MAX
±20
±20
µA/°C
TYP
1.7
10
15
15
µA
MAX
±20
±20
µA/°C
TYP
V
MIN
Average offset voltage drift
Noninverting input bias current
Average bias current drift
Inverting input bias current
VCM = 0 V
Average bias current drift
Input offset current
Average offset current drift
INPUT CHARACTERISTICS
Common-mode input range
Common-mode rejection ratio
±13.3
±13
±13
78
68
65
65
dB
MIN
Noninverting input resistance
1.3
MΩ
TYP
Noninverting input capacitance
0.1
pF
TYP
Inverting input resistance
30
Ω
TYP
Inverting input capacitance
1.4
pF
TYP
4
VCM = ±10 V
±13.6
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THS3096
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SLOS428B – DECEMBER 2003 – REVISED FEBRUARY 2006
ELECTRICAL CHARACTERISTICS (continued)
VS = ±15 V, RF = 909 Ω, RL = 100 Ω, and G = 2 (unless otherwise noted)
TYP
PARAMETER
TEST CONDITIONS
OVER TEMPERATURE
25°C
25°C
0°C to
70°C
-40°C to
85°C
UNIT
MIN/TYP/
MAX
RL = 1 kΩ
±13.2
±12.8
±12.5
±12.5
RL = 100 Ω
±12.5
±12.1
±11.8
±11.8
V
MIN
Output current (sourcing)
RL = 40 Ω
280
225
200
Output current (sinking)
RL = 40 Ω
250
200
175
200
mA
MIN
175
mA
Output impedance
f = 1 MHz, Closed loop
0.06
MIN
Ω
TYP
OUTPUT CHARACTERISTICS
Output voltage swing
POWER SUPPLY
Specified operating voltage
±15
±16
±16
±16
V
MAX
Maximum quiescent current
9.5
10.5
11
11
mA
MAX
9.5
8.5
8
8
mA
MIN
Minimum quiescent current
Per channel
Power supply rejection (+PSRR)
VS+ = 15.5 V to 14.5 V, VS- = 15 V
75
70
65
65
dB
MIN
Power supply rejection (-PSRR)
VS+ = 15 V, VS- = -15.5 V to -14.5 V
73
68
65
65
dB
MIN
POWER-DOWN CHARACTERISTICS (THS3096 ONLY)
VS+– 4
REF voltage range (1)
Power-down voltage level (1)
Power-down quiescent current
VPD quiescent current
V
Enable
PD ≥ REF + 2
Disable
PD ≤ REF + 0.8
PD = 0V
500
700
800
800
VPD = 0 V, REF = 0 V,
11
15
20
20
VPD = 3.3 V, REF = 0 V
11
15
20
20
Turnon time delay
90% of final value
60
Turnoff time delay
10% of final value
150
(1)
MAX
VS–
MIN
MIN
MAX
µA
MAX
µA
MAX
µs
TYP
For detailed information on th behavior of the powerdown circuit, see the Powerdown and Powerdown Reference sections in the
Application Information of this data sheet.
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THS3096
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SLOS428B – DECEMBER 2003 – REVISED FEBRUARY 2006
ELECTRICAL CHARACTERISTICS
VS = ±5 V, RF = 909 Ω, RL = 100 Ω, and G = 2 (unless otherwise noted)
TYP
PARAMETER
TEST CONDITIONS
25°C
OVER TEMPERATURE
25°C
0°C to
70°C
-40°C to
85°C
UNIT
MIN/TYP/
MAX
MHz
TYP
V/µs
TYP
ns
TYP
ns
TYP
dBc
TYP
AC PERFORMANCE
Small-signal bandwidth, -3 dB
G = 1, RF = 1.1 kΩ, VO = 200 mVPP
125
G = 2, RF = 909 Ω, VO = 200 mVPP
140
G = 5, RF = 715 Ω, VO = 200 mVPP
145
G = 10, RF = 604 Ω, VO = 200 mVPP
135
0.1 dB bandwidth flatness
G = 2, RF = 909 Ω, VO = 200 mVPP
42
Large-signal bandwidth
G = 2, RF = 909 Ω , VO = 5 VPP
125
G = 2, VO= 5-V step, RF = 909 Ω
1050
G = 5, VO= 5-V step, RF = 715 Ω
1350
Slew rate (25% to 75% level)
Rise and fall time
G = 2, VO = 5-V step, RF = 909 Ω
5
Settling time to 0.1%
G = -2, VO = 2 VPP step
35
Settling time to 0.01%
G = -2, VO = 2 VPP step
73
Harmonic distortion
2nd Harmonic distortion
RL = 100Ω
64
RL = 1 kΩ
67
RL = 100Ω
75
RL = 1 kΩ
75
3rd Harmonic distortion
G = 2,
RF = 909 Ω ,
VO = 2 VPP,
f = 10 MHz
Input voltage noise
f > 10 kHz
2
nV / √Hz
TYP
Noninverting input current noise
f > 10 kHz
13
pA / √Hz
TYP
Inverting input current noise
f > 10 kHz
13
pA / √Hz
TYP
Differential gain
Differential phase
Crosstalk
G = 2,
RL = 150 Ω,
RF = 909 Ω
G = 2,
RL = 100 Ω,
f = 10 kHz
NTSC
0.027%
PAL
0.025%
NTSC
0.04°
PAL
0.05°
Ch 1 to 2
60
Ch 2 to 1
56
TYP
dB
DC PERFORMANCE
Transimpedance
VO = ±2.5 V, Gain = 1
Input offset voltage
700
250
200
200
kΩ
MIN
0.3
2
3
3
mV
MAX
±10
±10
µV/°C
TYP
2
15
20
20
µA
MAX
±20
±20
µA/°C
TYP
5
15
20
20
µA
MAX
±20
±20
µA/°C
TYP
1
10
15
15
µA
MAX
±20
±20
µA/°C
TYP
V
MIN
Average offset voltage drift
Noninverting input bias current
Average bias current drift
Inverting input bias current
VCM = 0 V
Average bias current drift
Input offset current
Average offset current drift
INPUT CHARACTERISTICS
Common-mode input range
Common-mode rejection ratio
±3.3
±3
±3
66
60
57
57
dB
MIN
Noninverting input resistance
1.1
MΩ
TYP
Noninverting input capacitance
1.2
pF
TYP
Inverting input resistance
32
Ω
TYP
Inverting input capacitance
1.5
pF
TYP
6
VCM = ±2.0 V, VO = 0 V
±3.6
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THS3096
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SLOS428B – DECEMBER 2003 – REVISED FEBRUARY 2006
ELECTRICAL CHARACTERISTICS (continued)
VS = ±5 V, RF = 909 Ω, RL = 100 Ω, and G = 2 (unless otherwise noted)
TYP
PARAMETER
TEST CONDITIONS
OVER TEMPERATURE
25°C
25°C
0°C to
70°C
-40°C to
85°C
UNIT
MIN/TYP/
MAX
RL = 1 kΩ
±3.4
±3.1
±2.8
±2.8
RL = 100 Ω
±3.1
±2.7
±2.5
±2.5
V
MIN
Output current (sourcing)
RL = 10 Ω
200
160
140
Output current (sinking)
RL = 10 Ω
180
150
125
140
mA
MIN
125
mA
Output impedance
f = 1 MHz, Closed loop
0.09
MIN
Ω
TYP
OUTPUT CHARACTERISTICS
Output voltage swing
POWER SUPPLY
Specified operating voltage
±5
±4.5
±4.5
±4.5
V
MAX
Maximum quiescent current
8.2
9
9.5
9.5
mA
MAX
8.2
7
6.5
6.5
mA
MIN
Minimum quiescent current
Per channel
Power supply rejection (+PSRR)
VS+ = 5.5 V to 4.5 V, VS- = -5 V
73
68
63
63
dB
MIN
Power supply rejection (-PSRR)
VS+ = 5 V, VS- = -4.5 V to 5.5 V
71
65
60
60
dB
MIN
POWER-DOWN CHARACTERISTICS (THS3096 ONLY)
VS+ – 4
REF voltage range (1)
Power-down voltage level (1)
Power-down quiescent current
VPD quiescent current
PD ≥ REF + 2
Disable
PD ≤ REF + 0.8
PD = 0V
300
500
600
600
VPD = 0 V, REF = 0 V,
11
15
20
20
VPD = 3.3 V, REF = 0 V
11
15
20
20
90% of final value
60
Turnoff time delay
10% of final value
150
MIN
V
Enable
Turnon time delay
(1)
MAX
VS–
MIN
MAX
µA
MAX
µA
MAX
µs
TYP
For detailed information on th behavior of the powerdown circuit, see the Powerdown and Powerdown Reference sections in the
Application Information of this data sheet.
TYPICAL CHARACTERISTICS
TABLE OF GRAPHS
FIGURE
±15-V graphs
Noninverting frequency response
1, 2
Inverting frequency response
3
0.1 dB flatness
4
Noninverting frequency response
5
Inverting frequency response
6
Frequency response capacitive load
7
Recommended RISO
vs Capacitive load
2nd Harmonic distortion
vs Frequency
3rd Harmonic distortion
vs Frequency
Slew rate
vs Output voltage step
Noise
vs Frequency
Settling time
8
9, 11
10, 12
13, 14, 15
16
17, 18
Quiescent current
vs Supply voltage
19
Output voltage
vs Load resistance
20
Input bias and offset current
vs Case temperature
21
Input offset voltage
vs Case temperature
22
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SLOS428B – DECEMBER 2003 – REVISED FEBRUARY 2006
TYPICAL CHARACTERISTICS (continued)
FIGURE
Transimpedance
vs Frequency
23
Rejection ratio
vs Frequency
24
Noninverting small signal transient response
25
Inverting large signal transient response
26, 27
Overdrive recovery time
28
Differential gain
vs Number of loads
29
Differential phase
vs Number of loads
30
Closed loop output impedance
vs Frequency
31
Crosstalk
vs Frequency
32
Power-down quiescent current
vs Supply voltage
33
Turnon and turnoff time delay
8
34
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SLOS428B – DECEMBER 2003 – REVISED FEBRUARY 2006
TABLE OF GRAPHS
FIGURE
±5-V graphs
Noninverting frequency response
35
Inverting frequency response
36
0.1 dB flatness
37
Noninverting frequency response
38
Inverting frequency response
39
Settling time
40
2nd Harmonic distortion
vs Frequency
3rd Harmonic distortion
vs Frequency
41
Slew rate
vs Output voltage step
42
43, 44, 45
Noninverting small signal transient response
46
Output voltage load resistance
47
Input bias and offset current
vs Case temperature
48
Overdrive recovery time
49
Rejection ratio
vs Frequency
50
Crosstalk
vs Frequency
51
TYPICAL CHARACTERISTICS (±15 V)
NONINVERTING
FREQUENCY RESPONSE
RF = 499 Ω
RF = 909 Ω
7
Noninverting Gain − dB
Noninverting Gain − dB
8
6
5
RF = 1.2 k Ω
4
3
2
1
Gain = 2,
RL = 100 Ω,
VO = 200 mVPP,
VS = ±15 V
0
1M
10 M
100 M
f − Frequency − Hz
Figure 1.
1G
24
22
20
18
16
14
12
10
INVERTING
FREQUENCY RESPONSE
RL = 100 Ω,
VO = 200 mVPP, VS = ±15 V
G = 10, RF = 604 Ω
Inverting Gain − dB
9
NONINVERTING
FREQUENCY RESPONSE
G = 5, RF = 715 Ω
G =2, RF = 909 Ω
8
6
4
2
0
−2
−4
G =1, RF = 1.1 kΩ
1M
10 M
100 M
f − Frequency − Hz
Figure 2.
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1G
24
22
20
18
16
14
12
10
8
6
4
2
0
−2
−4
RL = 100 Ω,
VO = 200 mVPP, VS = ±15 V
G = −10, RF = 604 Ω
G = −5, RF = 715 Ω
G = −2, RF = 806 Ω
G = −1, RF = 909 Ω
1M
10 M
100 M
1G
f − Frequency − Hz
Figure 3.
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SLOS428B – DECEMBER 2003 – REVISED FEBRUARY 2006
TYPICAL CHARACTERISTICS (±15 V) (continued)
0.1 dB FLATNESS
NONINVERTING
FREQUENCY RESPONSE
16
Gain = 2,
RF = 909 Ω,
RL = 200 Ω,
VO = 200 mVPP,
VS = ±15 V
6.1
6
5.9
5.8
12
VO = 10VPP
VO = 5VPP
VO = 1VPP
Gain = 5,
RF = 715 Ω,
RL = 100 Ω,
VS = ±15 V
4
100 M
1G
1M
Figure 6.
FREQUENCY RESPONSE
CAPACITIVE LOAD
RECOMMENDED RISO
vs
CAPTIVATE LOAD
2ND HARMONIC DISTORTION
vs
FREQUENCY
R(ISO) = 30.9 Ω
CL = 22 pF
8
R(ISO) = 20 Ω
CL = 47 pF
R(ISO) = 15 Ω
CL = 100 pF
Gain = 5
RL = 100 Ω
VS =±15 V
2nd Harmonic Destortion − dBc
Recommended R ISO − Ω
10
−40
Gain = 5,
VS = ±15 V
40
12
0
VO = 2 VPP
Figure 5.
45
2
VO = 5 VPP
Figure 4.
100 M
R(ISO) = 39.2 Ω
CL = 10 pF
4
Gain = −5,
RF = 715 Ω,
RL = 100 Ω,
VS = ±15 V
f − Frequency − Hz
14
35
30
25
20
15
715 Ω
178 Ω
10
RISO
−
CL
+
5
100 M
1G
VS = ±15 V,
VO = 2 VPP
1G
G=1
RF = 1.1 kΩ,
RL = 100 Ω
−50
−60
−70
G=1
RF = 1.1 kΩ,
RL = 1 kΩ
G=2
RF = 909 Ω,
RL = 1 kΩ
−80
G=2
RF = 909 Ω,
RL = 100 Ω
−90
0
10 M
10
100 k
100
1M
10 M
100 M
f − Frequency − Hz
CL − Capacitive Load − pF
f − Frequency − Hz
Figure 7.
Figure 8.
Figure 9.
3RD HARMONIC DISTORTION
vs
FREQUENCY
2ND HARMONIC DISTORTION
vs
FREQUENCY
3RD HARMONIC DISTORTION
vs
FREQUENCY
−40
−30
−50
−60
−70
−30
VO = 20 VPP
G=1
RF = 1.1 kΩ,
RL = 1 kΩ
−40
G=1
RF = 1.1 kΩ,
RL = 100 Ω
G=2
RF = 909 Ω,
RL = 100 Ω
−50
−60
−70
VO = 10 VPP
G=5
RF = 715 Ω,
RL = 100 Ω,
Vs = ±15 V
VO = 5 VPP
−80
−80
−90
100 k
G=2
RF = 909 Ω,
RL = 1 kΩ
1M
10 M
f − Frequency − Hz
Figure 10.
100 M
VO = 20 VPP
−40
VO = 10 VPP
−50
−60
−70
G=5
RF = 715 Ω,
RL = 100 Ω,
Vs = ±15 V
−80
VO = 5 VPP
−90
−90
−100
100 k
Harmonic Distortion −dBc
VS = ±15 V,
VO = 2 VPP
Harmonic Distortion −dBc
3rd Harmonic Distortion − dBc
2
10 M
VO = 10 VPP
6
0
1M
VO = 20 VPP
8
10 M
100 M
f − Frequency − Hz
1M
10 M
f − Frequency − Hz
16
6
10
4
0
100 k
10
12
8
6
VO = 1 VPP
14
VO = 20VPP
10
2
5.7
Signal Gain − dB
VO = 2VPP
14
Noninverting Gain − dB
Noninverting Gain − dB
6.2
16
Inverting Gain − dB
6.3
−2
INVERTING
FREQUENCY RESPONSE
VO = 2 VPP
VO = 2 VPP
−100
1M
10 M
100 M
f − Frequency − Hz
Figure 11.
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100 k
1M
10 M
f − Frequency − Hz
Figure 12.
100 M
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SLOS428B – DECEMBER 2003 – REVISED FEBRUARY 2006
TYPICAL CHARACTERISTICS (±15 V) (continued)
SLEW RATE
vs
OUTPUT VOLTAGE STEP
SLEW RATE
vs
OUTPUT VOLTAGE STEP
4000
700
6000
Gain = 2
RL = 100 Ω
RF = 909 Ω
VS = ±15 V
3500
600
SR − Slew Rate − V/ µ s
Rise
Fall
500
400
300
Gain = 1
RL = 100 Ω
RF = 1.1 kΩ
VS = ±15 V
200
100
3000
2500
2000
Rise
1500
1000
0.5
1
1.5
2
2.5
3
3.5
1
2
3
4
5
6
7
8
9
10
0
10 12 14 16 18 20
Figure 15.
NOISE
vs
FREQUENCY
SETTLING TIME
SETTLING TIME
Rising Edge
10
In+
Vn
VO − Output Voltage − V
VO − Output Voltage − V
In−
0.5
0.25
Gain = −2
RL = 100 Ω
RF =806 Ω
VS = ±15 V
0
−0.25
−0.5
−0.75
Falling Edge
−1
1
100
1k
10 k
f − Frequency − Hz
−1.25
100 k
0
1
2
3
4
5
6
7
8
9
10
4.5
4
3.5
3
2.5
2
1.5
1
0.5
0
−0.5
−1
−1.5
−2
−2.5
−3
−3.5
−4
−4.5
Rising Edge
Gain = −2
RL = 100 Ω
RF = 806 Ω
VS = ±15 V
Falling Edge
0
2
4
t − Time − ns
6
8
10
Figure 17.
Figure 18.
QUIESCENT CURRENT
vs
SUPPLY VOLTAGE
OUTPUT VOLTAGE
vs
LOAD RESISTANCE
INPUT BIAS AND
OFFSET CURRENT
vs
CASE TEMPERATURE
TA = 25 °C
9.5
9
TA = −40 °C
8.5
8
7.5
Per Channel
7
5
6
7
8
9 10 11 12 13 14 15
VS − Supply Voltage − ±V
Figure 19.
VO - Output Voltage - V
TA = 85 °C
16
7
12
6.5
6
I IB - Input Bias Currents - µ A
I OS - Input Offset Currents - µ A
11
8
4
VS = ±15 V
TA = -40 to 85°C
0
-4
-8
-12
-16
10
100
RL - Load Resistance - Ω
Figure 20.
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12
t − Time − ns
Figure 16.
10.5
4
8
Figure 14.
100
3
6
Figure 13.
0.75
10
4
VO − Output Voltage −VPP
1.25
10
2
VO − Output Voltage −VPP
1
Hz
Fall
0
0
4
1000
I n − Current Noise − pA/ Hz
2000
1000
VO − Output Voltage − VPP
Vn − Voltage Noise − nV/
3000
0
0
I Q− Quiescent Current − mA
4000
Fall
500
0
Rise
Gain = 5
RL = 100 Ω
RF = 715 Ω
VS = ±15 V
5000
SR − Slew Rate − V/µ s
800
SR − Slew Rate − V/ µ s
SLEW RATE
vs
OUTPUT VOLTAGE STEP
1000
VS = ±15 V
IIB-
5.5
5
4.5
4
IIB+
3.5
3
2.5
2
1.5
1
IOS
0.5
0
-40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90
TC - Case Temperature - °C
Figure 21.
11
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SLOS428B – DECEMBER 2003 – REVISED FEBRUARY 2006
TYPICAL CHARACTERISTICS (±15 V) (continued)
INPUT OFFSET VOLTAGE
vs
CASE TEMPERATURE
TRANSIMPEDANCE
vs
FREQUENCY
70
100
2.5
2
VS = ±15 V
1.5
1
VS = ±5 V
0.5
90
VS = ±15 V and ±5 V
70
60
50
40
30
10
10
0
1M
10 M
100 M
1G
100 k
1M
10 M
100 M
1G
f − Frequency − Hz
Figure 24.
NONINVERTING SMALL SIGNAL
TRANSIENT RESPONSE
INVERTING LARGE SIGNAL
TRANSIENT RESPONSE
INVERTING LARGE SIGNAL
TRANSIENT RESPONSE
6
0.1
Input
0
−0.05
−0.1
Gain = 2,
RL = 100 Ω,
RF = 909 Ω,
VS = ±15 V
−0.15
−0.2
−0.25
0
10
20
30
3
2
1
Input
0
−1
−2
Gain = 2,
RL = 100 Ω,
RF = 715 Ω,
VS = ±15 V
−3
−4
−5
−6
−5 0
−0.3
−10
Output
4
40
50
60
70
VO − Output Voltage − V
0.15
0.05
12
10
5
Output
VO − Output Voltage − V
Gain = −5,
RL = 100 Ω,
RF = 715 Ω,
VS = ±15 V
8
6
4
2
Input
0
−2
−4
−6
Output
−8
−10
−12
5 10 15 20 25 30 35 40 45 50 55 60
−10
0
10
20
30
40
50
60
t − Time − ns
t − Time − ns
t − Time − ns
Figure 25.
Figure 26.
Figure 27.
OVERDRIVE RECOVERY TIME
DIFFERENTIAL GAIN
vs
NUMBER OF LOADS
DIFFERENTIAL PHASE
vs
NUMBER OF LOADS
20
0.10
4
G = 5,
RL = 100 Ω,
RF = 715 Ω,
VS = ±15 V
3
1
0
0
−5
−1
−10
−2
−15
−3
Differential Gain − %
5
0.08
VI − Input Voltage − V
2
0.07
PAL
0.04
0.03
0.02
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
t − Time − µs
Figure 28.
1
Gain = 2
RF = 909 Ω
VS = ±15 V
40 IRE − NTSC and Pal
Worst Case ±100 IRE Ramp
0.04
0.03
PAL
0.02
NTSC
0.01
NTSC
0.01
−20
°
0.06
0.05
70
0.05
Gain = 2
RF = 909 Ω
VS = ±15 V
40 IRE − NTSC and Pal
Worst Case ±100 IRE Ramp
0.09
Differential Phase −
VO − Output Voltage − V
PSRR+
20
Figure 23.
0.2
VO − Output Voltage − V
30
f − Frequency − Hz
0.3
12
CMRR
40
Figure 22.
0.25
10
50
20
TC - Case Temperature - °C
15
PSRR−
80
0
100 k
0
-40 -30 -20-10 0 10 20 30 40 50 60 70 80 90
VS = ±15 V
60
Rejection Ratio − dB
Transimpedance Gain − dB Ohms
VOS - Input Offset Voltage - mV
3
REJECTION RATIO
vs
FREQUENCY
−4
0
0
1
2
3
4
5
6
7
8
0
0
1
2
3
4
5
6
Number of Loads − 150 Ω
Number of Loads − 150 Ω
Figure 29.
Figure 30.
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TYPICAL CHARACTERISTICS (±15 V) (continued)
CLOSED-LOOP OUTPUT
IMPEDANCE
vs
FREQUENCY
CROSSTALK
vs
FREQUENCY
10
−10
G= 5, CH1 to 2
1
909 Ω
600
VS = ±15 V,
RL = 100 Ω
−20
Crosstalk − dB
Closed-Loop Output Impedance − Ω
Gain = 2,
RISO = 5.11 Ω,
RF = 909 Ω,
VS = ±15 V
Powerdown Quiescent Current - µ A
0
100
POWER-DOWN QUIESCENT
CURRENT
vs
SUPPLY VOLTAGE
909 Ω
0.1
−40
G= 5, CH2 to 1
−50
−60
G= 2, CH2 to 1
−70
−80
5.11 Ω VO
−
−30
+
G= 2, CH1 to 2
−90
0.01
−100
1M
10 M
100 M
1G
500
TA = 85°C
400
TA = -40°C
300
TA = 25°C
200
100
0
100 k
1M
10 M
100 M
f − Frequency − Hz
f − Frequency − Hz
Figure 31.
3
1G
4
5
6
7
8
9
10 11 12 13 14 15
VS - Supply Voltage - ±V
Figure 32.
Figure 33.
TURNON AND TURNOFF
TIME DELAY
6
5
4
Gain = 2,
VI = 0.1 Vdc
RL = 100 Ω
VS = ±15 V and ±5 V
3
2
1
0
0.3
0.2
0.1
Power-on Pulse − V
VO − Output Voltage Level − V
Power-on Pulse
Output Voltage
0
−0.1
0
1
2
3
4
5
6
7
t − Time − ms
Figure 34.
TYPICAL CHARACTERISTICS (±5 V)
NONINVERTING
FREQUENCY RESPONSE
8
6
4
2
0
−2
−4
G = 5, RF = 715 Ω
RL = 100 Ω,
VO = 200 mVPP,
VS = ±5 V
G = 2, RF = 909 Ω
10 M
6.3
G = −10, RF = 604 Ω
100 M
f − Frequency − Hz
Figure 35.
1G
Gain = 2,
RF = 909 Ω,
RL = 100 Ω,
VO = 200 mVPP,
VS = ±5 V
6.2
G = −5, RF = 715 Ω
RL = 100 Ω,
VO = 200 mVPP,
VS = ±5 V
G = −2, RF = 806 Ω
2
0
−2
−4
G = 1, RF = 1.1 kΩ
1M
16
14
12
10
8
6
4
0.1 dB FLATNESS
Noniverting Gain −dB
16
14
12
10
24
22
20
18
G = 10, RF = 604 Ω
Inverting Gain − dB
Noninverting Gain − dB
24
22
20
18
INVERTING
FREQUENCY RESPONSE
6.1
6
5.9
5.8
G = −1, RF = 906 Ω
5.7
1M
10 M
100 M
1G
1
10
f − Frequency − Hz
f − Frequency − MHz
Figure 36.
Figure 37.
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100
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SLOS428B – DECEMBER 2003 – REVISED FEBRUARY 2006
TYPICAL CHARACTERISTICS (±5 V) (continued)
NONINVERTING
FREQUENCY RESPONSE
INVERTING
FREQUENCY RESPONSE
16
16
1.25
VO = 2 VPP
12
10
VO = 1 VPP
8
VO = 5 VPP
6
G = 5,
RF = 715 Ω,
RL = 100 Ω,
VS = ±5V
1M
10
8
VO = 2 VPP
4
G = 5,
RF = 715 Ω,
RL = 100 Ω,
VS = ±5V
2
100 M
10 M
0
1G
0
1
2
3
5
6
7
8
9
SLEW RATE
vs
OUTPUT VOLTAGE STEP
−40
G = 2, RF = 909 Ω,
RL = 100 Ω
−70
G =1, RF = 1.1 kΩ,
RL = 1 kΩ
−80
G = 2, RF = 909 Ω,
RL = 1 kΩ
100 k
1M
10 M
f − Frequency − Hz
−50
G = 2, RF = 909Ω,
RL = 1 kΩ
G = 1, RF = 1.1 kΩ,
RL = 1 kΩ
−70
Gain =1
RL = 100 Ω
RF = 1.1 kΩ
VS = ±5 V
800
G = 1, RF = 1.1 kΩ,
RL = 100 Ω
−60
700
Rise
600
Fall
500
400
300
200
−80
VO = 2 VPP,
VS = ±5 V
100
−90
100 k
100 M
10
900
G = 2, RF = 909Ω,
RL = 100 Ω
G =1, RF = 1.1 kΩ,
RL = 100 Ω
1M
10 M
0
100 M
0
0.5
1
1.5
2
2.5
3
3.5
4
f − Frequency − Hz
VO − Output Voltage −VPP
Figure 41.
Figure 42.
Figure 43.
SLEW RATE
vs
OUTPUT VOLTAGE STEP
SLEW RATE
vs
OUTPUT VOLTAGE STEP
NONINVERTING SMALL SIGNAL
TRANSIENT RESPONSE
1400
Gain = 2
RL = 100 Ω
RF = 909Ω
VS = ±5 V
Rise
SR − Slew Rate − V/ µ s
1200
Fall
800
0.3
Gain = 5
RL = 100 Ω
RF = 715 Ω
VS = ±5 V
700
600
500
400
300
200
0.25
Output
0.2
Rise
VO − Output Voltage − V
1200
1000
Fall
800
600
400
0.15
0.1
Input
0.05
0
−0.05
−0.1
Gain = 2
RL = 100 Ω
RF = 909 Ω
VS = ±5 V
−0.15
−0.2
200
100
−0.25
0
0
4
t − Time − ns
3RD HARMONIC DISTORTION
vs
FREQUENCY
3rd Harmonic Distortion − dBc
2nd Harmonic Destortion − dBc
−1.25
1G
2ND HARMONIC DISTORTION
vs
FREQUENCY
−90
14
Falling Edge
−1
Figure 40.
−60
900
−0.5
Figure 39.
−50
1000
Gain = −2
RL = 100 Ω
RF = 806 Ω
VS = ±5 V
0
Figure 38.
VS = ±5 V,
VO = 2 VPP
1100
0.5
0.25
−0.75
VO = 5 VPP
10 M
100 M
f − Frequency − Hz
1M
f − Frequency − Hz
−40
Rising Edge
0.75
−0.25
6
SR − Slew Rate − V/ µ s
4
2
SR − Slew Rate − V/ µ s
VO − Output Voltage − V
12
1
VO = 1 VPP
14
Inverting Gain − dB
Noninverting Gain − dB
14
0
SETTLING TIME
0
VO − Output Voltage −VPP
1
2
3
4
VO − Output Voltage −VPP
Figure 44.
Figure 45.
1
2
3
4
5
0
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−0.3
−10
0
10
20
30
40
t − Time − ns
Figure 46.
50
60
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SLOS428B – DECEMBER 2003 – REVISED FEBRUARY 2006
TYPICAL CHARACTERISTICS (±5 V) (continued)
INPUT BIAS AND
OFFSET CURRENT
vs
CASE TEMPERATURE
2
1.5
1
0.5
VS = ±5 V
TA = -40 to 85°C
0
-0.5
-1
-1.5
-2
-2.5
-3
5
VS = ±5 V
IIB-
6
5
IOS
4
3
2
IIB+
1
0
-40 -30 -20 -10 0
-3.5
100
1000
Figure 47.
0.8
0.6
0.4
1
0.2
0
0
−1
−0.2
−2
−0.4
−3
−0.6
−4
−0.8
−1
0
10 20 30 40 50 60 70 80 90
0.2
0.4
0.6
0.8
1
t − Time − µs
Figure 48.
Figure 49.
REJECTION RATIO
vs
FREQUENCY
CROSSTALK
vs
FREQUENCY
70
0
VS = ±5 V
−10
60
VS = ±5 V,
RL = 100 Ω
−20
PSRR-
G= 5, CH1 to 2
50
40
20
2
TC - Case Temperature - °C
RL - Load Resistance - Ω
30
3
−5
Crosstalk − dB
10
1
Gain = 5,
RL = 100 Ω,
RF = 715 Ω,
VS = ±5 V
4
VI − Input Voltage − V
7
OVERDRIVE RECOVERY TIME
VO − Output Voltage − A
8
3
2.5
I IB - Input Bias Current - µ A
I OS - Input Offset Current - µ A
3.5
Rejection Ratio - dB
VO - Output Voltage - V
OUTPUT VOLTAGE
vs
LOAD RESISTANCE
CMRR
PSRR+
−30
−40
G= 5, CH2 to 1
−50
−60
G= 2, CH2 to 1
−70
−80
10
0
100 k
G= 2, CH1 to 2
−90
−100
1M
10 M
f - Frequency - Hz
100 M
100 k
Figure 50.
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10 M
100 M
f − Frequency − Hz
1G
Figure 51.
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SLOS428B – DECEMBER 2003 – REVISED FEBRUARY 2006
APPLICATION INFORMATION
WIDEBAND, NONINVERTING OPERATION
The THS3092/6 are unity gain stable 135-MHz
current-feedback operational amplifiers, designed to
operate from a ±5-V to ±15-V power supply.
Figure 52 shows the THS3092 in a noninverting gain
of 2-V/V configuration typically used to generate the
performance curves. Most of the curves were
characterized using signal sources with 50-Ω source
impedance, and with measurement equipment
presenting a 50-Ω load impedance.
15 V
+
0.1 µF
+
VI
49.9 Ω
6.8 µF
1
2
_
−VS
−15 V
Figure 52. Wideband, Noninverting Gain
Configuration
±15
--
1.1 k
±5
--
1.1 k
±15
909
909
909
178
715
±5
178
715
±15
66.5
604
±5
66.5
604
-1
±15 and ±5
909
909
-2
±15 and ±5
402
806
-5
±15 and ±5
143
715
-10
±15 and ±5
60.4
604
10
Current-feedback amplifiers are highly dependent on
16
RF (Ω)
909
6.8 µF
+
RG (Ω)
±5
5
0.1 µF
SUPPLY VOLTAGE
(V)
±15
50 Ω LOAD
909 Ω
RG
GAIN (V/V)
49.9 Ω
RF
909 Ω
Table 1. Recommended Resistor Values for
Optimum Frequency Response
THS3092 and THS3096 RF and RG values for minimal peaking
with RL = 100 Ω
+VS
50 Ω Source
the feedback resistor RF for maximum performance
and stability. Table 1 shows the optimal gain setting
resistors RF and RG at different gains to give
maximum bandwidth with minimal peaking in the
frequency response. Higher bandwidths can be
achieved, at the expense of added peaking in the
frequency response, by using even lower values for
RF. Conversely, increasing RF decreases the
bandwidth, but stability is improved.
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WIDEBAND, INVERTING OPERATION
Figure 53 shows the THS3092 in a typical inverting
gain configuration where the input and output
impedances and signal gain from Figure 52 are
retained in an inverting circuit configuration.
+VS
50 Ω Source
+
VI
15 V +VS
+
0.1 µF
+
VI
RG
RF
402 Ω
RM
57.6 Ω
806 Ω
0.1 µF
RG
909 Ω
6.8 µF
+VS
2
+
50 Ω Source
VI
57.6 Ω
−15 V
+VS
2
909 Ω
RF
VS
RG
_
402 Ω
RT
+
−VS
Figure 53. Wideband, Inverting Gain
Configuration
50 Ω LOAD
RF
49.9 Ω
50 Ω LOAD
49.9 Ω
_
+VS
2
6.8 µF
_
50 Ω Source
49.9 Ω
RT
806 Ω
49.9 Ω
50 Ω LOAD
+VS
2
Figure 54. DC-Coupled, Single-Supply Operation
SINGLE SUPPLY OPERATION
VDSL Driver Circuit
The THS3092/6 have the capability to operate from a
single
supply
voltage
ranging
from
10 V to 30 V. When operating from a single power
supply, biasing the input and output at mid-supply
allows for the maximum output voltage swing. The
circuits shown in Figure 54 shows inverting and
noninverting amplifiers configured for single supply
operations.
The THS3092 and THS3096 have the ability to drive
over 200 mA of current with very high voltage swings.
Using these amplifiers coupled with the very high
slew rate, low distortion, and low noise required in
VDSL applications, makes for a perfect match. In
VDSL systems where the receive signal is critical, the
use of a low transformer ratio is necessary. With this
low ratio, the output swing required from the line
driver amplifier must increase, especially when
driving the VDSL’s full 14.5-dBm power onto the line.
The line driver's low distortion and noise is critical for
the VDSL as the receive bands are intertwined with
the transmit frequency bands up to the 12-MHz VDSL
limit.
Figure 55 shows a traditional hybrid connection
approach for achieving the 14.5-dBm line power
utilizing a 1:1 transformer. Looking at the input to the
amplifiers shows a low-pass filter consisting of two
separate capacitors to ground. There is an argument
that since the signal coming out of the DAC is
fully-differential then a single capacitor (10 pF in this
case) is perfectly acceptable. The problem with this
idea is that many DACs have common-mode energy
due to images around the sampling frequency which
must be filtered before reaching the amplifier. An
amplifier simply amplifies its input–including the
DAC’s images at high frequencies–and pass it
through to the transformer and ultimately to the line,
possibly causing the system to fail EMC compliance.
A single capacitor does not remove these
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THS3096
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SLOS428B – DECEMBER 2003 – REVISED FEBRUARY 2006
20 V
10 V
0.01 F
4.99 k
1:1
330 pF
200 THS3092
24.9 *Hybrid Connection Not
Shown For Simplicity
4.99 k
Hybrid
0.022 F
To RX
604 0.022 F
10 V
0.015 F
THS3092
Figure 56.
100 −
+
330 pF
+
14.5 dBm
Line Power
604 133 200 100 −
DAC
VIN−
−
22 pF
1.21 k
14.5 dBm
Line Power
6.8 F
49.9 +
22 pF
DAC
VIN−
604 THS3092
330 pF
1.21 k
0.01 F
22 pF
0.01 F
DAC
VIN+
1:1
604 191 26 V
4.99 k
−
22 pF
13 V
200 24.9 +
330 pF
0.022 F
DAC
VIN+
6.8 F
THS3092
200 0.022 F
common-mode images, it only removes the
differential signal images. However, two separate
filter capacitors filter both the common-mode signals
and the differential-mode signals. Be sure to place
the ground connection point of the capacitors next to
each other, and then tie a single ground point at the
middle of this trace.
Video Distribution
49.9 4.99 k
13 V
Figure 55.
Additionally, level shifting must be done to center the
common-mode voltage appearing at the amplifier’s
noninverting input to optimally the midpoint of the
power supply. As a side benefit of the
ac-coupling/level shifter, a simple high pass filter is
formed. This is generally a good idea for VDSL
systems where the transmit band is typically above 1
MHz, but can be as low as 25 kHz.
One of the concerns about any DSL line driver is the
power dissipation. One of the most common ways to
reduce power is by using active termination, aka
synthesized impedance. Refer to TI Application Note
SLOA100 for more information on active termination.
The drawback to active termination is the received
signal is reduced by the same synthesis factor
utilized in the system. Due to the very high
attenuation of the line at up to 12 MHz, the receive
signal can be severely diminished. Thus, the use of
active termination should be kept to modest levels at
best. Figure 56 shows an example of utilizing a
simple active termination scheme with a synthesis
factor of 2 to achieve the same line power, but with a
reduced power supply voltage that ultimately saves
power in the system.
The wide bandwidth, high slew rate, and high output
drive current of the THS3092/6 matches the demands
for video distribution for delivering video signals down
multiple cables. To ensure high signal quality with
minimal degradation of performance, a 0.1-dB gain
flatness should be at least 7x the passband
frequency to minimize group delay variations from the
amplifier. A high slew rate minimizes distortion of the
video signal, and supports component video and
RGB video signals that require fast transition times
and fast settling times for high signal quality.
909 Ω
909 Ω
15 V
−
+
VI
75 Ω
75-Ω Transmission Line
−15 V
75 Ω
n Lines
VO(1)
75 Ω
VO(n)
75 Ω
75 Ω
Figure 57. Video Distribution Amplifier
Application
Driving Capacitive Loads
Applications such as FET line drivers can be highly
capacitive and cause stability problems for
high-speed amplifiers.
Figure 58 through Figure 63 show recommended
methods for driving capacitive loads. The basic idea
is to use a resistor or ferrite chip to isolate the phase
shift at high frequency caused by the capacitive load
from the amplifier’s feedback path. See Figure 58 for
recommended resistor values versus capacitive load.
18
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45
Gain = 5,
VS = ±15 V
Recommended R ISO − Ω
40
35
30
25
20
15
715 Ω
178 Ω
10
−
RISO
CL
+
5
0
10
100
CL − Capacitive Load − pF
Figure 58. Recommended RISO vs Capacitive Load
Figure 61 shows another method used to maintain
the low frequency load independence of the amplifier
while isolating the phase shift caused by the
capacitance at high frequency. At low frequency,
feedback is mainly from the load side of RISO. At high
frequency, the feedback is mainly via the 27-pF
capacitor. The resistor RIN in series with the negative
input is used to stabilize the amplifier and should be
equal to the recommended value of RF at unity gain.
Replacing RIN with a ferrite of similar impedance at
about 100 MHz as shown in Figure 62 gives similar
results with reduced dc offset and low frequency
noise. (See the ADDITIONAL REFERENCE
MATERIAL section for Expanding the usability of
current-feedback amplifiers.)
RF
715 Ω
27 pF
VS
178 Ω
_
+
5.11 Ω
VS
715 Ω
RG
178 Ω
1 µF
−VS
RIN
100 Ω LOAD
RISO
715 Ω
VS
_
100 Ω LOAD
5.11 Ω
+
49.9 Ω
1 µF
−VS
49.9 Ω
VS
Figure 59.
Figure 61.
715 Ω
178 Ω
RF
VS
Ferrite Bead
_
+
−VS
VS
1 µF
27 pF
FIN
100 Ω LOAD
RG
49.9 Ω
715 Ω
178 Ω
FB
VS
_
+
−VS
VS
Figure 60.
Placing a small series resistor, RISO, between the
amplifier’s output and the capacitive load, as shown
in Figure 59, is an easy way of isolating the load
capacitance.
Using a ferrite chip in place of RISO, as shown in
Figure 60, is another approach of isolating the output
of the amplifier. The ferrite's impedance characteristic
versus frequency is useful to maintain the low
frequency load independence of the amplifier while
isolating the phase shift caused by the capacitance at
high frequency. Use a ferrite with similar impedance
to RISO, 20 Ω - 50 Ω, at 100 MHz and low impedance
at dc.
100 Ω LOAD
5.11 Ω
1 µF
49.9 Ω
Figure 62.
Figure 63 is shown using two amplifiers in parallel to
double the output drive current to larger capacitive
loads. This technique is used when more output
current is needed to charge and discharge the load
faster like when driving large FET transistors.
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THS3096
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rails and are given in the specification tables. Above
the Enable Threshold Voltage, the device is on.
Below the Disable Threshold Voltage, the device is
off. Behavior in between these threshold voltages is
not specified.
715 Ω
VS
178 Ω
5.11 Ω
_
24.9 Ω
+
−VS
715 Ω
VS
VS
178 Ω
_
24.9 Ω
1 nF
5.11 Ω
+
−VS
Figure 63.
Figure 64 shows a push-pull FET driver circuit typical
of ultrasound applications with isolation resistors to
isolate the gate capacitance from the amplifier.
VS
VS
Figure 65 shows the total system output impedance
which includes the amplifier output impedance in
parallel with the feedback plus gain resistors, which
cumulate to 2420 Ω. Figure 52 shows this circuit
configuration for reference.
2500
ZOPD − Powerdown Output Impedance − Ω
5.11 Ω
+
_
Note that this power-down functionality is just that;
the amplifier consumes less power in power-down
mode. The power-down mode is not intended to
provide a high-impedance output. In other words, the
power-down functionality is not intended to allow use
as a 3-state bus driver. When in power-down mode,
the impedance looking back into the output of the
amplifier is dominated by the feedback and gain
setting resistors, but the output impedance of the
device itself varies depending on the voltage applied
to the outputs.
VS = ±15 V and ±5 V
2000
−VS
1500
604 Ω
1000
133 Ω
604 Ω
VS
_
5.11 Ω
1.21 kΩ
500
1.21 kΩ
−
+
50 Ω VO
1M
10 M
0
100 k
100 M
1G
f − Frequency − Hz
+
−VS
Figure 65. Power-down Output Impedance vs
Frequency
−VS
Figure 64. PowerFET Drive Circuit
SAVING POWER WITH POWER-DOWN
FUNCTIONALITY AND SETTING
THRESHOLD LEVELS WITH THE
REFERENCE PIN
The THS3096 features a power-down pin (PD) which
lowers the quiescent current from 9.5 mA down to
500 µA, ideal for reducing system power.
The power-down pin of the amplifier defaults to the
positive supply voltage in the absence of an applied
voltage, putting the amplifier in the power-on mode of
operation. To turn off the amplifier in an effort to
conserve power, the power-down pin can be driven
towards the negative rail. The threshold voltages for
power-on and power-down are relative to the supply
20
As with most current feedback amplifiers, the internal
architecture places some limitations on the system
when in power-down mode. Most notably is the fact
that the amplifier actually turns ON if there is a ±0.7 V
or greater difference between the two input nodes
(V+ and V–) of the amplifier. If this difference
exceeds ±0.7 V, the output of the amplifier creates an
output
voltage
equal
to
approximately
[(V+ – V–) – 0.7 V] × Gain. This also implies that if a
voltage is applied to the output while in power-down
mode, the V- node voltage is equal to
VO(applied) × RG/(RF + RG). For low gain configurations
and a large applied voltage at the output, the
amplifier may actually turn ON due to the
aforementioned behavior.
The time delays associated with turning the device on
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and off are specified as the time it takes for the
amplifier to reach either 10% or 90% of the final
output voltage. The time delays are in the order of
microseconds because the amplifier moves in and out
of the linear mode of operation in these transitions.
POWER-DOWN REFERENCE PIN
OPERATION
In addition to the power-down pin, the THS3096
features a reference pin (REF) which allows the user
to control the enable or disable power-down voltage
levels applied to the PD pin. In most split-supply
applications, the reference pin is connected to
ground. In either case, the user needs to be aware of
voltage-level thresholds that apply to the power-down
pin. The tables below show examples and illustrate
the relationship between the reference voltage and
the power-down thresholds. In the table, the threshold
levels are derived by the following equations:
PD ≤ REF + 0.8 V for disable
PD ≥ REF + 2.0 V for enable
where the usable range at the REF pin is VS– ≤ VREF≤
(VS+ – 4 V).
The recommended mode of operation is to tie the
REF pin to midrail, thus setting the enable/disable
thresholds to Vmidrail + 2 V and Vmidrail + 0.8 V
respectively.
Table 2. Power-Down Threshold Voltage Levels
SUPPLY
VOLTAGE
(V)
REFERENCE
PIN VOLTAGE
(V)
ENABLE
LEVEL
(V)
DISABLE
LEVEL
(V)
±15, ±5
0.0
2.0
0.8
±15
2.0
4.0
2.8
±15
–2.0
0.0
–1.2
±5
1.0
3.0
1.8
±5
–1.0
1.0
–0.2
30
15
17
15.8
10
5.0
7.0
5.8
Note that if the REF pin is left unterminated, it will
float to the positive rail and will fall outside of the
recommended operating range given above VS– ≤
VREF ≤ (VS+ – 4 V). As a result, it will no longer serve
as a reliable reference for the PD pin, and the
enable/disable thresholds given above will no longer
apply. If the PD pin is also left unterminated, it will
also float to the positive rail and the device will be
enabled. If balanced, split supplies are used (±VS)
and the REF and PD pins are grounded, the device
will be disabled.
PRINTED-CIRCUIT BOARD LAYOUT
TECHNIQUES FOR OPTIMAL
PERFORMANCE
Achieving optimum performance with high frequency
amplifier, like the THS3092/6, requires careful
attention to board layout parasitic and external
component types.
Recommendations that optimize performance include:
• Minimize parasitic capacitance to any ac ground
for all of the signal I/O pins. Parasitic capacitance
on the output and input pins can cause instability.
To reduce unwanted capacitance, a window
around the signal I/O pins should be opened in all
of the ground and power planes around those
pins. Otherwise, ground and power planes should
be unbroken elsewhere on the board.
• Minimize the distance (< 0.25”) from the power
supply pins to high frequency 0.1-µF and 100-pF
decoupling capacitors. At the device pins, the
ground and power plane layout should not be in
close proximity to the signal I/O pins. Avoid
narrow power and ground traces to minimize
inductance between the pins and the decoupling
capacitors. The power supply connections should
always be decoupled with these capacitors.
Larger (6.8 µF or more) tantalum decoupling
capacitors, effective at lower frequency, should
also be used on the main supply pins. These may
be placed somewhat farther from the device and
may be shared among several devices in the
same area of the PC board.
• Careful selection and placement of external
components preserve the high frequency
performance of the THS3092/6. Resistors should
be a very low reactance type. Surface-mount
resistors work best and allow a tighter overall
layout. Again, keep their leads and PC board
trace length as short as possible. Never use
wirebound type resistors in a high frequency
application. Since the output pin and inverting
input pins are the most sensitive to parasitic
capacitance, always position the feedback and
series output resistors, if any, as close as
possible to the inverting input pins and output
pins. Other network components, such as input
termination resistors, should be placed close to
the gain-setting resistors. Even with a low
parasitic capacitance shunting the external
resistors, excessively high resistor values can
create significant time constants that can degrade
performance.
Good
axial
metal-film
or
surface-mount resistors have approximately 0.2
pF in shunt with the resistor. For resistor values >
2.0 kΩ, this parasitic capacitance can add a pole
and/or a zero that can effect circuit operation.
Keep resistor values as low as possible,
consistent with load driving considerations.
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•
•
Connections to other wideband devices on the
board may be made with short direct traces or
through onboard transmission lines. For short
connections, consider the trace and the input to
the next device as a lumped capacitive load.
Relatively wide traces (50 mils to 100 mils)
should be used, preferably with ground and
power planes opened up around them. Estimate
the total capacitive load and determine if isolation
resistors on the outputs are necessary. Low
parasitic capacitive loads (< 4 pF) may not need
an RS since the THS3092/6 are nominally
compensated to operate with a 2-pF parasitic
load. Higher parasitic capacitive loads without an
RS are allowed as the signal gain increases
(increasing the unloaded phase margin). If a long
trace is required, and the 6-dB signal loss
intrinsic to a doubly-terminated transmission line
is acceptable, implement a matched impedance
transmission line using microstrip or stripline
techniques (consult an ECL design handbook for
microstrip and stripline layout techniques). A
50-Ω environment is not necessary onboard, and
in fact, a higher impedance environment
improves distortion as shown in the distortion
versus load plots. With a characteristic board
trace impedance based on board material and
trace dimensions, a matching series resistor into
the trace from the output of the THS3092/6 is
used as well as a terminating shunt resistor at the
input of the destination device. Remember also
that the terminating impedance is the parallel
combination of the shunt resistor and the input
impedance of the destination device: this total
effective impedance should be set to match the
trace impedance. If the 6-dB attenuation of a
doubly
terminated
transmission
line
is
unacceptable,
a
long
trace
can
be
series-terminated at the source end only. Treat
the trace as a capacitive load in this case. This
does not preserve signal integrity as well as a
doubly-terminated line. If the input impedance of
the destination device is low, there is some signal
attenuation due to the voltage divider formed by
the series output into the terminating impedance.
Socketing a high speed part like the THS3092/6
are not recommended. The additional lead length
and pin-to-pin capacitance introduced by the
socket can create an extremely troublesome
parasitic network which can make it almost
impossible to achieve a smooth, stable frequency
response. Best results are obtained by soldering
the THS3092/6 parts directly onto the board.
leadframe upon which the die is mounted [see
Figure 66(a) and Figure 66(b)]. This arrangement
results in the lead frame being exposed as a thermal
pad on the underside of the package [see
Figure 66(c)]. Because this thermal pad has direct
thermal contact with the die, excellent thermal
performance can be achieved by providing a good
thermal path away from the thermal pad. Note that
devices such as the THS3092/6 have no electrical
connection between the PowerPAD and the die.
The PowerPAD package allows for both assembly
and thermal management in one manufacturing
operation. During the surface-mount solder operation
(when the leads are being soldered), the thermal pad
can also be soldered to a copper area underneath the
package. Through the use of thermal paths within this
copper area, heat can be conducted away from the
package into either a ground plane or other heat
dissipating device.
The PowerPAD package represents a breakthrough
in combining the small area and ease of assembly of
surface mount with the, heretofore, awkward
mechanical methods of heatsinking.
DIE
DIE
End View (b)
22
Bottom View (c)
Figure 66. Views of Thermal Enhanced Package
Although there are many ways to properly heatsink
the PowerPAD package, the following steps illustrate
the recommended approach.
0.300
0.100
0.035
Pin 1
0.026
0.010
0.030
0.060
0.140
0.050
0.176
0.060
0.035
0.010
vias
PowerPAD™ DESIGN CONSIDERATIONS
The
THS3092/6
are
available
in
a
thermally-enhanced PowerPAD family of packages.
These packages are constructed using a downset
Thermal
Pad
Side View (a)
0.080
Top View
Figure 67. DDA PowerPAD PCB Etch and Via
Pattern
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PowerPAD™ LAYOUT CONSIDERATIONS
1. PCB with a top side etch pattern as shown in
Figure 67. There should be etch for the leads as
well as etch for the thermal pad.
2. Place 13 holes in the area of the thermal pad.
These holes should be 10 mils in diameter. Keep
them small so that solder wicking through the
holes is not a problem during reflow.
3. Additional vias may be placed anywhere along
the thermal plane outside of the thermal pad
area. This helps dissipate the heat generated by
the THS3092/6 IC. These additional vias may be
larger than the 10-mil diameter vias directly under
the thermal pad. They can be larger because
they are not in the thermal pad area to be
soldered so that wicking is not a problem.
4. Connect all holes to the internal ground plane.
Note that the PowerPAD is electrically isolated
from the silicon and all leads. Connecting the
PowerPAD to any potential voltage such as VS-,
is acceptable as there is no electrical connection
to the silicon.
5. When connecting these holes to the ground
plane, do not use the typical web or spoke via
connection methodology. Web connections have
a high thermal resistance connection that is
useful for slowing the heat transfer during
soldering operations. This makes the soldering of
vias that have plane connections easier. In this
application, however, low thermal resistance is
desired for the most efficient heat transfer.
Therefore, the holes under the THS3092/6
PowerPAD
package
should
make
their
connection to the internal ground plane with a
complete
connection
around
the
entire
circumference of the plated-through hole.
6. The top-side solder mask should leave the
terminals of the package and the thermal pad
area with its 13 holes exposed. The bottom-side
solder mask should cover the 13 holes of the
thermal pad area. This prevents solder from
being pulled away from the thermal pad area
during the reflow process.
7. Apply solder paste to the exposed thermal pad
area and all of the IC terminals.
8. With these preparatory steps in place, the IC is
simply placed in position and run through the
solder reflow operation as any standard
surface-mount component. This results in a part
that is properly installed.
POWER DISSIPATION AND THERMAL
CONSIDERATIONS
The THS3092/6 incorporates automatic thermal
shutoff protection. This protection circuitry shuts down
the amplifier if the junction temperature exceeds
approximately 160°C. When the junction temperature
reduces to approximately 140°C, the amplifier turns
on again. But, for maximum performance and
reliability, the designer must take care to ensure that
the design does not exeed a junction temperature of
125°C. Between 125°C and 150°C, damage does not
occur, but the performance of the amplifier begins to
degrade and long term reliability suffers. The thermal
characteristics of the device are dictated by the
package and the PC board. Maximum power
dissipation for a given package can be calculated
using the following formula.
T TA
P Dmax max
JA
where:
PDmax is the maximum power dissipation in the amplifier (W).
Tmax is the absolute maximum junction temperature (°C).
TA is the ambient temperature (°C).
θJA = θJC + θCA
θJC is the thermal coefficient from the silicon junctions to the
case (°C/W).
θCA is the thermal coefficient from the case to ambient air
(°C/W).
For systems where heat dissipation is more critical,
the THS3092 is offered in an 8-pin SOIC (DDA) with
PowerPAD package, and the THS3096 is offered in a
14-pin TSSOP (PWP) with PowerPAD package for
even better thermal performance. The thermal
coefficient for the PowerPAD packages are
substantially improved over the traditional SOIC.
Maximum power dissipation levels are depicted in the
graph for the available packages. The data for the
PowerPAD packages assume a board layout that
follows the PowerPAD layout guidelines referenced
above and detailed in the PowerPAD application note
(literature number SLMA002). The following graph
also illustrates the effect of not soldering the
PowerPAD to a PCB. The thermal impedance
increases substantially which may cause serious heat
and performance issues. Be sure to always solder the
PowerPAD to the PCB for optimum performance.
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THS3096
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DESIGN TOOLS
PD − Maximum Power Dissipation − W
4
ΤJ = 125°C
Evaluation
Fixtures,
Application Support
3.5
θJA = 45.8°C/W
3
θJA = 95°C/W
2
1.5
1
0.5
θJA = 158°C/W
0
−40
−20
0
20
40
60
80
100
TA − Free-Air Temperature − °C
Results are With No Air Flow and PCB Size = 3”x 3”
θJA = 45.8°C/W for 8-Pin SOIC w/PowerPAD (DDA)
θJA = 58.4°C/W for 8-Pin MSOP w/PowerPAD (DGN)
θJA = 95°C/W for 8-Pin SOIC High−K Test PCB (D)
θJA = 158°C/W for 8-Pin MSOP w/PowerPAD w/o Solder
Figure 68. Maximum Power Distribution vs
Ambient Temperature
When determining whether or not the device satisfies
the maximum power dissipation requirement, it is
important to not only consider quiescent power
dissipation, but also dynamic power dissipation. Often
times, this is difficult to quantify because the signal
pattern is inconsistent, but an estimate of the RMS
power dissipation can provide visibility into a possible
problem.
24
Models,
and
Texas Instruments is committed to providing its
customers with the highest quality of applications
support. To support this goal an evaluation board has
been developed for the THS3092/6 operational
amplifier. The board is easy to use, allowing for
straightforward evaluation of the device. The
evaluation board can be ordered through the Texas
Instruments web site, www.ti.com, or through your
local Texas Instruments sales representative.
θJA = 58.4°C/W
2.5
Spice
Computer simulation of circuit performance using
SPICE is often useful when analyzing the
performance of analog circuits and systems. This is
particularly true for video and RF-amplifier circuits
where parasitic capacitance and inductance can have
a major effect on circuit performance. A SPICE model
for the THS3092/6 is available through either the
Texas Instruments web site (www.ti.com) or as one
model on a disk from the Texas Instruments Product
Information Center (1–800–548–6132). The PIC is
also available for design assistance and detailed
product information at this number. These models do
a good job of predicting small-signal ac and transient
performance under a wide variety of operating
conditions. They are not intended to model the
distortion characteristics of the amplifier, nor do they
attempt to distinguish between the package types in
their
small-signal
ac
performance.
Detailed
information about what is and is not modeled is
contained in the model file itself.
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THS3092 EVM
GND
J8
-5V
J7
5V
J9
FB1
FB2
C1
C2
5V
-5 V
C3
+
+
C4
TP1 TP2
R6
J2
R1
5V
U1:A
R2
J3
2
3
R3
8
1
J1
R5
Figure 70. THS3092 EVM Board Layout
(Top Layer)
R4
4
-5 V
J4
R7
R8
R9
6
5
7
R10
U1:B
J5
J6
R11
R12
Figure 69. THS3092 EVM Schematic
Figure 71. THS3092 EVM Board Layout
(Ground Plane)
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THS3096
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Figure 72. THS3092 EVM Board Layout
(Power Plane)
Figure 73. THS3092 EVM Board Layout
(Bottom Layer)
Table 3. THS3092 EVM Bill of Materials
THS3092DGN EVM
(1)
26
ITEM
DESCRIPTION
SMD SIZE
REFERENCE
DESIGNATOR
PCB
QTY
MANUFACTURER'S
PART NUMBER (1)
1
Bead, Ferrite, 3 A, 80 Ω
1206
FB1, FB2
2
(Steward) HI1206N800R-00
2
Cap. 22 µF, Tanatalum,
35 V, 10%
D
C1, C2
2
(AVX) TAJD685K035R
3
Cap. 0.1 µF, Ceramic, X7R, 16 V
0805
C3, C4
2
(AVX) 08055C104KAT2A
4
Resistor, 178 Ω, 1/8 W, 1%
0805
R1, R8
2
(KOA) RK73H2ALTD1780F
5
Resistor, 715 Ω, 1/8 W, 1%
0805
R6, R7
2
(KOA) RK73H2ALTD7150F
6
Open
1206
R4, R12
2
7
Resistor, 0 Ω, 1/4 W, 1%
1206
R2, R9
2
(KOA) RK73Z2BLTD
8
Resistor, 49.9 Ω, 1/4 W, 1%
1206
R1, R5, R10, R11
4
(KOA) RK73H2BLTD49R9F
9
Connector, edge, SMA PCB jack
J1, J2, J3, J4, J5, J6
6
(Johnson) 142-0701-801
10
Jack, banana, 0.25" dia. hole
J7, J8, J9
3
(SPC) 813
11
Test point, black
TP1, TP2
2
(Keystone) 5001
12
IC, THS3092
U1
1
(TI) THS3092DDA
13
Board, printed-circuit
1
(TI) EDGE # 6446250 Rev. A
The manufacturer's part numbers were used for test purposes only.
Submit Documentation Feedback
THS3092
THS3096
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SLOS428B – DECEMBER 2003 – REVISED FEBRUARY 2006
THS3096 EVM
GND
J8
5V
J7
-5 V
J9
FB1
5V
FB2
C5
+
C1
C3
-5 V
C2
C4
+
TP1 TP2
R4
J1
R3
5V
U1:A
R1
J2
2
3
R2
14
4
R5
1
15
J3
Figure 75. THS3096 EVM Board Layout
(Top Layer)
R6
-5 V
J4
R9
R8
R7
12
11
J5
R12
U1:B
13
9
6
R11
J6
R10
R13
J10
JP1
R14
5V
R15
Figure 74. THS3096 EVM Schematic
Figure 76. THS3096 EVM Board Layout
(Ground Plane)
Submit Documentation Feedback
27
THS3092
THS3096
www.ti.com
SLOS428B – DECEMBER 2003 – REVISED FEBRUARY 2006
Figure 77. THS3096 EVM Board Layout
(Power Plane)
Figure 78. THS3096 EVM Board Layout
(Bottom Layer)
Table 4. THS3096 EVM Bill of Materials
THS3096PWP EVM
DESCRIPTION
SMD SIZE
REFERENCE
DESIGNATOR
PCB
QTY
MANUFACTURER'S
PART NUMBER
1
Bead, Ferrite, 3 A, 80 Ω
1206
FB1, FB2
2
(Steward) HI1206N800R-00
2
Cap. 22 µF, Tanatalum, 25 V, 10%
D
C1, C2
2
(AVX) TAJD226K025R
3
Cap. 0.1 µF, Ceramic, X7R, 50 V
0805
C3, C4
2
(AVX) 08055C104KAT2A
4
Cap. 0.1 µF, Ceramic, X7R, 50 V
1206
C5
1
(AVX) 12065C104KAT2A
5
Resistor, 100 Ω, 1/8W, 1%
0805
R13
1
(KOA) RK73H2ALTD1000F
6
Resistor, 178 Ω, 1/8 W, 1%
0805
R3, R8
2
(KOA) RK73H2ALTD1780F
7
Resistor, 715 Ω, 1/8 W, 1%
0805
R4, R9
2
(KOA) RK73H2ALTD7150F
8
Resistor, 20 kΩ, 1/8 W, 1%
0805
R14, R15
2
(KOA) RK73H2ALTD2002F
9
Open
1206
R6, R10
2
10
Resistor, 0 Ω, 1/4 W, 1%
1206
R1, R7
2
(KOA) RK73Z2BLTD
11
Resistor, 49.9 Ω, 1/4 W, 1%
1206
R2, R5, R11, R12
4
(KOA) RK73H2BLTD49R9F
12
Header, 0.1" ctrs, 0.025" sq. pins
2 pos.
JP1
1
(Sullins) PZC36SAAN
13
Shunts
JP1
1
(Sullins) SSC02SYAN
14
Connector, SMA PCB jack
J1, J2, J3, J4, J5, J6
6
(Amphenol) 901-144-8RFX
15
Jack, banana, 0.25" dia. hole
J7, J8, J9
3
(SPC) 813
16
Test point, red
J10
1
(Keystone) 5000
17
Test point, black
TP1, TP2
2
(Keystone) 5001
18
IC, THS3096
U1
1
(TI) THS3096PWP
19
Board, printed-circuit
1
(TI) EDGE # 6454586 Rev. A
ITEM
28
Submit Documentation Feedback
THS3092
THS3096
www.ti.com
SLOS428B – DECEMBER 2003 – REVISED FEBRUARY 2006
ADDITIONAL REFERENCE MATERIAL
• PowerPAD Made Easy, application brief (SLMA004)
• PowerPAD Thermally Enhanced Package, technical brief (SLMA002)
• Voltage Feedback vs Current Feedback Amplifiers, (SLVA051)
• Current Feedback Analysis and Compensation (SLOA021)
• Current Feedback Amplifiers: Review, Stability, and Application (SBOA081)
• Effect of Parasitic Capacitance in Op Amp Circuits (SLOA013)
• Expanding the Usability of Current-Feedback Amplifiers, by Randy Stephens, 3Q 2003 Analog Applications
Journal www.ti.com/sc/analogapps).
• Active Output Impedance for ADSL Line Drivers (SLOA100)
Submit Documentation Feedback
29
PACKAGE OPTION ADDENDUM
www.ti.com
6-Feb-2009
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
THS3092D
ACTIVE
SOIC
D
8
75
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
THS3092DDA
ACTIVE
SO
Power
PAD
DDA
8
75
Green (RoHS &
no Sb/Br)
CU SN
Level-1-260C-UNLIM
THS3092DDAG3
ACTIVE
SO
Power
PAD
DDA
8
75
Green (RoHS &
no Sb/Br)
CU SN
Level-1-260C-UNLIM
THS3092DDAR
ACTIVE
SO
Power
PAD
DDA
8
2500 Green (RoHS &
no Sb/Br)
CU SN
Level-1-260C-UNLIM
THS3092DDARG3
ACTIVE
SO
Power
PAD
DDA
8
2500 Green (RoHS &
no Sb/Br)
CU SN
Level-1-260C-UNLIM
THS3092DG4
ACTIVE
SOIC
D
8
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
THS3092DR
ACTIVE
SOIC
D
8
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
THS3092DRG4
ACTIVE
SOIC
D
8
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
THS3096D
ACTIVE
SOIC
D
14
50
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
THS3096DG4
ACTIVE
SOIC
D
14
50
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
THS3096DR
ACTIVE
SOIC
D
14
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
THS3096DRG4
ACTIVE
SOIC
D
14
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
THS3096PWP
ACTIVE
HTSSOP
PWP
14
90
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
THS3096PWPG4
ACTIVE
HTSSOP
PWP
14
90
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
THS3096PWPR
ACTIVE
HTSSOP
PWP
14
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
THS3096PWPRG4
ACTIVE
HTSSOP
PWP
14
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
75
Lead/Ball Finish
MSL Peak Temp (3)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
6-Feb-2009
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
25-Apr-2009
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
THS3092DDAR
SO
Power
PAD
DDA
THS3092DR
SOIC
THS3096DR
SOIC
THS3096PWPR
HTSSOP
SPQ
Reel
Reel
Diameter Width
(mm) W1 (mm)
A0 (mm)
B0 (mm)
K0 (mm)
P1
(mm)
W
Pin1
(mm) Quadrant
8
2500
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
D
8
2500
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
D
14
2500
330.0
16.4
6.5
9.0
2.1
8.0
16.0
Q1
PWP
14
2000
330.0
12.4
6.8
5.4
1.6
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
25-Apr-2009
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
THS3092DDAR
SO PowerPAD
DDA
8
2500
346.0
346.0
29.0
THS3092DR
SOIC
D
8
2500
346.0
346.0
29.0
THS3096DR
SOIC
D
14
2500
346.0
346.0
33.0
THS3096PWPR
HTSSOP
PWP
14
2000
346.0
346.0
29.0
Pack Materials-Page 2
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