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ADS1225
¨
ADS1226
¨ www.ti.com
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SBAS346C – MAY 2006 – REVISED JANUARY 2009
24-Bit Analog-to-Digital Converter with One- and Two-Channel Differential Inputs and Internal Oscillator
1
FEATURES
2
•
100SPS Data Rate (High-Speed Mode)
•
Single-Cycle Settling
•
Easy Conversion Control with START Pin
•
Automatic Shutdown
•
Low Noise: 4
µ
V
RMS
Mode)
Noise (High-Resolution
•
Input Multiplexer with Two Differential
Channels (ADS1226)
•
Voltage Reference Supports Ratiometric
Measurements
•
Self-Calibrating
•
Simple Read-Only 2-Wire Serial Interface
•
Internal High-Impedance Input Buffer
•
Internal Temperature Sensor
•
Internal Oscillator
•
Low-Power: 1mW While Operating, < 1
µ
A
During Shutdown
•
Analog and Digital Supplies: 2.7V to 5.5V
APPLICATIONS
•
Hand-Held Instrumentation
•
Portable Medical Equipment
•
Industrial Process Control
TEMPEN AVDD
DESCRIPTION
The ADS1225 and ADS1226 are 24-bit delta-sigma analog-to-digital (A/D) converters.
They offer excellent performance, ease-of-use, and low power in a small 4mm × 4mm QFN package and are well-suited for demanding high-resolution measurements, especially in portable and other space-saving and power-constrained applications.
The ADS1225 and ADS1226 convert on command using a dedicated START pin. Simply pulse this pin to initiate a conversion. Data is read in a single cycle for retrieval over a 2-wire serial interface that easily connects to popular microcontrollers like the
MSP430.
After the conversion completes, the
ADS1225 and ADS1226 automatically shuts down all circuitry.
Internal features include a two-channel multiplexer
(ADS1226), selectable input buffer, temperature sensor, and oscillator. The full-scale range is defined by the external voltage reference with support provided for up to a 5V differential input signal. Two operating modes allow for speed (100SPS data rate,
15
µ
V
RMS noise) or resolution (4
µ
V
RMS noise, 16SPS data rate).
The ADS1225/6 supports 2.7 to 5.5V analog and digital supplies. Power consumption is 1mW while converting with 3V supplies. The ADS1225 and
ADS1226 are fully specified over an extended industrial temperature range of –40°C to +105°C.
VREFP VREFN DVDD
START
AINP1
AINN1
AINP2
AINN2
MUX
Buffer
DS
ADC
Serial Interface
SCLK
DRDY/DOUT
Oscillator
MODE
ADS1226 Only
MUX BUFEN GND
ADS1225
ADS1226
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Copyright © 2006–2009, Texas Instruments Incorporated
ADS1225
ADS1226
SBAS346C – MAY 2006 – REVISED JANUARY 2009 .......................................................................................................................................................
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This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
ORDERING INFORMATION
For the most current package and ordering information, see the Package Option Addendum located at the end of this data sheet or see the TI web site at www.ti.com.
ABSOLUTE MAXIMUM RATINGS
(1)
Over operating free-air temperature range, unless otherwise noted.
AVDD to GND
DVDD to GND
Input current
Analog input voltage to GND
Digital input voltage to GND
Maximum junction temperature
Operating temperature range
Storage temperature range
ADS1225, ADS1226
–0.3 to +6
–0.3 to +6
100, momentary
10, continuous
–0.3 to AVDD +0.3
–0.3 to AVDD +0.3
+150
–55 to +125
–50 to +150
(1) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those specified is not implied.
UNIT
V
V mA mA
V
V
°C
°C
°C
2
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SBAS346C – MAY 2006 – REVISED JANUARY 2009
ELECTRICAL CHARACTERISTICS
All specifications at T
A
= –40°C to +105°C, AVDD = +5V, DVDD = +3V, and V
REF
= +5V, unless otherwise noted.
TEST CONDITIONS MIN
ADS1225, ADS1226
TYP MAX PARAMETER
Analog Input
Full-scale input voltage ±V
REF
Absolute input voltage
Differential input impedance
AINP – AINN
Buffer off; AINP, AINN with respect to GND
Buffer on; AINP, AINN with respect to GND
Buffer off
Buffer on
Buffer off
GND – 0.1
GND + 0.05
2
1
4
AVDD + 0.1
AVDD – 1.5
Common-mode input impedance
System Performance
Resolution
Data rate
Integral nonlinearity (INL)
Offset error
Offset error drift
Gain error
Gain error drift
Common-mode rejection
Analog power-supply rejection
Digital power-supply rejection
Noise
High-Speed mode
High-Resolution mode
End-point fit
At dc
At dc, ± 10% Δ in AVDD
At dc, DVDD = 2.7V to 5.5V
High-Speed mode
High-Resolution mode
24
75
12
85
100
16
0.0005
60
0.3
0.004
0.3
95
95
80
1.5
0.4
125
22
0.0020
200
0.025
UNIT
V
V
V
M
Ω
G Ω
M Ω
Bits
SPS
(1)
SPS
(1)
% of FSR
(2)
µ
V
µ
V/°C
% ppm/°C dB dB dB ppm of FSR, rms ppm of FSR, rms
Temperature Sensor
Temperature sensor voltage
Temperature sensor coefficient
Voltage Reference Input
Reference input voltage
Negative reference input
Positive reference input
Voltage reference impedance
T
A
= +25°C
V
REF
= VREFP – VREFN 0.5
GND – 0.1
VREFN + 0.5
106
360
1.5
AVDD
VREFP – 0.5
AVDD + 0.1
mV
µ
V/°C
V
V
V
M Ω
(1) SPS = samples per second.
(2) FSR = full-scale range = 2 × V
REF
.
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ADS1226
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ELECTRICAL CHARACTERISTICS (continued)
All specifications at T
A
= –40°C to +105°C, AVDD = +5V, DVDD = +3V, and V
REF
= +5V, unless otherwise noted.
TEST CONDITIONS MIN
ADS1225, ADS1226
TYP MAX PARAMETER
Digital Input/Output
V
IH
V
IL
Logic levels
V
OH
V
OL
Input leakage
Power Supply
AVDD
DVDD
I
OH
= 1mA
I
OL
= 1mA
0.8 DVDD
GND – 0.1
0.8 DVDD
2.7
2.7
DVDD + 0.1
0.2 DVDD
0.2 DVDD
±10
5.5
5.5
AVDD current
DVDD current
Total power dissipation
Shutdown
AVDD = 5V, converting, buffer off
AVDD = 5V, converting, buffer on
AVDD = 3V, converting, buffer off
AVDD = 3V, converting, buffer on
Shutdown
DVDD = 5V, converting
DVDD = 3V, converting
AVDD = 5V, DVDD = 3V, buffer off
AVDD = DVDD = 3V, buffer off
< 1
90
55
1.6
1
< 1
285
405
265
385
2.5
Temperature Range
Specified
Operating
Storage
–40
–55
–60
+105
+125
+150
UNIT
V
µ
A
µ
A
µ
A
µ
A
µ
A
µ
A
V
µ
A
µ
A mW mW
°C
°C
°C
V
V
V
V
µ
A
4
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SBAS346C – MAY 2006 – REVISED JANUARY 2009
PIN CONFIGURATION
RGV PACKAGE
QFN-16, 4.0mm × 4.0mm
(TOP VIEW)
START
SCLK
DRDY/DOUT
BUFEN
3
4
1
2
ADS1225
12 GND
10
9
11 AINN1
AINP1
NC
NAME
START
SCLK
TERMINAL
NO.
1
2
DRDY/DOUT 3
BUFEN
GND
TEMPEN
MODE
NC
NC
AINP1
AINN1
GND
VREFN
VREFP
AVDD
DVDD
8
9
10
11
12
13
14
15
16
6
7
4
5
PIN DESCRIPTIONS—ADS1225
ANALOG/DIGITAL
INPUT/OUTPUT
Digital Input
Digital Input
Digital Output
Digital Input
Ground
Digital Input
Digital Input
Analog Input
Analog Input
Ground
Analog Input
Analog Input
Analog
Digital
DESCRIPTION
High: Start conversions; Low: Shutdown
Serial clock input
Dual-purpose output:
Data ready: indicates valid data by going low.
Data output: outputs data, MSB first, on the rising edge of SCLK.
Enables buffer after MUX
Analog and digital ground
Selects temperature sensor input from MUX
Selects between High-Speed and High-Resolution modes
No connect
No connect
Analog channel 1 positive input
Analog channel 1 negative input
Analog and digital ground
Negative reference input
Positive reference input
Analog power supply
Digital power supply
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ADS1226
SBAS346C – MAY 2006 – REVISED JANUARY 2009 .......................................................................................................................................................
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RGV PACKAGE
QFN-16, 4.0mm × 4.0mm
(TOP VIEW)
START
SCLK
DRDY/DOUT
BUFEN
3
4
1
2
ADS1226
12 GND
10
9
11 AINN1
AINP1
AINN2
NAME
START
SCLK
TERMINAL
NO.
1
2
DRDY/DOUT 3
BUFEN
MUX
TEMPEN
MODE
AINP2
AINN2
AINP1
AINN1
GND
VREFN
VREFP
AVDD
DVDD
8
9
10
11
12
13
14
15
16
6
7
4
5
PIN DESCRIPTIONS—ADS1226
ANALOG/DIGITAL
INPUT/OUTPUT
Digital Input
Digital Input
Digital Output
Digital Input
Digital Input
Digital Input
Digital Input
Analog Input
Analog Input
Analog Input
Analog Input
Ground
Analog Input
Analog Input
Analog
Digital
DESCRIPTION
High: Start conversions; Low: Shutdown
Serial clock input
Dual-purpose output:
Data ready: indicates valid data by going low.
Data output: outputs data, MSB first, on the rising edge of SCLK.
Enables buffer after MUX
Selects analog input from MUX
Selects temperature sensor input from MUX
Selects between High-Speed and High-Resolution modes
Analog channel 2 positive input
Analog channel 2 negative input
Analog channel 1 positive input
Analog channel 1 negative input
Analog and digital ground
Negative reference input
Positive reference input
Analog power supply
Digital power supply
6
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SBAS346C – MAY 2006 – REVISED JANUARY 2009
TYPICAL CHARACTERISTICS
At T
A
= +25°C, AVDD = +5V, DVDD = +3V, and V
REF
= +5V, unless otherwise noted.
350
ANALOG CURRENT vs TEMPERATURE
Buffer Off
325
AVDD = 5V
300
275
250
225
200
-50 -25 0 25 50
AVDD = 3V
75 100 125
120
105
90
75
60
45
30
-55
Figure 1.
DIGITAL CURRENT vs TEMPERATURE
AVDD = 5V
-25
5 35 65
AVDD = 3V
95 125
110
100
90
80
70
60
50
40
2.5
Figure 3.
DIGITAL CURRENT vs SUPPLY VOLTAGE
3.0
5.0
3.5
4.0
4.5
DVDD Supply Voltage (V)
Figure 5.
5.5
500
ANALOG CURRENT vs TEMPERATURE
Buffer On
AVDD = 5V
450
400
350
300
-50 -25
450
400
350
300
250
0 25 50 75
AVDD = 3V
100 125
Figure 2.
ANALOG CURRENT vs SUPPLY VOLTAGE
Buffer On
Buffer Off
200
2.5
3.0
3.5
4.0
4.5
AVDD Supply Voltage (V)
Figure 4.
5.0
5.5
TEMPERATURE SENSOR VOLTAGE vs TEMPERATURE
150
140
130
120
110
100
90
80
70
-55 -25
5 35 65 95 125
Figure 6.
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ADS1226
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TYPICAL CHARACTERISTICS (continued)
At T
A
= +25°C, AVDD = +5V, DVDD = +3V, and V
REF
= +5V, unless otherwise noted.
15
INTEGRAL NONLINEARITY vs INPUT VOLTAGE
Buffer Off
°
10
°
5
0
-5
-10
-15
-5 -4 -3 -2 -1 0 1
Input Voltage, V
IN
(V)
Figure 7.
2
OFFSET vs TEMPERATURE
3
20
10
4 5
0
-10
-20
-30
-40
-50 -25
0 25 50 75 100
2.5
2.0
1.5
1.0
0.5
Figure 9.
NOISE vs INPUT VOLTAGE
3.5
3.0
High-Speed Mode
Buffer Off
0
-5 -4 -3 -2 -1 0 1
Input Voltage, V
IN
(V)
2
Figure 11.
3 4
125
5
INTEGRAL NONLINEARITY vs INPUT VOLTAGE
10
8
6
4
2
0
-2
-4
-6
-8
-10
-3.5
-2.5
°
°
Buffer On
2.5
3.5
-1.5
-0.5
0.5
Input Voltage, V
IN
(V)
Figure 8.
1.5
GAIN ERROR vs TEMPERATURE
0.002
0.001
0
-0.001
-0.002
-50 -25 0 25 50 75 100 125
3.0
2.5
Figure 10.
NOISE vs INPUT VOLTAGE
High-Speed Mode
Buffer On
2.0
1.5
1.0
0.5
0
-3.5
-2.5
-1.5
-0.5
0.5
Input Voltage, V
IN
(V)
Figure 12.
1.5
2.5
3.5
8
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SBAS346C – MAY 2006 – REVISED JANUARY 2009
TYPICAL CHARACTERISTICS (continued)
At T
A
= +25°C, AVDD = +5V, DVDD = +3V, and V
REF
= +5V, unless otherwise noted.
NOISE vs INPUT VOLTAGE
0.5
0.4
0.3
0.2
0.1
0.9
0.8
0.7
0.6
High-Resolution Mode
Buffer Off
0
-5 -4 -3 -2 -1
0 1
Input Voltage, V
IN
(V)
2
Figure 13.
3
NOISE HISTOGRAM
250
High-Speed Mode
200
4
150
100
50
120
0
Output Code
Figure 15.
HIGH-SPEED MODE DATA RATE vs TEMPERATURE
5
0.5
0.4
0.3
0.2
0.1
NOISE vs INPUT VOLTAGE
0.7
0.6
High-Resolution Mode
Buffer On
0
-3.5
-2.5
-1.5
-0.5
0.5
Input Voltage, V
IN
(V)
Figure 14.
1.5
2.5
3.5
30
20
10
60
50
40
NOISE HISTOGRAM
80
High-Resolution Mode
70
0
-30 -25 -20 -15 -10 -5 0 5
Output Code
10 15 20 25 30
Figure 16.
HIGH-RESOLUTION MODE DATA RATE vs TEMPERATURE
21
110
100
90
80
70
-50 -25
0 25 50
Temperature (°C)
Figure 17.
75 100 125
18
15
12
-50 -25
0 25 50
Temperature (°C)
Figure 18.
75 100 125
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ADS1225
ADS1226
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OVERVIEW
The ADS1225 and ADS1226 are 24-bit delta-sigma
A/D converters.
shows a conceptual diagram of the device. The ADS1225 has a single channel, while the ADS1226 allows for one of two input channels to be selected through a multiplexer. A buffer can also be selected to increase the input impedance. The modulator measures the differential input signal V
IN
= (AINP – AINN) against the differential reference V
REF
= (VREFP – VREFN). The full-scale input range is ±V
REF
. A 2-wire serial interface indicates conversion completion and provides the user with the output data. An internal oscillator allows for free-running of the ADS1225 and
ADS1226.
Two other pins are used to control the operation of the ADS1225 and ADS1226. The START pin initiates conversions. The MODE pin puts the device into one of two modes. In High-Speed mode, the device gives data at 100 samples per second (SPS).
In
High-Resolution mode, data comes out at 16SPS with lower noise.
In both modes, the device has single-cycle settling, reducing the latency of the output data.
ANALOG INPUTS (AINx+, AINx–)
The input signal to be measured is applied to the input pins AINPx and AINNx. The positive internal input is generalized as AINP, and the negative internal input is generalized as AINN. The signal is selected though the input MUX, which is controlled by
MUX, as shown in
. The ADS1225 and
ADS1226 accept differential input signals, but can also measure unipolar signals. When measuring unipolar (or single-ended) signals with respect to ground, connect the negative input (AINN) to ground and connect the input signal to the positive input
(AINP). Note that when the ADS1225 and ADS1226 are configured this way, only half of the converter full-scale range is used since only positive digital output codes are produced. An input buffer can be selected to increase the input impedance of the A/D converter with the BUFEN pin.
Table 1. Input Channel Selection with MUX
DIGITAL PIN
MUX
0
1
SELECTED ANALOG INPUTS
POSITIVE INPUT NEGATIVE INPUT
AINP1
AINP2
AINN1
AINN2
TEMPEN VREFP VREFN
START
AINP1
AINN1
AINP2
AINN2
MUX
AINP
AINN
Buffer
S
V
IN
S
V
REF
DS
ADC
Serial Interface
SCLK
DRDY/DOUT
Oscillator
MODE
ADS1226 Only
MUX BUFEN
Figure 19. Conceptual Diagram of the ADS1225 and ADS1226
10
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SBAS346C – MAY 2006 – REVISED JANUARY 2009
Analog Input Measurement Without the Input
Buffer
With the buffer disabled by setting the BUFEN pin low, the ADS1225 and ADS1226 measure the input signal using internal capacitors that are continuously charged and discharged.
shows a simplified schematic of the ADS1225/6 input circuitry, with
showing the on/off timings of the switches. The S
1 switches close during the input sampling phase. With S
1 closed, C
A1 charges to
AINP, C
A2 charges to AINN, and C
B charges to (AINP
– AINN). For the discharge phase, S
1 opens first and then S
2 closes.
C
A1 and C
A2 approximately VDD/2 and C
B discharge to discharges to 0V. The constant charging of the input capacitors presents a load on the inputs that can be represented by effective impedances.
shows the input circuitry with the capacitors and switches of
by their effective impedances.
AINPx
AINNx
AVDD/2
Zeff = t
SAMPLE
/C
A1
= 4MW
Zeff = t
SAMPLE
/C
B
= 2MW
Zeff = t
SAMPLE
/C
A2
= 4MW
AVDD/2
Figure 22. Effective Analog Input Impedances with the Buffer Off
ESD diodes protect the inputs. To keep these diodes from turning on, make sure the voltages on the input pins do not go below GND by more than 100mV, and likewise do not exceed VDD by 100mV. This limitation is shown in
ESD Protection
AVDD
AVDD/2
C
A1
3pF
GND
*
100mV t
(AINP, AINN) t
VDD
)
100mV
(1)
AINP
S
1
S
2
AINPx
AINNx
AVDD
MUX
AINN
S
1
C
B
6pF
Figure 20. Simplified Input Structure with the
Buffer Turned Off
S
2
AVDD/2
C
A2
3pF
Analog Input Measurement with the Input Buffer
When the buffer is enabled by setting the BUFEN pin high, a low-drift, chopper-stabilized input buffer is used to achieve very high input impedance. The buffer charges the input sampling capacitors, thus removing the load from the measurement. Because the input buffer is chopper-stabilized, the charging of parasitic capacitances causes the charge to be carried away, as if by resistance.
The input impedance can be modeled by a single resistor, as shown in
Figure 23 . Note that when START is low,
the buffer must be disabled to prevent loading of the inputs.
t
SAMPLE
ON
S
1
OFF
ON
S
2
OFF
Figure 21. S
1
and S
2
Switch Timing for
AINP
AINN
1GW
Figure 23. Effective Analog Input Impedances with the Buffer On
Note also that the analog inputs (listed in the
table as Absolute Input
Range) must remain between GND + 0.05V to AVDD
– 1.5V. Exceeding this range degrades linearity and results in performance outside the specified limits.
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TEMPERATURE SENSOR
Internal diodes provide temperature-sensing capability. By setting the TEMPEN pin high, the selected analog inputs are disconnected and the inputs to the A/D converter are connected to the anodes of two diodes scaled to 1x and 64x in current and size inside the MUX, as shown in
. By measuring the difference in voltage of these diodes, temperature changes can be inferred from a baseline temperature.
Typically, the difference in diode voltages is 106mV at +25°C, with a temperature coefficient of 360
µ
V/°C. A similar structure is used in the MSC1210 for temperature measurement. For more information, see TI application report SBAA100 ,
Using the MSC121x as a High-Precision Intelligent
Temperature Sensor, available for download at www.ti.com
.
TEMPEN
VOLTAGE REFERENCE INPUTS
(VREFP, VREFN)
The voltage reference used by the modulator is generated from the voltage difference between
VREFP and VREFN: V
REF
= VREFP – VREFN. The reference inputs use a structure similar to that of the analog inputs. A simplified diagram of the circuitry on the reference inputs is shown in
switches and capacitors can be modeled with an effective impedance of 1.5M
Ω.
AVDD
VREFP VREFN
AVDD
ESD
Protection
AVDD
16pF
Zeff = 1.5MW
8I 1I
AINP
AINN
Figure 25. Simplified Reference Input Circuitry
1X 8X
AINP1
AINN1
AINP2
AINN2
ESD diodes protect the reference inputs. To prevent these diodes from turning on, make sure the voltages on the reference pins do not go below GND by more than 100mV, and likewise, do not exceed VDD by
100mV. This limitation is shown in
:
MUX
Figure 24. Measurement of the Temperature
Sensor in the Input
GND
*
100mV t
(VREFP, VREFN) t
VDD
)
100mV
(2)
For best performance, bypass the voltage reference inputs with a 0.1
µ
F capacitor between VREFP and
VREFN. Place the capacitor as close as possible to the pins.
The differential voltage reference inputs and the wide range of operation (V
REF can support up to AVDD) make ratiometric measurements easy to implement.
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SBAS346C – MAY 2006 – REVISED JANUARY 2009
INTERNAL OSCILLATOR
The ADS1225 and ADS1226 have an internal oscillator and run without an external crystal or oscillator.
DATA READY/DATA OUTPUT (DRDY/DOUT)
This digital output pin serves two purposes. First, it indicates when new data is ready by going LOW.
Afterwards, on the first rising edge of SCLK, the
DRDY/DOUT pin changes function and begins to output the conversion data, most significant bit (MSB) first. Data is shifted out on each subsequent SCLK rising edge. After all 24 bits have been retrieved, the pin can be forced high with an additional SCLK. It then stays high until new data is ready. This configuration is useful when polling on the status of
DRDY/DOUT to determine when to begin data retrieval.
MODE
The ADS1225 and ADS1226 have two modes of operation, allowing for High-Speed or
High-Resolution. By taking the MODE pin high, the data rate is approximately 100Hz with an rms noise of
15
µ
V. When the MODE pin is low, the ADS1225 and
ADS1226 average multiple samples to increase the noise performance to 4
µ
V of rms noise with a data rate of 16Hz.
shows the MODE pin operation.
Table 2. MODE Pin Operation for the ADS1225 and ADS1226
MODE PIN
0
1
MODE
High-Resolution
High-Speed
DATA RATE
16SPS
100SPS
NOISE
4
µ
Vrms
15
µ
Vrms
SERIAL CLOCK INPUT (SCLK)
This digital input shifts serial data out with each rising edge. There is hysteresis built into this input, but care should still be taken to ensure a clean signal. Glitches or slow-rising signals can cause unwanted additional shifting. For this reason, it is best to make sure the rise-and-fall times of SCLK are less than 50ns.
START
The START pin provides easy and precise control of conversions. Pulse the START pin high to begin a conversion as shown in
and
. The completion of the conversion is indicated by the
DRDY/DOUT pin going low. Once the conversion completes, the ADS1225 and ADS1226 automatically shut down to save power. They stay shut down until
START is once again taken high to begin a new conversion.
t
START
START
Conversion Data
DRDY/DOUT t
CONV
SCLK
ADS1225/6
Status
Converting
Figure 26. Controlling Conversion with the START Pin
SYMBOL
t
START t
CONV
Table 3. START Pin Conversion Times for
DESCRIPTION
Minimum START pulse to initiate a conversion
Conversion time High-Speed mode
Conversion time High-Resolution mode
MIN
17
8.0
45.5
MAX
13.3
83.3
Shutdown
UNITS
µ s ms ms
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The ADS1225 and ADS1226 can be configured to continuously convert by holding the START pin high as shown in
Figure 27 . With START held high, a new
conversion starts immediately after the previous conversion completes. This configuration continues until the START pin is taken low. During calibration, the START pin must be kept high. Refer to the
section for details. Note that when
START is low, the buffer must be disabled to prevent loading of the inputs.
Table 4. Ideal Output Code vs Input Signal
Input Signal V
IN
(AINP – AINN)
≥ +V
REF
)
V
REF
2 23
*
1
IDEAL OUTPUT CODE
(
(1)
)
7FFFFFh
000001h
0
*
V
REF
2 23
*
1
000000h
FFFFFFh
DATA FORMAT
The ADS1225 and ADS1226 output 24 bits of data in binary twos complement format. The least significant bit (LSB) has a weight of (V
REF
)/(2
23
– 1). The positive full-scale input produces an output code of
7FFFFFh and the negative full-scale input produces an output code of 800000h. The output clips at these codes for signals exceeding full-scale.
summarizes the ideal output codes for different input signals.
v *
V
REF ǒ 2 23
2 23
*
1
Ǔ
800000h
(1) Excludes effects of noise, INL, offset, and gain errors.
START Data Ready Data Ready
DRDY/DOUT
ADS1225/6
Status
Converting
SCLK held low in this example.
Converting Converting
Figure 27. Conversion with the START Pin High
Converting
14
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SBAS346C – MAY 2006 – REVISED JANUARY 2009
DATA RETRIEVAL
With the START pin high, the ADS1225 and
ADS1226 continuously convert the analog input signal. To retrieve data, wait until DRDY/DOUT goes low, as illustrated in
and
occurs, begin shifting out the data by applying
SCLKs. Data is shifted out MSB first. It is not required to shift out all 24 bits of data, but the data must be retrieved before the new data is updated (see t
2 else it will be overwritten.
) or
Avoid data retrieval during the update period.
DRDY/DOUT remain at the state of the last bit shifted out until it is taken high (see t
6
), indicating that new data is being updated. To avoid having DRDY/DOUT remain in the state of the last bit, shift a 25th SCLK to force DRDY/DOUT high (refer to
). This technique is useful when a host controlling the
ADS1225 and ADS1226 is polling DRDY/DOUT to determine when data is ready.
Data
DRDY/DOUT
SCLK
Data Ready t
DS
1
MSB
23 22 t
PD
21 t
SCLK t
SCLK t
CONV
24
LSB
0 t
HD
START Tied High
Figure 28. Data Retrieval Timing
SYMBOL
t
DS t
SCLK t
PD t
HD t
UP t
CONV
Table 5. Data Retrieval Times for
DESCRIPTION
DRDY/DOUT low to first SCLK rising edge
SCLK positive or negative pulse width
SCLK rising edge to new data bit valid: propagation delay
SCLK rising edge to old data bit valid: hold time
Data updating: no readback allowed
Conversion time (1/data rate), High-Speed mode
Conversion time (1/data rate), High-Resolution mode
MIN
0
100
0
29.5
8.0
45.5
Data
Data Ready
DRDY/DOUT 23 22 21 0
SCLK
MAX
50
49.2
13.3
83.3
1 24 25
25th SCLK to Force DRDY /DOUT High
Figure 29. Data Retrieval with DRDY/DOUT Forced High Afterwards
New Data Ready t
UP
New Data Ready
UNITS
ns ns ns ns
µ s ms ms
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ADS1226
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SELF-CALIBRATION
Self-calibration can be initiated at any time by applying two additional SCLKs after retrieving 24 bits of data; however, the START pin must be kept high prior to data conversion and remain high until the calibration completes.
and
illustrate the timing pattern.
The 25th SCLK will send
DRDY/DOUT high. The falling edge of the 26th SCLK will begin the calibration cycle. Additional SCLK pulses may be sent after the 26th SCLK; however, activity on SCLK should be minimized during calibration for best results.
When the calibration is complete, DRDY/DOUT goes low, indicating that new data is ready. There is no need to alter the analog input signal applied to the
ADS1225 and ADS1226 during calibration; the input pins are disconnected within the A/D converter and the appropriate signals are applied internally and automatically. The first conversion after a calibration is fully settled and valid for use. The time required for a calibration depends on two independent signals: the falling edge of SCLK and an internal clock derived from CLK. Variations in the internal calibration values change the time required for calibration (t
CAL the range given by the min/max specs.
) within
High
START
Data Ready After Calibration
23 DRDY/DOUT 23 22 21 0
Calibration Begins
24 25 26
SCLK
1
SYMBOL
t
CAL
Figure 30. Self-Calibration Timing
Table 6. Self-Calibration Time for
DESCRIPTION
First data ready after calibration
MIN
187 t
CAL
MAX
313
UNITS
ms
16
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SBAS346C – MAY 2006 – REVISED JANUARY 2009
EXPOSED THERMAL PAD
The exposed thermal pads of the ADS1225 and
ADS1226 are internally connected to GND. To protect the package from board stress, solder the exposed thermal pad to the printed circuit board (PCB) and leave it floating electrically. For further information, see Application Report SLAU271 , QFN/SON PCB
Attachment, available for download from www.ti.com
.
GENERAL RECOMMENDATIONS
APPLICATION INFORMATION
The ADS1225 and ADS1226 are high-resolution A/D converters. Achieving optimal device performance requires careful attention to the support circuitry and
PCB design.
shows the basic connections for the ADS1225 and ADS1226. As with any precision circuit, be sure to use good supply bypassing capacitor techniques. A smaller value ceramic capacitor in parallel with a larger value tantalum capacitor works well. Place the capacitors, in particular the ceramic ones, close to the supply pins. Use a ground plane and tie the ADS1225 and
ADS1226 GND pin and bypass capacitors directly to it. Avoid ringing on the digital inputs. Small resistors
(
≈
100 Ω) in series with the digital pins can help by controlling the trace impedance. Place these resistors at the source end.
Pay special attention to the reference and analog inputs. These inputs are critical to performance.
Bypass the voltage reference using similar techniques to the supply voltages. The quality of the reference directly affects the overall accuracy of the device. Make sure to use a low noise and low drift reference such as the REF1004 . Often, only a simple
RC filter is needed on the inputs. The circuit limits the higher frequency noise. Avoid low-grade dielectrics for the capacitors and place them as close as possible to the input pins. Keep the traces to the input pins short, and carefully watch how they are routed on the PCB.
After the power supplies and reference voltage have stabilized, issue a self-calibration command to minimize offset and gain errors.
+5V
REF1004
+3V
16 15 14 13
100W
100W
100W
100W
1
START
2
SCLK
3
DRDY/DOUT
ADS1226
4
BUFEN
100W
GND
12
AINN1
11
AINP1
10
AINN2
9
5 6 7 8
100W
100W
Figure 31. Basic Connections
220pF
301W
301W
220pF
Same as shown for AINP1 and AINN1.
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ADS1226
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SMALL INPUT SIGNALS
shows the schematic of the ADS1225 for measuring small output signals such as the output of a bridge sensor or load cell. In this application, the load cell is combined with the ADS1225 and an
MSP430 microcontroller. An OPA2333 is used to buffer the inputs and to provide the gain of the load cell signal. A 5V source is used as the reference and the excitation, although any clean source can create a proper ratiometric signal for the reference.
A typical load cell with a bridge sensitivity of 2mV/V using a 5V source would have a full-scale output of
10mV. The recommended gain of the OPA2333, for this load cell using low-drift resistors, would be 1 +
2R
F
/R
G
= 100.8V/V. This value gives a full-scale measurement of approximately 1V while keeping the noise contribution of the OPA2333 low. The noise is low enough compared to full-scale to create a several-thousand count weigh scale, even in
High-Speed mode. For better accuracy, this noise could be lowered through either additional filtering or using the High-Resolution mode.
It is important to make sure that the reference and inputs are clean from clocks or other periodic signals to prevent coupling. Isolate the analog from the digital supplies and grounds whenever possible.
+5V +3V
Load Cell
+5V
1/2
OPA2333
+5V AVDD
VREFP
VREFN
DVDD
START
SCLK
DRDY/DOUT
MSP430xxx
R
G
100W
R
F
4.99kW
R
F
4.99kW
1kW
1kW
AINP1
AINN1
ADS1225
MODE
BUFEN
TEMPEN
+3V
G = 1 +
2R
F
R
G
GND
1/2
OPA2333
Use low-drift resistors
G
Figure 32. Using the OPA2333 as a Gain Stage in Front of the ADS1225
GND
18
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SBAS346C – MAY 2006 – REVISED JANUARY 2009
LARGE INPUT SIGNALS
Many industrial applications require measurement of signals that go beyond 5V. The ADS1225 can be used to measure large input signals with the help of an INA159. The precision, level translation differential amplifier converts a ±10V input to a 5V input scale.
This design allows systems to be run from a single
5V supply without the need for higher voltage supplies for signal conditioning.
shows a basic schematic. The negative input of the INA159 is grounded while the positive input is allowed to swing from –10V to +10V.
Similarly, the negative input of the ADS1225 is grounded while the positive input swings from 0.5V to
+4.5V given the useful V
OUT swing of the INA159.
The larger signal is easily measured without the need for extra ±10V supplies. See the INA159 data sheet for additional details.
+5V +3V
V
IN
±
10V
-IN
100kW
V+
20kW
SENSE
OUT
REF 2
REF 1
1kW
+5V
AVDD
VREFP
VREFN
DVDD
START
SCLK
DRDY/DOUT
AINP1
AINN1
ADS1225
MODE
BUFEN
TEMPEN
+3V
GND
+IN
100kW
INA159
V-
40kW
40kW
Figure 33. With the Help of an INA159, the ADS1225 Measures ±10V Signals
MSP430xxx
GND
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ADS1226
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DRDY/DOUT
SCLK
START Tied High
1
23
MSB
22 21
24
0
LSB
(a) Data Retrieval
DRDY/DOUT
SCLK
START Tied High
1
23 22 21 0
24 25
(b) Data Retrieval with DRDY /DOUT Forced High Afterwards
Data Ready
After Calibration
DRDY/DOUT
SCLK
START Tied High
1
23 22 21 0
Begin Calibration
24 25 26
(c) Self-Calibration
START
DRDY/DOUT
SCLK
DIGITAL PIN
START
BUFEN
MUX (ADS1226 only)
TEMPEN
MODE
23 22 21 20
1
(d) Single Conversions with START Pulse
Figure 34. Summary of Serial Interface Waveforms
Table 7. Digital Pin Operations
PIN NO.
1
4
5
6
7
0
Shutdown Mode
Buffer Off
AINP1 – AINN1 Input
Temperature Sensor Off
High-Resolution Mode
INPUT
1
Start Conversion
Buffer On
AINP2 – AINN2 Input
Temperature Sensor On
High-Speed Mode
20
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SBAS346C – MAY 2006 – REVISED JANUARY 2009
Revision History
Changes from Revision B (August 2007) to Revision C ................................................................................................
Page
•
Added last sentence to first paragraph of Analog Input Measurement with the Input Buffer section describing the
START mode
•
Added last sentence to second paragraph of Start section describing the START mode
.................................................. 14
Changes from Revision A (April 2007) to Revision B ....................................................................................................
Page
•
Changed effective impedance from 250k
Ω to 1.5MΩ in last sentence of
section ..................... 12
•
Changed
•
Added text to end of
section regarding keeping the START pin high during calibration
........................................ 14
•
Changed
title
•
Changed text in first paragraph of
•
Changed
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PACKAGE OPTION ADDENDUM
25-Nov-2008
PACKAGING INFORMATION
Orderable Device
ADS1225IRGVR
ADS1225IRGVRG4
ADS1225IRGVT
ADS1225IRGVTG4
ADS1226IRGVR
ADS1226IRGVRG4
ADS1226IRGVT
ADS1226IRGVTG4
Status
(1)
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
Package
Type
QFN
QFN
QFN
QFN
QFN
QFN
QFN
QFN
Package
Drawing
RGV
RGV
RGV
RGV
RGV
RGV
RGV
RGV
Eco Plan
(2)
Pins Package
Qty
16 2500 Green (RoHS & no Sb/Br)
Lead/Ball Finish MSL Peak Temp
(3)
CU NIPDAU Level-2-260C-1 YEAR
16 CU NIPDAU Level-2-260C-1 YEAR
16
2500 Green (RoHS & no Sb/Br)
250 Green (RoHS & no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR
16 CU NIPDAU Level-2-260C-1 YEAR
16
16
16
16
250 Green (RoHS & no Sb/Br)
2500 Green (RoHS & no Sb/Br)
2500 Green (RoHS & no Sb/Br)
250 Green (RoHS & no Sb/Br)
250 Green (RoHS & no Sb/Br)
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
www.ti.com
TAPE AND REEL INFORMATION
PACKAGE MATERIALS INFORMATION
25-Nov-2008
*All dimensions are nominal
Device
ADS1225IRGVR
ADS1225IRGVT
ADS1226IRGVR
ADS1226IRGVT
Package
Type
Package
Drawing
QFN
QFN
QFN
QFN
RGV
RGV
RGV
RGV
Pins
16
16
16
16
SPQ
2500
250
2500
250
Reel
Diameter
(mm)
Reel
Width
W1 (mm)
330.0
12.4
180.0
330.0
180.0
12.4
12.4
12.4
A0 (mm)
4.3
4.3
4.3
4.3
B0 (mm)
4.3
4.3
4.3
4.3
K0 (mm) P1
(mm)
W
(mm)
Pin1
Quadrant
1.5
1.5
1.5
1.5
8.0
8.0
8.0
8.0
12.0
12.0
12.0
12.0
Q2
Q2
Q2
Q2
Pack Materials-Page 1
www.ti.com
PACKAGE MATERIALS INFORMATION
25-Nov-2008
*All dimensions are nominal
Device
ADS1225IRGVR
ADS1225IRGVT
ADS1226IRGVR
ADS1226IRGVT
Package Type Package Drawing Pins
QFN
QFN
QFN
QFN
RGV
RGV
RGV
RGV
16
16
16
16
SPQ
2500
250
2500
250
Length (mm) Width (mm) Height (mm)
346.0
190.5
346.0
190.5
346.0
212.7
346.0
212.7
29.0
31.8
29.0
31.8
Pack Materials-Page 2
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