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FEATURES
•
Controlled Baseline
– One Assembly/Test Site, One Fabrication
Site
•
Extended Temperature Performance of –40
°
C to 125
°
C (TLC2543Q) and –55
°
C to 125
°
C
(TLC2543M)
•
Enhanced Diminishing Manufacturing Sources
(DMS) Support
•
Enhanced Product Change Notification
•
Qualification Pedigree
(1)
•
12-Bit-Resolution Analog-to-Digital Converter
(ADC)
•
10-
µ
s Conversion Time Over Operating
Temperature
•
11 Analog Input Channels
•
Three Built-In Self-Test Modes
•
Inherent Sample-and-Hold Function
•
Linearity Error . . .
±
1 LSB Max
•
On-Chip System Clock
•
End-of-Conversion (EOC) Output
•
Unipolar or Bipolar Output Operation (Signed
Binary With Respect to 1/2 the Applied
Voltage Reference)
•
Programmable Most Significant Bit (MSB) or
Least Significant Bit (LSB) First
(1) Component qualification in accordance with JEDEC and industry standards to ensure reliable operation over an extended temperature range. This includes, but is not limited to, Highly Accelerated Stress Test (HAST) or biased 85/85, temperature cycle, autoclave or unbiased HAST, electromigration, bond intermetallic life, and mold compound life. Such qualification testing should not be viewed as justifying use of this component beyond specified performance and environmental limits.
TLC2543-EP
12-BIT ANALOG-TO-DIGITAL CONVERTER
WITH SERIAL CONTROL AND 11 ANALOG INPUTS
SGLS125A – JULY 2002 – REVISED NOVEMBER 2006
•
Programmable Power Down
•
Programmable Output Data Length
•
CMOS Technology
•
Application Report Available
(2)
AIN0
AIN1
AIN2
AIN3
AIN4
AIN5
AIN6
AIN7
AIN8
GND
DW PACKAGE
(TOP VIEW)
6
7
4
5
8
9
10
1
2
3
17
16
15
14
13
12
11
20
19
18
V
CC
EOC
I/O CLOCK
DATA INPUT
DATA OUT
CS
REF +
REF −
AIN10
AIN9
(2)
Microcontroller Based Data Acquisition Using the TLC2543
12-bit Serial-Out ADC (SLAA012)
DESCRIPTION/ORDERING INFORMATION
The TLC2543 is a 12-bit, switched-capacitor, successive-approximation, analog-to-digital converter (ADC). This device, with three control inputs [chip select (CS), input-output clock (I/O CLOCK), and address input (DATA
INPUT)], is designed for communication with the serial port of a host processor or peripheral through a serial
3-state output. The device allows high-speed data transfers from the host.
In addition to the high-speed converter and versatile control capability, the device has an on-chip 14-channel multiplexer that can select any 1 of 11 inputs or any 1 of 3 internal self-test voltages. The sample-and-hold function is automatic. At the end of conversion, the end-of-conversion (EOC) output goes high to indicate that conversion is complete. The converter incorporated in the device features differential high-impedance reference inputs that facilitate ratiometric conversion, scaling, and isolation of analog circuitry from logic and supply noise.
A switched-capacitor design allows low-error conversion over the full operating temperature range.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Copyright © 2002–2006, Texas Instruments Incorporated
TLC2543-EP
12-BIT ANALOG-TO-DIGITAL CONVERTER
WITH SERIAL CONTROL AND 11 ANALOG INPUTS
SGLS125A – JULY 2002 – REVISED NOVEMBER 2006 www.ti.com
T
A
–40
°
C to 125
°
C
-55
°
C to 125
°
C
SOP – DW
SSOP - DB
ORDERING INFORMATION
PACKAGE
(1)
Tape and reel
Tape and Reel
ORDERABLE PART NUMBER
TLC2543QDWREP
TLC2543MDBREP
TOP-SIDE MARKING
TLC2543QEP
TLC2543MEP
(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package.
FUNCTIONAL BLOCK DIAGRAM
REF +
14
REF −
13
Sample-and-
Hold
Function
12-Bit
Analog-to-Digital
Converter
(Switched Capacitors)
AIN0
AIN1
AIN2
AIN3
AIN4
AIN5
AIN6
AIN7
AIN8
AIN9
AIN10
3
4
1
2
5
6
7
8
9
11
12
14-Channel
Analog
Multiplexer
4
Input Address
Register
12
Output
Data
Register
12
12-to-1 Data
Selector and
Driver
16
DATA
OUT
4
3
Self-Test
Reference
Control Logic and I/O
Counters
19
EOC
DATA
INPUT
17
I/O CLOCK
CS
18
15
2
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TLC2543-EP
12-BIT ANALOG-TO-DIGITAL CONVERTER
WITH SERIAL CONTROL AND 11 ANALOG INPUTS
SGLS125A – JULY 2002 – REVISED NOVEMBER 2006
TERMINAL FUNCTIONS
DESCRIPTION
TERMINAL
NAME NO.
AIN0
AIN1
AIN2
AIN3
AIN4
AIN5
AIN6
AIN7
AIN8
AIN9
AIN10
6
7
4
5
1
2
3
8
9
11
12
CS 15
I/O
DATA INPUT
DATA OUT
EOC
GND
I/O CLOCK
REF+
REF–
V
CC
17
16
19
10
18
14
13
20
I
Analog input. These 11 analog-signal inputs are internally multiplexed. The driving source impedance should be less than or equal to 50
Ω for 4.1-MHz I/O CLOCK operation, and be capable of slewing the analog input voltage into a capacitance of 60 pF.
I
I
I
I
I
O
O
Chip select. A high-to-low transition on CS resets the internal counters and controls and enables
DATA OUT, DATA INPUT, and I/O CLOCK. A low-to-high transition disables DATA INPUT and I/O
CLOCK within a setup time.
Serial-data input. A 4-bit serial address selects the desired analog input or test voltage to be converted next. The serial data is presented with the most significant bit (MSB) first and is shifted in on the first four rising edges of I/O CLOCK. After the four address bits are read into the address register, I/O CLOCK clocks the remaining bits in order.
The 3-state serial output for the A/D conversion result. DATA OUT is in the high-impedance state when CS is high and active when CS is low. With a valid CS, DATA OUT is removed from the high-impedance state and is driven to the logic level corresponding to the most significant bit/least significant bit (MSB/LSB) value of the previous conversion result. The next falling edge of I/O
CLOCK drives DATA OUT to the logic level corresponding to the next MSB/LSB, and the remaining bits are shifted out in order.
End of conversion. EOC goes from a high to a low logic level after the falling edge of the last I/O
CLOCK and remains low until the conversion is complete and the data is ready for transfer.
Ground. GND is the ground return terminal for the internal circuitry. Unless otherwise noted, all voltage measurements are with respect to GND.
Input/output clock. I/O CLOCK receives the serial input and performs the following four functions:
•
It clocks the eight input data bits into the input data register on the first eight rising edges of I/O
CLOCK with the multiplexer address available after the fourth rising edge.
•
On the fourth falling edge of I/O CLOCK, the analog input voltage on the selected multiplexer input begins charging the capacitor array and continues to do so until the last falling edge of the I/O
CLOCK.
•
It shifts the 11 remaining bits of the previous conversion data out on DATA OUT. Data changes on the falling edge of I/O CLOCK.
•
It transfers control of the conversion to the internal state controller on the falling edge of the last
I/O CLOCK.
Positive reference voltage. The upper reference voltage value (nominally V
CC
) is applied to REF+.
The maximum input voltage range is determined by the difference between the voltage applied to this terminal and the voltage applied to the REF– terminal.
Negative reference voltage. The lower reference voltage value (nominally ground) is applied to
REF–.
Positive supply voltage
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TLC2543-EP
12-BIT ANALOG-TO-DIGITAL CONVERTER
WITH SERIAL CONTROL AND 11 ANALOG INPUTS
SGLS125A – JULY 2002 – REVISED NOVEMBER 2006
Absolute Maximum Ratings
(1)
over operating free-air temperature range (unless otherwise noted)
www.ti.com
I
I
V
V
V
V
V
T
T
I
I
CC
I
O ref+ ref–
A stg
Supply voltage range
Input voltage range (any input)
Output voltage range
(2)
Positive reference voltage
Negative reference voltage
Peak input current (any input)
Peak total input current (all inputs)
Operating free-air temperature range
Storage temperature range
Lead temperature 1,6 mm (1/16 in) from the case for 10 s
TLC2543Q
TLC2543M
MIN
–0.5
–0.3
–0.3
–40
-55
–65
MAX UNIT
6.5
V
V
CC
+
0.3
V
CC
+
0.3
V
CC
+
0.1
V
V
V
–0.1
V
±
20 mA
±
30 mA
125
°
C
125
150
°
C
260
°
C
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to the GND terminal with REF– and GND wired together (unless otherwise noted).
Recommended Operating Conditions
V
V
V
V ref+
V
V
CC ref+ ref–
IH
IL
– V ref– t su(A) t h(A) t h(CS) t su(CS) t wH(I/O) t wL(I/O) t t(I/O) t t(CS)
Supply voltage
Positive reference voltage
(1)
Negative reference voltage
(1)
Differential reference voltage
(1)
Analog input voltage
(1)
High-level control input voltage
Low-level control input voltage
V
CC
= 4.5 V to 5.5 V
V
CC
= 4.5 V to 5.5 V
Clock frequency at I/O CLOCK
Setup time, address bits at DATA INPUT before I/O CLOCK
↑
(see
)
Hold time, address bits after I/O CLOCK
↑
(see
Hold time, CS low after last I/O CLOCK
↓
(see
)
Setup time, CS low before clocking in first address bit
(2)
(see
)
Pulse duration, I/O CLOCK high
Pulse duration, I/O CLOCK low
Transition time, I/O CLOCK high to low
(3)
(see
Transition time, DATA INPUT and CS
Operating free-air temperature
TLC2543Q
TLC2543M
MIN
4.5
2.5
0
2
0
100
0
0
1.425
120
120
NOM
5
V
CC
0
V
CC
MAX UNIT
5.5
V
V
V
CC
+ 0.1
V
CC
V
V
V
0.8
V
V
4.1
MHz
1
10
125
125 ns ns ns
µ s ns ns
µ s
µ s
°
C T
A
–40
-55
(1) Analog input voltages greater than that applied to REF+ convert as all ones (111111111111), while input voltages less than that applied to REF– convert as all zeros (000000000000).
(2) To minimize errors caused by noise at the CS input, the internal circuitry waits for a setup time after CS
↓ before responding to control input signals. No attempt should be made to clock in an address until the minimum CS setup time has elapsed.
(3) This is the time required for the clock input signal to fall from V
IH min to V
IL max or to rise from V
IL max to V
IH min. In the vicinity of normal room temperature, the devices function with input clock transition time as slow as 1
µ s for remote data acquisition applications where the sensor and the ADC are placed several feet away from the controlling microprocessor.
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TLC2543-EP
12-BIT ANALOG-TO-DIGITAL CONVERTER
WITH SERIAL CONTROL AND 11 ANALOG INPUTS
SGLS125A – JULY 2002 – REVISED NOVEMBER 2006
Electrical Characteristics
over recommended operating free-air temperature range, V
CC
(unless otherwise noted)
= V ref+
= 4.5 V to 5.5 V, f
(I/O CLOCK)
= 4.1 MHz
I
I
I
I
I
V
V
OH
OL
OZ
IH
IL
CC
CC(PD)
PARAMETER
High-level output voltage
Low-level output voltage
High-impedance off-state output current
High-level input current
Low-level input current
Operating supply current
Power-down current
Selected channel leakage current
V
CC
= 4.5 V,
V
CC
= 4.5 V to 5.5 V,
V
CC
= 4.5 V,
V
CC
= 4.5 V to 5.5 V,
V
O
= V
CC
,
V
O
= 0,
V
I
= V
CC
V
I
= 0
CS at 0 V
TEST CONDITIONS
I
OH
= –1.6 mA
I
OH
= –20
µ
A
I
OL
= 1.6 mA
I
OL
= 20
µ
A
CS at V
CC
CS at V
CC
For all digital inputs,
0
≤
V
I
≤
0.5 V or V
I
≥
V
CC
– 0.5 V
Selected channel at V
CC
, Unselected channel at 0 V
Selected channel at 0 V, Unselected channel at V
CC
C i
Maximum static analog reference current into REF+
Input capacitance
Analog inputs
Control inputs
V ref+
= V
CC
(1) All typical values are at V
CC
= 5 V, T
A
= 25
°
C.
, V ref–
= GND
MIN TYP
(1)
2.4
V
CC
– 0.1
MAX UNIT
V
0.4
0.1
V
1
1
1
2.5
µ
A
1 –2.5
10
µ
A
–10
µ
A
1 2.5
mA
4
1
30
5
25
µ
A
10
–10
60
15
µ
A
2.5
µ
A pF
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TLC2543-EP
12-BIT ANALOG-TO-DIGITAL CONVERTER
WITH SERIAL CONTROL AND 11 ANALOG INPUTS
SGLS125A – JULY 2002 – REVISED NOVEMBER 2006 www.ti.com
Operating Characteristics
over recommended operating free-air temperature range, V
CC
= V ref+
= 4.5 V to 5.5 V, f
(I/O CLOCK)
= 4.1 MHz
PARAMETER
Linearity error
(2)
TEST CONDITIONS
See
MIN TYP
(1)
E
L
E
D
E
O
E
G
E
T
Differential linearity error
Offset error
(3)
Gain error
(3)
Total unadjusted error
(5)
See
See
(4)
See
(4)
DATA INPUT = 1011 2048
Self-test output code
(6)
(see
DATA INPUT = 1100 0 t
(conv)
Conversion time
DATA INPUT = 1101
See
through
4095
8 t c t acq
Total cycle time
(access, sample, and conversion)
(7)
Channel acquisition time (sample)
(7)
See
through
See
through
4
MAX
±
1
±
1
±
1.5
±
1
±
1.75
UNIT
LSB
LSB
LSB
LSB
LSB
10
µ s
10 + total
I/O CLOCK periods + t d(I/O-EOC)
µ s
I/O
12 CLOCK periods t v t d(I/O-DATA) t d(I/O-EOC) t d(EOC-DATA) t
PZH
, t
PZL t
PHZ
, t
PLZ t r(EOC) t f(EOC) t r(bus) t f(bus) t d(I/O-CS)
Valid time,
DATA OUT remains valid after I/O
CLOCK
↓
Delay time,
I/O CLOCK
↓ to DATA OUT valid
Delay time, last I/O CLOCK
↓ to EOC
↓
Delay time,
EOC
↑ to DATA OUT (MSB/LSB)
Enable time,
CS
↓ to DATA OUT (MSB/LSB driven)
Disable time,
CS
↑ to DATA OUT (high impedance)
Rise time, EOC
Fall time, EOC
Rise time, data bus
Fall time, data bus
Delay time, last I/O CLOCK
↓ to CS
↓ to abort conversion
(8)
See
See
See
See
See
See
See
See
See
See
10
1.5
0.7
70
15
15
15
15
150
2.2
100
1.3
150
50
50
50
50
5 ns ns
µ s ns
µ s ns ns ns ns ns
µ s
(1) All typical values are at T
A
= 25
°
C.
(2) Linearity error is the maximum deviation from the best straight line through the A/D transfer characteristics.
(3) Gain error is the difference between the actual midstep value and the nominal midstep value in the transfer diagram at the specified gain point after the offset error has been adjusted to zero. Offset error is the difference between the actual midstep value and the nominal midstep value at the offset point.
(4) Analog input voltages greater than that applied to REF+ convert as all ones (111111111111), while input voltages less than that applied to REF– convert as all zeros (000000000000).
(5) Total unadjusted error comprises linearity, zero-scale, and full-scale errors.
(6) Both the input address and the output codes are expressed in positive logic.
(7) I/O CLOCK period = 1 /(I/O CLOCK frequency) (see
)
(8) Any transitions of CS are recognized as valid only when the level is maintained for a setup time. CS must be taken low at
≤
5
µ s of the tenth I/O CLOCK falling edge to ensure a conversion is aborted. Between 5
µ s and 10
µ s, the result is uncertain as to whether the conversion is aborted or the conversion results are valid.
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TLC2543-EP
12-BIT ANALOG-TO-DIGITAL CONVERTER
WITH SERIAL CONTROL AND 11 ANALOG INPUTS
SGLS125A – JULY 2002 – REVISED NOVEMBER 2006
PARAMETER MEASUREMENT INFORMATION
15 V
50
Ω
C1
10
µ
F
C2
0.1
µ
F
C3
470 pF
_
U1
+
10
Ω
TLC2543
AIN0−AIN10
V
I
C1
10
µ
F
C2
0.1
µ
F
C3
470 pF
50
Ω
−15 V
LOCATION
U1
C1
C2
C3
DESCRIPTION
OP27
10-
µ
F 35-V tantalum capacitor
0.1-
µ
F ceramic NPO SMD capacitor
470-pF porcelain Hi-Q SMD capacitor
PART NUMBER
—
—
AVX 12105C104KA105 or equivalent
Johanson 201S420471JG4L or equivalent
Figure 1. Analog Input Buffer to Analog Inputs AIN0–AIN10
Test Point
V
CC
R
L
= 2.18 k
Ω
Test Point
V
CC
R
L
= 2.18 k
Ω
EOC DATA OUT
C
L
= 50 pF
12 k
Ω
C
L
= 100 pF
12 k
Ω
CS t
PZH
, t
PZL
DATA
OUT
0.8 V
2.4 V
0.4 V
2 V
Figure 2. Load Circuits
t
PHZ
, t
PLZ
90%
10%
Figure 3. DATA OUT to Hi-Z Voltage Waveforms
Data
Valid
DATA INPUT
2 V
0.8 V t su(A) t h(A)
I/O CLOCK
0.8 V
Figure 4. DATA INPUT and I/O CLOCK
Voltage Waveforms
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TLC2543-EP
12-BIT ANALOG-TO-DIGITAL CONVERTER
WITH SERIAL CONTROL AND 11 ANALOG INPUTS
SGLS125A – JULY 2002 – REVISED NOVEMBER 2006 www.ti.com
2 V
CS
0.8 V t su(CS) t h(CS)
I/O CLOCK
0.8 V
Last
Clock
0.8 V
A.
To ensure full conversion accuracy, it is recommended that no input signal change occurs while a conversion is ongoing.
Figure 5. CS and I/O CLOCK Voltage Waveforms
t t(I/O)
I/O CLOCK
2 V
0.8 V t t(I/O)
2 V
0.8 V
I/O CLOCK Period
0.8 V t d(I/O-DATA) t v
DATA OUT
2.4 V
0.4 V
2.4 V
0.4 V t r(bus)
, t f(bus)
Figure 6. I/O CLOCK and DATA OUT Voltage Waveforms
I/O CLOCK
Last
Clock t d(I/O-EOC)
0.8 V
EOC
2.4 V
0.4 V t f(EOC)
Figure 7. I/O CLOCK and EOC Voltage Waveforms
t r(EOC)
EOC
0.4 V
2.4 V
DATA OUT t d(EOC-DATA)
2.4 V
0.4 V
Valid MSB
Figure 8. EOC and DATA OUT Voltage Waveforms
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TLC2543-EP
12-BIT ANALOG-TO-DIGITAL CONVERTER
WITH SERIAL CONTROL AND 11 ANALOG INPUTS
SGLS125A – JULY 2002 – REVISED NOVEMBER 2006
CS
(see Note A)
I/O
CLOCK
1 2 3
Access Cycle B
4 5 6 7
Sample Cycle B
8 11
DATA
OUT
A11 A10 A9 A8 A7 A6 A5 A4 A1
ÎÎÎ ÎÎ ÎÎ ÎÎ ÎÎ ÎÎ ÎÎ ÎÎ ÎÎ
Previous Conversion Data
MSB
ÎÎÎ ÎÎ ÎÎ ÎÎ ÎÎ ÎÎ ÎÎ ÎÎ ÎÎ
DATA
ÎÎÎ ÎÎ ÎÎ ÎÎ ÎÎ ÎÎ ÎÎ ÎÎ ÎÎ
INPUT
B7 B6 B5 B4 B3 B2 B1 B0
ÎÎ ÎÎ
MSB LSB
A0
LSB
ÎÎÎÎÎÎ
ÎÎÎÎÎÎ
12
ÎÎÎÎÎÎ
ÎÎÎÎÎÎ
Hi-Z State
1
B11
ÎÎ ÎÎ
ÎÎ ÎÎ
ÎÎ ÎÎ
EOC
Shift in New Multiplexer Address,
Simultaneously Shift Out Previous
Conversion Value t
(conv)
A/D Conversion
Interval
Initialize Initialize
A.
To minimize errors caused by noise at CS, the internal circuitry waits for a setup time after CS
↓ before responding to control input signals. Therefore, no attempt should be made to clock in an address until the minimum CS setup time has elapsed.
Figure 9. Timing for 12-Clock Transfer Using CS With MSB First
CS
(see Note A)
I/O
CLOCK
1 2 3
Access Cycle B
4 5 6 7
Sample Cycle B
8 11
DATA
OUT
A11 A10 A9 A8 A7 A6 A5 A4 A1
ÎÎÎ ÎÎ ÎÎ
MSB
Previous Conversion Data
ÎÎ ÎÎ
ÎÎÎ ÎÎ ÎÎ ÎÎ ÎÎ ÎÎ ÎÎ ÎÎ ÎÎ
DATA
INPUT
ÎÎ ÎÎ ÎÎ ÎÎ ÎÎ ÎÎ ÎÎ ÎÎ
B7 B6 B5 B4 B3 B2 B1 B0
ÎÎÎ ÎÎ ÎÎ
MSB
ÎÎ ÎÎ ÎÎ ÎÎ ÎÎ ÎÎ
LSB
A0
12
LSB
1
Low Level
B11
ÎÎÎ ÎÎ
ÎÎÎ ÎÎ
ÎÎÎ ÎÎ
C7
ÎÎÎ ÎÎ
EOC
Shift in New Multiplexer Address,
Simultaneously Shift Out Previous
Conversion Value t
(conv)
Initialize
A/D Conversion
Interval
Initialize
A.
To minimize errors caused by noise at CS, the internal circuitry waits for a setup time after CS
↓ before responding to control input signals. Therefore, no attempt should be made to clock in an address until the minimum CS setup time has elapsed.
Figure 10. Timing for 12-Clock Transfer Not Using CS With MSB First
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TLC2543-EP
12-BIT ANALOG-TO-DIGITAL CONVERTER
WITH SERIAL CONTROL AND 11 ANALOG INPUTS
SGLS125A – JULY 2002 – REVISED NOVEMBER 2006 www.ti.com
CS
(see Note A)
ÎÎÎÎÎÎ
I/O CLOCK
1 2 3
Access Cycle B
4 5 6
Sample Cycle B
7 8
ÎÎÎÎÎÎ
ÎÎÎÎÎÎ
1
ÎÎÎÎÎÎ
DATA OUT
A7 A6 A5 A4 A3 A2 A1 A0
ÎÎ Î
MSB
ÎÎ Î
ÎÎ Î ÎÎ ÎÎ ÎÎ ÎÎÎÎÎ Î
Previous Conversion Data
LSB
Î ÎÎ Î ÎÎ ÎÎ ÎÎ ÎÎÎÎÎ
DATA INPUT
ÎÎ Î Î ÎÎ Î ÎÎ ÎÎ ÎÎ ÎÎÎÎÎ
ÎÎ
B7
MSB
Î
B6
Î
B5
Î
B4
B3 B2 B1 B0
LSB
Hi-Z
B7
ÎÎÎ ÎÎ
ÎÎÎ ÎÎ
ÎÎÎ ÎÎ
EOC
Shift in New Multiplexer Address,
Simultaneously Shift Out Previous
Conversion Value t
(conv)
A/D Conversion
Interval
Initialize Initialize
A.
To minimize errors caused by noise at CS, the internal circuitry waits for a setup time after CS
↓ before responding to control input signals. Therefore, no attempt should be made to clock in an address until the minimum CS setup time has elapsed.
Figure 11. Timing for 8-Clock Transfer Using CS With MSB First
CS
(see Note A)
I/O CLOCK
1 2 3
Access Cycle B
4 5 6 7
Sample Cycle B
8 1
DATA OUT
A7 A6 A5 A4 A3 A2 A1 A0
ÎÎ ÎÎ ÎÎ ÎÎ ÎÎ ÎÎ Î ÎÎ ÎÎÎ
Previous Conversion Data
ÎÎ ÎÎ ÎÎ ÎÎ ÎÎ ÎÎ Î ÎÎ ÎÎÎ
MSB LSB
Low Level
ÎÎ ÎÎ ÎÎ ÎÎ ÎÎ ÎÎ Î ÎÎ ÎÎÎ
DATA INPUT
ÎÎ ÎÎ ÎÎ ÎÎ ÎÎ ÎÎ Î ÎÎ ÎÎÎ
B7 B6 B5 B4 B3 B2 B1 B0
MSB LSB
B7
ÎÎÎ ÎÎ
ÎÎÎ ÎÎ
ÎÎÎ ÎÎ
ÎÎÎ ÎÎ
C7
EOC
Shift in New Multiplexer Address,
Simultaneously Shift Out Previous
Conversion Value t
(conv)
A/D Conversion
Interval
Initialize Initialize
A.
To minimize errors caused by noise at CS, the internal circuitry waits for a setup time after CS
↓ before responding to control input signals. Therefore, no attempt should be made to clock in an address until the minimum CS setup time has elapsed.
Figure 12. Timing for 8-Clock Transfer Not Using CS With MSB First
10
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TLC2543-EP
12-BIT ANALOG-TO-DIGITAL CONVERTER
WITH SERIAL CONTROL AND 11 ANALOG INPUTS
SGLS125A – JULY 2002 – REVISED NOVEMBER 2006
CS
(see Note A)
I/O
CLOCK
1 2 3
Access Cycle B
4 5 6 7
Sample Cycle B
8 15 16
ÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎ
1
DATA
A15 A14 A13 A12 A11 A10
OUT
ÎÎÎ ÎÎ ÎÎ ÎÎ ÎÎ ÎÎ Î
A9
Î
A8 A1
ÎÎ
ÎÎÎ ÎÎ ÎÎ ÎÎ ÎÎ ÎÎ Î
MSB
Previous Conversion Data
Î ÎÎ
ÎÎÎ ÎÎ ÎÎ ÎÎ ÎÎ ÎÎ Î
DATA
INPUT
ÎÎÎ ÎÎ ÎÎ ÎÎ ÎÎ ÎÎ Î
B7
MSB
B6 B5 B4
LSB
B3 B2 B1
Î
Î
B0
ÎÎ
ÎÎ
A0
LSB
Hi-Z State
B15
ÎÎ ÎÎ
ÎÎ ÎÎ
ÎÎ ÎÎ
ÎÎ ÎÎ
C7
EOC
Shift in New Multiplexer Address,
Simultaneously Shift Out Previous
Conversion Value t
(conv)
A/D Conversion
Interval
Initialize Initialize
A.
To minimize errors caused by noise at CS, the internal circuitry waits for a setup time after CS
↓ before responding to control input signals. Therefore, no attempt should be made to clock in an address until the minimum CS setup time has elapsed.
Figure 13. Timing for 16-Clock Transfer Using CS With MSB First
CS
(see Note A)
I/O
CLOCK
1 2 3
Access Cycle B
4 5 6 7 8
Sample Cycle B
15 16
DATA
A15 A14 A13 A12 A11 A10 A9 A8 A1
OUT
ÎÎÎ ÎÎ Î ÎÎ ÎÎ ÎÎ ÎÎ ÎÎ ÎÎÎ
A0
Previous Conversion Data
ÎÎÎ ÎÎ Î ÎÎ ÎÎ ÎÎ ÎÎ ÎÎ ÎÎÎ
MSB LSB
ÎÎÎ ÎÎ Î ÎÎ ÎÎ ÎÎ ÎÎ ÎÎ ÎÎÎ
DATA
INPUT
ÎÎÎ ÎÎ Î ÎÎ ÎÎ ÎÎ ÎÎ ÎÎ ÎÎÎ
B7 B6 B5 B4
B3 B2 B1 B0
MSB LSB
1
Low Level
B15
ÎÎÎÎ ÎÎ
ÎÎÎÎ ÎÎ
ÎÎÎÎ ÎÎ
ÎÎÎÎ ÎÎ
C7
EOC
Shift in New Multiplexer Address,
Simultaneously Shift Out Previous
Conversion Value t
(conv)
A/D Conversion
Interval
Initialize
A.
To minimize errors caused by noise at CS, the internal circuitry waits for a setup time after CS
↓ before responding to control input signals. Therefore, no attempt should be made to clock in an address until the minimum CS setup time has elapsed.
Figure 14. Timing for 16-Clock Transfer Not Using CS With MSB First
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TLC2543-EP
12-BIT ANALOG-TO-DIGITAL CONVERTER
WITH SERIAL CONTROL AND 11 ANALOG INPUTS
SGLS125A – JULY 2002 – REVISED NOVEMBER 2006
PRINCIPLES OF OPERATION
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Initially, with chip select (CS) high, I/O CLOCK and DATA INPUT are disabled and DATA OUT is in the high-impedance state. CS going low begins the conversion sequence by enabling I/O CLOCK and DATA INPUT and removes DATA OUT from the high-impedance state.
The input data is an 8-bit data stream consisting of a 4-bit analog channel address (D7–D4), a 2-bit data length select (D3–D2), an output MSB or LSB first bit (D1), and a unipolar or bipolar output select bit (D0) that are applied to DATA INPUT. The I/O CLOCK sequence applied to the I/O CLOCK terminal transfers this data to the input data register.
During this transfer, the I/O CLOCK sequence also shifts the previous conversion result from the output data register to DATA OUT. I/O CLOCK receives the input sequence of 8, 12, or 16 clock cycles long, depending on the data-length selection in the input data register. Sampling of the analog input begins on the fourth falling edge of the input I/O CLOCK sequence and is held after the last falling edge of the I/O CLOCK sequence. The last falling edge of the I/O CLOCK sequence also takes EOC low and begins the conversion.
Converter Operation
The operation of the converter is organized as a succession of two distinct cycles: the I/O cycle and the actual conversion cycle.
I/O Cycle
The I/O cycle is defined by the externally provided I/O CLOCK and lasts 8, 12, or 16 clock periods, depending on the selected output data length.
During the I/O cycle, the following two operations take place simultaneously:
•
An 8-bit data stream consisting of address and control information is provided to DATA INPUT. This data is shifted into the device on the rising edge of the first eight I/O CLOCKs. DATA INPUT is ignored after the first eight clocks during 12- or 16-clock I/O transfers.
•
The data output, with a length of 8, 12, or 16 bits, is provided serially on DATA OUT. When CS is held low, the first output data bit occurs on the rising edge of EOC. When CS is negated between conversions, the first output data bit occurs on the falling edge of CS. This data is the result of the previous conversion period, and after the first output data bit, each succeeding bit is clocked out on the falling edge of each succeeding I/O
CLOCK.
Conversion Cycle
The conversion cycle is transparent to the user, and it is controlled by an internal clock synchronized to I/O
CLOCK. During the conversion period, the device performs a successive-approximation conversion on the analog input voltage. The EOC output goes low at the start of the conversion cycle and goes high when conversion is complete and the output data register is latched. A conversion cycle is started only after the I/O cycle is completed, which minimizes the influence of external digital noise on the accuracy of the conversion.
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12-BIT ANALOG-TO-DIGITAL CONVERTER
WITH SERIAL CONTROL AND 11 ANALOG INPUTS
SGLS125A – JULY 2002 – REVISED NOVEMBER 2006
PRINCIPLES OF OPERATION (continued)
Power Up and Initialization
After power up, CS must be taken from high to low to begin an I/O cycle. EOC is initially high, and the input data register is set to all zeroes. The contents of the output data register are random, and the first conversion result should be ignored. To initialize during operation, CS is taken high and is then returned low to begin the next I/O cycle. The first conversion after the device has returned from the power-down state may not read accurately due to internal device settling.
Current (N) I/O cycle
Current (N) conversion cycle
Current (N) conversion result
Previous (N – 1) conversion cycle
Next (N + 1) I/O cycle
Table 1. Operational Terminology
Entire I/O CLOCK sequence that transfers address and control data into the data register and clocks the digital result from the previous conversion from DATA OUT
The conversion cycle starts immediately after the current I/O cycle. The end of the current I/O cycle is the last clock falling edge in the I/O CLOCK sequence. The current conversion result is loaded into the output register when conversion is complete.
The current conversion result is serially shifted out on the next I/O cycle.
Conversion cycle just prior to the current I/O cycle
I/O period that follows the current conversion cycle
Example: In the 12-bit mode, the result of the current conversion cycle is a 12-bit serial-data stream clocked out during the next I/O cycle. The current I/O cycle must be exactly 12 bits long to maintain synchronization, even when this corrupts the output data from the previous conversion. The current conversion is begun immediately after the twelfth falling edge of the current I/O cycle.
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12-BIT ANALOG-TO-DIGITAL CONVERTER
WITH SERIAL CONTROL AND 11 ANALOG INPUTS
SGLS125A – JULY 2002 – REVISED NOVEMBER 2006 www.ti.com
Data Input
The data input is internally connected to an 8-bit serial-input address and control register. The register defines the operation of the converter and the output data length. The host provides the data word with the MSB first.
Each data bit is clocked in on the rising edge of the I/O CLOCK sequence (see
for the data input-register format).
FUNCTION SELECT
Table 2. Input-Register Format
ADDRESS BITS
INPUT DATA BYTE
L1
D7
(MSB)
D6 D5 D4 D3
L0
D2
LSBF
D1
BIP
D0
(LSB)
Select input channel
AIN0
AIN1
AIN2
AIN3
AIN4
AIN5
AIN6
AIN7
AIN8
AIN9
AIN10
Select test voltage
(V ref+
– V ref–
)/2
V ref–
V ref+
Software power down
Output data length
8 bits
12 bits
16 bits
Output data format
MSB first
LSB first (LSBF)
Unipolar (binary)
Bipolar (BIP) 2s complement
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
X
0
(1)
1
1
0
1
0
1
0
1
(1) The four MSBs (D7–D4) of the data register address one of the 11 input channels, a reference-test voltage, or the power-down mode.
The address bits affect the current conversion, which is the conversion that immediately follows the current I/O cycle. The reference voltage is nominally equal to V ref+
– V ref–
.
Data Input Address Bits
The four MSBs (D7–D4) of the data register address 1 of the 11 input channels, a reference-test voltage, or the power-down mode. The address bits affect the current conversion, which is the conversion that immediately follows the current I/O cycle. The reference voltage is nominally equal to V ref+
– V ref–
.
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12-BIT ANALOG-TO-DIGITAL CONVERTER
WITH SERIAL CONTROL AND 11 ANALOG INPUTS
SGLS125A – JULY 2002 – REVISED NOVEMBER 2006
Data Output Length
The next two bits (D3 and D2) of the data register select the output data length. The data-length selection is valid for the current I/O cycle (the cycle in which the data is read). The data-length selection, being valid for the current I/O cycle, allows device start-up without losing I/O synchronization. A data length of 8, 12, or 16 bits can be selected. Since the converter has 12-bit resolution, a data length of 12 bits is suggested.
With D3 and D2 set to 00 or 10, the device is in the 12-bit data-length mode and the result of the current conversion is output as a 12-bit serial data stream during the next I/O cycle. The current I/O cycle must be exactly 12 bits long for proper synchronization, even when this means corrupting the output data from a previous conversion. The current conversion is started immediately after the twelfth falling edge of the current I/O cycle.
With bits D3 and D2 set to 11, the 16-bit data-length mode is selected, which allows convenient communication with 16-bit serial interfaces. In the 16-bit mode, the result of the current conversion is output as a 16-bit serial data stream during the next I/O cycle with the four LSBs always reset to 0 (pad bits). The current I/O cycle must be exactly 16 bits long to maintain synchronization even when this means corrupting the output data from the previous conversion. The current conversion is started immediately after the sixteenth falling edge of the current
I/O cycle.
With bits D3 and D2 set to 01, the 8-bit data-length mode is selected, which allows fast communication with 8-bit serial interfaces. In the 8-bit mode, the result of the current conversion is output as an 8-bit serial data stream during the next I/O cycle. The current I/O cycle must be exactly eight bits long to maintain synchronization, even when this means corrupting the output data from the previous conversion. The four LSBs of the conversion result are truncated and discarded. The current conversion is started immediately after the eighth falling edge of the current I/O cycle.
Since D3 and D2 take effect on the current I/O cycle when the data length is programmed, there can be a conflict with the previous cycle when the data-word length is changed from one cycle to the next. This may occur when the data format is selected to be LSB first, since at the time the data length change becomes effective (six rising edges of I/O CLOCK), the previous conversion result has already started shifting out.
In actual operation, when different data lengths are required within an application and the data length is changed between two conversions, no more than one conversion result can be corrupted and only when it is shifted out in
LSB-first format.
Sampling Period
During the sampling period, one of the analog inputs is internally connected to the capacitor array of the converter to store the analog input signal. The converter starts sampling the selected input immediately after the four address bits have been clocked into the input data register. Sampling starts on the fourth falling edge of I/O
CLOCK. The converter remains in the sampling mode until the eighth, twelfth, or sixteenth falling edge of the I/O
CLOCK depending on the data-length selection. After the EOC delay time from the last I/O CLOCK falling edge, the EOC output goes low indicating that the sampling period is over and the conversion period has begun. After
EOC goes low, the analog input can be changed without affecting the conversion result. Since the delay from the falling edge of the last I/O CLOCK to EOC low is fixed, time-varying analog input signals can be digitized at a fixed rate without introducing systematic harmonic distortion or noise due to timing uncertainty.
After the 8-bit data stream has been clocked in, DATA INPUT should be held at a fixed digital level until EOC goes high (indicating that the conversion is complete) to maximize the sampling accuracy and minimize the influence of external digital noise.
Data Register, LSB First
D1 in the input data register (LSB first) controls the direction of the output binary data transfer. When D1 is reset to 0, the conversion result is shifted out MSB first. When set to 1, the data is shifted out LSB first. Selection of
MSB first or LSB first always affects the next I/O cycle and not the current I/O cycle. When changing from one data direction to another, the current I/O cycle is never disrupted.
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Data Register, Bipolar Format
D0 (BIP) in the input data register controls the binary data format used to represent the conversion result. When
D0 is cleared to 0, the conversion result is represented as unipolar (unsigned binary) data. Nominally, the conversion result of an input voltage equal to V ref– input voltage equal to V ref+ is a code of all ones (111 . . . 1), and the conversion result of (V code of a one followed by zeros (100 . . . 0).
is a code of all zeros (000 . . . 0), the conversion result of an ref+
+ V ref–
)/2 is a
When D0 is set to 1, the conversion result is represented as bipolar (signed binary) data. Nominally, conversion of an input voltage equal to V ref– equal to V ref+ is a code of a one followed by zeros (100 . . . 0), conversion of an input voltage is a code of a zero followed by all ones (011 . . . 1), and the conversion of (V ref+
+ V ref–
)/2 is a code of all zeros (000 . . . 0). The MSB is interpreted as the sign bit. The bipolar data format is related to the unipolar format in that the MSBs are always each other's complement.
Selection of the unipolar or bipolar format always affects the current conversion cycle, and the result is output during the next I/O cycle. When changing between unipolar and bipolar formats, the data output during the current I/O cycle is not affected.
End of Conversion (EOC) Output
The EOC signal indicates the beginning and the end of conversion. In the reset state, EOC is always high.
During the sampling period (beginning after the fourth falling edge of the I/O CLOCK sequence), EOC remains high until the internal sampling switch of the converter is safely opened. The opening of the sampling switch occurs after the eighth, twelfth, or sixteenth I/O CLOCK falling edge, depending on the data-length selection in the input data register. After the EOC signal goes low, the analog input signal can be changed without affecting the conversion result.
The EOC signal goes high again after the conversion is completed and the conversion result is latched into the output data register. The rising edge of EOC returns the converter to a reset state and a new I/O cycle begins.
On the rising edge of EOC, the first bit of the current conversion result is on DATA OUT when CS is low. When
CS is negated between conversions, the first bit of the current conversion result occurs at DATA OUT on the falling edge of CS.
Data Format and Pad Bits
D3 and D2 of the input data register determine the number of significant bits in the digital output that represent the conversion result. The LSB-first bit determines the direction of the data transfer while the BIP bit determines the arithmetic conversion. The numerical data is always justified toward the MSB in any output format.
The internal conversion result is always 12 bits long. When an 8-bit data transfer is selected, the four LSBs of the internal result are discarded to provide a faster 1-byte transfer. When a 12-bit transfer is used, all bits are transferred. When a 16-bit transfer is used, four LSB pad bits are always appended to the internal conversion result. In the LSB-first mode, four leading zeros are output. In the MSB-first mode, the last four bits output are zeros.
When CS is held low continuously, the first data bit of the newly completed conversion occurs on DATA OUT on the rising edge of EOC. When a new conversion is started after the last falling edge of I/O CLOCK, EOC goes low and the serial output is forced to a setting of 0 until EOC goes high again.
When CS is negated between conversions, the first data bit occurs on DATA OUT on the falling edge of CS. On each subsequent falling edge of I/O CLOCK after the first data bit appears, the data is changed to the next bit in the serial conversion result until the required number of bits has been output.
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12-BIT ANALOG-TO-DIGITAL CONVERTER
WITH SERIAL CONTROL AND 11 ANALOG INPUTS
SGLS125A – JULY 2002 – REVISED NOVEMBER 2006
Chip-Select (CS) Input
CS enables and disables the device. During normal operation, CS should be low. Although the use of CS is not necessary to synchronize a data transfer, it can be brought high between conversions to coordinate the data transfer of several devices sharing the same bus.
When CS is brought high, the serial-data output is immediately brought to the high-impedance state, releasing its output data line to other devices that may share it. After an internally generated debounce time, I/O CLOCK is inhibited, thus preventing any further change in the internal state.
When CS is subsequently brought low again, the device is reset. CS must be held low for an internal debounce time before the reset operation takes effect. After CS is debounced low, I/O CLOCK must remain inactive (low) for a minimum time before a new I/O cycle can start.
CS can interrupt any ongoing data transfer or any ongoing conversion. When CS is debounced low long enough before the end of the current conversion cycle, the previous conversion result is saved in the internal output buffer and shifted out during the next I/O cycle.
Power-Down Features
When a binary address of 1110 is clocked into the input data register during the first four I/O CLOCK cycles, the power-down mode is selected. Power down is activated on the falling edge of the fourth I/O CLOCK pulse.
During power down, all internal circuitry is put in a low-current standby mode. No conversions are performed, and the internal output buffer keeps the previous conversion cycle data results provided that all digital inputs are held above V
CC
– 0.5 V or below 0.5 V. The I/O logic remains active so the current I/O cycle must be completed, even when the power-down mode is selected. Upon power-on reset and before the first I/O cycle, the converter normally begins in the power-down mode. The device remains in the power-down mode until a valid input address (other than 1110) is clocked in. Upon completion of that I/O cycle, a normal conversion is performed with the results being shifted out during the next I/O cycle.
Analog Input, Test, and Power-Down Mode
The 11 analog inputs, 3 internal voltages, and power-down mode are selected by the input multiplexer according to the input addresses shown in
,
, and
Table 5 . The input multiplexer is a break-before-make
type to reduce input-to-input noise rejection resulting from channel switching. Sampling of the analog input starts on the falling edge of the fourth I/O CLOCK and continues for the remaining I/O CLOCK pulses. The sample is held on the falling edge of the last I/O clock pulse. The three internal test inputs are applied to the multiplexer, then sampled and converted in the same manner as the external analog inputs. The first conversion after the device has returned from the power-down state may not read accurately due to internal device settling.
AIN0
AIN1
AIN2
AIN3
AIN4
AIN5
AIN6
AIN7
AIN8
AIN9
AIN10
Table 3. Analog-Channel-Select Address
ANALOG INPUT
SELECTED
VALUE SHIFTED INTO DATA INPUT
BINARY HEX
0000
0001
0
1
0010
0011
0100
0101
0110
0111
1000
1001
1010
2
3
4
5
6
7
8
9
A
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12-BIT ANALOG-TO-DIGITAL CONVERTER
WITH SERIAL CONTROL AND 11 ANALOG INPUTS
SGLS125A – JULY 2002 – REVISED NOVEMBER 2006 www.ti.com
INTERNAL SELF-TEST
VOLTAGE SELECTED
(1)
Table 4. Test-Mode-Select Address
VALUE SHIFTED INTO DATA INPUT
BINARY HEX
UNIPOLAR OUTPUT
RESULT (HEX)
(2)
V ref +
– V ref –
2
V ref–
V ref+
1011
1100
1101
B
C
D
800
000
FFF
(1) V ref+ is the voltage applied to REF+, and V ref– is the voltage applied to REF–.
(2) The output results shown are the ideal values and may vary with the reference stability and with internal offsets.
INPUT COMMAND
Power down
Table 5. Power-Down-Select Address
VALUE SHIFTED INTO DATA INPUT
BINARY HEX
1110 E
RESULT
I
CC
≤
25
µ
A
Converter and Analog Input
The CMOS threshold detector in the successive-approximation conversion system determines each bit by examining the charge on a series of binary-weighted capacitors (see
Figure 1 ). In the first phase of the
conversion process, the analog input is sampled by closing the S
C
This action charges all the capacitors to the input voltage.
switch and all S
T switches simultaneously.
In the next phase of the conversion process, all S
T and S
C switches are opened and the threshold detector begins identifying bits by identifying the charge (voltage) on each capacitor relative to the reference (REF–) voltage. In the switching sequence, 12 capacitors are examined separately until all 12 bits are identified and the charge-convert sequence is repeated. In the first step of the conversion phase, the threshold detector looks at the first capacitor (weight = 4096). Node 4096 of this capacitor is switched to the REF+ voltage, and the equivalent nodes of all the other capacitors on the ladder are switched to REF–. When the voltage at the summing node is greater than the trip point of the threshold detector (approximately one-half V
CC
), a bit 0 is placed in the output register and the 4096-weight capacitor is switched to REF–. When the voltage at the summing node is less than the trip point of the threshold detector, a bit 1 is placed in the register and this
4096-weight capacitor remains connected to REF+ through the remainder of the successive-approximation process. The process is repeated for the 2048-weight capacitor, the 1024-weight capacitor, and so forth down the line until all bits are determined. With each step of the successive-approximation process, the initial charge is redistributed among the capacitors. The conversion process relies on charge redistribution to determine the bits from MSB to LSB.
Reference Voltage Inputs
The two reference inputs used with the device are the voltages applied to the REF+ and REF– terminals. These voltage values establish the upper and lower limits of the analog input to produce a full-scale and zero-scale reading, respectively. These voltages and the analog input should not exceed the positive supply or be lower than ground consistent with the specified absolute maximum ratings. The digital output is at full scale when the input signal is equal to or higher than REF+ terminal voltage, and at zero when the input signal is equal to or lower than REF– terminal voltage.
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4096
Node 4096
2048
REF+
1024
REF+
16
REF+
8
REF+
TLC2543-EP
12-BIT ANALOG-TO-DIGITAL CONVERTER
WITH SERIAL CONTROL AND 11 ANALOG INPUTS
SGLS125A – JULY 2002 – REVISED NOVEMBER 2006
S
C
Threshold
Detector
1
To Output
Latches
4
REF+
2
REF+
1
REF+
REF − REF −
S
T
REF −
S
T
REF −
S
T
REF −
S
T
REF −
S
T
REF −
S
T
REF −
S
T
REF −
S
T
S
T
V
I
Figure 15. Simplified Model of the Successive-Approximation System
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12-BIT ANALOG-TO-DIGITAL CONVERTER
WITH SERIAL CONTROL AND 11 ANALOG INPUTS
SGLS125A – JULY 2002 – REVISED NOVEMBER 2006
APPLICATION INFORMATION
111111111111
See Notes A and B
111111111110
111111111101
V
FS www.ti.com
V
FSnom
4095
4094
4093
V
FT
= V
FS
− 1/2 LSB
100000000001
100000000000
011111111111
V
ZT
= V
ZS
+ 1/2 LSB
V
ZS
000000000010
2
000000000001
1
000000000000
0 0.0012
0.0024
2.4564
2.4576
2.4588
4.9128
0
4.9140
4.9152
V
I
− Analog Input Voltage − V
A.
This curve is based on the assumption that V ref+ and V ref– have been adjusted so that the voltage at the transition from digital 0 to 1 (V
ZT
) is 0.0006 V and the transition to full scale (V
FT
) is 4.9134 V. 1 LSB = 1.2 mV.
B.
The full-scale value (V
FS
) is the step whose nominal midstep value has the highest absolute value. The zero-scale value (V
ZS
) is the step whose nominal midstep value equals zero.
Figure 16. Ideal Conversion Characteristics
2049
2048
2047
Analog
Inputs
6
7
4
5
8
1
2
3
9
11
12
TLC2543
15
AIN0
AIN1
AIN2
AIN3
AIN4
AIN5
AIN6
AIN7
AIN8
I/O CLOCK
DATA INPUT
AIN9
AIN10
GND
CS
DATA OUT
EOC
REF+
REF−
18
17
16
19
14
13
10
Processor
5-V DC Regulated
Control
Circuit
To Source
Ground
Figure 17. Serial Interface
20
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12-BIT ANALOG-TO-DIGITAL CONVERTER
WITH SERIAL CONTROL AND 11 ANALOG INPUTS
SGLS125A – JULY 2002 – REVISED NOVEMBER 2006
APPLICATION INFORMATION (continued)
Simplified Analog Input Analysis
Using the equivalent circuit in
, the time required to charge the analog input capacitance from 0 V to V
S within one-half LSB can be derived as follows:
The capacitance charging voltage is given by:
V
C
+
V
S ǒ
1
* e
* tc ń
RtCi
Ǔ
(1)
Where:
R t
= R s
+ r i
The final voltage to 1/2 LSB is given by:
V
C
(1/2 LSB) = V
S
− (V
S
/8192)
(2)
Equating equation 1 to equation 2 and solving for time t c
V
S
* ǒ
V
S ń
8192
Ǔ
+
V
S ǒ
1
* e
* tc ń
RtCi
Ǔ gives
(3) and t c
(1/2 LSB) = R t
×
C i
×
ln(8192)
(4) t
Therefore, with the values given, the time for the analog input signal to settle is: c
(1/2 LSB) = (R s
+ 1 k
Ω
)
×
60 pF
×
ln(8192)
(5)
This time must be less than the converter sample time shown in the timing diagrams.
Driving Source
(A)
TLC2543
V
S
R s
V
I r i
1 k
Ω
Max
V
C
C i
60 pF Max
V
I
V
S
R s r i
C i
V
C
= Input Voltage at AIN
= External Driving Source Voltage
= Source Resistance
= Input Resistance
= Input Capacitance
= Capacitance Charging Voltage
A.
Driving source requirements:
•
Noise and distortion for the source must be equivalent to the resolution of the converter.
•
R s must be real at the input frequency.
Figure 18. Equivalent Input Circuit Including the Driving Source
21
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PACKAGE OPTION ADDENDUM
18-Sep-2008
PACKAGING INFORMATION
Orderable Device
TLC2543MDBREP
TLC2543QDWREP
V62/03614-01XE
V62/03614-02YE
Status
(1)
ACTIVE
ACTIVE
ACTIVE
ACTIVE
Package
Type
SSOP
SOIC
SOIC
SSOP
Package
Drawing
DB
DW
DW
DB
Eco Plan
(2)
Pins Package
Qty
20 2000 Green (RoHS & no Sb/Br)
Lead/Ball Finish MSL Peak Temp
(3)
CU NIPDAU Level-1-260C-UNLIM
20 CU NIPDAU Level-1-260C-UNLIM
20
2000 Green (RoHS & no Sb/Br)
2000 Green (RoHS & no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
20 2000 Green (RoHS & no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF TLC2543-EP :
•
•
Catalog: TLC2543
• Automotive: TLC2543-Q1
Military: TLC2543M
NOTE: Qualified Version Definitions:
•
•
Catalog - TI's standard catalog product
• Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
Military - QML certified for Military and Defense Applications
Addendum-Page 1
www.ti.com
TAPE AND REEL INFORMATION
PACKAGE MATERIALS INFORMATION
16-Jul-2008
*All dimensions are nominal
Device
TLC2543MDBREP
TLC2543QDWREP
Package
Type
Package
Drawing
SSOP
SOIC
DB
DW
Pins
20
20
SPQ
2000
2000
Reel
Diameter
(mm)
Reel
Width
W1 (mm)
330.0
16.4
330.0
24.4
A0 (mm)
8.2
10.8
B0 (mm)
7.5
13.1
K0 (mm) P1
(mm)
W
(mm)
Pin1
Quadrant
2.5
2.65
12.0
16.0
12.0
24.0
Q1
Q1
Pack Materials-Page 1
www.ti.com
PACKAGE MATERIALS INFORMATION
16-Jul-2008
*All dimensions are nominal
Device
TLC2543MDBREP
TLC2543QDWREP
Package Type Package Drawing Pins
SSOP
SOIC
DB
DW
20
20
SPQ
2000
2000
Length (mm) Width (mm) Height (mm)
346.0
346.0
346.0
346.0
33.0
41.0
Pack Materials-Page 2
MECHANICAL DATA
MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001
PLASTIC SMALL-OUTLINE DB (R-PDSO-G**)
28 PINS SHOWN
0,65
28
0,38
0,22
15
0,15
M
0,25
0,09
5,60
5,00
8,20
7,40
1
A
14
0
°
–
ā
8
°
Gage Plane
0,25
0,95
0,55
2,00 MAX
Seating Plane
0,10
0,05 MIN
PINS **
DIM
A MAX
14
6,50
16
6,50
20 24 28 30 38
7,50 8,50 10,50 10,50 12,90
A MIN
5,90 5,90 6,90 7,90 9,90 9,90 12,30
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-150
4040065 /E 12/01
POST OFFICE BOX 655303
•
DALLAS, TEXAS 75265
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