TMDS351

TMDS351 www.ti.com

..........................................................................................................................................................

SLLS840A – MAY 2007 – REVISED AUGUST 2007

2.5 Gbps 3-TO-1 DVI/HDMI SWITCH

1

FEATURES

•

Compatible with HDMI 1.3a

•

Supports 2.5 Gbps Signaling Rate for 480i/p,

720i/p, and 1080i/p Resolutions up to 12-Bit

Color Depth

•

Integrated Receiver Termination

•

Selectable Receiver Equalization to

Accommodate to Different Input Cable

Lengths

•

Intra-Pair Skew < 40 ps

•

Inter-Pair Skew < 65 ps

•

HBM ESD Protection Exceeds 8 kV to TMDS

Inputs

•

3.3-V Fixed Supply to TMDS I/Os

•

5-V Fixed Supply to HPD, DDC, and Source

Selection Circuits

•

64-Pin TQFP Package

•

ROHS Compatible and 260

°

C Reflow Rated

APPLICATIONS

•

Digital TV

•

Digital Projector

DESCRIPTION

The TMDS351 is a 3-port digital video interface (DVI) or high-definition multimedia interface (HDMI) switch that allows up to 3 DVI or HDMI ports to be switched to a single display terminal. Four TMDS channels, one hot plug detector, and a digital display control (DDC) interface are supported on each port. Each TMDS channel supports signaling rates up to 2.5 Gbps to allow 1080p resolution in 12-bit color depth.

When S1 is high and S2 is low, all input terminations are disconnected, TMDS inputs are high impedance with standard TMDS terminations, all internal MOSFETs are turned off to disable the DDC links, and all HPD outputs are connected to the HPD_SINK. This allows the initiation of the HDMI physical address discovery process.

Termination resistors (50Ω), pulled up to V

CC

, are integrated at each TMDS receiver input. External terminations are not required. A precision resistor is connected externally from the VSADJ pin to ground for setting the differential output voltage to be compliant with the TMDS standard.

The TMDS351 provides two levels of receiver input equalization for different ranges of cable lengths. Each

TMDS receiver owns frequency responsive equalization circuits. When EQ sets low, the receiver supports the input connection in short range HDMI cables. When EQ sets high, the receiver supports the input connection in long range HDMI cables. The TMDS351 supports power saving operation. When a system is under standby mode and there is no digital audio/visual content from a connected source, the 3.3-V supply voltage, V

CC

, can be powered off to minimize power consumption from the TMDS inputs, outputs, and internal switching circuits. The

HPD, DDC, and source selection circuits are powered up by the 5-V supply voltage, V

DD

, to maintain the system hot plug detect response, the DDC link from the selected source to the sink under system standby operation. The device is characterized for operation from 0

°

C to 70

°

C.

Typical Application

DVD Player

Digital TV

Game

Console

STB

TMDS351

3-to-1

PHY SX

1

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

Copyright © 2007, Texas Instruments Incorporated

TMDS351

SLLS840A – MAY 2007 – REVISED AUGUST 2007 ..........................................................................................................................................................

www.ti.com

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.

FUNCTIONAL BLOCK DIAGRAM

EQ

A24

B24

Vcc

RINT RINT

TMDS

Rx

A23

Vcc

RINT RINT

TMDS

Rx

B23

Vcc

RINT RINT

A22

TMDS

Rx

B22

Vcc

A21

RINT RINT

B21

TMDS

Rx

Vcc

A34

RINT RINT

TMDS

Rx

B34

Vcc

A33

RINT RINT

TMDS

Rx

B33

Vcc

A32

RINT RINT

TMDS

Rx

B32

Vcc

A31

RINT RINT

TMDS

Rx

B31

HPD1

HPD2

HPD3

TMDS

Driver

TMDS

Driver

TMDS

Driver

TMDS

Driver

Y4

Z4

Y3

Z3

Y2

Z2

Y1

Z1

VSADJ

Control

Logic

S1

S2

HPD_SINK

SCL1

SDA1

SCL2

SDA2

SCL3

SDA3

SCL_SINK

SDA_SINK

HPD/DDC

Power Supply

V

DD

2

Submit Documentation Feedback

Product Folder Link(s):

TMDS351



..........................................................................................................................................................


PAG PACKAGE

(TOP VIEW)

SDA3

SCL3

GND

B31

A31

Vcc

B32

A32

GND

B33

A33

Vcc

B34

A34

GND

VSADJ

12

13

14

15

16

8

9

6

7

10

11

3

4

5

1

2

TMDS351

64-pin TQFP

44

43

42

41

40

39

38

48

47

46

45

37

36

35

34

33

A14

B14

Vcc

A13

B13

GND

A12

B12

Vcc

A11

B11

SCL1

SDA1

HPD1

EQ

S2



TMDS351


3

TMDS351

HPD1

HPD2

HPD3

HPD_SINK

SCL1

SCL2

SCL3

SCL_SINK

SDA1

SDA2

SDA3

SDA_SINK

S1, S2

V

CC

V

DD

VSADJ

Y1, Y2, Y3, Y4

Z1, Z2, Z3, Z4


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TERMINAL FUNCTIONS

TERMINAL

NAME

A11, A12, A13, A14

NO.

39, 42, 45, 48

A21, A22, A23, A24

A31, A32, A33, A34

54, 57, 60, 63

5, 8, 11, 14

B11, B12, B13, B14

B21, B22, B23, B24

B31, B32, B33, B34

GND

38, 41, 44, 47

53, 56, 59, 62

4, 7, 10, 13

3, 9, 15, 22, 28,

43, 58

EQ 34

37

52

2

29

36

51

1

35

50

64

31

30

32. 33

6, 12, 19, 25, 40,

46, 55, 61

49

16

26,23,20,17

27,24,21,18

I/O

I

I/O

I/O

I/O

I/O

I/O

O

O

O

I

I/O

I/O

I/O

I

I

O

O

I

I

I

I

I

I

DESCRIPTION

Source port 1 TMDS positive inputs



Source port 1 TMDS negative inputs



Ground

TMDS Input equalization selector (control pin)

EQ = Low – HDMI 1.3 compliant cable

EQ = High – 10m 28 AWG HDMI cable

Source port 1 hot plug detector output (status pin)



Sink port hot plug detector input (status pin)

Source port 1 DDC I

2

C clock line

Source port 2 DDC I

2

C clock line

Source port 3 DDC I

2

C clock line

Sink port DDC I

2

C clock line

Source port 1 DDC I

2

C data line

Source port 2 DDC I

2

C data line

Source port 3 DDC I

2

C data line

Sink port DDC I

2

C data line

Source selector

Power supply

HPD/DDC Power supply

TMDS compliant voltage swing control (control pin)

Sink port TMDS positive outputs

Sink port TMDS negative outputs

4



TMDS351



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CONTROL PINS

S2

H

H

L

L

S1

H

L

L

H

Table 1. Source Selection Lookup

(1)

HOT PLUG DETECT STATUS

Y/Z

I/O SELECTED

SCL_SINK

SDA_SINK

A1/B1

Terminations of A2/B2 and A3/B3 are disconnected

A2/B2


A3/B3


SCL1

SDA1

SCL2

SDA2

SCL3

SDA3

None (Z)

All terminations are disconnected

None (Z)

Are pulled HIGH by external pull-up termination

HPD1

HPD_SINK

L

L

HPD_SINK

HPD2

L

HPD_SINK

L

HPD_SINK

HPD3

L

L

HPD_SINK

HPD_SINK

(1) H: Logic high; L: Logic low; X: Don't care; Z: High impedance



TMDS351


5

TMDS351


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EQUIVALENT INPUT AND OUTPUT SCHEMATIC DIAGRAMS

TMDS Input Stage

TMDS Output Stage

V

CC

V

CC

Y

Z

50 W

A

50 W

B

Control Input Stage

V

CC

10 mA

Status and Source Selector

V

DD

EQ HPD_SINK

S1

S2

HPD output stage

V

DD

HPD1

HPD2

HPD3

SCL/SDA

Source

DDC pass gate

V

DD

SCL/SDA

Sink

6



TMDS351



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PART NUMBER

TMDS351PAG

TMDS351PAGR

ORDERING INFORMATION

(1)

PART MARKING

TMDS351

TMDS351

PACKAGE

64-PIN TQFP

64-PIN TQFP Tape/Reel

(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI web site at www.ti.com.

ABSOLUTE MAXIMUM RATINGS

over operating free-air temperature range (unless otherwise noted)

(1)

Supply voltage range

(2)

Voltage range

Electrostatic discharge

V

CC

V

DD

Anm

(3)

, Bnm

Ym, Zm, VSADJ, EQ

SCLn, SCL_SINK, SDAn, SDA_SINK, HPDn, HPD_SINK, S1, S2

Anm, Bnm

Human body model

(4)

Charged-device model

(5)

(all pins)

Machine model

(6)

(all pins)

Continuous power dissipation

All pins

UNIT

–0.5 V to 4 V

–0.5 V to 6 V

2.5 V to 4 V

–0.5V to 4 V

–0.5 V to 6 V

±8000 V

±4000 V

±1500 V

±200 V

See Dissipation Rating

Table

(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating

conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) All voltage values, except differential I/O bus voltages, are with respect to network ground terminal.

(3) n = 1, 2, 3; m = 1, 2, 3, 4

(4) Tested in accordance with JEDEC Standard 22, Test Method A114-B

(5) Tested in accordance with JEDEC Standard 22, Test Method C101-A

(6) Tested in accordance with JEDEC Standard 22, Test Method A115-A

DISSIPATION RATINGS

PACKAGE

64-TQFP PAG

PCB JEDEC

STANDARD

Low-K

High-K

T

A

≤ 25

°

C

1111 mW

1492 mW

DERATING FACTOR

ABOVE T

A

= 25

°

C

11.19 mW/

°

C

(1)

14.92

(1) This is the inverse of the junction-to-ambient thermal resistance when board-mounted and with no air flow.

T

A

= 70

°

C

POWER RATING

611 mW

820 mW

THERMAL CHARACTERISTICS

over operating free-air temperature range (unless otherwise noted)

TEST CONDITIONS

R

θ

JB

R

θ

JC

PARAMETER

Junction-to-board thermal resistance

Junction- to-case thermal resistance

P

D

Device power dissipation

V

IH

= V

CC

, V

IL

= V

CC

- 0.6 V, R

T

= 50 Ω, AV

Am/Bm(2:4) = 2.5-Gbps HDMI data pattern,

CC

Am/Bm(1) = 250-MHz clock

= 3.3V,

(1) The maximum rating is simulation under 3.6-V V

CC

, 5.5-V V

DD

, and 600 mV V

ID

.

MIN TYP MAX

(1)

33.4

15.6

UNIT

°

C/W

°

C/W

590 750 mW



TMDS351


7

TMDS351


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RECOMMENDED OPERATING CONDITIONS

V

CC

Supply voltage

V

DD

T

A

Standby supply voltage

Operating free-air temperature

TMDS DIFFERENTIAL PINS

V

IC

V

ID

R

VSADJ

AV

CC

R

T

Input common mode voltage

Receiver peak-to-peak differential input voltage

Resistor for TMDS compliant voltage swing range

TMDS output termination voltage, see

Termination resistance, see

Signaling rate

Figure 1

Figure 1

CONTROL PINS

V

IH

V

IL

LVTTL High-level input voltage

LVTTL Low-level input voltage

DDC I/O PINS

V

I(DDC)

DDC Input voltage

STATUS and SOURCE SELECTOR PINS

V

IH

V

IL

LVTTL High-level input voltage

LVTTL Low-level input voltage

MIN NOM

3 3.3

4.5

0

5

V

CC

–0.4

150

3.66

4.02

3 3.3

45

0

50

V

CC

+0.01

V

1560 mVp-p

4.47

3.6

k Ω

V

55 Ω

2.5

Gbps

2

GND

GND

2

GND

MAX UNIT

3.6

V

5.5

70

V

°

C

V

CC

0.8

V

DD

V

DD

0.8

V

V

V

V

V

ELECTRICAL CHARACTERISTICS

over recommended operating conditions (unless otherwise noted)

PARAMETER

I

CC

I

DD

Supply current

Power supply current, 5-V

V

IH

R

T

= V

= 50

CC

, V

IL

Ω, AV

= V

CC

TEST CONDITIONS

CC

– 0.6 V,

= 3.3 V

Am/Bm(2:4) = 2.5 Gbps HDMI data pattern

Am/Bm(1) = 250 MHz clock

V

IH

R

T

= V

= 50

CC

, V

IL

Ω, AV

= V

CC

CC

– 0.6 V,

= 3.3 V

Am/Bm(2:4) = 2.5 Gbps HDMI data pattern

Am/Bm(1) = 250 MHz clock

S1/S2 =

Low/Low,

Low/High,

High/High

S1/S2 =

High/Low

TMDS DIFFERENTIAL PINS

V

OH

V

OL

V swing

V

OD(O)

V

OD(U)

Single-ended high-level output voltage

Single-ended low-level output voltage

Single-ended output swing voltage

Overshoot of output differential voltage

Undershoot of output differential voltage

ΔV

OC(SS)

Change in steady-state common-mode output voltage between logic states

I

(OS)

V

I(open)

Short circuit output current

Single-ended input voltage under high impedance input or open input

R

INT

Input termination resistance

I

I

CONTROL PINS

IH

High-level digital input current

(2)

IL

Low-level digital input current

(2)

DDC I/O PINS

I lkg

C

IO

Input leakage current

Input/output capacitance

See

Figure 2 , AV

CC

R

T

= 50 Ω

= 3.3 V,

See

Figure 3

I

I

= 10 µA

V

IN

= 2.9 V

V

IH

= 2 V or V

CC

V

IL

= GND or 0.8 V

V

I

= 0.1 V

DD to 0.9 V

DD to isolated DDC inputs

V

I(pp)

= 1 V, 100 kHz

(1) All typical values are at 25

°

C and with a 3.3-V supply.

(2) I

IH and I

IL specifications are not applicable to the VSADJ pin.

8



TMDS351

MIN TYP

(1)

AV

CC

–10

AV

CC

–600

400

-12

V

CC

–10

45

-10

-10

-10

176

8

2

MAX UNIT

200

20

5

50

AV

CC

+10

AV

CC

–400 mV mV

600 mV

15% 2

×

V swing

25% 2

×

V swing

5 mV

12

V

CC

+10

55 mA mV

Ω

10

10

10

10 mA mA

µA

µA

µA pF



..........................................................................................................................................................


ELECTRICAL CHARACTERISTICS (continued)

over recommended operating conditions (unless otherwise noted)

PARAMETER

I

IH

I

IL

V

OH

V

OL

R

ON

V

PASS

Switch resistance

Switch output voltage

STATUS AND SOURCE SELECTOR PINS

High-level digital input current

Low-level digital input current

TTL High-level output voltage

TTL Low-level output voltage

TEST CONDITIONS

I

O

= 3 mA, V

O

= 0.4 V

V

I

= 5 V, I

O

= 100 µA

V

IH

= 2 V or V

DD

V

IL

= GND or 0.8 V

I

OH

= –100

µ

A

I

OL

= 100

µ

A

MIN TYP

(1)

27

1.9

-10

-10

2.4

GND

MAX

40

3.6

UNIT

Ω

V

10

10

V

DD

0.4

µA

µA

V

V

SWITCHING CHARACTERISTICS

(1)

over recommended operating conditions (unless otherwise noted) t t t t t

SX t en t dis t jit(pp)

PARAMETER

TMDS DIFFERENTIAL PINS (Y/Z)

t

PLH t

PHL t r t f t sk(p) t sk(D) t sk(o) t sk(pp) t jit(pp)

Propagation delay time, low-to-high-level output

Propagation delay time, high-to-low-level output

Differential output signal rise time (20% - 80%)

Differential output signal fall time (20% - 80%)

Pulse skew (|t

PHL

Intra-pair differential skew, see

Part-to-part skew

– t

PLH

|)

(3)

(5)

Figure 4

Inter-pair channel-to-channel output skew

(4)

Peak-to-peak output jitter from Yj/Zj(1) residual jitter

Peak-to-peak output jitter from Yj/Zj(2:4) residual jitter pd(DDC) sx(DDC) pd(HPD) sx(HPD)

Select to switch output

Enable time

Disable time

Propagation delay from SCLn to SCL_SINK or SDAn to

SDA_SINK or SDA_SINK to SDAn

Switch time from SCLn to SCL_SINK

Propagation delay (from HPD_SINK to the active port of HPD)

Switch time from port select to the latest valid status of HPD

TEST CONDITIONS

See

Figure 2

, AV

CC

R

T

= 3.3 V,

= 50 Ω, PRE = 0 V

See

Figure 5

,

Am/Bm(1) = 250 MHz clock,

Am/Bm(2:4) = 2.5 Gbps HDMI pattern

See

Figure 6

,

10-mA Current source to the input

See

Figure 7

, C

L

= 10 pF

MIN

400

400

60

60

TYP

(2)

8

60

50

170

9

650

650

80

80

6

20

30

8

8

14

33

MAX UNIT

15

15

20

50 ns ns ns ns

(1) Measurements are made with the Agilent 81250 ParBert System with a N4872A generator (600 fs t

JIT(CLK)

, 13 ps t

JIT(pp)

) and a N4873A analyzer.

(2) All typical values are at 25

°

C and with a 3.3-V supply.

(3) t sk(p)

(4) t sk(o) is the magnitude of the time difference between t

PLH and t

PHL of a specified terminal.

is the magnitude of the difference in propagation delay times between any specified terminals of a sink-port bank when inputs of the active source port are tied together.

(5) t sk(pp) is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both devices operate with the same source, the same supply voltages, at the same temperature, and have identical packages and test circuits.

900

900

140

140

20

40

65

510

20

80

70

250

15 ps ps ps ps ps ps ps ps ps ps ns ns ns



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TMDS351


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PARAMETER MEASUREMENT INFORMATION

RT

AVcc

RT

Z

O

= R

T

TMDS

Driver

TMDS

Receiver

Z

O

= R

T

Figure 1. Termination for TMDS Output Driver

R

INT

Vcc

R

INT

A

V

A

VID

B

V

B

V

ID

A

TMDS

Receiver

V

B

TMDS

Driver

V swing

RT

Y

CL

0.5 pF

Z

V

Z

V

Z

V

Y

RT

AVcc

V

A

V

B

V

ID

V

ID(pp)

V

ID

DC Coupled

Vcc

AC Coupled

Vcc+0.2 V

Vcc−0.4 V

0.4 V

Vcc−0.2 V

0 V

−0.4 V t

PHL t

PLH

V swing

80%

100%

V OD(O)

0V Differential

VOD(pp)

20%

0% t f t r

VOD(U)

V

OC n

V

OC(SS)

NOTE: All input pulses are supplied by a generator having the following characteristics: t r

Agilent 81250. C

L or t f

< 100 ps, 100 MHz from includes instrumentation and fixture capacitance within 0.06 m of the D.U.T. Measurement equipment provides a bandwidth of 20 GHz minimum.

Figure 2. Timing Test Circuit and Definitions

10



TMDS351



..........................................................................................................................................................


PARAMETER MEASUREMENT INFORMATION (continued)

50

W

I

OS

TMDS

Driver

50

W

+

_

0 V or 3.6 V

V

Y

V

Z

Figure 3. Short Circuit Output Current Test Circuit

V

OH

50% t sk(D)

Figure 4. Definition of Intra-Pair Differential Skew

V

OL

AVcc

RT RT

Data +

Data -

Video Patterm

Generator

1000 mVpp

Differential

Clk+

Clk-

Coax

Coax

SMA

SMA

Coax

Coax

SMA

SMA

HDMI Cables

RX

+

EQ

M

U

X

OUT

TMDS351

<2" 50!

Transmission Line

<2" 50!

Transmission Line

SMA

SMA

Coax

Coax

RX

+

EQ

M

U

X

OUT

<2" 50!

Transmission Line

<2" 50!

Transmission Line

SMA

SMA

Coax

Coax

AVcc

Jitter Test

Instrument

RT RT

Jitter Test

Instrument

TP1 TP2

TP3

A.

HDMI 1.3 compliant cable when EQ = Low, and 10m 28AWG input cable when EQ = High.

B.

All jitters are measured in BER of 10

-9

C.

The residual jitter reflects the total jitter measured at the output of the DUT, TP3, subtract the total jitter from the signal generator, TP1

Figure 5. Jitter Test Circuit



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PARAMETER MEASUREMENT INFORMATION (continued)

Port 1

A

B

Port 2 A

B

Port 3 A

B

S1

Clocking

S2

VDD

2

VDD

0V t

SX t

SX

Output

75 mV

-75 mV

Hi-Z

75 mV

-75 mV t dis

Figure 6. TMDS Outputs Control Timing Definitions

t en

HPD_SINK

HPD1

HPD2

HPD3

S1

S2

SDA_SINK

SDA1

SDA2

SDA3 t pd(DDC) t pd(HPD) t pd(DDC) t pd(HPD) t sx(DDC) t sx(HPD)

1.5V

1.5V

0V

VDD

VDD

2

VDD

2

0.4 V

2.4 V

0 V

VDD

2

VDD

Figure 7. DDC and HPD Timing Definitions

12



TMDS351



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TYPICAL CHARACTERISTICS

SUPPLY CURRENT vs

SIGNAL RATE

SUPPLY CURRENT vs

FREE-AIR TEMPERATURE

200

200

S1 = S2 = HIGH

S1 = S2 = HIGH

150

V

CC

= AV

CC

= 3.3 V, T = 25°C,

TP1 V

ID(PP)

= 1200 mV

PP

, R

VSADJ

Am/Bm(2:4) HDMI Data pattern, 250 Mbps-2.5 Gbps

Am/Bm(1) Clock, 25 MHz-250 MHz

150

V

CC

= AV

CC

= 3.3 V,

V

ID(PP)

= 1200 mV

PP

, R

VSADJ

Am/Bm(2:4)

Am/Bm(1)

2.5-Gbps

250-MHz

HDMI Data pattern,

Clock

100

100

50

S1 = HIGH S2 = LOW I

DD

0

250 450 650 850 1050 1250 1450 1650 1850 2450

Signal Rate - Mbps

Figure 8.

RESIDUAL PEAK-TO-PEAK JITTER

(Data Channels) vs

SIGNAL RATE

20

See Note A

15

10

EQ = HIGH

15m 26 AWG

EQ = LOW

5m 28 AWG

5

EQ = HIGH 10m 28 AWG

EQ = LOW 3m 30 AWG

0

750 950 1150 1485

Signal Rate - Mbps

1850 2250

A.

Channels 2, 3, 4, V

CC

25

°

C, R

VSADJ

= 4.02 k

= AV

Ω, See

CC

Figure 10.

= 3.3 V, T

Figure 6

A

=

50

S1 = HIGH S2 = LOW

I

DD

0

0 10 20 30 40 50 60 70

Figure 9.


(Clock Channel) vs

FREQUENCY

5

See Note A

4


3



2

1


0

75 95 115 148.5

f - Frequency - MHz

185

A.

Channel 1, V

CC

R

VSADJ

= AV

CC

= 3.3 V, T

A

= 4.02 k

Ω, See

Figure 6

Figure 11.

= 25

°

C,

225



TMDS351


13

TMDS351


www.ti.com

TYPICAL CHARACTERISTICS (continued)


(Data Channel) vs

CABLE

20

See Note A

18

16

14

12

10

8

EQ = Low

EQ = High

6

4

2

0

1.5m

30AWG

3m 30

AWG

5m

28AWG

Cable

10m

28AWG

15m

26AWG

A.

1080p 10-Bit, V

R

VSADJ

CC

= AV

CC

= 3.3 V, T

A

= 25

°

C,

= 4.02 k Ω, See

Figure 6 , Clock

Channel = 185.6 MHz, Data Channel = 1.856

Gbps

Figure 12.

20


(Data Channel) vs

CABLE

See Note A

15

10

5

EQ = Low

EQ = High

0

1.5m

30AWG

3m 30

AWG

5m

28AWG

Cable

10m

28AWG

A.

1080p 12-Bit, V

R

VSADJ

CC

= AV

CC

= 3.3 V, T

A

= 25

°

C,

= 4.02 k Ω, See

Figure 6

, Clock

Channel = 222.8 MHz, Data Channel = 2.228

Gbps

Figure 13.

15m

26AWG

14



TMDS351



..........................................................................................................................................................


APPLICATION INFORMATION

Supply Voltage

The TMDS351 is powered up with two different power sources. One is 3.3-V V

CC other is 5-V V

DD for the TMDS circuitry, and the for HPD, DDC, and most of the control logic. It is recommended to provide the same 3.3-V power source to the TMDS circuitry of the TMDS351 and its output termination voltage. This minimizes the leakage current from the ESD protection circuitry. When the digital television (DTV) is in standby mode operation, the same common 3.3-V power source can be turned on or off. Either way will minimize the leakage current in the device, and in the receiver connected at the output where the termination is integrated.

TMDS Inputs

Selectable frequency response equalization circuitries are provided to all twelve differential input to support short range and long range cable connections. The frequency response compensation curves and target cable losses are shown in

Figure 14

and

Figure 15

.

-5

-6

-7

-8

-9

0

-1

-2

-3

-4 spec

EQ = Low

3m 30 AWG cable

-10

-11

-12

-13

0 250 500 750 1000 1250 f - Frequency - MHz

1500 1750

Figure 14. Frequency Response Compensation Curve at EQ = L

2000



TMDS351


15

TMDS351


www.ti.com

0

-2

-4

-6

-8 spec

-10

-12

-14

-16

EQ = High

10m cable

-18

-20

0 250 500 750 1000 1250 f - Frequency - MHz

1500 1750

Figure 15. Frequency Response Compensation Curve at EQ = H

2000

Internal termination circuitry which can be switched on or off, provides 50-

Ω resistance to each differential input pin when a port is selected. External terminations are not required. When the termination is switched on, current will flow to the TMDS driver. When a port is not selected, the termination is open. This stops supply current flowing from the input pins of the un-selected ports. This switchable termination provides the connected HDMI source another method of determining the sink port status, and whether it is selected or not selected, without referring to the HPD pin status.

TMDS Input Fail-Safe

The TMDS input does not incorporate a fail-safe circuit. To implement fail-safe, the input can be externally biased to prevent output oscillation. One pin can be pulled high to V as shown in

Figure 16 .

CC with the other grounded through a 1-k

Ω resistor

R

INT

V

CC

R

INT

A

TMDS

Receiver

B

TMDS

Driver

Y

Z

R

T

R

T

AV

CC

Figure 16. TMDS Input Fail-Safe Recommendation

TMDS Outputs

A 10% precision resistor, 4.02-k Ω, is recommended to control the output swing to the HDMI compliant 400 mV to

600 mV range (500 mV typical). The TMDS outputs are high impedance under standby mode operation, S1 = H and S2 = L.

16




TMDS351


..........................................................................................................................................................


HPD Pins

The HPD circuits are powered by the 5-V supply. They provide 5-V TTL output signals to the SOURCE with a typical 1-k

Ω output resistance. An external 1-kΩ resistor is not needed here. The HPD output of the selected source port follows the logic level of the HPD_SINK input. Unselected HPD outputs are kept low. When the device is in standby mode, all HPD outputs follow HPD_SINK. A 1-k

Ω resistor to ground keeps all HPD outputs low in standby mode if a fixed low state is preferred.

DDC Channels

The DDC circuits (SDA, SCL) are powered by a 5-V supply. The I/O pins can connect to the 5-V termination voltages directly. A 47-k

Ω pull-up resistor to the 5 V is recommended on the SCL1, SCL2, and SCL3 pins. There is no pull-up resistor on the SDA pins. The pull-up resistor can be replaced with a different value.

Source Sink

V

DDSource

V

DDSink

V

CCRx

R upSource

R upSink

R upRx

I to-Source

Ron

SCL_SINK

SDA_SINK

SCL

SDA

I to-Sink

Driver (Source) Driver (Sink)

Figure 17. Simplified Electrical Circuit Model for DDC Channel

In

Figure 17

, when the Driver (Sink) pulls the bus low, the highest voltage level is V ol(Sink)max through the pass-gate resistor can be presented as:

. The current flow

V dd

*

V ol

(

Sink)max

Ito

*

Sink

+

R upSource

ø

R upSink

(1) where the V ddsource

= V ddsink

= V dd

To simplify the equation, V ol(Sink)max lto

*

Sink

+

V dd

R upSource

ø

R upSink is set equal to 0 V to reach equation (2):

(2)

The voltage at the input of the SINK is Ito - Sink

×

Ron + V ol(Sink)max input low threshold voltage of the Driver (Source), V ith(Source)min

, which should be lower than the minimum to keep the bus in correct interoperations.

V ith(Source)min u lto

*

Sink Ron

)

V ol(Sink)max

(3)

By combining equations (2) and (3), the minimum pull-up resistor at the Sink input is:

V dd

Ron R upSource

R upSink w

(V ith(Source)min

*

V ol(Sink)max

) R upSource

*

V dd

Ron

(4)

Applying the same methodology to calculate the pull-up resistor at the input of the Driver (Sink), the minimum pull-up resistor is:

R upRx

V ccRx

Ron w

(V ith(Sink)min

*

V ol(Source)max

)

(5)

The data sheet V

PASS specification ensures the maximum output voltage is clamped at 3.6 V to support a 3.3-V connection. Resistors pulling up to 3.3 V on SCL_SINK and SDA_SINK ensure the high level does not exceed the 3.3-V termination voltage.



17


TMDS351

TMDS351


www.ti.com

Layout Considerations

The high-speed differential TMDS inputs are the most critical paths for the TMDS351. There are several considerations to minimize discontinuities on these transmission lines between the connectors and the device:

•

Maintain 100-

Ω differential transmission line impedance into and out of the TMDS351

•

Keep an uninterrupted ground plane beneath the high-speed I/Os

•

Keep the ground-path vias to the device as close as possible to allow the shortest return current path

•

Keep the trace lengths of the TMDS signals between connector and device as short as possible

Using the TMDS351 in Systems with Different CEC Link Requirements

The TMDS351 supports a DTV with up to three HDMI inputs when used in conjunction with a signal-port HDMI receiver or four HDMI inputs when used in conjunction with a dual-port HDMI receiver.

Figure 18

and

Figure 19

show simplified application block diagrams for the TMDS351 in different DTVs with different consumer electronic control (CEC) requirements. The CEC is an optional feature of the HDMI interface for centralizing and simplifying user control instructions from multiple audio/video products in an inter-connected system, even when all the audio/video products are from different manufacturers. This feature minimizes the number of remote controls in a system, as well as reducing the number of times buttons need to be pressed.

A DTV Supporting a Passive CEC Link

In

Figure 18 , the DTV does not have the capability of handling CEC signals, but allows CEC signals to pass over

the CEC bus. The source selection is done by the control command of the DTV. The user cannot force the command from any audio/video product on the CEC bus. The selected source reads the E-EDID data after receiving an asserted HPD signal. The micro-controller loads different CEC physical addresses while changing the source by means of the S1 and S2 pins.

E-EDID Reading Configurations in Standby Mode

When the DTV system is in standby mode, the sources will not read the E-EDID memory because the 1-k Ω pull-down resistor keeping the HPD_SINK input at logic low forces all HPD pins to output logic low to all sources.

The source will not read the E-EDID data with a low on HPD signal. However, if reading the E-EDID data in the system standby mode is preferred, then TMDS351 can still support this need.

The recommended configuration sequences are:

1. Apply the same 3.3-V power to the V

CC

2. Turn off V

CC

, and keep V circuits are active.

DD of TMDS351 and the TMDS line termination at the HDMI receiver on. The TMDS circuit is off, but the HPD, the DDC and the source selection

3. Set S1 and S2 to select the source port which is allowed to read the E-EDID memory.

Please note if the source has a time-out limitation between the 5 V and the HPD signals, the above configuration is not applicable. Uses individual EEPROMs assigned for each input port, see

Figure 19 . The solution uses

E-EDID data to be readable during system power off or standby mode operations.

18



TMDS351



..........................................................................................................................................................


SOURCE 1

SOURCE 2

SOURCE 3

HPD

5V

SDA

SCL

CEC

CLK

D0

D1

D2

HPD

5V

SDA

SCL

CEC

CLK

D0

D1

D2

HPD

5V

SDA

SCL

CEC

CLK

D0

D1

D2

SINK

HPD

5V

SDA

SCL

CEC

CLK

D0

D1

D2

5V

47kW

CEC

HPD

5V

SDA

SCL

CEC

CLK

D 0

D 1

D2

5V

47kW

CEC

HPD

5V

SDA

SCL

CEC

CLK

D0

D1

D2

5V

47kW

CEC

HPD1

SDA1

SCL1

A11/B11

A12/B12

A13/B13

A14/B14

HPD2

SDA2

SCL2

A21/B21

A22/B22

A23/B23

A24/B24

HPD3

SDA3

SCL3

A31/B31

A32/B32

A33/B33

A34/B34

VDD

(5 V)

VCC

(3.3 V)

GND

EQ

S1

S2 mController

HPD_SINK

SDA_SINK

SCL_SINK

Y1/Z1

Y2/Z2

Y3/Z3

Y4/Z4

1kW

E-EDID

4.7kW

3.3V

4.7kW

DDC_SDA

DDC_SCL

HDMI RX

Y1/Z1

Y2/Z2

Y3/Z3

Y4/Z4

VSADJ

4.02 kW 10%

Figure 18. Three-Port HDMI Enabled DTV with TMDS351 – CEC Commands Passing Through

A DTV Supporting an Active CEC Link

In

Figure 19

, the CEC PHY and CEC LOGIC functions are added. The DTV can initiate and/or react to CEC signals from its remote control or other audio/video products on the same CEC bus. All sources must have their own CEC physical address to support the full functionality of the CEC link.

A source reads its CEC physical address stored its E-EDID memory after receiving a logic-high from the HPD feedback. When HPD is high, the sink-assigned CEC physical address should be maintained. Otherwise, when

HPD is low the source sets CEC physical address value to (F.F.F.F).

Case 1 – AC Coupled Source (See

Figure 19

, Port 1)

When the source TMDS lines are AC coupled or when the source cannot detect the TMDS termination provided in the connected sink, the indication of the source selection can only come from the HPD signal. The TMDS351

HPD1 pin should be applied directly as the HPD signal back to the source.

Case 2 – DC Coupled Source (See

Figure 19

, Port 2)

When the source TMDS lines are DC coupled, there are two methods to inform the source that it is the active source to the sink. One is checking the HPD signal from the sink, and the other is checking the termination condition in the sink.

In a full CEC operation mode, the HPD signal is set high whether the port is selected or not. The source loads and maintains the CEC physical address when HPD is high. As soon as HPD goes low, the source loses the

CEC physical address. To keep the CEC physical address to the source, the HPD signal is looping back from the source provided 5-V signal through a 1-k

Ω pull-up resistor in the sink. This method is acceptable in application where the HDMI transmitter can detect the receiver termination by current sensing, and the receiver has switchable termination on the TMDS inputs. The internal termination resistors are connected to the termination voltage when the port is selected, or they are disconnected when the port is not selected. The TMDS351 features switchable termination on the TMDS inputs.



19


TMDS351

TMDS351


www.ti.com

Case 3 – External Logic Control for HPD (See

Figure 19

, Port 3)

When the HDMI transmitter does not have the capability of detecting the receiver termination, using the HPD signal as a reference for sensing port selections is the only possible method. External control logic for switching the connections of the HPD signals between the HPD pins of the TMDS351 and the 5-V signal from the source provides a good solution.

E-EDID Reading Configurations in Standby Mode

When the TMDS351 is in standby mode operation, S1 = H and S2 = L, all sources can read their E-EDID memories simultaneously with all HPD pins following HPD_SINK in logic-high. HPD_SINK input low will prevent

E-EDID reading in standby mode operation.

SINK

VDD

(5 V)

VCC

(3.3 V)

SOURCE 1

With AC Coupled

HDMI Output

HPD

5V

SDA

SCL

CEC

CLK

D0

D1

D2

HPD

5V

SDA

SCL

CEC

CLK

D0

D1

D2

5 V

47kW

CEC

E-EDID

HPD1

SDA1

SCL1

A11/B11

A12/B12

A13/B13

A14/B14

EQ

S1

S2

SDA SCL mController

CEC

LOGIC

SOURCE 2

With DC Coupled

HDMI Output

SOURCE 3 in General

HDMI Output

HPD

5V

SDA

SCL

CEC

CLK

D0

D1

D2

HPD

5V

SDA

SCL

CEC

CLK

D0

D1

D2

HPD

5V

SDA

SCL

CEC

CLK

D0

D1

D2

HPD

5V

SDA

SCL

CEC

CLK

D0

D1

D2

CEC

PHY

5 V

47kW

CEC E-EDID

1 kW

5 V

47kW

CEC E-EDID

1 k W

HPD2

SDA2

SCL2

A21/B21

A22/B22

A23/B23

A24/B24

HPD3

SDA3

SCL3

A31/B31

A32/B32

A33/B33

A34/B34

GND

HPD_SINK

1 kW

SDA_SINK

4.7kW

SCL_SINK

3.3 V

4.7kW

DDC_SDA

DDC_SCL

Y1/Z1

Y2/Z2

Y3/Z3

Y4/Z4

HDMI RX

Y1/Z1

Y2/Z2

Y3/Z3

Y4/Z4

VSADJ

4.02 k W 10%

Figure 19. Three-Port HDMI Enabled DTV with TMDS351 – CEC Commands Active

20



TMDS351


www.ti.com

PACKAGE OPTION ADDENDUM

25-Sep-2007

PACKAGING INFORMATION

Orderable Device

TMDS351PAG

TMDS351PAGG4

TMDS351PAGR

TMDS351PAGRG4

Status

(1)

ACTIVE

ACTIVE

ACTIVE

ACTIVE

Package

Type

TQFP

TQFP

TQFP

TQFP

Package

Drawing

PAG

PAG

PAG

PAG

Eco Plan

(2)

Pins Package

Qty

64 160 Green (RoHS & no Sb/Br)

Lead/Ball Finish MSL Peak Temp

(3)

CU NIPDAU Level-3-260C-168 HR

64 CU NIPDAU Level-3-260C-168 HR

64

160 Green (RoHS & no Sb/Br)

1500 Green (RoHS & no Sb/Br)


64 1500 Green (RoHS & no Sb/Br)


(1)

The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2)

Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

(3)

MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 1

www.ti.com

TAPE AND REEL INFORMATION

PACKAGE MATERIALS INFORMATION

8-Aug-2008

*All dimensions are nominal

Device

TMDS351PAGR

Package

Type

Package

Drawing

TQFP PAG

Pins

64

SPQ

1500

Reel

Diameter

(mm)

Reel

Width

W1 (mm)

330.0

24.4

A0 (mm)

13.0

B0 (mm)

13.0

K0 (mm) P1

(mm)

W

(mm)

Pin1

Quadrant

1.5

16.0

24.0

Q2

Pack Materials-Page 1

www.ti.com

PACKAGE MATERIALS INFORMATION

8-Aug-2008

*All dimensions are nominal

Device

TMDS351PAGR

Package Type Package Drawing Pins

TQFP PAG 64

SPQ

1500

Length (mm) Width (mm) Height (mm)

346.0

346.0

41.0

Pack Materials-Page 2

PAG (S-PQFP-G64)

0,50

48

49

33

0,27

0,17

0,08

M

32

MECHANICAL DATA

MTQF006A – JANUARY 1995 – REVISED DECEMBER 1996

PLASTIC QUAD FLATPACK

64 17

1 16

7,50 TYP

10,20

9,80

SQ

12,20

11,80

SQ

0,05 MIN

1,05

0,95

1,20 MAX

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.

C. Falls within JEDEC MS-026

Seating Plane

0,08

0,13 NOM

0,25

Gage Plane

0

°

– 7

°

0,75

0,45

4040282 / C 11/96

POST OFFICE BOX 655303

•

DALLAS, TEXAS 75265

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