TL16C2752

TL16C2752 www.ti.com

................................................................................................................................................

SLWS188A – JUNE 2006 – REVISED SEPTEMBER 2008

1.8-V to 5-V DUAL UART WITH 64-BYTE FIFOS

1

FEATURES

•

Larger FIFOs Reduce CPU Overhead

•

Programmable Auto-RTS and Auto-CTS

•

In Auto-CTS Mode, CTS Controls the

Transmitter

•

In Auto-RTS Mode, RCV FIFO Contents, and

Threshold Control RTS

•

Serial and Modem Control Outputs Drive a

RJ11 Cable Directly When Equipment is on the

Same Power Drop

•

Capable of Running With All Existing

TL16C450 Software

•

After Reset, All Registers Are Identical to the

TL16C450 Register Set

•

Up to 48-MHz Clock Rate for up to 3-Mbps

(Standard 16× Sampling) Operation, or up to

6-Mbps (Optional 8× Sampling) Operation With

V

CC

= 5 V Nominal

•




V

CC

= 3.3 V Nominal

•

Up to 24-MHz Clock Rate for up to 1.5-Mbps



V

CC

= 2.5 V Nominal

•




V

CC

= 1.8 V Nominal

•

In TL16C450 Mode, Hold and Shift Registers

Eliminate the Need for Precise

Synchronization Between the CPU and Serial

Data

•

Programmable Baud-Rate Generator Allows

Division of Any Input Reference Clock by 1 to

(2

16

– 1) and Generates an Internal 16× Clock

•

Standard Asynchronous Communication Bits

(Start, Stop, and Parity) Added to or Deleted

From the Serial Data Stream

•

5-V, 3.3-V, 2.5-V, and 1.8-V Operation

•

Independent Receiver Clock Input

•

Transmit, Receive, Line Status, and Data Set

Interrupts Independently Controlled

•

Fully Programmable Serial Interface

Characteristics

– 5-, 6-, 7-, or 8-Bit Characters

– Even-, Odd-, or No-Parity Bit Generation and Detection

– 1-, 1 ＝-, or 2-Stop Bit Generation

– Baud Generation (DC to 1 Mbit/s)

•

False-Start Bit Detection

•

Complete Status Reporting Capabilities

•

3-State Output TTL Drive Capabilities for

Bidirectional Data Bus and Control Bus

•

Line Break Generation and Detection

•

Internal Diagnostic Capabilities

– Loopback Controls for Communications

Link Fault Isolation

– Break, Parity, Overrun, and Framing Error

Simulation

•

Fully Prioritized Interrupt System Controls

•

Modem Control Functions (CTS, RTS, DSR,

DTR, RI, and DCD)

•

Available in 44-Pin PLCC (FN) or 32-Pin QFN

(RHB) Packages

•

Each UART's Internal Register Set May Be

Written Concurrently to Save Setup Time

•

Multifunction (MF) Output Allows Users to

Select Among Several Functions, Saving

Package Pins

APPLICATIONS

•

Point-of-Sale Terminals

•

Gaming Terminals

•

Portable Applications

•

Router Control

•

Cellular Data

•

Factory Automation

1

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

Copyright © 2006–2008, Texas Instruments Incorporated

TL16C2752

SLWS188A – JUNE 2006 – REVISED SEPTEMBER 2008 ................................................................................................................................................

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DESCRIPTION

The TL16C2752 is a speed and functional upgrade of the TL16C2552. Since they are pinout and software compatible, designs can easily migrate from the TL16C2552 to the TL16C2752 if needed. The additional functionality within the TL16C2752 is accessed via an extended register set. Some of the key new features are larger receive and transmit FIFOs, embedded IrDA encoders and decoders, RS-485 transceiver controls, software flow control (Xon/Xoff) modes, programmable transmit FIFO thresholds, extended receive and transmit threshold levels for interrupts, and extended receive threshold levels for flow control halt/resume operation.

The TL16C2752 is a dual universal asynchronous receiver and transmitter (UART). It incorporates the functionality of two independent UARTs: each UART having its own register set and transmit and receive FIFOs.

The two UARTs share only the data bus interface and clock source, otherwise they operate independently.

Another name for the UART function is asynchronous communications element (ACE), and these terms will be used interchangeably. The bulk of this document describes the behavior of each ACE, with the understanding that two such devices are incorporated into the TL16C2752.

Functionally equivalent to the TL16C450 on power up or reset (single character or TL16C450 mode), each ACE can be placed in an alternate FIFO mode. This relieves the CPU of excessive software overhead by buffering received and to-be-transmitted characters. Each receiver and transmitter store up to 64 bytes in their respective

FIFOs, with the receive FIFO including three additional bits per byte for error status. In the FIFO mode, selectable hardware or software autoflow control features can significantly reduce program overload and increase system efficiency by automatically controlling serial data flow.

Each ACE performs serial-to-parallel conversions on data received from a peripheral device or modem and stores the parallel data in its receive buffer or FIFO, and each ACE performs parallel-to-serial conversions on data sent from its CPU after storing the parallel data in its transmit buffer or FIFO. The CPU can read the status of either ACE at any time. Each ACE includes complete modem control capability and a processor interrupt system that can be tailored to the application.

Each ACE includes a programmable baud rate generator capable of dividing a reference clock with divisors of from 1 to 65535, thus producing a 16× or 8× internal reference clock for the transmitter and receiver logic. Each

ACE accommodates up to a 3-Mbaud serial data rate (48-MHz input clock). As a reference point, that speed would generate a 333-ns bit time and a 3.33＝s character time (for 8,N,1 serial data), with the internal clock running at 48 MHz and 16× sampling.

Each ACE has a TXRDY and RXRDY (via MF) output that can be used to interface to a DMA controller.

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TL16C2752 Block Diagram

A2−A0

D7−D0

CS

CHSEL

IOR

IOW

INTA

INTB

TXRDYA

TXRDYB

MFA

MFB

RESET

Data Bus

Interface

Baud-

Rate

Gen

UART Channel A

64-Byte TX FIFO

UART Registers

Tx

IR ENC

64-Byte RX FIFO

Rx

IR DEC

Baud-

Rate

Gen

UART Channel B

64-Byte TX FIFO

Tx

IR ENC

UART Registers

64-Byte RX FIFO

Rx

IR DEC

XTAL1

XTAL2

Crystal

OSC

Buffer

A.

MF output allows selection of OP, BAUDOUT, or RXRDY per channel.

TXA

CTSA

DTRA

DSRA, RIA, CDA

RTSA

RXA

TXB

CTSB

DTRB

DSRB, RIB, CDB

RTSB

RXB

V

CC

GND



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TL16C2752


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TERMINAL FUNCTIONS

NAME

A0

A1

A2

CDA,

CDB

CHSEL

CS

CTSA,

CTSB

D0–D4

D5–D7

DSRA,

DSRB

DTRA,

DTRB

GND

INTA,

INTB

IOR

IOW

NC

MFA,

MFB

TERMINAL

FN NO.

RHB NO.

10

14

15

3

6

7

42,

30

16

18

40,

28

2–6

7–9

41,

29

37,

27

12, 22

34,

17

24

20

–

35,

19

–

8

10

25,

17

27–31

32, 1, 2

–

–

20

21,

9

14

11

18, 19

–

I/O DESCRIPTION

I

I

I

I

Address 0 select bit. Internal registers address selection.



Carrier detect (active low). These inputs are associated with individual UART channels A and

B. A low on these pins indicates that a carrier has been detected by the modem for that channel. The state of these inputs is reflected in the modem status register (MSR). These inputs should be pulled high if unused.

I

I

I

Channel select. UART channel A or B is selected by the state of this pin when CS is a logic 0.

A logic 0 on the CHSEL selects the UART channel B, while a logic 1 selects UART channel A.

CHSEL could just be an address line from the user CPU such as A3. Bit 0 of the alternate function register (AFR) can temporarily override CHSEL function, allowing the user to write to both channel register simultaneously with one write cycle when CS is low. It is especially useful during the initialization routine.

UART chip select (active low). This pin selects channel A or B in accordance with the state of the CHSEL pin. This allows data to be transferred between the user CPU and the TL16C2752.

Clear to send (active low). These inputs are associated with individual UART channels A and

B. A logic low on the CTS pins indicates the modem or data set is ready to accept transmit data from the TL16C2752. Status can be tested by reading MSR bit 4. These pins only affect the transmit and receive operations when auto CTS function is enabled through the enhanced feature register (EFR) bit 7, for hardware flow control operation. These inputs should be pulled high if unused.

Data bus (bidirectional). These pins are the 8-bit, 3-state data bus for transferring information

I/O to or from the controlling CPU. D0 is the least significant bit (LSB) and the first data bit in a transmit or receive serial data stream.

I

Data set ready (active low). These inputs are associated with individual UART channels A and

B. A logic low on these pins indicates the modem or data set is powered on and is ready for data exchange with the UART. The state of these inputs is reflected in the modem status register (MSR). These inputs should be pulled high if unused.

Data terminal ready (active low). These outputs are associated with individual UART channels

A and B. A logic low on these pins indicates that the TL16C2752 is powered on and ready.

O These pins can be controlled through the modem control register. Writing a 1 to MCR bit 0 sets the DTR output to low, enabling the modem. The output of these pins is high after writing a 0 to MCR bit 0, or after a reset.

Signal and power ground

Interrupt A and B (active high). These pins provide individual channel interrupts, INTA and

INTB. INTA and INTB are enabled when MCR bit 3 is set to a logic 1, interrupt sources are

O enabled in the interrupt enable register (IER). Interrupt conditions include receiver errors, available receiver buffer data, available transmit buffer space, or when a modem status flag is detected. INTA and INTB are in the high-impedance state after reset.

I

I

Read input (active-low strobe). A high-to-low transition on IOR loads the contents of an internal register defined by address bits A0–A2 onto the TL16C2752 data bus (D0–D7) for access by an external CPU.

Write input (active-low strobe). A low-to-high transition on IOW transfers the contents of the data bus (D0–D7) from the external CPU to an internal register that is defined by address bits

A0–A2 and CSA and CSB.

No internal connection

O

Multifunction. This output pin can function as the OP, BAUDOUT, or RXRDY pin. One of these output signal functions can be selected by the user-programmable bits 1–2 of the alternate function register (AFR). These signal functions are described as follows:

1.

OP–When OP (active low) is selected, the MF pin is a logic 0 when MCR bit 3 is set to a logic 1 (see MCR bit 3). MCR bit 3 defaults to a logic 1 condition after a reset or powerup.

2.

BAUDOUT–When BAUDOUT function is selected, the 16× baud rate clock output is available at this pin.

3.

RXRDY–RXRDY (active low) is intended for monitoring DMA data transfers.

If it is not used, leave it unconnected.





................................................................................................................................................


TERMINAL FUNCTIONS (continued)

NAME

TERMINAL

FN NO.

RHB NO.

RESET

RIA,

RIB

RTSA,

RTSB

RXA,

RXB

TXA,

TXB

TXRDYA,

TXRDYB

V

CC

XTAL1

XTAL2

21

43,

31

36,

23

39,

25

38,

26

1,

32

33, 44

11

13

12

–

22,

13

24,

15

23,

16

–

26

4

5

I/O DESCRIPTION

I

I

I

O

Reset. RESET will reset the internal registers and all the outputs. The UART transmitter output and the receiver input are disabled during reset time. See TL16C2752 external reset conditions for initialization details. RESET is an active-high input.

Ring indicator (active low). These inputs are associated with individual UART channels A and

B. A logic low on these pins indicates the modem has received a ringing signal from the telephone line. A low-to-high transition on these input pins generates a modem status interrupt, if enabled. The state of these inputs is reflected in the modem status register (MSR).

These inputs should be pulled high if unused.

O

O

I

Request to send (active low). These outputs are associated with individual UART channels A and B. A low on the RTS pin indicates the transmitter has data ready and waiting to send.

Writing a 1 in the modem control register (MCR bit 1) sets these pins to low, indicating data is available. After a reset, these pins are set to high. These pins only affects the transmit and receive operation when auto RTS function is enabled through the enhanced feature register

(EFR) bit 6, for hardware flow control operation.

I

Receive data input. These inputs are associated with individual serial channel data to the

TL16C2752. During the local loopback mode, these RX input pins are disabled and TX data is internally connected to the UART RX input internally.

Transmit data. These outputs are associated with individual serial transmit channel data from

O the TL16C2752. During the local loopback mode, the TX input pin is disabled and TX data is internally connected to the UART RX input.

Transmit ready (active low). TXRDY A and B go low when there are at least a trigger-level number of spaces available. They go high when the TX buffer is full.

Power-supply inputs

Crystal or external clock. XTAL1 functions as a crystal input or as an external clock input. A crystal can be connected between XTAL1 and XTAL2 to form an internal oscillator circuit (see

Figure 4 ). Alternatively, an external clock can be connected to XTAL1 to provide custom data

rates.

Crystal oscillator or buffered clock (see also XTAL1). XTAL2 is used as a crystal oscillator output or buffered a clock output.

Detailed Description

Hardware Autoflow Control (see

Figure 1 )

Hardware autoflow control is comprised of auto-CTS and auto-RTS. With auto-CTS, the CTS input must be active before the transmitter FIFO can emit data. With auto-RTS, RTS becomes active when the receiver needs more data and notifies the sending serial device. When RTS is connected to CTS, data transmission does not occur unless the receiver FIFO has space for the data; thus, overrun errors are eliminated using ACE1 and

ACE2 from a TLC16C2752 with the autoflow control enabled. If not, overrun errors can occur when the transmit data rate exceeds the receiver FIFO read latency.

ACE1 ACE2

Serial to

Parallel

RX TX

RCV

FIFO

Parallel to Serial

RTS CTS

XMT

FIFO

Flow

Control

Flow

Control

D7 −D0

D7 −D0

XMT

FIFO

Parallel to Serial

TX RX Serial to

Parallel

RCV

FIFO

CTS RTS

Flow

Control

Flow

Control

Figure 1. Autoflow Control (Auto-RTS and Auto-CTS) Example

Copyright © 2006–2008, Texas Instruments Incorporated Submit Documentation Feedback


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TL16C2752


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Auto-RTS

Auto-RTS data flow control originates in the receiver timing and control block (see

Figure 4

) and is linked to the programmed receiver FIFO trigger level. When the receiver FIFO level reaches the defined halt trigger level 8

(see

Figure 3 ), RTS is deasserted. The sending ACE may send an additional byte after the trigger level is

reached (assuming the sending ACE has another byte to send) because it may not recognize the deassertion of

RTS until after it has begun sending the additional byte. RTS is automatically reasserted once the defined resume trigger level is reached.

Auto-CTS

The transmitter circuitry checks CTS before sending the next data byte. When CTS is active, it sends the next byte. To stop the transmitter from sending the following byte, CTS must be released before the middle of the last stop bit that is currently being sent (see

Figure 2 ). The auto-CTS function reduces interrupts to the host system.

When flow control is enabled, CTS level changes do not trigger host interrupts because the device automatically controls its own transmitter. Without auto-CTS, the transmitter sends any data present in the transmit FIFO and a receiver overrun error may result.

Auto-RTS and Auto-CTS Functional Timing

Start Byte N Stop Start Byte N+1 Stop Start Byte Stop SIN

RTS

RD

(RD RBR)

1 2 N

Figure 2. RTS Functional Timing Waveforms

N+1

SOUT

CTS

Start Bits 0 −7 Stop Start Bits 0 −7 Stop

Figure 3. CTS Functional Timing Waveforms

A.

Pin numbers shown are for 44-pin PLCC FN package.

Figure 4. Functional Block Diagram

Start Bits 0 −7 Stop




TL16C2752

V

CC

V

I

V

IH

V

IL

V

O

I

OH

I

OL

V

CC

V

I

V

IH

V

IL

V

O

I

OH

I

OL www.ti.com

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ABSOLUTE MAXIMUM RATINGS

(1) over operating free-air temperature range (unless otherwise noted)

V

V

V

T

T

CC

I

O

A stg

Supply voltage range

(2)

Input voltage range at any input

Output voltage range

Operating free-air temperature range

Storage temperature range

Lead temperature 1,6 mm (1/16 inch) from case for 10 s

TL16C2752

TL16C2752I

MIN

–0.5

–0.5

–0.5

0

–40

–65

MAX UNIT

7 V

7

7

70

V

V

°C

85

150

260

°C

°C

(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) All voltage values are with respect to V

SS

.

RECOMMENDED OPERATING CONDITIONS

1.8 V

＝10% over operating free-air temperature range (unless otherwise noted)

Supply voltage

Input voltage

High-level input voltage

Low-level input voltage

Output voltage

High-level output current (all outputs)

Low-level output current (all outputs)

Oscillator/clock speed

MIN NOM MAX UNIT

1.62

1.8

1.98

V

0

1.4

–0.3

0

V

CC

1.98

0.4

V

V

V

V

CC

V

0.5

mA

1 mA

10 MHz


2.5 V


Supply voltage

Input voltage



Output voltage




MIN

2.25

0

1.8

–0.3

0

NOM MAX UNIT

2.5

2.75

V

V

CC

2.75

0.6

V

V

V

V

CC

V

1 mA

2 mA

16 MHz




TL16C2752

V

IL

V

O

I

OH

I

OL


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3.3 V


V

CC

V

I

V

IH

V

IL

V

O

I

OH

I

OL

Supply voltage

Input voltage



Output voltage




MIN

3

0

0.7 × V

CC

0

NOM

3.3

MAX UNIT

3.6

V

V

CC

V

V

0.3 × V

CC

V

V

CC

V

1.8

mA

3.2

mA

20 MHz


5 V


V

CC

V

I

V

IH

Supply voltage

Input voltage



Output voltage




All except XTAL1, XTAL2

XTAL1, XTAL2

All except XTAL1, XTAL2

XTAL1, XTAL2

MIN

4.5

0

2

0.7 × V

CC

0

NOM

5

MAX UNIT

5.5

V

V

CC

V

V

0.8

0.3 × V

CC

V

CC

4

V

V mA

4 mA

24 MHz

ELECTRICAL CHARACTERISTICS

1.8 V Nominal

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

V

OH

V

OL

I

I

I

OZ

I

CC

PARAMETER

High-level output voltage

(2)

Low-level output voltage

(2)

Input current

High-impedance-state output current

Supply current

TEST CONDITIONS

I

OH

= –0.5 mA

I

OL

= 1 mA

V

CC

= 1.98 V, V

SS

= 0, V

I

All other terminals floating

= 0 to 1.98 V,

V

CC

= 1.98 V, V

SS

= 0, V

I

= 0 to 1.98 V,

Chip selected in write mode or chip deselected

V

CC

= 1.98 V, T

A

= 0°C, RXA, RXB, DSRA, DSRB, CDA,

CDB, CTSA, CTSB, RIA, and RIB at 1.4 V, All other inputs at

0.4 V, XTAL1 at 16 MHz, No load on outputs

MIN TYP

(1)

1.3

C i(CLK)

Clock input impedance 15

C

O(CLK)

Clock output impedance

V

CC

T

A

= 0, V

SS

= 0, f = 1 MHz,

= 25°C, All other terminals grounded

20

C

I

C

O

Input impedance

Output impedance

6

10

MAX UNIT

0.5

V

V

10 ＝A

±20 ＝A mA

20 pF

30 pF

10 pF

20 pF

(1) All typical values are at V

CC

= 1.8 V and T

A

= 25°C.

(2) These parameters apply for all outputs except XTAL2.





................................................................................................................................................



2.5 V Nominal


V

OH

V

OL

I

I

I

OZ

I

CC

PARAMETER


(2)


(2)

Input current


Supply current

TEST CONDITIONS

I

OH

= –1 mA

I

OL

= 2 mA

V

CC

= 2.75 V, V

SS

= 0, V

I


= 0 to 2.75 V,

V

CC

= 2.75 V, V

SS

= 0, V

I

= 0 to 2.75 V,


V

CC

= 2.75 V, T

A


CDB, CTSA, CTSB, RIA, and RIB at 1.8 V, All other inputs at 0.6 V, XTAL1 at 24 MHz, No load on outputs

MIN TYP

(1)

1.8

C i(CLK)


C

O(CLK)


V

CC

T

A

= 0, V

SS

= 0, f = 1 MHz,


20

C

I

C

O

Input impedance

Output impedance

6

10

MAX UNIT

V

0.5

V

10 ＝A

±20 ＝A

20

30

10

20 mA pF pF pF pF


CC

= 2.5 V and T

A

= 25°C.



3.3 V Nominal


V

OH

V

OL

I

I

I

OZ

I

CC

PARAMETER


(2)


(2)

Input current


Supply current

TEST CONDITIONS

I

OH

= –1.8 mA

I

OL

= 3.2 mA

V

CC

= 3.6 V, V

SS

= 0, V

I

= 0 to 3.6 V,


V

CC

= 3.6 V, V

SS

= 0, V

I

= 0 to 3.6 V,


V

CC

= 3.6 V, T

A


CDB, CTSA, CTSB, RIA, and RIB at 2 V, All other inputs at 0.8 V, XTAL1 at 32 MHz, No load on outputs

MIN TYP

(1)

2.4

C i(CLK)


C

O(CLK)


V

CC

T

A

= 0, V

SS

= 0, f = 1 MHz,


20

C

I

C

O

Input impedance

Output impedance

6

10


CC

= 3.3 V and T

A

= 25°C.


MAX UNIT

V

0.5

V

10 ＝A

±20 ＝A

20

30

10

20 mA pF pF pF pF




TL16C2752


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5 V Nominal


V

OH

V

OL

I

I

I

OZ

I

CC

PARAMETER


(2)


(2)

Input current


Supply current

TEST CONDITIONS

I

OH

= –4 mA

I

OL

= 4 mA

V

CC

= 5.5 V, V

SS

= 0, V

I

= 0 to 5.5 V,


V

CC

= 3.6 V, V

SS

= 0, V

I

= 0 to 3.6 V,


V

CC

= 5.5 V, T

A


CDB, CTSA, CTSB, RIA, and RIB at 2 V,

All other inputs at 0.8 V, XTAL1 at 32 MHz,

No load on outputs

MIN TYP

(1)

4

C i(CLK)


C

O(CLK)


V

CC

T

A

= 0, V

SS

= 0, f = 1 MHz,


20

C

I

C

O

Input impedance

Output impedance

6

10


CC

= 3.3 V and T

A

= 25°C.


MAX UNIT

V

0.4

V

10 ＝A

＝20 ＝A

20

30

10

20 mA pF pF pF pF

TIMING REQUIREMENTS


PARAMETER t cW t w6 t w7 t w8 t w1 t w2 t cR t t t t t t t t t t

SU3 h4 h5 h7 d5 d8 d10 d11 d12 d13

Pulse duration, RESET

Pulse duration, clock high

Pulse duration, clock low

Cycle time, read (t w7

+ t d8

+ t h7

)

Cycle time, write (t w6

+ t d5

+ t h4

)

Pulse duration, IOW or CS

Pulse duration, IOR or CS

Setup time, data valid before IOW ↑ or CS ↑

Hold time, address valid after IOW ↑ or CS ↑

Hold time, data valid after IOW ↑ or

CS ↑

Hold time, data valid after IOR ↑ or

CS ↑

Delay time, address valid before

IOW ↓ or CS↓

Delay time, address valid to IOR ↓ or

CS ↓

Delay time, IOR ↓ or CS↓ to data valid

Delay time, IOR ↑ or CS↑ to floating data

Write cycle to write cycle delay

Read cycle to read cycle delay

ALT.

SYMBOL t

RESET t

XH t

XL

RC

WC t

IOW t

IOR t

DS t

WA t

DH t

RA t

AW t

AR t

RVD t

HZ

FIGURE

6

8

7

7

8

7

7

7

8

7

8

8

8

7

8

TEST

CONDITIONS

C

L

= 30 pF

C

L

= 30 pF

1.8 V

MIN MAX

1

25

115

115

80

80

25

20

15

20

15

15

55

40

100

100

LIMITS

2.5 V

MIN MAX MIN

3.3 V

MAX

1 1

16

80

80

55

55

20

15

10

15

10

10

35

30

75

75

12

62

62

45

45

15

10

5

10

7

7

25

20

60

60

57

57

40

40

15

5 V

MIN MAX

1

UNIT

＝s

8 ns ns ns ns ns ns

10

5

10

7

7

20

20

50

50 ns ns ns ns ns ns ns ns ns





................................................................................................................................................


BAUD GENERATOR SWITCHING CHARACTERISTICS

over recommended ranges of supply voltage and operating free-air temperature, C

L

= 30 pF (for FN package only) t w3 t w4 t d1 t d2

PARAMETER

Pulse duration, BAUDOUT low

Pulse duration, BAUDOUT high

Delay time, XIN ↑ to BAUDOUT↑

Delay time, XIN ↑↓ to BAUDOUT↓

ALT.

SYMBOL t

LW t

HW t

BLD t

BHD

FIGURE

6

6

6

6

TEST

CONDITION

S

CLK ÷ 2

CLK ÷ 2

1.8 V

MIN MAX

50

50

35

35

LIMITS

2.5 V

MIN MAX

3.3 V

MIN MAX

35

35

27

27

25

25

20

20

MIN

5 V

MAX

16

16

15

15

UNIT ns ns ns ns

RECEIVER SWITCHING CHARACTERISTICS

(1) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) t d12

PARAMETER

ALT.

SYMBOL t

SCD

FIGURE

9

TEST

CONDITIONS

1.8 V

MIN MAX

20

LIMITS

2.5 V

MIN MAX

15

3.3 V 5 V

MIN MAX MIN MAX

10 10 t d13 t d14 t d26 t d27 t d28 t d29

Delay time, RCLK to sample

Delay time, stop to set INT or read RBR to LSI interrupt or stop to RXRDY ↓

Delay time, read RBR/LSR to reset INT

Delay time, RCV threshold byte to RTS ↑

Delay time, read of last byte in receive FIFO to RTS ↓

Delay time, first data bit of 16th character to RTS ↑

Delay time, RBRRD low to RTS ↓ t

SINT t

RINT

8, 9, 10,

11, 12

8, 9, 10,

11, 12

19

19

20

20

C

L

= 30 pF

C

L

= 30 pF

C

L

= 30 pF

C

L

= 30 pF

C

L

= 30 pF

1

100

1

90

1

80

1

70

UNIT ns

RCLK cycle ns

2

2

2

2 baudout cycles

(2) baudout cycles baudout cycles baudout cycles

(1) In the FIFO mode, the read cycle (RC) = 1 baud clock (min) between reads of the receive FIFO and the status registers (interrupt identification register or line status register).

(2) A baudout cycle is equal to the period of the input clock divided by the programmed divider in DLL, DLM.

TRANSMITTER SWITCHING CHARACTERISTICS

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) t d15 t d16

PARAMETER

Delay time, initial write to transmit start

Delay time, start to INT

ALT.

SYMBOL t

IRS t

STI

FIGURE

14

14

TEST

CONDITIONS

2.5 V

LIMITS

1.8 V

MIN MAX MIN MAX

3.3 V 5 V

MIN MAX MIN MAX

8

8

24

10

8

8

24

10

8

8

24

10

8

8

UNIT

24

10 baudout cycles baudout cycles t d17 t d18 t d19 t d20

Delay time, IOW (WR THR) to reset INT

Delay time, initial write to INT

(THRE

(1)

)

Delay time, read IOR ↑ to reset INT

(THRE

(1)

)

Delay time, write to TXRDY inactive t

HR t

SI t

IR t

WXI

14

14

14

15, 16

C

L

= 30 pF

C

L

= 30 pF

C

L

= 30 pF

16

70

34

70

60

16

60

34

50

45

16

50

34

35

35

16

50

34 baudout cycles

35

35 ns ns ns t d21

Delay time, start to TXRDY active t

SXA

15, 16 C

L

= 30 pF 9 9 9 9 baudout cycles t

SU4

Setup time, CTS ↑ before midpoint of stop bit

18 30 20 10 10 ns t d25

Delay time, CTS low to TX ↓ 18 C

L

= 30 pF 24 24 24 24 baudout cycles

(1) THRE = Transmitter holding register empty; IIR = interrupt identification register

Copyright © 2006–2008, Texas Instruments Incorporated Submit Documentation Feedback 11


TL16C2752


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MODEM CONTROL SWITCHING CHARACTERISTICS

over operating free-air temperature range (unless otherwise noted)

PARAMETER t t d22 d23 t d24

Delay time, WR MCR to output

Delay time, modem interrupt to set INT

Delay time, RD MSR to reset

INT

ALT.

SYMBOL

FIGURE t

MDO t

SIM t

RIM

17

17

17

TEST

CONDITIONS

C

L

= 30 pF

C

L

= 30 pF

C

L

= 30 pF

1.8 V

MIN MAX

90

60

LIMITS

2.5 V

MIN MAX MIN

3.3 V

MAX

70 60

50 40

80 60 50

MIN

5 V

MAX

50

35

UNIT ns ns

40 ns

N

XTAL t w1 t w2 t d2 t d1

MFA,B

(1/1) t d1 t d2

MFA,B

(1/2) t w3 t w4

MFA,B

(1/3)

MFA,B

(1/N)

(N > 3)

2 XIN Cycles

(N −2) XIN Cycles

Figure 5. Input Clock and Baud Generator Timing Waveforms

(for FN Package Only) (When AFR2:1 = 01)





................................................................................................................................................


CHSEL,

A2 −A0 t d5

Valid Address t h4 t d5

Valid Address t w6 t h4

CS t w6 t w6 t d12 t w6

IOW

D7 −D0

CHSEL,

A2 −A0

CS t d8 t su3 t h5

Valid Data

Figure 6. Write Cycle Timing Waveforms t su3

Valid Data

Valid Address t h7 t d8

Valid Address t w7 t w7 t w7 t d13 t w7 t h5 t h7

IOR

D7 −D0 t d10 t d10 t d11

Valid Data

Figure 7. Read Cycle Timing Waveforms

Valid Data t h11




TL16C2752


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RCLK

(Internal)

Sample Clock

(Internal)

TL16C450 Mode:

RXA, RXB Start

Sample Clock

INT

(data ready)

8 CLKs

Data Bits 5− 8 Parity Stop t d12

50% 50% t d13

50% t d14

50%

INT

(RCV error)

IOR

(read RBR)

50%

Active

IOR

(read LSR)

50% Active t d14

Figure 8. Receiver Timing Waveforms





................................................................................................................................................


RXA, RXB

Sample Clock

(Internal)

Trigger Level

INT

(FCR6, 7 = 0, 0)

INT

Line Status

Interrupt (LSI)

IOR

(RD LSR)

IOR

(RD RBR)

Data Bits 5 −8

Stop

50% 50% t d13

(see Note A) t d14

50% 50% t d14

Active

50%

50%

Active

Figure 9. Receive FIFO First Byte (Sets DR Bit) Waveforms

(FIFO at or above trigger level)

(FIFO below trigger level)

RXA, RXB

Sample Clock

(Internal)

Time-Out or

Trigger Level

Interrupt

Line Status

Interrupt (LSI)

Stop

50% t d13

(see Note A) t d13

50% Top Byte of FIFO t d14

50% t d14

50%

50%

(FIFO at or above trigger level)

(FIFO below trigger level)

IOP

(RD LSR)

IOR

(RD RBR)

Active 50% 50% Active

Previous Byte

Read From FIFO

Figure 10. Receive FIFO Bytes Other Than the First Byte (DR Internal Bit Already Set) Waveforms




TL16C2752


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IOR

(RD RBR)

RXA, RXB

(first byte) Stop

50% Active

See Note A

Sample Clock

(Internal) t d13

(see Note B)

RXRDYA, RXRDYB

50% t d14

50%

Figure 11. Receiver Ready (RXRDY) Waveforms, FCR0 = 0 or FCR0 = 1 and FCR3 = 0 (Mode 0)

IOR

(RD RBR)

RXA, RXB

(first byte that reaches the trigger level)

Sample Clock

(Internal) t d13

(see Note B)

50%

Active

See Note A t d14

RXRDYA, RXRDYB

50% 50%

Figure 12. Receiver Ready (RXRDY) Waveforms, FCR0 = 1 and FCR3 = 1 (Mode 1)

Start

50% Data Bits Parity

Start

50% TXA, TXB

INT

(THRE)

50% t d15

50% 50%

Stop t d16

50% 50% t d18 t d17 t d17

IOW

(WR THR)

50% 50% 50%

IOR t d19

50%

Figure 13. Transmitter Timing Waveforms





................................................................................................................................................


IOW

(WR THR)

Byte 1

50%

TXA, TXB Data Parity

Stop

Start

50% t d20 t d21

TXRDYA, TXRDYB

50% 50%

Figure 14. Transmitter Ready (TXRDY) Waveforms, FCR0 = 0 or FCR0 = 1 and FCR3 = 0 (Mode 0)

IOW

(WR THR)

Byte 16

50%

TXA, TXB Data Parity

Stop

Start

50% t d20 t d21

TXRDYA, TXRDYB

50%

FIFO Full

50%

Figure 15. Transmitter Ready (TXRDY) Waveforms, FCR0 = 1 and FCR3 = 1 (Mode 1)

IOW

(WR MCR)

50% 50% t d22 t d22

RTSA, RTSB, DTRA,

DTRB, OPA, OPB

50% 50%

50%

CTSA, CTSB, DSRA,

DSRB, CDA, CDB

INT

(modem)

IOR

(RD MSR) t d23

50% t d24

50%

50%

50% t d23

RI

Figure 16. Modem Control Timing Waveforms

50%




TL16C2752


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CTSA, CTSB

TXA, TXB t su4

50% 50% t d25

50%

Midpoint of Stop Bit

Figure 17. CTS and TX Autoflow Control Timing (Start and Stop) Waveforms

Midpoint of Stop Bit

RXA, RXB t d26

50% t d27

50% RTSA,

RTSB

IOR

50%

Figure 18. Auto-RTS Timing





................................................................................................................................................


APPLICATION INFORMATION

A.

Pin numbers shown are for 44-pin PLCC FN package.

Figure 19. Typical TL16C2752 Connection




TL16C2752


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PRINCIPLES OF OPERATION

0 0 0

0 0 0

0 0 1

0 1 0

0 0 0

0 0 1

0 0 1

0 1 0

0 1 1

1 0 0

1 0 1

UART Internal Registers

Each of the UART channel in the TL16C2752 has its own set of configuration registers selected by address lines

A0, A1, and A2 with CS and CHSEL selecting the channel. The complete register set is shown in

Table 1

and

Table 2

.

Table 1. UART Channel A and B UART Internal Registers

ADDRESS

A2–A0

RESET

(HEX)

VALUE

COMMENTS REGISTER READ/WRITE

1 1 0

1 1 1

1 1 1

1 1 1

0 0 0

0 0 1

0 1 0

1 0 0

1 0 1

1 1 0

1 1 1

00

0A

00

01

00

00

00

XX

XX

XX

XX

00

60

X0

FF

00

80

00

00

00

00

00

00

00

00

LCR[7] = 0

LCR[7] = 1, LCR ≠ 0xBF

DLL, DLM = 0x00,

LCR[7] = 1, LCR ≠ 0xBF

LCR[7] = 0

LCR[7] = 0

16C550 Compatible Registers

RHR–Receive Holding Register

THR–Transmit Holding Register

DLL–Div Latch Low Byte

DLM–Div Latch High Byte

AFR–Alternate Function Register

DREV–Device Revision Code

DVID–Device Identification Code

IER–Interrupt Enable Register

ISR–Interrupt Status Register

FCR–FIFO Control Register

LCR

LCR

LCR

≠ 0xBF

≠ 0xBF, FCTR[6] = 0

≠ 0xBF, FCTR[6] = 1

LCR = 0xBF

LCR–Line Control Register

MCR–Modem Control Register

LSR–Line Status Register

Reserved

MSR–Modem Status Register

Reserved

SPR–Scratch Pad Register

FLVL–RX/TX FIFO Level Counter Register

EMSR–Enhanced Mode Select Register

Enhanced Registers

TRG–RX/TX FIFO Trigger Level Register

FC–RX/TX FIFO Level Counter Register

FCTR–Feature Control Register

EFR–Enhanced Function Register

Xon-1–Xon Character 1

Xon-2–Xon Character 2

Xoff-1–Xoff Character 1

Xoff-2–Xoff Character 2

Read only

Write only

Read/Write

Read/Write

Read/Write

Read only

Read only

Read/Write

Read only

Write only

Read/Write

Read/Write

Read only

Write only

Read only

Write only

Read/Write

Read only

Write only

Write only

Read only

Read/Write

Read/Write

Read/Write

Read/Write

Read/Write

Read/Write





................................................................................................................................................


Address

A2–A0

0 0 0

0 0 0

0 0 1

0 1 0

0 1 0

0 1 1

1 0 0

1 0 1

1 1 0

1 1 1

1 1 1

1 1 1

0 0 0

0 0 1

0 1 0

0 0 0

0 0 1

0 0 0

0 0 0

0 0 1

0 1 0

1 0 0

1 0 1

1 1 0

1 1 1

Register

Name

RHR

THR

IER

ISR

FCR

LCR

MCR

LSR

MSR

SPR

EMSR

FLVL

DLL

DLM

AFR

DREV

DVID

TRG

FC

FCTR

EFR

XON1

XON2

XOFF1

XOFF2

Table 2. Internal Registers Description

(1)

Read/

Write

SCPAD Swap

Trig Table Bit

1

Bit 0

RD

WR

RD/WR

RD

WR

RD/WR

RD/WR

RD

RD

RD/WR

WR

RD

RD/WR

LCR[7] = 0

LCR ≠ 0xBF

LCR ≠ 0xBF

FCTR Bit 6 = 0

Bit 7

Bit 7

0/

CTS Int.

Enable

FIFOs

Enabled

RXFIFO

Trigger

Divisor

Enable

0/

BRG

Prescaler

RX FIFO

Global Error

CD# Input

Bit 7

16C550 Compatible Registers

Bit 6 Bit 5 Bit 4

Bit 6

0/

RTS Int.

Enable

Bit 5

0/

Xoff Int.

Enable

Bit 4

0/

Sleep Mode

Enable

FIFOs

Enabled

RXFIFO

Trigger

0/ 0/

INT Source Bit INT Source

5 Bit 4

0/

TXFIFO

Trigger

0/

TXFIFO

Trigger

Bit 3

Bit 3

Modem Stat.

Int. Enable

DMA Mode

Enable

Bit 2

Bit 2

RX Line Stat.

Int. Enable

TX FIFO

Reset

Bit 1

Bit 1

TX Empty Int.

Enable

RX FIFO

Reset

Bit 0

Bit 0

RX Data Int.

Enable

INT Source Bit INT Source Bit INT Source Bit INT Source Bit

3 2 1 0

FIFOs Enable

Set TX Break Set Parity Even Parity Parity Enable Stop Bits

Word Length

Bit 1

Word Length

Bit 0

0/

IR Mode

Enable

THR & TSR

Empty

RI# Input

Bit 6

0/

XonAny

THR Empty

DSR# Input

Bit 5

Internal

Loopback

Enable

RX Break

CTS# Input

Bit 4

OP2# Output

Control

RX Framing

Error

Delta CD#

Bit 3

Rsrvd (OP1#)

RX Parity

Error

Delta RI#

Bit 2

RTS# Output

Control

RX Overrun

Error

Delta DSR#

Bit 1

DTR# Output

Control

RX Data

Ready

Delta CTS#

Bit 0

LDR ≠ 0xBF

FCTR Bit 6 = 1

RD/WR LCR[7] = 1 LCR

≠ 0xBF

RD/WR

RD

RD

LCR[7] = 1 LCR

≠ 0xBF DLL =

0x00 DLM =

0x00

16X

Sampling

Rate Mode

Bit 7

Bit 7

Bit 7

Rsvd

Bit 7

0

LSR Error

Interrupt

Imd/Dly#

Bit 6

Auto RTS

Hyst. Bit 3

Bit 5

Auto RTS

Hyst Bit 2

Baud-Rate Generator Divisor

Bit 4

Bit 6

Bit 6

Bit 5

Bit 5

Bit 4

Bit 4

Rsvd

Bit 6

0

Rsvd

Bit 5

0

Rsvd

Bit 4

0

Auto RS485

Output

Inversion

Bit 3

Bit 3

Bit 3

Rsvd

Bit 3

1

Rsrvd

Bit 2

Bit 2

Bit 2

RXRDY#

Select

Bit 2

0

Rx/Tx FIFO

Count

Bit 1

Bit 1

Bit 1

Baudout#

Select

Bit 1

1

Rx/Tx FIFo

Count

Bit 0

Bit 0

Bit 0

Concurrent

Write

Bit 0

0

WR

RD

RD/WR

Comments Bit 7

Bit 7

Bit 7

RX/TX

Mode

Bit 6 Bit 5

Bit 6

Enhanced Registers

Bit 5

Bit 6 Bit 5

Bit 4

Bit 4

Bit 4

Trig Table

Bit 0

Bit 3

Bit 3

Bit 3

Auto RS485

Direction

Control

Bit 2

Bit 2

Bit 2

RX IR Input

Inv.

Bit 1

Bit 1

Bit 1

Auto RTS

Hyst Bit 1

Bit 0

Bit 0

Auto RTS

Hyst Bit 0

RD/WR

RD/WR

RD/WR

RD/WR

RD/WR

LCR = 0xBF

Auto CTS

Enable

Bit 7

Bit 7

Bit 7

Bit 7

Auto RTS

Enable

Bit 6

Bit 6

Bit 6

Bit 6

Special Char

Select

Bit 5

Bit 5

Bit 5

Bit 5

Enable

IER[7:4],

ISR[5:4],

FCT[5:4],

MCR[7:5]

Bit 4

Bit 4

Bit 4

Bit 4

Software Flow

Cntl Bit 3

Bit 3

Bit 3

Bit 3

Bit 3

Software Flow

Cntl Bit 2

Bit 2

Bit 2

Bit 2

Bit 2

Software Flow

Cntl Bit 1

Bit 1

Bit 1

Bit 1

Bit 1

Software Flow

Cntl Bit 0

Bit 0

Bit 0

Bit 0

Bit 0

(1) Shaded bits are accessible when EFR Bit 4 = 1.




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PACKAGE OPTION ADDENDUM

20-Mar-2008

PACKAGING INFORMATION

Orderable Device

TL16C2752FN

TL16C2752FNG4

TL16C2752FNR

TL16C2752FNRG4

TL16C2752IFN

TL16C2752IFNG4

TL16C2752IFNR

TL16C2752IFNRG4

Status

(1)

ACTIVE

ACTIVE

ACTIVE

ACTIVE

ACTIVE

ACTIVE

ACTIVE

ACTIVE

Package

Type

PLCC

PLCC

PLCC

PLCC

PLCC

PLCC

PLCC

PLCC

Package

Drawing

FN

FN

FN

FN

FN

FN

FN

FN

Eco Plan

(2)

Pins Package

Qty

44 26 Green (RoHS & no Sb/Br)

Lead/Ball Finish MSL Peak Temp

(3)

CU NIPDAU Level-3-260C-168 HR

44 CU NIPDAU Level-3-260C-168 HR

44

26 Green (RoHS & no Sb/Br)


CU NIPDAU Level-3-260C-168 HR

44 CU NIPDAU Level-3-260C-168 HR

44

44

44

44






CU NIPDAU

CU NIPDAU

CU NIPDAU

CU NIPDAU

Level-3-260C-168 HR

Level-3-260C-168 HR

Level-3-260C-168 HR

Level-3-260C-168 HR

(1)

The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2)

Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

(3)

MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 1

MECHANICAL DATA

MPLC004A – OCTOBER 1994

PLASTIC J-LEADED CHIP CARRIER FN (S-PQCC-J**)

20 PIN SHOWN

3

D

D1

1 19

Seating Plane

0.004 (0,10)

0.180 (4,57) MAX

0.120 (3,05)

0.090 (2,29)

0.020 (0,51) MIN

0.032 (0,81)

0.026 (0,66)

4 18

D2 / E2

E E1

D2 / E2

8 14

9 13

0.050 (1,27)

0.008 (0,20) NOM

0.021 (0,53)

0.013 (0,33)

0.007 (0,18) M

NO. OF

PINS

**

52

68

84

20

28

44

D / E D1 / E1 D2 / E2

MIN MAX MIN MAX MIN MAX

0.385 (9,78)

0.485 (12,32)

0.395 (10,03)

0.495 (12,57)

0.350 (8,89)

0.450 (11,43)

0.356 (9,04)

0.456 (11,58)

0.685 (17,40)

0.785 (19,94)

0.695 (17,65)

0.795 (20,19)

0.650 (16,51)

0.750 (19,05)

0.656 (16,66)

0.756 (19,20)

0.985 (25,02)

1.185 (30,10)

0.995 (25,27)

1.195 (30,35)

0.950 (24,13)

1.150 (29,21)

0.958 (24,33)

1.158 (29,41)

0.141 (3,58)

0.191 (4,85)

0.291 (7,39)

0.341 (8,66)

0.441 (11,20)

0.541 (13,74)

0.169 (4,29)

0.219 (5,56)

0.319 (8,10)

0.369 (9,37)

0.469 (11,91)

0.569 (14,45)

4040005 / B 03/95

NOTES: A. All linear dimensions are in inches (millimeters).

B. This drawing is subject to change without notice.

C. Falls within JEDEC MS-018

POST OFFICE BOX 655303

•

DALLAS, TEXAS 75265

1

IMPORTANT NOTICE

Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment.

TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where mandated by government requirements, testing of all parameters of each product is not necessarily performed.

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TL16C2752

1.8-V to 5-V DUAL UART WITH 64-BYTE FIFOS

FEATURES

APPLICATIONS

DESCRIPTION

TL16C2752 Block Diagram

Detailed Description

Auto-RTS

Auto-CTS

Auto-RTS and Auto-CTS Functional Timing

ABSOLUTE MAXIMUM RATINGS

RECOMMENDED OPERATING CONDITIONS

1.8 V

RECOMMENDED OPERATING CONDITIONS

2.5 V

RECOMMENDED OPERATING CONDITIONS

3.3 V

RECOMMENDED OPERATING CONDITIONS

5 V

ELECTRICAL CHARACTERISTICS

1.8 V Nominal

ELECTRICAL CHARACTERISTICS

2.5 V Nominal

ELECTRICAL CHARACTERISTICS

3.3 V Nominal

ELECTRICAL CHARACTERISTICS

5 V Nominal

TIMING REQUIREMENTS

BAUD GENERATOR SWITCHING CHARACTERISTICS

RECEIVER SWITCHING CHARACTERISTICS

TRANSMITTER SWITCHING CHARACTERISTICS

MODEM CONTROL SWITCHING CHARACTERISTICS

APPLICATION INFORMATION

PRINCIPLES OF OPERATION

UART Internal Registers

PACKAGE OPTION ADDENDUM

PACKAGING INFORMATION

MECHANICAL DATA

Related manuals

Table of contents

TL16C2752

1.8-V to 5-V DUAL UART WITH 64-BYTE FIFOS

FEATURES

APPLICATIONS

DESCRIPTION

TL16C2752 Block Diagram

Detailed Description

Auto-RTS

Auto-CTS

Auto-RTS and Auto-CTS Functional Timing

ABSOLUTE MAXIMUM RATINGS

RECOMMENDED OPERATING CONDITIONS

1.8 V

RECOMMENDED OPERATING CONDITIONS

2.5 V

RECOMMENDED OPERATING CONDITIONS

3.3 V

RECOMMENDED OPERATING CONDITIONS

5 V

ELECTRICAL CHARACTERISTICS

1.8 V Nominal

ELECTRICAL CHARACTERISTICS

2.5 V Nominal

ELECTRICAL CHARACTERISTICS

3.3 V Nominal

ELECTRICAL CHARACTERISTICS

5 V Nominal

TIMING REQUIREMENTS

BAUD GENERATOR SWITCHING CHARACTERISTICS

RECEIVER SWITCHING CHARACTERISTICS

TRANSMITTER SWITCHING CHARACTERISTICS

MODEM CONTROL SWITCHING CHARACTERISTICS

APPLICATION INFORMATION

PRINCIPLES OF OPERATION

UART Internal Registers

PACKAGE OPTION ADDENDUM

PACKAGING INFORMATION

MECHANICAL DATA

Related manuals

Texas Instruments

TMS320DM643X DMP

Table of contents