TL16PC564B

SLLS225B – MARCH 1996 – REVISED FEBRUARY 2003
D Integrated Asynchronous Communications
D
D
D
D
D
D
Element (ACE) Compatible With PCMCIA
PC Card Standard Release 2.01
Consists of a Single TL16C550 ACE Plus
PCMCIA Interface Logic
Provides Common I-Bus/Z-Bus
Microcontroller Inputs for Most Intel and
Zilog Subsystems
Fully Programmable 256-Byte Card
Information Structure (CIS) and 8-Byte Card
Configuration Register (CCR)
Adds or Deletes Standard Asynchronous
Communication Bits (Start, Stop and
Parity) to or From Serial Data Stream
Independently Controlled Transmit,
Receive, Line Status, and Data Set
Interrupts
Subsystem Selectable Serial-Bypass Mode
Provides Subsystem With Direct Parallel
Access to the FIFOs
D Fully Programmable Serial-Interface
D
D
D
D
D
D
Characteristics:
– 5-, 6-, 7-, or 8-Bit Characters
– Even-, Odd-, or No-Parity Bit Generation
and Detection
– 1-, 1 1/2-, or 2-Stop Bit Generation
– Baud-Rate Generation
Fully Prioritized Interrupt System Controls
Modem Control Functions
Provides TL16C450 Mode at Reset Plus
Selectable Normal TL16C550 Operation or
Extended 64-Byte FIFO Mode
Selectable Auto-RTS Mode Deactivates
RTS at 14 Bytes in 550 Mode and at
56 Bytes in Extended 550 Mode
Selectable Auto-CTS Mode Deactivates
Serial Transfers When CTS is Inactive
Available in 100 Pin Thin Quad Flatpack
(PZ) Package or 100-Ball (GGM) MicroStar
BGA Package
description
The TL16PC564B/BLV is designed to provide all the functions necessary for a Personal Computer Memory
Card International Association (PCMCIA) universal asynchronous receiver transmitter (UART) subsystem
interface. This interface provides a serial-to-parallel conversion for data to and from a modem
coder-decoder/digital signal processor (CODEC/DSP) function to a PCMCIA parallel data-port format. A
computer central processing unit (CPU), through a PCMCIA host controller, can read the status of the
asynchronous communications element (ACE) interface at any point in the operation. Reported status
information includes the type of transfer operation in process, the status of the operation, and any error
conditions encountered.
Attribute memory consists of a 256-byte card information structure (CIS) and eight 8-byte card configuration
registers (CCR). The CIS, implemented with a dual-port random-access memory (DPRAM), is available to both
the host CPU and subsystem (modem), as are the CCRs. This DPRAM is used in place of the electrically
erasable programmable read-only memory (EEPROM) normally used for the CIS. At power up, attribute
memory is initialized by the subsystem.
The TL16PC564B/BLV uses a TL16C550 ACE-type core with an expanded 64 × 11 receiver first-in-first-out
(FIFO) memory and a 64 × 8 transmitter FIFO memory. The receiver trigger logic flags have been adjusted in
order to take full advantage of the increased capacity when in the extended mode. In addition, eight of the UART
registers have been mapped into the subsystem (modem) memory space as read-only registers. This allows
the subsystem to read UART status information.
A subsystem-selectable serial-bypass mode has been implemented to allow the subsystem to bypass the serial
portion of the UART and write directly to the receiver FIFO and read directly from the transmitter FIFO. Interrupt
operation is not affected in this mode.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Intel is a registered trademark of Intel System, Inc.
Zilog is a registered trademark of Zilog Incorporated
MicroStar BGA is a trademark of Texas Instruments Incorporated.
Copyright  1996 – 2003, Texas Instruments Incorporated
! "#$ ! %#&'" ( $)
(#" ! " !%$"" ! %$ *$ $! $+! ! #$ !
! (( , -) (#" %"$!!. ($! $"$!!'- "'#($
$! . '' %$ $!)
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1
SLLS225B – MARCH 1996 – REVISED FEBRUARY 2003
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
HD3
HD4
HD5
VCC
HD6
HD7
CE1
OE
HA9
GND
HA8
WE
IREQ
HA7
VCC
HA6
HA5
HA4
HA3
HA2
GND
HA1
HA0
HD0
HD1
PZ PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
HD2
STSCHG
REG
VCC
INPACK
TESTOUT
GND
GND
RESET
GND
SA7
IOWR
IORD
CE2
SA6
VCC
SA5
SA4
SA3
SA2
SA1
GND
SA0
VCC
UARTCLK
ALE (AS)†
IRQ
SELZ/I
RD(DS)†
GND
WR(R/W)†
CS
SIN
DTR
RTS
VCC
OUT1
BAUDOUT
GND
RCLK
GND
XIN
GND
OUT2
SOUT
DSR
VCC
DCD
CTS
RI
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
EXTEND
VTEST
SSAB
GND
ARBCLKI
GND
ARBCLKO
ARBPGM0
ARBPGM1
VCC
RST
NANDOUT
GND
SAD7
SAD6
GND
SAD5
SAD4
SAD3
SAD2
VCC
VCC
SAD1
SA8
SAD0
† The terminal names not enclosed in parentheses correspond to an Intel microcontroller signal, and the terminal
names enclosed in parentheses correspond to a Zilog microcontroller signal.
2
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SLLS225B – MARCH 1996 – REVISED FEBRUARY 2003
VCC
SA4
DCD
OUT2
DSR
GND
GND
RCLK
GND
DTR
IORD
XIN
CS
VCC
BAUDOUT
GND
SAD5
WR (R/W)†
SAD1
SELZ/I
IRQ
SAD0
SA8
ALE (AS)†
GGM PACKAGE
(BOTTOM VIEW)
K
RI
CTS
SOUT
RTS
J
VCC
UARTCLK
SA0
SIN
RD (DS)†
IOWR
INPACK
HA7
GND
D
TESTOUT
VCC
C
HA4
HD1
B
STSCHG
A
2
VCC
GND
1
3
4
5
6
7
8
9
10
REG
VCC
HD2
HD3
E
HA0
GND
HD0
VTEST
HD5
HD4
SA5
VCC
SA7
HA2
HA1
GND
ARBCLK1
HD6
EXTEND
F
RESET
GND
HA3
ARBCLK0
OE
GND
SA3
CE2
SA6
IREQ
HA6
HA5
ARBPGM1
GND
HA9
G
NANDOUT
HA8
WE
SAD7
SAD6
GND
SA1
GND
SA2
VCC
RST
HD7
CE1
SAD3
OUT1
SAD4
H
ARBPGM0
SSAB
GND
VCC
VCC
SAD2
† The terminal names not enclosed in parentheses correspond to an Intel microcontroller signal, and the terminal
names enclosed in parentheses correspond to a Zilog microcontroller signal.
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3
SLLS225B – MARCH 1996 – REVISED FEBRUARY 2003
block diagram
HD7–HD0†
HA9–HA0†
REG
CE1
CE2
WE
OE
IORD
95, 96, 98–100, 75–77
8
DATA
ADDR
10
92, 90, 87, 85–81,
79, 78
10
73
94
62
OE
WE
Reset
Host CPU
Control
Logic
89
93
63
Attribute
Memory
(CIS 256 × 8,
CCR 8 × 8
plus arbitration
logic)
10
Reset
8
Control
ARBCLKI
ARBPGM1–
ARBPGM0†
SAD7–SAD0†
SA8–SA0
SELZ/I
SSAB
ALE(AS)
WR(R/W)
RD(DS)
CS
5
9,8
2
8
DATA
14, 15, 17–20,
23, 25
8
24,65,61,
59–55,53
28
3
26
9
9
ADDR
OE
WE
Subsystem
Control
Logic
31
29
32
71
74
27
88
51
11
Reset
RESET
IOWR
EXTEND
CTS
DCD
DSR
RI
6
UART Select
42
Master Clock
33
40
Reset
49
48
46
50
† Bit 0 is the least significant bit.
4
INPACK
STSCHG
IRQ
IREQ
UARTCLK
RST
UART
TL16C550C
64
1
Reset
SIN
RCLK
ARBCLKO
Reset
Validation
67
Divide by N
XIN
7
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38
34
37
44
35
45
BAUDOUT
DTR
OUT1
OUT2
RTS
SOUT
SLLS225B – MARCH 1996 – REVISED FEBRUARY 2003
Terminal Functions
TERMINAL
PZ NO.
GGM NO.
INTERFACE†
I/O
DESCRIPTION
ALE (AS)
26
J2
S
I
Address-latch enable/address strobe. ALE(AS) is an address-latch enable
in the Intel mode and an address strobe in the Zilog mode. ALE (AS) is
active high for an Intel subsystem and active low for a Zilog subsystem.
ARBCLKO
7
D1
M
O
Arbitration clock output. ARBCLKO is equal to the input on ARBCLKI
divided by the binary-coded divisor input on ARBPGM (1–0).
ARBCLKI
5
C1
M
I
Arbitration clock input. ARBCLKI is the base clock used in arbitration for
the attribute memory DRAM and the reset validation circuitry.
ARBPGM0
ARBPGM1
8
9
D3
E1
M
I
Arbitration clock divisor program. These two bits set the divisor for
ARBCLKI. Divide by 1, 2, 4, and 8 are available.
BAUDOUT
38
F5
U
O
Baud output. BAUDOUT is an active-low 16× signal for the transmitter
section of the UART. The clock rate is established by the reference clock
(UARTCLK) frequency divided by a divisor specified by the baud generator
divisor latches. BAUDOUT may also be used for the receiver section by
tying this output to the RCLK input.
CE1
CE2
94
62
A4
F7
H
I
Card enable 1 and card enable 2 are active-low signals. CE1 enables
even-numbered address bytes, and CE2 enables odd-numbered address
bytes. A multiplexing scheme based on HA0, CE1, and CE2 allows an 8-bit
host to access all data on HD0 through HD7 if desired. These signals have
internal pullup resistors.
CS
32
K4
S
I
Chip select. CS is the active-low chip select from the Zilog or Intel
microcontroller.
CTS
49
K9
U
I
Clear to send. CTS is an active-low modem status signal whose condition
can be checked by reading bit 4 (CTS) of the modem status register (MSR).
Bit 0 (delta clear to send) of the MSR indicates that the signal has changed
states since the last read from the MSR. If the modem-status interrupt is
enabled when CTS changes states, an interrupt is generated.
DCD
48
J8
U
I
Data carrier detect. DCD is an active-low modem-status signal whose
condition can be checked by reading bit 7 (DCD) of the MSR. Bit 3 (delta
data carrier detect) of the MSR indicates that the signal has changed states
since the last read from the MSR. If the modem-status interrupt is enabled
when DCD changes states, an interrupt is generated.
DSR
46
H7
U
I
Data set ready. DSR is an active-low modem status signal whose condition
can be checked by reading bit 5 (DSR) of the MSR. Bit 1 (delta data set
ready) of the MSR indicates that the signal has changed states since the
last read from the MSR. If the modem-status interrupt is enabled when
DSR changes states, an interrupt is generated.
DTR
34
K5
U
O
Data terminal ready. DSD is an active-low signal. When active, DTR
informs the modem or data set that the UART is ready to establish
communication. DTR is placed in the active state by setting the DTR bit 0
of the modem control register (MCR) to a high level. DTR is placed in the
inactive state either as a result of a reset, doing a loop-mode operation, or
resetting bit 0 (DTR) of the MCR.
EXTEND
1
B2
U
I
FIFO extend. When EXTEND is high, the UART is configured as a
standard TL16C550 with 16-byte transmit and receive FIFOs. When
EXTEND is low and FIFO control register (FCR) bit 5 is high, the FIFOs are
extended to 64 bytes and the receiver-interrupt trigger levels adjust
accordingly. EXTEND low in conjunction with FIFO control register (FCR)
bit 4 set high enables the auto-RTS function.
4,6,13,16,30,
39,41,43,54,
66,68,69,80,91
C3,D2,E5,F3,
K3,K6,H6,G7,
H8,E8,D7,D10
A8,C5
M
NAME
GND
Common ground
† Host = H, Subsystem = S, UART = U, Miscellaneous = M
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SLLS225B – MARCH 1996 – REVISED FEBRUARY 2003
Terminal Functions
TERMINAL
INTERFACE†
I/O
DESCRIPTION
B8
C8
B7
A7
C7
A6
B6
D6
B5
D5
H
I
The 10-bit address bus addresses the attribute memory (bits 1–8) and addresses the
internal UART as either PCMCIA I/O (bits 0–2) or as a standard COM port (bits 0–9).
77
76
75
100
99
98
96
95
A9
B9
A10
A1
A2
B3
C4
B4
H
I/O
The 8-bit bidirectional data bus transfers data to and from the attribute memory and
the internal UART.
INPACK
71
D8
H
O
Input port acknowledge. INPACK is an active-low output signal that is asserted when
the card responds to an I/O read cycle at the address on the HA bus.
IORD
63
F6
H
I
I/O read strobe. IORD is an active-low input signal activated to read data from the card
I/O space. The REG signal and at least one of the card enable inputs (CE1, CE2) must
also be active for the I/O transfer to take place. This signal has an internal pullup
resistor.
IOWR
64
E10
H
I
I/O write strobe. IORW is an active-low input signal activated to write data to the card
I/O space. The REG signal and at least one of the card enable inputs (CE1, CE2) must
also be active for the I/O transfer to take place. This signal has an internal pullup
resistor.
IREQ
88
E6
H
O
Interrupt request. IREQ is an active-low output signal asserted by the card to indicate
to the host CPU that a card device requires host software service. This signal doubles
as READY/BUSY during power-up initialization.
IRQ
27
K2
S
O
Interrupt request. This active-high IRQ to the subsystem indicates a host CPU write
to attribute memory has occurred.
NANDOUT
12
E4
M
O
This is a production test output.
OE
93
D4
H
I
Output enable. OE is an active-low input signal used to gate memory read data from
the card. This signal has an internal pullup resistor.
OUT1
OUT2
37
44
G5
K7
U
O
Output 1 and output 2 are active-low signals. OUT1 and OUT2 are user-defined output
terminals that are set to their active state by setting respective MCR bits (OUT1 and
OUT2) high. OUT1 and OUT2 are set to their inactive (high) state as a result of a reset,
doing loop-mode operation, or by resetting bit 2 (OUT1) or bit 3 (OUT2) of the MCR.
This signal has an open-drain outputs.
RCLK
40
J6
U
I
Receiver clock. RCLK is the 16×-baud-rate clock input for the receiver section of the
UART.
RD(DS)
29
H3
S
I
Read enable or data strobe input. RD(DS) is the active-low read enable in the Intel
mode and the active-low data strobe in the Zilog mode.
REG
73
C9
H
I
Attribute memory select. This active-low input signal is generated by the host CPU and
accesses attribute memory (OE and WE active) and I/O space (IORD or IOWR
active). PCMCIA common memory access is excluded. This signal has an internal
pullup resistor and hysteresis on the input buffer.
RESET
67
E7
H
I
Reset. RESET is an active-high input that serves as the master reset for the device.
RESET clears the UART, placing the card in an unconfigured state. This signal has
an internal pullup resistor.
NAME
PZ NO.
GGM NO.
HA0
HA1
HA2
HA3
HA4
HA5
HA6
HA7
HA8
HA9
78
79
81
82
83
84
85
87
90
92
HD0
HD1
HD2
HD3
HD4
HD5
HD6
HD7
† Host = H, Subsystem = S, UART = U, Miscellaneous = M
6
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SLLS225B – MARCH 1996 – REVISED FEBRUARY 2003
Terminal Functions
TERMINAL
PZ NO.
GGM NO.
INTERFACE†
I/O
DESCRIPTION
RI
50
K10
U
I
Ring indicator. RI is an active-low modem status signal whose condition can
be checked by reading bit 6 (RI) of the MSR. The trailing-edge ring indicator
(TERI) bit 2 of the MSR indicates that RI has transitioned from a low to a high
state since the last read from the MSR. If the modem status interrupt is enabled
when this transition occurs, an interrupt is generated.
RST
11
E3
M
O
This is the qualified active-low reset signal. RST has a fail-safe open-drain
output.
RTS
35
J5
U
O
Request to send is an active-low signal. When active, RTS informs the modem
of the data set that the UART is ready to receive data. RTS is set to its active
state by setting the RTS modem control register bit and is set to its inactive
(high) state either as a result of a reset, doing loop-mode operation, or by
resetting bit 1 (RTS) of the MCR.
SA0
SA1
SA2
SA3
SA4
SA5
SA6
SA7
53
55
56
57
58
59
61
65
H9
H10
G9
G10
G8
F10
F8
E9
S
I
When SSAB is high, this is the subsystem address bus and SAD (7–0) is the
subsystem data bus. When SSAB is low, this bus is not used and SAD(7–0)
is the subsystem multiplexed address/data bus.
SA8
24
J1
S
I
Address bit 8 is bit 8 of the subsystem address bus.
SAD0
SAD1
SAD2
SAD3
SAD4
SAD5
SAD6
SAD7
25
23
20
19
18
17
15
14
K1
H2
G2
G1
G4
F4
F2
F1
S
I/O
Subsystem address/data 7–0. This is a multiplexed bidirectional address/data
bus to the attribute-memory DPRAM and CCRs when SSAB is low. This
becomes a bidirectional data bus when SSAB is high.
SELZ/I
28
J3
S
I
Select Zilog or Intel mode. SELZ/I is used to select between a Zilog-like or
Intel-like microcontroller. 1 = Zilog, 0 = Intel.
SIN
33
H4
U
I
Serial data input. SIN moves information from the communication line or
modem to the TL16PC564B UART receiver circuits. Data on the serial bus is
disabled when operating in the loop mode.
SOUT
45
J7
U
O
Serial out. SOUT is the composite serial data output to a connected
communication device. SOUT is set to the marking (logic 1) state as a result
of a reset.
SSAB
3
C2
S
I
Separate subsystem address bus. SSAB is used to select between a
multiplexed address/data bus subsystem interface (SSAB = 0) and a
subsystem interface with separate address and data buses (SSAB = 1). This
signal has an internal pulldown resistor.
STSCHG
74
B10
H
O
Status change. STSCHG is an optional active-low output signal used to alert
the host that a subsystem write to attribute memory has occurred. This signal
has an open-drain output.
TESTOUT
70
D9
M
O
This is a production test output.
UARTCLK
51
J9
M
O
UART clock. UARTCLK is a clock output whose frequency is determined by the
frequency on XIN and the divisor value on the PGMCLK register.
10,21,22,36,
47,52,60,
72,86,97
E2,G3,H1,
H5,K8,J10,
F9,C10,C6,A
3
M
NAME
VCC
3.3-V or 5-V supply voltage
† Host = H, Subsystem = S, UART = U, Miscellaneous = M
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SLLS225B – MARCH 1996 – REVISED FEBRUARY 2003
Terminal Functions
TERMINAL
PZ NO.
GGM NO.
INTERFACE†
I/O
DESCRIPTION
WE
89
A5
H
I
Write enable. WE is an active-low input signal used for strobing attribute-memory
write data into the card. This signal has an internal pullup resistor
WR(R/W)
31
J4
S
I
Write or read/write enable. WR(R/W) is the active-low write enable in the Intel mode
and read/write in the Zilog mode.
XIN
42
G6
M
I
Crystal input. XIN is a clock input divided internally based on the PGMCLK register
value, then used as the primary UART clock input.
VTEST
2
B1
M
I
VTEST is an active-high production test input with an internal pulldown resistor. It
can be left open or tied to ground.
NAME
† Host = H, Subsystem = S, UART = U, Miscellaneous = M
detailed description
reset-validation circuit
A reset-validation circuit has been implemented to qualify the active-high RESET input. At power up, the level
on the RST output is unknown. Whenever RESET is stable for at least eight ARBCLKIs, RST reflects the
inverted state of that stable value of RESET. Any changes on RESET must be valid for eight ARBCLKI clocks
before the change is reflected on RST. This 8-clock filter provides needed hysteresis on the master reset input.
RST is driven by a low-noise, open-drain, fail-safe output buffer.
host CPU memory map
The host CPU attribute memory space is mapped as follows:
Host CPU Address Bits 9–1 (HA0 = 0)
0 – 255
256
257
258
259
260
261
262
263
Attribute Memory Space
CIS
CCR0
CCR1
CCR2
CCR3
CCR4
CCR5
CCR6
CCR7
The host CPU I/O space is mapped as follows:
Normal Mode
0 (DLAB = 0)†
0 (DLAB = 0)†
0 (DLAB = 1)†
1 (DLAB = 0)†
1 (DLAB = 1)†
2
2
3
4
5
6
7
COM1
3F8
3F8
3F8
3F9
3F9
3FA
3FA
3FB
3FC
3FD
3FE
3FF
Address Mode (hex)
COM2 COM3 COM4
2F8
3E8
2E8
2F8
3E8
2E8
2F8
3E8
2E8
2F9
3E9
2E9
2F9
3E9
2E9
2FA
3EA
2EA
2FA
3EA
2EA
2FB
3EB
2EB
2FC
3EC
2EC
2FD
3ED
2ED
2FE
3EE
2EE
2FF
3EF
2EF
I/O Space
UART receiver buffer register (RBR) – read only
UART transmitter holding register (THR) – write only
UART divisor latch LSB (DLL)
UART interrupt enable register (IER)
UART divisor latch MSB (DLM)
UART interrupt identification register (IIR) – read only
UART FIFO control register (FCR) – write only
UART line control register (LCR)
UART modem control register (MCR) – bit 5 read only
UART line status register (LSR)
UART modem status rgister (MSR)
UART scratch register (SCR)
† DLAB is bit 7 of the line control register (LCR).
8
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SLLS225B – MARCH 1996 – REVISED FEBRUARY 2003
subsystem memory map
The subsystem attribute memory space is mapped as follows:
Subsystem Address Bits 8–0
0 – 255
256
257
258
259
260
261
262
263
Attribute Memory Space
CIS
CCR0
CCR1
CCR2
CCR3
CCR4
CCR5
CCR6
CCR7
The subsystem control space is mapped as follows:
Subsystem Address Bits 8–0
272
288
Control Space
Control Register
PGMCLK Register (write only)
The subsystem UART space is mapped as follows:
Subsystem Address Bits 8–0
304
304
305
306
307
308
309
310
311
320
320
UART Space
UART MCR bit 5 (write only)
UART DLL (read only)
UART IER (read only)
UART FCR (read only)
UART LCR (read only)
UART MCR (read only)
UART LSR (read only)
UART MSR (read only)
UART DLM (read only)
UART transmitter FIFO (read only)†
UART receiver FIFO (write only)†
† Only when serial bypass mode is enabled
host CPU/attribute-memory interface
The host CPU/attribute-memory interface is comprised of one port of the internal DPRAM, the eight CCRs, and
necessary control circuitry. Signals HA0 and CE1 are gated together internally so that the output of the gate is
low when both signals have been asserted by the host CPU. This output is combined with REG and the decoded
address, HA(9–1), to provide the chip enable for the DPRAM and CCRs. This composite chip enable in
combination with WE or OE allows writes and reads to the DPRAM and CCRs.
subsystem/attribute-memory interface
The subsystem/attribute-memory interface is comprised of the second port of the internal DPRAM, the eight
CCRs, and necessary control circuitry. When in multiplexed mode (SSAB = 0), the combination of signals
SELZ/I and ALE(AS) allows either a positive-pulse Intel or a negative-pulse Zilog address latch-enable strobe
to latch the address on SA8 and SAD(7–0). When in the Zilog mode (SELZ/I high), the combination of read/write
[WR(R/W)], data strobe [RD(DS)], and decoded address allows ZBUS access. When in the Intel configuration
(SELZ/I low), the combination of read [RD(DS)], write [WR(R/W)], and decoded address allows IBUS access.
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When in nonmultiplexed mode (SSAB = 1), SA(7–0) become the lower-order address bits, SAD(7–0) are strictly
the bidirectional data bus, and ALE(AS) is nonfunctional. All other interface signals function the same.
SSAB
0
0
0
0
1
1
1
1
RD(DS)
0
1
0
0
0
1
0
0
SELZ/I
0
0
1
1
0
0
1
1
WR(R/W)
1
0
1
0
1
0
1
0
Address
SA8, SAD(7–0)
SA8, SAD(7–0)
SA8, SAD(7–0)
SA8, SAD(7–0)
SA(8–0)
SA(8–0)
SA(8–0)
SA(8–0)
Operation
Intel read
Intel write
Zilog read
Zilog write
Intel read
Intel write
Zilog read
Zilog write
attribute-memory arbitration
Arbitration for the attribute memory is necessary whenever there is simultaneous access to the same DPRAM
or CCR address for the conditions of:
•
•
•
Host CPU read and subsystem write
Host CPU write and subsystem read
Host CPU write and subsystem write
If arbitration were not provided, attribute-memory data would be corrupted and invalid data read due to
uncontrolled access to the same DPRAM or CCR address.
The arbitration control circuitry synchronizes the asynchronous accesses of the host CPU and subsystem to
the DPRAM and CCR and controls the access based on the pending host CPU and subsystem
attribute-memory operation. The synchronizing and control circuitry needs a clock called the arbitration clock.
The external clock (ARBCLKI) goes through a programmable divider and can be divided by one, two, four, or
eight to generate a clock frequency within an allowed range for the arbitration logic to work correctly. The output
of this frequency divider is named ARBCLKO. The programmable divider bits are defined as follows:
ARBPGM1
ARBPGM0
INTERNAL
ARITRATION CLOCK
L
L
ARBCLKI/1
L
H
ARBCLKI/2
H
L
ARBCLKI/4
H
H
ARBCLKI/8
The upper period limit of ARBCLKO is N/6, where N (ns) is the shortest of the two attribute-memory accesses,
host CPU or subsystem. The lower period limit of ARBCLKO is based on the DPRAM specifications at the supply
voltage used:
5 V = 14-ns clock cycle (71 MHz)
3 V = 26-ns clock cycle (38.5 MHz)
For any arbitration condition, attribute-memory access is controlled to ensure valid data is read for a port that
is doing a read operation and valid data is written for a port that is doing a write operation. When both the host
CPU and subsystem are performing simultaneous write operations to the same address, the host CPU is
allowed to write and the subsystem write is ignored.
host CPU/subsystem handshake
Two signals are provided for handshaking between the host CPU and the subsystem. The active-high IRQ
signifies to the subsystem that the host CPU has written data into attribute memory. The subsystem can clear
IRQ by writing a 1 to bit 6 of the subsystem control register. The active-low STSCHG signifies to the host CPU
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that the subsystem has written data to attribute memory provided bit 2 of the subsystem control register
(STSCHG enable) is high. The host CPU can clear STSCHG by reading any location in attribute memory. The
control of these signals is synchronized to ARBCLKO to ensure there are no false assertions/deassertions.
There is additional arbitration performed for instances of simultaneous assertion/deasseration of IRQ or
STSCHG. When a subsystem write and host CPU read occurs simultaneously, STSCHG may be briefly
deasserted prior to being asserted, but the write ultimately wins arbitration. When the host CPU read occurs
more than one-half an arbitration clock after the subsystem write, STSCHG is deasserted. IRQ is arbitrated in
a similar fashion.
host CPU/UART interface
The UART select is derived from either host CPU address information or logic levels on CE1, CE2 and REG.
In the address mode, host CPU address bits HA9, HA7, HA6, HA5, and HA3 are combined with conditional
derivatives of HA4 and HA8 to select the UART (HA4 and HA8 select COM ports 1–4 based on settings in the
subsystem control register). CE1 and CE2 are combined such that either of these two signals in combination
with REG enable the UART in the event that these signals are present. In the event that CE1 or CE2 are not
present, the UART must be accessed in the address mode previously described. The UART select in
conjunction with IORD and IOWR allows host CPU accesses to the UART. Host CPU address bits HA2–HA0
are decoded to select which UART register is to be accessed.
All UART registers remain intact with the exception of the FIFO control register (FCR) and the modem-control
register (MCR). The FCR (host CPU write-only address 2) bits 4 and 5 in conjunction with EXTEND control RTS
operation and FIFO depth as follows:
BIT 5
BIT 4
EXTEND
RTS OPERATION
FIFO DEPTH
X
X
H
Normal
16 bytes
0
0
L
Normal
16 bytes
0
1
L
Auto
16 bytes
1
0
L
Normal
64 bytes
1
1
L
Auto
64 bytes
FCR bit 5 high and EXTEND low redefine the receiver FIFO trigger levels set by FCR bits 6 and 7 as follows:
BIT 7
BIT 6
TRIGGER LEVEL
0
0
1
0
1
16
1
0
32
1
1
56
The MCR (host CPU address 4) bit 5 is read only. Bit 5 is controlled by the subsystem to enable (high) the
auto-CTS mode of operation
subsystem/UART interface
The UART provides a serial-communications channel to the subsystem with enhanced RTS control (see
auto-RTS description). This channel is capable of operating at 115 kbps and is the main communications
channel to the subsystem (refer to the TL16C550 specification for the detailed description of the
serial-communications channel).
Many of the UART registers have been mapped into the subsystems memory space as read only. In addition,
MCR bit 5 (subsystem address 130 hex) is controlled by the subsystem to enable (high) auto-CTS. The
subsystem can read the MCR at address 134 hex. When reading the FCR (subsystem address 132 hex), bits
1 and 2 are always high, and bits 4 and 5 are low only when EXTEND is low and the host CPU has set them
high (64-byte FIFOs and auto-RTS enabled) (refer to the subsystem memory map).
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subsystem control register
The subsystem control register is an 8-bit register located at subsystem address 110 (hex). This register is
programmed based on host CPU configuration information and has a default selection of COM2 after a valid
reset. The bit definitions are as follows (0 = LSB):
Bits 0 and 1 define which host COM port the UART is connected to when the chip is in the address mode.
COM2 is the default (power-up) condition.
BIT 1
BIT 0
COM PORT
0
0
COM1
1
0
COM2
0
1
COM3
1
1
COM4
Bit 2 is a host CPU interrupt-enable bit. When bit 2 is set, any subsystem attribute-memory write cycle
causes STSCHG to be asserted. Bit 2 is cleared after a valid reset.
Bit 3 enables or disables address-mode selection as described in the host CPU/UART interface description.
Bit 3 is cleared (disabling the address mode) after a valid reset.
Bits 4 and 5 together ensure adherence to PCMCIA power-up requirements. At power up, the card must
operate as a memory card and all host CPU I/O operations must be disabled. IREQ, which doubles as the
host CPU READY/BUSY line, powers up low, indicating that the memory card is busy. Once the subsystem
initializes attribute memory, the subsystem sets bit 4 to indicate that the memory card is ready. Then bit 5 is
reset, changing the configuration from a memory card to an I/O card, enabling host CPU UART accesses.
IREQ now becomes the host CPU interrupt-request line.
BIT 5
BIT 4
CONFIGURATION
1
0
Memory card, I/O operation (UART) disabled; IREQ is low, indicating card is busy (power-up and reset
condition)
1
1
Memory card, I/O operation (UART) disabled; IREQ is high, indicating card is ready
0
X
I/O card, I/O operation (UART) enabled; IREQ now functions as the host CPU interrupt-request line
Bit 6 is a self-clearing bit that resets the subsystem IRQ signal. Writing a 1 to this location clears the IRQ
interrupt.
Bit 7 enables or disables serial-bypass mode as described in the subsystem serial-bypass-mode
description. Bit 7 is cleared (disabling serial-bypass mode) after a valid reset.
subsystem PGMCLK register/divide-by-n circuit
The subsystem PGMCLK register is a 6-bit write-only register located at address 120 hex and is used to select
the divisor of the divide-by-n-and-a-half circuitry. Any write to this register generates a reset to the UART and
the divide-by-n circuitry.
The divide-by-n circuitry allows for a divisor from 0 to 31.5 in 0.5 increments (PGMCLK0 is the half bit). The
divided clock output drives the UART clock input and can be seen on UARTCLK. The UART requires a clock
with a minimum high pulse duration of 50 ns and a minimum low pulse duration of 50 ns (10-MHz maximum
operating frequency). A programmed divisor between 2 and 7.5 drives the UART clock low for one XIN clock
cycle for integer divisors and one-and-a-half XIN clock cycles for integer-plus-a-half divisors. A programmed
divisor of eight or greater drives the UART clock low for four XIN clock cycles for integer divisors. A
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four-and-a-half XIN clock cycles for integer-plus-a-half divisors. Based on the above parameters, the
acceptable XIN/divisor combinations can be derived. The precision of the programmable clock generator for
integer-plus-a-half divisors depends on the closeness to a 50% duty cycle for the XIN input clock.
NOTE
With a divisor less than or equal to 8 (whole number), the UART clock will have a low pulse equal
to one clock cycle of the XIN clock. Caution should be used as noted in the following example.
A 20 MHz clock period yields 50 ns total, including rise time and fall time, if a divisor of less than
or equal to 8 (whole number) is used. This provides a total down period less than 50 ns to the UART
clock, which is less than that which is required for the UART to function properly.
Caution should be used when selecting the XIN and divisor combination.
PGMCLK(0–5) VALUE (HEX)
RESULT
0
(0)
No clock (driven high)
0.5
(1)
Divide-by-1
1
(2)
Divide-by-1
1.5
(3)
Divide-by-1
(4) to 31.5 (3F)
Divide-by-2 to divide-by-31.5
2
subsystem serial-bypass mode
The optional serial-bypass mode is implemented to allow a high-throughput path to/from the host CPU. When
this mode is enabled and subsystem control register bit 7 is high, the serial portion of the UART is bypassed
and the subsystem has direct parallel access to the receiver FIFO (write address 140 hex) and the transmitter
FIFO (read address 140 hex). All host CPU interrupts operate normally except for receiver parity, framing, and
breaking interrupts.
auto-CTS operation
The optional auto-CTS operation is implemented so that the host CPU cannot overflow the modem receive
buffer. Auto-CTS operation is enabled when the subsystem sets MCR (subsystem address 130 hex) bit 5 high.
When enabled, deactivating CTS (high) halts the transmitter section of the UART after it completes the current
transfer. Once CTS is reactivated (low) by the modem, transfers resume. Interrupt operation is not affected by
enabling auto-CTS.
auto-RTS operation
The optional auto-RTS operation is implemented so that the subsystem cannot overflow the receiver FIFO.
Auto-RTS operation is enabled when FCR bit 4 is high and EXTEND is low and operates independently from
the trigger-level circuitry. In the 16-byte FIFO mode, the RTS bit in the modem-control register (bit 1) clears when
14 characters are in the receive FIFO. This action causes RTS to go high (inactive). In the 64-byte FIFO mode,
the MCR RTS bit clears when 56 characters are in the receiver FIFO. Interrupt operation is not affected and
operates the same way in either auto-RTS or nonauto-RTS mode. When enabled, a receive-dataavailable interrupt occurs after the trigger level is reached. The MCR RTS bit must then be set by the host CPU
after the receiver FIFO has been read.
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power consumption
The TL16PC564B has low power consumption under the following conditions:
•
•
•
•
32-MHz signal on XIN
Divide-by-n is set to give a 1.8432-MHz UARTCLK signal
Nominal data
VCC = 5 V
The current (ICC) and power consumption are 18 mA (typical) and 90 mW (typical), respectively. These current
and power figures fluctuate with changes in the above conditions.
absolute maximum ratings over operating free-air temperature range†
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 6 V
Input voltage range, VI (standard) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V
Input voltage range, VI (fail safe) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 6.5 V
Output voltage range, VO (standard) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V
Output voltage range, VO (fail safe) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 6.5 V
Input clamp current, IIK (VI < 0 or VI > VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
Output clamp current, IOK (VO < 0 or VO > VCC) (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
Operating free-air operating temperature range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. Applies for external input and bidirectional buffers. VI > VCC does not apply to fail-safe pins.
2. Applies for external output and bidirectional buffers. VO > VCC does not apply to fail-safe pins.
recommended operating conditions
low voltage (3.3 V nominal)
Supply voltage
voltage, VCC
TL16PC564B
TL16PC564BLV
Input voltage, VI
MIN
NOM
MAX
3
3.3
3.6
V
2.7
3
3.3
V
VCC
V
0
High-level input voltage (CMOS), VIH (see Note 3)
0.7VCC
V
Low-level input voltage (CMOS), VIL (see Note 3)
Output voltage, VO (see Note 4)
High-level output current, IOH
Low level output current
Low-level
current, IOL
UNIT
0.3VCC
VCC
0
All outputs except RST, STSCHG, OUT1, OUT2 (see Note 5)
1.8
All outputs except RST
3.2
RST
6.4
V
V
mA
mA
Input transition time, tt
0
25
ns
Operating free-air temperature range, TA
0
25
70
°C
Junction temperature range, TJ (see Note 6)
0
25
115
°C
NOTES: 3.
4.
5.
6.
14
Meets TTL levels, VIHmin = 2 V and VILmax = 0.8 V on nonhysteresis inputs
Applies for external output buffers
RST, STSCHG, OUT1, and OUT2 are open-drain outputs, so IOH does not apply.
These junction temperatures reflect simulation conditions. Absolute maximum junction temperature is 150°C. The customer is
responsible for verifying junction temperature.
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standard voltage (5 V nominal)
Supply voltage, VCC
Input voltage, VI
MIN
NOM
4.75
5
0
High-level input voltage (CMOS), VIH
Output voltage, VO (see Note 4)
5.25
V
VCC
V
V
0.2VCC
VCC
0
Low level output current
Low-level
current, IOL
UNIT
0.7VCC
Low-level input voltage (CMOS), VIL
High-level output current, IOH
MAX
All outputs except RST, STSCHG, OUT1, OUT2 (see Note 5)
4
All outputs except RST
4
RST
8
V
V
mA
mA
Input transition time, tt
0
25
ns
Operating free-air temperature range, TA
0
25
70
°C
Junction temperature range, TJ (see Note 6)
0
25
115
°C
NOTES: 4. Applies for external output buffers
5. RST, STSCHG, OUT1, and OUT2 are open-drain outputs, so IOH does not apply.
6. These junction temperatures reflect simulation conditions. Absolute maximum junction temperature is 150°C. The customer is
responsible for verifying junction temperature.
electrical characteristics over recommended ranges of operating free-air temperature and supply
voltage (unless otherwise noted)
low voltage (3.3 V nominal)
PARAMETER
TEST CONDITIONS
VOH
VOL
High-level output voltage
IOH = rated
IOL = rated
VIT+
VIT–
Positive-going input threshold voltage (see Note 7)
Vhys
IOZ
Hysteresis (VIT+ – VIT–) (see Note 7)
IIL
IIH
Low-level input current (see Note 9)
VI = VCC or GND
VI = GND
High-level input current (see Note 10)
VI = VCC
Low-level output voltage
MIN
MAX
VCC–0.55
V
0.5
0.7 VCC
Negative-going input threshold voltage (see Note 7)
0.3 VCC
0.1 VCC
3-state-output high-impedance current (see Note 8)
UNIT
V
V
V
0.3 VCC
V
±10
µA
–1
µA
1
µA
standard voltage (5 V nominal)
PARAMETER
TEST CONDITIONS
VOH
VOL
High-level output voltage
IOH = rated
IOL = rated
VIT+
VIT–
Positive-going input threshold voltage (see Note 7)
Vhys
IOZ
Hysteresis (VIT+ – VIT–) (see Note 7)
IIL
IIH
Low-level input current (see Note 9)
VI = VCC or GND
VI = GND
High-level input current (see Note 10)
VI = VCC
Low-level output voltage
MAX
0.5
0.2 VCC
0.1 VCC
3-state-output high-impedance current (see Note 8)
UNIT
V
0.7 VCC
Negative-going input threshold voltage (see Note 7)
NOTES: 7.
8.
9.
10.
MIN
VCC–0.8
V
V
V
0.3 VCC
V
±10
µA
–1
µA
1
µA
Applies for external input and bidirectional buffers with hysteresis
The 3-state or open-drain output must be in the high-impedance state.
Specifications only apply with pullup terminator turned off.
Specifications only apply with pulldown terminator turned off.
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XIN timing requirements over recommended operating free-air temperature range (see Figure 1)
TEST CONDITIONS
VCC = 3.3 V,
VCC = 5 V
VCC = 3.3 V,
Input frequency
tc1
C cle time,
Cycle
time XIN
tw1
P lse d
Pulse
duration,
ration XIN clock high
tw2
P lse duration,
Pulse
d ration XIN clock low
lo
VCC = 5 V
VCC = 3.3 V,
VCC = 5 V
VCC = 3.3 V,
MIN
See Note 11
MAX
50
60
See Note 11
ns
10
ns
8
See Note 11
VCC = 5 V
MHz
20
16.7
See Note 11
UNIT
10
ns
8
NOTE 11: TL16PC564BLV device tested at VCC = 3 V.
clock switching characteristics over recommended operating free-air temperature range (see
Figure 1)
PARAMETER
TEST CONDITIONS
VCC = 3.3 V,
VCC = 5 V
VCC = 3.3 V,
MIN
See Note 11
td1
time XIN↑ to UARTCLK↑
Delay time,
td2
Delay time,
time XIN↓ to UARTCLK↓
td3
VCC = 3.3 V,
VCC = 5 V
See Note 11
Delay time,
time XIN↑ to UARTCLK↓
td4
VCC = 3.3 V,
VCC = 5 V
See Note 11
time XIN↑ to UARTCLK↑
Delay time,
td5
VCC = 3.3 V,
VCC = 5 V
See Note 11
Delay time,
time XIN↓ to UARTCLK↑
MAX
UNIT
14
8
See Note 11
16
VCC = 5 V
10
19.8
13
20.6
13.5
21
13.8
ns
ns
ns
ns
ns
NOTE 11: TL16PC564BLV device tested at VCC = 3 V.
host CPU I/O read-cycle timing requirements over recommended ranges of operating free-air
temperature and supply voltage (see Figure 2 and Note 12)
MIN
th1
th2
Hold time, HA(9–0) valid after IORD↑
tw4
tsu1
Pulse duration, IORD low
tsu2
th3
Setup time, CEx↓ before IORD↓
th4
tsu3
Hold time, REG↑ valid after IORD↑
Setup time, HA(9–0) valid before IORD↓
MAX
UNIT
20
ns
0
ns
165
ns
70
ns
5
ns
20
ns
Hold time, HD(7–0) valid after IORD↑
0
ns
Setup time, REG↓ before IORD↓
5
ns
Hold time, CEx↑ after IORD↑
td6
Delay time, HD(7–0) valid after IORD↓
100
NOTE 12: The maximum load on INPACK is one low power shot with 50-pF total load. All timing is measured in nanoseconds.
ns
host CPU I/O read-cycle switching characteristics over recommended ranges of operating free-air
temperature and supply voltage (see Figure 2 and Note 11)
PARAMETER
td7
td8
MIN
MAX
UNIT
Delay time, INPACK↓ after IORD↓
45
ns
Delay time, INPACK↑ after IORD↑
45
ns
NOTE 12: The maximum load on INPACK is one low power Schottky (LSTTL) diode with 50-pF total load. All timing is measured in nanoseconds.
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host CPU I/O write-cycle timing requirements over recommended ranges of operating free-air
temperature and supply voltage (see Figure 3)
MIN
tsu4
th5
Setup time, HD(7–0) valid before IOWR↓
tw6
tsu5
Pulse duration, IOWR low
th6
tsu6
th7
tsu7
Hold time, CEx↑ after IOWR↑
th8
Hold time, HD(7–0) valid after IOWR↑
Hold time, HA(9–0) valid after IOWR↑
MAX
UNIT
60
ns
20
ns
165
ns
70
ns
Hold time, REG↑ after IOWR↑
0
ns
Setup time, CEx↓ before IOWR↓
5
ns
20
ns
5
ns
30
ns
Setup time, HA(9–0) valid before IOWR↓
Setup time, REG↓ before IOWR↓
transmitter switching characteristics over recommended ranges of operating free-air temperature
and supply voltage (see Figure 4)
PARAMETER
TEST CONDITIONS
MIN
MAX
UNIT
td9
Delay time, SOUT↓ after IOWR↑
8
24
Baud
cycles
td10
Delay time, IREQ↓ after SOUT↓
8
8
Baud
cycles
td11
Delay time, IREQ↓ after IOWR↑
16
32
Baud
cycles
td12
td13
Delay time, IREQ↑ after IOWR↑
CL = 100 pF
140
ns
Delay time, IREQ↑ after IORD↑
CL = 100 pF
140
ns
receiver switching characteristics over recommended ranges of operating free-air temperature
and supply voltage (see Figure 5)
PARAMETER
td14
Delay time, sample CLK↑ after RCLK↑
td15
Delay time, IREQ↓ after SIN↓
td16
Delay time, IREQ↑ after IORD↑
TEST CONDITIONS
MIN
MAX
UNIT
100
ns
1
CL = 100 pF
150
RCLK
cycles
ns
modem-control switching characteristics over recommended ranges of operating free-air
temperature and supply voltage, CL = 100 pF (see Figure 6)
PARAMETER
MIN
MAX
UNIT
td17
Delay time, RTS, DTR, OUT1, OUT2 ↓ or ↑ after IOWR↑
50
ns
td18
Delay time, IREQ↓ after CTS, DSR, DCD↓
30
ns
td19
td20
Delay time, IREQ↑ after IORD↑
35
ns
Delay time, IREQ↓ after RI↑
30
ns
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host CPU attribute-memory write-cycle timing requirements over recommended ranges of
operating free-air temperature and supply voltage (see Figures 7 and 8)
MIN
MAX
UNIT
tc2
tw8
Write cycle tIme, HA(9–0)
250
ns
Pulse duration, WE low
150
ns
tsu8
tsu9
Setup time, CEx↓ before WE↑
180
ns
Setup time, HA(9–0) before WE↑ (see Note 12)
180
ns
tsu10
tsu11
Setup time, HA(9–0) before WE↓ and CEx↓(see Note 13)
30
ns
Setup time, OE↑ before WE↓
10
ns
th9
trec1
Hold time, HD(7–0) after WE↑
30
ns
Recovery time, HA(9–0) after WE↑
30
ns
tsu12
th10
Setup time, HD(7–0) before WE↑
80
ns
Hold time, OE↓ after WE↑
10
ns
tsu13
th11
Setup time, CEx↓ before WE↓
0
ns
20
ns
Hold time, CEx↑ after WE↑
NOTE 13: The REG signal timing is identical to address signal timing.
host CPU attribute-memory write-cycle switching characteristics over recommended ranges of
operating free-air temperature and supply voltage (see Figure 7)
PARAMETER
MIN
MAX
UNIT
100
ns
100
ns
tdis1
tdis2
Disable time, HD(7–0) after WE↓
ten1
ten2
Enable time, HD(7–0) after WE↑
5
ns
Enable time, HD(7–0) after OE↓
5
ns
Disable time, HD(7–0) after OE↑
host CPU attribute-memory read-cycle timing requirements over recommended ranges of
operating free-air temperature and supply voltage (see Figure 9)
MIN
MAX
300
UNIT
tc3
td22
Read cycle time
Delay time, HD(7–0) after HA(9–0)
300
ns
ns
td23
td24
Delay time, HD(7–0) after CEx↓
300
ns
Delay time, HD(7–0) after OE↓
150
ns
th12
tsu14
Hold time, HD(7–0) after HA(9–0)
th13
tsu15
th14
0
ns
Setup time, CEx↓ before OE↓
0
ns
Hold time, HA(9–0) after OE↑
20
ns
Setup time, HA(9–0) before OE↓
30
ns
Hold time, CEx↑ after OE↑
20
ns
host CPU attribute-memory read-cycle switching characteristics over recommended ranges of
operating free-air temperature and supply voltage (see Figure 9)
PARAMETER
MIN
MAX
UNIT
100
ns
100
ns
tdis3
tdis4
Disable time, HD(7–0) after CEx↑
ten3
ten4
Enable time, HD(7–0) after CEx↓
5
ns
Enable time, HD(7–0) after OE↓
5
ns
18
Disable time, HD(7–0) after OE↑
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subsystem Intel-mode timing requirements (32 MHz) (see Figure 10)
INTEL
SYMBOL
JEDEC
SYMBOL
tLHLL
tAVLL
tw11
tsu16
Pulse duration, ALE high
48
ns
Setup time, SA8, SAD(7–0) valid to ALE low
21
ns
tPLLL
tLLAX
td25
th15
Delay time, CS low to ALE low
21
ns
Hold time, SA8, SAD(7–0) valid after ALE↓
21
ns
tLLWL
tLLRL
td26
td27
Delay time, ALE low to WR low
16
ns
Delay time, ALE low to RD low
16
ns
tWHLH
tAFRL
td28
td29
Delay time, WR high to ALE high
21
ns
0
ns
tRLRH
tWLWH
tw12
tw13
Pulse duration, RD low
120
ns
Pulse duration, WR low
120
ns
tRHAX
tWHDX
td30
th16
Delay time, RD high to SA8, SAD(7–0) active
48
ns
Hold time, SA8, SAD(7–0) valid after WR high
48
ns
tWHPH
tRHPH
td31
td32
Delay time, WR high to CS high
21
ns
Delay time, RD high to CS high
21
ns
tPHPL
tw14
Pulse duration, CS high
21
ns
MIN
Delay time, SA8, SAD(7–0) in high-impedance state to RD low
MAX
UNIT
subsystem Zilog-mode timing requirements (20 MHz) (see Figure 11)
ZILOG
SYMBOL
JEDEC
SYMBOL
MIN
MAX
UNIT
tdA(AS)
tdAS(A)
tsu17
td33
Setup time, SA8 and SAD(7–0) valid before AS high
20
ns
Delay time, AS high to SA8 and SAD(7–0) invalid
35
ns
tdAS(DR)
twAS
td34
tw15
Delay time, AS high to data in on SAD(7–0)
tdA(DS)
twDS(read)
td35
tw16
Delay time, SA8 and SAD(7–0) invalid to DS low
twDS(write)
tdDS(DR)
tw17
td36
thDS(DR)
tdDS(A)
th17
th18
Hold time, DS high to data in invalid
tdDS(AS)
tdDO(DS)
tdRW(AS)
Pulse duration, AS low
150
ns
35
ns
0
ns
Pulse duration, DS low (read)
125
ns
Pulse duration, DS low (write)
65
ns
Delay time, DS low to data in valid
80
ns
0
ns
Hold time, DS high to data out invalid
20
ns
td37
td38
Delay time, DS high to AS low
30
ns
Delay time, SAD(7–0) (write data from µP) valid to DS low
10
ns
td39
Delay time, R/W active to AS high
20
ns
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SLLS225B – MARCH 1996 – REVISED FEBRUARY 2003
subsystem Intel nonmultiplexed timing requirements (see Figure 12)
MIN
MAX
UNIT
tsu18
tw18
Setup time, SA(8–0), CS valid to RD, WR↓
30
ns
Pulse duration, RD low
120
ns
tw19
tsu19
Pulse duration, WR low
120
ns
50
ns
ten4
td40
Enable time, RD↓ to SAD(7–0) driving
5
ns
th19
th20
Hold time, SA(8–0), CS valid after RD, WR↑
30
ns
Hold time, SAD(7–0) valid after WR↑
30
ns
tdis3
Disable time, RD↑ to SAD(7–0) high impedance
Setup time, SAD(7–0) valid to WR↑
Delay time, RD↓ to SAD(7–0) valid
105
5
15
MIN
MAX
ns
ns
subsystem Zilog nonmultiplexed timing requirments (see Figure 13)
20
UNIT
tsu20
tsu21
Setup time, SA(8–0), CS, R/W valid to DS↓ (write)
90
ns
Setup time, SA(8–0), CS, R/W valid to DS↓ (read)
30
ns
tw20
tw21
Pulse duration, DS low (write)
65
ns
Pulse duration, DS low (read)
125
ns
tsu22
ten5
Setup time, SAD(7–0) valid to DS↑
50
ns
5
ns
td41
th21
Delay time, DS↓ to SAD(7–0) valid
Hold time, SA(8–0), CS, R/W valid after DS↑
30
ns
th22
tdis4
Hold time, SAD(7–0), CS, R/W valid after DS↑
30
ns
Enable time, DS↓ to SAD(7–0) driving
105
Hold time, DS↑ to SAD(7–0) high impedance
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15
ns
ns
SLLS225B – MARCH 1996 – REVISED FEBRUARY 2003
ARBCLK switching characteristics over recommended operating free-air temperature range (see
Figure 14)
TEST CONDITIONS
tc4
C cle time,
Cycle
time internal arbitration clock ( ARBCLKI ÷ ARBPGM)
tc5
C cle time
Cycle
time, arbitration clock
td42
Delay time,
time ARBCLKI↑ to ARBCLK0↑ (÷1)
td43
Dela time,
Delay
time ARBCLKI↓ to ARBCLK0↓ (÷1)
td44
time ARBCLKI↑ to ARBCLK0↑ (÷2)
Delay time,
td45
Delay time,
time ARBCLKI↑ to ARBCLK0↓ (÷2)
td46
Delay time,
time ARBCLKI↑ to ARBCLK0↑ (÷4)
td47
Delay time,
time ARBCLKI↑ to ARBCLK0↓ (÷4)
td48
Delay time,
time ARBCLKI↑ to ARBCLK0↑ (÷8)
td49
time ARBCLKI↑ to ARBCLK0↓ (÷8)
Delay time,
VCC = 3.3 V,
VCC = 5 V
See Note 11
VCC = 3.3 V,
VCC = 5 V
VCC = 3.3 V,
See Note 11
VCC = 5 V
VCC = 3.3 V,
VCC = 5 V
VCC = 3.3 V,
VCC = 5 V
VCC = 3.3 V,
VCC = 5 V
VCC = 3.3 V,
VCC = 5 V
VCC = 3.3 V,
VCC = 5 V
VCC = 3.3 V,
VCC = 5 V
VCC = 3.3 V,
MIN
MAX
26
Note 14
14
Note 14
UNIT
ns
26
ns
14
See Note 11
13
ns
7.3
See Note 11
15.5
ns
10
See Note 11
15.3
ns
8.8
See Note 11
17.5
ns
11
See Note 11
19.5
ns
11.5
See Note 11
21.5
ns
13.5
See Note 11
22.7
ns
13.5
See Note 11
25
VCC = 5 V
ns
15.7
NOTES: 11. TL16PC564BLV device tested at 3 V.
14. tc4 MAX = N/6, where N = shortest (in ns) of the two attribute-memory accesses, host CPU or subsystem.
reset timing requirements over recommended ranges of operating free-air temperature and supply
voltage (unless otherwise noted) (see Figure 15)
TEST CONDITIONS
tw22
tw23
Pulse duration, RESET active
MIN
MAX
8⋅tc5
8⋅tc5
Pulse duration, RESET inactive
td50
Delay time,
time ARBCLKI↑ to RST low
td51
Delay time,
time ARBCLKI↑ to RST high impedance
VCC = 3.3 V,
VCC = 5 V
See Note 11
VCC = 3.3 V,
See Note 11
UNIT
ns
ns
10.4
7.5
ns
13.9
VCC = 5 V
9.7
ns
NOTE 11: TL16PC564BLV device tested at 3 V.
subsystem interrupt-request timing requirements over recommended ranges of operating free-air
temperature and supply voltage (see Figure 16)
MIN
td52
Delay time, WE↑ to IRQ↑ (see Note 15)
td53
Delay time, SCR bit 6↑ to IRQ↓ (see Note 16)
MAX
UNIT
2tc5
3tc5
ARBCLKI
cycles
tc5
2tc5
ARBCLKI
cycles
NOTES: 11. TL16PC564BLV device tested at 3 V.
15. Synchronized to rising edge of ARBCLKI
16. Synchronized to falling edge of ARBCLKI
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SLLS225B – MARCH 1996 – REVISED FEBRUARY 2003
host CPU status change timing requirements over recommended ranges of operating free-air
temperature and supply voltage (see Figure 17)
MIN
td54
Delay time, subsystem write↑ to STSCHG↓ (see Note 14)
td55
Delay time, OE↓ to STSCHG high impedance (see Note 15)
MAX
UNIT
2tc5
3tc5
ARBCLKI
cycles
tc5
2tc5
ARBCLKI
cycles
NOTES: 15. Synchronized to rising edge of ARBCLKI
16. Synchronized to falling edge of ARBCLKI
PARAMETER MEASUREMENT INFORMATION
N
tw1
tc1
XIN
tw2
td1
td2
UARTCLK
(1/0.5 – 1/1.5)
td3
td4
UARTCLK†
(1/2 – 1/7)
1 XIN Cycle
td3
(N–1)XIN Cycles
td5
UARTCLK†
(1/2.5 – 1/7.5)
1.5 XIN Cycles
(N–1.5)XIN Cycles
td3
‡
UARTCLK
(1/8 – 1/31)
td4
4 XIN Cycles
(N–4)XIN Cycles
td5
td3
UARTCLK‡
(1/8.5 – 1/31.5)
4.5 XIN Cycles
(N–4.5)
XIN Cycles
† The low portion of the UARTCLK cycle = 1 XIN cycle for PGMCLK integer values of 2 to 7 and 1.5 XIN cycles for PGMCLK noninteger values
2.5 to 7.5.
‡ The low portion of the UARTCLK cycle = 4 XIN cycles for PGMCLK integer values of 8 to 31 and 4.5 XIN cycles for PGMCLK noninteger values
8.5 to 31.5.
Figure 1. XIN Clock Timing Waveforms
22
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SLLS225B – MARCH 1996 – REVISED FEBRUARY 2003
PARAMETER MEASUREMENT INFORMATION
HA(9–0)
90%
50%
10%
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
REG
10%
10%
CE1, CE2
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
th1
tsu3
th2
10%
10%
tsu2
th3
tw4
IORD
50%
tsu1
50%
td7
INPACK
10%
10%
td6
td8
th4
HD(7–0)
Valid
NOTE A: All timings are measured at the card. Skews and delays from the system driver/receiver to the card must be accounted for by the system
design.
Figure 2. Host CPU I/O Read Timing Waveforms
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SLLS225B – MARCH 1996 – REVISED FEBRUARY 2003
PARAMETER MEASUREMENT INFORMATION
50%
HA(9–0)
50%
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
th5
REG
10%
10%
tsu7
CE1, CE2
th6
10%
10%
tsu6
th7
tw6
IOWR
50%
50%
th8
tsu5
tsu4
HD(7–0)
NOTE A: All timings are measured at the card. Skews and delays from the system driver/receiver to the card must be accounted for by the system
design.
Figure 3. Host CPU I/O Write Timing Waveforms
SOUT
50%
Start
Data Bits (5–8)
Parity
Stop
Start
50%
td9
td10
IREQ
50%
td11
IOWR
(write transmitter
holding register)
td12
50%
50%
td13
IORD
(read interruptidentification
register)
50%
Figure 4. Transmitter Timing Waveforms
24
50%
50%
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SLLS225B – MARCH 1996 – REVISED FEBRUARY 2003
PARAMETER MEASUREMENT INFORMATION
8 Clocks
RCLK
td14
Sample CLK
(internal)
TL16C450 Mode:
SIN
Start
Data Bits (5–8)
Parity
50%
Stop
Sample CLK
td15
IREQ
(data read or
receive ERR)
50%
50%
td16
IORD
(read RBR or
read LSR)
50%
Figure 5. Receiver Timing Waveforms
IOWR
(write MCR)
50%
50%
td17
td17
RTS, DTR
OUT1, OUT2
50%
50%
CTS, DSR
DCD
50%
td18
IREQ
50%
50%
td19
IORD
(read MSR)
50%
td20
50%
50%
RI
Figure 6. Modem Control Timing Waveforms
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SLLS225B – MARCH 1996 – REVISED FEBRUARY 2003
PARAMETER MEASUREMENT INFORMATION
tc2
HA(9–0)
90%
90%
90%
10%
10%
10%
ÎÎÎÎÎÎ
ÎÎÎÎÎÎ
CE1, CE2
See Note A
tsu8
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
tsu13
10%
tsu9
th11
90%
OE
90%
tsu11
tw8
trec1
90%
WE
See Note A
10%
90%
10%
10%
th10
tsu12
See Note B
th9
90%
Data Input Established
HD(7–0) IN
10%
tdis1
tdis2
90%
10%
ten2
ten1
90%
HD(7–0) OUT
10%
NOTES: A. The hatched portion may be either high or low.
B. When the data I/O terminal is in the output state, no signals should be applied to HD(7–0) by the system.
Figure 7. Host CPU Attribute-Memory Write Timing Waveforms (WE Control)
26
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PARAMETER MEASUREMENT INFORMATION
tc2
90%
10%
HA(9–0)
90%
10%
tsu10
trec1
tsu8
CE1, CE2
90%
90%
10%
10%
See Note B
ÎÎÎÎÎÎ
ÎÎÎÎÎÎ
WE
See Note C
HD(7–0)
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
90%
See Note A
10%
tsu12
90%
Data Input Established
10%
See Note A
th9
90%
10%
NOTES: A. The hatched portion may be either high (H) or low (L).
B. OE must be high (H).
C. When the data I/O terminal is in the output state, no signals should be applied to HD(7–0) by the system.
Figure 8. Host CPU Attribute-Memory Write Timing Waveforms (CE Control)
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SLLS225B – MARCH 1996 – REVISED FEBRUARY 2003
PARAMETER MEASUREMENT INFORMATION
tc3
td22
90%
10%
HA(9–0)
90%
10%
90%
10%
th12
th13
CE1, CE2
ÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎ
th14
td23
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
90%
See Note A
See Note A
10%
tsu14
tsu15
ten3
90%
OE
90%
10%
td24
tdis3
tdis4
ten4
HD (7–0)
90%
90%
90%
10%
10%
10%
NOTE A: The shaded portion may be either high or low.
Figure 9. Host CPU Attribute-Memory Read Timing Waveforms
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PARAMETER MEASUREMENT INFORMATION
tw11
ALE
50%
50%
50%
tsu16
SA8,
SAD(7–0)
td28
th15
50%
µP Address
µP Data
50%
50%
td29
td26, td27
td30, th16
tw12, tw13
WR or RD
50%
50%
td25
tw14
td31, td32
CS
50%
50%
Figure 10. Subsystem Intel-Mode Timing Waveforms
90%
10%
R/W
td39
90%
10%
CS
td34
SA8,
SAD(7–0)
90%
10%
µP Address
90%
90%
10%
10%
th18
µP Data Out
90%
10%
µP Data In
90%
10%
td38
tsu17
10%
td33
td37
90%
10%
td35
tw15
DS
10%
th17
90%
AS
90%
µP Out
td36
90%
10%
90%
90%
10%
10%
tw17
tw16
NOTE A: Figures 10 and 11 are from the microprocessor perspective, not from the UART perspective.
Figure 11. Subsystem Zilog-Mode Timing Waveforms
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SLLS225B – MARCH 1996 – REVISED FEBRUARY 2003
PARAMETER MEASUREMENT INFORMATION
SA (8–0) CS
tsu18
th19
tw18, tw19
WR or RD
tsu19
th20
SAD (7–0) IN
td40
tdis3
ten4
Data Valid
SAD (7–0) OUT
Figure 12. Subsystem Intel Nonmultiplexed Timing Waveforms
SA (8–0) CS
R/W
tsu20
th21
tsu21
tw20
DS
tw21
tsu22
th22
SAD (7–0) IN
td41
tdis4
ten5
Data Valid
SAD (7–0) OUT
Figure 13. Subsystem Zilog Nonmultiplexed Timing Waveforms
30
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SLLS225B – MARCH 1996 – REVISED FEBRUARY 2003
PARAMETER MEASUREMENT INFORMATION
tc5
ARBCLKI
td43
td42
ARBCLKO (1/1)
td45
tc4
td44
ARBCLKO (1/2)
td47
tc4
td46
ARBCLKO (1/4)
td49
tc4
td48
ARBCLKO (1/8)
Figure 14. Arbitration-Clock Timing Waveforms
tc5
ARBCLKI
1
2
3
4
5
6
7
8
1
2
3
tw22
4
5
6
7
8
tw23
RESET
td50
td51
RST
Figure 15. Reset Timing Waveforms
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SLLS225B – MARCH 1996 – REVISED FEBRUARY 2003
PARAMETER MEASUREMENT INFORMATION
WE
SCR Bit 6
td52
td53
IRQ
Figure 16. IRQ Timing Waveforms
Subsystem Write
(Intel WR)
(Zilog DS)
OE
td54
STSCHG
Figure 17. STSCHG Timing Waveforms
32
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td55
SLLS225B – MARCH 1996 – REVISED FEBRUARY 2003
MECHANICAL DATA
GGM (S–PBGA–N100)
PLASTIC BALL GRID ARRAY
10,10
SQ
9,90
7,20 TYP
0,80
0,40
K
0,80
J
H
G
F
E
0,40
D
C
B
A
A1 Corner
1
2
3
4
5
6
7
8
9
10
Bottom View
0,95
0,85
1,40 MAX
Seating Plane
0,55
0,45
0,08
0,45
0,35
0,10
4145257–3/C 12/01
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice
C. MicroStar BGA configuration.
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SLLS225B – MARCH 1996 – REVISED FEBRUARY 2003
MECHANICAL DATA
PZ (S-PQFP-G100)
PLASTIC QUAD FLATPACK
0,27
0,17
0,50
75
0,08 M
51
76
50
100
26
1
0,13 NOM
25
12,00 TYP
Gage Plane
14,20
SQ
13,80
16,20
SQ
15,80
0,05 MIN
1,45
1,35
0,25
0°–ā7°
0,75
0,45
Seating Plane
0,08
1,60 MAX
4040149/A 03/95
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Falls within JEDEC MO-136
34
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PACKAGE OPTION ADDENDUM
www.ti.com
10-Apr-2008
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
TL16PC564BPZ
ACTIVE
LQFP
PZ
100
90
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
TL16PC564BPZG4
ACTIVE
LQFP
PZ
100
90
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
Lead/Ball Finish
MSL Peak Temp (3)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
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Addendum-Page 1
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