UC3843

UC3843
UC1842/3/4/5
UC2842/3/4/5
UC3842/3/4/5
www.ti.com
SLUS223C – APRIL 1997 – REVISED JUNE 2007
CURRENT MODE PWM CONTROLLER
FEATURES
•
•
•
•
•
•
•
•
•
•
•
DESCRIPTION
Optimized For Off-line and DC-to-DC
Converters
Low Start-Up Current (<1 mA)
Automatic Feed Forward Compensation
Pulse-by-Pulse Current Limiting
Enhanced Load Response Characteristics
Under-Voltage Lockout With Hysteresis
Double Pulse Suppression
High Current Totem Pole Output
Internally Trimmed Bandgap Reference
500-kHz Operation
Low RO Error Amp
The UC1842/3/4/5 family of control devices provides
the necessary features to implement off-line or
dc-to-dc fixed frequency current mode control
schemes with a minimal external parts count.
Internally implemented circuits include under-voltage
lockout featuring start up current less than 1 mA, a
precision reference trimmed for accuracy at the error
amp input, logic to insure latched operation, a PWM
comparator which also provides current limit control,
and a totem pole output stage designed to source or
sink high peak current. The output stage, suitable for
driving N-Channel MOSFETs, is low in the off state.
Differences between members of this family are the
under-voltage lockout thresholds and maximum duty
cycle ranges. The UC1842 and UC1844 have UVLO
thresholds of 16 VON and 10 VOFF, ideally suited to
off-line applications. The corresponding thresholds
for the UC1843 and UC1845 are 8.4 V and 7.6 V.
The UC1842 and UC1843 can operate to duty cycles
approaching 100%. A range of zero to 50% is
obtained by the UC1844 and UC1845 by the addition
of an internal toggle flip flop which blanks the output
off every other clock cycle.
BLOCK DIAGRAM
Vcc
7 12
UVLO
34 V
S/R
GROUND
5
9
5V
REF
8 14
VREF
5V
50 mA
2.50 V
Internal
BIAS
VREF
Good
Logic
4
7
RT/CT
OSC
Error
Amp
VFB
2
COMP 1
CURRENT
SENSE
3
7 11
VC
3
1
6 10
OUTPUT
T
S
2R
R
R
1V
CURRENT
SENSE
COMPARATOR
PWM
LATCH
5
8
POWER
GROUND
5
Note 1: A/B A = DIL−8 Pin Number. B = SO−14 and CFP−14 Pin Number.
Note 2:
Toggle flip flop used only in 1844 and 1845.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 1997–2007, Texas Instruments Incorporated
UC1842/3/4/5
UC2842/3/4/5
UC3842/3/4/5
www.ti.com
SLUS223C – APRIL 1997 – REVISED JUNE 2007
ABSOLUTE MAXIMUM RATINGS (1)
UNIT
Low impedance source
Supply voltage
30 V
ICC < 30 mA
Self Limiting
±1 A
Output current
5 µJ
Output energy (capacitive load)
Analog inputs (Pins 2, 3)
–0.3 V to 6.3 V
Error amp output sink current
10 mA
TA≤ 25°C (DIL-8)
1W
TA≤ 25°C (SOIC-14)
Power dissipation
725 mW
TA≤ 25°C (SOIC-8)
650 mW
Storage temperature range
–65°C to 150°C
Junction temperature range
–55°C to 150°C
Lead temperature (soldering, 10 seconds)
(1)
300°C
All voltages are with respect to Pin 5. All currents are positive into the specified terminal. Consult Packaging Section of Databook for
thermal limitations and considerations of packages.
CONNECTION DIAGRAMS
DIL-8, SOIC-8
N or J PACKAGE, D8 PACKAGE
(TOP VIEW)
7
3
6
4
5
VREF
VCC
OUTPUT
GROUND
SOIC-14, CFP-14
D or W PACKAGE
(TOP VIEW)
COMP
NC
VFB
NC
ISENSE
NC
RT/CT
1
2
3
4
5
6
7
14
13
12
11
10
9
8
VREF
NC
VCC
VC
OUTPUT
GROUND
PWR GND
3 2 1 20 19
NC
VFB
NC
4
18
5
6
17
16
ISENSE
NC
7
15
14
8
NC − No internal connection
2
NC
8
2
NC
COMP
NC
VREF
1
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9 10 11 12 13
NC
RT / CT
NC
PWR GND
GROUND
COMP
VFB
ISENSE
RT/CT
PLCC-20
Q PACKAGE
(TOP VIEW)
VCC
VC
NC
OUTPUT
NC
UC1842/3/4/5
UC2842/3/4/5
UC3842/3/4/5
www.ti.com
SLUS223C – APRIL 1997 – REVISED JUNE 2007
THERMAL CHARACTERISTICS
over operating free-air temperature range (unless otherwise noted)
θJC
θJA
J
28 (1)
125-160
N
25
110 (2)
SOIC-8
D8
42
84-160 (2)
SOIC-14
D14
35
50-120 (2)
CFP-14
W
5.49°C/W
175.4C/W
PLCC-20
Q
34
43-75 (2)
PACKAGE
DIL-8
(1)
(2)
θJC data values stated were derived from MIL-STD-1835B.
Specified θJA (junction to ambient) is for devices mounted to 5 in2 FR4 PC board with one ounce copper where noted. When resistance
range is given, lower values are for 5 in2. Test PWB was 0.062 in thick and typically used 0.635-mm trace widths for power packages
and 1.3-mm trace widths for non-power packages with 100 x 100-mil probe land area at the end of each trace.
DISSIPATION RATINGS
PACKAGE
TA≤ 25°C
POWER RATING
DERATING FACTOR
ABOVE TA≤ 25°C
TA≤ 70°C
POWER RATING
TA≤ 85°CPO
WER RATING
TA≤ 125°C
POWER RATING
W
700 mW
5.5 mW/°C
452 mW
370 mW
150 mW
ELECTRICAL CHARACTERISTICS
Unless otherwise stated, these specifications apply for –55°C ≤ TA≤ 125°C for the UC184X; –40°C ≤ TA≤ 85°C for the
UC284X; 0°C ≤ TA≤ 70°C for the 384X; VCC = 15 V (1); RT = 10 kΩ; CT = 3.3 nF, TA = TJ.
PARAMETER
TEST CONDITIONS
UC1842/3/4/5
UC2842/3/4/5
UC3842/3/4/5
UNIT
MIN
TYP
MAX
MIN
TYP
MAX
4.95
4.90
REFERENCE SECTION
Output Voltage
TJ = 25°C, IO = 1 mA
5.00
5.05
5.00
5.10
Line Regulation
12 ≤ VIN≤ 25 V
6
20
6
20
Load Regulation
1 ≤ I0≤ 20 mA
6
25
6
25
Temp. Stability
See
0.2
0.4
Total Output Variation
Line, load, tempature
Output Noise Voltage
10 Hz≤ f ≤ 10 kHz, TJ =
Long Term Stability
TA = 125°C, 1000 Hrs (2)
(2) (3)
(2)
Output Short Circuit
4.9
25°C (2)
5.1
0.2
4.82
50
–30
25
–100
–180
–30
52
57
47
0.2%
1%
mV
0.4
mV/°C
5.18
V
µV
50
5
V
5
25
mV
–100
–180
mA
52
57
kHz
0.2%
1%
OSCILLATOR SECTION
Initial Accuracy
TJ = 25°C (4)
Voltage Stability
12 ≤ VCC≤ 25 V
Temp. Stability
TMIN≤ TA≤ TMAX (2)
Amplitude
(1)
(2)
(3)
(4)
47
VPIN 4 peak-to-peak
(2)
5%
5%
1.7
1.7
V
Adjust VCC above the start threshold before setting at 15 V.
These parameters, although specified, are not 100% tested in production.
Temperature stability, sometimes referred to as average temperature coefficient, is described by the equation:
V
(max) * VREF (min)
Temp Stability + REF
TJ(max) * TJ (min)
VREF(max) and VREF(min) are the maximum and minimum reference voltages measured over
the appropriate temperature range. Note that the extremes in voltage do not necessarily occur at the extremes in temperature.
Output frequency equals oscillator frequency for the UC1842 and UC1843.
Output frequency is one half oscillator frequency for the UC1844 and UC1845.
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UC1842/3/4/5
UC2842/3/4/5
UC3842/3/4/5
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SLUS223C – APRIL 1997 – REVISED JUNE 2007
ELECTRICAL CHARACTERISTICS (continued)
Unless otherwise stated, these specifications apply for –55°C ≤ TA≤ 125°C for the UC184X; –40°C ≤ TA≤ 85°C for the
UC284X; 0°C ≤ TA≤ 70°C for the 384X; VCC = 15 V; RT = 10 kΩ; CT = 3.3 nF, TA = TJ.
PARAMETER
TEST CONDITIONS
UC1842/3/4/5
UC2842/3/4/5
UC3842/3/4/5
UNIT
MIN
TYP
MAX
MIN
TYP
MAX
2.45
2.50
2.55
2.42
2.50
2.58
V
–0.3
–1
–0.3
–2
µA
ERROR AMP SECTION
Input Voltage
VPIN
1
= 2.5 V
Input Bias Current
AVOL
2 ≤ VO≤ 4 V
Unity Gain Bandwidth
TJ = 25°C
PSRR
12 ≤ VCC≤ 25 V
Output Sink Current
VPIN 2 = 2.7 V, VPIN 1 = 1.1 V
Output Source Current
VPIN 2 = 2.3 V, VPIN 1 = 5 V
VOUT High
VPIN
2
= 2.3 V, RL = 15 kΩ to ground
VOUT Low
VPIN
2
= 2.7 V, RL = 15 kΩ to Pin 8
Gain
See
(6) (7)
Maximum Input Signal
VPIN
1= 5V
PSRR
12 ≤ VCC≤ 25 V
(5)
65
90
65
90
dB
0.7
1
0.7
1
MHz
60
70
60
70
dB
2
6
2
6
–0.5
–0.8
–0.5
–0.8
5
6
5
6
0.7
1.1
2.85
3
3.15
0.9
1
1.1
mA
V
0.7
1.1
2.85
3
3.15
V/V
0.9
1
1.1
V
CURRENT SENSE SECTION
(6)
(5) (6)
70
Delay to Output
70
dB
–2
–10
–2
–10
µA
150
300
150
300
ns
ISINK = 20 mA
0.1
0.4
0.1
0.4
ISINK = 200 mA
1.5
2.2
1.5
2.2
Input Bias Current
VPIN
3
= 0 V to 2 V
(5)
OUTPUT SECTION
Output Low Level
Output High Level
ISOURCE = 20 mA
ISOURCE = 200 mA
13
13.5
12
13.5
(5)
Rise Time
TJ = 25°C, CL = 1 nF
Fall Time
TJ = 25°C, CL = 1nF (5)
13
13.5
12
13.5
50
150
50
150
50
150
50
150
V
ns
UNDER-VOLTAGE LOCKOUT SECTION
Start Threshold
Min. Operating Voltage After
Turn On
X842/4
15
16
17
14.5
16
17.5
X843/5
7.8
8.4
9.0
7.8
8.4
9.0
X842/4
9
10
11
8.5
10
11.5
X843/5
7.0
7.6
8.2
7.0
7.6
8.2
X842/3
95%
97%
100%
95%
97%
100%
X844/5
46%
48%
50%
47%
48%
50%
V
PWM SECTION
Maximum Duty Cycle
Minimum Duty Cycle
0%
0%
TOTAL STANDBY CURRENT
Start-Up Current
Operating Supply Current
VPIN 2 = VPIN 3 = 0 V
VCC Zener Voltager
ICC = 25 mA
(5)
(6)
(7)
4
30
These parameters, although specified, are not 100% tested in production.
Parameter measured at trip point of latch with VPIN 2 = 0.
A + DVPIN 1 , 0 v VPIN 3 v 0.8 V
DVPIN 3
Gain defined as:
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0.5
1
0.5
1
11
17
11
17
34
30
34
mA
V
UC1842/3/4/5
UC2842/3/4/5
UC3842/3/4/5
www.ti.com
SLUS223C – APRIL 1997 – REVISED JUNE 2007
ERROR AMP CONFIGURATION
Error amp can source or sink up to 0.5 mA.
2.5 V
0.5 mA
+
VFB
ZI
_
2
COMP
ZF
1
UNDER-VOLTAGE LOCKOUT
During under-voltage lock-out, the output drive is biased to sink minor amounts of current. Pin 6 should be
shunted to ground with a bleeder resistor to prevent activating the power switch with extraneous leakage
currents.
VCC
VCC
7
ON/OFF Command
to REST of IC
UC1842
UC1844
UC1843
UC1845
VON
16 V
8.4 V
VOFF
10 V
7.6 V
<17 mA
<1 mA
VCC
VOFF
VON
CURRENT SENSE CIRCUIT
A small RC filter may be required to suppress switch transients.
ERROR
AMP
2R
IS
R
1
R
3
RS
COMP
CURRENT
SENSE
1V
CURRENT
SENSE
COMPARATOR
C
GND
5
5
Peak Current (IS) is Determined By The Formula
,1.0 V
ISMAX
RS
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UC1842/3/4/5
UC2842/3/4/5
UC3842/3/4/5
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SLUS223C – APRIL 1997 – REVISED JUNE 2007
OSCILLATOR SECTION
8
30
4
CT
GROUND
100
10
t d − ms
RT/CT
Timing Resistance vs Frequency
Deadtime vs CT (RT >5 kW)
RT
RT − (k W)
VREF
3
5
1
0.3
1
2.2
4.7
1.72
For RT> 5 K f ~
RTCT
10 22
CT − nF
47
30
10
3
100
100
1k
OUTPUT SATURATION CHARACTERISTICS
4
VCC = 15 V
Saturation Voltage − V
3
TA = 25°C
TA = −55°C
2
SOURCE SAT
(VCC − VOH)
1
SINK SAT (VOL)
0
.01
.02
.03 .04 .05
.07 .1
.2
.3 .4 .5
.7
1
Output Current, Source or Sink − A
80
0
60
−45
θ
40
−90
20
−135
Av
−180
0
100
1k
10 k
100 k
1M
f − Frequency − Hz
6
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10 M
Phase Margin − °
Voltage Gain − dB
ERROR AMPLIFIER OPEN-LOOP FREQUENCY RESPONSE
10
10 k
100 k
f − Frequency − Hz
1M
UC1842/3/4/5
UC2842/3/4/5
UC3842/3/4/5
www.ti.com
SLUS223C – APRIL 1997 – REVISED JUNE 2007
OPEN-LOOP LABORATORY FIXTURE
High peak currents associated with capacitive loads necessitate careful grounding techniques. Timing and bypas
capacitors should be conected close to pin 5 in a single point ground. The transistor and 5k potentiometer are
used to sample the oscillator waveform and apply an adjustable ramp to pin 3.
VREF
R1
2N2222
4.7 kW
100 kW
1 kW
ERROR AMP
ADJUST
5 kW
4.7 kW
ISENSE
ADJUST
A
UC1842
1
COMP
2
VFB
3
ISENSE
OUTPUT 6
4
RT / CT
GROUND 5
VREF
8
VCC
0.1 mF
VCC 7
0.1 mF
1 kW 1 W
OUTPUT
GROUND
CT
SHUTDOWN TECHNIQUES
Shutdown of the UC1842 can be accomplished by two methods; either raise pin 3 above 1 V or pull pin 1 below
a voltage two diode drops above ground. Either method causses the output of the PWM comparator to be high
(refer to block diagram). The PWM latch is reset dominant so that the output will remain low until the next clock
cycle after the shutdown condition at pin 1 and/or 3 is removed. In one example, an externally latched shutdown
may be accomplished by adding an SCR which will be reset by cycling VCC below the lower UVLO threshold. At
this pint the reference turns off, allowing the SCR to reset.
1 kW
8
VREF
3
ISENSE
1
COMP
SHUTDOWN
330 W
500 W
SHUTDOWN
To Current
SENSE RESISTOR
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UC1842/3/4/5
UC2842/3/4/5
UC3842/3/4/5
www.ti.com
SLUS223C – APRIL 1997 – REVISED JUNE 2007
OFFLINE FLYBACK REGULATOR
T1
R1
5Ω1W
117 VAC
D6
U9D946
L1
+6 V
VARO
VM 68
C9
3300 pF
600 V
R12
4.7 kΩ
2W
C1
250 µF
250 V
R2
56 kΩ
2W
N5
NP
C10
4700 µF
10 V
C11
4700 µF
10 V
COM
D4
1N3613
D7
UF81002
+12 V
R4
4.7 kΩ
D2
1N3612
R3
20 kΩ
D3
1N3612
C12
2200 µF
16 V
N12
N12
2
C2
100 µF
25 V
7
R5 150 kΩ
R9
68 Ω
3W
C3
22 µF
C4
47 µF
25 V
−12 V
NC
D8
UES1002
1
C14
UC3844
R7
22 Ω
100 pF
8
Q1
UFN833
6
R8
R6
10 kΩ
C5
0.01 µF
±12 V COM
C13
2200 µF
16 V
C8
680 pF
600 V
3
4
5
1 kΩ
USD1120
R13
20 kΩ
C7
470 pF
C6
0.0022 µF
R10
0.55 Ω
1W
D8
1N3613
R11
2.7 kΩ
2W
Power Supply Specifications
1. Input Voltages
a. 5VAC to 130VA (50 Hz/60 Hz)
2. Line Isolation: 3750 V
3. Switchng Frequency: 40 kHz
4. Efficiency at Full Load 70%
5. Output Voltage:
a. +5 V, ±5%; 1A to 4A load
Ripple voltage: 50 mV P-P Max
b. +12 V, ±3%; 0.1A to 0.3A load
Ripple voltage: 100 mV P-P Max
c. –12 V, ±3%; 0.1A to 0.3A load
Ripple voltage: 100 mV P-P Max
SLOPE COMPENSATION
A fraction of the oscillator ramp can be resistively summed with the current sense signal to provide slope
compensation for converters requiring duty cycles over 50%.
VREF
8
0.1 mF
RT / CT
RT
4
CT
UC1842/3
ISENSE
ISENSE
R1
R2
3
C
8
Submit Documentation Feedback
RSENSE
PACKAGE OPTION ADDENDUM
www.ti.com
28-May-2009
PACKAGING INFORMATION
Orderable Device
Status (1)
5962-8670401PA
5962-8670401XA
5962-8670402PA
5962-8670402XA
Pins Package Eco Plan (2)
Qty
Package
Type
Package
Drawing
ACTIVE
CDIP
JG
8
1
TBD
ACTIVE
LCCC
FK
20
1
TBD
ACTIVE
CDIP
JG
8
1
TBD
ACTIVE
LCCC
FK
20
1
TBD
5962-8670403PA
ACTIVE
CDIP
JG
8
1
TBD
Lead/Ball Finish
A42 SNPB
MSL Peak Temp (3)
N / A for Pkg Type
POST-PLATE N / A for Pkg Type
A42 SNPB
N / A for Pkg Type
POST-PLATE N / A for Pkg Type
A42 SNPB
N / A for Pkg Type
5962-8670403XA
ACTIVE
LCCC
FK
20
1
TBD
5962-8670404DA
ACTIVE
CFP
W
14
1
TBD
POST-PLATE N / A for Pkg Type
A42 SNPB
N / A for Pkg Type
5962-8670404PA
ACTIVE
CDIP
JG
8
1
TBD
A42 SNPB
N / A for Pkg Type
5962-8670404XA
ACTIVE
LCCC
FK
20
1
TBD
UC1842J
ACTIVE
CDIP
JG
8
1
TBD
A42 SNPB
N / A for Pkg Type
UC1842J883B
ACTIVE
CDIP
JG
8
1
TBD
A42 SNPB
N / A for Pkg Type
UC1842L883B
ACTIVE
LCCC
FK
20
1
TBD
UC1842W
ACTIVE
CFP
W
14
1
TBD
A42 SNPB
N / A for Pkg Type
UC1843J
ACTIVE
CDIP
JG
8
1
TBD
A42 SNPB
N / A for Pkg Type
UC1843J883B
ACTIVE
CDIP
JG
8
1
TBD
A42 SNPB
N / A for Pkg Type
UC1843L
ACTIVE
LCCC
FK
20
1
TBD
POST-PLATE N / A for Pkg Type
UC1843L883B
ACTIVE
LCCC
FK
20
1
TBD
POST-PLATE N / A for Pkg Type
UC1843W
ACTIVE
CFP
W
14
1
TBD
A42 SNPB
N / A for Pkg Type
POST-PLATE N / A for Pkg Type
POST-PLATE N / A for Pkg Type
UC1844J
ACTIVE
CDIP
JG
8
1
TBD
A42 SNPB
N / A for Pkg Type
UC1844J883B
ACTIVE
CDIP
JG
8
1
TBD
A42 SNPB
N / A for Pkg Type
UC1844L
ACTIVE
LCCC
FK
20
1
TBD
POST-PLATE N / A for Pkg Type
UC1844L883B
ACTIVE
LCCC
FK
20
1
TBD
POST-PLATE N / A for Pkg Type
UC1844W
ACTIVE
CFP
W
14
1
TBD
A42 SNPB
N / A for Pkg Type
UC1845J
ACTIVE
CDIP
JG
8
1
TBD
A42 SNPB
N / A for Pkg Type
UC1845J883B
ACTIVE
CDIP
JG
8
1
TBD
A42 SNPB
N / A for Pkg Type
UC1845L
ACTIVE
LCCC
FK
20
1
TBD
POST-PLATE N / A for Pkg Type
UC1845L883B
ACTIVE
LCCC
FK
20
1
TBD
POST-PLATE N / A for Pkg Type
UC1845W
ACTIVE
CFP
W
14
1
TBD
A42 SNPB
N / A for Pkg Type
UC1845W883B
ACTIVE
CFP
W
14
1
TBD
A42 SNPB
N / A for Pkg Type
UC2842D
ACTIVE
SOIC
D
14
50
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
UC2842D8
ACTIVE
SOIC
D
8
75
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
UC2842D8G4
ACTIVE
SOIC
D
8
75
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
UC2842D8TR
ACTIVE
SOIC
D
8
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
UC2842D8TRG4
ACTIVE
SOIC
D
8
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
UC2842DG4
ACTIVE
SOIC
D
14
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
UC2842DTR
ACTIVE
SOIC
D
14
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
UC2842DTRG4
ACTIVE
SOIC
D
14
2500 Green (RoHS &
CU NIPDAU
Level-1-260C-UNLIM
50
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
28-May-2009
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
UC2842DW
ACTIVE
SOIC
DW
16
40
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
UC2842DWG4
ACTIVE
SOIC
DW
16
40
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
UC2842J
OBSOLETE
CDIP
JG
8
TBD
Call TI
UC2842N
ACTIVE
PDIP
P
8
50
Green (RoHS &
no Sb/Br)
CU NIPDAU
N / A for Pkg Type
UC2842NG4
ACTIVE
PDIP
P
8
50
Green (RoHS &
no Sb/Br)
CU NIPDAU
N / A for Pkg Type
Lead/Ball Finish
MSL Peak Temp (3)
no Sb/Br)
Call TI
UC2842P
OBSOLETE
PDIP
P
8
TBD
Call TI
UC2843D
ACTIVE
SOIC
D
14
50
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
UC2843D8
ACTIVE
SOIC
D
8
75
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
UC2843D8G4
ACTIVE
SOIC
D
8
75
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
UC2843D8TR
ACTIVE
SOIC
D
8
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
UC2843D8TRG4
ACTIVE
SOIC
D
8
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
UC2843DG4
ACTIVE
SOIC
D
14
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
UC2843DTR
ACTIVE
SOIC
D
14
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
UC2843DTRG4
ACTIVE
SOIC
D
14
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
50
Call TI
UC2843J
OBSOLETE
CDIP
JG
8
TBD
Call TI
UC2843N
ACTIVE
PDIP
P
8
50
Green (RoHS &
no Sb/Br)
CU NIPDAU
N / A for Pkg Type
UC2843NG4
ACTIVE
PDIP
P
8
50
Green (RoHS &
no Sb/Br)
CU NIPDAU
N / A for Pkg Type
UC2844D
ACTIVE
SOIC
D
14
50
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
UC2844D8
ACTIVE
SOIC
D
8
75
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
UC2844D8G4
ACTIVE
SOIC
D
8
75
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
UC2844D8TR
ACTIVE
SOIC
D
8
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
UC2844D8TRG4
ACTIVE
SOIC
D
8
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
UC2844DG4
ACTIVE
SOIC
D
14
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
UC2844DTR
ACTIVE
SOIC
D
14
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
UC2844DTRG4
ACTIVE
SOIC
D
14
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
UC2844N
ACTIVE
PDIP
P
8
50
Green (RoHS &
no Sb/Br)
CU NIPDAU
N / A for Pkg Type
UC2844NG4
ACTIVE
PDIP
P
8
50
Green (RoHS &
CU NIPDAU
N / A for Pkg Type
50
Addendum-Page 2
Call TI
PACKAGE OPTION ADDENDUM
www.ti.com
28-May-2009
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
UC2845D
ACTIVE
SOIC
D
14
50
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
UC2845D8
ACTIVE
SOIC
D
8
75
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
UC2845D8G4
ACTIVE
SOIC
D
8
75
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
UC2845D8TR
ACTIVE
SOIC
D
8
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
UC2845D8TRG4
ACTIVE
SOIC
D
8
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
UC2845DG4
ACTIVE
SOIC
D
14
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
UC2845DTR
ACTIVE
SOIC
D
14
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
UC2845DTRG4
ACTIVE
SOIC
D
14
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
Lead/Ball Finish
MSL Peak Temp (3)
no Sb/Br)
50
UC2845J
OBSOLETE
CDIP
JG
8
TBD
Call TI
UC2845N
ACTIVE
PDIP
P
8
50
Green (RoHS &
no Sb/Br)
CU NIPDAU
N / A for Pkg Type
UC2845NG4
ACTIVE
PDIP
P
8
50
Green (RoHS &
no Sb/Br)
CU NIPDAU
N / A for Pkg Type
UC3842D
ACTIVE
SOIC
D
14
50
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
UC3842D8
ACTIVE
SOIC
D
8
75
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
UC3842D8G4
ACTIVE
SOIC
D
8
75
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
UC3842D8TR
ACTIVE
SOIC
D
8
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
UC3842D8TRG4
ACTIVE
SOIC
D
8
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
UC3842DG4
ACTIVE
SOIC
D
14
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
UC3842DTR
ACTIVE
SOIC
D
14
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
UC3842DTRG4
ACTIVE
SOIC
D
14
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
UC3842N
ACTIVE
PDIP
P
8
50
Green (RoHS &
no Sb/Br)
CU NIPDAU
N / A for Pkg Type
UC3842NG4
ACTIVE
PDIP
P
8
50
Green (RoHS &
no Sb/Br)
CU NIPDAU
N / A for Pkg Type
50
Call TI
UC3842P
OBSOLETE
PDIP
P
8
TBD
Call TI
UC3843D
ACTIVE
SOIC
D
14
50
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
UC3843D8
ACTIVE
SOIC
D
8
75
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
UC3843D8G4
ACTIVE
SOIC
D
8
75
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
UC3843D8TR
ACTIVE
SOIC
D
8
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
Addendum-Page 3
Call TI
PACKAGE OPTION ADDENDUM
www.ti.com
28-May-2009
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
UC3843D8TRG4
ACTIVE
SOIC
D
8
UC3843DG4
ACTIVE
SOIC
D
14
UC3843DTR
ACTIVE
SOIC
D
UC3843DTRG4
ACTIVE
SOIC
UC3843N
ACTIVE
UC3843NG4
2500 Green (RoHS &
no Sb/Br)
Lead/Ball Finish
MSL Peak Temp (3)
CU NIPDAU
Level-1-260C-UNLIM
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
14
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
D
14
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
PDIP
P
8
50
Green (RoHS &
no Sb/Br)
CU NIPDAU
N / A for Pkg Type
ACTIVE
PDIP
P
8
50
Green (RoHS &
no Sb/Br)
CU NIPDAU
N / A for Pkg Type
UC3843P
OBSOLETE
PDIP
P
8
TBD
Call TI
Call TI
UC3843QTR
OBSOLETE
PLCC
FN
20
TBD
Call TI
Call TI
UC3844D
ACTIVE
SOIC
D
14
50
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
UC3844D8
ACTIVE
SOIC
D
8
75
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
UC3844D8G4
ACTIVE
SOIC
D
8
75
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
UC3844D8TR
ACTIVE
SOIC
D
8
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
UC3844D8TRG4
ACTIVE
SOIC
D
8
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
UC3844DG4
ACTIVE
SOIC
D
14
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
UC3844DTR
ACTIVE
SOIC
D
14
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
UC3844DTRG4
ACTIVE
SOIC
D
14
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
UC3844N
ACTIVE
PDIP
P
8
50
Green (RoHS &
no Sb/Br)
CU NIPDAU
N / A for Pkg Type
UC3844NG4
ACTIVE
PDIP
P
8
50
Green (RoHS &
no Sb/Br)
CU NIPDAU
N / A for Pkg Type
50
50
UC3844P
OBSOLETE
PDIP
P
8
TBD
Call TI
UC3845AJ
ACTIVE
CDIP
JG
8
1
TBD
A42 SNPB
UC3845D
ACTIVE
SOIC
D
14
50
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
UC3845D8
ACTIVE
SOIC
D
8
75
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
UC3845D8G4
ACTIVE
SOIC
D
8
75
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
UC3845D8TR
ACTIVE
SOIC
D
8
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
UC3845D8TRG4
ACTIVE
SOIC
D
8
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
UC3845DG4
ACTIVE
SOIC
D
14
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
UC3845DTR
ACTIVE
SOIC
D
14
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
UC3845DTRG4
ACTIVE
SOIC
D
14
2500 Green (RoHS &
CU NIPDAU
Level-1-260C-UNLIM
50
Addendum-Page 4
Call TI
N / A for Pkg Type
PACKAGE OPTION ADDENDUM
www.ti.com
28-May-2009
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
UC3845N
ACTIVE
PDIP
P
8
50
Green (RoHS &
no Sb/Br)
CU NIPDAU
N / A for Pkg Type
UC3845NG4
ACTIVE
PDIP
P
8
50
Green (RoHS &
no Sb/Br)
CU NIPDAU
N / A for Pkg Type
UC3845P
OBSOLETE
PDIP
P
8
TBD
Call TI
Lead/Ball Finish
MSL Peak Temp (3)
no Sb/Br)
Call TI
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF UC1842, UC1843, UC1844, UC1845, UC3842, UC3843, UC3844, UC3845, UC3845AM :
UC3842M, UC3845A
• Catalog:
• Space: UC1842-SP, UC1843-SP, UC1844-SP, UC1845-SP
NOTE: Qualified Version Definitions:
- TI's standard catalog product
• Catalog
• Space - Radiation tolerant, ceramic packaging and qualified for use in Space-based application
Addendum-Page 5
PACKAGE MATERIALS INFORMATION
www.ti.com
19-Mar-2008
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
Diameter Width
(mm) W1 (mm)
A0 (mm)
B0 (mm)
K0 (mm)
P1
(mm)
W
Pin1
(mm) Quadrant
UC2842D8TR
SOIC
D
8
2500
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
UC2842DTR
SOIC
D
14
2500
330.0
16.4
6.5
9.0
2.1
8.0
16.0
Q1
UC2843D8TR
SOIC
D
8
2500
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
UC2843DTR
SOIC
D
14
2500
330.0
16.4
6.5
9.0
2.1
8.0
16.0
Q1
UC2844D8TR
SOIC
D
8
2500
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
UC2844DTR
SOIC
D
14
2500
330.0
16.4
6.5
9.0
2.1
8.0
16.0
Q1
UC2845D8TR
SOIC
D
8
2500
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
UC2845DTR
SOIC
D
14
2500
330.0
16.4
6.5
9.0
2.1
8.0
16.0
Q1
UC3842D8TR
SOIC
D
8
2500
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
UC3842DTR
SOIC
D
14
2500
330.0
16.4
6.5
9.0
2.1
8.0
16.0
Q1
UC3843D8TR
SOIC
D
8
2500
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
UC3843DTR
SOIC
D
14
2500
330.0
16.4
6.5
9.0
2.1
8.0
16.0
Q1
UC3844D8TR
SOIC
D
8
2500
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
UC3844DTR
SOIC
D
14
2500
330.0
16.4
6.5
9.0
2.1
8.0
16.0
Q1
UC3845D8TR
SOIC
D
8
2500
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
UC3845DTR
SOIC
D
14
2500
330.0
16.4
6.5
9.0
2.1
8.0
16.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
19-Mar-2008
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
UC2842D8TR
SOIC
UC2842DTR
SOIC
D
8
2500
340.5
338.1
20.6
D
14
2500
333.2
345.9
28.6
UC2843D8TR
SOIC
UC2843DTR
SOIC
D
8
2500
340.5
338.1
20.6
D
14
2500
333.2
345.9
UC2844D8TR
28.6
SOIC
D
8
2500
340.5
338.1
20.6
UC2844DTR
SOIC
D
14
2500
333.2
345.9
28.6
UC2845D8TR
SOIC
D
8
2500
340.5
338.1
20.6
UC2845DTR
SOIC
D
14
2500
333.2
345.9
28.6
UC3842D8TR
SOIC
D
8
2500
340.5
338.1
20.6
UC3842DTR
SOIC
D
14
2500
333.2
345.9
28.6
UC3843D8TR
SOIC
D
8
2500
340.5
338.1
20.6
UC3843DTR
SOIC
D
14
2500
333.2
345.9
28.6
UC3844D8TR
SOIC
D
8
2500
340.5
338.1
20.6
UC3844DTR
SOIC
D
14
2500
333.2
345.9
28.6
UC3845D8TR
SOIC
D
8
2500
340.5
338.1
20.6
UC3845DTR
SOIC
D
14
2500
333.2
345.9
28.6
Pack Materials-Page 2
MECHANICAL DATA
MLCC006B – OCTOBER 1996
FK (S-CQCC-N**)
LEADLESS CERAMIC CHIP CARRIER
28 TERMINAL SHOWN
18
17
16
15
14
13
NO. OF
TERMINALS
**
12
19
11
20
10
A
B
MIN
MAX
MIN
MAX
20
0.342
(8,69)
0.358
(9,09)
0.307
(7,80)
0.358
(9,09)
28
0.442
(11,23)
0.458
(11,63)
0.406
(10,31)
0.458
(11,63)
21
9
22
8
44
0.640
(16,26)
0.660
(16,76)
0.495
(12,58)
0.560
(14,22)
23
7
52
0.739
(18,78)
0.761
(19,32)
0.495
(12,58)
0.560
(14,22)
24
6
68
0.938
(23,83)
0.962
(24,43)
0.850
(21,6)
0.858
(21,8)
84
1.141
(28,99)
1.165
(29,59)
1.047
(26,6)
1.063
(27,0)
B SQ
A SQ
25
5
26
27
28
1
2
3
4
0.080 (2,03)
0.064 (1,63)
0.020 (0,51)
0.010 (0,25)
0.020 (0,51)
0.010 (0,25)
0.055 (1,40)
0.045 (1,14)
0.045 (1,14)
0.035 (0,89)
0.045 (1,14)
0.035 (0,89)
0.028 (0,71)
0.022 (0,54)
0.050 (1,27)
4040140 / D 10/96
NOTES: A.
B.
C.
D.
E.
All linear dimensions are in inches (millimeters).
This drawing is subject to change without notice.
This package can be hermetically sealed with a metal lid.
The terminals are gold plated.
Falls within JEDEC MS-004
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
MECHANICAL DATA
MPLC004A – OCTOBER 1994
FN (S-PQCC-J**)
PLASTIC J-LEADED CHIP CARRIER
20 PIN SHOWN
Seating Plane
0.004 (0,10)
0.180 (4,57) MAX
0.120 (3,05)
0.090 (2,29)
D
D1
0.020 (0,51) MIN
3
1
19
0.032 (0,81)
0.026 (0,66)
4
E
18
D2 / E2
E1
D2 / E2
8
14
0.021 (0,53)
0.013 (0,33)
0.007 (0,18) M
0.050 (1,27)
9
13
0.008 (0,20) NOM
D/E
D2 / E2
D1 / E1
NO. OF
PINS
**
MIN
MAX
MIN
MAX
MIN
MAX
20
0.385 (9,78)
0.395 (10,03)
0.350 (8,89)
0.356 (9,04)
0.141 (3,58)
0.169 (4,29)
28
0.485 (12,32)
0.495 (12,57)
0.450 (11,43)
0.456 (11,58)
0.191 (4,85)
0.219 (5,56)
44
0.685 (17,40)
0.695 (17,65)
0.650 (16,51)
0.656 (16,66)
0.291 (7,39)
0.319 (8,10)
52
0.785 (19,94)
0.795 (20,19)
0.750 (19,05)
0.756 (19,20)
0.341 (8,66)
0.369 (9,37)
68
0.985 (25,02)
0.995 (25,27)
0.950 (24,13)
0.958 (24,33)
0.441 (11,20)
0.469 (11,91)
84
1.185 (30,10)
1.195 (30,35)
1.150 (29,21)
1.158 (29,41)
0.541 (13,74)
0.569 (14,45)
4040005 / B 03/95
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-018
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1
MECHANICAL DATA
MCER001A – JANUARY 1995 – REVISED JANUARY 1997
JG (R-GDIP-T8)
CERAMIC DUAL-IN-LINE
0.400 (10,16)
0.355 (9,00)
8
5
0.280 (7,11)
0.245 (6,22)
1
0.063 (1,60)
0.015 (0,38)
4
0.065 (1,65)
0.045 (1,14)
0.310 (7,87)
0.290 (7,37)
0.020 (0,51) MIN
0.200 (5,08) MAX
Seating Plane
0.130 (3,30) MIN
0.023 (0,58)
0.015 (0,38)
0°–15°
0.100 (2,54)
0.014 (0,36)
0.008 (0,20)
4040107/C 08/96
NOTES: A.
B.
C.
D.
E.
All linear dimensions are in inches (millimeters).
This drawing is subject to change without notice.
This package can be hermetically sealed with a ceramic lid using glass frit.
Index point is provided on cap for terminal identification.
Falls within MIL STD 1835 GDIP1-T8
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
MECHANICAL DATA
MPDI001A – JANUARY 1995 – REVISED JUNE 1999
P (R-PDIP-T8)
PLASTIC DUAL-IN-LINE
0.400 (10,60)
0.355 (9,02)
8
5
0.260 (6,60)
0.240 (6,10)
1
4
0.070 (1,78) MAX
0.325 (8,26)
0.300 (7,62)
0.020 (0,51) MIN
0.015 (0,38)
Gage Plane
0.200 (5,08) MAX
Seating Plane
0.010 (0,25) NOM
0.125 (3,18) MIN
0.100 (2,54)
0.021 (0,53)
0.015 (0,38)
0.430 (10,92)
MAX
0.010 (0,25) M
4040082/D 05/98
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-001
For the latest package information, go to http://www.ti.com/sc/docs/package/pkg_info.htm
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
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