UC1845A-EP

UC1845A-EP
SGLS134C − SEPTEMBER 2002 − REVISED FEBRUARY 2006
D Controlled Baseline
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
− One Assembly/Test Site, One Fabrication
Site
Extended Temperature Performance of
−55°C to 125°C
Enhanced Diminishing Manufacturing
Sources (DMS) Support
Enhanced Product Change Notification
Qualification Pedigree†
Optimized for Off-line and DC-to-DC
Converters
Low Start Up Current (<0.5 mA)
Trimmed Oscillator Discharge Current
Automatic Feed Forward Compensation
Pulse-by-Pulse Current Limiting
Enhanced Load Response Characteristics
Under-Voltage Lockout With Hysteresis
Double Pulse Suppression
High Current Totem Pole Output
Internally Trimmed Bandgap Reference
500 kHz Operation
Low RO Error Amp
D PACKAGE
(TOP VIEW)
† Component qualification in accordance with JEDEC and industry
standards to ensure reliable operation over an extended
temperature range. This includes, but is not limited to, Highly
Accelerated Stress Test (HAST) or biased 85/85, temperature
cycle, autoclave or unbiased HAST, electromigration, bond
intermetallic life, and mold compound life. Such qualification
testing should not be viewed as justifying use of this component
beyond specified performance and environmental limits.
COMP
VFB
1
8
2
7
ISENSE
RT/CT
3
6
4
5
VREF
VCC
OUTPUT
GND
description
The UC1842A/3A/4A/5A family of control ICs is a pin-for-pin compatible improved version of the UC3842/3/4/5
family. Providing the necessary features to control current mode switched mode power supplies, this family has
the following improved features. Start up current is guaranteed to be less than 0.5 mA. Oscillator discharge is
trimmed to 8.3 mA. During under voltage lockout, the output stage can sink at least 10 mA at less than 1.2 V
for VCC over 5 V.
The difference between members of this family are shown in the table below.
PART NUMBER
UVLO ON
UVLO OFF
MAXIMUM DUTY CYCLE
UC1842A
16 V
10 V
<100%
UC1843A
8.5 V
7.9 V
<100%
UC1844A
16 V
10 V
<50%
UC1845A
8.5 V
7.9 V
<50%
ORDERING INFORMATION‡
PACKAGE‡
TA
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
−55°C to 125°C
SOP − D
Tape and reel
UC1842AMDREP
1842AME
−55°C to 125°C
SOP − D
Tape and reel
UC1843AMDREP
1843AME
−55°C to 125°C
SOP − D
Tape and reel
UC1844AMDREP
1844AME
−55°C to 125°C
SOP − D
Tape and reel
UC1845AMDREP
1845AME
‡ Package drawings, standard packing quantities, thermal data, symbolization, and PCB design
guidelines are available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright  2006, Texas Instruments Incorporated
!"# $"%&! '#(
'"! ! $#!! $# )# # #* "#
'' +,( '"! $!#- '# #!#&, !&"'#
#- && $##(
POST OFFICE BOX 655303
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1
SGLS134C − SEPTEMBER 2002 − REVISED FEBRUARY 2006
block diagram
NOTES: 1. Toggle flip flop used only in 1844A and 1845A.
Ordering Information
UC 184
4
A
M
D
R
EP
ENHANCED PLASTIC INDICATOR
TAPE and REEL INDICATOR
PACKAGE
D = Plastic SOIC
MILITARY TEMPERATURE RANGE INDICATOR
IMPROVED PERFORMANCE INDICATOR
PRODUCT OPTION
2 through 5
2
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SGLS134C − SEPTEMBER 2002 − REVISED FEBRUARY 2006
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†‡
VCC voltage (low impedance source) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 V
VCC voltage (ICC mA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . self limiting
Output current, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±1 A
Output energy (capacitive load) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 µJ
Analog Inputs (pins 2, 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 6.3 V
Error Amp Output Sink current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 mA
Power Dissipation at TA < 25_C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 W
Package thermal impedance, θJA (see Note 1): . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65_C to 150_C
Lead temperature soldering 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . 260_C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
‡ Unless otherwise indicated, voltages are reference to ground and currents are positive into and negative out of the specified terminals.
NOTE 1: Long term high-temperature storage and/or extended use at maximum recommended operating conditions may result in a reduction
of overall device life. See http://www.ti.com/ep_quality for additional information on enhanced plastic packaging.
electrical characteristics, TA = −55_C to 125_C for the UC184xAM-EP, VCC = 15 V (see Note 1),
RT = 10 kΩ, CT = 3.3 nF, and TA = TJ (unless otherwise stated)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
Reference Section
Output voltage
TJ = 25_C, IO = 1 mA
Line regulation voltage
Load regulation voltage
Temperature stability
See Notes NO TAG and NO TAG
Total output variation voltage
Line, Load, Temp.
Output noise voltage
f = 10 Hz to 10 kHz,
See Note NO TAG
TJ = 25_C
Long term stability
1000 hours, See Note 2
TA = 125_C
4.95
5
5.05
VIN = 12 V to 25 V
6
20
mV
IO = 1 mA to 20 mA
6
25
mV
0.2
0.4
mV/_C
5.1
V
4.9
Output short-circuit current
V
µV
50
5
25
mV
−30
−100
−180
mA
47
52
57
kHz
0.2%
1%
Oscillator Section
Initial accuracy
See Note NO TAG
TJ = 25_C
Voltage stability
VCC = 12 V to 25 V
Temperature stability
TA = MIN to MAX, See Note 2
5%
Amplitude peak-to-peak
V pin 4,
1.7
Discharge current
V pin 4 = 2 V, See Note 3
See Note 2
TJ = 25_C
7.8
TJ = Full range
7.5
8.3
V
8.8
8.8
mA
NOTES: 1. Adjust VCC above the start threshold before setting at 15 V.
2. Not production tested.
3. This parameter is measured with RT = 10 kΩ to VREF. This contributes approximately 300 µA of current to the measurement. The
total current flowing into the RT/C pin will be approximately 300 µA higher than the measured value.
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3
SGLS134C − SEPTEMBER 2002 − REVISED FEBRUARY 2006
electrical characteristics, TA = −55_C to 125_C for the UC184xAM-EP, VCC = 15 V (see Note 1),
RT = 10 kΩ, CT = 3.3 nF, and TA = TJ (unless otherwise stated)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
Error Amplifier Section
Input voltage
COMP = 2.5 V
2.45
Input bias current
Open loop voltage gain (AVOL)
VO = 2 V to 4 V
Unity gain bandwidth
See Note 2
PSRR
VCC = 12 V to 25 V
Output sink current
FB = 2.7 V, COMP = 1.1 V
Output source current
FB = 2.3 V, COMP = 5 V
VOUT high
FB = 2.3 V, RL = 15 kΩ to GND
VOUT low
FB = 2.7 V, RL = 15 kΩ to VREF
TJ = 25_C
2.5
2.55
V
−0.3
−1
µA
65
90
dB
0.7
1
MHz
60
70
dB
2
6
mA
−0.5
−0.8
mA
5
6
V
0.7
1.1
V
2.85
3
3.15
V/V
0.9
1
1.1
V
Current Sense Section
Gain
See Note 3 and Note 4
Maximum input signal
COMP = 5 V, See Note 3
PSRR
VCC = 12 V to 25 V,See Note 3
70
−2
−10
µA
ISENSE = 0 V to 2 V, See Note 2
150
300
ns
IOUT = 20 mA
0.1
0.4
IOUT = 200 mA
15
2.2
Input bias current
Delay to output
dB
Output Section (OUT)
Low-level output voltage
High-level output voltage
IOUT = −20 mA
13
13.5
IOUT = −200 mA
12
13.5
V
V
Rise time
CL = 1 nF, See Note 2
TJ = 25_C
50
150
ns
Fall time
CL = 1 nF, See Note 2
TJ = 25_C
50
150
ns
UVLO saturation
VCC = 5 V, IOUT = 10 mA
0.7
1.2
V
Undervoltage Lockout Section
Start threshold
Minimum operation voltage after turn on
NOTES: 1.
2.
3.
4.
4
UC1842A,
UC1844A
15
16
17
UC1843A,
UC1845A
7.8
8.4
9
UC1842A,
UC1844A
9
10
11
UC1843A,
UC1845A
7
7.6
8.2
Adjust VCC above the start threshold before setting at 15 V.
Not production tested.
Parameter measured at trip point of latch with VFB at 0 V.
Gain is defined by:
DVCOMP ; 0 v VSENSE v 0.8 V.
A=
DVSENSE
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
V
V
SGLS134C − SEPTEMBER 2002 − REVISED FEBRUARY 2006
electrical characteristics, TA = −55_C to 125_C for the UC184xAM-EP, VCC = 15 V (see Note 1),
RT = 10 kΩ, CT = 3.3 nF, and TA = TJ (unless otherwise stated)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
PWM Section
Maximum duty cycle
UC1842A, UC1843A
94%
96%
100%
UC1844A, UC1845A
47%
48%
50%
Minimum duty cycle
0%
Total Standby Current
Start-up current
Operating supply current
FB = 0 V, SENSE = 0 V
VCC internal zener voltage
ICC = 25 mA
NOTES: 1. Adjust VCC above the start threshold before setting at 15 V.
30
0.3
0.5
mA
11
17
mA
34
V
PARAMETER MEASUREMENT INFORMATION
Error Amp can source and sink up to 0.5 mA and sink up to 2 mA.
Figure 1. Error Amp Configuration
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5
SGLS134C − SEPTEMBER 2002 − REVISED FEBRUARY 2006
PARAMETER MEASUREMENT INFORMATION
During UVLO, the Output is low.
Figure 2. Under Voltage Lockout
Peak Current (Is) is determined by the following formula:
IsmaxȀ 1V
RS
A small RC filter may be required to suppress switch transients.
Figure 3. Current Sense Circuit
6
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SGLS134C − SEPTEMBER 2002 − REVISED FEBRUARY 2006
PARAMETER MEASUREMENT INFORMATION
Error Amplifier Open-Loop Frequency Response
Output Saturation Characteristics
Figure 5
Figure 4
APPLICATION INFORMATION
Oscillator Frequency vs Timing Resistance
Maximum Duty Cycle vs Timing Resistor
Figure 6. Oscillator
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7
SGLS134C − SEPTEMBER 2002 − REVISED FEBRUARY 2006
APPLICATION INFORMATION
High peak currents associated with capacitive loads necessitate careful grounding techniques. Timing and bypass capacitors should be
connected close to pin 5 in a single point ground. The transistor and 5k potentiometer are used to sample the oscillator waveform and apply an
adjustable ramp to pin 3.
Figure 7. Open-Loop Laboratory Text Fixture
A fraction of the oscillator ramp can be resistively summed
with the current sense signal to provide slope compensation
for converters requiring duty cycles over 50%.
Note that capacitor, C, forms a filter with R2 to suppress the
leading edge switch spikes.
Figure 8. Slope Compression
8
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SGLS134C − SEPTEMBER 2002 − REVISED FEBRUARY 2006
APPLICATION INFORMATION
Power Supply Specifications
1.
2.
3.
4.
5.
Input Voltage
95VAC to 130VAC (50 Hz/60 Hz)
Line Isolation
3750 V
Switching Frequency 40 kHz
Efficiency, Full Load
70%
Output Voltage:
A. +5V, ±5%; 1A to 4A Load
B. +12V, ±3%; 0.1A to 0.3A Load Ripple voltage: 100 mV P-P Max
C. −12V, ±3%; 0.1A to 0.3A Load Ripple voltage: 100 mV P-P Max
Figure 9. Off-Line Flyback Regulator
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9
PACKAGE OPTION ADDENDUM
www.ti.com
8-Jun-2009
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
UC1842AMDREP
ACTIVE
SOIC
D
8
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
UC1843AMDREP
ACTIVE
SOIC
D
8
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
UC1843AMDREPG4
ACTIVE
SOIC
D
8
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
UC1844AMDREP
ACTIVE
SOIC
D
8
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
UC1845AMDREP
ACTIVE
SOIC
D
8
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
V62/03625-01YE
ACTIVE
SOIC
D
8
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
V62/03625-02YE
ACTIVE
SOIC
D
8
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
V62/03625-03YE
ACTIVE
SOIC
D
8
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
V62/03625-04YE
ACTIVE
SOIC
D
8
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
Lead/Ball Finish
MSL Peak Temp (3)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF UC1842A-EP, UC1843A-EP, UC1844A-EP, UC1845A-EP :
• Catalog: UC1842A, UC1843A, UC1844A, UC1845A
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
8-Jun-2009
• Space: UC1842A-SP, UC1843A-SP, UC1844A-SP, UC1845A-SP
NOTE: Qualified Version Definitions:
- TI's standard catalog product
• Catalog
Space
Radiation tolerant, ceramic packaging and qualified for use in Space-based application
•
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
21-Apr-2009
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
Diameter Width
(mm) W1 (mm)
A0 (mm)
B0 (mm)
K0 (mm)
P1
(mm)
W
Pin1
(mm) Quadrant
UC1842AMDREP
SOIC
D
8
2500
330.0
12.4
6.4
5.2
2.1
4.0
12.0
Q1
UC1843AMDREP
SOIC
D
8
2500
330.0
12.4
6.4
5.2
2.1
4.0
12.0
Q1
UC1844AMDREP
SOIC
D
8
2500
330.0
12.4
6.4
5.2
2.1
4.0
12.0
Q1
UC1845AMDREP
SOIC
D
8
2500
330.0
12.4
6.4
5.2
2.1
4.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
21-Apr-2009
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
UC1842AMDREP
SOIC
D
8
2500
367.0
367.0
35.0
UC1843AMDREP
SOIC
D
8
2500
367.0
367.0
35.0
UC1844AMDREP
SOIC
D
8
2500
367.0
367.0
35.0
UC1845AMDREP
SOIC
D
8
2500
367.0
367.0
35.0
Pack Materials-Page 2
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