TLC5951

TLC5951 www.ti.com

.........................................................................................................................................................

SBVS127A – MARCH 2009 – REVISED APRIL 2009

24-Channel, 12-Bit PWM LED Driver with 7-Bit Dot Correction and 3-Group, 8-Bit Global Brightness Control

1

FEATURES

23

•

24-Channel Constant-Current Sink Output

•

Current Capability: 40 mA

•

Selectable Grayscale (GS) Control with PWM:

12-Bit (4096 Step), 10-Bit (1024 Step), 8-Bit

(256 Step)

•

Three Independent Grayscale Clocks for Three

Color Groups

•

Dot Correction (DC): 7-Bit (128 Step)

•

Global Brightness Control (BC) for Each Color

Group: 8-Bit (256 Step)

•

Auto Display Repeat Function

•

Independent Data Port for GS and BC/DC Data

•

Communication Path Between Each Data Port

•

LED Power-Supply Voltage up to 15 V

•

V

CC

= 3.0 V to 5.5 V

•

Constant-Current Accuracy:

– Channel-to-Channel = ±1.5%

– Device-to-Device = ±3%

•

CMOS Logic Level I/O

•

Data Transfer Rate: 30 MHz

¼

•

33-MHz Grayscale Control Clock

•

Continuous Base LED Open Detection (LOD)

•

Continuous Base LED Short Detection (LSD)

•

Thermal Shutdown (TSD) with Auto Restart

•

Grouped Delay to Prevent Inrush Current

•

Operating Air Temperature: –40°C to +85°C

•

Packages: HTSSOP-38, QFN-40

APPLICATIONS

•

Full-Color LED Displays

•

LED Signboards

DESCRIPTION

The TLC5951 is a 24-channel, constant-current sink driver. Each channel has an individually-adjustable,

4096-step, pulse width modulation (PWM) grayscale

(GS) brightness control and 128 step constant-current dot correction (DC). The dot correction adjusts brightness deviation between channels and other

LED drivers. The output channels are grouped into three groups of eight channels. Each channel group has a 256-step global brightness control (BC) function and an individual grayscale clock input.

VLED

¼ ¼

Controller

GSSIN

GSSCK

GSLAT

DCSIN

DCSCK

XBLNK

GSCKR

GSCKG

GCCKB

FLAGS

READ

R

IREF

¼

OUTR0/G0/B0

¼

OUTR7/G7/B7

GSSIN

GSSCK

GSSOUT

GSLAT

DCSIN

DCSCK

XBLNK

GSCKR

GSCKG

GSCKB

IREF

TLC5951

IC1

DCSOUT

VCC

GND

VCC

¼

7

R

IREF

¼

OUTR0/G0/B0

¼

OUTR7/G7/B7

GSSIN

GSSCK

GSSOUT

GSLAT

DCSIN

DCSCK

XBLNK

GSCKR

GSCKG

GSCKB

IREF

TLC5951

ICn

DCSOUT

VCC

GND

VCC

Typical Application Circuit (Multiple Daisy-Chained TLC5951s)

1

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2

PowerPAD is a trademark of Texas Instruments, Incorporated.

3

All other trademarks are the property of their respective owners.

UNLESS OTHERWISE NOTED this document contains

PRODUCTION DATA information current as of publication date.

Products conform to specifications per the terms of Texas

Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

Copyright © 2009, Texas Instruments Incorporated

TLC5951

SBVS127A – MARCH 2009 – REVISED APRIL 2009 .........................................................................................................................................................

www.ti.com

DESCRIPTION (CONTINUED)

GS, DC, and BC data are accessible via a serial interface port. DC and BC can be programmed via a dedicated serial interface port.

The TLC5951 has three error detection circuits for LED open detection (LOD), LED short detection (LSD), and thermal error flag (TEF). LOD detects a broken or disconnected LED while LSD detects a shorted LED. TEF indicates an over-temperature condition.

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

ORDERING INFORMATION

(1)

PRODUCT

TLC5951

TLC5951

PACKAGE-LEAD

HTSSOP-38 PowerPAD™

6 mm × 6 mm QFN-40

(2)

ORDERING NUMBER

TLC5951DAPR

TLC5951DAP

TLC5951RHAR

TLC5951RHAT

TRANSPORT MEDIA,

QUANTITY

Tape and Reel, 2000

Tube, 40

Tape and Reel, 2500

Tape and Reel, 250

(1) For the most current package and ordering information see the Package Option Addendum at the end of this document, or see the TI web site at www.ti.com

.

(2) Product preview device.

ABSOLUTE MAXIMUM RATINGS

(1) (2)

Over operating free-air temperature range, unless otherwise noted.

V

CC

I

OUT

V

IN

V

OUT

T

J(max)

T

STG

Supply voltage

Output current (dc)

PARAMETER

VCC

OUTR0 to R7, OUTG0 to G7, OUTB0 to B7

Input voltage range

GSSIN, GSSCK, GSLAT, GSCKR, GSCKG,

GSCKB, DCSIN, DCSCK, XBLNK, IREF

GSSOUT, DCSOUT

Output voltage range

OUTR0 to 7, OUTG0 to 7, OUTB0 to 7

Operation junction temperature

Storage temperature

ESD rating

Human body model (HBM)

Charged device model (CDM)

TLC5951

–0.3 to +6.0

50

–0.3 to V

CC

+ 0.3

–0.3 to V

CC

+ 0.3

–0.3 to +16

+150

–55 to +150

2000

500

UNIT

V mA

V

V

V

°C

°C

V

V

(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating

conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) All voltage values are with respect to network ground terminal.

2

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Product Folder Link(s):

TLC5951



.........................................................................................................................................................


DISSIPATION RATINGS

DERATING FACTOR

ABOVE T

A

= +25°C PACKAGE

HTSSOP-38 with

PowerPAD soldered

(1)

HTSSOP-38 with

PowerPAD not soldered

(2)

QFN-40

(3)

38.8 mW/°C

19.9 mW/°C

26.7 mW/°C

T

A

< +25°C

POWER RATING

4845 mW

2490 mW

T

A

= +70°C

POWER RATING

3101 mW

1594 mW

T

A

= +85°C

POWER RATING

2519 mW

1295 mW

3342 mW 2139 mW 1738 mW

(1) With PowerPAD soldered onto copper area on printed circuit board (PCB); 2-oz. copper. For more information, see SLMA002 (available for download at www.ti.com

).

(2) With PowerPAD not soldered onto copper area on PCB.

(3) The package thermal impedance is calculated in accordance with JESD51-5.

RECOMMENDED OPERATING CONDITIONS

At T

A

= –40°C to +85°C, unless otherwise noted.

I

V

IH

V

IL

I

OH

I

OL

PARAMETER

DC CHARACTERISTICS: V

CC

= 3 V to 5.5 V

V

CC

Supply voltage

V

O

Voltage applied to output

OUTR0-OUTR7, OUTG0-OUTG7,

OUTB0-OUTB7

OLC

High level input voltage

Low level input voltage

High level output current

Low level output current

Constant output sink current

GSSOUT, DCSOUT

GSSOUT, DCSOUT

OUTR0-OUTR7, OUTG0-OUTG7,

OUTB0-OUTB7

T

T

A

J

Operating free-air temperature

Operating junction temperature

AC CHARACTERISTICS, V

CC

= 3V to 5.5V

f

CLK (SCK)

Data shift clock frequency f

CLK

(GSCKR/G/B)

T

WH0

/T

WL0

Grayscale clock frequency

T

WH1

/T

WL1

T

WL2

T

SU0

T

SU1

T

SU2

Pulse duration

GSSCK, DCSCK

GSCKR, GSCKG, GSCKB

GSSCK, DCSCK

GSLAT

XBLNK

GSSIN – GSSCK

XBLNK

↑, DCSIN – DCSCK↑

↑ – GSCKR↑, GSCKG↑, or GSCKB↑

T

T

SU3

SU4

Setup time

GSLAT ↑ – GSSCK↑

GSLAT ↑ for GS data – GSCKR↑, GSCKG↑, or GSCKB ↑ when display timing reset mode is disabled

GSLAT ↑ for GS data – GSCKR↑, GSCKG↑, or GSCKB ↑ when display timing reset mode is enabled

T

H0

T

H1

T

H2

Hold time

GSSIN – GSSCK ↑, DCSIN – DCSCK↑

GSLAT ↑ – GSSCK↑

GSLAT ↓ – GSSCK↑

MIN

3.0

0.7 × V

CC

GND

–40

–40

5

10

150

10

30

30

40

100

5

35

5

TLC5951

NOM MAX

5.5

15

V

CC

0.3 × V

CC

–1

1

40

+85

+125

30

33

UNIT

°C

°C ns ns ns ns ns

MHz

MHz ns ns ns ns ns ns

V

V

V

V mA mA mA



TLC5951


3

TLC5951


www.ti.com

ELECTRICAL CHARACTERISTICS

At T

A

V

CC

= –40°C to +85°C, V

= 3.3 V.

CC

= 3 V to 5.5 V, and V

LED

= 5 V, unless otherwise noted. Typical values are at T

A

= +25°C and

V

OH

V

OL

I

I

I

CC1

I

CC2

I

CC3

I

CC4

I

OLC

I

OLKG

ΔI

OLC

PARAMETER TEST CONDITIONS

High level output voltage At GSSOUT, DCSOUT, I

OH

= –1 mA

Low level output voltage At GSSOUT, DCSOUT, I

OL

= 1 mA

Input current

Supply current

At GSSCK, GSLAT, DCSIN, DCSCK, GSCKR/G/B with V

I

At GSSIN, GSSCK, GSLAT, DCSIN, XBLNK, DCSCK,

GSCKR/G/B with V

I

= GND

= V

CC

,

GSSIN, GSSCK, GSLAT, DCSIN, DCSCK = low, XBLNK = low,

GSCKR/G/B = low, V

OUTRn/Gn/Bn

= 1 V, BCR/G/B = FFh,

DCRn/Gn/Bn = 7Fh with DC high adjustment range,

R

IREF

= 24 k Ω (I

OUTRn/Gn/Bn

= 2 mA target)

GSSIN, GSSCK, GSLAT, DCSIN, DCSCK = low, XBLNK = low,

GSCKR/G/B = low, V

OUTRn/Gn/Bn

= 1 V, BCR/G/B = FFh,


R

IREF

= 2.4 k Ω (I

OUTRn/Gn/Bn

= 20 mA target)

GSSIN, GSSCK, GSLAT, DCSIN, DCSCK = low, XBLNK = high,

GSCKR/G/B = 33 MHz, V

OUTRn/Gn/Bn

= 1 V,

GSRn/Gn/Bn = FFFh, BCR/G/B = FFh,


R

IREF

= 2.4 k Ω (I

OUTRn/Gn/Bn

= 20 mA target), auto repeat on

GSSIN, GSSCK, GSLAT, DCSIN, DCSCK = low, XBLNK = high,

GSCKR/G/B = 33 MHz, V

OUTRn/Gn/Bn

= 1 V,

GSRn/Gn/Bn = FFFh, BCR/G/B = FFh,


R

IREF

= 1.2 k Ω (I

OUTRn/Gn/Bn

= 40 mA target), auto repeat on

Constant output current

Leakage output current

Constant-current error

(channel-to-channel in same color group)

(1)

At OUTR0-OUTR7, OUTG0-OUTG7, OUTB0-OUTB7,

All OUTRn/Gn/Bn = on, BCR/G/B = FFh,


V

OUTRn/Gn/Bn

R

IREF

= 1.2 k

= 1 V, V

Ω (I

OUTfix

OUTRn/Gn/Bn

= 1 V,

= 40 mA target)

At OUTR0-OUTR7, OUTG0-OUTG7 and OUTB0-OUTB7,

XBLNK = low, V

OUTRn/Gn/Bn

= V

OUTfix

= 15 V, R

IREF

= 1.2 k Ω




V

OUTRn/Gn/Bn

R

IREF

= 1 V, V

OUTfix

= 1.2 k

Ω (I

OUTRn/Gn/Bn

= 1 V,

= 40 mA target)

MIN

V

CC

– 0.4

–1

35

TLC5951

TYP

1

6

12

21

40

±1.5

MAX

V

CC

0.4

1

3

10

27

55

45

0.1

±4

UNIT

V

V

µ

A mA mA mA mA mA

µ

A

%

(1) The deviation of each output in the same color group from the average of the same color group (OUTR0-OUTR7, OUTG0-OUTG7, or

OUTB0-OUTB7) constant current. The deviation is calculated by the formula (X = R, G, or B; n = 0-7):

I

OUTXn

(N = 0-7)

D

(%) =

-

1

´

100

(I

OUTX0

+ I

OUTX1

+ ... + I

OUTX6

+ I

OUTX7

)

8

4



TLC5951



.........................................................................................................................................................


ELECTRICAL CHARACTERISTICS (continued)

At T

A

V

CC

= –40°C to +85°C, V

= 3.3 V.

CC

= 3 V to 5.5 V, and V

LED

= 5 V, unless otherwise noted. Typical values are at T

A

= +25°C and

MIN

TLC5951

TYP MAX UNIT

ΔI

OLC1

ΔI

OLC2

ΔI

OLC3

ΔI

OLC4

T

TEF

T

HYS

V

LOD

V

LSD

V

IREF

R

PDWN

PARAMETER

Constant current error

(color group to color group in same device)

Constant current error

(device to device)

Line regulation

Load regulation

(4)

(5)

(2)

(3)

TEST CONDITIONS




V

OUTRn/Gn/Bn

R

IREF

= 1.2 k

= 1 V, V

Ω (I

OUTfix

OUTRn/Gn/Bn

= 1 V,

= 40 mA target)




V

OUTRn/Gn/Bn

R

IREF

= 1.2 k

= 1 V, V

Ω (I

OUTfix

OUTRn/Gn/Bn

= 1 V,

= 40 mA target)




V

OUTRn/Gn/Bn

R

IREF

= 1 V, V

OUTfix

= 1.2 k Ω (I

OUTRn/Gn/Bn

= 1 V,

= 40 mA target)




V

OUTRn/Gn/Bn

R

IREF

= 1.2 k

= 1 V, V

Ω (I

OUTfix

OUTRn/Gn/Bn

= 1 V,

= 40 mA target)

Thermal error flag threshold

(6)

Thermal error flag hysteresis

(6)

Junction temperature

Junction temperature

LED open detection threshold

LED short detection threshold

All OUTRn/Gn/Bn = on

All OUTRn/Gn/Bn = on

Reference voltage output R

IREF

= 1.2 k Ω

Pull-down resistor At XBLNK, GSSIN

150

5

0.20

2.4

1.17

250

±1

±1

±0.5

±1

163

10

0.25

2.5

1.20

500

±3

±6

±2

±3

175

20

0.30

2.6

1.23

750

%

%

%/V

%/V

°C

°C

V

V

V k

Ω

(2) The deviation of each color group in the same device from the average of all constant current. The deviation is calculated by the formula

(X = R, G, or B):

(I

OUTX0

+ I

OUTX1

+ ... + I

OUTX6

+ I

OUTX7

)

D

(%) =

8

(I

OUTR0

+ +I

¼

OUTR 7

+ I

OUTG0

+ +I

¼

OUTG 7

+ I

OUTB0

+ +I

¼

OUTB 7

)

24

-

1

´

100

(3) The deviation of the all constant-current average from the ideal constant-current value. The deviation is calculated by the formula:

(I

OUTR0

+ +

¼

I

OUTR7

+ I

OUTG0

+ +I

¼

OUTG7

+ I

OUTB0

+ +I

¼

OUTB7

)

-

(Ideal Output Current)

24

D

(%) =

´

100

Ideal Output Current

Ideal current is calculated by the following equation:

1.20

I

OUT(IDEAL, mA)

= 40

´

R

IREF

( )

W

(4) Line regulation is calculated by the following equation (X = R, G, or B; n = 0-7):

(I

OUTXn at V

CC

= 5.5 V)

-

(I

OUTXn at V

CC

= 3.0 V)

100

D

(%/V) =

´

(I

OUTXn at V

CC

= 3.0 V)

5.5 V 3 V

-

(5) Load regulation is calculated by the following equation (X = R, G, or B; n = 0-7):

(I

OUTXn at V

OUTXn

= 3 V) (I

-

OUTXn at V

OUTXn

= 1 V)

100

D

(%/V) =

´

(I

OUTXn at V

OUTXn

= 1 V) 3 V 1 V

-

(6) Not tested; specified by design.



TLC5951


5

TLC5951


www.ti.com

SWITCHING CHARACTERISTICS

At T

A

= –40°C to +85°C, V

CC noted. Typical values are at T

= 3 V to 5.5 V, C

A

= +25°C and V

L

= 15 pF, R

L

CC

= 3.3 V.

= 100 Ω, R

IREF

= 1.2 k Ω, and V

LED

= 5.0 V, unless otherwise t

R0 t

R1 t

F0 t

F1 t

D0 t

D1 t

D2 t

D3 t

D4 t

D5 t

D6 t

D7 t

D8 t

D9 t

ON_ERR

PARAMETER

Rise time

Fall time

Propagation delay

Output on-time error

(1)

TEST CONDITIONS

GSSOUT, DCSOUT

OUTR0-OUTR7, OUTG0-OUTG7, OUTB0-OUTB7, with BCR/G/B = FFh and DCRn/Gn/Bn = 7Fh with DC high adjustment range

GSSOUT, DCSOUT

OUTR0-OUTR7, OUTG0-OUTG7, OUTB0-OUTB7, with BCR/G/B = FFh and DCRn/Gn/Bn = 7Fh with DC high adjustment range

GSSCK ↑ to GSSOUT, DCSCK↑ to DCSOUT

GSLAT ↑ to GSSOUT

XBLNK ↓ to OUTR0/G0/B0, OUTR4/G4/B4 off

GSCKR/G/B ↑ to OUTR0/G0/B0, OUTR4/G4/B4 on, with BCR/G/B = FFh and DCRn/Gn/Bn = 7Fh with DC high adjustment range




Internal latch pulse generation delay from DCSCK

GSLAT ↑ to I

OUTRn/Gn/Bn changing by dot correction control

(control data are 0Ch

≥ 72h or 72h ≥ 0Ch with DC high adjustment range), BCR/G/B = FFh

GSLAT ↑ to I

OUTRn/Gn/Bn changing by global brightness control

(control data are 19h ≥ E6h or E6h ≥ 19h with DCRn/Gn/Bn = 7Fh with

DC high adjustment range) t

OUT_ON

– T

GSCKR/G/B

, GS

DATA

= 001h, GSCKR/G/B = 33 MHz, with BCR/G/B = FFh and DCRn/Gn/Bn = 7Fh with DC high adjustment range

MIN TYP MAX UNIT

6 15 ns

5

20

35

50

3

–15

10

6

10

15 25 ns

50 100 ns

20 40 ns

18

42

66 106 ns

90 140 ns

5

30

30 ns

15 ns

30 ns

40 ns

73 ns

7 ms

50 ns

100 300 ns

5 ns

(1) Output on-time error (t

ON_ERR the constant current driver. T

) is calculated by the formula t

GSCKR

ON_ERR is the period of GSCKR, T

GSCKG

(ns) = t

OUT_ON

– T

GSCKR/G/B

. t

OUT_ON is the period of GSCKG, and T indicates the actual on-time of

GSCKB is the period of GSCKB.

6



TLC5951



.........................................................................................................................................................


FUNCTIONAL BLOCK DIAGRAM

VCC

GSSIN

GSSCK

GSLAT

DCSIN

DCSCK

GSCKR

GSCKG

GSCKB

XBLNK

IREF

GND

VCC

33rd GSCKR/G/B After XBLNK

Goes High or Internal Blank Signal

(1)

LOD/LSD Data Latch for R/G/B

GND

Reference

Current

Control

Latch

Select

Auto Latch

Pulse Gen

GS Counter for RED

3

12

LSB

0

LSB

0

288

216

48

MSB

288-Bit Common Shift Register

LSB

288

287

Lower 216

MSB

Grayscale Data Latch

(12 Bits x 24 Channels)

Higher 17

287

MSB

216-Bit DC/BC/FC/UD Shift Register

0

Lower 199

215

216

LSB MSB

Dot Correction (7-Bit x 24-Channels)/

Brightness Control (8-Bit x 3 Group)/

Function Control (7-Bit)/User-Defined (17-Bit) Data Latch

0

216

215

216

TMGRST

Lower 198

96

12-Bit PWM

Timing Control

96

DSPRPT/PWMMODE

3

GS Counter for GREEN

12

GS Counter for BLUE

12

8

4-Grouped

Switch Delay

12-Bit PWM

Timing Control

8

4-Grouped

Switch Delay

3

96

12-Bit PWM

Timing Control

8

4-Grouped

Switch Delay

3

3

195

8

24

8

8

8-Bit Brightness

Control

8

8-Bit Brightness

Control

8

8-Bit Brightness

Control

8

171

Thermal

Detection

24-Channel Constant-Current Driver with 7-Bit Dot Correction

48

LED Open Detection (LOD)/LED Short Detection (LSD)

GSSOUT

DCSOUT

OUTR0

¼

¼

OUTR7

¼ ¼

OUTG0

¼

OUTG7 OUTB0

¼

OUTB7

(1) The internal blank signal is generated when GSLAT is input for GS data with display timing reset enabling. Furthermore, the signal is generated at the 4096th GSCK when auto repeat mode is enabled. XBLNK can be connected to V repeat is enabled.

CC when the display timing reset or auto



7


TLC5951

TLC5951


www.ti.com

PIN CONFIGURATIONS

DAP PACKAGE

HTSSOP-38 PowerPAD

(TOP VIEW)

RHA PACKAGE

(1)

6 mm × 6 mm QFN-40

(TOP VIEW)

GSSIN

1

GSSCK

2

GSLAT

3

GSCKG

4

GSCKR

5

GSCKB

6

OUTG0

7

OUTR0

8

OUTB0

9

OUTG1

10

OUTR1

11

OUTB1

12

OUTG2 13

OUTR2 14

OUTB2 15

OUTG3 16

OUTR3 17

OUTB3 18

GSSOUT 19

Thermal Pad

(Bottom Side)

38 DCSIN

37 DCSCK

36 XBLNK

35

VCC

34

IREF

33

GND

32

OUTG7

31

OUTR7

30

OUTB7

29 OUTG6

28 OUTR6

27 OUTB6

26 OUTG5

25 OUTR5

24 OUTB5

23 OUTG4

22 OUTR4

21 OUTB4

20 DCSOUT

OUTG3

OUTR3

OUTB3

NC

(2)

GSSOUT

DCSOUT

NC

(2)

OUTB4

OUTR4

OUTG4 10

8

9

6

7

3

4

1

2

5

(1) Product preview device.

(2) NC = no connection.

Thermal Pad

(Bottom Side)

30

29

28

GSCKR

GSCKG

GSLAT

27

26

25

24

23

GSSCK

GSSIN

DCSIN

DCSCK

XBLNK

22

21

VCC

IREF

8



TLC5951



.........................................................................................................................................................


TERMINAL FUNCTIONS

NAME

TERMINAL

NO.

DAP RHA I/O

GSSIN

GSSCK

GSLAT

GSSOUT

DCSIN

DCSCK

DCSOUT

GSCKR

GSCKG

GSCKB

XBLNK

IREF

OUTR0-

OUTR7

1

2

3

19

38

37

20

5

4

6

36

34

26

27

28

5

25

24

6

30

29

31

23

21

8, 11, 14, 2, 9, 12, 15,

17, 22, 25, 18, 33, 36,

28, 31 39

I

I

I

O

I

I

O

I

I

I

I

I/O

O

DESCRIPTION

Serial data input for the 288-bit common shift register for grayscale (GS), dot correction (DC), global brightness control (BC), and function control (FC) data.

GSSIN is connected to the LSB of the 288-bit common shift register. This pin is internally pulled to GND with a 500-k Ω resistor.

Serial data shift clock for the 288-bit common shift register for GS/DC/BC/FC data.

Data present on GSSIN are shifted into the LSB of the shift register with the rising edge of GSSCK. Data in the shift register are shifted toward the MSB at each rising edge of GSSCK. The MSB data of the shift register appear on GSSOUT.

Data in the 288-bit common shift register are copied to the GS data latch or to the

DC/BC/FC data latch at the rising edge of GSLAT. The level of GSLAT at the last

GSSCK before the GSLAT rising edge determines which of the two latches the data are transferred into. When GSLAT is low at the last GSSCK rising edge, all

288 bits in the common shift register are copied to the GS data latch. When

GSLAT is high at the last GSSCK rising edge, bits 0-198 are copied to the

DC/BC/FC data latch and bits 199-215 are copied to the 216-bit DC/BC/FC/UD shift register. The GSLAT rising edge for a DC/BC/FC/UD data write must be input more than 7 ms after a data write through the DCSIN pin.

Serial data output of the 288-bit common shift register. LED open detection (LOD),

LED short detection (LSD), thermal error flag (TEF), and 199-bit data in the

DC/BC/FC data latch can be read via GSSOUT. GSSOUT is connected to the

MSB of the shift register. Data are clocked out at the rising edge of GSSCK.

Serial data input for the 216-bit DC/BC/FC/UD shift register. DCSIN is connected to the LSB of the shift register.

Serial data shift clock for the 216-bit DC/BC/FC/UD shift register. Data present on

DCSIN are shifted into the LSB of the shift register with the DCSCK rising edge.

Data in the shift register are shifted toward the MSB at each DCSCK rising edge.

The MSB data of the register appear on DCSOUT. The 216-bit data in the shift register are automatically copied to DC/BC/FC/UD data latch 3 ms to 7 ms after the DCSCK rising edge is not input.

Serial data output of the 216-bit shift register. DCSOUT is connected to the MSB of the shift register. Data are clocked out at the rising edge of DCSCK.

Reference clock for the GS pulse width modulation (PWM) control for the RED

LED output group. When XBLNK is high, each GSCKR rising edge increments the

RED LED GS counter for PWM control.

Reference clock for the GS PWM control for the GREEN LED output group. When

XBLNK is high, each GSCKR rising edge increments the GREEN LED GS counter for PWM control.

Reference clock for the GS PWM control for the BLUE LED output group. When

XBLNK is high, each GSCKR rising edge increments the BLUE LED GS counter for PWM control.

When XBLNK is low, all constant-current outputs (OUTR0-OUTR7,

OUTG0-OUTG7, OUTB0-OUTB7) are forced off. The grayscale counters for each color group are reset to '0', and the grayscale PWM timing controller is initialized.

When XBLNK is high, all constant current outputs are controlled by the grayscale

PWM timing controller for each color LED. This pin is internally pulled to GND with a 500 k Ω resistor.

A resistor connected between IREF and GND sets the maximum current for all constant current outputs.

Constant-current outputs for the RED LED group. These outputs are controlled with the GSCKR clock signal.

The RED LED group is divided into four subgroups: OUTR0/OUTR4,

OUTR1/OUTR5, OUTR2/OUTR6, and OUTR3/OUTR7.

Each paired output turns on/off with 24 ns (typ) time delay between other paired outputs. Multiple outputs can be tied together to increase the constant current capability. Different voltages can be applied to each output.



TLC5951


9

TLC5951


www.ti.com

TERMINAL FUNCTIONS (continued)

NAME

TERMINAL

NO.

DAP RHA I/O

OUTG0-

OUTG7

OUTB0-

OUTB7

VCC

GND

NC

7, 10, 13, 1, 10, 13,

16, 23, 26, 16, 19, 32,

29, 32 35, 38

9, 12, 15, 3, 8, 11, 14,

18, 21, 24, 17, 34, 37,

27, 30 40

35

33

—

22

20

4, 7

O

O

—

—

—

DESCRIPTION

Constant-current outputs for the GREEN LED group. These outputs are controlled with the GSCKG clock signal.

The GREEN LED group is divided into four subgroups: OUTG0/OUTG4,

OUTG1/OUTG5, OUTG2/OUTG6, and OUTG3/OUTG7.


Constant current outputs for the BLUE LED group. These outputs are controlled with the GSCKB clock signal.

The BLUE LED group is divided into four subgroups: OUTB0/OUTB4,

OUTB1/OUTB5, OUTB2/OUTB6, and OUTB3/OUTB7.


Power supply

Power ground

No internal connection

10



TLC5951



.........................................................................................................................................................


PARAMETER MEASUREMENT INFORMATION

PIN EQUIVALENT INPUT AND OUTPUT SCHEMATIC DIAGRAMS

VCC VCC

INPUT

GND

Figure 1. GSSCK, GSLAT, DCSIN, DCSCK, GSCKR,

GSCKG, GSCKB

VCC

INPUT

GND

Figure 2. GSSIN, XBLNK

OUTn

GND

SOUT

TEST CIRCUITS

GND

Figure 3. GSSOUT, DCSOUT

VCC

R

IREF

IREF

VCC

OUTXn

(2)

GND

R

L

C

L

(1)

V

LED

Figure 4. OUTR0/G0/B0 Through OUTR7/G7/B7

VCC

VCC

GND

SOUT

C

L

(1)

(1) C

L includes measurement probe and jig capacitance.

(2) X = R, G, or B; n = 0-7.

Figure 5. Rise Time and Fall Time Test Circuit for

OUTRn/Gn/Bn

(1) C

L includes measurement probe and jig capacitance.

Figure 6. Rise Time and Fall Time Test Circuit for

GSSOUT and DCSOUT

VCC

R

IREF

IREF

VCC OUTR0

OUTXn

(1)

GND OUTB7

V

OUTfix

V

OUTRn/Gn/Bn

(1) X = R, G, or B; n = 0-7.

Figure 7. Constant-Current Test Circuit for OUTRn/Gn/Bn



TLC5951


11

TLC5951


www.ti.com

TIMING DIAGRAMS

T

WH0

, T

WL0

, T

WH1

, T

WL1

, T

WL2

:

V

CC

INPUT 50%

GND

T

WH

T

WL

T

SU0

, T

SU1

, T

SU2

, T

SU3

, T

SU4

, T

H0

, T

H1

, T

H2

:

CLOCK

INPUT

(1)

50%

V

CC

T

SU

T

H

GND

V

CC

DATA/CONTROL

INPUT

(1)

50%

GND

(1) Input pulse rise and fall time is 1 ns to 3 ns.

t

R0

, t

R1

, t

F0

, t

F1

, t

D0

, t

D1

, t

D2

, t

D3

, t

D4

, t

D5

, t

D6

, t

D7

, t

D8

, t

D9

:

Figure 8. Input Timing

V

CC

INPUT

(1)

50%

GND t

D

V

OH or V

OUTRn/Gn/BnH

90%

OUTPUT

50%

10% t or t

R F

V

OL or V

OUTRn/Gn/BnL

(1) Input pulse rise and fall time is 1 ns to 3 ns.

Figure 9. Output Timing

12



TLC5951



.........................................................................................................................................................


TIMING DIAGRAMS (continued)

GSCKR

(GSCKG)

(GSCKB)


(Internal)

Dot Correction/

Brightness Control Function

Control Data Latch (Internal)

Common Shift Register

Bit 0 (Internal)


Bit 1 (Internal)

GSSIN

GSSCK

T

GSR0

0A

SU0

GSB7

11B

GSB7

10B

T

H0

GSB7

9B

GSB7

8B

GSB7

7B f

CLK

(SCLK)

GSR0

3B

GSR0

2B

GSR0

1B

GSR0

0B

T

WH0

1 2 3 4

T

SU2

5

T

WL0

285 286 287 288

T

H1

T

WH1

GSB7

11C

GSB7

10C

GSB7

9C

GSB7

8C

GSB7

7C

GSB7

6C

GSB7

5C

GSB7

4C

GSB7

3C

1 2 3 4 5 6 7

GSLAT

T

SU3

, T

SU4

XBLNK

Shift Register Data Are Transferred to GS Data Latch

T

SU1 f

CLK

(GSCKR/G/B)

T

WL2

GSB7

11B

GSB7

10B

GSB7

9B

GSB7

8B

GSB7

7B

DCR0

Bit 0

GSB7

11B

GSB7

10B

GSB7

9B

GSB7

8B

Previous Data

GSR0

3B

GSR0

2B

GSR0

1B

GSR0

0B

DCR0

Bit 0

GSR0

4B

GSR0

3B

GSR0

2B

GSR0

1B

DCR0

Bit 1

Latest Data

GSB7

11C

GSB7

10C

GSB7

9C

GSB7

8C

GSB7

7C

GSB7

9C

GSB7

8C

GSB7

7C

DCR0

0B

GSB7

11C

GSB7

10C

GSB7

9C

GSB7

8C

GSB7

7C

GSB7

9C

GSB7

8C


Bit 286 (Internal)

GSSOUT

OUTR0, OUTR4

(OUTG0, OUTG4)

(OUTB0, OUTB4)

OUTR1, OUTR5

(OUTG1, OUTG5)

(OUTB1, OUTB5)

OUTR2, OUTR6

(OUTG2, OUTG6)

(OUTB2, OUTB6)

OUTR3, OUTR7

(OUTG3, OUTG7)

(OUTB3, OUTB7)

OFF

ON

OFF

ON

OFF

ON

OFF

ON

(V

LOD

B6A

LOD

B5A t

D0

LOD

B7A

LOD

B6A

LOD

B4A

LOD

B5A

LOD

B3A

LOD

B4A

LOD

B2A

LOD

B3A

OUTRnH

)

DCR0

1A

DCR0

0A

GSR0

11B

GSR0

10B

LOD

B6B

DCR0

3A

DCR0

2A

DCR0

1A

DCR0

0A

GSB7

11B

SID Data Are Transferred to


LOD

B7B

(V

OUTRnL

)

Figure 10. Grayscale Data Write Timing

LOD

B5B

LOD

B4B

LOD

B3B

LOD

B2B

LOD

B1B

LOD

B0B

LOD

G7B

LOD

G6B

LOD

B6B

LOD

B5B

LOD

B4B

LOD

B3B

LOD

B2B

LOD

B1B

LOD

B0B

LOD

G7B t

D2

ON t

D3 t

F1

ON t

D4 t

R1

ON t

D5 t

D6

ON



TLC5951


13

TLC5951


www.ti.com


GSCKR

(GSCKG)

(GSCKB)


(Internal)

Dot Correction/

Brightness Control Function

Control Data Latch (Internal)


Bit 0 (Internal)


Bit 1 (Internal)

GSSIN

GSSCK

T

GSR0

0A

SU0

NO

VAL71

NO

VAL70

T

H0

NO

VAL69

NO

VAL68

NO

VAL67 f

CLK

(SCLK)

DCR0

3B

DCR0

2B

DCR0

1B

DCR0

0B

T

WH0

T

H1

1 2 3 4 5

T

WL0

285 286 287 288

T

WL1

T

SU2

NO

VAL71

NO

VAL70

NO

VAL69

NO

VAL68

NO

VAL67

NO

VAL66

NO

VAL65

NO

VAL64

NO

VAL63

1 2 3 4 5 6 7 8 9

GSLAT

XBLNK

T

H2

T

SU1

Shift Register Data Are Transferred to DC/BC/FC/UD Data Latch f

CLK

(GSCKR/G/B)

T

WL2

DCR0

0A

NO

VAL71

NO

VAL70

NO

VAL69

NO

VAL68

NO

VAL67

DCR0

1A

DCR0

0A

NO

VAL71

NO

VAL70

NO

VAL69

NO

VAL68

Previous Data

DCR0

3B

DCR0

2B

DCR0

1B

DCR0

0B

DCR0

4B

DCR0

3B

DCR0

2B

DCR0

1B

Latest Data

NO

VAL71

NO

VAL70

NO

VAL69

NO

VAL68

NO

VAL67

NO

VAL66

NO

VAL65

NO

VAL64

DCR0

0B

NO

VAL71

NO

VAL70

NO

VAL69

NO

VAL68

NO

VAL67

NO

VAL66

NO

VAL65


Bit 286 (Internal)

GSSOUT

NO

VAL70

NO

VAL71

NO

VAL69

NO

VAL68 t

D0

NO

VAL70

NO

VAL69

NO

VAL67

NO

VAL66

NO

VAL68

NO

VAL67

NO

VAL65

NO

VAL66

(V

OUTRnH

)

(V

OUTRnL

)

DCR0

1A

DCR0

0A

NO

VAL71

NO

VAL70

DCR0

2A

DCR0

1A

DCR0

0A

NO

VAL71

SID Data Are Not Transferred to


ON

NO

VAL69

NO

VAL68

NO

VAL67

NO

VAL66

NO

VAL65

NO

VAL64

NO

VAL63

NO

VAL62

NO

VAL70

NO

VAL69

NO

VAL68

NO

VAL67

NO

VAL66

NO

VAL65

NO

VAL64

NO

VAL63 t

D2

OUTR0, OUTR4

(OUTG0, OUTG4)

(OUTB0, OUTB4)

OUTR1, OUTR5

(OUTG1, OUTG5)

(OUTB1, OUTB5)

OUTR2, OUTR6

(OUTG2, OUTG6)

(OUTB2, OUTB6)

OUTR3, OUTR7

(OUTG3, OUTG7)

(OUTB3, OUTB7)

OFF

ON

OFF

ON

OFF

ON

OFF

ON t

D3 t

D4 t

D5

ON

ON

ON t

D6 t , t

D9

Figure 11. Dot Correction/Global Brightness Control/Function Control/User-Defined

Data Write Timing from GS Data Path

14



TLC5951



.........................................................................................................................................................



DCSIN

DCR0

0A

USER

16B

USER

15B

T

H0

USER

14B

USER

13B

USER

12B

T

SU0

DCSCK

1 2 3 4 5

T

WL0

Auto Generated

Latch Pulse

(Internal)

DCR0

3B

DCR0

2B

DCR0

1B

DCR0

0B

T

WH0

213 214 215 216 t

D7

Grayscale

Data Latch

(Internal)

DC/BC/FC/UD

Data Latch

(Internal)

DCSOUT

USER

16C

USER

15C

USER

14C

USER

13C

USER

12C

USER

11C

USER

10C

Previous Data

USER

16A t

D0

USER

15A

USER

14A

USER

13A

USER

12A

USER

11A

DCR0

3A

DCR0

2A t /t

R0 F0

DCR0

1A

DCR0

0A

USER

16B

Latest Data

USER

15B

USER

14B

USER

13B

USER

12B

USER

11B

USER

10B

USER

9B

Figure 12. Dot Correction/Global Brightness Control/Function Control

Data Write Timing from DC Data Path

GSSIN

GSR0

1B

GSR0

0B

GSB7

11C

GSB7

10C

GSB7

9C

GSB7

8C

GSB7

7C

GSB6

0C

GSG6

11C

GSG6

10C

GSG5

1C

GSG5

0C

GSR5

11C

GSR0

1C

GSR0

0C

287 288

T

SU2

1 2 3 4

GSSCK

T

H1

T

WH1

GSLAT

GS Data Latch

(Internal)

DC/BC/FC/UC

Data Latch

(Internal)

Previous Data

Common Shift

Register Bit 0

(Internal)

Common Shift

Register Bit 1

(Internal)

GSR0

2B

GSR0

1B

GSR0

0B

GSR0

3B

GSR0

2B

GSR0

1B

Common Shift

Register Bit 286

(Internal)

GSSOUT

(Common Shift

Register Bit 287)

GSB7

11B

GSB7

10B

GSB7

11B

Latest Data

DCR0

0

DCR0

1

LOD

B6B t

D1

LOD

B7B

GSB7

11C

GSB7

10C

GSB7

9C

GSB7

8C

DCR0

0

GSB7

11C

GSB7

10C

GSB7

9C

LOD

B5B

LOD

B4B

LOD

B3B

LOD

B2B

LOD

B6B

LOD

B5B

LOD

B4B

LOD

B3B

5 46 47 48 49 93 94 95 96 286 287 288

GSB6

2C

GSB6

1C

GSB6

0C

GSB6

3C

GSB6

2C

GSB6

1C

LSD

B0B

TEF

Reserved

LSD

R1B

LSD

R0B

TEF

GSG5

2C

GSG5

1C

GSG5

0C

GSG5

3C

GSG5

2C

GSG5

1C

FUNC

1

FUNC

0

BCB

6

FUNC

2

FUNC

1

FUNC

0

GSR0

2C

GSR0

1C

GSR0

0C

GSR0

3C

GSR0

2C

GSR0

1C

DCR

0

GSB7

11C

GSB7

10C

DCR

1

DCR

0

GSB7

11C

Figure 13. Status Information Data Read Timing



TLC5951


15

TLC5951


www.ti.com

TYPICAL CHARACTERISTICS

At T

A

= +25°C and V

CC

= 3.3 V, unless otherwise noted.

100

REFERENCE RESISTOR vs OUTPUT CURRENT

24000

10

9600

1

0

4800

3200

2400

1920

10 20 30

Maximum Output Current (mA)

Figure 14.

1600

1371

1200

40

45

40

15

10

5

35

30

25

20

0

0

OUTPUT CURRENT vs OUTPUT VOLTAGE

I

O

= 40 mA

0.5

T = +25 C, V

°

CC

= +3.3 V, BCX = FFh

DCXn = 7Fh with High Adjustment Range

I = 30 mA

O

I

O

= 5 mA

I

O

= 10 mA

I

O

= 20 mA

1.0

1.5

Output Voltage (V)

Figure 16.

2.0

I

O

= 2 mA

2.5

3.0

45

40

35

30

25

20

15

10

5

0

0


I

O

= 40 mA

0.5

T = +25 C, V

°

CC

= +5 V, BCX = FFh


I

O

= 30 mA

I

O

= 5 mA

I

O

= 10 mA

I = 20 mA

O

1.0

1.5

Output Voltage (V)

Figure 18.

2.0

I

O

= 2 mA

2.5

3.0

POWER DISSIPATION vs TEMPERATURE

6000

5000

4000

TLC5951RHA

3000

2000

TLC5951DAP, Soldered

TLC5951DAP, Not Soldered

1000

41

40

39

45

44

43

42

38

37

36

35

0

0

-

40

-

20 0 20 40 60

Free-Air Temperature ( C)

°

Figure 15.

80


0.5

T = +85 C

°

T = +25 C

°

T = 40 C

°

100

I

OLCMax

= 40 mA, V

CC

= +3.3 V, BCX = FFh


2.5

3.0

1.0

1.5

Output Voltage (V)

Figure 17.

2.0

41

40

39

38

37

45

44

43

42

36

35

0


0.5

T = +85 C

°

T = 40 C

°

I

OLCMax

= 40 mA, V

CC

= +5 V, BCX = FFh


2.5

3.0

1.0

1.5

Output Voltage (V)

Figure 19.

2.0

T = +25 C

°

16



TLC5951



.........................................................................................................................................................


TYPICAL CHARACTERISTICS (continued)

At T

A

= +25°C and V

CC


1

0

-

1

-

2

-

3

-

4

-

40

4

3

CONSTANT-CURRENT ERROR vs AMBIENT TEMPERATURE

(Channel-to-Channel, RED Color)

I

OLCMax

= 40 mA

DCRn = 7Fh with High Adjustment Range

BCR = FFh

2

-

20

V

CC

= 3.3 V

V

CC

= 5 V

80 0 20 40

Ambient Temperature ( )

°

Figure 20.

60 100

-

1

-

2

1

0

-

3

-

4

-

40

4

3


(Channel-to-Channel, BLUE Color)

I

OLCMax

= 40 mA

DCBn = 7Fh with High Adjustment Range

BCB = FFh

2

-

20

V

CC

= 3.3 V

V = 5 V

CC

80 0 20 40


°

Figure 22.

60 100

1

0

-

1

4

3

2

-

2

-

3

-

4

0

CONSTANT-CURRENT ERROR vs OUTPUT

(Channel-to-Channel, GREEN Color)

I

OLCMax

= 2 mA to 40 mA Set By R

IREF

T = +25 C

°

DCGn = 7Fh with High Adjustment Range

BCG = FFh

V

CC

= 3.3 V

V = 5 V

CC

10 30 40 20

Output Current (mA)

Figure 24.

0

-

1

-

2

-

3

-

4

-

40

2

1

4

3



I

OLCMax

= 40 mA

DCGn = 7Fh with High Adjustment Range

BCG = FFh

-

20

V

CC

= 3.3 V

V

CC

= 5 V

80 0 20 40


°

Figure 21.

60 100

-

1

-

2

-

3

-

4

0

1

0

4

3

2



I

OLCMax


IREF

T = +25 C

°

A

DCRn = 7Fh with High Adjustment Range

BCR = FFh

V

CC

= 3.3 V

V = 5 V

CC

10 30 20

Output Current (mA)

Figure 23.

40

1

0

-

1

4

3

2

-

2

-

3

-

4

0



I

OLCMax


IREF

T = +25 C

°

DCBn = 7Fh with High Adjustment Range

BCB = FFh

V

CC

= 3.3 V

V = 5 V

CC

10 30 20

Output Current (mA)

Figure 25.

40



17


TLC5951

TLC5951


www.ti.com


At T

A

= +25°C and V

CC


0

-

1

-

2

-

3

-

4

10

2

1

4

3



Constant Current = 13 mA to 40 mA

Set By DCRn with High Adjustment Range

T = +25 C, I

°

A OLCMax

= 40 mA

BCR = FFh

V

CC

= 3.3 V

V

CC

= 5 V

15 35 20 25 30

Output Current (mA)

Figure 26.

40

4

3

2

-

1

-

2

1

0

-

3

-

4

10




Set By DCBn with High Adjustment Range

T = +25 C, I

°

OLCMax

= 40 mA

BCB = FFh

V

CC

= 3.3 V

V = 5 V

CC

15 35 20 25 30

Output Current (mA)

Figure 28.

40

1

0

-

1

4

3

2

-

2

-

3

-

4

0




Set By DCGn with Low Adjustment Range

T = +25 C, I

°

OLCMax

= 40 mA

BCG = FFh

V

CC

= 3.3 V

V = 5 V

CC

5 25 10 15 20

Output Current (mA)

Figure 30.

30

0

-

1

-

2

-

3

-

4

10

2

1

4

3




Set By DCGn with High Adjustment Range

T = +25 C, I

A

°

OLCMax

= 40 mA

BCG = FFh

V

CC

= 3.3 V

V

CC

= 5 V

15 35 20 25 30

Output Current (mA)

Figure 27.

40

4

3

2

-

1

-

2

1

0

-

3

-

4

0




Set By DCRn with Low Adjustment Range

T = +25 C, I

°

OLCMax

= 40 mA

BCR = FFh

V

CC

= 3.3 V

V = 5 V

CC

5 25 10 15 20

Output Current (mA)

Figure 29.

30

1

0

-

1

4

3

2

-

2

-

3

-

4

0




Set By DCBn with Low Adjustment Range

T = +25 C, I

°

OLCMax

= 40 mA

BCB = FFh

V

CC

= 3.3 V

V = 5 V

CC

5 25 10 15 20

Output Current (mA)

Figure 31.

30

18



TLC5951



.........................................................................................................................................................



At T

A

= +25°C and V

CC


0

-

1

-

2

-

3

-

4

0

2

1

4

3




Set By BCR with Low Adjustment Range

T = +25 C, I

°

A OLCMax

= 40 mA

DCRn = FFh

V

CC

= 3.3 V

V

CC

= 5 V

10 30 20

Output Current (mA)

Figure 32.

40

4

3

2

-

1

-

2

1

0

-

3

-

4

0




Set By BCB with Low Adjustment Range

T = +25 C, I

°

OLCMax

= 40 mA

DCBn = FFh

V

CC

= 3.3 V

V = 5 V

CC

10 30 20

Output Current (mA)

Figure 34.

40

45

40

15

10

5

35

30

25

20

0

0

DOT CORRECTION LINEARITY

(I

OLCMax with Lower Range)

Low Adjustment Range

T = +25 C, BCx = FFh

°

V

CC

= 3.3 V

16

I = 40 mA

O

I = 20 mA

O

I

O

= 2 mA

32 48 64 80

Dot Correction Data (dec)

Figure 36.

96 112

128

0

-

1

-

2

-

3

-

4

0

2

1

4

3




Set By BCG with Low Adjustment Range

T = +25 C, I

A

°

OLCMax

= 40 mA

DCGn = FFh

V

CC

= 3.3 V

V

CC

= 5 V

10 30 20

Output Current (mA)

Figure 33.

40

45

20

15

10

40

35

30

25

5

0

0


(I

OLCMax with Upper Range)

High Adjustment Range

T = +25 C, BCx = FFh

°

V

CC

= 3.3 V

I

O

= 40 mA

16

I

O

= 2 mA

I

O

= 20 mA

32 48 64 80


Figure 35.

96 112 128

45

40

15

10

5

35

30

25

20

0

0

(I


OLCMax with Upper and Lower Range)

I

OLCMax

= 40 mA

BCx = FFh

V

CC

= 3.3 V


16

Low Adjustment Range

T = 40 C

°

112 32 48 64 80


Figure 37.

96

128



TLC5951


19

TLC5951


www.ti.com


At T

A

= +25°C and V

CC


45

20

15

10

40

35

30

25

5

0

0

GLOBAL BRIGHTNESS CONTROL LINEARITY

(I

OLCMax with Upper Range)


T = +25 C

°

DCXn = 7Fh

V

CC

= 3.3 V

I

O

= 40 mA

32

I

O

= 2 mA

I

O

= 20 mA

224 256 64 96 128 160 192

Brightness Correction Data (dec)

Figure 38.

CONSTANT-CURRENT OUTPUT

VOLTAGE WAVEFORM

GLOBAL BRIGHTNESS CONTROL LINEARITY

(Ambient Temperature with Upper Range)

45

20

15

10

40

35

30

25

5

0

0


I

OLCMax

= 40 mA

DCXn = 7Fh

V

CC

= 3.3 V

32 64 96 128 160 192

Brightness Correction Data (dec)

Figure 39.

T = 40 C

°

224 256

CH1 (2 V/div)

CH2 (2 V/div)

CH3 (2 V/div)

I

OLCMax

= 40 mA , BCX = 7Fh


T = +25 C, GSCKR/G/B = 33 MHz

°

A

V

CC

= 3.3 V, V

LED

= 5 V, R = 100

W,

C = 15 pF

Time (25 ns/div)

Figure 40.

DETAILED DESCRIPTION

MAXIMUM CONSTANT SINK CURRENT VALUE

The TLC5951 maximum constant sink current value for each channel, I

OLCMax resistor, R

IREF

, placed between R

IREF and GND. The R

IREF

, is determined by an external resistor value is calculated with

Equation 1 .

R

IREF

(k ) =

W

V (V)

IREF

´

40

I

OLCMax

(mA)

(1)

Where:

V

IREF

= the internal reference voltage on IREF (1.20 V, typically)

I

OLCMax is the largest current for each output. Each output sinks the I

OLCMax current when it is turned on, the dot correction is set to the maximum value of 7Fh (127d), and the global brightness control data are set to the maximum value of FFh (255d). Each output sink current can be reduced by lowering the output dot correction or brightness control value.

I

R

IREF must be between 1.2 k Ω and 24 kΩ to keep I unstable when I

OLCMax

OLCMax

OLCMax between 40 mA (typ) and 2mA (typ); the output may be is set lower than 2 mA. Output currents lower than 2 mA can be achieved by setting to 2 mA or higher and then using dot correction and global brightness control to lower the output current.

20




TLC5951


.........................................................................................................................................................


Figure 14

and

Table 1

show the constant sink current versus external resistor, R

IREF

, characteristics. Multiple outputs can be tied together to increase the constant-current capability. Different voltages can be applied to each output.

Table 1. Maximum Constant Current Output versus

External Resistor Value

I

OLCMax

(mA, Typical)

40

35

30

25

20

15

10

5

2

R

IREF

(k Ω)

1.2

1.371

1.6

1.92

2.4

3.2

4.8

9.6

24

DOT CORRECTION (DC) FUNCTION

The TLC5951 has the capability to adjust the output current of each channel (OUTR0-OUTR7, OUTG0-OUTG7,

OUTB0-OUTB7) individually. This function is called dot correction (DC). The DC function allows the brightness and color deviations of LEDs connected to each output to be individually adjusted. Each output DC is programmed with a 7-bit word for each channel output. Each channel output current is adjusted with 128 steps within one of two adjustment ranges. The dot correction high adjustment range allows the output current to be adjusted from 33.3% to 100% of the maximum output current, I

OLCMax

. The dot correction low adjustment range allows the output current to be adjusted from 0% to 66.7% of I

OLCMax

. The range control bits in the function control latch select the high or low adjustment range.

Equation 2

and

Equation 3

calculate the actual output current as a function of R

IREF

, DC value, adjustment range, and brightness control value. There are three range control bits that control the DC adjustment range for three groups of outputs: OUTR0-OUTR7, OUTG0-OUTG7, and OUTB0-OUTB7. DC data are programmed into the TLC5951 via the serial interface.

When the IC is powered on, the DC data in the 216-bit common shift register and data latch contain random data. Therefore, DC data must be written to the DC latch before turning the constant-current output on.

Additionally, XBLNK should be low when the device turns on to prevent the outputs from turning on before the proper grayscale values can be written. All constant-current outputs are off when XBLNK is low.



TLC5951


21

TLC5951


www.ti.com

GLOBAL BRIGHTNESS CONTROL (BC) FUNCTION

The TLC5951 has the capability to adjust the output current of each color group simultaneously. This function is called global brightness control (BC). The global brightness control for each of the three color groups,

(OUTR0-OUTR7, OUTG0-OUTG7, and OUTB0-OUTB7), is programmed with a separate 8-bit word. The BC of each group is adjusted with 256 steps from 0% to 100%. 0% corresponds to 0 mA. 100% corresponds to the maximum output current programmed by R

IREF and each output DC value. Note that even though the BC value for all color groups are identical, the output currents can be different if the DC values are different.

Equation 2

and

Equation 3

calculate the actual output current as a function of R

IREF

, DC adjustment range, and brightness control value. BC data are programmed into the TLC5951 via the serial interface.

When the IC is powered on, the BC data in the 216-bit common shift register and data latch contain random data. Therefore, BC data must be written to the BC latch before turning the constant-current output on.

Additionally, XBLNK should be low when the device turns on to prevent the outputs from turning on before the proper grayscale values can be written. All constant-current outputs are off when XBLNK is low.

Equation 2

determines the output sink current for each color group when the dot correction high adjustment range is chosen.

I

OUT

(mA) =

1

3

I

OLCMax

(mA) +

2

3

I

OLCMax

(mA)

´

DC

127

´

BC

255

(2)

Equation 3

determines the output sink current for each color group when the dot correction low adjustment range is chosen.

I

OUT

(mA) =

2

3

I

OLCMax

(mA)

´

DC

127

´

BC

255

(3)

Where:

I

OLCMax

= the maximum channel current for each channel determined by R

IREF

DC = the decimal dot correction value for the output. This value ranges between 0 and 127.

BC = the decimal brightness control value for the output color group. This value ranges between 0 and 255.

DC DATA

(Binary)

000 0000

000 0001

000 0010

—

111 1101

111 1110

111 1111

Table 2. Output Current versus DC Data and I

OLCMax

with

Dot Correction High Adjustment Range (BC Data = FFh)

DC DATA

(Decimal)

0

1

2

—

125

126

127

DC DATA

(Hex)

00

01

02

—

7D

7E

7F

BC DATA

(Hex)

FF

FF

FF

—

FF

FF

FF

PERCENTAGE

OF I

OLCMax

I

OUT

, mA

(%) (I

OLCMax

I

OUT

= 40 mA) (I

OLCMax

, mA

= 2 mA)

33.3

13.33

0.67

33.9

34.4

—

99.0

13.54

13.75

—

39.58

0.68

0.69

—

1.98

99.5

100.0

39.79

40.00

1.99

2.00

22



TLC5951



.........................................................................................................................................................


DC DATA

(Binary)

000 0000

000 0001

000 0010

—

111 1101

111 1110

111 1111

Table 3. Output Current versus DC Data and I

OLCMax

with

Dot Correction Low Adjustment Range (BC Data = FFh)

DC DATA

(Decimal)

0

1

2

—

125

126

127

DC DATA

(Hex)

00

01

02

—

7D

7E

7F

BC DATA

(Hex)

FF

FF

FF

—

FF

FF

FF

PERCENTAGE

OF I

OLCMax

I

OUT

, mA

(%) (I

OLCMax

I

OUT

= 40 mA) (I

OLCMax

, mA

= 2 mA)

0 0 0

0.5

1.0

0.21

0.42

0.01

0.01

—

65.6

66.1

66.7

—

26.25

26.46

26.67

—

1.31

1.32

1.33

BC DATA

(Binary)

000 0000

000 0001

000 0010

—

111 1101

111 1110

111 1111

BC DATA

(Hex)

00

—

33

—

80

—

CC

—

FF

Table 4. Output Current versus BC Data and I

OLCMax

with

Dot Correction High Adjustment Range (DC Data = 7Fh)

BC DATA

(Decimal)

0

1

2

—

253

254

255

BC DATA

(Hex)

00

01

02

—

FD

FE

FF

DC DATA

(Hex)

7F

7F

7F

—

7F

7F

7F

PERCENTAGE

OF I

OLCMax

I

OUT

, mA

(%) (I

OLCMax

I

OUT

= 40 mA) (I

OLCMax

, mA

= 2 mA)

0 0 0

0.4

0.8

0.16

0.31

0.01

0.02

—

99.2

99.6

100.0

—

39.69

39.84

40.00

—

1.98

1.99

2.00

Table 5. Output Current versus BC Data, DC Data, and I

OLCMax

Dot Correction High Adjustment Range with

BC DATA

(Decimal)

0

—

51

—

128

—

204

—

255

DC DATA

(Hex)

20

—

20

—

20

—

20

—

20

DC DATA

(Decimal)

32

—

32

—

32

—

32

—

32

PERCENTAGE I

OLCMax

OF I

OLCMax

(%)

= 40 mA

(mA, Typical)

I

OLCMax

= 2 mA

(mA, Typical)

0

—

0

—

0

—

10.02

—

4.01

—

0.2

—

25.16

—

40.10

—

50.13

10.06

—

16.04

—

13.33

0.5

—

0.8

—

1.0



TLC5951


23

TLC5951


www.ti.com

GRAYSCALE (GS) FUNCTION (PWM CONTROL)

The TLC5951 can adjust the brightness of each output channel using a pulse width modulation (PWM) control scheme. The use of 12 bits per channel results in 4096 brightness steps, from 0% up to 100% brightness. The grayscale circuitry is duplicated for each of the three color groups.

The PWM operation for each color group is controlled by a 12-bit GS counter. Three GS counters are implemented to control each of the three color outputs, OUTR0-OUTR7, OUTG0-OUTG7, and OUTB0-OUTB7.

Each counter increments on each rising edge of the grayscale reference clock (GSCKR, GSCKG, or GSCKB).

The falling edge of XBLNK resets the three counter values to '0'. The grayscale counter values are held at '0' while XBLNK is low, even if the GS clock input is toggled high and low. Pulling XBLNK high enables the GS clock. The first rising edge of a GS clock after XBLNK goes high increments the corresponding grayscale counter by one and switches on all outputs with a non-zero GS value programmed into the GS latch. Each additional rising edge on a GS clock increases the corresponding GS counter by one.

The GS counters keep track of the number of clock pulses from the respective GS clock inputs (GSCKR,

GSCKG, and GSCKB). Each output stays on while the counter is less than or equal to the programmed grayscale value. Each output turns off at the rising edge of the GS counter value when the counter is larger than the output grayscale latch value.

Equation 4

calculates each output (OUTRn/Gn/Bn) on-time (t

OUT_ON

): t

OUTON

(ns) = T

GSCLKR/G/B

(ns) GSn

´

(4)

Where:

T

GSCKR/G/B

= one period of GS clock for the color

GSn = the programmed grayscale value for OUTRn/Gn/Bn (GSn = 0d to 4095d)

When new GS data are latched into the GS data latch with the rising edge on GSLAT during a PWM cycle, the

GS data latch registers are immediately updated. This latching can cause the outputs to turn on or off unexpectedly. For proper operation, GS data should only be latched into the IC at the end of a display period when XBLNK is low.

Table 6

summarizes the GS data value versus the output on-time duty cycle.

When the IC is powered up, the 288-bit common shift register and GS data latch contain random data.

Therefore, GS data must be written to the GS latch before turning the constant-current output on. Additionally,

XBLNK should be low when the device is powered up to prevent the outputs from turning on before the proper

GS values are programmed into the registers. All constant-current outputs are off when XBLNK is low.

If there are any unconnected outputs (OUTRn, OUTGn, and OUTBn), including LEDs in a failed short or failed open condition, the GS data corresponding to the unconnected output should be set to '0' before turning on the

LEDs. Otherwise, the VCC supply current (I

VCC

) increases while that constant-current output is programmed to be on.

GS DATA

(Binary)

0000 0000 0000

0000 0000 0001

0000 0000 0010

—

0111 1111 1111

1000 0000 0000

1000 0000 0001

—

1111 1111 1101

1111 1111 1110

1111 1111 1111

Table 6. Output Duty Cycle and On-Time versus GS Data

GS DATA

(Decimal)

0

1

2

—

2047

2048

2049

—

4093

4094

4095

GS DATA

(Hex)

000

001

002

—

7FF

800

801

—

FFD

FFE

FFF

OUTPUT ON-TIME DUTY

CYCLE (%)

0

0.02

0.05

—

49.99

50.01

50.04

—

99.95

99.98

100

OUTPUT ON-TIME

(33-MHz GS Clock) (ns)

0

30

61

—

62030

62061

62091

—

124030

124061

124091

24



TLC5951



.........................................................................................................................................................


PWM Counter 12-Bit Mode Without Auto Repeat

XBLNK

(1)

GSCKR

GSCKG

GSCKB

OUTRn/Gn/Bn

(GSDATA = 000h)

OFF (V

OUTRn/Gn/BnH

)

ON (V

OUTRn/Gn/BnL

)

OFF

OUTRn/Gn/Bn

(GSDATA = 001h)

ON

OUTRn/Gn/Bn

(GSDATA = 003h)

OFF

OUTRn/Gn/Bn

(GSDATA = 002h)

ON

OFF

ON

OFF

OUTRn/Gn/Bn

(GSDATA = 7FFh)

ON

OFF

OUTRn/Gn/Bn

(GSDATA = 800h)

ON

OFF

OUTRn/Gn/Bn

(GSDATA = 801h)

ON

1 2 3 4

¼

2048

2049

2050

¼

GS counter starts to count GSCKR/G/B after

XBLNK goes high.

Drivers do not turn on when Grayscale data are zero.

T = GSCKR/G/B 1

´

T = GSCKR/G/B 2

´

T = GSCKR/G/B 3

´

T = GSCKR/G/B 2047

´

T = GSCKR/G/B 2048

´

T = GSCKR/G/B

´

2049

¼

(V

OUTRn/Gn/BnH

)

(V

OUTRn/Gn/BnL

)

(V

OUTRn/Gn/BnH

)

(V

OUTRn/Gn/BnL

)

(V

OUTRn/Gn/BnH

)

(V

OUTRn/Gn/BnL

)

(V

OUTRn/Gn/BnH

)

(V

OUTRn/Gn/BnL

)

(V

OUTRn/Gn/BnH

)

(V

OUTRn/Gn/BnL

)

(V

OUTRn/Gn/BnH

)

(V

OUTRn/Gn/BnL

)

4095

4096

4097 ¼

¼

1 2 3 4

¼

OFF

T = GSCKR/G/B 4093

´

(V

OUTRn/Gn/BnH

)

OUTRn/Gn/Bn

(GSDATA = FFDh)

ON

(V

OUTRn/Gn/BnL

)

(V

OUTRn/Gn/BnH

)

OFF

T = GSCKR/G/B 4094

´

OUTRn/Gn/Bn

(GSDATA = FFEh)

ON

(V

OUTRn/Gn/BnL

)

(V

OUTRn/Gn/BnH

)

OFF T = GSCKR/G/B 4095

´

OUTRn/Gn/Bn

(GSDATA = FFFh)

ON

OUTRn/Gn/Bn turns on at the first rising edge of GSCKR/G/B after

XBLNK goes high except when Grayscale data are zero.

(V

OUTRn/Gn/BnL

)

OUTRn/Gn/Bn does not turn on again until XBLNK goes low once in case of no auto repeat mode.

(1) The internal blank signal is generated when GSLAT is input for GS data with display timing reset enabled. Also, the signal is generated at

4096th GSCKR/G/B when the auto repeat mode is enabled. XBLNK can be connected to VCC when the display timing reset or auto repeat is enabled.

Figure 41. PWM Operation 1



TLC5951


25

TLC5951


www.ti.com

PWM Counter 8-, 10-, or 12-Bit Mode Without Auto Repeat

XBLNK

GSCKR

GSCKG

GSCKB

1 2 3 4

¼

¼

255

256

257

¼

1023

1024

1025

¼

GS counter starts to count GSCKR/G/B after XBLNK goes high.

PWM 8-Bit Mode

(FC Bit 1/0 = 1/1)

OFF (V

OUTRn/Gn/BnH

)

T = GSCKR/G/B

´

255

OUTRn/Gn/Bn

(GSDATA = FFFh)

ON (V

OUTRn/Gn/Bn

)

OUTRn/Gn/Bn is forced off even if GS data is greater than 0FFh.

OUTRn/Gn/Bn does not turn on again until XBLNK goes low.

PWM 10-Bit Mode

(FC Bit 1/0 = 1/0)

OFF (V

OUTXnH

)

OUTRn/Gn/Bn

(GSDATA = FFFh)

ON (V

OUTRn/Gn/Bn

)

T = GSCKR/G/B

´

1023

OUTRn/Gn/Bn is forced off even if GS data are greater than 3FFh.

OUTRn/Gn/Bn does not turn on again until XBLNK goes low.

PWM 12-Bit Mode

(FC Bit 1/0 = 0/X)

OFF (V

OUTXnH

)

T = GSCKR/G/B

´

4095

OUTRn/Gn/Bn

(GSDATA = FFFh)

ON (V

OUTRn/Gn/Bn

)

4095

4096

4097

¼


1 2 3 4

¼

PWM Counter 8-, 10-, or 12-Bit Mode With Auto Repeat

XBLNK

GSCKR

GSCKG

GSCKB

1 2 3

¼

¼

256

255 257

¼

¼

1023

1024

1025

¼

¼

4095

4096

1 2

¼

GS counter starts to count GSCKR/G/B after XBLNK goes high.

PWM 8-Bit Mode

(FC Bit 1/0 = 1/1)

OUTRn/Gn/Bn

(GSDATA = 0FFh to FFFh)

OFF

T =

GSCKR/G/B 255

´

ON

OUTRn/Gn/Bn is forced off even if

GS data are greater than 0FFh.

T = GSCKR/G/B 1

´ x2 of off period is generated.

x11 of off period is generated.

PWM 10-Bit Mode

(FC Bit 1/0 = 1/0)

OUTRn/Gn/Bn

(GSDATA = 3FFh to FFFh)

OFF

ON

T = GSCKR/G/B

´

1023

¼

4095

4096

1 2

¼

¼

4095

4096

1 2

¼ x15 of off period is generated.

¼

OUTRn/Gn/Bn is forced off even if

GS data are greater than 3FFh.



PWM 12-Bit Mode

(FC Bit 1/0 = 0/X)

OUTRn/Gn/Bn

(GSDATA = FFFh)

OFF

ON

T = GSCKR/G/B

´

4095


1

26



TLC5951



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REGISTER AND DATA LATCH CONFIGURATION

The TLC5951 has two data latches to store information: the grayscale (GS) data latch and the DC/BC/FC/UD data latch. The GS data latch can be written as 288-bit data through GSSIN with GSSCK. The DC/BC/FC/UD data latch can be written as data through DCSIN with DCSCK. Also, DC/BC/FC data can be written to the

DC/BC/FC/UD data latch through GSSIN with GSSCK. UD data are written to the upper 17 bits of the 216-bit

DC/BC/FC/UD shift register at the same time. The data in the DC/BC/FC/UC data latch can be read via

GSSOUT with GSSCK.

Figure 44

shows the grayscale shift register and data latch configuration.

From LSD/LOD/TEF Data Holder

288-Bit Common Shift Register

49

These 49 bits of data are loaded into the upper 49 bits of the 288-bit shift register when GSLAT is low at the last GSSCK rising edge before the rising edge of GSLAT.

From 216-Bit DC/BC/FC/UD Data Latch

216

These 216 bits of data are loaded into the lower 216 bits of the 288-bit shift register when

GSLAT is low at the last GSSCK rising edge before the rising edge of GSLAT.

GSSOUT

MSB

Common

Data Bit

287

Common

Data Bit

286

Common

Data Bit

285

Common

Data Bit

284

Common

Data Bit

283

Common

Data Bit

282

¼

Common

Data Bit

5

Common

Data Bit

4

Common

Data Bit

3

Common

Data Bit

2

LSB

Common

Data Bit

1

Common

Data Bit

0

GSSIN

GSSCK

DCSOUT

Lower 216 Bits of 288 Bits

MSB

287 276

OUTB7

Bit 11

¼

OUTB7

Bit 0

GS Data for OUTB7

¼

47 36

288

35

288

24

Grayscale Data Latch (12 Bits

´

24 Channels)

23

12 11

LSB

0

OUTR1

Bit 11

¼

OUTR1

Bit 0

OUTB0

Bit 11

¼

OUTB0

Bit 0

OUTG0

Bit 11

¼

OUTG0

Bit 0

OUTR0

Bit 11

¼

OUTR0

Bit 0

GS Data for OUTR1 GS Data for OUTB0 GS Data for OUTG0 GS Data for OUTR0

288

Upper 17 Bits of 216 Bits

To PWM Timing Control Block for Each Color

These 17 bits of data are loaded into the upper 17 bits of the 216-bit shift register when GSLAT is high at the last GSSCK rising edge before the GSLAT rising edge. The other bits remain unchanged.

216-Bit DC/BC/FC/UD Shift Register

MSB

215 214

Data

Bit 215

Data

Bit 214

¼

¼

197 196

Data

Bit 197

Data

Bit 196

195

Data

Bit 195

¼

5

Data

Bit 5

4

Data

Bit 4

3

Data

Bit 3

2

Data

Bit 2

1

Data

Bit 1

0

Data

Bit 0

DCSIN

DCSCK

This latch pulse is generated when GSLAT is low at the last GSSCK rising edge before the

GSLAT rising edge.

Lower 199 Bits of 216 Bits

These 199 bits of data are loaded into the lower 199 bits of the

216-bit shift register when GSLAT is high at the last GSSCK rising edge before the GSLAT rising edge. The User Defined bit data in the 216-bit data latch remain unchanged.

216

These 216 bits of data are automatically loaded into the

216-bit data latch by the latch pulse generated 3ms-7ms after the DCSCK rising edge is not input.

216-Bit DC/BC/FC/UD Data Latch

MSB

215-199

User

Defined

Bits 16-0

198-192

FUNC

Bits 6-0

191-184 183-176 175-168 167-161 160-154 153-147

BRIGHT

Bits 7-0

OUTB0-7

BRIGHT

Bits 7-0

OUTG0-7

BRIGHT

Bits 7-0

OUTR0-7

DOTCOR

Bits 6-0

OUTB7

DOTCOR

Bits 6-0

OUTG7

DOTCOR

Bits 6-0

OUTR7

¼

27-21 20-14 13-7

LSB

6-0

DOTCOR

Bits 6-0

OUTR1

DOTCOR

Bits 6-0

OUTB0

DOTCOR

Bits 6-0

OUTG0

DOTCOR

Bits 6-0

OUTR0

Function

Control

Global Brightness Control Dot Correction

216

Dot Correction (7 Bits

´

24 Channels)/

Global Brightness Control (8 Bits 3 Group)/

´

Function Control (7 Bits)

User Defined (17 Bits)

This latch pulse is generated when

GSLAT is high at the last GSSCK rising edge before the GSLAT rising edge. Otherwise, the latch pulse is generated 3 ms to 7 ms after the DCSCK rising edge.

7 24 216 171

To GS Counter/PWM Timing

Control Block

To Global Brightness

Control Block

To 288-Bit Common

Shift Register

To Dot Correction

Control Block

Figure 44. Grayscale Shift Register and Data Latch Configuration



TLC5951


27

TLC5951


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The 288-bit common shift register is used to shift data from the GSSIN pin into the TLC5951. The data shifted into this register are used for grayscale data, global brightness control, and dot correction data. The register LSB is connected to GSSIN and the MSB is connected to GSSOUT. On each GSSCK rising edge, the data on GSSIN are shifted into the register LSB and all 288 bits are shifted towards the MSB. The register MSB is always connected to GSSOUT.

The level of GSLAT at the last GSSCK before the GSLAT rising edge determines which latch the data are transferred into. When GSLAT is low at the last GSSCK rising edge, all 288 bits are latched into the grayscale data latch. When GSLAT is high at the last GSSCK rising edge, bits 0-198 are copied to bits 0-198 in the

DC/BC/FC/UD data latch and bits 199-215 are copied to bits 199-215 in the 216-bit DC/BC/FC/UD shift register at the GSLAT rising edge. To avoid data from being corrupted, the GSLAT rising edge must be input more than

7 ms after the last DCSCK for a DC/BC/FC/UD data write. When the IC powers on, the 288-bit common shift register contains random data.

Grayscale Data Latch

The grayscale (GS) data latch is 288 bits long. This latch contains the 12-bit PWM grayscale value for each of the TLC5951 constant-current outputs. The PWM grayscale values in this latch set the PWM on-time for each constant-current driver. See

Table 6

for the on-time duty of each GS data bit.

Figure 45

shows the shift register and latch configuration. Refer to

Figure 10

for the timing diagram for writing data into the GS shift register and latch.

Data are latched from the 288-bit common shift register into the GS data latch at the rising edge of the GSLAT pin. The conditions for latching data into this register are described in the

288-Bit Common Shift Register

section.

When data are latched into the GS data latch, the new data are immediately available on the constant-current outputs. For this reason, data should only be latched when XBLNK is low. If data are latched with XBLNK high, the outputs may turn on or off unexpectedly.

MSB

287 276

OUTB7

Bit 11

¼

OUTB7

Bit 0

GS Data for OUTB7

¼

47 36 35 24 23 12 11

LSB

0

OUTR1

Bit 11

¼

OUTR1

Bit 0

OUTB0

Bit 11

¼

OUTB0

Bit 0

OUTG0

Bit 11

¼

OUTG0

Bit 0

OUTR0

Bit 11

¼

OUTR0

Bit 0

GS Data for OUTR1 GS Data for OUTB0 GS Data for OUTG0 GS Data for OUTR0

Figure 45. Grayscale Data Latch Configuration

28



TLC5951



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When the IC powers on, the grayscale data latch contains random data. Therefore, grayscale data must be written to the 288-bit common shift register and latched into the GS data latch before turning on the constant-current outputs. XBLNK should be low when powering on the TLC5951 to force all outputs off until the internal registers can be programmed. All constant-current outputs are forced off when XBLNK is low. The data bit assignment is shown in

Table 7

.

BITS

11-0

23-12

35-24

47-36

59-48

71-60

83-72

95-84

107-96

119-108

131-120

143-132

Table 7. Grayscale Data Bit Assignment

DATA

OUTR0

OUTG0

OUTB0

OUTR1

OUTG1

OUTB1

OUTR2

OUTG2

OUTB2

OUTR3

OUTG3

OUTB3

BITS

155-144

167-156

179-168

191-180

203-192

215-204

227-216

239-228

251-240

263-252

275-264

287-276

DATA

OUTR4

OUTG4

OUTB4

OUTR5

OUTG5

OUTB5

OUTR6

OUTG6

OUTB6

OUTR7

OUTG7

OUTB7

DC/BC/FC/UD Shift Register

The 216-bit DC/BC/FC/UD shift register is used to shift data from the DSSIN pin into the TLC5951. The data shifted into this register are used for the dot correction (DC), global brightness control (BC), function control (FC), and user-defined (UD) data latches. Each of these latches is described in the following sections. The register

LSB is connected to DCSIN and the MSB is connected to DCSOUT. On each DCSCK rising edge, the data on

DCSIN are shifted into the register LSB and all 216 bits are shifted towards the MSB. The register MSB is always connected to DCOUT. When the IC is powered on, the 216-bit DC/BC/FC/UD shift register contains random data.

DC/BC/FC/UD Data Latch

The 216-bit DC/BC/FC/UD data latch contains dot correction (DC) data, global brightness control (BC) data, function control (FC) data, and user-defined (UD) data. Data can be written into this latch from the DC/BC/FC/UD shift register. Furthermore, DC/BC/FC data can be written into this latch from the 288-bit common shift register.

At this time, UD data are written to bits 199-215 in the 216-bit DC/BC/FC/UD shift register data latch. When the

IC is powered on, the DC/BC/FC/UD data latch contains random data.

MSB

215-199

User

Defined

Bits 16-0

198-192 191-184

FUNC

Bits 6-0

BRIGHT

Bits 7-0

OUTB0-7

183-176 175-168 167-161 160-154 153-147 146-140

BRIGHT

Bits 7-0

OUTG0-7

BRIGHT

Bits 7-0

OUTR0-7

DOTCOR

Bits 6-0

OUTB7

DOTCOR

Bits 6-0

OUTG7

DOTCOR

Bits 6-0

OUTR7

DOTCOR

Bits 6-0

OUTB6

¼

27-21 20-14 13-7

LSB

6-0

DOTCOR

Bits 6-0

OUTR1

DOTCOR

Bits 6-0

OUTB0

DOTCOR

Bits 6-0

OUTG0

DOTCOR

Bits 6-0

OUTR0

User

Defined

Function

Control

Global Brightness Control Dot Correction

Figure 46. DC/BC/FC/UD Data Latch Configuration

Dot Correction Data Latch

The dot correction (DC) data latch is 168 bits long. The DC data latch consists of bits 0-167 in the DC/BC/FC/UD data latch. This latch contains the 7-bit DC value for each of the TLC5951 constant-current outputs. Each DC value individually adjusts the output current for each constant-current driver. As explained in the

Dot Correction

(DC) Function

section, the DC values are used to adjust the output current from 0% to 66.7% of the maximum value when the dot correction low adjustment range is selected and from 33.3% to 100% of the maximum value when the dot correction high adjustment range is selected. The adjustment range is selected by the range control bits in the function control latch.



29


TLC5951

TLC5951


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Table 2

and

Table 3

show how the DC data affect the percentage of the maximum current each output. See

Figure 46

for the DC data latch configuration.

Figure 11

illustrates the timing diagram for writing data from the GS data path into the shift registers and latches.

Figure 12

illustrates the timing diagram for writing data from the DC data path into the shift registers and DC latches. DC data are automatically latched from the DC/BC/FC/UD shift register into the DC data latch with an internal latch signal. The internal latch signal is generated in 3 ms to 7 ms after the last DCSCK rising edge.

When the IC powers on, the DC data latch contains random data. Therefore, DC data must be written into the

TLC5951 and latched into the DC data latch before turning on the constant-current outputs. XBLNK should be low when powering on the TLC5951 to force all outputs off until the internal registers can be programmed. All constant-current outputs are forced off when XBLNK is low. The data bit assignment is shown in

Table 8 .

BITS

6-0

13-7

20-14

27-21

34-28

41-35

48-42

55-49

62-56

69-63

76-70

83-77

Table 8. Dot Correction Data Bit Assignment

DATA

OUTR0

OUTG0

OUTB0

OUTR1

OUTG1

OUTB1

OUTR2

OUTG2

OUTB2

OUTR3

OUTG3

OUTB3

BITS

90-84

97-91

104-98

111-105

118-112

125-119

132-126

139-133

146-140

153-147

160-154

167-161

DATA

OUTR4

OUTG4

OUTB4

OUTR5

OUTG5

OUTB5

OUTR6

OUTG6

OUTB6

OUTR7

OUTG7

OUTB7

Global Brightness Control Data Latch

The global brightness control (BC) data latch is 24 bits long. The BC data latch consists of bits 168-191 in the

DC/BC/FC/UD data latch.

The data of the BC data latch are used to adjust the constant-current values for eight channel constant-current drivers of each color group. The current can be adjusted from 0% to 100% of each output current adjusted by brightness control with 8-bit resolution.

Table 4

describes the percentage of the maximum current for each brightness control data.

When the IC is powered on, the data in the BC data latch are not set to a specific default value. Therefore, brightness control data must be written to the BC latch before turning on the constant-current output. The data bit assignment is shown in

Table 9 .

BITS

175-168

183-176

191-184

Table 9. Data Bit Assignment

GLOBAL BRIGHTNESS CONTROL DATA BITS 6-0

OUTR0-OUTR7 group

OUTG0-OUTG7 group

OUTB0-OUTB7 group

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TLC5951



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Function Control Data Latch

The function control (FC) data latch is 7 bits in length and is used to select the dot correction adjustment range, grayscale counter mode, enabling of the auto display repeat, and display timing reset function. When the IC is powered on, the data in the FC latch are not set to a specific default value. Therefore, function control data must be written to the FC data latch before turning on the constant current output.

BIT

192

193

194

195

196

198, 197


DESCRIPTION

Dot correction adjustment range for the RED color output (0 = lower range, 1 = higher range).

When this bit is '0', dot correction can control the range of constant current by 0% to 66.7% (typ) of the maximum current set by an external resistor. This mode only operates the output for the red LED driver group.

When this bit is '1', dot correction can control the range of constant current by 33.3% (typ) to 100% of the maximum current set by an external resistor.

Dot correction adjustment range for the GREEN color output (0 = lower range, 1 = higher range).

When this bit is '0', dot correction can control the range of constant current by 0% to 66.7% (typ) of the maximum current set by an external resistor. This mode only operates the output for the green LED driver group.


Dot correction adjustment range for the BLUE color output (0 = lower range, 1 = higher range).

When this bit is '0', dot correction can control the range of constant current by 0% to 66.7% (typ) of the maximum current set by an external resistor. This mode only operates the output for the blue LED driver group.


Auto display repeat mode (0 = disabled, 1 = enabled).

When this bit is '0', the auto repeat function is disabled. Each output driver is turned on and off once after XBLNK goes high.

When this bit is '1', each output driver is repeatedly toggled on/off every 4096th grayscale clock without the XBLNK level changing when the GS counter is configured as a 12-bit mode. If the GS counter is configured as a 10-bit mode, the outputs continue to cycle on/off every 1024th grayscale clock. If the GS counter is set to the 8-bit mode, the output on/off repetition cycles every 256th grayscale clock.

Display timing reset mode (0 = disabled, 1 = enabled).

When this bit is '1', the GS counter is reset to '0' and all outputs are forced off at the GSLAT rising edge for a GS data write.

This function is identical to the low pulse of the XBLNK signal when input. Therefore, the XBLNK signal is not needed to control from a display controller. PWM control starts again from the next input GSCKR/G/B rising edge.

When this bit is '0', the GS counter is not reset and no outputs are forced off even if a GSLAT rising edge is input. In this mode, the XBLNK signal should be input after the PWM control of all LED are finished. Otherwise, the PWM control might be not exact.

Grayscale counter mode select, bits 1-0.

The grayscale counter mode is selected by the setting of bits 1 and 0.

Table 11

shows the GS counter mode.

Table 11. GS Counter Mode Truth Table

GRAYSCALE COUNTER MODE

BIT 1 BIT 0

0

1

1

X (don't care)

0

1

FUNCTION MODE

12-bit counter mode (maximum output on-time = 4095 × GS clock)



The grayscale data latch bit length is always 288 bits in any grayscale counter mode. All constant-current outputs are forced off at the 256th grayscale clock in the 8-bit mode even if all grayscale data are FFFh. In 10-bit mode, all outputs are forced off at 1024th grayscale clock even if all grayscale data are FFFh.



TLC5951


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User-Defined Data Latch

The user-defined (UD) data latch is 17 bits in length and is not used for any device functionality. However, these data can be used for communication between a controller connected to DCSIN and another controller connected to GSSIN. When the IC is powered on, the data in the UD latch are not set to a specific default value.

BITS

215-199


USER-DEFINED DATA BITS

16-0

STATUS INFORMATION DATA (SID)

Status information data (SID) are 288 bits in length and are read-only data. SID consists of the LED open detection (LOD) error, LED short detection (LSD), thermal error flag (TEF), and the data in the DC/BC/FC/UD data latch. The SID are shifted out onto GSSOUT with the GSSCK rising edge after GSLAT is input for a GS data write. These SID are loaded into the 288-bit common shift register after data in the 288-bit common shift register are copied to the data latch.

LOD/LSD Data Latch (48 Bits)

LOD

Data of

OUTB7

¼

LOD

Data of

OUTR0

LSD

Data of

OUTB7

¼

LSD

Data of

OUTR0

TEF

MSB

User

Defined

Bits 16-0

Function

Control

Bits 6-0

BC Data of

OUTBn

¼

216-Bit DC/BC/FC/UD Data Latch

BC Data of

OUTRn

BC Data of

OUTB7

¼

LSB

BC Data of

OUTR0

17 7

GSSOUT

Common

Data Bit

287

¼

Common

Data Bit

264

MSB

Common

Data Bit

263

¼

Common

Data Bit

240

Common

Data Bit

239

(Reserved Data)

Common

Data Bit

238-216

Common

Data Bit

215-199

Common

Data Bit

198-192

Common

Data Bit

191

¼

Common

Data Bit

168

Common

Data Bit

167

¼

Common

Data Bit

0

LSB


Figure 47. DC/BC/FC Data Load Assignment

GSSIN

GSSCK

32



TLC5951


TLC5951

62-56

69-63

76-70

83-77

90-84

97-91

104-98

111-105

118-112

125-119

BITS

6-0

13-7

20-14

27-21

34-28

41-35

48-42

55-49

132-126

139-133

146-140

153-147

160-154

167-161

175-168

183-176

191-184

198-192

215-199

238-216

239

www.ti.com

.........................................................................................................................................................


247-240

255-248

263-256

271-264

279-272

287-280


DESCRIPTION

Dot correction data bits 6-0 for OUTR0

Dot correction data bits 6-0 for OUTG0

Dot correction data bits 6-0 for OUTB0






















Global brightness control data bits 6-0 for OUTR0-OUTR7 group

Global brightness control data bits 6-0 for OUTG0-OUTG7 group

Global brightness control data bits 6-0 for OUTB0-OUTB7 group

Function control data bits 6-0

User-defined data bits 16-0

Reserved for TI test

Thermal error flag (TEF)

1 = High temperature condition, 0 = Normal temperature condition

LED short detection (LSD) data for OUTR7-OUTR0

1 = LED is short, 0 = Normal operation

LSD data for OUTG7-OUTG0


LSD data for OUTB7-OUTB0


LED open detection (LOD) data for OUTR7-OUTR0

1 = LED is open or connected to GND, 0 = Normal operation

LOD data for OUTG7-OUTG0


LOD data for OUTB7-OUTB0




TLC5951


33

TLC5951


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CONTINUOUS BASE LOD, LSD, AND TEF

The LOD data are updated at the rising edge of the 33rd GSCKR/G/B pulse after XBLNK goes high; LOD/LSD data are retained until the next 33rd GSCKR/G/B. LOD/LSD data are only checked for outputs that are turned on during the rising edge of the 33rd GSCKR/G/B pulse. A '1' in an LOD bit indicates an open LED or shorted LED to GND condition for the corresponding output. A '0' indicates normal operation. It is possible for LOD/LSD data to show a '0' even if the LED is open when the grayscale data are less than 20h (32d).

The TEF bit indicates that the IC temperature is too high. The TEF flag also indicates that the IC has turned off all drivers to avoid damage by overheating the device. A '1' in the TEF bit means that the IC temperature has exceeded the detect temperature threshold (T

TEF

) and all outputs are turned off. A '0' in the TEF bit indicates normal operation with normal temperature conditions.

The IC automatically turns the drivers back on when the IC temperature decreases to less than (T

TEF

– T

HYST

).

When the IC is powered on, LOD/LSD data do not show correct values. Therefore LOD/LSD data must be read from the 33rd GSCKR/G/B pulse input after XBLNK goes high.

Table 14

shows a truth table for LOD/LSD and

TEF.

SID DATA

0

1

Table 14. LOD/LSD/TEF Truth Table

LED OPEN DETECTION (LODn)

CONDITION

LED SHORT DETECTION (LSDn)

LED is not opened

(V

OUTRn/Gn/Bn

> V

LOD

)

LED is open or shorted to GND

(V

OUTRn/Gn/Bn

≤ V

LOD

)

(V

LED is not shorted

OUTRn/Gn/Bn

≤ V

LSD

)

LED is shorted between anode and cathode or shorted to higher voltage side

(V

OUTRn/Gn/Bn

> V

LSD

)

THERMAL ERROR FLAG (TEF)

Device temperature is lower than high-side detect temperature

(Temperature ≤T

TEF

)

Device temperature is higher than high-side detect temperature and driver is forced off

(Temperature > T

TEF

)

XBLNK

(1)

1 2 3 4 30 31 32 33 34 35

4094

4093

4096

4095

1 2 3 30 31 32 33 34 35

GSCKR

GSCKG

GSCKB

1st GSCLK Period

OFF

OUTRn/Gn/Bn

(Data = FFFh)

GND

ON

V

OUTRn/Gn/Bn If the OUTRn/Gn/Bn voltage (V

OUTRn/Gn/Bn

) is less than VLOD (0.25 V, typ) at the rising edge of the 33rd

GSCKR/G/B after the rising edge of XBLNK or internal blank, the LOD sets the SID bit corresponding to the output equal to ‘1’.

Also, i f the OUTRn/Gn/Bn voltage is greater than than VLSD (2.5 V, typ) at the rising edge of the 33rd

GSCKR/G/B after the falling edge of XBLNK or internal blank, the LSD sets the SID bit equal to ‘1’.

New LOD/LSD Data

LOD/LSD Data Latch

(Internal)

Old LOD/LSD Data

(1) The internal blank signal is generated when GSLAT is input for GS data with display timing reset enabled. Also, the signal is generated at the 4096th GSCK when auto repeat mode is enabled. XBLNK can be connected to VCC when the display timing reset or auto repeat is enabled.

Figure 48. LED Open Detection (LOD) LED Shorted Detection Data Update Timing

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THERMAL SHUTDOWN AND THERMAL ERROR FLAG

The thermal shutdown (TSD) function turns off all constant-current outputs on the IC when the junction temperature (T

J

) exceeds the threshold (T

TEF

= +163°C, typ) and sets the thermal error flag (TEF) to '1'. All outputs are latched off when TEF is set to '1' and remain off until the next grayscale cycle after XBLNK goes high and the junction temperature drops below (T

TEF

– T

HYST

). TEF remains as '1' until GSLAT is input with low temperature. TEF is set to '0' once the junction temperature drops below (T

TEF

– T

HYST

), but the output does not turn on until the first GSCKR/G/B in the next display period even if TEF is set to '0'.

GSLAT

GSCK

Grayscale

Data Latch

XBLNK

(1)

Old Latched GS Data New Latched GS Data

1 2 3 4

4094

4093

4096

4095 1 2 3

GSCKR/G/B

IC Junction

T < T

J (TEF) T

J

³

T

(TEF)

T < T

J (TEF)

-

T

(HYS) T

J

³

T

(TEF)

The TEF bit of SID is rest to ‘0’ at the rising edge of GSSCK after the falling edge of GSLAT for a GS data write.

'1'

TEF in SID

(Internal Data)

'0' '0'

OFF

OUTRn/Gn/Bn is forced off when T exceeds T

(TEF)

.

Also, the TEF bit is set to ‘1’ at the same time.

OFF

OUTRn/Gn/Bn ON ON

OUTRn/Gn/Bn is turned off at the rising edge of GSCKR/G/B after the rising edge of XBLNK.

(1) The following internal signal also works to turn the constant outputs on as same as XBLNK inputting. The internal blank signal is generated when GSLAT is input for GS data with display timing reset enabled. Also, the signal is generated at the 4096th GSCKR/G/B when auto repeat mode is enabled. XBLNK can be connected to VCC when the display timing reset or auto repeat is enabled.

Figure 49. TEF/TSD Timing

NOISE REDUCTION

Large surge currents may flow through the IC and the board on which the device is mounted if all 24 outputs turn on simultaneously at the start of each grayscale cycle. These large current surges could induce detrimental noise and electromagnetic interference (EMI) into other circuits. The TLC5951 turns the outputs on in a series delay for each group independently to provide a circuit soft-start feature. The output current sinks are grouped into four groups in each color group. For example, for the RED color output, the first grouped outputs that are turned on/off are OUTR0 and OUTR4. The second grouped outputs that are turned on/off are OUTR1 and OUTR5. The third grouped outputs are OUTR2 and OUTR6 and the fourth grouped outputs are OUTR3 and OUTR7. Each grouped output is turned on and off sequentially with a small delay between groups. However, each color output on and off is controlled by the color grayscale clock.



TLC5951


35

TLC5951


www.ti.com

Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Original (March 2009) to Revision A .......................................................................................................

Page

•

Changed T

SU3

•

Changed V

O

•

Changed I

OH minimum specification to 40 ns in the Recommended Operating Conditions table

....................................... 3

minimum specification to maximum specification in the Recommended Operating Conditions table

.............. 3


............. 3

•

Changed I

OL

•

Changed I

OLC

minimum specification to maximum specification in the Recommended Operating Conditions table .............. 3


............ 3

•

Changed f

CLK (SCLK)


•

Changed f

CLK (GSCKR/G/B) minimum specification to maximum specification in the Recommended Operating Conditions

.... 3

table

....................................................................................................................................................................................... 3

•

Changed I

CC2

•

Changed I

CC3

typical value to 6 mA in the Electrical Characteristics table ............................................................................ 4

typical value to 12 mA and maximum value to 27 mA in the Electrical Characteristics table

......................... 4

•

Changed I

CC4 typical value to 21 mA and maximum value to 55 mA in the Electrical Characteristics table

•

Changed ΔI

OLC2 typical value to ±1% in the Electrical Characteristics table

......................... 4

......................................................................... 4

•

Changed

ΔI

OLC3

•

Changed t

R0

typical value to ±0.5% in the Electrical Characteristics table

typical value to 6 ns in the Switching Characteristics table

...................................................................... 4

.............................................................................. 6

•

Changed t

F0 typical value to 6 ns in the Switching Characteristics table

.............................................................................. 6

•

Changed fourth paragraph of Maximum Constant Sink Current Value section to reference correct graph ........................ 21

•

Changed DC function adjustment range description to reflect proper adjustment range for each control in Dot

Correction (DC) Function section

........................................................................................................................................ 21

•

Changed brightness control to dot correction data in 288-Bit Common Shift Register section

........................................... 28

•

Corrected number of bits contained within the DC/BC/FC/UD shift register in the DC/BC/FC/UD Shift Register section .. 29

•

Corrected typo about which bits are written in the DC/BC/FC/UD Data Latch section

....................................................... 29

•

Corrected percentage of adjustment rage selected in the Dot Correction Data Latch section

........................................... 29

•

Deleted second paragraph of Status Information Data (SID) section .................................................................................. 32

•

Updated LOD bit = '1' condition description in the Continuous Base LOD, LSD, and TEF section .................................... 34

36



TLC5951


PACKAGE OPTION ADDENDUM

9-Apr-2009 www.ti.com

PACKAGING INFORMATION

Orderable Device

TLC5951DAP

TLC5951DAPR

Status

(1)

ACTIVE

ACTIVE

Package

Type

HTSSOP

HTSSOP

Package

Drawing

DAP

DAP

Eco Plan

(2)

Pins Package

Qty

38 40 Green (RoHS & no Sb/Br)

Lead/Ball Finish MSL Peak Temp

(3)

CU NIPDAU Level-3-260C-168 HR

38 2000 Green (RoHS & no Sb/Br)

CU NIPDAU Level-3-260C-168 HR

(1)

The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2)

Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

(3)

MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

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In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 1

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