TMS320C6204

D

High-Performance Fixed-Point Digital

Signal Processor (DSP) − TMS320C6204

− 5-ns Instruction Cycle Time

− 200-MHz Clock Rate

− Eight 32-Bit Instructions/Cycle

− 1600 MIPS

D

C6204 GLW Ball Grid Array (BGA) Package is Pin-Compatible With the C6202/02B/03

GLS BGA Package

†

D

VelociTI



Advanced Very-Long-Instruction-

Word (VLIW) TMS320C62x



DSP Core

− Eight Highly Independent Functional

Units:

− Six ALUs (32-/40-Bit)

− Two 16-Bit Multipliers (32-Bit Result)

− Load-Store Architecture With 32 32-Bit

General-Purpose Registers

− Instruction Packing Reduces Code Size

− All Instructions Conditional

D

Instruction Set Features

− Byte-Addressable (8-, 16-, 32-Bit Data)

− 8-Bit Overflow Protection

− Saturation

− Bit-Field Extract, Set, Clear

− Bit-Counting

− Normalization

D

1M-Bit On-Chip SRAM

− 512K-Bit Internal Program/Cache

(16K 32-Bit Instructions)

− 512K-Bit Dual-Access Internal Data

(64K Bytes)

− Organized as Two 32K-Byte Blocks for

Improved Concurrency

D

32-Bit External Memory Interface (EMIF)

− Glueless Interface to Synchronous

Memories: SDRAM or SBSRAM

− Glueless Interface to Asynchronous

Memories: SRAM and EPROM

− 52M-Byte Addressable External Memory

Space

SPRS152C − OCTOBER 2000 − REVISED MARCH 2004

D

Four-Channel Bootloading

Direct-Memory-Access (DMA) Controller

With an Auxiliary Channel

D

32-Bit Expansion Bus (XB)

− Glueless/Low-Glue Interface to Popular

PCI Bridge Chips

− Glueless/Low-Glue Interface to Popular

Synchronous or Asynchronous

Microprocessor Buses

− Master/Slave Functionality

− Glueless Interface to Synchronous FIFOs and Asynchronous Peripherals

D

Two Multichannel Buffered Serial Ports

(McBSPs)

− Direct Interface to T1/E1, MVIP, SCSA

Framers

− ST-Bus-Switching Compatible

− Up to 256 Channels Each

− AC97-Compatible

− Serial-Peripheral Interface (SPI)

Compatible (Motorola



)

D

Two 32-Bit General-Purpose Timers

D

Flexible Phase-Locked-Loop (PLL) Clock

Generator

D

IEEE-1149.1 (JTAG

‡

)

Boundary-Scan-Compatible

D

288-Pin MicroStar BGA



Package (GHK)

D

340-Pin BGA Package (GLW)

D

0.15-

µ

m/5-Level Metal Process

− CMOS Technology

D

3.3-V I/Os, 1.5-V Internal

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

VelociTI, TMS320C62x, and MicroStar BGA are trademarks of Texas Instruments.

Motorola is a trademark of Motorola, Inc.

† For more details, see the GLW BGA package bottom view.

‡ IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture.

! "#$ ! %#&'" ($)

(#"! " !%$""! %$ *$ $! $+! !#$!

!(( ,-) (#" %"$!!. ($! $"$!!'- "'#($

$!. '' %$$!)

POST OFFICE BOX 1443

•

HOUSTON, TEXAS 77251−1443

Copyright



2004, Texas Instruments Incorporated

1


Table of Contents

GHK and GLW BGA packages (bottom view) . . . . . . . . . . 3 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . device characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4

4

C62x device compatibility . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 functional and CPU (DSP core) block diagram . . . . . . . . . 7

CPU (DSP core) description memory map summary

. . . . . . . . . . . . . . . . . . . . . . . .

. . . . . . . . . . . . . . . . . . . . . . . . . . . .

8

10 peripheral register descriptions . . . . . . . . . . . . . . . . . . . . .

DMA channel synchronization events . . . . . . . . . . . . . . .

11

16 interrupt sources and interrupt selector . . . . . . . . . . . . . . 17 signal groups description . . . . . . . . . . . . . . . . . . . . . . . . . . 18 signal descriptions development support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

21

31 documentation support clock PLL

. . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

34

35 power-down mode logic . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 power-supply sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . 38 absolute maximum ratings over operating case temperature ranges . . . . . . . . . . . . . . . . . . . . . . . . . . 39 recommended operating conditions . . . . . . . . . . . . . . . . . 39 electrical characteristics over recommended ranges of supply voltage and operating case temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 parameter measurement information . . . . . . . . . . . . . . . 41 input and output clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 asynchronous memory timing . . . . . . . . . . . . . . . . . . . . . 45 synchronous-burst memory timing . . . . . . . . . . . . . . . . . 48 synchronous DRAM timing . . . . . . . . . . . . . . . . . . . . . . . . 50

HOLD/HOLDA timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 reset timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 external interrupt timing . . . . . . . . . . . . . . . . . . . . . . . . . . 57 expansion bus synchronous FIFO timing . . . . . . . . . . . . 58 expansion bus asynchronous peripheral timing . . . . . . 60 expansion bus synchronous host-port timing . . . . . . . . 63 expansion bus asynchronous host-port timing . . . . . . . 69

XHOLD/XHOLDA timing . . . . . . . . . . . . . . . . . . . . . . . . . . 71 multichannel buffered serial port timing . . . . . . . . . . . . . 73

DMAC, timer, power-down timing . . . . . . . . . . . . . . . . . . 85

JTAG test-port timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

2


•



GHK and GLW BGA packages (bottom view)

GHK 288-PIN BALL GRID ARRAY (BGA) PACKAGE ( BOTTOM VIEW )

P

N

M

L

K

J

H

G

F

E

D

C

B

A

W

V

U

T

R

1 3

2 4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

GLW 340-PIN BGA PACKAGE ( BOTTOM VIEW )

AB

Y

AA

W

V

U

T

R

P

N

M

L

K

J

H

G

F

E

D

C

B

A

1

2

3 5

4 6

7

8

9 11

10 12

13

14

15 17

16 18

19

20

21

22

The C6204 GLW BGA package is pin-compatible with the C6202/02B/03 GLS package except that the inner row of balls (which are additional power and ground pins) are removed for the C6204 GLW package.

These balls are NOT applicable for the C6204 devices 340-pin GLW BGA package.


•


3


description

The TMS320C62x



DSPs (including the TMS320C6204 device) compose the fixed-point DSP generation in the TMS320C6000



DSP platform. The TMS320C6204 (C6204) device is based on the high-performance, advanced VelociTI



very-long-instruction-word (VLIW) architecture developed by Texas Instruments (TI), making the C6204 an excellent choice for multichannel and multifunction applications.

With performance of up to 1600 million instructions per second (MIPS) at a clock rate of 200 MHz, the C6204 offers cost-effective solutions to high-performance DSP-programming challenges. The C6204 DSP possesses the operational flexibility of high-speed controllers and the numerical capability of array processors. This processor has 32 general-purpose registers of 32-bit word length and eight highly independent functional units.

The eight functional units provide six arithmetic logic units (ALUs) for a high degree of parallelism and two 16-bit multipliers for a 32-bit result. The C6204 can produce two multiply-accumulates (MACs) per cycle for a total of

400 million MACs per second (MMACS). The C6204 DSP also has application-specific hardware logic, on-chip memory, and additional on-chip peripherals.

The C6204 includes a large bank of on-chip memory and has a powerful and diverse set of peripherals. Program memory consists of a 64K-byte block that is user-configurable as cache or memory-mapped as program space.

Data memory consists of two 32K-byte blocks of RAM. The peripheral set includes two multichannel buffered serial ports (McBSPs), two general-purpose timers, a 32-bit expansion bus (XB) that offers ease of interface to synchronous or asynchronous industry-standard host bus protocols, and a glueless 32-bit external memory interface (EMIF) capable of interfacing to SDRAM or SBSRAM and asynchronous peripherals.

The C6204 has a complete set of development tools which includes: a new C compiler, an assembly optimizer to simplify programming and scheduling, and a Windows



debugger interface for visibility into source code execution.

device characteristics

1 provides an overview of the TMS320C6204, TMS320C6202/02B, and the TMS320C6203 pin-compatible C62x



DSPs. The table shows significant features of each device, including the capacity of on-chip RAM, the peripherals, the execution time, and the package type with pin count, etc. This data sheet primarily focuses on the functionality of the TMS320C6204 device although it also identifies to the user the pin-compatibility of the 6204 GLW and the C6202/02B and C6203 GLS BGA packages. For the functionality information on the TMS320C6202/02B devices, see the TMS320C6202, TMS320C6202B Fixed-Point Digital

Signal Processors Data Sheet (literature number SPRS104). For the functionality information on the

TMS320C6203 device, see the TMS320C6203 Fixed-Point Digital Signal Processor Data Sheet (literature number SPRS086). And for more details on the C6000



DSP device part numbers and part numbering, see

Table 14 and Figure 4.

4

TMS320C6000, C62x, and C6000 are trademarks of Texas Instruments.

Windows is a registered trademark of Microsoft Corporation.


•



device characteristics (continued)

Internal

Program

Memory

Table 1. Characteristics of the Pin-Compatible TMS320C6204 and C6202/02B/03B/03C DSPs

HARDWARE FEATURES

EMIF

Internal Data

Memory

DMA

Expansion Bus

McBSPs

32-Bit Timers

Size (Bytes)

Organization

Size (Bytes)

Organization

C6204

√

4-Channel With

Throughput

Enhancements

√

2

2

64K

1 Block:

64K-Byte

Cache/Mapped

Program

64K

2 Blocks:

Four 16-Bit Banks per Block

50/50 Split

C6202

√

4-Channel

√

3

2

256K

Block 0:

128K-Byte Mapped

Program

Block 1:

128K-Byte

Cache/Mapped

Program

128K

2 Blocks:


50/50 Split

C6202B

√

4-Channel With

Throughput

Enhancements

√

3

2

256K

Block 0:

128K-Byte Mapped

Program

Block 1:

128K-Byte

Cache/Mapped

Program

128K

2 Blocks:


50/50 Split

C6203B/C

√

4-Channel With

Throughput

Enhancements

√

3

2

384K

Block 0:

256K-Byte Mapped

Program

Block 1:

128K-Byte

Cache/Mapped Program

512K

2 Blocks:

Four 16-Bit Banks per

Block

50/50 Split

CPU ID +

Rev ID

Control Status Register

(CSR.[31:16])

0x0003 0x0002 0x0003 0x0003

Frequency

Cycle Time

Voltage

MHz ns

Core (V)

I/O (V)

200

5 ns (C6204-200)

1.5

3.3

200, 250

4 ns (C6202-250)

5 ns (C6202-200)

1.8

3.3

250

4 ns (C6202B-250)

1.5

250, 300 (03B)

300 (03C)

3.33 ns (C6203C-300)

3.33 ns (C6203B-300)

4 ns (C6203B-250)

1.2 (C6203C)

1.5 (C6203B)

1.7 (C6203BGLS Only)

3.3

x1, x4, x8, x10

(GJL Pkg)

PLL Options

CLKIN frequency multiplier

[Bypass (x1), x4, x6, x7, x8, x9, x10, and x11] x1, x4 (Both Pkgs) x1, x4 (Both Pkgs)

3.3

x1, x4, x8, x10

(GJL Pkg)

BGA

Process

Technology

Product

Status

27 x 27 mm

18 x 18 mm

16 x 16 mm

µ m

Product Preview (PP)

Advance Information (AI)

Production Data (PD)

−

340-pin GLW

288-pin GHK

0.15

µ m

PD

352-pin GJL

384-pin GLS

−

0.18

µ m

PD

All PLL Options

(GLS Pkg)

352-pin GJL

384-pin GLS

−

0.15

µ m

PP

All PLL Options

(GLS Pkg)

352-pin GNZ

384-pin GLS

384-pin GNY

−

0.15

µ m

PD


•


5


C62x



device compatibility

The TMS320C6202, C6202B, C6203, and C6204 devices are pin-compatible; thus, making new system designs easier and providing faster time to market. The following list summarizes the C62x



DSP device characteristic differences:

D

Core Supply Voltage (1.8 V versus 1.7 V, 1.5 V, 1.2 V)

The C6202 device core supply voltage is 1.8 V while the C6202B, C6203B, C6204 devices have core supply voltages of 1.5 V. The C6203B device (GLS package only) has a 1.7-V core supply voltage, and the C6203C device has a core supply voltage of 1.2 V.

D

PLL Options Availability

Table 1 identifies the available PLL multiply factors [e.g., CLKIN x1 (PLL bypassed), x4, etc.] for each of the

C62x



DSP devices. For additional details on the PLL clock module and specific options for the C6204 device, see the Clock PLL section of this data sheet.

For additional details on the PLL clock module and specific options for the C6202/02B/03 devices, see the

Clock PLL sections of the TMS320C6202, TMS320C6202B Fixed-Point Digital Signal Processors Data

Sheet (literature number SPRS104) and the TMS320C6203 Fixed-Point Digital Signal Processor Data

Sheet (literature number SPRS086).

D

On-Chip Memory Size

The C6202/02B, C6203, and C6204 devices have different on-chip program memory and data memory sizes (see Table 1).

D

McBSPs

The C6204 device has two McBSPs on-chip while the C6202, C6202B, C6203 devices have three McBSPs on-chip.

For a more detailed discussion on migration concerns, and similarities/differences between the C6202,

C6202B, C6203, and C6204 devices, see the How to Begin Development and Migrate Across the

TMS320C6202/6202B/6203/6204 DSPs Application Report (literature number SPRA603).

6


•



functional and CPU (DSP core) block diagram

SDRAM or

SBSRAM

SRAM

ROM/FLASH

I/O Devices

32

External Memory

Interface (EMIF)

C6204 Digital Signal Processor

Program

Access/Cache

Controller

Internal Program Memory

64K

Framing Chips:

H.100, MVIP,

SCSA, T1, E1

AC97 Devices,

SPI Devices,

Codecs

Timer 0

Timer 1

Multichannel

Buffered Serial

Port 0

Multichannel

Buffered Serial

Port 1

.L1

Data Path A

A Register File

.S1

C62x CPU (DSP Core)

Instruction Fetch

Instruction Dispatch

Instruction Decode

.M1

.D1

Data Path B

B Register File

.D2 .M2

.S2

.L2

Control

Registers

Control

Logic

Test

In-Circuit

Emulation

Interrupt

Control

Interrupt

Selector

Synchronous

FIFOs

I/O Devices

HOST CONNECTION

Master /Slave

TI PCI2040

Power PC

683xx

960

32

Expansion

Bus (XB)

32-Bit

Peripheral Control Bus

Data

Access

Controller

DMA

4-Ch With

Throughput

PLL

(x1, x4)

Power-

Down

Logic

Internal Data

Memory

64K

Boot Configuration


•


7


CPU (DSP core) description

The CPU fetches VelociTI



advanced very-long instruction words (VLIW) (256 bits wide) to supply up to eight

32-bit instructions to the eight functional units during every clock cycle. The VelociTI



VLIW architecture features controls by which all eight units do not have to be supplied with instructions if they are not ready to execute. The first bit of every 32-bit instruction determines if the next instruction belongs to the same execute packet as the previous instruction, or whether it should be executed in the following clock as a part of the next execute packet. Fetch packets are always 256 bits wide; however, the execute packets can vary in size. The variable-length execute packets are a key memory-saving feature, distinguishing the C62x CPU from other

VLIW architectures.

The CPU features two sets of functional units. Each set contains four units and a register file. One set contains functional units .L1, .S1, .M1, and .D1; the other set contains units .D2, .M2, .S2, and .L2. The two register files each contain 16 32-bit registers for a total of 32 general-purpose registers. The two sets of functional units, along with two register files, compose sides A and B of the CPU [see the functional and CPU (DSP core) block diagram and Figure 1]. The four functional units on each side of the CPU can freely share the 16 registers belonging to that side. Additionally, each side features a single data bus connected to all the registers on the other side, by which the two sets of functional units can access data from the register files on the opposite side. While register access by functional units on the same side of the CPU as the register file can service all the units in a single clock cycle, register access using the register file across the CPU supports one read and one write per cycle.

Another key feature of the C62x CPU is the load/store architecture, where all instructions operate on registers

(as opposed to data in memory). Two sets of data-addressing units (.D1 and .D2) are responsible for all data transfers between the register files and the memory. The data address driven by the .D units allows data addresses generated from one register file to be used to load or store data to or from the other register file. The

C62x CPU supports a variety of indirect addressing modes using either linear- or circular-addressing modes with 5- or 15-bit offsets. All instructions are conditional, and most can access any one of the 32 registers. Some registers, however, are singled out to support specific addressing or to hold the condition for conditional instructions (if the condition is not automatically “true”). The two .M functional units are dedicated for multiplies.

The two .S and .L functional units perform a general set of arithmetic, logical, and branch functions with results available every clock cycle.

The processing flow begins when a 256-bit-wide instruction fetch packet is fetched from a program memory.

The 32-bit instructions destined for the individual functional units are “linked” together by “1” bits in the least significant bit (LSB) position of the instructions. The instructions that are “chained” together for simultaneous execution (up to eight in total) compose an execute packet. A “0” in the LSB of an instruction breaks the chain, effectively placing the instructions that follow it in the next execute packet. If an execute packet crosses the

256-bit-wide fetch-packet boundary, the assembler places it in the next fetch packet, while the remainder of the current fetch packet is padded with NOP instructions. The number of execute packets within a fetch packet can vary from one to eight. Execute packets are dispatched to their respective functional units at the rate of one per clock cycle and the next 256-bit fetch packet is not fetched until all the execute packets from the current fetch packet have been dispatched. After decoding, the instructions simultaneously drive all active functional units for a maximum execution rate of eight instructions every clock cycle. While most results are stored in 32-bit registers, they can be subsequently moved to memory as bytes or half-words as well. All load and store instructions are byte-, half-word, or word-addressable.

8


•



CPU (DSP core) description (continued)

src1

ÁÁÁÁ Á ÁÁÁÁÁÁ

Data Path A

ST1

Á

ÁÁÁÁ

.L1

src2

ÁÁÁÁ Á

dst

ÁÁÁÁ

long dst long src

ÁÁÁÁ Á

8

8

ÁÁÁÁ ÁÁÁÁ Á

long src long dst

ÁÁÁÁ Á

dst

.S1

ÁÁÁÁ Á

src1

ÁÁÁÁ Á Á

src2

ÁÁÁÁ ÁÁÁÁ Á

dst

.M1

src1

ÁÁÁÁ Á

src2

ÁÁÁÁ Á

Á

Á Á

Á

Á

Á Á

ÁÁÁÁÁÁ

ÁÁÁÁÁÁ

8

ÁÁ ÁÁÁÁÁÁ ÁÁ

ÁÁ ÁÁÁÁÁÁ

32

ÁÁÁÁÁÁ

ÁÁÁÁÁÁ

Register

File A

ÁÁ ÁÁÁÁÁÁ

(A0−A15)

ÁÁÁÁÁÁ

ÁÁ ÁÁÁÁÁÁ

ÁÁ ÁÁÁÁÁÁ

ÁÁÁÁÁÁ

LD1

DA1

Á

ÁÁÁÁ

dst

ÁÁÁÁ Á

.D1

src1

src2

ÁÁÁÁ Á Á

Á ÁÁ ÁÁÁÁÁÁ

ÁÁ ÁÁÁÁÁÁ

ÁÁÁÁ

ÁÁÁÁÁÁ

2X

ÁÁÁÁÁÁ

1X

ÁÁÁÁÁÁ

DA2

Á

ÁÁÁÁ Á

src2

.D2

src1

ÁÁÁÁ Á Á

dst

ÁÁÁÁ

ÁÁÁÁÁÁ

ÁÁ ÁÁÁÁÁÁ ÁÁ

LD2

Data Path B

ST2

Á

ÁÁÁÁ Á

src2

.M2

src1

Á

dst

ÁÁÁÁ Á

src2

ÁÁÁÁ Á ÁÁÁÁ

src1

ÁÁÁÁ Á

.S2

dst long src

ÁÁÁÁ

ÁÁÁÁ Á

long src

8

long dst

ÁÁÁÁ Á

dst

8

src2

ÁÁÁÁ Á

Á

Á

Á Á

Á

Á

Á Á

32

8

ÁÁ ÁÁÁÁÁÁ

ÁÁÁÁÁÁ

ÁÁ ÁÁÁÁÁÁ

ÁÁÁÁÁÁ

Register

File B

ÁÁÁÁÁÁ

(B0−B15)

ÁÁ ÁÁÁÁÁÁ

ÁÁÁÁÁÁ

ÁÁÁÁÁÁ

ÁÁ ÁÁÁÁÁÁ

ÁÁÁÁÁÁ

ÁÁ

ÁÁÁÁÁÁ

Á ÁÁÁÁÁÁ

src1

Á

ÁÁÁÁ Á Á ÁÁÁÁÁÁ

Control

Register

File

ÁÁ

Figure 1. TMS320C62x CPU (DSP Core) Data Paths


•


9


memory map summary

Table 2 shows the memory map address ranges of the C6204 device. The C6204 device has the capability of a MAP 0 or MAP 1 memory block configuration. The maps differ in that MAP 0 has external memory mapped at address 0x0000 0000 and MAP 1 has internal memory mapped at address 0x0000 0000. These memory block configurations are set up at reset by the boot configuration pins (generically called BOOTMODE[4:0]). For the C6204 device, the BOOTMODE configuration is handled, at reset, by the expansion bus module (specifically

XD[4:0] pins). For more detailed information on the C6204 device settings, which include the device boot mode configuration at reset and other device-specific configurations, see TMS320C6201/C670x DSP Boot Modes

and Configuration (literature number SPRU642).

Table 2. TMS320C6204 Memory Map Summary

EMIF CE0

MEMORY BLOCK DESCRIPTION

MAP 0

External Memory Interface (EMIF) CE0

MAP 1

Internal Program RAM

Reserved

EMIF CE0

EMIF CE1

Internal Program RAM

Reserved

EMIF CE0

EMIF CE0

EMIF CE1

EMIF CE1

EMIF Registers

DMA Controller Registers

Expansion Bus (XBus) Registers

McBSP 0 Registers

McBSP 1 Registers

Timer 0 Registers

Timer 1 Registers

Interrupt Selector Registers

Reserved

EMIF CE2

EMIF CE3

Reserved

XBus XCE0

XBus XCE1

XBus XCE2

XBus XCE3

Internal Data RAM

Reserved

(BYTES)

256K

256K

256K

6M

16M

16M

1G – 64M

256M

256M

256M

256M

64K

2G – 64K

64K

4M – 64K

12M

4M

64K

4M – 64K

256K

256K

256K

256K

256K

0000 0000 – 0000 FFFF

0001 0000 – 003F FFFF

0040 0000 – 00FF FFFF

0100 0000 – 013F FFFF

0140 0000 – 0140 FFFF

0141 0000 – 017F FFFF

0180 0000 – 0183 FFFF

0184 0000 – 0187 FFFF

0188 0000 – 018B FFFF

018C 0000 – 018F FFFF

0190 0000 – 0193 FFFF

0194 0000 – 0197 FFFF

0198 0000 – 019B FFFF

019C 0000 – 019F FFFF

01A0 0000 – 01FF FFFF

0200 0000 – 02FF FFFF

0300 0000 – 03FF FFFF

0400 0000 – 3FFF FFFF

4000 0000 – 4FFF FFFF

5000 0000 – 5FFF FFFF

6000 0000 – 6FFF FFFF

7000 0000 – 7FFF FFFF

8000 0000 – 8000 FFFF

8001 0000 – FFFF FFFF

10


•



peripheral register descriptions

Table 3 through Table 11 identify the peripheral registers for the C6204 device by their register names, acronyms, and hex address or hex address range. For more detailed information on the register contents, bit names, and their descriptions, see the peripheral reference guide referenced in TMS320C6000 Peripherals

Reference Guide (literature number SPRU190).

Table 3. EMIF Registers

HEX ADDRESS RANGE

0180 0000

0180 0004

0180 0008

0180 000C

0180 0010

0180 0014

0180 0018

0180 001C

0180 0020 − 0180 0054

0180 0058 − 0183 FFFF

ACRONYM

GBLCTL

REGISTER NAME

EMIF global control

CECTL1

CECTL0

−

CECTL2

CECTL3

SDCTL

SDTIM

−

–

COMMENTS

EMIF CE1 space control

External or internal; dependant on MAP0 or MAP1 configuration (selected byt the MAP bit in the EMIF GBLCTL register

External or internal; dependant on MAP0 or MAP1 configuration (selected byt the MAP bit in the EMIF GBLCTL register


Reserved



EMIF SDRAM control

EMIF SDRAM refresh control

Reserved

Reserved

Corresponds to EMIF CE2 memory space:

[0200 0000 − 02FF FFFF]

Corresponds to EMIF CE3 memory space:

[0300 0000 − 03FF FFFF]


•


11


peripheral register descriptions (continued)


0184 0000

0184 0004

0184 0008

0184 000C

0184 0010

0184 0014

0184 0018

0184 001C

0184 0020

0184 0024

0184 0028

0184 002C

0184 0030

0184 0034

0184 0038

0184 003C

0184 0040

0184 0044

0184 0048

0184 004C

0184 0050

0184 0054

0184 0058

0184 005C

0184 0060

0184 0064

0184 0068

0184 006C

0184 0070

0184 0074 − 0187 FFFF

Table 4. DMA Registers

ACRONYM

PRICTL0

PRICTL2

SECCTL0

SECCTL2

SRC0

SRC2

DST0

DST2

XFRCNT0

XFRCNT2

GBLCNTA

GBLCNTB

DMA channel 0 primary control

DMA channel 2 primary control

DMA channel 0 secondary control


DMA channel 0 source address


DMA channel 0 destination address


DMA channel 0 transfer counter


DMA global count reload register A

DMA global count reload register B

GBLIDXA

GBLIDXB

DMA global index register A

DMA global index register B

GBLADDRA DMA global address register A

REGISTER NAME

GBLADDRB DMA global address register B

PRICTL1 DMA channel 1 primary control

PRICTL3 DMA channel 3 primary control

SECCTL1

SECCTL3

SRC1




SRC3

DST1

DST3




XFRCNT1

XFRCNT3



GBLADDRC DMA global address register C

GBLADDRD DMA global address register D

AUXCTL DMA auxiliary control register

– Reserved

12


•





0188 0000

0188 0004

0188 0008

0188 000C

0188 0010

0188 0014

0188 0018

0188 001C

0188 0020

0188 0024

0188 0028 − 018B FFFF

−

−


019C 0000

019C 0004

019C 0008

019C 000C − 019C 01FF

019C 0200

019C 0204 − 019F FFFF


019C 0200

Table 5. Expansion Bus (XBUS) Registers

ACRONYM

XBGC

XCECTL1

REGISTER NAME

Expansion bus global control register

XCE1 space control register

XCECTL0

XBHC

XCECTL2


Expansion bus host port interface control register


XCECTL3

−

−

XBIMA

XBEA

−

XBISA

XBD


Reserved

Reserved

Expansion bus internal master address register

Expansion bus external address register

Reserved

Expansion bus internal slave address

Expansion bus data

COMMENTS

Corresponds to XBus XCE0 memory space: [4000 0000 − 4FFF FFFF]


DSP read/write access only





Table 6. Interrupt Selector Registers

ACRONYM

MUXH

REGISTER NAME

Interrupt multiplexer high

MUXL

EXTPOL

−

PDCTL

−

Interrupt multiplexer low

External interrupt polarity

Reserved

Peripheral power-down control register

Reserved

COMMENTS

Selects which interrupts drive CPU interrupts

10−15 (INT10−INT15)

Selects which interrupts drive CPU interrupts 4−9

(INT04−INT09)

Sets the polarity of the external interrupts

(EXT_INT4−EXT_INT7)

Table 7. Peripheral Power-Down Control Register

ACRONYM

PDCTL

REGISTER NAME

Peripheral power-down control register


•


13




018C 0000

018C 0004

018C 0008

018C 000C

018C 0010

018C 0014

018C 0018

018C 001C

018C 0020

018C 0024

018C 0028 − 018F FFFF

Table 8. McBSP 0 Registers

ACRONYM

DRR0

DXR0

SPCR0

RCR0

XCR0

SRGR0

MCR0

RCER0

XCER0

PCR0

–

REGISTER NAME

McBSP0 data receive register

McBSP0 data transmit register

McBSP0 serial port control register

McBSP0 receive control register

McBSP0 transmit control register

McBSP0 sample rate generator register

McBSP0 multichannel control register

McBSP0 receive channel enable register

McBSP0 transmit channel enable register

McBSP0 pin control register

Reserved


0190 0000

0190 0004

0190 0008

0190 000C

0190 0010

0190 0014

0190 0018

0190 001C

0190 0020

0190 0024

0190 0028 − 0193 FFFF

Table 9. McBSP 1 Registers

ACRONYM

DRR1

DXR1

SPCR1

RCR1

XCR1

SRGR1

MCR1

RCER1

XCER1

PCR1

–

REGISTER NAME

Data receive register

McBSP1 data transmit register

McBSP1 serial port control register

McBSP1 receive control register

McBSP1 transmit control register

McBSP1 sample rate generator register

McBSP1 multichannel control register

McBSP1 receive channel enable register

McBSP1 transmit channel enable register

McBSP1 pin control register

Reserved

COMMENTS

The CPU and DMA/EDMA controller can only read this register; they cannot write to it.

COMMENTS

The CPU and DMA/EDMA controller can only read this register; they cannot write to it.

14


•





0194 0000

0194 0004

0194 0008

0194 000C − 0197 FFFF


0198 0000

0198 0004

0198 0008

0198 000C − 019B FFFF

PRD0

CNT0

−

Table 10. Timer 0 Registers

ACRONYM

CTL0

REGISTER NAME

Timer 0 control register

Timer 0 period register

Timer 0 counter register

Reserved

COMMENTS

Determines the operating mode of the timer, monitors the timer status, and controls the function of the TOUT pin.

Contains the number of timer input clock cycles to count.

This number controls the TSTAT signal frequency.

Contains the current value of the incrementing counter.

Table 11. Timer 1 Registers

ACRONYM

CTL1

REGISTER NAME

Timer 1 control register

PRD1

CNT1

−

Timer 1 period register

Timer 1 counter register

Reserved

COMMENTS

Determines the operating mode of the timer, monitors the timer status, and controls the function of the TOUT pin.

Contains the number of timer input clock cycles to count.

This number controls the TSTAT signal frequency.

Contains the current value of the incrementing counter.


•


15


DMA channel synchronization events

The C6204 DMA supports up to four independent programmable DMA channels. The four main DMA channels can be read/write synchronized based on the events shown in Table 12. Selection of these events is done via the RSYNC and WSYNC fields in the Primary Control registers (PRICTLx) of the specific DMA channel. The default setting is “no synchronization” for all four DMA channels. For more detailed information on the DMA module, associated channels, and event-synchronization, see TMS320C620x/C670x DSP Program and Data

Memory Controller / Direct Memory Access (DMA) Controller Reference Guide (literature number SPRU190).

Table 12. TMS320C6204 DMA Synchronization Events

†

DMA EVENT

NUMBER

(BINARY)

00000

00001

00010

00011

00100

00101

00110

00111

01000

01001

01010

01011

01100

01101

01110

EVENT NAME

None

TINT0

TINT1

SD_INT

EXT_INT4

EXT_INT5

EXT_INT6

EXT_INT7

DMA_INT0

DMA_INT1

DMA_INT2

DMA_INT3

XEVT0

REVT0

XEVT1

No Synchronization (default)

Timer 0 interrupt

Timer 1 interrupt

EMIF SDRAM timer interrupt

External interrupt pin 4




DMA channel 0 interrupt




McBSP0 transmit event

McBSP0 receive event

McBSP1 transmit event

EVENT DESCRIPTION

01111

10000

REVT1

DSP_INT

McBSP1 receive event

Host processor-to-DSP interrupt

10001 − 11111 Reserved Reserved. Not used.

† For synchronization event selection, the PRICTLx register for the specific DMA channel needs to be programmed with a binary event number identified in this table. The default setting is “no synchronization” for all four DMA channels.

16


•



interrupt sources and interrupt selector

The C62x DSP core supports 16 prioritized interrupts, which are listed in Table 13. The highest-priority interrupt is INT_00 (dedicated to RESET) while the lowest-priority interrupt is INT_15. The first four interrupts

(INT_00−INT_03) are non-maskable and fixed. The remaining interrupts (INT_04−INT_15) are maskable and default to the interrupt source specified in Table 13. The interrupt source for interrupts 4−15 can be programmed by modifying the selector value (binary value) in the corresponding fields of the Interrupt Selector Control registers: MUXH (address 0x019C0000) and MUXL (address 0x019C0004).

Table 13. C6204 DSP Interrupts

CPU

INTERRUPT

NUMBER

INT_00†

INT_01†

INT_02†

INT_03†

INT_04‡

INT_05‡

INT_06‡

INT_07‡

INT_08‡

INT_09‡

INT_10‡

INT_11‡

INT_12‡

INT_13‡

INT_14‡

INT_15‡

−

INTERRUPT

SELECTOR

CONTROL

REGISTER

−

−

−

−

MUXL[4:0]

MUXL[9:5]

MUXL[14:10]

MUXL[20:16]

MUXL[25:21]

MUXL[30:26]

MUXH[4:0]

MUXH[9:5]

MUXH[14:10]

MUXH[20:16]

MUXH[25:21]

MUXH[30:26]

−

SELECTOR

VALUE

(BINARY)

−

−

−

−

00100

00101

00110

00111

01000

01001

00011

01010

01011

00000

00001

00010

01100

INTERRUPT

EVENT

RESET

NMI

Reserved

Reserved

EXT_INT4

EXT_INT5

EXT_INT6

EXT_INT7

DMA_INT0

DMA_INT1

SD_INT

DMA_INT2

DMA_INT3

DSP_INT

TINT0

TINT1

XINT0

INTERRUPT SOURCE

Reserved. Do not use.

Reserved. Do not use.







EMIF SDRAM timer interrupt



Host-port interface (HPI)-to-DSP interrupt

Timer 0 interrupt

Timer 1 interrupt

McBSP0 transmit interrupt

−

−

−

−

−

−

01101

01110

01111

RINT0

XINT1

RINT1

McBSP0 receive interrupt

McBSP1 transmit interrupt

McBSP1 receive interrupt

− − 10000 − 11111 Reserved Reserved. Do not use.

† Interrupts INT_00 through INT_03 are non-maskable and fixed.

‡ Interrupts INT_04 through INT_15 are programmable by modifying the binary selector values in the Interrupt Selector Control registers fields.

Table 13 shows the default interrupt sources for Interrupts INT_04 through INT_15. For more detailed information on interrupt sources and selection, see TMS320C6000 DSP Interrupt Selector Reference Guide (literature number SPRU646).


•


17


signal groups description

CLKIN

CLKOUT2

CLKOUT1

CLKMODE0

CLKMODE1

CLKMODE2

PLLV

PLLG

PLLF

RSV11

RSV10

RSV9

RSV8

RSV7

RSV6

RSV5

RSV4

RSV3

RSV2

RSV1

RSV0

TMS

TDO

TDI

TCK

TRST

EMU1

EMU0

Clock/PLL

IEEE Standard

1149.1

(JTAG)

Emulation

Reserved

Reset and

Interrupts

DMA Status

Power-Down

Status

Control/Status

Figure 2. CPU (DSP Core) Signals

RESET

NMI

EXT_INT7

EXT_INT6

EXT_INT5

EXT_INT4

IACK

INUM3

INUM2

INUM1

INUM0

DMAC3

DMAC2

DMAC1

DMAC0

PD

18


•



signal groups description (continued)

ED[31:0]

CE3

CE2

CE1

CE0

EA[21:2]

BE3

BE2

BE1

BE0

32

20

Data

Asynchronous

Memory

Control

Memory Map

Space Select

Synchronous

Memory

Control

Word Address

Byte Enables

HOLD/

HOLDA

EMIF

(External Memory Interface)

ARE

AOE

AWE

ARDY

SDA10

SDRAS/SSOE

SDCAS/SSADS

SDWE/SSWE

HOLD

HOLDA

TOUT1

TINP1

TOUT0

TINP0

Timer 1

Timers

Timer 0

McBSP1

Transmit

McBSP0

Transmit

CLKX1

FSX1

DX1

CLKR1

FSR1

DR1

CLKS1

Receive

Receive

Clock

Clock

McBSPs

(Multichannel Buffered Serial Ports)

Figure 3. Peripheral Signals

CLKX0

FSX0

DX0

CLKR0

FSR0

DR0

CLKS0


•


19


signal groups description (continued)

XD[31:0]

XBE3/XA5

XBE2/XA4

XBE1/XA3

XBE0/XA2

XRDY

XHOLD

XHOLDA

32

Data

Byte-Enable

Control/

Address

Control

Arbitration

Clocks

I/O Port

Control

Expansion Bus

Host

Interface

Control

Figure 3. Peripheral Signals (Continued)

XCLKIN

XFCLK

XOE

XRE

XWE/XWAIT

XCE3

XCE2

XCE1

XCE0

XCS

XAS

XCNTL

XW/R

XBLAST

XBOFF

20


•



Signal Descriptions

NAME

PIN NO.

GHK GLW†

CLKIN

CLKOUT1

CLKOUT2

CLKMODE0

CLKMODE1

J3

T18

T19

L3

−

B10

Y18

AB19

B12

A9

I

O

O

I

I

CLOCK/PLL

Clock Input

Clock output at full device speed

Clock output at half of device speed

-

Used for synchronous memory interface

Clock mode selects

-

Selects what multiply factors of the input clock frequency the CPU frequency equals.

For more details on CLKMODE pins and the PLL multiply factors, see the Clock PLL

CLKMODE2

PLLV§

PLLG§

PLLF§

TMS

TDO

TDI

TCK

TRST

EMU1

EMU0

−

K5

L2

L1

E17

D19

D18

D17

C19

E18

F15

A14

C11

C12

A11

Y5

AA4

Y4

AB2

AA3

AA5

AB4

I

A¶

A¶

A¶

Note: For the C6204 GLW package, the CLKMODE2 (A14) and CLKMODE1 (A9) pins are internally unconnected.

PLL analog VCC connection for the low-pass filter

PLL analog GND connection for the low-pass filter

PLL low-pass filter connection to external components and a bypass capacitor

I

O/Z

I

JTAG EMULATION

JTAG test-port mode select (features an internal pullup)

JTAG test-port data out

JTAG test-port data in (features an internal pullup)

I JTAG test-port clock

I JTAG test-port reset (features an internal pulldown)

I/O/Z Emulation pin 1, pullup with a dedicated 20-k

Ω

resistor#

I/O/Z Emulation pin 0, pullup with a dedicated 20-k

Ω

resistor#

RESET AND INTERRUPTS

RESET

NMI

E8

A8

J3

K2 I

I Device reset

Nonmaskable interrupt

-

Edge-driven (rising edge)

EXT_INT7

EXT_INT6

EXT_INT5

EXT_INT4

IACK

B15

C15

A16

B16

A15

U2

U3

W1

V2

V1

I

O

-

Edge-driven

-

Polarity independently selected via the external interrupt polarity register bits

(EXTPOL.[3:0])

Interrupt acknowledge for all active interrupts serviced by the CPU

INUM3 F12 R3

INUM2 A14 T1

INUM1 B14 T2

-

Valid during IACK for all active interrupts (not just external)

-

Encoding order follows the interrupt-service fetch-packet ordering

INUM0 C14 T3

† The C6204 GLW BGA package is a subset of the GLS package (C6202/02B/03), with the inner row of core supply voltage (CVDD) and ground

(VSS) pins removed (see the GLW BGA package bottom view).

‡ I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground

§ PLLV, PLLG, and PLLF are not part of external voltage supply or ground. See the clock PLL section for information on how to connect these pins.

¶ A = Analog Signal (PLL Filter)

# For emulation and normal operation, pull up EMU1 and EMU0 with a dedicated 20-k Ω

resistor. For boundary scan, pull down EMU1 and EMU0 with a dedicated 20-k

Ω

resistor.


•


21


Signal Descriptions (Continued)

NAME

PIN NO.

GHK GLW†

PD

XD27

XD26

XD25

XD24

XD23

XD22

XD21

XD20

XD19

XD18

XD17

XCLKIN

XFCLK

XD31

XD30

XD29

XD28

B18

H5

G2

M1

M2

M3

N1

N2

N3

P1

P2

N5

R1

R2

P5

T1

T2

U1

Y2

C8

A8

C13

A13

C14

B14

B15

C15

A15

B16

C16

A17

B17

C17

B18

A19

C18

O

I

O

POWER-DOWN STATUS

Power-down modes 2 or 3 (active if high)

EXPANSION BUS

Expansion bus synchronous host interface clock input

Expansion bus FIFO interface clock output

-

-

Used for transfer of data, address, and control

Also controls initialization of DSP modes and expansion bus at reset via pullup/

XD10

XD9

XD8

XD7

XD6

XD5

XD16

XD15

XD14

XD13

XD12

XD11

T3

U2

V1

V2

W2

U4

W3

V4

W4

U5

V5

W5

B19

C19

B20

A21

C21

D20

B22

D21

E20

E21

D22

F20

XD4

XD3

XD2

XD1

U6

V6

V3

W6

F21

E22

G20

G21

XD0 U7 G22




22


•




NAME

PIN NO.

GHK GLW†

EXPANSION BUS (CONTINUED)

XCE3

XCE2

XCE1

XCE0

XBE3/XA5

XBE2/XA4

XBE1/XA3

XBE0/XA2

XOE

XRE

XWE/XWAIT

XCS

XAS

F1

G3

H1

F2

E1

F3

F5

B4

A3

C4

B3

E3

E2

B5

C6

A6

C7

B7

C9

B6

D2

B1

D3

C2

C5

A4

-

-

-

-

Enabled by bits 28, 29, and 30 of the word address

Only one asserted during any I/O port data access

Act as byte-enable for host port operation

Act as address for I/O port operation

O/Z Expansion bus I/O port output-enable

O/Z

O/Z

Expansion bus I/O port read-enable

Expansion bus I/O port write-enable and host-port wait signals

I Expansion bus host-port chip-select input

I/O/Z Expansion bus host-port address strobe

XCNTL

XW/R

XRDY

XBLAST

XBOFF

H2

H3

D2

D1

J1

B9

B8

C4

B4

A10

I

I/O/Z

I

Expansion bus host control. XCNTL selects between expansion bus address or data register.

I/O/Z Expansion bus host-port write/read enable. XW/R polarity is selected at reset.

I/O/Z Expansion bus host-port ready (active low) and I/O port ready (active high)

Expansion bus host-port burst last-polarity selected at reset

Expansion bus back off

XHOLD

XHOLDA

C2

C1

A2

B3

I/O/Z Expansion bus hold request

I/O/Z Expansion bus hold acknowledge

EMIF − CONTROL SIGNALS COMMON TO ALL TYPES OF MEMORY

CE3

CE2

V18

U17

Y21

W20

CE1

CE0

W18

V17

AA22

W21

-

-

Enabled by bits 24 and 25 of the word address

Only one asserted during any external data access

BE3 U16 V20

BE2

BE1

W17

V16

V21

W22

-

Decoded from the two lowest bits of the internal address

-

Byte-write enables for most types of memory

-

Can be directly connected to SDRAM read and write mask signal (SDQM)

BE0 W16 U20





•


23



NAME

PIN NO.

GHK GLW†

EMIF − ADDRESS

EA9

EA8

EA7

EA6

EA5

EA4

EA3

EA2

EA15

EA14

EA13

EA12

EA11

EA10

EA21

EA20

EA19

EA18

EA17

EA16

V11

U11

R11

W12

U12

R12

W13

V13

V9

U9

W10

V10

U10

W11

V7

W7

U8

V8

W8

W9

M21

N22

N20

N21

P21

P20

R22

R21

K20

K22

L21

L20

L22

M20

H20

H21

H22

J20

J21

K21

EMIF − DATA

ED31

ED30

ED29

ED28

ED27

ED26

ED25

F14

E19

F17

G15

F18

F19

G17

Y6

AA6

AB6

Y7

AA7

AB8

Y8

ED24

ED23

ED22

ED21

ED20

ED19

G18

G19

H17

H18

H19

J18

AA8

AA9

Y9

AB10

Y10

AA10

I/O/Z External data

ED18

ED17

ED16

ED15

J19

K15

K17

K18

AA11

Y11

AB12

Y12

ED14 K19 AA12




24


•




NAME

PIN NO.

GHK GLW†

EMIF − DATA (CONTINUED)

ED7

ED6

ED5

ED4

ED3

ED2

ED13

ED12

ED11

ED10

ED9

ED8

ED1

ED0

L17

L18

L19

M19

M18

M17

N19

P19

N15

P18

P17

R19

AA13

Y13

AB13

Y14

AA14

AA15

Y15

AB15

AA16

Y16

AB17

AA17

I/O/Z External data

ARE

AOE

AWE

ARDY

SDA10

SDCAS/SSADS

SDRAS/SSOE

SDWE/SSWE

HOLD

HOLDA

R18

R17

Y17

AA18

U14

W14

V14

W15

T21

R20

T22

T20

EMIF − ASYNCHRONOUS MEMORY CONTROL

O/Z

O/Z

O/Z

I

Asynchronous memory read-enable

Asynchronous memory output-enable

Asynchronous memory write-enable

Asynchronous memory ready input

EMIF − SYNCHRONOUS DRAM (SDRAM)/SYNCHRONOUS BURST SRAM (SBSRAM) CONTROL

U19 AA19 O/Z SDRAM address 10 (separate for deactivate command)

V19 AB21 O/Z SDRAM column-address strobe/SBSRAM address strobe

U18

T17

Y19

AA20

O/Z

O/Z

SDRAM row-address strobe/SBSRAM output-enable

SDRAM write-enable/SBSRAM write-enable

P14

V15

E5

C5

V22

U21

D1

E2

O

I

I

O

EMIF − BUS ARBITRATION

Hold request from the host

Hold-request-acknowledge to the host

TIMER 0

Timer 0 or general-purpose output

Timer 0 or general-purpose input

TOUT0

TINP0

TOUT1

TINP1

A5

B5

F2

F3

O

I

TIMER 1

Timer 1 or general-purpose output

Timer 1 or general-purpose input

DMA ACTION COMPLETE STATUS

DMAC3

DMAC2

A17

B17

V3

W2

DMAC1 C16 AA1

DMAC0 A18 W3





•


25



NAME

PIN NO.

GHK GLW†

CLKS0

CLKR0

CLKX0

DR0

DX0

FSR0

FSX0

A12

B9

C9

A10

B10

E10

A9

C6

B6

E6

A7

B7

C7

A6

K3

L2

K1

M2

M3

M1

L3

E1

G2

G3

H1

H2

H3

G1

MULTICHANNEL BUFFERED SERIAL PORT 0 (McBSP0)

I External clock source (as opposed to internal)

I/O/Z Receive clock

I/O/Z Transmit clock

I

O/Z

Receive data

Transmit data

I/O/Z Receive frame sync

I/O/Z Transmit frame sync

MULTICHANNEL BUFFERED SERIAL PORT 1 (McBSP1)

I External clock source (as opposed to internal) CLKS1

CLKR1

CLKX1

DR1

DX1

FSR1

FSX1

RSV0

RSV1

RSV2

RSV3

RSV4

C8

A4

K3

L5

B19

J2

E3

B11

B13

C10

I/O/Z Receive clock

I/O/Z Transmit clock

I Receive data

O/Z Transmit data

I/O/Z Receive frame sync

I/O/Z Transmit frame sync

I

I

I

O

O

RESERVED FOR TEST

Reserved for testing, pullup with a dedicated 20-k

Ω

resistor


Ω

resistor


Ω

resistor

Reserved (leave unconnected, do not connect to power or ground)

Reserved (leave unconnected, do not connect to power or ground)

RSV5

RSV6

RSV7

RSV8

RSV9

RSV10

C17

D3

K2

J17

N18

C11

N1

N2

N3

R2

R1

P3

I

I/O

I/O

I

O

I/O

Reserved (leave unconnected)






RSV11 − P2 I/O Reserved (leave unconnected) [For C6204 GLW packages only]




26


•




NAME

PIN NO.

GHK GLW†

TYPE‡ DESCRIPTION

SUPPLY VOLTAGE PINS

K14

L6

L15

M14

P3

P15

R3

R6

R7

R8

R9

E11

E13

F6

G1

H14

J6

A2

B1

B2

C3

E7

E9

A3

A7

A16

A20

D4

D6

D7

D9

D10

D13

D14

D16

D17

D19

F1

F4

F19

F22

G4

G19

J4

J19

K4

−

−

−

−

−

−

R10

R13

R14

U3

U15

−

K19

L1

M22

N4

N19

P4

P19

T4

T19

U1

U4

U19

−

−

U22

W4

− W6

− W7





•


27



NAME

PIN NO.

GHK GLW†

SUPPLY VOLTAGE PINS (CONTINUED)

E14

F9

F10

G5

H15

J2

J5

J15

M5

M15

N17

−

−

−

−

−

B12

−

−

−

−

−

−

W9

W10

W13

W14

W16

W17

W19

AB5

AB9

AB14

AB18

E7

E8

E10

E11

E12

E13

E15

E16

G5

G18

H5

H18

−

−

−

−

−

−

P6

P9

P12

U13

−

−

K5

K18

L5

L18

M5

M18

N5

N18

R5

R18

T5

T18

−

−

V7

V8

− V10

− V11




28


•




NAME

PIN NO.

GHK GLW†

SUPPLY VOLTAGE PINS (CONTINUED)

−

−

−

−

V12

V13

V15

V16

GROUND PINS

C12

C13

C18

E12

G7

G8

G9

G10

G11

G12

G13

A11

A13

B8

B11

B13

C10

B21

C1

C3

C20

C22

D5

D8

D11

D12

D15

D18

A1

A5

A12

A18

A22

B2

GND Ground pins

H13

J7

J8

J9

J10

J11

H7

H8

H9

H10

H11

H12

E4

E5

E6

E9

E14

E17

E18

E19

F5

F18

H4

H19

J12

J13

J1

J5

K1 J18

K7 J22





•


29



NAME

PIN NO.

GHK GLW†

GROUND PINS (CONTINUED)

L13

M7

M8

M9

M10

M11

M12

M13

N7

N8

N9

L7

L8

L9

L10

L11

L12

K8

K9

K10

K11

K12

K13

L4

L19

M4

M19

P1

P5

P18

P22

R4

R19

U5

U18

V4

V5

V6

V9

V14

V17

V18

V19

W5

W8

W11

GND Ground pins

−

−

−

−

−

−

N10

N11

N12

N13

V12

−

W12

W15

W18

Y1

Y3

Y20

Y22

AA2

AA21

AB1

AB3

AB7

−

−

AB11

AB16

− AB20

− AB22




30


•



development support

TI offers an extensive line of development tools for the TMS320C6000



DSP platform, including tools to evaluate the performance of the processors, generate code, develop algorithm implementations, and fully integrate and debug software and hardware modules.

The following products support development of C6000



DSP-based applications:

Software Development Tools:

Code Composer Studio



Integrated Development Environment (IDE) including Editor

C/C++/Assembly Code Generation, and Debug plus additional development tools

Scalable, Real-Time Foundation Software (DSP BIOS), which provides the basic run-time target software needed to support any DSP application.

Hardware Development Tools:

Extended Development System (XDS



) Emulator (supports C6000



DSP multiprocessor system debug)

EVM (Evaluation Module)

The TMS320 DSP Development Support Reference Guide (SPRU011) contains information about development-support products for all TMS320



DSP family member devices, including documentation. See this document for further information on TMS320



DSP documentation or any TMS320



DSP support products from Texas Instruments. An additional document, the TMS320 Third-Party Support Reference Guide

(SPRU052), contains information about TMS320



DSP-related products from other companies in the industry.

To receive TMS320



DSP literature, contact the Literature Response Center at 800/477-8924.

For a complete listing of development-support tools for the TMS320C6000 DSP platform, visit the Texas

Instruments web site on the Worldwide Web at http://www.ti.com uniform resource locator (URL) and select

“Find Development Tools”. For device-specific tools, under “Semiconductor Products” select “Digital Signal

Processors”, choose a product family, and select the particular DSP device. For information on pricing and availability, contact the nearest TI field sales office or authorized distributor.

Code Composer Studio, XDS, and TMS320 are trademarks of Texas Instruments.


•


31


device and development-support tool nomenclature

To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all

TMS320



DSP devices and support tools. Each TMS320



DSP commercial family member has one of three prefixes: TMX, TMP, or TMS. Texas Instruments recommends two of three possible prefix designators for support tools: TMDX and TMDS. These prefixes represent evolutionary stages of product development from engineering prototypes (TMX / TMDX) through fully qualified production devices/tools (TMS / TMDS).

Device development evolutionary flow:

TMX

TMP

TMS

Experimental device that is not necessarily representative of the final device’s electrical specifications

Final silicon die that conforms to the device’s electrical specifications but has not completed quality and reliability verification

Fully qualified production device

Support tool development evolutionary flow:

TMDX

Development-support product that has not yet completed Texas Instruments internal qualification testing.

TMDS

Fully qualified development-support product

TMX and TMP devices and TMDX development-support tools are shipped against the following disclaimer:

“Developmental product is intended for internal evaluation purposes.”

TMS devices and TMDS development-support tools have been characterized fully, and the quality and reliability of the device have been demonstrated fully. TI’s standard warranty applies.

Predictions show that prototype devices (TMX or TMP) have a greater failure rate than the standard production devices. Texas Instruments recommends that these devices not be used in any production system because their expected end-use failure rate still is undefined. Only qualified production devices are to be used.

TI device nomenclature also includes a suffix with the device family name. This suffix indicates the package type

(for example, GLW), the temperature range (for example, blank is the default commercial temperature range), and the device speed range in megahertz (for example, -200 is 200 MHz).

Table 14 lists the device orderable part numbers (P/Ns) and Figure 4 provides a legend for reading the complete device name for any TMS320C6000



DSP family member. For more information on the C6204 device orderable P/Ns, visit the Texas Instruments web site on the Worldwide web at http://www.ti.com URL, or contact the nearest TI field sales office or authorized distributor.

32


•



device and development-support tool nomenclature (continued)

Table 14. TMS320C6204 Device Part Numbers (P/Ns) and Ordering Information

DEVICE ORDERABLE P/N

TMS320C6204GHK

TMS320C6204GLW

DEVICE SPEED

200 MHz/1600 MIPS

200 MHz/1600 MIPS

CVDD

(CORE VOLTAGE)

1.5 V

1.5 V

DVDD

(I/O VOLTAGE)

3.3 V

3.3 V

OPERATING CASE

TEMPERATURE

RANGE

0

_

C to 90

_

C

0

_

C to 90

_

C

TMS 320 C 6204 GLW ( )

PREFIX

TMX = Experimental device

TMP = Prototype device

TMS = Qualified device

SMX= Experimental device, MIL

SMJ = MIL-PRF-38535, QML

SM = High Rel (non-38535)

DEVICE FAMILY

320 = TMS320 t

DSP family

200

DEVICE SPEED RANGE

100 MHz

120 MHz

150 MHz

167 MHz

200 MHz

233 MHz

250 MHz

300 MHz

400 MHz

500 MHz

600 MHz

TEMPERATURE RANGE (DEFAULT: 0

°

C TO 90

°

C)

Blank = 0

°

C to 90

°

C, commercial temperature

A = −40

°

C to 105

°

C, extended temperature

TECHNOLOGY

C = CMOS

PACKAGE TYPE†

GFN = 256-pin plastic BGA

GGP = 352-pin plastic BGA

GJC = 352-pin plastic BGA

GJL = 352-pin plastic BGA

GLS = 384-pin plastic BGA

GLW = 340-pin plastic BGA

GNY = 384-pin plastic BGA

GNZ = 352-pin plastic BGA

GLZ = 532-pin plastic BGA

GHK = 288-pin plastic MicroStar BGA t

DEVICE

C6000 DSP:

6201

6202

6204

6205

6415

6416

6202B 6211 6701

6203B 6211B 6711

6203C 6414 6711B

6712

6713

† BGA =

Ball Grid Array

QFP = Quad Flatpack

Figure 4. TMS320C6000



DSP Platform Device Nomenclature (Including the TMS320C6204)


•


33


documentation support

Extensive documentation supports all TMS320



DSP family devices from product announcement through applications development. The types of documentation available include: data sheets, such as this document, with design specifications; complete user’s reference guides for all devices and tools; technical briefs; development-support tools; on-line help; and hardware and software applications. The following is a brief, descriptive list of support documentation specific to the C6000



DSP devices:

The TMS320C6000 CPU and Instruction Set Reference Guide (literature number SPRU189) describes the

C6000



DSP core (CPU) architecture, instruction set, pipeline, and associated interrupts.

The TMS320C6000 DSP Peripherals Overview Reference Guide (literature number SPRU190) briefly describes the functionality of the peripherals available on the C6000



DSP platform of devices, such as the

64-/32-/16-bit external memory interfaces (EMIFs), 32-/16-bit host-port interfaces (HPIs), multichannel buffered serial ports (McBSPs), direct memory access (DMA), enhanced direct-memory-access (EDMA) controller, expansion bus (XB), peripheral component interconnect (PCI), clocking and phase-locked loop (PLL); and power-down modes.

The TMS320C6000 Technical Brief (literature number SPRU197) gives an introduction to the C62x



/C67x

 devices, associated development tools, and third-party support.

The tools support documentation is electronically available within the Code Composer Studio



IDE. For a complete listing of the latest C6000



DSP documentation, visit the Texas Instruments web site on the

Worldwide Web at http://www.ti.com uniform resource locator (URL).

The How to Begin Development and Migrate Across the TMS320C6202/6202B/6203/6204 DSPs application report (literature number SPRA603) describes the migration concerns and identifies the similarities and differences between the C6202, C6202B, C6203, and C6204 C6000



DSP devices.

C67x is a trademark of Texas Instruments.

34


•



clock PLL

Most of the internal C6204 clocks are generated from a single source through the CLKIN pin. This source clock either drives the PLL, which multiplies the source clock in frequency to generate the internal CPU clock, or bypasses the PLL to become the internal CPU clock.

To use the PLL to generate the CPU clock, the external PLL filter circuit must be properly designed. Figure 5,

Table 15, and Table 16 show the external PLL circuitry for either x1 (PLL bypass) or x4 PLL multiply modes.

Figure 6 shows the external PLL circuitry for a system with ONLY x1 (PLL bypass) mode.

To minimize the clock jitter, a single clean power supply should power both the C6204 device and the external clock oscillator circuit. Noise coupling into PLLF directly impacts PLL clock jitter. The minimum CLKIN rise and fall times should also be observed. For the input clock timing requirements, see the input and output clocks electricals section.

3.3V

PLLV

Internal to C6204

C3

10

m

F

C4

0.1

m

F

CLKMODE0

CLKMODE1†

CLKMODE2†

CLKIN

PLL

PLLMULT

PLLCLK

CLKIN

LOOP FILTER

1

0

CPU

CLOCK

(For the PLL Options and CLKMODE pins setup, see Table 15 and Table 16)

C2

C1

R1

† CLKMODE1 and CLKMODE2 pins are not applicable to the GHK package.

NOTES: A. Keep the lead length and the number of vias between pin PLLF, pin PLLG, R1, C1, and C2 to a minimum. In addition, place all PLL components (R1, C1, C2, C3, C4, and EMI Filter) as close to the C6000



DSP device as possible. Best performance is achieved with the PLL components on a single side of the board without jumpers, switches, or components other than the ones shown.

B. For reduced PLL jitter, maximize the spacing between switching signals and the PLL external components (R1, C1, C2, C3, C4, and the EMI Filter).

C. The 3.3-V supply for the EMI filter must be from the same 3.3-V power plane supplying the I/O voltage, DVDD.

D. EMI filter manufacturer: TDK part number ACF451832-333, 223, 153, 103. Panasonic part number EXCCET103U.

Figure 5. External PLL Circuitry for Either PLL Multiply Modes or x1 (Bypass) Mode

3.3V

PLLV

CLKMODE0

CLKMODE1†

CLKMODE2†

PLLMULT

PLL

Internal to C6204

CLKIN

PLLCLK

CLKIN

LOOP FILTER

1

0

CPU

CLOCK

† CLKMODE1 and CLKMODE2 pins are not applicable to the GHK package.

NOTES: A. For a system with ONLY PLL x1 (bypass) mode, short the PLLF to PLLG.

B. The 3.3-V supply for PLLV must be from the same 3.3-V power plane supplying the I/O voltage, DVDD.

Figure 6. External PLL Circuitry for x1 (Bypass) PLL Mode Only


•


35


clock PLL (continued)

Table 15. GHK/GLW Packages PLL Multiply and Bypass (x1) Options

†

GHK PACKAGE − 16 X 16 MM MICROSTAR BGA

E

GLW PACKAGE − 18 X 18 MM BGA

BIT (PIN NO.)

CLKMODE2 (A14)

[GLW ONLY]

CLKMODE1 (A9)

[GLW ONLY]

CLKMODE0 (L3) [GHK]

CLKMODE0 (B12) [GLW]

PLL MULTIPLY

FACTOR‡

X (Don’t Cares) X 0 Bypass (x1)

X X 1 x4

† For the GLW package only, the CLKMODE2 (A14) and CLKMODE1 (A9) pins are internally unconnected. These pins are not applicable to the

GHK package.

‡ f(CPU Clock) = f(CLKIN) x (PLL mode)

Table 16. PLL Component Selection Table

§

CLKMODE

CLKIN

RANGE

(MHz)

CPU CLOCK

FREQUENCY

(CLKOUT1)

RANGE (MHz)

CLKOUT2

RANGE

(MHz)

R1 [

(

±

Ω

1%]

)

C1 [

±

10%]

(nF)

C2 [

±

10%]

(pF)

TYPICAL

LOCK TIME

(

µ

s)

x4 32.5−50 130−200 65−100 60.4

27 560 75

§ Under some operating conditions, the maximum PLL lock time may vary by as much as 150% from the specified typical value. For example, if the typical lock time is specified as 100

µ s, the maximum value may be as long as 250

µ s.

power-down mode logic

Figure 7 shows the power-down mode logic on the C6204.

CLKOUT1

TMS320C6204

Internal Clock Tree

PD

(pin)

PD2

Clock

PLL

Power-

Down

Logic

PD1

IFR

PWRD

IER

CSR

CPU

Internal

Peripheral

Internal

Peripheral

PD3

CLKIN RESET

Figure 7. Power-Down Mode Logic

†

36


•



triggering, wake-up, and effects

The power-down modes and their wake-up methods are programmed by setting the PWRD field (bits 15−10) of the control status register (CSR). The PWRD field of the CSR is shown in Figure 8 and described in Table 17.

When writing to the CSR, all bits of the PWRD field should be set at the same time. Logic 0 should be used when

“writing” to the reserved bit (bit 15) of the PWRD field. The CSR is discussed in detail in the TMS320C6000 CPU

and Instruction Set Reference Guide (literature number SPRU189).

31 16

15

Reserved

R/W-0

7

14

Enable or

Non-Enabled

Interrupt Wake

R/W-0

13

Enabled

Interrupt Wake

R/W-0

12

PD3

R/W-0

11

PD2

R/W-0

10

PD1

R/W-0

9 8

0

Legend: R/W−x = Read/write reset value

NOTE: The shadowed bits are not part of the power-down logic discussion and therefore are not covered here. For information on these other bit fields in the CSR register, see the TMS320C6000 CPU and Instruction Set Reference Guide (literature number SPRU189).

Figure 8. PWRD Field of the CSR Register

Power-down mode PD1 takes effect eight to nine clock cycles after the instruction that sets the PWRD bits in the

CSR.

If PD1 mode is terminated by a non-enabled interrupt, the program execution returns to the instruction where PD1 took effect. If PD1 mode is terminated by an enabled interrupt, the interrupt service routine will be executed first, then the program execution returns to the instruction where PD1 took effect. The GIE bit in CSR and the NMIE bit in the interrupt enable register (IER) must also be set in order for the interrupt service routine to execute; otherwise, execution returns to the instruction where PD1 took effect upon PD1 mode termination by an enabled interrupt.

PD2 and PD3 modes can only be aborted by device reset. Table 17 summarizes all the power-down modes.


•


37


triggering, wake-up, and effects (continued)

Table 17. Characteristics of the Power-Down Modes

PRWD FIELD

(BITS 15−10)

000000

POWER-DOWN

MODE

No power-down

WAKE-UP METHOD EFFECT ON CHIP’S OPERATION

— —

CPU halted (except for the interrupt logic)

001001 PD1 Wake by an enabled interrupt

010001 PD1

Wake by an enabled or non-enabled interrupt boundary of the CPU, preventing most of the CPU’s logic from switching. During PD1, DMA transactions can proceed between peripherals and internal memory.

011010

011100

PD2†

PD3†

Wake by a device reset

Wake by a device reset

Output clock from PLL is halted, stopping the internal clock structure from switching and resulting in the entire chip being halted. All register and internal RAM contents are preserved. All functional I/O “freeze” in the last state when the PLL clock is turned off.

Input clock to the PLL stops generating clocks. All register and internal RAM contents are preserved. All functional I/O “freeze” in the last state when the PLL clock is turned off. Following reset, the

PLL needs time to re-lock, just as it does following power-up.

Wake-up from PD3 takes longer than wake-up from PD2 because the PLL needs to be re-locked.

All others Reserved — —

† When entering PD2 and PD3, all functional I/O remains in the previous state. However, for peripherals which are asynchronous in nature or peripherals with an external clock source, output signals may transition in response to stimulus on the inputs. Under these conditions, peripherals will not operate according to specifications.

power-supply sequencing

TI DSPs do not require specific power sequencing between the core supply and the I/O supply. However, systems should be designed to ensure that neither supply is powered up for extended periods of time if the other supply is below the proper operating voltage.

system-level design considerations

System-level design considerations, such as bus contention, may require supply sequencing to be implemented. In this case, the core supply should be powered up at the same time as, or prior to (and powered down after), the I/O buffers. This is to ensure that the I/O buffers receive valid inputs from the core before the output buffers are powered up, thus, preventing bus contention with other chips on the board.

power-supply design considerations

For systems using the C6000



DSP platform of devices, the core supply may be required to provide in excess of 2 A per DSP until the I/O supply is powered up. This extra current condition is a result of uninitialized logic within the DSP(s) and is corrected once the CPU sees an internal clock pulse. With the PLL enabled, as the

I/O supply is powered on, a clock pulse is produced stopping the extra current draw from the supply. With the

PLL disabled, as many as five external clock cycle pulses may be required to stop this extra current draw. A normal current state returns once the I/O power supply is turned on and the CPU sees a clock pulse. Decreasing the amount of time between the core supply power up and the I/O supply power up can minimize the effects of this current draw.

38


•



power-supply design considerations (continued)

A dual-power supply with simultaneous sequencing, such as available with TPS563xx controllers or PT69xx plug-in power modules, can be used to eliminate the delay between core and I/O power up [see the Using the

TPS56300 to Power DSPs application report (literature number SLVA088)]. A Schottky diode can also be used to tie the core rail to the I/O rail, effectively pulling up the I/O power supply to a level that can help initialize the logic within the DSP.

Core and I/O supply voltage regulators should be located close to the DSP (or DSP array) to minimize inductance and resistance in the power delivery path. Additionally, when designing for high-performance applications utilizing the C6000



platform of DSPs, the PC board should include separate power planes for core, I/O, and ground, all bypassed with high-quality low-ESL/ESR capacitors.

absolute maximum ratings over operating case temperature ranges (unless otherwise noted)

†

Supply voltage range, CV

DD

(see Note 1)

Supply voltage range, DV

DD

(see Note 1)

Input voltage range

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . − 0.3 V to 2.3 V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

−0.3 V to 4 V

−0.3 V to 4 V

Output voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 4 V

Operating case temperature ranges, T

C

:(default)

Storage temperature range, T stg

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

(A version)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Temperature cycle range, (1000-cycle performance): (GHK package)

(GLW package)

. . . . . . . . . . . . . . . . .

. . . . . . . . . . . . . . . . .

0

_

C to 90

_

C

−40

_

C to105

_

C

−65

_

C to 150

_

C

−55

_

C to 125

_

C

−40

_

C to125

_

C

† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTE 1: All voltage values are with respect to VSS

.

recommended operating conditions

CVDD Supply voltage, Core

DVDD Supply voltage, I/O

Supply ground VSS

VIH

VIL

High-level input voltage

Low-level input voltage

IOH

IOL

High-level output current

Low-level output current

(default)

(A version)

MIN NOM MAX UNIT

1.43

1.5

1.57

V

3.14

3.3

3.46

V

0

2

0

−40

0 0

0.8

−8 mA

8 mA

90

_

C

105

_

C

V

V

V


•


39


electrical characteristics over recommended ranges of supply voltage and operating case temperature (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

VOH

VOL

II

IOZ

High-level output voltage

Low-level output voltage

Input current‡

Off-state output current

IDD2V Supply current, CPU + CPU memory access§

IDD2V Supply current, peripherals§

IDD3V Supply current, I/O pins§

DVDD = MIN,

DVDD = MIN,

VI = VSS to DVDD

VO = DVDD or 0 V

CVDD

CVDD

DVDD

IOH = MAX

IOL = MAX

= NOM, CPU clock = 200 MHz



2.4

290

240

100

0.6

±

10

±

10

V

V uA uA mA mA mA

Ci Input capacitance 10 pF

Co Output capacitance 10 pF

‡ TMS and TDI are not included due to internal pullups. TRST is not included due to internal pulldown.

§ Measured with average activity (50% high / 50% low power). For more details on CPU, peripheral, and I/O activity, see the TMS320C6000 Power

Consumption Summary application report (literature number SPRA486).

40


•



PARAMETER MEASUREMENT INFORMATION

IOL

Tester Pin

Electronics

Vcomm

50

Ω

Output

Under

Test

CT

IOH

Where: IOL

IOH

= 2 mA

= 2 mA

Vcomm = 1.5 V

CT = 15−30-pF typical load-circuit capacitance

Figure 9. Test Load Circuit for AC Timing Measurements

signal transition levels

All input and output timing parameters are referenced to 1.5 V for both “0” and “1” logic levels.

Vref = 1.5 V

Figure 10. Input and Output Voltage Reference Levels for ac Timing Measurements

All rise and fall transition timing parameters are referenced to V

IL

MAX and V

IH

MIN for input clocks, and

V

OL

MAX and V

OH

MIN for output clocks.

Vref = VIH MIN (or VOH MIN)

Vref = VIL MAX (or VOL MAX)

Figure 11. Rise and Fall Transition Time Voltage Reference Levels


•


41


INPUT AND OUTPUT CLOCKS timing requirements for CLKIN

†‡§

(see Figure 12)

NO.

PLL Mode x4

-200

PLL Mode x1

(BYPASS)

MAX

1 tc(CLKIN) Cycle time, CLKIN

2 tw(CLKINH) Pulse duration, CLKIN high

3 tw(CLKINL) Pulse duration, CLKIN low

4 tt(CLKIN) Transition time, CLKIN

† The reference points for the rise and fall transitions are measured at VIL MAX and VIH MIN.

‡ M = the PLL multiplier factor (x4). For more details, see the Clock PLL section of this data sheet.

§ C = CLKIN cycle time in ns. For example, when CLKIN frequency is 50 MHz, use C = 20 ns.

MIN MAX MIN

5 * M 5

0.4C

0.4C

5

0.45C

0.45C

0.6

UNIT

ns ns ns ns

1

4

2

CLKIN

3

4

Figure 12. CLKIN Timings

timing requirements for XCLKIN

¶

(see Figure 13)

1 tc(XCLKIN) Cycle time, XCLKIN

2 tw(XCLKINH) Pulse duration, XCLKIN high

3 tw(XCLKINL) Pulse duration, XCLKIN low

¶ P = 1/CPU clock frequency in nanoseconds (ns).

-200

MIN MAX

4P

1.8P

1.8P

ns ns ns

1

2

XCLKIN

3

Figure 13. XCLKIN Timings

42


•



INPUT AND OUTPUT CLOCKS (CONTINUED) switching characteristics over recommended operating conditions for CLKOUT1

†‡§

(see Figure 14)

-200

CLKMODE = X4 CLKMODE = X1

MIN MAX MIN MAX

1

2

3 tc(CKO1) Cycle time, CLKOUT1 tw(CKO1H) Pulse duration, CLKOUT1 high tw(CKO1L) Pulse duration, CLKOUT1 low

P − 0.7

(P/2) − 0.7

(P/2) − 0.7

4 tt(CKO1) Transition time, CLKOUT1

† The reference points for the rise and fall transitions are measured at VOL MAX and VOH MIN.

‡ PH is the high period of CLKIN in ns and PL is the low period of CLKIN in ns.

§ P = 1/CPU clock frequency in ns.

P + 0.7

(P/2 ) + 0.7

(P/2 ) + 0.7

0.6

P − 0.7

PH − 0.7

PL − 0.7

P + 0.7

PH + 0.7

PL + 0.7

0.6

ns ns ns ns

1

4

2

CLKOUT1

3

4

Figure 14. CLKOUT1 Timings

switching characteristics over recommended operating conditions for CLKOUT2

†§

(see Figure 15)

2

3 tw(CKO2H) tw(CKO2L)

Pulse duration, CLKOUT2 high

Pulse duration, CLKOUT2 low

4 tt(CKO2) Transition time, CLKOUT2

† The reference points for the rise and fall transitions are measured at VOL MAX and VOH MIN.

§ P = 1/CPU clock frequency in ns.

-200

MIN MAX

P − 0.7

P + 0.7

P − 0.7

P + 0.7

0.6

ns ns ns

1

4

2

CLKOUT2

3

4

Figure 15. CLKOUT2 Timings


•


43


INPUT AND OUTPUT CLOCKS (CONTINUED) switching characteristics over recommended operating conditions for XFCLK

†‡

(see Figure 16)

1

2 tc(XFCK) tw(XFCKH)

Cycle time, XFCLK

Pulse duration, XFCLK high

3 tw(XFCKL) Pulse duration, XFCLK low

4 tt(CKO2) Transition time, XFCLK

† P = 1/CPU clock frequency in ns.

‡ D = 8, 6, 4, or 2; FIFO clock divide ratio, user-programmable

-200

MIN

D * P − 0.7

MAX

D * P + 0.7

(D/2) * P − 0.7

(D/2) * P + 0.7

(D/2) * P − 0.7

(D/2) * P + 0.7

0.6

ns ns ns ns

1

4

2

XFCLK

3

4

Figure 16. XFCLK Timings

44


•



ASYNCHRONOUS MEMORY TIMING timing requirements for asynchronous memory cycles

†‡§¶

(see Figure 17 − Figure 20)

-200

MIN MAX

3

4

6

7 tsu(EDV-AREH) Setup time, EDx valid before ARE high th(AREH-EDV) Hold time, EDx valid after ARE high tsu(ARDYH-AREL) Setup time, ARDY high before ARE low th(AREL-ARDYH) Hold time, ARDY high after ARE low

9 tsu(ARDYL-AREL) Setup time, ARDY low before ARE low

10 th(AREL-ARDYL) Hold time, ARDY low after ARE low

1.5

3.5

−[(RST − 3) * P − 6]

(RST − 3) * P + 3

−[(RST − 3) * P − 6]

(RST − 3) * P + 3 ns ns ns ns ns ns

11 tw(ARDYH) Pulse width, ARDY high

15 tsu(ARDYH-AWEL) Setup time, ARDY high before AWE low

16 th(AWEL-ARDYH) Hold time, ARDY high after AWE low

2P

−[(WST − 3) * P − 6]

(WST − 3) * P + 3 ns ns ns

18 tsu(ARDYL-AWEL) Setup time, ARDY low before AWE low −[(WST − 3) * P − 6] ns

19 th(AWEL-ARDYL) Hold time, ARDY low after AWE low (WST − 3) * P + 3 ns

† To ensure data setup time, simply program the strobe width wide enough. ARDY is internally synchronized. If ARDY does meet setup or hold time, it may be recognized in the current cycle or the next cycle. Thus, ARDY can be an asynchronous input.

‡ RS = Read Setup, RST = Read Strobe, RH = Read Hold, WS = Write Setup, WST = Write Strobe, WH = Write Hold. These parameters are programmed via the EMIF CE space control registers.

§ P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns.

¶ The sum of RS and RST (or WS and WST) must be a minimum of 4 in order to use ARDY input to extend strobe width.

switching characteristics over recommended operating conditions for asynchronous memory cycles

‡§¶#

(see Figure 17 − Figure 20)

MIN

-200

TYP MAX

1

2

5 tosu(SELV-AREL) Output setup time, select signals valid to ARE low toh(AREH-SELIV) Output hold time, ARE high to select signals invalid tw(AREL) Pulse width, ARE low

8 td(ARDYH-AREH) Delay time, ARDY high to ARE high

12 tosu(SELV-AWEL) Output setup time, select signals valid to AWE low

13 toh(AWEH-SELIV) Output hold time, AWE high to select signals invalid

14 tw(AWEL) Pulse width, AWE low

RS * P − 2

RH * P − 2

3P

WS * P − 2

WH * P − 2

RST * P

WST * P

4P + 5 ns ns ns ns ns ns ns

17 td(ARDYH-AWEH) Delay time, ARDY high to AWE high 3P 4P + 5 ns

‡ RS = Read Setup, RST = Read Strobe, RH = Read Hold, WS = Write Setup, WST = Write Strobe, WH = Write Hold. These parameters are programmed via the EMIF CE space control registers.


¶ The sum of RS and RST (or WS and WST) must be a minimum of 4 in order to use ARDY input to extend strobe width.

# Select signals include: CEx, BE[3:0], EA[21:2], AOE; and for writes, include ED[31:0], with the exception that CEx can stay active for an additional

7P ns following the end of the cycle.


•


45


ASYNCHRONOUS MEMORY TIMING (CONTINUED)

Setup = 2 Strobe = 3 Hold = 2

CLKOUT1

1 2

CEx

1 2

BE[3:0]

1 2

EA[21:2]

3

4

ED[31:0]

1

2

AOE

5

6

7

ARE

AWE

ARDY

Figure 17. Asynchronous Memory Read Timing (ARDY Not Used)

Setup = 2 Strobe = 3 Not Ready Hold = 2

CLKOUT1

CEx

1

1

BE[3:0]

1

EA[21:2]

3

4

ED[31:0]

1

AOE

8

10

9

ARE

AWE

11

ARDY

2

2

2

2

Figure 18. Asynchronous Memory Read Timing (ARDY Used)

46


•



ASYNCHRONOUS MEMORY TIMING (CONTINUED)


CLKOUT1

CEx

12 13

12 13

BE[3:0]

EA[21:2]

12 13

12 13

ED[31:0]

AOE

ARE

15

16

14

AWE

ARDY

Figure 19. Asynchronous Memory Write Timing (ARDY Not Used)


CLKOUT1

12

CEx

12

BE[3:0]

12

EA[21:2]

12

ED[31:0]

13

13

13

13

AOE

ARE

17

18

19

AWE

ARDY

11

Figure 20. Asynchronous Memory Write Timing (ARDY Used)


•


47


SYNCHRONOUS-BURST MEMORY TIMING timing requirements for synchronous-burst SRAM cycles (see Figure 21)

7

8 tsu(EDV-CKO2H) th(CKO2H-EDV)

Setup time, read EDx valid before CLKOUT2 high

Hold time, read EDx valid after CLKOUT2 high

-200

MIN MAX

2.5

1.5

ns ns

switching characteristics over recommended operating conditions for synchronous-burst SRAM cycles

†‡

(see Figure 21 and Figure 22)

MIN

-200

MAX

1

2

3

4 tosu(CEV-CKO2H) Output setup time, CEx valid before CLKOUT2 high toh(CKO2H-CEV) Output hold time, CEx valid after CLKOUT2 high tosu(BEV-CKO2H) Output setup time, BEx valid before CLKOUT2 high toh(CKO2H-BEIV) Output hold time, BEx invalid after CLKOUT2 high

5

6

9 tosu(EAV-CKO2H) Output setup time, EAx valid before CLKOUT2 high toh(CKO2H-EAIV) Output hold time, EAx invalid after CLKOUT2 high tosu(ADSV-CKO2H) Output setup time, SDCAS/SSADS valid before CLKOUT2 high

10 toh(CKO2H-ADSV) Output hold time, SDCAS/SSADS valid after CLKOUT2 high

11 tosu(OEV-CKO2H) Output setup time, SDRAS/SSOE valid before CLKOUT2 high

12 toh(CKO2H-OEV) Output hold time, SDRAS/SSOE valid after CLKOUT2 high

13 tosu(EDV-CKO2H) Output setup time, EDx valid before CLKOUT2 high§

14 toh(CKO2H-EDIV) Output hold time, EDx invalid after CLKOUT2 high

15 tosu(WEV-CKO2H) Output setup time, SDWE/SSWE valid before CLKOUT2 high

P − 0.8

P − 4

P − 0.8

P − 4

P − 0.8

P − 4

P − 0.8

P − 4

P − 0.8

P − 4

P − 1

P − 4

P − 0.8

ns ns ns ns ns ns ns ns ns ns ns ns ns

16 toh(CKO2H-WEV) Output hold time, SDWE/SSWE valid after CLKOUT2 high P − 4 ns

† P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns.

‡ SDCAS/SSADS, SDRAS/SSOE, and SDWE/SSWE operate as SSADS, SSOE, and SSWE, respectively, during SBSRAM accesses.

§ For the first write in a series of one or more consecutive adjacent writes, the write data is generated one CLKOUT2 cycle early to accommodate the ED enable time.

48


•



SYNCHRONOUS-BURST MEMORY TIMING (CONTINUED)

CLKOUT2

1 2

CEx

BE[3:0]

3

BE1

5

A1

BE2 BE3 BE4

4

6

EA[21:2]

A2 A3

Q1

7

A4

8

Q2

ED[31:0]

9 10

Q3 Q4

SDCAS/SSADS†

11 12

SDRAS/SSOE†

SDWE/SSWE†

† SDCAS/SSADS, SDRAS/SSOE, and SDWE/SSWE operate as SSADS, SSOE, and SSWE, respectively, during SBSRAM accesses.

Figure 21. SBSRAM Read Timing

CLKOUT2

1 2

CEx

BE[3:0]

EA[21:2]

3

BE1

5

A1

BE2

A2

BE3

A3

BE4

A4

4

6

13 14

Q1 Q2 Q3 Q4

ED[31:0]

9 10

SDCAS/SSADS†

SDRAS/SSOE†

15 16

SDWE/SSWE†

† SDCAS/SSADS, SDRAS/SSOE, and SDWE/SSWE operate as SSADS, SSOE, and SSWE, respectively, during SBSRAM accesses.

Figure 22. SBSRAM Write Timing


•


49


SYNCHRONOUS DRAM TIMING timing requirements for synchronous DRAM cycles (see Figure 23)

7

8 tsu(EDV-CKO2H) Setup time, read EDx valid before CLKOUT2 high th(CKO2H-EDV) Hold time, read EDx valid after CLKOUT2 high

-200

MIN MAX

1.25

3 ns ns

switching characteristics over recommended operating conditions for synchronous DRAM cycles

†‡

(see Figure 23−Figure 28)

MIN

-200

MAX

1

2

3

4 tosu(CEV-CKO2H) toh(CKO2H-CEV) tosu(BEV-CKO2H) toh(CKO2H-BEIV)

5

6

9 tosu(EAV-CKO2H) toh(CKO2H-EAIV) tosu(CASV-CKO2H)

10 toh(CKO2H-CASV)

11 tosu(EDV-CKO2H)

12 toh(CKO2H-EDIV)

Output setup time, CEx valid before CLKOUT2 high

Output hold time, CEx valid after CLKOUT2 high

Output setup time, BEx valid before CLKOUT2 high

Output hold time, BEx invalid after CLKOUT2 high

Output setup time, EAx valid before CLKOUT2 high

Output hold time, EAx invalid after CLKOUT2 high

Output setup time, SDCAS/SSADS valid before CLKOUT2 high

Output hold time, SDCAS/SSADS valid after CLKOUT2 high

Output setup time, EDx valid before CLKOUT2 high§

Output hold time, EDx invalid after CLKOUT2 high

P − 1

P − 3.5

P − 1

P − 3.5

P − 1

P − 3.5

P − 1

P − 3.5

P − 3

P − 3.5

ns ns ns ns ns ns ns ns ns ns

13 tosu(WEV-CKO2H)

14 toh(CKO2H-WEV)

Output setup time, SDWE/SSWE valid before CLKOUT2 high

Output hold time, SDWE/SSWE valid after CLKOUT2 high

15 tosu(SDA10V-CKO2H) Output setup time, SDA10 valid before CLKOUT2 high

P − 1

P − 3.5

P − 1 ns ns ns

16 toh(CKO2H-SDA10IV) Output hold time, SDA10 invalid after CLKOUT2 high

17 tosu(RASV-CKO2H) Output setup time, SDRAS/SSOE valid before CLKOUT2 high

P − 3.5

P − 1 ns ns

18 toh(CKO2H-RASV) Output hold time, SDRAS/SSOE valid after CLKOUT2 high P − 3.5

ns


‡ SDCAS/SSADS, SDRAS/SSOE, and SDWE/SSWE operate as SDCAS, SDRAS, and SDWE, respectively, during SDRAM accesses.

§ For the first write in a series of one or more consecutive adjacent writes, the write data is generated one CLKOUT2 cycle early to accommodate the ED enable time.

50


•



SYNCHRONOUS DRAM TIMING (CONTINUED)

READ

READ

READ

CLKOUT2

1 2

CEx

BE[3:0]

EA[15:2]

5

CA1

3

BE1

6

CA2

4

BE2

CA3

BE3

ED[31:0]

15 16

7

D1

8

D2 D3

SDA10

SDRAS/SSOE†

9 10

SDCAS/SSADS†

SDWE/SSWE†

† SDCAS/SSADS, SDRAS/SSOE, and SDWE/SSWE operate as SDCAS, SDRAS, and SDWE, respectively, during SDRAM accesses.

Figure 23. Three SDRAM READ Commands

WRITE

WRITE WRITE

CLKOUT2

1

2

CEx

BE[3:0]

EA[15:2]

3

5

BE1

11

CA1

D1

15

4

BE2

6

CA2

12

D2

BE3

CA3

D3

ED[31:0]

SDA10

16

SDRAS/SSOE†

9 10

SDCAS/SSADS†

13 14

SDWE/SSWE†


Figure 24. Three SDRAM WRT Commands


•


51



ACTV

CLKOUT2

1

2

CEx

BE[3:0]

EA[15:2]

ED[31:0]

5

Bank Activate/Row Address

15

SDA10

17

Row Address

18

SDRAS/SSOE†

SDCAS/SSADS†

SDWE/SSWE†


Figure 25. SDRAM ACTV Command

DCAB

CLKOUT2

1

2

CEx

BE[3:0]

EA[15:2]

ED[31:0]

15

16

SDA10

17

18

SDRAS/SSOE†

SDCAS/SSADS†

13

14

SDWE/SSWE†


Figure 26. SDRAM DCAB Command

52


•




REFR

CLKOUT2

1

2

CEx

BE[3:0]

EA[15:2]

ED[31:0]

SDA10

17

18

SDRAS/SSOE†

9

10

SDCAS/SSADS†

SDWE/SSWE†


Figure 27. SDRAM REFR Command

MRS

CLKOUT2

1

2

CEx

BE[3:0]

EA[15:2]

ED[31:0]

5

MRS Value

6

SDA10

17

18

SDRAS/SSOE†

9

10

SDCAS/SSADS†

13

14

SDWE/SSWE†


Figure 28. SDRAM MRS Command


•


53


HOLD/HOLDA TIMING timing requirements for the HOLD/HOLDA cycles

†

(see Figure 29)

-200

MIN MAX

P 3 toh(HOLDAL-HOLDL) Output hold time, HOLD low after HOLDA low


ns

switching characteristics over recommended operating conditions for the HOLD/HOLDA cycles

†‡

(see Figure 29)

-200

1

2 td(HOLDL-EMHZ) td(EMHZ-HOLDAL)

Delay time, HOLD low to EMIF Bus high impedance

Delay time, EMIF Bus high impedance to HOLDA low

MIN MAX

4P

0

§

2P ns ns

4 td(HOLDH-EMLZ) Delay time, HOLD high to EMIF Bus low impedance 3P 7P ns

5 td(EMLZ-HOLDAH) Delay time, EMIF Bus low impedance to HOLDA high 0 2P ns


‡ EMIF Bus consists of CE[3:0], BE[3:0], ED[31:0], EA[21:2], ARE, AOE, AWE, SDCAS/SSADS, SDRAS/SSOE, SDWE/SSWE, and SDA10.

§ All pending EMIF transactions are allowed to complete before HOLDA is asserted. The worst case for this is an asynchronous read or write with external ARDY used or a minimum of eight consecutive SDRAM reads or writes when RBTR8 = 1. If no bus transactions are occurring, then the minimum delay time can be achieved. Also, bus hold can be indefinitely delayed by setting NOHOLD = 1.

DSP Owns Bus

External Requestor

Owns Bus

DSP Owns Bus

3

HOLD

2 5

HOLDA

1

4

EMIF Bus†

C6204 C6204

† EMIF Bus consists of CE[3:0], BE[3:0], ED[31:0], EA[21:2], ARE, AOE, AWE, SDCAS/SSADS, SDRAS/SSOE, SDWE/SSWE, and SDA10.

Figure 29. HOLD/HOLDA Timing

54


•



RESET TIMING timing requirements for reset

†

(see Figure 30)

-200

MIN MAX

Width of the RESET pulse (PLL stable)‡

Width of the RESET pulse (PLL needs to sync up)§

10P

250 ns

µ s

10 tsu(XD) Setup time, XD configuration bits valid before RESET high¶ 5P ns

11 th(XD) Hold time, XD configuration bits valid after RESET high¶ 5P ns


‡ This parameter applies to CLKMODE x1 when CLKIN is stable, and applies to CLKMODE x4 when CLKIN and PLL are stable.

§ This parameter applies to CLKMODE x4 only (it does not apply to CLKMODE x1). The RESET signal is not connected internally to the Clock

PLL circuit. The PLL requires a minimum of 250

µ s to stabilize following device power up or after PLL configuration has been changed. During that time, RESET must be asserted to ensure proper device operation. See the clock PLL section for PLL lock times.

¶ XD[31:0] are the boot configuration pins during device reset.

switching characteristics over recommended operating conditions during reset

†#

(see Figure 30)

-200

MIN MAX

2

3

4

5

6 td(RSTL-CKO2IV) td(RSTH-CKO2V) td(RSTL-HIGHIV) td(RSTH-HIGHV) td(RSTL-LOWIV)

Delay time, RESET low to CLKOUT2 invalid

Delay time, RESET high to CLKOUT2 valid

Delay time, RESET low to high group invalid

Delay time, RESET high to high group valid

Delay time, RESET low to low group invalid

P

P

P

4P

4P ns ns ns ns ns

7

8 td(RSTH-LOWV) td(RSTL-ZHZ)

Delay time, RESET high to low group valid

Delay time, RESET low to Z group high impedance P

4P ns ns

9 td(RSTH-ZV) Delay time, RESET high to Z group valid 4P ns


# High group consists of:

XFCLK, HOLDA

Low group consists of:

Z group consists of:

IACK, INUM[3:0], DMAC[3:0], PD, TOUT0, and TOUT1.

EA[21:2], ED[31:0], CE[3:0], BE[3:0], ARE, AWE, AOE, SDCAS/SSADS, SDRAS/SSOE, SDWE/SSWE,

SDA10, CLKX0, CLKX1, FSX0, FSX1, DX0, DX1, CLKR0, CLKR1, FSR0, FSR1, XCE[3:0], XBE[3:0]/XA[5:2],

XOE, XRE, XWE/XWAIT, XAS, XW/R, XRDY, XBLAST, XHOLD, and XHOLDA.


•


55


RESET TIMING (CONTINUED)

CLKOUT1

1

10

11

RESET

2 3

CLKOUT2

4 5

HIGH GROUP†

6 7

LOW GROUP†

8

9

Z GROUP†

XD[31:0]‡

Boot Configuration

† High group consists of:

Low group consists of:

Z group consists of:

XFCLK, HOLDA

IACK, INUM[3:0], DMAC[3:0], PD, TOUT0, and TOUT1.

EA[21:2], ED[31:0], CE[3:0], BE[3:0], ARE, AWE, AOE, SDCAS/SSADS, SDRAS/SSOE, SDWE/SSWE,

SDA10, CLKX0, CLKX1, FSX0, FSX1, DX0, DX1, CLKR0, CLKR1, FSR0, FSR1, XCE[3:0], XBE[3:0]/XA[5:2],

XOE, XRE, XWE/XWAIT, XAS, XW/R, XRDY, XBLAST, XHOLD, and XHOLDA.

‡ XD[31:0] are the boot configuration pins during device reset.

Figure 30. Reset Timing

56


•



EXTERNAL INTERRUPT TIMING timing requirements for interrupt response cycles

†

(see Figure 31)

2 tw(ILOW) Width of the interrupt pulse low

3 tw(IHIGH) Width of the interrupt pulse high


-200

MIN MAX

2P

2P ns ns

switching characteristics over recommended operating conditions during interrupt response cycles

†

(see Figure 31)

1 tR(EINTH − IACKH) Response time, EXT_INTx high to IACK high

4

5 td(CKO2L-IACKV) td(CKO2L-INUMV)

Delay time, CLKOUT2 low to IACK valid

Delay time, CLKOUT2 low to INUMx valid

6 td(CKO2L-INUMIV) Delay time, CLKOUT2 low to INUMx invalid


1

-200

MIN MAX

9P

0

0

0 ns

10 ns

10 ns

10 ns

CLKOUT2

3

2

EXT_INTx, NMI

Intr Flag

4

4

IACK

6

5

INUMx Interrupt Number

Figure 31. Interrupt Timing


•


57


EXPANSION BUS SYNCHRONOUS FIFO TIMING timing requirements for synchronous FIFO interface (see Figure 32, Figure 33, and Figure 34)

5

6 tsu(XDV-XFCKH) th(XFCKH-XDV)

Setup time, read XDx valid before XFCLK high

Hold time, read XDx valid after XFCLK high

-200

MIN MAX

3.5

2 ns ns

switching characteristics over recommended operating conditions for synchronous FIFO interface (see Figure 32, Figure 33, and Figure 34)

1

2

3

4

7 td(XFCKH-XCEV) td(XFCKH-XAV) td(XFCKH-XOEV) td(XFCKH-XREV) td(XFCKH-XWEV)

Delay time, XFCLK high to XCEx valid

Delay time, XFCLK high to XBE[3:0]/XA[5:2] valid†

Delay time, XFCLK high to XOE valid

Delay time, XFCLK high to XRE valid

Delay time, XFCLK high to XWE/XWAIT‡ valid

8 td(XFCKH-XDV) Delay time, XFCLK high to XDx valid

9 td(XFCKH-XDIV) Delay time, XFCLK high to XDx invalid

† XBE[3:0]/XA[5:2] operate as address signals XA[5:2] during synchronous FIFO accesses.

‡ XWE/XWAIT operates as the write-enable signal XWE during synchronous FIFO accesses.

-200

MIN MAX

1 7

1 7

1

1

1

7

7

7

9

1 ns ns ns ns ns ns ns

XFCLK

1 1

XCE3†

XBE[3:0]/XA[5:2]‡

2

XA1

3

XA2 XA3

XOE

4

XRE

XWE/XWAIT§

6

5

XD[31:0] D1 D2 D3

† FIFO read (glueless) mode only available in XCE3.

‡ XBE[3:0]/XA[5:2] operate as address signals XA[5:2] during synchronous FIFO accesses.

§ XWE/XWAIT operates as the write-enable signal XWE during synchronous FIFO accesses.

Figure 32. FIFO Read Timing (Glueless Read Mode)

XA4

4

D4

2

3

58


•



EXPANSION BUS SYNCHRONOUS FIFO TIMING (CONTINUED)

XFCLK

1

XCEx

XBE[3:0]/XA[5:2]†

2

XA1

3

XA2 XA3

XOE

4

XRE

XWE/XWAIT‡

6

5

XD[31:0]

D1 D2



Figure 33. FIFO Read Timing

D3

XA4

4

D4

1

2

3

XFCLK

1

XCEx

XBE[3:0]/XA[5:2]†

XOE

XRE

2

XA1 XA2 XA3

7

XWE/XWAIT‡

XD[31:0]

8

D1 D2



Figure 34. FIFO Write Timing

D3

XA4

D4

1

2

7

9


•


59


EXPANSION BUS ASYNCHRONOUS PERIPHERAL TIMING timing requirements for asynchronous peripheral cycles

†‡§¶


-200

MIN MAX

3

4

6

7 tsu(XDV-XREH) Setup time, XDx valid before XRE high th(XREH-XDV) Hold time, XDx valid after XRE high tsu(XRDYH-XREL) Setup time, XRDY high before XRE low th(XREL-XRDYH) Hold time, XRDY high after XRE low

9 tsu(XRDYL-XREL) Setup time, XRDY low before XRE low

10 th(XREL-XRDYL) Hold time, XRDY low after XRE low

8.5

1

−[(RST − 3) * P − 10]

(RST − 3) * P + 2

−[(RST − 3) * P − 6]

(RST − 3) * P + 2 ns ns ns ns ns ns

11 tw(XRDYH) Pulse width, XRDY high

15 tsu(XRDYH-XWEL) Setup time, XRDY high before XWE low

16 th(XWEL-XRDYH) Hold time, XRDY high after XWE low

2P

−[(WST − 3) * P − 10]

(WST − 3) * P + 2 ns ns ns

18 tsu(XRDYL-XWEL) Setup time, XRDY low before XWE low −[(WST − 3) * P − 6] ns

19 th(XWEL-XRDYL) Hold time, XRDY low after XWE low (WST − 3) * P + 2 ns

† To ensure data setup time, simply program the strobe width wide enough. XRDY is internally synchronized. If XRDY does meet setup or hold time, it may be recognized in the current cycle or the next cycle. Thus, XRDY can be an asynchronous input.

‡ RS = Read Setup, RST = Read Strobe, RH = Read Hold, WS = Write Setup, WST = Write Strobe, WH = Write Hold. These parameters are programmed via the XBUS XCE space control registers.


¶ The sum of RS and RST (or WS and WST) must be a minimum of 4 in order to use XRDY input to extend strobe width.

switching characteristics over recommended operating conditions for asynchronous peripheral cycles

‡§¶#


MIN

-200

TYP MAX

1

2

5 tosu(SELV-XREL) Output setup time, select signals valid to XRE low toh(XREH-SELIV) Output hold time, XRE low to select signals invalid tw(XREL) Pulse width, XRE low

8 td(XRDYH-XREH) Delay time, XRDY high to XRE high

12 tosu(SELV-XWEL) Output setup time, select signals valid to XWE low

13 toh(XWEH-SELIV) Output hold time, XWE low to select signals invalid

14 tw(XWEL) Pulse width, XWE low

RS * P − 2

RH * P − 2

3P

WS * P − 2

WH * P − 2

RST * P

WST * P

4P + 5 ns ns ns ns ns ns ns

17 td(XRDYH-XWEH) Delay time, XRDY high to XWE high 3P 4P + 5 ns

‡ RS = Read Setup, RST = Read Strobe, RH = Read Hold, WS = Write Setup, WST = Write Strobe, WH = Write Hold. These parameters are programmed via the XBUS XCE space control registers.


¶ The sum of RS and RST (or WS and WST) must be a minimum of 4 in order to use XRDY input to extend strobe width.

# Select signals include: XCEx, XBE[3:0]/XA[5:2], XOE; and for writes, include XD[31:0], with the exception that XCEx can stay active for an additional 7P ns following the end of the cycle.

60


•



EXPANSION BUS ASYNCHRONOUS PERIPHERAL TIMING (CONTINUED)


CLKOUT1

1 2

XCEx

1 2

XBE[3:0]/

XA[5:2]†

3

4

XD[31:0]

1

2

XOE

5

6

7

XRE

XWE/XWAIT‡

XRDY§

† XBE[3:0]/XA[5:2] operate as address signals XA[5:2] during expansion bus asynchronous peripheral accesses.

‡ XWE/XWAIT operates as the write-enable signal XWE during expansion bus asynchronous peripheral accesses.

§ XRDY operates as active-high ready input during expansion bus asynchronous peripheral accesses.

Figure 35. Expansion Bus Asynchronous Peripheral Read Timing (XRDY Not Used)


CLKOUT1

1 2

XCEx

XBE[3:0]/

XA[5:2]†

1 2

3

4

XD[31:0]

1 2

XOE

8

10

9

XRE

XWE/XWAIT‡

11

XRDY§




Figure 36. Expansion Bus Asynchronous Peripheral Read Timing (XRDY Used)


•


61


EXPANSION BUS ASYNCHRONOUS PERIPHERAL TIMING (CONTINUED)


CLKOUT1

XCEx

XBE[3:0]/

XA[5:2]†

XD[31:0]

12

12

12

13

13

13

XOE

XRE

15

16

14

XWE/XWAIT‡

XRDY§




Figure 37. Expansion Bus Asynchronous Peripheral Write Timing (XRDY Not Used)


CLKOUT1

12 13

XCEx

XBE[3:0]/

XA[5:2]†

12 13

12 13

XD[31:0]

XOE

XRE

17

18

19

XWE/XWAIT‡

11

XRDY§




Figure 38. Expansion Bus Asynchronous Peripheral Write Timing (XRDY Used)

62


•



EXPANSION BUS SYNCHRONOUS HOST-PORT TIMING timing requirements with external device as bus master (see Figure 39 and Figure 40)

1

2

3

4 tsu(XCSV-XCKIH) Setup time, XCS valid before XCLKIN high th(XCKIH-XCS) Hold time, XCS valid after XCLKIN high tsu(XAS-XCKIH) th(XCKIH-XAS)

Setup time, XAS valid before XCLKIN high

Hold time, XAS valid after XCLKIN high

5

6 tsu(XCTL-XCKIH) Setup time, XCNTL valid before XCLKIN high th(XCKIH-XCTL) Hold time, XCNTL valid after XCLKIN high

7

8 tsu(XWR-XCKIH) th(XCKIH-XWR)

Setup time, XW/R valid before XCLKIN high†

Hold time, XW/R valid after XCLKIN high†

9 tsu(XBLTV-XCKIH) Setup time, XBLAST valid before XCLKIN high‡

10 th(XCKIH-XBLTV) Hold time, XBLAST valid after XCLKIN high‡

16 tsu(XBEV-XCKIH) Setup time, XBE[3:0]/XA[5:2] valid before XCLKIN high§

17 th(XCKIH-XBEV) Hold time, XBE[3:0]/XA[5:2] valid after XCLKIN high§

18 tsu(XD-XCKIH) Setup time, XDx valid before XCLKIN high

19 th(XCKIH-XD) Hold time, XDx valid after XCLKIN high

† XW/R input/output polarity selected at boot.

‡ XBLAST input polarity selected at boot.

§ XBE[3:0]/XA[5:2] operate as byte-enables XBE[3:0] during host-port accesses.

-200

MIN MAX

3.5

2.8

3.5

2.8

3.5

2.8

3.5

2.8

3.5

2.8

3.5

2.8

3.5

2.8

ns ns ns ns

switching characteristics over recommended operating conditions with external device as bus master

¶


ns ns ns ns ns ns ns ns ns ns

11 td(XCKIH-XDLZ)

12 td(XCKIH-XDV)

13 td(XCKIH-XDIV)

Delay time, XCLKIN high to XDx low impedance

Delay time, XCLKIN high to XDx valid

Delay time, XCLKIN high to XDx invalid

14 td(XCKIH-XDHZ)

15 td(XCKIH-XRY)

Delay time, XCLKIN high to XDx high impedance

Delay time, XCLKIN high to XRDY invalid#

20 td(XCKIH-XRYLZ) Delay time, XCLKIN high to XRDY low impedance

21 td(XCKIH-XRYHZ) Delay time, XCLKIN high to XRDY high impedance#

¶ P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns.

# XRDY operates as active-low ready input/output during host-port accesses.

MIN

0

-200

MAX

16.5

5

5

5

4P

16.5

16.5

2P + 5 3P + 16.5

ns ns ns ns ns ns ns


•


63


EXPANSION BUS SYNCHRONOUS HOST-PORT TIMING (CONTINUED)

XCLKIN

2

1

XCS

4

3

XAS

6

5

XCNTL

8

7

XW/R†

8

7

XW/R†

XBE[3:0]/XA[5:2]‡

10

9

XBLAST§

10

9

XBLAST§

XD[31:0]

20

11

12

D1

15

D2 D3 D4

13

14

15

XRDY¶

21

† XW/R input/output polarity selected at boot

‡ XBE[3:0]/XA[5:2] operate as byte-enables XBE[3:0] during host-port accesses.

§ XBLAST input polarity selected at boot

¶ XRDY operates as active-low ready input/output during host-port accesses.

Figure 39. External Host as Bus Master—Read

64


•




XCLKIN

2

1

XCS

4

3

XAS

6

5

XCNTL

8

7

XW/R†

8

7

XW/R†

16

17

XBE1 XBE2 XBE3 XBE4

XBE[3:0]/XA[5:2]‡

9

XBLAST§

9

XBLAST§

18

XD[31:0] D1

20

15

XRDY¶


‡ XBE[3:0]/XA[5:2] operate as byte-enables XBE[3:0] during host-port accesses.

§ XBLAST input polarity selected at boot

¶ XRDY operates as active-low ready input/output during host-port accesses.

19

D2 D3

Figure 40. External Host as Bus Master—Write

D4

10

10

15

21


•


65


EXPANSION BUS SYNCHRONOUS HOST-PORT TIMING (CONTINUED) timing requirements with C62x



as bus master (see Figure 41, Figure 42, and Figure 43)

-200

MIN MAX

9 tsu(XDV-XCKIH)

10 th(XCKIH-XDV)

11 tsu(XRY-XCKIH)

12 th(XCKIH-XRY)

Setup time, XDx valid before XCLKIN high

Hold time, XDx valid after XCLKIN high

Setup time, XRDY valid before XCLKIN high†

Hold time, XRDY valid after XCLKIN high†

14 tsu(XBFF-XCKIH) Setup time, XBOFF valid before XCLKIN high

15 th(XCKIH-XBFF) Hold time, XBOFF valid after XCLKIN high

† XRDY operates as active-low ready input/output during host-port accesses.

3.5

2.8

3.5

2.8

3.5

2.8

ns ns ns ns ns ns

switching characteristics over recommended operating conditions with C62x



as bus master

(see Figure 41, Figure 42, and Figure 43)

1

2

3

4

5

6

7

8 td(XCKIH-XASV) td(XCKIH-XWRV) td(XCKIH-XBLTV) td(XCKIH-XBEV) td(XCKIH-XDLZ) td(XCKIH-XDV) td(XCKIH-XDIV) td(XCKIH-XDHZ)

Delay time, XCLKIN high to XAS valid

Delay time, XCLKIN high to XW/R valid‡

Delay time, XCLKIN high to XBLAST valid§

Delay time, XCLKIN high to XBE[3:0]/XA[5:2] valid¶

Delay time, XCLKIN high to XDx low impedance

Delay time, XCLKIN high to XDx valid

Delay time, XCLKIN high to XDx invalid

Delay time, XCLKIN high to XDx high impedance

13 td(XCKIH-XWTV) Delay time, XCLKIN high to XWE/XWAIT valid#

‡ XW/R input/output polarity selected at boot.

§ XBLAST output polarity is always active low.

¶ XBE[3:0]/XA[5:2] operate as byte-enables XBE[3:0] during host-port accesses.

# XWE/XWAIT operates as XWAIT output signal during host-port accesses.

-200

MIN MAX

5 16.5

5 16.5

5 16.5

5 16.5

0

16.5

5

4P

5 16.5

ns ns ns ns ns ns ns ns ns

66


•




XCLKIN

1

1

XAS

2 2

XW/R†

XW/R†

3

3

XBLAST‡

4 4

XBE[3:0]/XA[5:2]§

XD[31:0]

5

6

AD

7

8

D1

9

BE

10

D2

11

D3 D4

12

XRDY

13

13

XWE/XWAIT¶


‡ XBLAST output polarity is always active low.


¶ XWE/XWAIT operates as XWAIT output signal during host-port accesses.

Figure 41. C62x



as Bus Master—Read

XCLKIN

1

1

XAS

XW/R†

2

XW/R†

2

3

3

XBLAST‡

4 4

XBE[3:0]/XA[5:2]§

XD[31:0]

5

6

Addr D1

11

D2 D3 D4

7

8

12

XRDY

13

13

XWE/XWAIT¶




¶ XWE/XWAIT operates as XWAIT output signal during host-port accesses.

Figure 42. C62x



as Bus Master—Write


•


67



XCLKIN

1 1

XAS

XW/R†

2 2

XW/R†

XBLAST‡

4 4

XBE[3:0]/XA[5:2]§

6

XD[31:0]

XRDY

5

Addr

11

D1

12

D2

8

14

XBOFF

XHOLD¶

XHOLDA¶

XHOLD#

XHOLDA#




¶ Internal arbiter enabled

# External arbiter enabled

|| This diagram illustrates XBOFF timing. Bus arbitration timing is shown in Figure 46 and Figure 47.

Figure 43. C62x



as Bus Master—BOFF Operation

||

15

7

68


•



EXPANSION BUS ASYNCHRONOUS HOST-PORT TIMING timing requirements with external device as asynchronous bus master

†

(see Figure 44 and

Figure 45)

1 tw(XCSL) Pulse duration, XCS low

2

3

4 tw(XCSH) tsu(XSEL-XCSL) th(XCSL-XSEL)

10 th(XRYL-XCSL)

11 tsu(XBEV-XCSH)

Pulse duration, XCS high

Setup time, expansion bus select signals‡ valid before XCS low

Hold time, expansion bus select signals‡ valid after XCS low

Hold time, XCS low after XRDY low

Setup time, XBE[3:0]/XA[5:2] valid before XCS high§

12 th(XCSH-XBEV)

13 tsu(XDV-XCSH)

Hold time, XBE[3:0]/XA[5:2] valid after XCS high§

Setup time, XDx valid before XCS high

14 th(XCSH-XDV) Hold time, XDx valid after XCS high


‡ Expansion bus select signals include XCNTL and XR/W.


MIN

-200

MAX

4P

4P

1

3

P + 1.5

1

3

1

3

switching characteristics over recommended operating conditions with external device as asynchronous bus master

†


ns ns ns ns ns ns ns ns ns

5

6

7

8 td(XCSL-XDLZ) td(XCSH-XDIV) td(XCSH-XDHZ) td(XRYL-XDV)

Delay time, XCS low to XDx low impedance

Delay time, XCS high to XDx invalid

Delay time, XCS high to XDx high impedance

Delay time, XRDY low to XDx valid

9 td(XCSH-XRYH) Delay time, XCS high to XRDY high


-200

MIN MAX

0

0 12

4P

1

0 12 ns ns ns ns ns


•


69


EXPANSION BUS ASYNCHRONOUS HOST-PORT TIMING (CONTINUED)

1

1

2

10

10

XCS

3 3

4 4

XCNTL

XBE[3:0]/XA[5:2]†

3

4

3

4

XR/W‡

3

4

3

4

XR/W‡

XD[31:0]

5 8

Word

7

6 5 8

7

6

9 9

XRDY

† XBE[3:0]/XA[5:2] operate as byte-enables XBE[3:0] during host-port accesses.

‡ XW/R input/output polarity selected at boot

XCS

Figure 44. External Device as Asynchronous Master—Read

10 1

2

10

1

3

4

3

4

XCNTL

11

12

11

12

XBE[3:0]/XA[5:2]†

3

4

3

4

XR/W‡

3

4

3

4

XR/W‡

13

14

13

14

XD[31:0]

9 9

XRDY

† XBE[3:0]/XA[5:2] operate as byte-enables XBE[3:0] during host-port accesses.

‡ XW/R input/output polarity selected at boot

Figure 45. External Device as Asynchronous Master—Write

70


•



XHOLD/XHOLDA TIMING timing requirements for expansion bus arbitration (internal arbiter enabled)

†

(see Figure 46)

-200

MIN MAX

P 3 toh(XHDAH-XHDH) Output hold time, XHOLD high after XHOLDA high


ns

switching characteristics over recommended operating conditions for expansion bus arbitration

(internal arbiter enabled)

†‡

(see Figure 46)

1

2 td(XHDH-XBHZ) td(XBHZ-XHDAH)

Delay time, XHOLD high to XBus high impedance

Delay time, XBus high impedance to XHOLDA high

4 td(XHDL-XHDAL) Delay time, XHOLD low to XHOLDA low

5 td(XHDAL-XBLZ) Delay time, XHOLDA low to XBus low impedance


‡ XBus consists of XBE[3:0]/XA[5:2], XAS, XW/R, and XBLAST.

§ All pending XBus transactions are allowed to complete before XHOLDA is asserted.

DSP Owns Bus

External Requestor

Owns Bus

DSP Owns Bus

3

XHOLD (input)

2 4

XHOLDA (output)

1

XBus† C6204

† XBus consists of XBE[3:0]/XA[5:2], XAS, XW/R, and XBLAST.

5

Figure 46. Expansion Bus Arbitration—Internal Arbiter Enabled

C6204

-200

MIN MAX

3P

§

0

3P

2P

0 2P ns ns ns ns


•


71


XHOLD/XHOLDA TIMING (CONTINUED) switching characteristics over recommended operating conditions for expansion bus arbitration

(internal arbiter disabled)

†

(see Figure 47)

1 td(XHDAH-XBLZ) Delay time, XHOLDA high to XBus low impedance‡

2 td(XBHZ-XHDL) Delay time, XBus high impedance to XHOLD low‡


‡ XBus consists of XBE[3:0]/XA[5:2], XAS, XW/R, and XBLAST.

-200

MIN MAX

2P 2P + 10 ns

0 2P ns

2

XHOLD (output)

XHOLDA (input)

1

XBus†

† XBus consists of XBE[3:0]/XA[5:2], XAS, XW/R, and XBLAST.

C6204

Figure 47. Expansion Bus Arbitration—Internal Arbiter Disabled

72


•



MULTICHANNEL BUFFERED SERIAL PORT TIMING timing requirements for McBSP

†‡

(see Figure 48)

2

3 tc(CKRX) tw(CKRX)

Cycle time, CLKR/X

Pulse duration, CLKR/X high or CLKR/X low

CLKR/X ext

CLKR/X ext

CLKR int

CLKR ext

CLKR int

CLKR ext

CLKR int

MIN

-200

MAX

2P§

P − 1¶

9

2

6

3

8 ns ns

CLKR ext

CLKR int

0.5

4

CLKR ext

CLKX int

3

9

10 tsu(FXH-CKXL)

CLKX ext 2

CLKX int 6

11 th(CKXL-FXH)

CLKX ext 3

† CLKRP = CLKXP = FSRP = FSXP = 0. If the polarity of any of the signals is inverted, then the timing references of that signal are also inverted.

‡ P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns.

§ The maximum bit rate for the C6204 devices is 100 Mbps or CPU/2 (the slower of the two). Care must be taken to ensure that the AC timings specified in this data sheet are met. The maximum bit rate for McBSP-to-McBSP communications is 100 MHz; therefore, the minimum CLKR/X clock cycle is either twice the CPU cycle time (2P), or 10 ns (100 MHz), whichever value is larger. For example, when running parts at 200 MHz

(P = 5 ns), use 10 ns as the minimum CLKR/X clock cycle (by setting the appropriate CLKGDV ratio or external clock source). When running parts at 100 MHz (P = 10 ns), use 2P = 20 ns (50 MHz) as the minimum CLKR/X clock cycle. The maximum bit rate for McBSP-to-McBSP communications applies when the serial port is a master of the clock and frame syncs (with CLKR connected to CLKX, FSR connected to FSX,

CLKXM = FSXM = 1, and CLKRM = FSRM = 0) in data delay 1 or 2 mode (R/XDATDLY = 01b or 10b) and the other device the McBSP communicates to is a slave.

¶ The minimum CLKR/X pulse duration is either (P −1) or 4 ns, whichever is larger. For example, when running parts at 200 MHz (P = 5 ns), use

4 ns as the minimum CLKR/X pulse duration. When running parts at 100 MHz (P = 10 ns), use (P − 1) = 9 ns as the minimum CLKR/X pulse duration.


•


73


MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED) switching characteristics over recommended operating conditions for McBSP

†‡

(see Figure 48)

-200

MIN MAX

1

2

3

4 td(CKSH-CKRXH) tc(CKRX) tw(CKRX) td(CKRH-FRV)

Delay time, CLKS high to CLKR/X high for internal

CLKR/X generated from CLKS input

Cycle time, CLKR/X

Pulse duration, CLKR/X high or CLKR/X low

Delay time, CLKR high to internal FSR valid

CLKR/X int

CLKR/X int

CLKR int

CLKX int

CLKX ext

3

2P−2§¶

−3

3

12

C − 2# C + 2#

−3 3

3

9 ns ns ns ns

12

13 tdis(CKXH-DXHZ) td(CKXH-DXV)

CLKX high

CLKX int

CLKX ext

CLKX int

CLKX ext

−1

2

−1

2

5

9

4

11

FSX int −1 5

14 td(FXH-DXV)

ONLY applies when in data delay 0 (XDATDLY = 00b) mode.

FSX ext 2 12

† CLKRP = CLKXP = FSRP = FSXP = 0. If the polarity of any of the signals is inverted, then the timing references of that signal are also inverted.

‡ Minimum delay times also represent minimum output hold times.


¶ The maximum bit rate for the C6204 devices is 100 Mbps or CPU/2 (the slower of the two). Care must be taken to ensure that the AC timings specified in this data sheet are met. The maximum bit rate for McBSP-to-McBSP communications is 100 MHz; therefore, the minimum CLKR/X clock cycle is either twice the CPU cycle time (2P), or 10 ns (100 MHz), whichever value is larger. For example, when running parts at 200 MHz

(P = 5 ns), use 10 ns as the minimum CLKR/X clock cycle (by setting the appropriate CLKGDV ratio or external clock source). When running parts at 100 MHz (P = 10 ns), use 2P = 20 ns (50 MHz) as the minimum CLKR/X clock cycle. The maximum bit rate for McBSP-to-McBSP communications applies when the serial port is a master of the clock and frame syncs (with CLKR connected to CLKX, FSR connected to FSX,

CLKXM = FSXM = 1, and CLKRM = FSRM = 0) in data delay 1 or 2 mode (R/XDATDLY = 01b or 10b) and the other device the McBSP communicates to is a slave.

# C = H or L

S = sample rate generator input clock = P if CLKSM = 1 (P = 1/CPU clock frequency)

= sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period)

H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even

= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero

L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even


CLKGDV should be set appropriately to ensure the McBSP bit rate does not exceed the 100-MHz limit.

74


•


CLKR

FSR (int)

FSR (ext)

DR

CLKX

FSX (int)

FSX (ext)

FSX (XDATDLY=00b)

DX


MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED)

CLKS

1

4

3

2

3

4

5

6

9

10

11

3

2

3

7

Bit(n-1)

8

(n-2) (n-3)

Bit 0

12

14

13

Bit(n-1)

Figure 48. McBSP Timings

13

(n-2) (n-3)


•


75


MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED) timing requirements for FSR when GSYNC = 1 (see Figure 49)

1

2 tsu(FRH-CKSH) Setup time, FSR high before CLKS high th(CKSH-FRH) Hold time, FSR high after CLKS high

-200

MIN MAX

4

4 ns ns

CLKS

FSR external

CLKR/X (no need to resync)

CLKR/X (needs resync)

1

2

Figure 49. FSR Timing When GSYNC = 1

76


•



MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED) timing requirements for McBSP as SPI master or slave: CLKSTP = 10b, CLKXP = 0

†‡

(see Figure 50)

MASTER SLAVE

MIN MAX MIN MAX

4 tsu(DRV-CKXL) Setup time, DR valid before CLKX low 12

5 th(CKXL-DRV) Hold time, DR valid after CLKX low 4


‡ For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.

-200

2 − 3P

6 + 6P ns ns

switching characteristics over recommended operating conditions for McBSP as SPI master or slave: CLKSTP = 10b, CLKXP = 0

†‡

(see Figure 50)

1

2

3

6

7 th(CKXL-FXL) td(FXL-CKXH) td(CKXH-DXV) tdis(CKXL-DXHZ) tdis(FXH-DXHZ)

Hold time, FSX low after CLKX low¶

Delay time, FSX low to CLKX high#

Delay time, CLKX high to DX valid

Disable time, DX high impedance following last data bit from

CLKX low


FSX high

MASTER§

MIN MAX

-200

MIN

SLAVE

MAX

T − 3 T + 5

L − 4 L + 5

−4

L − 2

5

L + 3

3P + 3

P + 3

5P + 17

3P + 17 ns ns ns ns ns

8 td(FXL-DXV) Delay time, FSX low to DX valid



§ S = sample rate generator input clock = P if CLKSM = 1 (P = 1/CPU clock frequency)


T = CLKX period = (1 + CLKGDV) * S



2P + 2 4P + 17 ns




¶ FSRP = FSXP = 1. As a SPI master, FSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on FSX and FSR is inverted before being used internally.

CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP

CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP

# FSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock

(CLKX).


•


77



CLKX

1 2

FSX

DX

DR

Bit 0

7

6

8

4

Bit(n-1)

3

(n-2)

5

(n-2)

(n-3) (n-4)

Bit 0 Bit(n-1) (n-3) (n-4)

Figure 50. McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 0

78


•




†‡

(see Figure 51)

MASTER SLAVE

MIN MAX MIN MAX

4 tsu(DRV-CKXH) Setup time, DR valid before CLKX high 12

5 th(CKXH-DRV) Hold time, DR valid after CLKX high 4



-200

2 − 3P

5 + 6P ns ns


†‡

(see Figure 51)

1

2

3

6 th(CKXL-FXL) td(FXL-CKXH) td(CKXL-DXV) tdis(CKXL-DXHZ)

Hold time, FSX low after CLKX low¶

Delay time, FSX low to CLKX high#

Delay time, CLKX low to DX valid


CLKX low

MASTER§

MIN MAX

-200

MIN

SLAVE

MAX

L − 2 L + 3

T − 2 T + 3

−2

−2

4

4

3P + 4

3P + 3

5P + 17

5P + 17 ns ns ns ns

7 td(FXL-DXV) Delay time, FSX low to DX valid H − 2 H + 4




2P + 2 4P + 17




= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero ns








(CLKX).


•


79



CLKX

1 2

FSX

DX

DR

6

Bit 0

7

4

Bit(n-1)

3

(n-2)

5

(n-2)

(n-3) (n-4)

Bit 0 Bit(n-1) (n-3) (n-4)


80


•




†‡

(see Figure 52)

MASTER SLAVE

MIN MAX MIN MAX

4 tsu(DRV-CKXH) Setup time, DR valid before CLKX high 12

5 th(CKXH-DRV) Hold time, DR valid after CLKX high 4



-200

2 − 3P

5 + 6P ns ns


†‡

(see Figure 52)

1

2

3

6 th(CKXH-FXL) td(FXL-CKXL) td(CKXL-DXV) tdis(CKXH-DXHZ)

Hold time, FSX low after CLKX high¶

Delay time, FSX low to CLKX low#

Delay time, CLKX low to DX valid


CLKX high

MASTER§

MIN MAX

-200

MIN

SLAVE

MAX

T − 2 T + 3

H − 2 H + 3

−2

H − 2

4

H + 3

3P + 4 5P + 17 ns ns ns ns

7 tdis(FXH-DXHZ)


FSX high

P + 3 3P + 17 ns

8 td(FXL-DXV) Delay time, FSX low to DX valid






2P + 2 4P + 17 ns










(CLKX).


•


81



CLKX

1 2

FSX

DX

DR

7

6

Bit 0

8

4

Bit(n-1)

3

(n-2)

5

(n-2)

(n-3) (n-4)

Bit 0 Bit(n-1) (n-3) (n-4)


82


•




†‡

(see Figure 53)

MASTER SLAVE

MIN MAX MIN MAX

4 tsu(DRV-CKXL) Setup time, DR valid before CLKX low 12

5 th(CKXL-DRV) Hold time, DR valid after CLKX low 4



-200

2 − 3P

5 + 6P ns ns


†‡

(see Figure 53)

1

2

3

6 th(CKXH-FXL) td(FXL-CKXL) td(CKXH-DXV) tdis(CKXH-DXHZ)

Hold time, FSX low after CLKX high¶

Delay time, FSX low to CLKX low#

Delay time, CLKX high to DX valid


CLKX high

MASTER§

MIN MAX

-200

MIN

SLAVE

MAX

H − 2 H + 3

T − 2 T + 1

−2

−2

4

4

3P + 4

3P + 3

5P + 17

5P + 17 ns ns ns ns

7 td(FXL-DXV) Delay time, FSX low to DX valid L − 2 L + 4




2P + 2 4P + 17




= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero ns








(CLKX).


•


83



CLKX

1 2

FSX

DX

DR

Bit 0

6 7

4

Bit(n-1)

3

(n-2)

5

(n-2)

(n-3) (n-4)

Bit 0 Bit(n-1) (n-3)


(n-4)

84


•



DMAC, TIMER, POWER-DOWN TIMING switching characteristics over recommended operating conditions for DMAC outputs

†

(see Figure 54)

-200

MIN MAX

2P − 3 1 tw(DMACH) Pulse duration, DMAC high


1

DMAC[3:0]

Figure 54. DMAC Timing

ns

timing requirements for timer inputs

†

(see Figure 55)

1 tw(TINPH) Pulse duration, TINP high

2 tw(TINPL) Pulse duration, TINP low


-200

MIN MAX

2P

2P

switching characteristics over recommended operating conditions for timer outputs

†

(see Figure 55)

-200

MIN MAX

2P − 3

2P − 3

3 tw(TOUTH) Pulse duration, TOUT high

4 tw(TOUTL) Pulse duration, TOUT low


2

1

TINPx

4

3

TOUTx

Figure 55. Timer Timing

ns ns ns ns


•


85


DMAC, TIMER, POWER-DOWN TIMING (CONTINUED) switching characteristics over recommended operating conditions for power-down outputs

†

(see Figure 56)

-200

MIN MAX

2P ns 1 tw(PDH) Pulse duration, PD high


1

PD

Figure 56. Power-Down Timing

86


•



JTAG TEST-PORT TIMING timing requirements for JTAG test port (see Figure 57)

1

3

4 tc(TCK) Cycle time, TCK tsu(TDIV-TCKH) Setup time, TDI/TMS/TRST valid before TCK high th(TCKH-TDIV) Hold time, TDI/TMS/TRST valid after TCK high

-200

MIN MAX

35

11

9 ns ns ns

switching characteristics over recommended operating conditions for JTAG test port

(see Figure 57)

2 td(TCKL-TDOV) Delay time, TCK low to TDO valid

-200

MIN MAX

−4.5

12 ns

TCK

TDO

TDI/TMS/TRST

1

2

3

Figure 57. JTAG Test-Port Timing

4

2


•


87


MECHANICAL DATA

GHK (S-PBGA-N288)

16,10

15,90

SQ

0,95

0,85

PLASTIC BALL GRID ARRAY

0,80

14,40 TYP

T

R

P

N

M

L

K

J

W

V

U

H

G

F

E

D

C

B

A

1,40 MAX

1 3

2 4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

0,12

0,08

0,55

0,45

∅

0,08

M

0,45

0,35

Seating Plane

0,10

4145273-4/C 12/99

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.

C. MicroStar BGA



configuration

thermal resistance characteristics (S-PBGA package)

NO

1

2

3

4

R

Θ

JC

R

Θ

JA

R

Θ

JA

R

Θ

JA

Junction-to-case

Junction-to-free air



5 R

Θ

JA


† m/s = meters per second

°

C/W

9.5

26.5

23.9

22.6

21.3

Air Flow (m/s†)

N/A

0.00

0.50

1.00

2.00

MicroStar BGA is a trademark of Texas Instruments.

88


•



MECHANICAL DATA

PLASTIC BALL GRID ARRAY (CAVITY DOWN) GLW (S-PBGA-N340)

18,10

17,90

SQ

0,45

0,35

∅

0,10

M

0,80

16,80 TYP

0,40

AB

AA

Y

W

V

U

T

R

P

N

M

L

K

J

H

G

F

E

D

C

B

A

1

2

3 5 7 9 11 13 15 17 19 21

4 6 8 10 12 14 16 18 20 22

2,095 MAX

Seating Plane

0,15

0,50

0,30

4200619/B 01/01

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.

thermal resistance characteristics (S-PBGA package)

NO

1

2

3

R

Θ

JC

R

Θ

JA

R

Θ

JA

Junction-to-case



4

5

R

Θ

JA

R

Θ

JA



† m/s = meters per second

°

C/W

11.7

14.2

12.3

10.9

9.3

Air Flow (m/s†)

N/A

0.00

0.50

1.00

2.00


•


89


REVISION HISTORY

This data sheet revision history highlights the technical changes made to the SPR152B device-specific data sheet to make it an SPRS152C revision.

Scope: Applicable updates to the C62x device family, specifically relating to the C6204 device, have been incorporated.

PAGE(S)

NO.

All

ADDITIONS/CHANGES/DELETIONS

Updated the title for literature number SPRU190 to:

TMS320C6000 DSP Peripherals Overview Reference Guide

10 memory map summary:

Changed the document reference in the last sentence of the paragraph.

11

16

17

36

43 peripheral register descriptions:

Updated the information regarding the document reference.

DMA synchronization events:

Updated the information regarding the document reference.

Table 13, C6202/02B DSP Interrupts:

Changed the document reference in the second footnote to:

TMS320C6000 DSP Interrupt Selector Reference Guide (literature number SPRU646)

Added the power-down mode logic section and accompanying information.

switching characteristics over recommended operating conditions for CLKOUT2 table:

Removed NO. 1 (parameter tc(CKO2) ) from the table.

90


•


PACKAGE OPTION ADDENDUM

4-May-2009 www.ti.com

PACKAGING INFORMATION

Status

(1)

Orderable Device

TMS320C6204GHK200 ACTIVE

TMS320C6204GHK200E OBSOLETE BGA MI

CROSTA

R

TMS320C6204GHKA200 ACTIVE BGA MI

CROSTA

R

TMS320C6204GLW200 ACTIVE BGA

TMS320C6204ZHK200

Package

Type

BGA MI

CROSTA

R

TMS320C6204ZHKA200

TMX320C6204GHK

TMX320C6204GLW

ACTIVE

ACTIVE

BGA MI

CROSTA

R

BGA MI

CROSTA

R

OBSOLETE BGA MI

CROSTA

R

OBSOLETE BGA

Package

Drawing

GHK

GHK

GHK

GLW

ZHK

ZHK

GHK

Pins Package

Qty

288 90

288

288

340

288

288

288

60

1

90 Green (RoHS &

90

Eco Plan

(2)

TBD

TBD

TBD

TBD no Sb/Br)

Green (RoHS & no Sb/Br)

TBD

Lead/Ball Finish MSL Peak Temp

SNPB

Call TI

SNPB

SNPB

SNAGCU

SNAGCU

Call TI

(3)

Level-3-220C-168 HR

Call TI

Level-3-220C-168 HR

Level-4-220C-72 HR

Level-3-260C-168 HR

Level-3-260C-168 HR

Call TI

GLW 340 TBD Call TI Call TI

(1)

The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2)

Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

(3)

MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 1

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TMS320C6204

GHK and GLW BGA packages (bottom view)

description

device characteristics

device characteristics (continued)

C62x

device compatibility

functional and CPU (DSP core) block diagram

CPU (DSP core) description

CPU (DSP core) description (continued)

memory map summary

peripheral register descriptions

peripheral register descriptions (continued)

peripheral register descriptions (continued)

peripheral register descriptions (continued)

peripheral register descriptions (continued)

DMA channel synchronization events

interrupt sources and interrupt selector

signal groups description

signal groups description (continued)

signal groups description (continued)

development support

documentation support

clock PLL

clock PLL (continued)

power-down mode logic

power-supply sequencing

absolute maximum ratings over operating case temperature ranges (unless otherwise noted)

recommended operating conditions

electrical characteristics over recommended ranges of supply voltage and operating case temperature (unless otherwise noted)

PARAMETER MEASUREMENT INFORMATION

signal transition levels

INPUT AND OUTPUT CLOCKS timing requirements for CLKIN

(see Figure 12)

timing requirements for XCLKIN

(see Figure 13)

INPUT AND OUTPUT CLOCKS (CONTINUED) switching characteristics over recommended operating conditions for CLKOUT1

(see Figure 14)

switching characteristics over recommended operating conditions for CLKOUT2

(see Figure 15)

INPUT AND OUTPUT CLOCKS (CONTINUED) switching characteristics over recommended operating conditions for XFCLK

(see Figure 16)

ASYNCHRONOUS MEMORY TIMING timing requirements for asynchronous memory cycles

(see Figure 17 − Figure 20)

switching characteristics over recommended operating conditions for asynchronous memory cycles

(see Figure 17 − Figure 20)

ASYNCHRONOUS MEMORY TIMING (CONTINUED)

ASYNCHRONOUS MEMORY TIMING (CONTINUED)

SYNCHRONOUS-BURST MEMORY TIMING timing requirements for synchronous-burst SRAM cycles (see Figure 21)

switching characteristics over recommended operating conditions for synchronous-burst SRAM cycles

(see Figure 21 and Figure 22)

SYNCHRONOUS-BURST MEMORY TIMING (CONTINUED)

SYNCHRONOUS DRAM TIMING timing requirements for synchronous DRAM cycles (see Figure 23)

switching characteristics over recommended operating conditions for synchronous DRAM cycles

(see Figure 23−Figure 28)

SYNCHRONOUS DRAM TIMING (CONTINUED)

SYNCHRONOUS DRAM TIMING (CONTINUED)

SYNCHRONOUS DRAM TIMING (CONTINUED)

HOLD/HOLDA TIMING timing requirements for the HOLD/HOLDA cycles

(see Figure 29)

switching characteristics over recommended operating conditions for the HOLD/HOLDA cycles

(see Figure 29)

RESET TIMING timing requirements for reset

(see Figure 30)

switching characteristics over recommended operating conditions during reset

(see Figure 30)

RESET TIMING (CONTINUED)

EXTERNAL INTERRUPT TIMING timing requirements for interrupt response cycles

(see Figure 31)

switching characteristics over recommended operating conditions during interrupt response cycles

(see Figure 31)

EXPANSION BUS SYNCHRONOUS FIFO TIMING timing requirements for synchronous FIFO interface (see Figure 32, Figure 33, and Figure 34)

switching characteristics over recommended operating conditions for synchronous FIFO interface (see Figure 32, Figure 33, and Figure 34)

EXPANSION BUS SYNCHRONOUS FIFO TIMING (CONTINUED)

EXPANSION BUS ASYNCHRONOUS PERIPHERAL TIMING timing requirements for asynchronous peripheral cycles

(see Figure 35−Figure 38)

switching characteristics over recommended operating conditions for asynchronous peripheral cycles

(see Figure 35−Figure 38)

EXPANSION BUS ASYNCHRONOUS PERIPHERAL TIMING (CONTINUED)

EXPANSION BUS ASYNCHRONOUS PERIPHERAL TIMING (CONTINUED)