SST 39VF160

SST 39VF160
16 Mbit (x16) Multi-Purpose Flash
SST39LF160 / SST39VF160
Data Sheet
SST39LF/VF1603.0 & 2.7V 16Mb (x16) MPF memories
FEATURES:
• Organized as 1M x16
• Single Voltage Read and Write Operations
– 3.0-3.6V for SST39LF160
– 2.7-3.6V for SST39VF160
• Superior Reliability
– Endurance: 100,000 Cycles (typical)
– Greater than 100 years Data Retention
• Low Power Consumption
(typical values at 14 MHz)
– Active Current: 12 mA (typical)
– Standby Current: 4 µA (typical)
– Auto Low Power Mode: 4 µA (typical)
• Sector-Erase Capability
– Uniform 2 KWord sectors
• Fast Read Access Time
– 55 ns for SST39LF160
– 70 and 90 ns for SST39VF160
• Latched Address and Data
• Fast Erase and Word-Program
– Sector-Erase Time: 18 ms (typical)
– Block-Erase Time: 18 ms (typical)
– Chip-Erase Time: 70 ms (typical)
– Word-Program Time: 14 µs (typical)
– Chip Rewrite Time: 15 seconds (typical) for
SST39LF/VF160
• Automatic Write Timing
– Internal VPP Generation
• End-of-Write Detection
– Toggle Bit
– Data# Polling
• CMOS I/O Compatibility
• JEDEC Standard
– Flash EEPROM Pinouts and command sets
• Packages Available
– 48-lead TSOP (12mm x 20mm)
– 48-ball TFBGA (8mm x 10mm)
PRODUCT DESCRIPTION
The SST39LF/VF160 devices are 1M x16 CMOS MultiPurpose Flash (MPF) manufactured with SST’s proprietary, high performance CMOS SuperFlash technology.
The split-gate cell design and thick-oxide tunneling injector attain better reliability and manufacturability compared
with alternate approaches. The SST39LF160 write (Program or Erase) with a 3.0-3.6V power supply. The
SST39VF160 write (Program or Erase) with a 2.7-3.6V
power supply. These devices conform to JEDEC standard
pinouts for x16 memories.
Featuring high performance Word-Program, the
SST39LF/VF160 devices provide a typical Word-Program
time of 14 µsec. These devices use Toggle Bit or Data#
Polling to indicate the completion of Program operation.
To protect against inadvertent write, they have on-chip
hardware and Software Data Protection schemes.
Designed, manufactured, and tested for a wide spectrum
of applications, these devices are offered with a guaranteed typical endurance of 10,000 cycles. Data retention is
rated at greater than 100 years.
The SST39LF/VF160 devices are suited for applications
that require convenient and economical updating of program, configuration, or data memory. For all system applications, they significantly improve performance and
reliability, while lowering power consumption. They inherently use less energy during Erase and Program than
alternative flash technologies. The total energy consumed
is a function of the applied voltage, current, and time of
©2003 Silicon Storage Technology, Inc.
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application. Since for any given voltage range, the SuperFlash technology uses less current to program and has a
shorter erase time, the total energy consumed during any
Erase or Program operation is less than alternative flash
technologies. These devices also improve flexibility while
lowering the cost for program, data, and configuration
storage applications.
The SuperFlash technology provides fixed Erase and Program times, independent of the number of Erase/Program
cycles that have occurred. Therefore the system software
or hardware does not have to be modified or de-rated as
is necessary with alternative flash technologies, whose
Erase and Program times increase with accumulated
Erase/Program cycles.
To meet high density, surface mount requirements, the
SST39LF/VF160 are offered in a 48-lead TSOP and a
48-ball TFBGA package. See Figures 1 and 2 for pin
assignments.
Device Operation
Commands are used to initiate the memory operation functions of the device. Commands are written to the device
using standard microprocessor write sequences. A command is written by asserting WE# low while keeping CE#
low. The address bus is latched on the falling edge of WE#
or CE#, whichever occurs last. The data bus is latched on
the rising edge of WE# or CE#, whichever occurs first.
The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc.
MPF is a trademark of Silicon Storage Technology, Inc.
These specifications are subject to change without notice.
16 Mbit Multi-Purpose Flash
SST39LF160 / SST39VF160
Data Sheet
is based on uniform block size of 32 KWord. The SectorErase operation is initiated by executing a six-byte command sequence with Sector-Erase command (30H) and
sector address (SA) in the last bus cycle. The Block-Erase
operation is initiated by executing a six-byte command
sequence with Block-Erase command (50H) and block
address (BA) in the last bus cycle. The sector or block
address is latched on the falling edge of the sixth WE#
pulse, while the command (30H or 50H) is latched on the
rising edge of the sixth WE# pulse. The internal Erase
operation begins after the sixth WE# pulse. The End-ofErase operation can be determined using either Data#
Polling or Toggle Bit methods. See Figures 9 and 10 for timing waveforms. Any commands issued during the Sectoror Block-Erase operation are ignored.
The SST39LF/VF160 also have the Auto Low Power
mode which puts the device in a near standby mode after
data has been accessed with a valid Read operation. This
reduces the IDD active read current from typically 15 mA to
typically 4 µA. The Auto Low Power mode reduces the typical IDD active read current to the range of 1 mA/MHz of
read cycle time. The device exits the Auto Low Power
mode with any address transition or control signal transition
used to initiate another Read cycle, with no access time
penalty. Note that the device does not enter Auto Low
Power mode after power-up with CE# held steadily low until
the first address transition or CE# is driven high.
Read
The Read operation of the SST39LF/VF160 is controlled by
CE# and OE#, both have to be low for the system to obtain
data from the outputs. CE# is used for device selection.
When CE# is high, the chip is deselected and only standby
power is consumed. OE# is the output control and is used
to gate data from the output pins. The data bus is in high
impedance state when either CE# or OE# is high. Refer to
the Read cycle timing diagram for further details (Figure 3).
Chip-Erase Operation
The SST39LF/VF160 provide a Chip-Erase operation,
which allows the user to erase the entire memory array to
the “1” state. This is useful when the entire device must be
quickly erased.
The Chip-Erase operation is initiated by executing a sixbyte command sequence with Chip-Erase command (10H)
at address 5555H in the last byte sequence. The Erase
operation begins with the rising edge of the sixth WE# or
CE#, whichever occurs first. During the Erase operation,
the only valid read is Toggle Bit or Data# Polling. See Table
4 for the command sequence, Figure 8 for timing diagram,
and Figure 19 for the flowchart. Any commands issued during the Chip-Erase operation are ignored.
Word-Program Operation
The SST39LF/VF160 are programmed on a word-by-word
basis. Before programming, the sector where the word
exists must be fully erased. The Program operation is
accomplished in three steps. The first step is the three-byte
load sequence for Software Data Protection. The second
step is to load word address and word data. During the
Word-Program operation, the addresses are latched on the
falling edge of either CE# or WE#, whichever occurs last.
The data is latched on the rising edge of either CE# or
WE#, whichever occurs first. The third step is the internal
Program operation which is initiated after the rising edge of
the fourth WE# or CE#, whichever occurs first. The Program operation, once initiated, will be completed within 20
µs. See Figures 4 and 5 for WE# and CE# controlled Program operation timing diagrams and Figure 16 for flowcharts. During the Program operation, the only valid reads
are Data# Polling and Toggle Bit. During the internal Program operation, the host is free to perform additional tasks.
Any commands issued during the internal Program operation are ignored.
Write Operation Status Detection
The SST39LF/VF160 provide two software means to
detect the completion of a Write (Program or Erase) cycle,
in order to optimize the system Write cycle time. The software detection includes two status bits: Data# Polling
(DQ7) and Toggle Bit (DQ6). The End-of-Write detection
mode is enabled after the rising edge of WE#, which initiates the internal Program or Erase operation.
The actual completion of the nonvolatile write is asynchronous with the system; therefore, either a Data# Polling or
Toggle Bit read may be simultaneous with the completion
of the write cycle. If this occurs, the system may possibly
get an erroneous result, i.e., valid data may appear to conflict with either DQ7 or DQ6. In order to prevent spurious
rejection, if an erroneous result occurs, the software routine
should include a loop to read the accessed location an
additional two (2) times. If both reads are valid, then the
device has completed the Write cycle, otherwise the rejection is valid.
Sector-/Block-Erase Operation
The Sector- (or Block-) Erase operation allows the system
to erase the device on a sector-by-sector (or block-byblock) basis. The SST39LF/VF160 offer both Sector-Erase
and Block-Erase modes. The sector architecture is based
on uniform sector size of 2 KWord. The Block-Erase mode
©2003 Silicon Storage Technology, Inc.
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16 Mbit Multi-Purpose Flash
SST39LF160 / SST39VF160
Data Sheet
Data# Polling (DQ7)
Software Data Protection (SDP)
When the SST39LF/VF160 are in the internal Program
operation, any attempt to read DQ7 will produce the complement of the true data. Once the Program operation is
completed, DQ7 will produce true data. Note that even
though DQ7 may have valid data immediately following the
completion of an internal Write operation, the remaining
data outputs may still be invalid: valid data on the entire
data bus will appear in subsequent successive Read
cycles after an interval of 1 µs. During internal Erase operation, any attempt to read DQ7 will produce a ‘0’. Once the
internal Erase operation is completed, DQ7 will produce a
‘1’. The Data# Polling is valid after the rising edge of fourth
WE# (or CE#) pulse for Program operation. For Sector-,
Block- or Chip-Erase, the Data# Polling is valid after the rising edge of sixth WE# (or CE#) pulse. See Figure 6 for
Data# Polling timing diagram and Figure 17 for a flowchart.
The SST39LF/VF160 provide the JEDEC approved Software Data Protection scheme for all data alteration operations, i.e., Program and Erase. Any Program operation
requires the inclusion of the three-byte sequence. The
three-byte load sequence is used to initiate the Program
operation, providing optimal protection from inadvertent
Write operations, e.g., during the system power-up or
power-down. Any Erase operation requires the inclusion of
six-byte sequence. These devices are shipped with the
Software Data Protection permanently enabled. See Table
4 for the specific software command codes. During SDP
command sequence, invalid commands will abort the
device to Read mode within TRC. The contents of DQ15DQ8 can be VIL or VIH, but no other value, during any SDP
command sequence.
Common Flash Memory Interface (CFI)
Toggle Bit (DQ6)
During the internal Program or Erase operation, any consecutive attempts to read DQ6 will produce alternating 1s
and 0s, i.e., toggling between 1 and 0. When the internal
Program or Erase operation is completed, the DQ6 bit will
stop toggling. The Toggle Bit is valid after the rising edge of
fourth WE# (or CE#) pulse for Program operation. For Sector-, Block- or Chip-Erase, the Toggle Bit is valid after the
rising edge of sixth WE# (or CE#) pulse. See Figure 7 for
Toggle Bit timing diagram and Figure 17 for a flowchart.
The SST39LF/VF160 also contain the CFI information to
describe the characteristics of the device. In order to enter
the CFI Query mode, the system must load the three-byte
sequence, similar to the Software ID Entry command. The
last byte cycle of this command loads 98H (CFI Query
command) to address 5555H. Once the device enters the
CFI Query mode, the system can read CFI data at the
addresses given in Tables 5 through 7. The system must
write the CFI Exit command to return to Read mode from
the CFI Query mode.
Data Protection
Product Identification
The SST39LF/VF160 provide both hardware and software
features to protect nonvolatile data from inadvertent writes.
The Product Identification mode identifies the devices as
the SST39LF/VF160 and manufacturer as SST. This mode
may be accessed by software operations. Users may use
the Software Product Identification operation to identify the
part (i.e., using the device ID) when using multiple manufacturers in the same socket. For details, see Table 4 for
software operation, Figure 11 for the Software ID Entry and
Read timing diagram, and Figure 18 for the Software ID
Entry command sequence flowchart.
Hardware Data Protection
Noise/Glitch Protection: A WE# or CE# pulse of less than 5
ns will not initiate a write cycle.
VDD Power Up/Down Detection: The Write operation is
inhibited when VDD is less than 1.5V.
Write Inhibit Mode: Forcing OE# low, CE# high, or WE#
high will inhibit the Write operation. This prevents inadvertent writes during power-up or power-down.
TABLE 1: PRODUCT IDENTIFICATION
Manufacturer’s ID
Address
Data
0000H
00BFH
0001H
2782H
Device ID
SST39LF/VF160
T1.2 399
©2003 Silicon Storage Technology, Inc.
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16 Mbit Multi-Purpose Flash
SST39LF160 / SST39VF160
Data Sheet
Product Identification Mode Exit/
CFI Mode Exit
Read mode after any inadvertent transient condition that
apparently causes the device to behave abnormally, e.g.,
not read correctly. Please note that the Software ID Exit/
CFI Exit command is ignored during an internal Program or
Erase operation. See Table 4 for software command
codes, Figure 13 for timing waveform, and Figure 18 for a
flowchart.
In order to return to the standard Read mode, the Software
Product Identification mode must be exited. Exit is accomplished by issuing the Software ID Exit command
sequence, which returns the device to the Read mode.
This command may also be used to reset the device to the
FUNCTIONAL BLOCK DIAGRAM
X-Decoder
Memory Address
SuperFlash
Memory
Address Buffer & Latches
Y-Decoder
CE#
I/O Buffers and Data Latches
Control Logic
OE#
WE#
DQ15 - DQ0
399 ILL B1.1
A15
A14
A13
A12
A11
A10
A9
A8
A19
NC
WE#
NC
NC
NC
NC
A18
A17
A7
A6
A5
A4
A3
A2
A1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
Standard Pinout
Top View
Die Up
SST39LF160/SST39VF160
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
A16
NC
VSS
DQ15
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
VDD
DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
OE#
VSS
CE#
A0
399 ILL F01.2
FIGURE 1: PIN ASSIGNMENTS FOR 48-LEAD TSOP
©2003 Silicon Storage Technology, Inc.
S71145-04-000 11/03 399
4
16 Mbit Multi-Purpose Flash
SST39LF160 / SST39VF160
Data Sheet
TOP VIEW (balls facing down)
SST39LF/VF160
6
5
4
NC
DQ15 VSS
A13
A12
A14
A15
A16
A9
A8
A10
A11
DQ7 DQ14 DQ13 DQ6
WE#
NC
NC
A19
DQ5 DQ12 VDD DQ4
NC
NC
A18
NC
DQ2 DQ10 DQ11 DQ3
A7
A17
A6
A5
DQ0 DQ8
A3
A4
A2
A1
3
2
DQ9 DQ1
1
A0
CE#
OE# VSS
A B C D E F G H
399 ILL F02a.0
FIGURE 2: PIN ASSIGNMENTS FOR 48-BALL TFBGA
TABLE 2: PIN DESCRIPTION
Symbol
Pin Name
Functions
A19-A0
Address Inputs
To provide memory addresses. During Sector-Erase A19-A11 address lines will select the
sector. During Block-Erase, A19-A15 address line will select the block.
DQ15-DQ0
Data Input/output
To output data during Read cycles and receive input data during Write cycles.
Data is internally latched during a Write cycle.
The outputs are in tri-state when OE# or CE# is high.
CE#
Chip Enable
To activate the device when CE# is low
OE#
Output Enable
To gate the data output buffers
WE#
Write Enable
To control the Write operations
VDD
Power Supply
To provide power supply voltage:
VSS
Ground
NC
No Connection
3.0-3.6V for SST39LF160
2.7-3.6V for SST39VF160
Unconnected pins
T2.3 399
©2003 Silicon Storage Technology, Inc.
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16 Mbit Multi-Purpose Flash
SST39LF160 / SST39VF160
Data Sheet
TABLE 3: OPERATION MODES SELECTION
Mode
CE#
OE#
WE#
DQ
Address
Read
VIL
VIL
VIH
DOUT
AIN
Program
VIL
VIH
VIL
DIN
AIN
Erase
VIL
VIH
VIL
X1
Sector or Block address,
XXH for Chip-Erase
Standby
VIH
X
X
High Z
X
X
VIL
X
High Z/ DOUT
X
X
X
VIH
High Z/ DOUT
X
VIL
VIL
VIH
Write Inhibit
Product Identification
Software Mode
See Table 4
T3.4 399
1. X can be VIL or VIH, but no other value
TABLE 4: SOFTWARE COMMAND SEQUENCE
Command
Sequence
1st Bus
Write Cycle
2nd Bus
Write Cycle
3rd Bus
Write Cycle
4th Bus
Write Cycle
Addr1
Data2
Addr1
Data2
Addr1
Data2
Addr1
Data2
Word-Program
5555H
AAH
2AAAH
55H
5555H
A0H
WA3
Data
Sector-Erase
5555H
AAH
2AAAH
55H
5555H
80H
5555H
Block-Erase
5555H
AAH
2AAAH
55H
5555H
80H
Chip-Erase
5555H
AAH
2AAAH
55H
5555H
80H
Software ID Entry5,6 5555H
AAH
2AAAH
55H
5555H
90H
CFI Query Entry5
5555H
AAH
2AAAH
55H
5555H
98H
Software ID Exit7/
CFI Exit
XXH
F0H
Software ID Exit7/
CFI Exit
5555H
AAH
2AAAH
55H
5555H
F0H
5th Bus
Write Cycle
6th Bus
Write Cycle
Addr1
Data2
Addr1
Data2
AAH
2AAAH
55H
SAX4
30H
5555H
AAH
2AAAH
55H
BAX4
50H
5555H
AAH
2AAAH
55H
5555H
10H
T4.5 399
1.
2.
3.
4.
Address format A14-A0 (Hex), Addresses A19-A15 can be VIL or VIH, but no other value, for Command sequence for SST39LF/VF160
DQ15 - DQ8 can be VIL or VIH, but no other value, for Command sequence
WA = Program word address
SAX for Sector-Erase; uses A19-A11 address lines
BAX, for Block-Erase; uses A19-A15 address lines
5. The device does not remain in Software Product ID mode if powered down.
6. With A19-A1 = 0; SST Manufacturer’s ID = 00BFH, is read with A0 = 0,
SST39LF/VF160 Device ID = 2782H, is read with A0 = 1
7. Both Software ID Exit operations are equivalent
©2003 Silicon Storage Technology, Inc.
S71145-04-000 11/03 399
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16 Mbit Multi-Purpose Flash
SST39LF160 / SST39VF160
Data Sheet
TABLE 5: CFI QUERY IDENTIFICATION STRING1 FOR SST39LF/VF160
Address
10H
11H
12H
13H
14H
15H
16H
17H
18H
19H
1AH
Data
0051H
0052H
0059H
0001H
0007H
0000H
0000H
0000H
0000H
0000H
0000H
Data
Query Unique ASCII string “QRY”
Primary OEM command set
Address for Primary Extended Table
Alternate OEM command set (00H = none exists)
Address for Alternate OEM extended Table (00H = none exits)
T5.0 399
1. Refer to CFI publication 100 for more details.
TABLE 6: SYSTEM INTERFACE INFORMATION
Address
Data
1BH
0027H1
FOR
SST39LF/VF160
Data
VDD Min (Program/Erase)
0030H1
DQ7-DQ4: Volts, DQ3-DQ0: 100 millivolts
1CH
0036H
VDD Max (Program/Erase)
DQ7-DQ4: Volts, DQ3-DQ0: 100 millivolts
1DH
0000H
VPP min (00H = no VPP pin)
1EH
0000H
VPP max (00H = no VPP pin)
1FH
0004H
Typical time out for Word-Program 2N µs (24 = 16 µs)
20H
0000H
Typical time out for min size buffer program 2N µs (00H = not supported)
21H
0004H
Typical time out for individual Sector/Block-Erase 2N ms (24 = 16 ms)
22H
0006H
Typical time out for Chip-Erase 2N ms (26 = 64 ms)
23H
0001H
Maximum time out for Word-Program 2N times typical (21 x 24 = 32 µs)
24H
0000H
Maximum time out for buffer program 2N times typical
25H
0001H
Maximum time out for individual Sector/Block-Erase 2N times typical (21 x 24 = 32 ms)
26H
0001H
Maximum time out for Chip-Erase 2N times typical (21 x 26 = 128 ms)
T6.2 399
1. 0030H for SST39LF160 and 0027H for SST39VF160
TABLE 7: DEVICE GEOMETRY INFORMATION
Address
27H
28H
29H
2AH
2BH
2CH
2DH
2EH
2FH
30H
31H
32H
33H
34H
Data
0015H
0001H
0000H
0000H
0000H
0002H
00FFH
0001H
0010H
0000H
003FH
0000H
0000H
0001H
FOR
SST39LF/VF160
Data
Device size = 2N Bytes (15H = 21; 221 = 2 MByte)
Flash Device Interface description; 0001H = x16-only asynchronous interface
Maximum number of bytes in multi-byte write = 2N (00H = not supported)
Number of Erase Sector/Block sizes supported by device
Sector Information (y + 1 = Number of sectors; z x 256B = sector size)
y = 155 + 1 = 512 sectors (01FFH = 511)
z = 16 x 256 Bytes = 4 KBytes/sector (0010H = 16)
Block Information (y + 1 = Number of blocks; z x 256B = block size)
y = 31 + 1 = 32 blocks (001FH = 31)
z = 256 x 256 Bytes = 64 KBytes/block (0100H = 256)
T7.3 399
©2003 Silicon Storage Technology, Inc.
S71145-04-000 11/03 399
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16 Mbit Multi-Purpose Flash
SST39LF160 / SST39VF160
Data Sheet
Absolute Maximum Stress Ratings (Applied conditions greater than those listed under “Absolute Maximum
Stress Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation
of the device at these conditions or conditions greater than those defined in the operational sections of this data
sheet is not implied. Exposure to absolute maximum stress rating conditions may affect device reliability.)
Temperature Under Bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55°C to +125°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65°C to +150°C
D. C. Voltage on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to VDD+0.5V
Transient Voltage (<20 ns) on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -2.0V to VDD+2.0V
Voltage on A9 Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 13.2V
Package Power Dissipation Capability (Ta = 25°C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0W
Surface Mount Lead Soldering Temperature (3 Seconds) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240°C
Output Short Circuit Current1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
1. Outputs shorted for no more than one second. No more than one output shorted at a time.
OPERATING RANGE: SST39LF160
Range
Commercial
Ambient Temp
VDD
0°C to +70°C
3.0-3.6V
OPERATING RANGE: SST39VF160
Range
Ambient Temp
Commercial
Industrial
AC CONDITIONS
OF
VDD
0°C to +70°C
2.7-3.6V
-40°C to +85°C
2.7-3.6V
TEST
Input Rise/Fall Time . . . . . . . . . . . . . . 5 ns
Output Load . . . . . . . . . . . . . . . . . . . . CL = 30 pF for SST39LF160
Output Load . . . . . . . . . . . . . . . . . . . . . CL = 100 pF for SST39VF160
See Figures 14 and 15
©2003 Silicon Storage Technology, Inc.
S71145-04-000 11/03 399
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16 Mbit Multi-Purpose Flash
SST39LF160 / SST39VF160
Data Sheet
TABLE 8: DC OPERATING CHARACTERISTICS
VDD = 3.0-3.6V FOR SST39LF160 AND 2.7-3.6V FOR SST39VF1601
Limits
Symbol
Parameter
Min
IDD
Power Supply Current
Max
Units
Test Conditions
Address input=VILT/VIHT, at f=1/TRC Min,
VDD=VDD Max
Read2
20
mA
CE#=VIL, OE#=WE#=VIH, all I/Os open
Program and Erase
30
mA
CE#=WE#=VIL, OE#=VIH
ISB
Standby VDD Current
20
µA
CE#=VIHC, VDD=VDD Max
IALP
Auto Low Power Current
20
µA
CE#=VILC, VDD=VDD Max,
all inputs = VSS or VDD, WE#=VIHC
ILI
Input Leakage Current
1
µA
VIN=GND to VDD, VDD=VDD Max
ILO
Output Leakage Current
10
µA
VOUT=GND to VDD, VDD=VDD Max
VIL
Input Low Voltage
0.8
V
VDD=VDD Min
VILC
Input Low Voltage (CMOS)
0.3
V
VDD=VDD Max
VIH
Input High Voltage
0.7 VDD
V
VDD=VDD Max
VIHC
Input High Voltage (CMOS)
VDD-0.3
V
VDD=VDD Max
VOL
Output Low Voltage
V
IOL=100 µA, VDD=VDD Min
VOH
Output High Voltage
V
IOH = -100 µA, VDD=VDD Min
0.2
VDD-0.2
T8.8 399
1. Typical conditions for the Active Current shown on the front data sheet page are average values at 25°C
(room temperature), and VDD = 3V for VF devices or VDD = 5V for SF devices. Not 100% tested.
2. Values are for 70 ns conditions. See the Multi-Purpose Flash Power Rating application note for further information.
TABLE 9: RECOMMENDED SYSTEM POWER-UP TIMINGS
Symbol
Parameter
Minimum
Units
TPU-READ1
Power-up to Read Operation
100
µs
Power-up to Program/Erase Operation
100
µs
TPU-WRITE
1
T9.0 399
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
TABLE 10: CAPACITANCE
Parameter
CI/O
1
CIN1
(Ta = 25°C, f=1 Mhz, other pins open)
Description
Test Condition
Maximum
I/O Pin Capacitance
VI/O = 0V
12 pF
Input Capacitance
VIN = 0V
6 pF
T10.0 399
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
TABLE 11: RELIABILITY CHARACTERISTICS
Symbol
NEND
TDR1
ILTH
1
1,2
Parameter
Minimum Specification
Units
Test Method
Endurance
10,000
Cycles
JEDEC Standard A117
100
Years
JEDEC Standard A103
100 + IDD
mA
JEDEC Standard 78
Data Retention
Latch Up
T11.3 399
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
2. NEND endurance rating is qualified as a 10,000 cycle minimum for the whole device. A sector- or block-level rating would result in a
higher minimum specification.
©2003 Silicon Storage Technology, Inc.
S71145-04-000 11/03 399
9
16 Mbit Multi-Purpose Flash
SST39LF160 / SST39VF160
Data Sheet
AC CHARACTERISTICS
TABLE 12: READ CYCLE TIMING PARAMETERS VDD = 3.0-3.6V FOR SST39LF160 AND 2.7-3.6V FOR SST39VF160
SST39LF160-55
Max
SST39VF160-70
Min
Max
SST39VF160-90
Symbol
Parameter
Min
TRC
Read Cycle Time
55
TCE
Chip Enable Access Time
TAA
Address Access Time
55
70
90
ns
TOE
Output Enable Access Time
30
35
45
ns
TCLZ1
CE# Low to Active Output
0
0
0
ns
TOLZ1
OE# Low to Active Output
0
0
0
ns
TCHZ1
CE# High to High-Z Output
15
20
30
ns
TOHZ1
OE# High to High-Z Output
15
20
30
ns
TOH1
Output Hold from Address Change
70
Max
Units
90
ns
90
55
0
Min
ns
70
0
0
ns
T12.2 399
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
TABLE 13: PROGRAM/ERASE CYCLE TIMING PARAMETERS
Symbol
Parameter
Min
Max
20
Units
TBP
Word-Program Time
TAS
Address Setup Time
0
ns
µs
TAH
Address Hold Time
30
ns
TCS
WE# and CE# Setup Time
0
ns
TCH
WE# and CE# Hold Time
0
ns
TOES
OE# High Setup Time
0
ns
TOEH
OE# High Hold Time
10
ns
TCP
CE# Pulse Width
40
ns
TWP
WE# Pulse Width
40
ns
TWPH1
WE# Pulse Width High
30
ns
1
CE# Pulse Width High
30
ns
TDS
Data Setup Time
30
ns
TDH1
Data Hold Time
0
TIDA1
Software ID Access and Exit Time
150
ns
TCPH
ns
TSE
Sector-Erase
25
ms
TBE
Block-Erase
25
ms
TSCE
Chip-Erase
100
ms
T13.0 399
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
©2003 Silicon Storage Technology, Inc.
S71145-04-000 11/03 399
10
16 Mbit Multi-Purpose Flash
SST39LF160 / SST39VF160
Data Sheet
TAA
TRC
ADDRESS A19-0
TCE
CE#
TOE
OE#
TOHZ
TOLZ
VIH
WE#
DQ15-0
TCHZ
TOH
TCLZ
HIGH-Z
HIGH-Z
DATA VALID
DATA VALID
399 ILL F03.2
FIGURE 3: READ CYCLE TIMING DIAGRAM
INTERNAL PROGRAM OPERATION STARTS
TBP
5555
TAH
ADDRESS A19-0
2AAA
5555
ADDR
TDH
TWP
WE#
TAS
TDS
TWPH
OE#
TCH
CE#
TCS
DQ15-0
Note:
XXAA
XX55
XXA0
SW0
SW1
SW2
DATA
WORD
(ADDR/DATA)
399 ILL F04.3
X can be VIL or VIH, but no other value
FIGURE 4: WE# CONTROLLED PROGRAM CYCLE TIMING DIAGRAM
©2003 Silicon Storage Technology, Inc.
S71145-04-000 11/03 399
11
16 Mbit Multi-Purpose Flash
SST39LF160 / SST39VF160
Data Sheet
INTERNAL PROGRAM OPERATION STARTS
TBP
5555
TAH
ADDRESS A19-0
2AAA
5555
ADDR
TDH
TCP
CE#
TAS
TDS
TCPH
OE#
TCH
WE#
TCS
DQ15-0
Note:
XXAA
XX55
XXA0
DATA
SW0
SW1
SW2
WORD
(ADDR/DATA)
399 ILL F05.3
X can be VIL or VIH, but no other value
FIGURE 5: CE# CONTROLLED PROGRAM CYCLE TIMING DIAGRAM
ADDRESS A19-0
TCE
CE#
TOES
TOEH
OE#
TOE
WE#
DQ7
DATA
DATA#
DATA#
DATA
399 ILL F06.2
FIGURE 6: DATA# POLLING TIMING DIAGRAM
©2003 Silicon Storage Technology, Inc.
S71145-04-000 11/03 399
12
16 Mbit Multi-Purpose Flash
SST39LF160 / SST39VF160
Data Sheet
ADDRESS A19-0
TCE
CE#
TOES
TOE
TOEH
OE#
WE#
DQ6
TWO READ CYCLES
WITH SAME OUTPUTS
399 ILL F07.2
FIGURE 7: TOGGLE BIT TIMING DIAGRAM
TSCE
SIX-BYTE CODE FOR CHIP-ERASE
5555
ADDRESS A19-0
2AAA
5555
5555
2AAA
5555
CE#
OE#
TWP
WE#
DQ15-0
XXAA
XX55
XX80
XXAA
XX55
XX10
SW0
SW1
SW2
SW3
SW4
SW5
399 ILL F08.3
Note:
This device also supports CE# controlled Chip-Erase operation. The WE# and CE# signals are
interchageable as long as minimum timings are met. (See Table 13)
X can be VIL or VIH, but no other value
FIGURE 8: WE# CONTROLLED CHIP-ERASE TIMING DIAGRAM
©2003 Silicon Storage Technology, Inc.
S71145-04-000 11/03 399
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16 Mbit Multi-Purpose Flash
SST39LF160 / SST39VF160
Data Sheet
TBE
SIX-BYTE CODE FOR BLOCK-ERASE
5555
ADDRESS A19-0
2AAA
5555
5555
2AAA
BAX
CE#
OE#
TWP
WE#
DQ15-0
XXAA
XX55
XX80
XXAA
XX55
XX50
SW0
SW1
SW2
SW3
SW4
SW5
399 ILL F17.3
Note: This device also supports CE# controlled Block-Erase operation. The WE# and CE# signals are
interchageable as long as minimum timings are met. (See Table 13)
BAX = Block Address
X can be VIL or VIH, but no other value
FIGURE 9: WE# CONTROLLED BLOCK-ERASE TIMING DIAGRAM
TSE
SIX-BYTE CODE FOR SECTOR-ERASE
5555
ADDRESS A19-0
2AAA
5555
5555
2AAA
SAX
CE#
OE#
TWP
WE#
DQ15-0
XXAA
XX55
XX80
XXAA
XX55
XX30
SW0
SW1
SW2
SW3
SW4
SW5
399 ILL F18.3
Note: This device also supports CE# controlled Sector-Erase operation. The WE# and CE# signals are
interchageable as long as minimum timings are met. (See Table 13)
SAX = Sector Address
X can be VIL or VIH, but no other value
FIGURE 10: WE# CONTROLLED SECTOR-ERASE TIMING DIAGRAM
©2003 Silicon Storage Technology, Inc.
S71145-04-000 11/03 399
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16 Mbit Multi-Purpose Flash
SST39LF160 / SST39VF160
Data Sheet
THREE-BYTE SEQUENCE FOR
SOFTWARE ID ENTRY
5555
ADDRESS A14-0
2AAA
5555
0000
0001
CE#
OE#
TIDA
TWP
WE#
TWPH
DQ15-0
XXAA
XX55
SW0
TAA
00BF
XX90
SW1
Device ID
399 ILL F09.4
SW2
Device ID = 2782H for SST39LF/VF160
Note: X can be VIL or VIH, but no other value
FIGURE 11: SOFTWARE ID ENTRY
AND
READ
THREE-BYTE SEQUENCE FOR
CFI QUERY ENTRY
5555
ADDRESS A14-0
2AAA
5555
CE#
OE#
TIDA
TWP
WE#
TWPH
DQ15-0
TAA
XXAA
XX55
XX98
SW0
SW1
SW2
399 ILL F20.1
Note:
FIGURE 12: CFI QUERY
X can be VIL or VIH, but no other value
AND
READ
©2003 Silicon Storage Technology, Inc.
S71145-04-000 11/03 399
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16 Mbit Multi-Purpose Flash
SST39LF160 / SST39VF160
Data Sheet
THREE-BYTE SEQUENCE FOR
SOFTWARE ID EXIT AND RESET
5555
ADDRESS A14-0
DQ15-0
XXAA
2AAA
5555
XX55
XXF0
TIDA
CE#
OE#
TWP
WE#
T WHP
SW0
SW1
SW2
399 ILL F10.1
Note:
X can be VIL or VIH, but no other value
FIGURE 13: SOFTWARE ID EXIT/CFI EXIT
©2003 Silicon Storage Technology, Inc.
S71145-04-000 11/03 399
16
16 Mbit Multi-Purpose Flash
SST39LF160 / SST39VF160
Data Sheet
VIHT
INPUT
VIT
REFERENCE POINTS
VOT
OUTPUT
VILT
399 ILL F11.1
AC test inputs are driven at VIHT (0.9 VDD) for a logic “1” and VILT (0.1 VDD) for a logic “0”. Measurement reference points
for inputs and outputs are VIT (0.5 VDD) and VOT (0.5 VDD). Input rise and fall times (10% ↔ 90%) are <5 ns.
Note: VIT - VINPUT Test
VOT - VOUTPUT Test
VIHT - VINPUT HIGH Test
VILT - VINPUT LOW Test
FIGURE 14: AC INPUT/OUTPUT REFERENCE WAVEFORMS
TO TESTER
TO DUT
CL
399 ILL F12.1
FIGURE 15: A TEST LOAD EXAMPLE
©2003 Silicon Storage Technology, Inc.
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17
16 Mbit Multi-Purpose Flash
SST39LF160 / SST39VF160
Data Sheet
Start
Load data: XXAAH
Address: 5555H
Load data: XX55H
Address: 2AAAH
Load data: XXA0H
Address: 5555H
Load Word
Address/Word
Data
Wait for end of
Program (TBP,
Data# Polling
bit, or Toggle bit
operation)
Program
Completed
399 ILL F13.3
Note:
X can be VIL or VIH, but no other value
FIGURE 16: WORD-PROGRAM ALGORITHM
©2003 Silicon Storage Technology, Inc.
S71145-04-000 11/03 399
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16 Mbit Multi-Purpose Flash
SST39LF160 / SST39VF160
Data Sheet
Internal Timer
Toggle Bit
Data# Polling
Program/Erase
Initiated
Program/Erase
Initiated
Program/Erase
Initiated
Wait TBP,
TSCE, TSE
or TBE
Read word
Read DQ7
Read same
word
Program/Erase
Completed
No
Is DQ7 =
true data?
Yes
No
Does DQ6
match?
Program/Erase
Completed
Yes
Program/Erase
Completed
399 ILL F14.0
FIGURE 17: WAIT OPTIONS
©2003 Silicon Storage Technology, Inc.
S71145-04-000 11/03 399
19
16 Mbit Multi-Purpose Flash
SST39LF160 / SST39VF160
Data Sheet
CFI Query Entry
Command Sequence
Software Product ID Entry
Command Sequence
Software ID Exit/CFI Exit
Command Sequence
Load data: XXAAH
Address: 5555H
Load data: XXAAH
Address: 5555H
Load data: XXAAH
Address: 5555H
Load data: XXF0H
Address: XXH
Load data: XX55H
Address: 2AAAH
Load data: XX55H
Address: 2AAAH
Load data: XX55H
Address: 2AAAH
Wait TIDA
Load data: XX98H
Address: 5555H
Load data: XX90H
Address: 5555H
Load data: XXF0H
Address: 5555H
Return to normal
operation
Wait TIDA
Wait TIDA
Wait TIDA
Read CFI data
Read Software ID
Return to normal
operation
399 ILL F15.2
Note:
X can be VIL or VIH, but no other value
FIGURE 18: SOFTWARE PRODUCT ID/CFI COMMAND FLOWCHARTS
©2003 Silicon Storage Technology, Inc.
S71145-04-000 11/03 399
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16 Mbit Multi-Purpose Flash
SST39LF160 / SST39VF160
Data Sheet
Chip-Erase
Command Sequence
Sector-Erase
Command Sequence
Block-Erase
Command Sequence
Load data: XXAAH
Address: 5555H
Load data: XXAAH
Address: 5555H
Load data: XXAAH
Address: 5555H
Load data: XX55H
Address: 2AAAH
Load data: XX55H
Address: 2AAAH
Load data: XX55H
Address: 2AAAH
Load data: XX80H
Address: 5555H
Load data: XX80H
Address: 5555H
Load data: XX80H
Address: 5555H
Load data: XXAAH
Address: 5555H
Load data: XXAAH
Address: 5555H
Load data: XXAAH
Address: 5555H
Load data: XX55H
Address: 2AAAH
Load data: XX55H
Address: 2AAAH
Load data: XX55H
Address: 2AAAH
Load data: XX10H
Address: 5555H
Load data: XX30H
Address: SAX
Load data: XX50H
Address: BAX
Wait TSCE
Wait TSE
Wait TBE
Chip erased
to FFFFH
Sector erased
to FFFFH
Block erased
to FFFFH
Note:
X can be VIL or VIH, but no other value
399 ILL F16.2
FIGURE 19: ERASE COMMAND SEQUENCE
©2003 Silicon Storage Technology, Inc.
S71145-04-000 11/03 399
21
16 Mbit Multi-Purpose Flash
SST39LF160 / SST39VF160
Data Sheet
PRODUCT ORDERING INFORMATION
SST
39
XX
VF
XX
160
XXX
- 70
- XXX
-
4C
XX
EK
- XXX
E
X
Environmental Attribute
E = non-Pb
Package Modifier
K = 48 leads or balls
Package Type
E = TSOP (type 1, die up, 12mm x 20mm)
B = TFBGA (8mm x 10mm)
Temperature Range
C = Commercial = 0°C to +70°C
I = Industrial = -40°C to +85°C
Minimum Endurance
4 = 10,000 cycles
Read Access Speed
55 = 55 ns
70 = 70 ns
90 = 90 ns
Device Density
160 = 16 Mbit
Voltage
L = 3.0-3.6V
V = 2.7-3.6V
Product Series
39 = Multi-Purpose Flash
Valid combinations for SST39LF160
SST39LF160-55-4C-EK
SST39LF160-55-4C-EKE
SST39LF160-55-4C-BK
Valid combinations for SST39VF160
SST39VF160-70-4C-EK
SST39VF160-70-4C-EKE
SST39VF160-90-4C-EK
SST39VF160-90-4C-EKE
SST39VF160-70-4C-BK
SST39VF160-70-4I-EK
SST39VF160-70-4I-EKE
SST39VF160-90-4I-EK
SST39VF160-90-4I-EKE
SST39VF160-70-4I-BK
SST39VF160-90-4C-BK
SST39VF160-90-4I-BK
Note: Valid combinations are those products in mass production or will be in mass production. Consult your SST sales
representative to confirm availability of valid combinations and to determine availability of new combinations.
©2003 Silicon Storage Technology, Inc.
S71145-04-000 11/03 399
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16 Mbit Multi-Purpose Flash
SST39LF160 / SST39VF160
Data Sheet
PACKAGING DIAGRAMS
1.05
0.95
Pin # 1 Identifier
0.50
BSC
0.27
0.17
12.20
11.80
0.15
0.05
18.50
18.30
DETAIL
1.20
max.
0.70
0.50
20.20
19.80
0˚- 5˚
Note: 1. Complies with JEDEC publication 95 MO-142 DD dimensions,
although some dimensions may be more stringent.
2. All linear dimensions are in millimeters (max/min).
3. Coplanarity: 0.1 mm
4. Maximum allowable mold flash is 0.15 mm at the package ends, and 0.25 mm between leads.
48-LEAD THIN SMALL OUTLINE PACKAGE (TSOP) 12MM
SST PACKAGE CODE: EK
X
©2003 Silicon Storage Technology, Inc.
0.70
0.50
1mm
48-tsop-EK-8
20MM
S71145-04-000 11/03 399
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16 Mbit Multi-Purpose Flash
SST39LF160 / SST39VF160
Data Sheet
TOP VIEW
BOTTOM VIEW
10.00 ± 0.20
5.60
0.80
6
6
5
5
4.00
4
4
8.00 ± 0.20
3
3
2
2
1
1
0.80
0.30 ± 0.05
(48X)
H G F E D C B A
A B C D E F G H
A1 CORNER
A1 CORNER
SIDE VIEW
1.10 ± 0.10
1mm
0.08
SEATING PLANE
0.21 ± 0.05
Note:
1. Although many dimensions are similar to those of JEDEC Publication 95, MO-210, this specific package is not registered.
2. All linear dimensions are in millimeters.
3. Coplanarity: 0.08 mm
4. Ball opening size is 0.25 mm (± 0.05 mm)
48-tfbga-BK-8x10-300mic-14
48-BALL THIN-PROFILE, FINE-PITCH BALL GRID ARRAY (TFBGA) 8MM
SST PACKAGE CODE: BK
X
10MM
TABLE 14: REVISION HISTORY
Number
Description
02
•
03
•
•
•
04
•
•
•
Date
May 2002
2002 Data Book
Removed B3K package
Re-introduced BK package
Changes to Table 8 on page 9
– Added footnotes for MPF power usage and Typical conditions
– Clarified the Test Conditions for Power Supply Current and Read parameters
– Corrected IDD Program and Erase Current parameter from 25 mA to 30 mA
– Corrected IALP Test Condition for CE# from VIHC to VILC
2004 Data Book
Updated the BK package diagram
Added non-Pb MPNs and removed footnote (See page 22)
Mar 2003
Nov 2003
Silicon Storage Technology, Inc. • 1171 Sonora Court • Sunnyvale, CA 94086 • Telephone 408-735-9110 • Fax 408-735-9036
www.SuperFlash.com or www.sst.com
©2003 Silicon Storage Technology, Inc.
S71145-04-000 11/03 399
24
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