DEPARTMENT OF TECHNOLOGY Current Distribution in High RF Power Transistors Jihad Mohamad El-Rashid Youssef Tawk September 2007 Master’s Thesis in Electronics/Telecommunication Supervisor: Tony Fondén-Ericsson AB Examiner: Olof Bengtsson 1 2 Abstract To obtain the power levels required from high RF power transistors, the size of the chip has often to be made so large that inductance of electrical connections inside the package cannot be neglected. This may have the effect that various parts of the transistor chip are not connected exactly parallel, i.e. drain and gate voltages and currents densities will not be the same on different parts of the chip. This may result in degraded output power and efficiency. The same effect may occur when more than one chip are connected in parallel in a transistor package to obtain even higher output power. Often the connections to the transistor package are approximated as a number of electrical point connections (normally three: gate, drain, source); meaning that each of them can be described by a single electrical potential and current. In reality, they may be large enough that voltage and current distributions have to be considered. These distributions will be affected by different mountings of the transistor and other connected components. In this work, the LDMOS power transistor MRF6S21140HR3 was modeled using the segmentation method in high frequency signal simulation HFSS which is a 3D Full-Wave Electromagnetic Field Simulation, and utilized the advanced design system ADS to find a parameterized lumped model. Both the electromagnetic and lumped models showed consistent results. Non-ideal parallel connection of sub-transistors on chip is very important, but further studies are needed for definite conclusion. It was verified through modeling that non ideal parallel connection of different chips in the package does have an effect; the effect however is quiet small which proves that the signal is slightly nonuniformly distributed between the three chips in the package. External connection to PCB (drain connection is considered in this work) can effectively be taken as a point connection to some approximation. The electrical behavior of the modeled transistor was studied through the design of a class B power amplifier in order to estimate the importance of performance degradation due to non-ideal parallel connections and how these non ideal connections degrade efficiency and output power. The modeled transistor can deliver a maximum output power of 147 watts and efficiency of 65%. We have also studied the current distribution between the three chips in a three stage class B power amplifier. Again, the difference in the current distribution between the three chips turned out to be quiet small. All these results are presented through this work. The final conclusion regarding the current distribution between multichips cannot be made just based on these simulation results. The next step should be aimed at considering other effects, the thermal effect for example, in order to know exactly whether it is uniformly or not uniformly distributed. 3 Acknowledgments First and foremost, we would like to express our sincere appreciation for our supervisor, PhD Tony Fondén, for the excellence guidance, extensive corporation, and wisdom. Tony’s vast experience, patience, and thorough explanations made this thesis an incredible learning experience. We walked away from almost every conversation we had, having learned something new. This entire work was guided by his extensive research and comprehensive understanding. We would like also to thank our examiner Olof Bengtsson at the University of Gävle for providing feedback and encouragement throughout the work period. We wish to thank the entire FJB/WRP department employees at Ericsson. Special thanks to Lars Ridell Virtanen for providing us with the microscopic photos of the transistor, Janusz Holowacz for his help in ADS and Piotr Jedrzejewski for his HFSS assistance. Special thanks to Christel Karlsson, the secretary department at Ericsson, for her assistance on different administrative issues. We owe special thanks to Nedzad Lekic, the manager of the FJB/WRP department for giving us this opportunity to do this work in such professional environment and for his consistent advisement throughout this work. We would like to thank all the staff in the ITB/Electronics department at the University of Gävle, professors, teachers and colleagues. A special round of thanks goes to all members of our families for their love, support, encouragement, wishes, prayers, having confidence in us and teaching us that we should strive to be all that we can be. 4 5 Table of Contents 1. Chapter 1: Introduction…………………………………………………………….14 1.1 Introduction…………………………………………………………………….14 1.2 Outline of this thesis……………………………………………………………15 2. Chapter 2: RF Power Transistors & Amplifiers…………………………………..16 2.1 RF Power Transistors………………………………………….....................16 2.2 Si Laterally Diffused MOSFET (Si-LDMOS) ………………......................17 2.3 Application in Power Amplifiers……………………………….....................19 2.4 The MRF6S21140HR3………………………………………………………19 2.5 Modeling Strategy……………………………………………………………21 2.6 RF Power Amplifiers………………………………………………………...22 2.6.1 Operating Classes…………………………………….....................24 2.6.2 Input/Output matching networks…………………….....................26 2.6.3 Efficiency…………………………………………………………28 2.6.4 Gain………………………………………………….....................28 2.6.5 Linearity…………………………………………………………..28 3. Chapter 3: RF Modeling of Prematch Circuitry………………...….....................30 3.1 Introduction…………………………………………………………………30 3.2 Geometry……………………………………………………………………31 3.3. Theory………………………………………………………….....................32 3.3.1 Electromagnetic simulations and modeling………...……………..32 3.3.2. Modeling methodology……………………………………………33 3.3.2.1. Modeling of Bondwires…………………….......................33 3.3.2.2. Mutual Inductances………………………...……………..35 3.4. Results and Discussions……………………………………………………..37 3.4.1. Modeling of Bondwire set 4……………………………………37 3.4.2. Bondwire set 4 & 5 Mutual inductances………………………..43 3.4.3. Modeling of Prematch Capacitors………………………………45 3.4.4. Modeling of Package Leads……………………….....................48 3.4.5. Modeling of a Prematch Single Chip Circuitry………………...56 3.4.6. Modeling of Prematch Full Package Circuitry…………………60 3.5. Conclusion………………………………………………............................67 6 4. Chapter 4: Design of Class B Amplifier using the Modeled Transistor…………..69 4.1. Introduction………………………………………………………………69 4.2. DC Simulation and I-V curves…………………………….......................69 4.2.1. Results and Discussions……………………………......................70 4.3. Design of a single chip class B power amplifier…………………………71 4.3.1 Results and Discussions…………………………….......................72 4.4. Current Distribution on three chips Class B Power Amplifier…………...74 4.4.1. Design of Three Chips Class B Power Amplifier………………..74 4.4.2. Results and Discussions………………………………………....74 4.4.3. Current and Voltage Distribution on Three Chips…….………...76 4.5. Conclusion………………………………………………………………..77 5. Chapter 5: Off Chip connection: Design of Output PCB………………………….78 5.1. Introduction……………………………………………………………….78 5.2. Design of Output PCB…………………………………………………….78 5.2.1. Realization………………………………………………………...78 5.2.2. Investigation of the Position of the output Port…………………...80 5.2.3. Comparison between wave and lumped ports for PCB…………...82 5.2.4. Crowding Effect…………………………………………………..82 5.3. Realization of drain model and PCB……………………………………...84 5.3.1. Results and Discussion…………………………………………....85 5.3.2. Conclusion………………………………………………………...87 5.4. Design of Three Chips Class B Amplifier with PCB……………………..88 5.4.1. Results and Discussion……………………………………………89 5.4.2. Conclusion………………………………………………………...96 6. Chapter 6: Onchip Current Distribution…………………………………………...97 6.1. Introduction……………………………………………………………….97 6.2. Onchip Geometry…………………………………………………………97 6.3. Equivalent Circuit…………………………………………………………98 6.3.1. HFSS Implementation…………………………………………….98 6.3.2. Momentum Implementation……………………………………..102 6.3.3. Equivalent Lumped Model………………………………………104 6.4. Power Amplifier Design and Current Distribution……………...……….108 6.4.1. Gate Current Distribution………………………………………..108 6.4.2. Drain Current Distribution………………..……………………...111 7 6.5. Conclusion………………………………………………….................116 7. Chapter 7: Summary……………………………………………………………...117 8. Chapter 8: Conclusion…………………………………………………….............118 9. Chapter 9: References…………………………………………………….............120 Appendixes Appendix A……………………………………………………………………………122 Appendix B……………………………………………………………………............130 Appendix C……………………………………………………………………............132 Appendix D……………………………………………………………………............134 Appendix E……………………………………………………………………............136 8 List of Figures: Figure 2-1: Basic types of transistors [4]........................................................................... 14 Figure 2-2 Cross section of LDMOS [4] ........................................................................... 15 Figure 2-3 A top view of the MRF6S21140HR................................................................. 18 Figure 2-4 Block diagram of a power amplifier: Input Matching Network (IMN), Output matching network (OMN), Bias Network (BN), Accessory Network (AN) ..................... 21 Figure 2-5 Classes of Power Amplifiers............................................................................ 22 Figure 2-6 Class A Vgs-Ids transfer characteristics .......................................................... 22 Figure 2-7 Class B Vgs-Ids transfer characteristics........................................................... 23 Figure 2-8 Class AB Vgs-Ids transfer characteristics........................................................ 23 Figure 3-1 Top view of the Transistor ............................................................................... 29 Figure 3-2 (a) Drain Bondwires (b) Gate Bondwires ........................................................ 30 Figure 3-3 Piecewise Approximation of Bondwires.......................................................... 31 Figure 3-4 Equivalent circuit of Bondwire Model............................................................. 31 Figure 3-5 Final Model of an array of Single Set of Bondwires........................................ 33 Figure 3-6 Definition of Mutual Inductance...................................................................... 34 Figure 3-7 Loops Formed with Network Elements ........................................................... 34 Figure 3-8 Modeling of Bondwires in ADS ...................................................................... 34 Figure 3-9 Bondwire Shape in ADS .................................................................................. 35 Figure 3-10 HFSS Input Geometry.................................................................................... 35 Figure 3-11 Closer view of Bondwire Set 4 ...................................................................... 36 Figure 3-12 Imported HFSS S-Parameters Simulations .................................................... 36 Figure 4-1 DC Simulation setup: The die model consists of drain-source capacitance C5, drain source resistance, R5, gate source capacitance C4, gate source resistance R4, and Drain Source Current Generator SDD2P........................................................................... 67 Figure 4-2 I-V characteristics ............................................................................................ 68 Figure 4-3 A single chip class B power amplifier ............................................................. 69 Figure 4-4 Some significant results of simulations............................................................ 70 Figure 4-5 Efficiency and Output Power versus swept drain voltage................................ 71 Figure 4-6 A three chips class B power Amplifier ............................................................ 72 Figure 4-7 Some significant results of simulation ............................................................. 73 Figure 4-8 Efficiency and Output Power versus swept drain voltage................................ 74 Figure 4-9 Drain current and voltage distribution between the three chips....................... 74 Figure 5-1 HFSS Model of PCB........................................................................................ 77 Figure 5-2 Exported S-parameters from HFSS.................................................................. 77 Figure 5-3 Positioning of port 1: Center, right, and left. ................................................... 78 Figure 5-4 S-parameters exported to ADS......................................................................... 79 9 Figure 5-5 Comparison results at different ports...............................................................80 Figure 5-6 Current distribution on the PCB.......................................................................81 Figure 5-7 Lumped model..................................................................................................82 Figure 5-8 HFSS model.....................................................................................................83 Figure 5-9 Difference between the three chips for lumped model.....................................84 Figure 5-10 Difference between the three chips for electromagnetic model.....................84 Figure 5-11 Difference for the three chips between electromagnetic and lumped model..................................................................................................................................85 Figure 5-12 A complete class B Power Amplifier.............................................................86 Figure 5-13 Results of simulation......................................................................................87 Figure 5-14 Drain Currents and voltages distribution for the three chips..........................88 Figure 5-15 The power amplifier for right and left position of output port.......................90 Figure 5-16 Different results for different positions of the output port of the PCB are observed. (a) Right Position is the position where one outer chip is closer to the quarter wavelength than the (b) other outer chip (left position).....................................................92 Figure 6-1 Top view of the metallization layer of the transistor die..................................95 Figure 6-2 Transistor Chip Geometry implemented in HFSS............................................96 Figure 6-3 LDMOS Model, ctr is the number of transistors on the die.............................97 Figure 6-4 Integration Lines representing the current direction through the port..............97 Figure 6-5 HFSS Geometry of the total model simulated..................................................98 Figure 6-6 (a) Structure with 2 ports (b) Structure with 4 ports........................................98 Figure 6-7 HFSS Simulations results exported to ADS.....................................................99 Figure 6-8 Comparison between real and imaginary S-parameters values of Gate input and Gate metallization ports...............................................................................................99 Figure 6-9 Comparison between Gate input and metallization ports after connecting them to the gate source capacitance and resistance...................................................................100 Figure 6-10 Momentum Implementation.........................................................................101 Figure 6-11 Comparison between gate ports without (a) and with (b) connecting them to the gate source and drain source capacitance and resistance...........................................101 Figure 6-12 Momentum layout for two consecutive gate and drain fingers....................102 Figure 6-13 Equivalent Lumped Model...........................................................................102 Figure 6-14 Comparison results between lumped and electromagnetic simulation for two consecutive fingers...........................................................................................................103 Figure 6-15 Layout of the metal plate connecting the bondwires....................................104 Figure 6-16 Equivalent lumped model.............................................................................104 Figure 6-17 Comparison results.......................................................................................104 Figure 6-18 Full lumped model for the onchip metallization..........................................105 10 Figure 6-19 Comparison between electromagnetic and lumped model for the full onchip metallization ....................................................................................................................106 Figure 6-20 Three LDMOS models connected between drain and gate fingers.............. 106 Figure 6-21 Power Amplifier schematic.......................................................................... 107 Figure 6-22 Comparison between magnitudes of intrinsic gate voltages for different sub transistors......................................................................................................................... 108 Figure 6-23 Comparison between magnitudes of intrinsic gate voltages for different sub transistors positioned at the same side ............................................................................. 109 Figure 6-24 Modified LDMOS Transistor Model ........................................................... 110 Figure 6-25 Two LDMOS modified models connected to a drain finger........................ 110 Figure 6-26 Class B Power Amplifier circuit Design ...................................................... 111 Figure 6-27 Intrinsic Drain Current and Voltage of the six Sub Transistors ................... 112 Figure 6-28 Intrinsic Drain Current and Voltage of the three Sub Transistors connected to the edge of the fingers...................................................................................................... 113 Figure 6-29 Intrinsic Drain Current and Voltage of the three Sub Transistors close to the drain side.......................................................................................................................... 113 Figure E-0-1 Bondwires positions inside the package..................................................... 134 Figure E-0-2 Bondwire Set 1 ........................................................................................... 134 Figure E-0-3 Different Distances related to Bondwire Set 1 ........................................... 135 Figure E-0-4 Geometry of Bondwire Set 1...................................................................... 135 Figure E-0-5 Bondwire Set 2 ........................................................................................... 135 Figure E-0-6 Different Distances related to Bondwire Set 2 ........................................... 136 Figure E-0-7 Geometry of Bondwire Set 2...................................................................... 136 Figure E-0-8 Bondwire Set 3 ........................................................................................... 136 Figure E-0-9 Different Distances related to Bondwire Set 3 ........................................... 137 Figure E-0-10 Geometry of Bondwire Set 3.................................................................... 137 Figure E-0-11 Bondwire Set 4 and Set 5 ......................................................................... 137 Figure E-0-12 Different Distances related to Bondwire Set 4 & Set 5............................ 138 Figure E-0-13 Geometry of Bondwire Set 4.................................................................... 138 Figure E-0-14 Geometry of Bondwire Set 5.................................................................... 139 11 Chapter 1 1.1. Introduction To meet the needs of the cellular and personal communication systems market, which is continuing to move towards 3G air-interfaces such as GPRS, CDMA2000 and WCDMA, high power RF devices are being designed to be smaller, more efficient, low cost-cost and more manufacturability. The power gain, output power, efficiency and linearity of the power amplifier are critical parameters that affect the overall performance and cost-effectiveness of the system. Silicon technology has evolved to meet these needs especially with the laterally diffused metal-oxide semiconductor transistor LDMOS. As performance aspects such as gain, efficiency, linearity and reliability continue to improve, accurate and efficient modeling techniques for these RF power modules from the device level to the package level become very important [1]. The main goal of this work was conducting investigation on the signal distribution between the multichips of the transistor. Studies will be performed on the current distribution between the multichips through the modeled transistor and through applying this model in the design of power amplifier to study whether the signal is uniformly or not uniformly distributed between the multichips and to conclude the main contributor to the non uniformity distribution. Another question addressed in this work is whether it is possible to find a general model for power transistors, where the resulting model is able to predict the DC behavior, the RF small signal behavior and the RF large signal behavior of power transistor. The model should include the electrical effects of the prematch capacitors, the bond wires, the package, the die and the PCB (Printed Circuit Board).. Also comparison between the electromagnetic and electrical models of the transistor will take place to make sure that both models lead to consistent results. To access the modeling approach, an existing power transistor is chosen: The Freescale MRF6S21140H transistor, which is a RF power field effect transistor (N-Channel Enhancement-Mode Lateral MOSFET) with externally one gate lead, one drain lead, and one source connected to ground plane. This transistor is designed for WCDMA base station applications with frequencies from 2110 to 2170 MHz. Several strategies are available for modeling power transistors. In our work, modeling by segmentation is used [2]. The four components of a power transistor (the die, the prematch capacitors, the bondwires, and the package) are modeled separately. Agilent’s Advanced Design System (ADS) was used to simulate the electrical circuits representing the electrical behavior, and Ansoft’s 3D Full-Wave Electromagnetic Field Simulation HFSS was utilized to create 12 actual electromagnetic models for the geometry and material parameters of the MRF6S21140HR3 transistor and a PCB structure relevant to this transistor. The lumped model in addition with the PCB will be used in designing a class B power amplifier to investigate the current distribution on the transistor chips inside the package. In addition the same study will be taken for the Onchip interconnection by finding a suitable lumped model and then using it also in a design of a power amplifier to study the uniformity between different parts of the chip. Many studies have been made on parts and modeling of Power transistors. One of the many references that have been used is a work performed on Modeling of RF High Power Bipolar Transistors at the Technical University of Delft by Koenraad Mouthaan [2]. The work includes electrical and thermal modeling of the Philips BLV 910 high power transistor. It emphasizes whether it is possible to find a general modeling strategy of power transistors. Another reliable reference is the work done by Johan Sjöström [3] at Ericsson concerning the Quasistatic Electromagnetic Modeling and Simulation of the package for MIC’s LDMOS transistors PTF10136. Concerning the current distribution in RF power transistors, there were no direct studies on the uniformity in the signal distribution between the multichips. However, most of the relied information that has been used was some IEEE publications that mainly focused on the distributed effects in RF power transistors based on performance aspects, but the most reliable sources were some internal researches and reports provided by Ericsson. 1.2. Outline of the thesis • Chapter 2: Brief overview of RF power transistors. The Si-LDMOS is introduced. Power Amplifiers: Operation classes and the typical and specific properties for a power amplifier. • Chapter 3: RF Modeling of Prematch Circuitry including modeling of bondwires, package leads, prematch capacitors, etc… • Chapter 4: Design of Class B power amplifier using the modelled transistor. Design of single and multichips power amplifier is introduced. Current distribution between multichips is investigated. • Chapter 5: Off chip connection: Design of output printed circuit board and its realization with the drain model. • Chapter 6: Onchip current distribution • Chapter 7: Summary • Chapter 8: Conclusion • Chapter 9: References 13 Chapter 2 2.1. RF Power Transistors RF power transistors are devices designed to amplify RF signals to high powers. Transistors can be separated into two main groups: Bipolar and Unipolar. Bipolar Junction Transistors (BJT) use both electrons and holes as charge carriers. Unipolar or Field effect transistors (FET) operate only with one type of charge carriers. However there exist different types of FETs, as Metal-Oxide (Insulator)-semiconductor-FET or referred as (MOSEFET or MISFET), and other FETs transistors (Figure 2.1). Figure 2.1 shows basic types of transistors Figure 2-1: Basic types of transistors I [4] There are two main types of the MOSFET: a depletion transistor (D-MOSFET) and an enhancement transistor (E-MOSEFET) which is mostly used, and there are many technologies for power devices such as LDMOS that uses the enhancement mode. The SiLDMOS is used in this work I Used with permission of the author. J.Olsson et al., 1W/mm RF power density at 3.2 GHz for a dual-layer RESURF LDMOS transistor, IEEE Electron Device Lett, vol. 23,pp.206-8, April 2002 14 2.2. Si Laterally Diffused MOSFET (Si-LDMOS) As mobile communications networks spread in services and grow in quality, new challenges are posed on their supporting RF electronics. One of the circuits where this push forward has been mostly sensed is the RF power amplifier, PA, either in its hand-held or base-station versions. For the latter one, maximized output power, power added efficiency and linearity are requirements difficult to be simultaneously reached. System designers have continuously demanded for innovative PA designs and new solid-state devices. One of these technologies, which has presented promising capabilities in terms of output power Pout, power added efficiency PAE, and nonlinear distortion, was the Silicon Laterally-Diffused Metal-Oxide Field Effect Transistor, Si LDMOS. The LDMOS devices exhibit some interesting properties such as better linearity and a negative temperature coefficient. It is therefore today the dominating device in base station amplifiers for mobile telephone systems. The lateral diffused metal-oxide-semiconductor transistor (LDMOS) was developed for RF applications in 1972 by Sigg [5]. Today it has replaced the bipolar transistors in many high-power telecommunication applications since the LDMOS has several advantages over the bipolar, and we will state few of them: • For high drain current, the MOSFETs have high input impedance and lower temperature coefficient. • Thermally more stable, FET cells combine better with each other than cells of bipolar transistors. This makes it easier to scale the active area when designing for high output power. In addition, the good thermal stability of the MOSFET causes superior load-mismatch tolerance in comparison to the BJT. • The MOSFET devices have lower inter-modulation distortion (IMD) than the bipolar. • In addition, due to quite low inductance (due to a single bulk-source connection), MOSFETs have a higher power gain than bipolar transistor [6]. Figure 2.2 shows a cross section of LDMOS Figure 2-2 Cross section of LDMOS II [4] II Used with permission of the author. J.Olsson et al., 1W/mm RF power density at 3.2 GHz for a dual-layer RESURF LDMOS transistor, IEEE Electron Device Lett, vol. 23,pp.206-8, April 2002 15 In Class AB mode of operation, LDMOS transistors have superior inter-modulation performance over bipolar transistors due to a softer high power saturation 'knee' and improved linearity at low power levels. There are two general disadvantages of the MOSFETs. First, the gate is sensitive to electrostatic charges. The sensitivity to electric charges causes two problems: lowering of the threshold voltage and risk to destroy the device 1 (electrostatic charges). Second, at higher temperature the output power is reduced due to decreasing of trans-conductance. The short channel length is typically created by the lateral diffusion of a p-type implantation. The LDMOS has a slightly lower doped and long n type drift region, which enhances the depletion region, thus increases the breakdown voltage. On the other hand, the on-state drain resistance is higher which degrades RF performance, thus there is always a trade-off between RF output power and on-resistance [5]. The n+ source is strapped to a p+ sinker region by the source metal, then p+ sinker is diffused to connect to the p+ substrate, which is itself bonded to the RF ground, thus minimizing common lead inductance and maximizing common source RF power gain. The source metal, isolated by a dielectric layer, also extends over the polysilicon gate to provide an interelectrode shield (not in Fig 2.2), thereby minimizing drain-gate capacitance C gd [7]. The sinker principle is used for lateral power devices, and obvious advantage is in decreasing number of contacts on the surface that makes LDMOS easier to integrate. The single source contact made on the backside of bulk substrate, eliminates the extra surface bond wires. Therefore device integration is much easier since there are only two contacts left on the surface namely, drain and gate. The LDMOS could be seen as a transformation of a low power MOSFET transistor. There are additional features, which improve RF properties and produce higher power. The RF performance using such connection is better, because the source inductance is reduced. The high-frequency properties of Si-LDMOS transistor is usually determined by the length of the channel region. The shorter channel length improves the linearity since the transistor always works in velocity saturation [7]. 1 Largely reduced by protection diodes in today’s devices. However, in some specialized applications, the protection diode may disturb operation. 16 2.3. Application in Power Amplifier Makers of wireless infrastructure equipment and cellular handsets are constantly pressured to beef up performance while cutting the size and cost of their systems. The emerging third generation (3G) of mobile communications applications is only adding to the stress. It's not surprising that designers of such equipment are always exploring newer techniques and low-cost alternatives. This is especially so in the RF power arena, a critical communication-system function that enables the signal to reach all the nooks and crannies in a communications cell. In the 900-MHz to 2.4-GHz spectrum, power-amplifier designers are tapping recent advances in silicon-based lateral-diffused MOS (LDMOS) power transistors to create new solutions as viable alternatives to bipolar junction transistors (BJTs), gallium-arsenide (GaAs) FETs, and hetero-junction structures. LDMOS power transistors have improved in efficiency, linearity, peak-power capability, and cost-per-watt performance, as well as matched input/output impedances for easy implementation. Though LDMOS technology has progressed substantially in the last few years, its efficiency is still trailing behind GaAs transistors at higher frequencies and higher power levels. Moreover, bias-current drift continues to haunt the technology. Unlike some other FET’s, the dies are fabricated with a grounded internal source connection, which removes the need for the insulating layer of toxic beryllium-oxide. This offers the benefits of reduced package cost and lower thermal resistance. The devices have generally higher power gain and are more Voltage Standing Wave Ratio (VSWR) tolerant. VSWR is the ratio of the maximum/minimum values of standing wave pattern along a transmission line to which a load is connected. Recent advances in the performance of silicon-based LDMOS have given RF power amplifier (PA) designers a viable alternative to create competitive solutions for infrastructure equipment in 0.9 to 2.5 GHz. Besides improvements in efficiency, linearity, peak-power capability, and cost/Watt, the developers have licked the bias current drift and aging issues that plagued this transistor for some time. Consequently, it has replaced bipolar and is going head-on against gallium-arsenide (GaAs) FET’s and hetero structures [8]. 2.4. MRF6S21140HR3 (N-Channel Enhancement-Mode Lateral MOSFETs) The MRF6S21140HR3 from Freescale is designed for W–CDMA base station applications with frequencies from 2110 to 2170 MHz. It is Suitable for TDMA, CDMA and multi-carrier amplifier applications. 17 It is to be used in Class AB for PCN–PCS/cellular radio and WLL applications. This transistor is capable of delivering 140 Watts in the 2110-2170 MHz frequency range [9]. A top view photograph of the MRF6S21140HR3 high power transistor is shown in Figure 2.3 Figure 2-3 A top view of the MRF6S21140HR Some specific parameters of the MRF6S21140HR are presented in Table 2.1. Rating Drain-Source Voltage Symbol Unit VDSS Value -0.5, +68 Gate-Source Voltage VGS -0.5, +12 Vdc PD 500 2.9 W Storage Temperature Range Tstg -65 to +150 ο C Case Operating Temperature TC 150 ο C TJ 200 ο C Total Device Dissipation@ TC = 25 ο C ο Derate above 25 C Operating Junction Temperature Table 2-1 Maximum ratings for MRF6S21140H 18 Vdc ο W/ C In general, a power transistor contains four types of components: 1) The transistor die(s): The die is the part of the power transistor where the amplification takes place. The die consists of a block of silicon with a number of active areas referred to active cells. The actual amplification of the power transistor is taking place in these active areas. In power amplifiers up to a few ten of watts, one die is normally used. But for higher power amplifiers, multiple dies are found. Device technologies constantly improve and optimize the performance of the die by changing doping profiles and geometries of the die. 2) The matching capacitor(s): The matching capacitor consists particularly of a layer of isolating silicon oxide. It had been introduced to match the low impedance of the die to somewhat higher impedance at the input of the transistor. This matching is achieved by using the combination of the inductive behavior of the bond wires in combination with the capacitors. Similarly the post match capacitor has been introduced to transform the output impedance of a power transistor to higher impedance. 3) The bondwires: Bondwires are wires with diameter in the order of 25-50 μm . The wires interconnect the die, the prematch capacitor and the package. They also provide matching of the low (and largely capacitive) input impedance of the die to higher (and less reactive) impedance at the input of the transistor. The main purpose of the drain shunt bondwires is to approximately resonate out the drain source capacitance. 4) The package: The main function of the package is to provide a good, reproducible and solderable interface to the relatively small internal components. It also protects the internal components. The die and the prematch capacitor are attached to the package, and bondwires are placed to interconnect the components. The package itself consists of a metal block with ceramic substrate attached to it. 2.5. Modeling strategy Several strategies are available for modeling power transistors as modeling by measurement, modeling by rigorous calculations, and modeling by segmentation. In our work modeling by segmentation is used [2], the four components of a power transistor (die, prematch capacitor, bondwires and package) are modeled separately .For each component a separate model having a limited number of parameters and number of ports is built. These models can be based on measurements, rigorous calculations or approximations and electromagnetic simulations. Models are connected together in an electrical simulator and the resultant network is solved for currents and voltages. The segmentation approach is useful because it allows a flexible modeling of the power transistor. Building models of separate components yields compact models relatively fast. 19 Even if some modeling parts of the project would fail, models of separate components would still be available. If for example one model fails to describe the behavior of bondwires correctly, this model can be replaced by another model without changing the whole model for the power transistor. In some cases, parts may even be modeled with discrete elements such as inductors, resistors, capacitors and transmission lines 2 . Additionally, implementation of a model for a transistor reduces to the implementation of models for the components which can be optimized for maximum computational speed and minimum memory usage. An advantage of implementing separate models is that each model can be fully optimized for computational speed and memory usage. In many cases however, the optimization does not improve the overall speed and memory requirements for a full model of a transistor. Only dominant effects are modeled and some couplings are neglected. The exact accuracy of the model is hard to estimate. Accuracy of the model is an important point to consider. Due to some various approximations made, there can be a considerable error in the results. In some cases, these errors can be traced by comparing the model with measurements or rigorous calculations. In principle, it should be possible to estimate the accuracy of the model of each component by performing rigorous calculations. By comparing the complete model of a power transistor with for example measurements, it should be possible to find the error introduced by the neglected couplings. The optimization of the modeled performance of a power transistor can be rather difficult due to the large number of parameters involved and the influence each parameter has on the overall performance of the power transistor. If the desired response of each model is known, it is in principle possible to optimize the parameters associated with that model for the desired response. 2.6. RF Power Amplifiers Wireless communication has emerged as a mass communication medium and is growing rapidly. The combination of new services, advanced technologies and free market price competition has made wireless communication attractive for virtually anyone. Wireless communication is in essence the bidirectional link between a mobile telephone on the one hand and a base station on the other. A mobile telephone consists of a transmitter to send signals to the base station and a receiver to receive signals from the base station. 2 A transmission line is not a discrete element although an ideal transmission line is a distributed component of a particularly easy sort, and can sometimes be used to good advantage in circuit models. 20 The RF power amplifier (PA), a critical element in transmitter units of communication systems, is expected to provide a suitable output power at a very good gain with high efficiency and linearity. The output power from a PA must be sufficient for reliable transmission. High gain reduces the number of amplifier stages required to deliver the desired output power and hence reduces the size and manufacturing cost. High efficiency improves thermal management, battery lifetime and operational costs. Good linearity is necessary for bandwidth efficient modulation. However these are contrasting requirements and a typical power amplifier design would require a certain level of compromise. There are several types of power amplifiers which differ from each other in terms of linearity, output power or efficiency. Power amplifier design involves providing simultaneously effective impedance matching (depending on the technical requirements and operation conditions), stability in operation and practical implementation. This is most easily achieved by performing an accurate device modeling. The quality of the power amplifier design is evaluated by realizing the maximum power gain under stable operating conditions with minimum amplifier stages regardless of the requirement for linearity or high efficiency. Some of the typical design aspects of power amplifier are gain and gain flatness, output power, efficiency, operation frequency and bandwidth, etc… The bias network is an important part of the power amplifier design. In fact, the bias network (BN) controls the operation class of the transistor and at the same time it prevents the RF signal from leaking to the DC source and prevents the DC signal from leaking to the RF trajectory. The Bias network of a high power amplifier differ from the normal amplifier by the fact that it is non resistive. The main reason behind that choice is that high power amplifier consumes high current, so to prevent additional heating in the system, non-resistive bias network is used. The block diagram of a power amplifier using n-channel FET which is dominating at RF is shown in Figure 2.4. Figure 2-4 Block diagram of a power amplifier: Input Matching Network (IMN), Output matching network (OMN), Bias Network (BN), Accessory Network (AN) 21 2.6.1. Operating Classes In order to operate a transistor for a certain class, the gate and drain DC voltages have to be biased carefully to the certain operation point (quiescent point or q-point). The reason is that the choice of q-point greatly influences linearity, power handling and efficiency. Figure 2.5 shows typical classes that are chosen according to specific requirements [10]: Figure 2-5 Classes of Power Amplifiers Class A: Class A is the most linear amplifier with the q-point biased close to half of the maximum drain current. The class A amplifiers are also characterized by maximum possible conduction angle (2π) and rather low DC power efficiency (equal or less than 50% in theory 3 ). Figure 2.6 shows close to ideal transfer characteristic with biased q-point for class A operation. The strongly non-linear effect (overdrive) occurs only when the drain current exceeds its saturation point (pinch-off) and/or gets into sub threshold region (cutoff) Figure 2-6 Class A Vgs-Ids transfer characteristics 22 Class B: For a class B amplifier the operation point has to be selected at the threshold voltage to achieve high power efficiency (equal or less 78 % in theory). The reduced linearity for class B (as compared to class A) is the so called ‘’cross over distortion’’, the 180 degree conduction angle by itself does not introduce any distortion in the relevant frequency interval (Figure 2.7). There will be current through the device only during half of the input waveform (the positive part for the N-channel transistor). Hence, the input amplitude requirement of such a mode is twice as high as for class A. Figure 2-7 Class B Vgs-Ids transfer characteristics Class AB: The class AB amplifier shows a flexible solution for a trade-off between linearity and efficiency of the previous classes. In this mode the q-point has to be chosen in between A and B points with its exact place being a matter of application requirements. Therefore, the conduction angle is π-2π and typically chosen closer to the threshold voltage. Thus, the transistor response of class AB is wider than for class B due to the operation point. Also, the power efficiency is higher than for class A. Many telecommunication applications utilize this mode. Figure 2-8 Class AB Vgs-Ids transfer characteristics IV 3 For maximum output And just as important, efficiency decreases even much more with decreased input signal amplitude than for class B IV Figures 2-5, 2-6, 2-7, 2-8 are used with permission of the author. S. C. Cripps, RF Power Amplifiers for Wireless Communication, Norwood, MA, Artech House, 1999. 23 Table 2.2 brings together comparisons for different classes in terms of quiescent point and conduction angle. Class A B AB q-point ( 0.5 0 0-0.5 Vq ) Quiescent current ( 0.5 0 0-0.5 Iq /Imax ) Conduction angle Max efficiency 2π π π -2 π 50 % 78 % 50 % - 78 % Table 2-2 Comparison for different classes of amplifiers 2.6.2. Input/Output matching networks (IMN & OMN) An important aspect in the design of power amplifier is the input/output matching networks (IMN&OMN). The design also comprises the accessory networks (AN) for adjusting conditions for proper operations of transistors. In power amplifier designs, to achieve high accuracy, high maximum output power, high gain and high efficiency a matching network is required on the input and the output. Matching networks are passive, consisting of micro-strip lines, inductors, capacitors and resistors3. Input and output matching networks transform the input and output impedance of the transistor to the source and load impedance. They provide proper transformation of impedance between source and the power amplifier as well between the power amplifier and load in order to achieve maximum gain, output power and efficiency [11]. There are three types of matching principles: 1) Conjugate matching The conjugate matching for the maximum gain is similar to what is issued in low noise amplifier (LNA) design. The IMN and OMN are adjusted to transfer source/load impedance (often 50 ohms) toward device input/output impedance. By this method, theoretically, it is possible to achieve the maximum power gain and the minimum losses due to standing waves. In practice, during design it is important to consider the trade-off between the noise factor and the maximum achievable power gain. The conjugate matching is based on small signal S-parameter analysis. It is not effective for power amplifier, because the input signal cannot be treated as a small-signal. 3 Normally no resistors, save for parasitic resistance that should preferably be as small as possible 24 2) Load Line Matching The load line matching is explained in Cripps [9] and will be used in our work. The general idea is based on load line optimal resistance matching ( R opt ) which provides highest output power. Therefore the output matching network OMN must transform the external load (50 Ohms) so it is transformed to R opt of the device at the intrinsic drain. The final formula to find R opt is expressed as follows: R opt = (Vdmax − VKnee ) I dmax (1) Where Vdmax is the maximum intrinsic drain voltage, Vknee is the point where current reaches saturation region when Vgs is constant and I d max is the maximum instantaneous drain current. The design of input matching network IMN is similar to conjugate matching. The theoretical result of loadline-matching design generally is 0.5-3 dB higher in 1dB compression point ( P1dB ) than the conjugate matching [9]. 3) The matching based on Load Pull Analysis This matching technique is based on a seeking of the optimal load impedance, which gives the convenient and flexible solution to solve a trade-off between efficiency, output power and possibly other parameters. The method from the very beginning utilized the relevant measurement equipment [10]. The Power and efficiency contours are generated empirically by the connecting various loads to the amplifier and by measuring the gain and the output power at each value of the load impedance. The simple ideal load line match can actually be seen as simple ideal theoretical model of such a load pull match. So for an ideal class B amplifier, they are actually not different, but same matching method. If sub-transistors are connected in parallel, and if the current is distributed equally between the sub-transistors, i.e. if they see same voltages and have same currents, hence it is still possible to provide a match that is ideal for all the sub-transistors at the same time. However, if they do not have the same currents, then designing an ideal match for some sub-transistors could be not ideal for other sub-transistors resulting in degraded for output power capability and efficiency. 25 When designing a power amplifier, some important parameters that should be considered are: Power (dBm or watts), Efficiency, Gain (dB), Linearity, and Stability 2.6.3. Efficiency One measure of amplifier efficiency is the drain efficiency defined as the ratio of the RF output power to DC input power: η= POUT , where PDC = VDC * I DC PDC (2) One drawback of this definition is that it does not account for the RF power delivered at the input of the amplifier. Since most power amplifiers have relatively low gains, the efficiency tends to overrate the actual efficiency. A better measure that includes the effect of input power is the power added efficiency, defined as: PAE = POUT − PIN P = (1 − 1/G ) * OUT = (1 − 1/G ) * η PDC PDC (3) Where G is the power gain of the amplifier. Silicon transistor amplifiers in the cellular telephone band of 800-900 MHz band have power added efficiencies on the order of 80%, but efficiency drops quickly with increasing frequency. Power amplifiers are often designed to provide the best efficiency, even if this means that the resulting gain is less than the maximum possible. PAE is generally used for analyzing PA performance when the gain is low. This parameter is of particular importance from power consumption and power dissipation point of view. It is usually quantified in percentage. 2.6.4. Gain In microwave designs, the gain is represented by different definitions. Its most representative definition is the transducer power gain. It is the ratio between the power delivered to the load and the power available from the source. Transducer gain can be expressed by: G= PL PS (4) Where PS is the RF available input power and PL is the RF output power. 2.6.5. Linearity The RF power amplifiers are inherently non-linear and are the main contributors for distortion products in a transceiver chain. Power amplifiers effect the utilization of the spectrum through nonlinear performance. Non-linearity is typically caused due to the 26 compression behavior of the power amplifier, which occurs when the RF transistor operates in its saturation region due to a certain high input level. Cross-over distortion is particularly important at low input level. The term crossover signifies the "crossing over" of the signal between devices, in this case, from the upper transistor to the lower and viceversa. Some of the widely used figure of merits for quantifying linearity is the: • 1 dB compression point • Third order inter modulation distortion • Third order intercept point (IP3) • Adjacent channel leakage ratio ACLR or adjacent channel power ration ACPR These quantities are explained in [10] 27 Chapter 3 3.1. RF Modeling of Prematch Circuitry Introduction In this chapter, results from electromagnetic modeling and simulation for the passive parts of the package for MRF6S21140H RF power field effect transistor, using HFSS and ADS are presented. The common components of power transistors are dies, bondwires, matching capacitors and a package. As stated before the modeling approach chosen is to model each component separately and to connect all sub models together to form a full electrical model. We will take a brief look at the electromagnetic simulation and modeling. The simulations were done using HFSS and all models have as input physical constants, spatial dimensions, material permittivities and conductivities. The modeling starts with the bondwires. The lumped model of a single bondwire is given in terms of a pi network that is composed by a series resistance, inductance and two shunt capacitances. Then the model of a single wire is extended to a model for multiple parallel wires. The mutual inductances effect between sets of bondwires is also taken in consideration and is computed using the delft model in ADS. The modeling of prematch capacitors is considered. The package includes six prematch shunt capacitors where each one will be modeled as a single lumped capacitor and one gate prematch capacitor composed of a copper plate over a dielectric substrate of relative permittivity 9 [13] and will be modeled as a RLC circuit. . The modeling of the package leads will be considered. The lead capacitances are composed of a dielectric substrate of relative permittivity 9 and a copper plate of thickness 0.12 mm. The electromagnetic simulation was done in HFSS including the physical geometry and 4 ports (1 input port and 3 internal ports from lead to the three chips). Finally all the extracted lumped models will be connected together to form a full model of the package that reflects the behavior of the prematch circuitry up to 5 GHz. We have to mention also that difference less then 10% between lumped model and electromagnetic simulation is presented, and all the fitting procedures was done in terms of S-Parameters. It is important to note that for a correct description of the electrical behavior, the thermal behavior (not be included in our work) must also be considered since a substantial amount of electrical power is dissipated, introducing an increase in temperature. Electrical modeling of packages for high-speed digital and high-frequency analog 28 applications has been a field of strong interest in recent years. Modeling techniques, based on either quasi-static algorithms or full-wave solutions, have been developed and are widely used. The quasi-static solutions are fast and computationally efficient. However, they only represent the low-frequency approximation to Maxwell’s equations [14]. With continuing improvement in numerical algorithms and computer performance, full-wave characterization becomes increasingly popular due to its greater accuracy. Among available full-wave numerical techniques [15], the finite-element method (FEM) is the most flexible technique for the analysis and characterization of geometrically complex electronic packaging structures [16]. 3.2 Geometry Images of RF power transistor MRF6S21140H - captured by a microscope are shown in Fig. 3.1, Fig. 3.2 and Fig. 3.3. Fig. 3.1 shows a top view, Fig. 3.2(a) shows a side view of the bondwires connected to the transistor chip after that the package was cut in half; Fig. 3.2(b) shows a side view of the bondwires to the gate lead. The geometrical models were extracted quantitatively from these pictures. A few accessible structures (Package leads, transistor chips, prematch capacitors) were measured on the physical transistor and then measuring the corresponding on pictures, and could so obtain scale factors. These figures along with many several figures helped us to extract the geometry and dimensions of each component inside the package as accurately as possible, but this accuracy remain a point of interest specially in seeing how much the simulations will be affected by small differences in any dimension of the components. These differences in small variations of the dimensions in the bondwires geometry will be studied throughout this work. Figure 3-1 Top view of the Transistor 29 (a) (b) Figure 3-2 (a) Drain Bondwires (b) Gate Bondwires 3.3 Theory 3.3.1 Electromagnetic Simulations and Modeling The electromagnetic behavior of packages or interconnect structures can be determined by solution of Maxwell's equations. Given macroscopic material parameters like conductivity and permittivity, and boundary conditions set by geometry and excitations, the unknown electric and magnetic fields in the structure can be calculated. To use a structure in a circuit connected with other components, it must be characterized by its behavior as seen from one or several access ports (Appendix D). This is done by applying excitation signals at the ports, and calculating the resulting internal electromagnetic behavior, including the response at the ports. The relation between port quantities, such as voltages and currents, can be described by multiport matrices, such as the impedance, admittance, scattering, inductance, capacitance, and resistance matrices. These can be implemented in circuit simulators for use in circuit simulation. One of the main problems with EM simulation of realistic packages is the heterogeneous nature of the geometry [13]; the PCB transmission line and ground plane being orders of magnitude larger than the transistor gate width. Another problem is that at high frequencies, the inductive behavior of the current paths, in combination with ohmic loss, makes the current distribution in the conductor no uniform (skin effect). Thus, to be able to accurately calculate high frequency loss requires a model capable of representing this no uniform current, which typically means even more unknowns, increasing complexity. In this work, the full wave EM simulation tool HFSS from Ansoft was used [17]. It is an interactive software package for calculating the electromagnetic behavior of a structure. The software includes post-processing commands for analyzing this behavior in detail. HFSS has been used for extraction of inductance and capacitance in packages and on-chip interconnect for RF integrated circuits and RF power transistors. 30 3.3.2 Modeling Methodology 3.3.2.1 Modeling of Bondwires The MRF6S21140H contains five sets of bondwires, two on the drain side and three on the gate side. Each set is formed by three arrays and each array has several bondwires in parallel. All the bondwires are made from aluminum and have a radius of approximately 30 μm . In modeling, each bondwire is represented by a specific number of straight segments. This is illustrated in Figure 3-3, where the microscopic photo of a bondwire is shown: on the left two coupled bondwires are shown; on the right, five segments representing the bondwire are shown. Figure 3-3 Piecewise Approximation of Bondwires The geometry of the bondwires with their corresponding lengths, heights above ground plane and separating distances between arrays and sets can be found in Appendix E. To a first approximation, the lumped model of an array of bondwires is given in term of an equivalent low pass pi-network that is composed by a series inductance, resistance and two shunt capacitances. Figure 3-4 shows the simplified model where L1 is the total inductance of the bondwire array, R1 is the total resistance and C1, and C2 represent the capacitances to ground plane of the bondwire array. Figure 3-4 Equivalent circuit of Bondwire Model These quantities RLC [18] can be calculated as: ⎛ 1 ⎝ ω * Y12 • L = im⎜⎜ ⎞ ⎟⎟ (H) ⎠ 31 Y + Y12 ⎞ • C1 = im⎛⎜ 11 ⎟ (F) ω ⎝ ⎠ ⎛ Y + Y21 ⎞ • C 2 = im⎜ 22 ⎟ (F) ω ⎝ ⎠ (5) • R = real⎛⎜ 1 ⎞⎟ ( Ω ) ⎟ ⎜ ⎝ Y21 ⎠ Where the Y (Admittance matrix frequency dependent) parameters are extracted from the electromagnetic simulations. The component values (L, C1, C2, and R) are not constant but frequency dependent. And this frequency dependence makes the model only seemingly lumped because a lumped model in the strict sense should have frequency independent components values. If we took a constant resistance then this model approximation simplifies the computations of the resistance substantially since the accurate computation of the resistance requires the current distribution in the bondwire to be known with high accuracy [2]. To be able to accurately calculate high frequency loss requires a model capable of representing this nonuniform current (e.g., Skin effect).The HFSS is able to accurately compute these distributions. In particular HFSS cannot compute DC solution and has often problems at low frequency. For a second approximation the loss in the bondwire can be calculated analytically. The DC resistance is computed using: R DC = 1 (Ω) σ * π2 * r2 (6) Where l is the length of the bondwire, r is the radius of the bondwire and σ is the conductivity of the bondwire. And the Skin effect resistance is computed using: R AC = 1 ( Ω ) where δ S = σ * 2 * π * δS These two resistances intersect at the frequency: f= 1 π *f *μ *σ * (7) 4 . Far below this frequency π*r *μ*σ 2 the DC resistance dominates and far above this frequency the skin resistance dominates. In principle the inductance of the bondwires should also be modified for the skin effect behavior but its effect is found negligible for the frequencies used. The first disadvantage of this model is its limited scoop, it treats only the resistance, the second disadvantage is its approximate nature and finally it is still not a strictly lumped model. So the simple analytical model of the AC resistances calculated above is only used for comparison, as a consistency check and as a way to better understand the qualitative physics of the loss in the bondwire. * Microwave Engineering by David M. Pozar, third addition. 32 Finally to have a model that is actually in a strict sense lumped and including the skin effect in the bondwire, the circuit in Figure 3-5 is used (A lumped model with frequency independent component values). The accuracy is of course a little limited but by comparing to the very accurate seemingly lumped model of figure 3-4, we can see that it is still accurate enough for many purposes. Figure 3-5 Final Model of an array of Single Set of Bondwires 3.3.2.2 Mutual Inductances Mutual inductance is the concept that the current through one inductor can induce a voltage in another nearby inductor. It is important as the mechanism by which transformers work, but it can also cause unwanted coupling between conductors in a circuit. The mutual inductance M is also a measure of the coupling between two inductors. To calculate the mutual inductances between the bondwires inside the package of the transistor, Philips/TU Delft Bondwires Model [2] in ADS was used. The Bondwire model calculates the inductance matrix of coupled bondwires using Neumann’s inductance equation. L ij = ϕ ij Ij = dI i .dI j μ 4π C∫i C∫j ri − r j (8) The principle of this equation for closed loops is illustrated in Figure 3-17. The mutual inductance Lij between a closed loop Ci and a closed loop Cj is defined as the ratio between the flux through Cj, due to a current in Ci, and the current in Ci. The figure shows the definition of the mutual inductance between two current carrying loops as the ratio of the magnetic flux in contour Cj and the current in loop i [19]. In practice, however, bondwires are only part of a loop. To account for this effect, the concept of partial inductances is used. This concept is illustrated in Figure 3-6. This 33 figure illustrates that the model calculates the partial inductance between the bondwires, ignoring possible couplings between the wires and other circuit elements. Figure 3-6 Definition of Mutual Inductance Figure 3-7 shows Current carrying loops formed with network elements. On the left, closed loops are shown using elements such as a capacitor, a resistor and a voltage source. Each loop also has a Bondwire. If only the mutual inductance between the wires is of interest, the concept of partial inductance is used [20] where for reasons of simplicity the mutual coupling between the wires and the remaining network elements is assumed negligible. In this case Neumann’s inductance equation is not applied to the closed contours, but to the wires only. Figure 3-7 Loops Formed with Network Elements Figure 3-8 shows the modeling of bondwires in ADS. Inductive coupling is modeled by the inductance matrix L and resistive losses are modeled by a resistance matrix R. Figure 3-8 Modeling of Bondwires in ADS V V Figures 3-6, 3-7, 3-8, 3-9 are used with permission of the author. ADS Documentation help 2006 edition ( License granted to Ericsson) 34 The reason behind using ADS Delft Model instead of HFSS was for consuming time and memory usage in simulations, because the results of both simulations shows us a small difference which can be ignored. In the following this difference will be studied in detail regarding time and mutual inductance values extracted. The Bondwire shape is generated in ADS using five segments coordinates as shown in Figure 3-9. The coordinates can be extracted according to the dimensions of the bondwires inside the package. Figure 3-9 Bondwire Shape in ADS In the following we will study the mutual inductances between one array of bondwire set 4 and one array of bondwire Set 5.The procedure followed will be the same for all the mutual inductances between all the sets of bondwires therefore they will not be discussed in detail and all the results can be found in Appendix B. We have to mention that mutual inductances between bondwire sets 4, 5 and bondwire sets 1, 2 were found so negligible due to a large separation distance between them and will be not included in the final circuit model. 3.4 Results and Discussions 3.4.1 Modeling of Bondwire Set 4 This subsection presents the modeling of one array of bondwire Set 4. Figure 3-10 shows a 3D view of the geometry. In this picture a box of vacuum with ten coupled bondwires inside it is shown, the bottom of the box is a perfect ground plane. The bondwires are from aluminum and they are connected together with a metal plate over a box of vacuum on the both sides. Figure 3-11 shows a close view of the bondwires and the two lumped ports (highlighted) assigned on the side of each box of vacuum. Figure 3-10 HFSS Input Geometry 35 Figure 3-11 Closer view of Bondwire Set 4 The box surrounding the bondwires should be made as large as possible. If the box dimensions are too small, the inductance computed is too low. If the box is made too large the problem cannot be handled by the solver due to limited memory or box resonances may occur. The strategy to follow is to start with a reasonably small box and to increase the dimensions gradually until the computed inductance does not depend on the box dimensions. The metal plate connecting the bondwires together in each side has 4.9x0.2 mm dimensions and 0.147 mm above ground plane and this plate behaves as a capacitor at low frequencies which can be extracted by doing simple simulation for the geometry above without the bondwires. A value of 0.059 pF was found and it is used when extracting the final lumped components model of the bondwires; it should be subtracted from the total capacitance on each side that we get by using the formulas of a RLC pi networks. We have to mention that HFSS does not simulate down to 0 Hz (DC frequencies), but it extrapolate the DC frequencies. The electromagnetic simulation result is imported to ADS as a touchstone and we used it to obtain the RLC values of the lumped model. S-PARAMETERS S_Param SP1 Start=0 GHz Stop=5 GHz Step=0.1 GHz S2P SNP6 File="C:\Bond4\BondwireSet4.s2p" Term Term1 Num=1 Z=50 Ohm 1 2 Ref Term Term2 Num=2 Z=50 Ohm Figure 3-12 Imported HFSS S-Parameters Simulations 36 A 50 ohms termination impedance is used. Table 3.1 shows the extracted value over the whole band of use. Table 3-1 Lumped components values for Bondwire Set 4 L1 is in nH, R1 in ohm and Cshunt, Ctrans in pF. We can see clearly that the current is non uniform distributed inside the bondwires. Figure 3-10 shows the variation of the resistance with frequency. 37 Figure 3-13 Resistance vs. Frequency Using Microsoft Excel we can see this variation in a polynomial equation: R = -2E-40freq^4 + 2E-30freq^3 - 8E-21freq^2 + 2E-11freq + 0.0035 R1 represent the HFSS result, R3 for the final lumped model including skin effect and R4 for the first simple frequency dependent resistance. The inductance is almost constant over the band which verifies that the skin effect gives a negligible impact on inductance value. Figure 3-14Inductance (nH) vs. Frequency Ctrans and Cshunt represent the contact capacitances of the bondwires on the transistor chip and the shunt capacitances sides and they are almost equal and constant over the frequency band, but we should also subtract from them 0.059 pF the value of the capacitance behavior of the two metal plates. 38 Figure 3-15 Capacitance Contacts (pF) vs. Frequency This method in extracting the capacitances is not very efficient and do not give an accurate value but at least it shows that these capacitances are very small and their effect on the total behavior of the package model will be negligible, therefore the accurate computation of the capacitances elements remains a point for future works. One array of bondwire Set 4 is formed of ten parallel bondwires of length 2.043 mm and a radius of 30 μm which give a 0.021 ohm DC resistance for a single Bondwire and 0.00203 ohm for the whole set. The electromagnetic simulation gives us a resistance of 0.0029 ohm at 10 MHz which can be approached at DC level to the value extracted above. As for the AC resistance, at 2.14 GHz (center frequency of interest) the electromagnetic simulation gives a value of 0.021 ohm and the formula used for skin effect resistance gives 0.018 ohm, this small difference is due to the approximation of using ten parallel resistances. The RLC pi circuit can be build having all the needed parameters for the lumped model. Figure 3-16 shows the first approximation circuit with a frequency dependent resistance and Figure 3-17 shows the final circuit of lumped model for one array of bondwire Set 4. Bondw ire Set 4 Term Term3 Num=3 Z=50 Ohm C C1 C=0.059 pF C C2 C=0.165 pF Var Eqn L L1 L=0.19 nH R= Z1P_Eqn Z1P1 Z[1,1]=R C C3 C=0.165 pF C C4 C=0.059 pF Term Term4 Num=4 Z=50 Ohm VAR VAR1 R=(2e-40*pow (freq,4)) - (2e-30*pow (freq,3)) + (6e-21*pow (freq,2)) - (4e-13*(freq)) + 0.0056 Figure 3-16 First Approximation Model 39 Bondw ire Set 4 R R2 R=0.022 Ohm Term Term8 Num=8 Z=50 Ohm C C7 C=0.059 pF C L C6 L3 C=0.166 pF L=0.008 nH R= L L2 L=0.19 nH R= R R1 R=0.00203 Ohm C C5 C=0.165 pF C C8 C=0.059 pF Term Term7 Num=7 Z=50 Ohm Figure 3-17 Final Model of Bondwire Set 4 Comparison Results and Discussions: Figure 3-15 shows the comparison results between the electromagnetic simulations and the lumped model for the bondwires. It’s clearly shown that the S-Parameters are well fitted by the lumped model. Figure 3-18 Comparison Results In HFSS a circle must be approximated by straight segments. In our structure we used a six segments polygon to create the bondwires. To study the influence of the circumference discrimination, the number of segments is increased to ten and the obtained inductance is 0.2015 nH at 2.14 GHz .But when six segments are used, the obtained inductance is 0.201 nH (0.74 % difference). If the number of segments is increased to twenty, the inductance extracted is 0.202 nH (0.1 % difference). It is concluded from these results that the discrimination of six segments is enough to compute the inductance correctly. 40 The influence of the radius of the wire on the inductance is also studied with HFSS. The radius of a bondwire is varied from 25 μm to 35 μm in steps of 1 μm . Figure 3-19 shows the inductance versus the radius at a frequency of 2.14 GHz. The maximum difference occur when the wire radius is 35 μm , then the inductance computed is 0.196 nH, and at 30 μm its 0.201 nH so we have 2.48% difference which is acceptable. It is concluded that if our measurement for the radius values of the bondwires was not so accurate this difference will slightly influence the inductance computed. The effect on the other parameters of the lumped circuit was not taken in consideration because it is so negligible and approximately has no influence. Figure 3-19 Inductance vs. radius at 2.14 GHz The work done for a single bondwires Set 4 is similar for all the rest of the bondwires and all the results extracted can be found in Appendix A with the HFSS implementation and the appropriate lumped model for each set of the bondwires. 3.4.2 Bondwire Set 4, 5 Mutual Inductances Bondwire set 4 and Bondwire set 5 on the same transistor chip are the closest sets inside the package. Figure 3-20 Bondwire Set 4 and Set 5 41 Figure 3-21 shows how the model is implemented in ADS and Figure 3-22 shows the layout generated from the circuit. BONDW_Usershape Shape1 X_1=0 um Z_4=503 um X_2=1397 um Z_5=503 um X_3=1598 um Z_6=503 um X_4=1699 um X_5=1800 um X_6=2680 um Y_1=0 um Y_2=0 um Y_3=0 um Y_4=0 um Y_5=0 um Y_6=0 um Z_1=0 um Z_2=503 um Z_3=503 um 1 Term Term1 Num=1 Z=50 Ohm 2 3 4 5 6 7 8 9 10 Term Term2 Num=2 Z=50 Ohm 11 12 13 14 BONDW_Usershape Shape2 X_1=0 um Z_4=790 um X_2=113 um Z_5=540 um X_3=241 um Z_6=0 um X_4=363 um X_5=766 um X_6=1137 um Y_1=0 um Y_2=0 um Y_3=0 um Y_4=0 um Y_5=0 um Y_6=0 um Z_1=0 um Z_2=537 um Z_3=729 um 15 16 S-PARAMETERS 17 18 S_Param SP1 Start=0.1 GHz Stop=5 GHz Step=0.1 GHz 19 BONDW19 WIRESET1 Figure 3-21 ADS Implementation Figure 3-22 Layout Generated To extract the mutual inductance between the two sets from the circuit above the following formula was used: ⎛ Z12 ⎞ M = 1e12 * im⎜ ⎟ (pH) ⎝ 2*π*f ⎠ (7) Where Z12 is the impedance between port 1 and port 2. Table 3.2 shows the mutual inductance between Bondwire Set 4 and Bondwire Set 5 connected to the same transistor chip. 42 freq 100.0 MHz 200.0 MHz 300.0 MHz 400.0 MHz 500.0 MHz 600.0 MHz 700.0 MHz 800.0 MHz 900.0 MHz 1.000 GHz 1.100 GHz 1.200 GHz 1.300 GHz 1.400 GHz 1.500 GHz 1.600 GHz 1.700 GHz 1.800 GHz 1.900 GHz 2.000 GHz 2.100 GHz 2.200 GHz 2.300 GHz 2.400 GHz M 37.971 37.971 37.970 37.970 37.970 37.970 37.970 37.970 37.970 37.970 37.970 37.970 37.970 37.970 37.970 37.970 37.970 37.970 37.970 37.970 37.970 37.970 37.970 37.970 Table 3-2 Mutual Inductance between Bondwire Set 4 and Bondwire Set 5 connected to the same transistor chip As a test of accuracy of the delft model for this case, a test simulation by HFSS was performed and it gave a value of 44 pH. The difference from Delft Model will be then 6 pH. Using HFSS will lead us to more accurate results but also additional time and memory usage in simulations, therefore ADS Delft Model was used to extract these values and this slight difference between the two results can be approached by doing simple tuning on the final circuit model. 3.4.3 Modeling of Prematch Capacitors The MRF6S21140H transistor package includes six prematch capacitors, three on the drain side and three on the gate side. These capacitors were modeled, measured [12] and found to have values of 200 pF for the drain side capacitors and 22 pF for the gate side capacitors. These two values will be used as simple lumped capacitors in the final circuit model of the package, but in HFSS we will create two models that have the same behavior of simple 200 and 22 pF capacitors. A top view photo of a single transistor chip with two prematch capacitors is shown in Figure 3-23. The one on the drain side has a length of approximately 5.35 mm, a width of 0.752 mm, a height of 0.147 mm and a 0.45 mm distance from the transistor chip. The one on the gate side has a length of approximately 5.35 mm, a width of 0.61 mm, a height of 0.147 mm and a 0.62 mm distance from the transistor chip. 43 Figure 3-23 Top view of the Transistor Prematch Capacitors The prematch capacitor consists of three layers, one metal layer at the bottom, a silicon dioxide Si O 2 layer in the middle and a metal plate on the top. Figure 3-24 shows a schematic cross section of a prematch capacitor with a high h for the Si O 2 layer. This thickness will be tuned so that this geometry will have the same behavior for a single capacitor of value 200 pF and then 22 pF. Figure 3-24 Schematic view of a Prematch Capacitor cross section Figure 3-25 show the geometry implementation in HFSS. It includes the prematch capacitor inside a box of vacuum with two wave ports on the sides. 44 Figure 3-25 HFSS implementation of a Prematch Capacitor For the drain side prematch capacitor with a 0.752 mm width, to obtain the same behavior as a 200 pF we should have a thickness h equal to 0.71 μm . Figure 3-26 shows the value of the capacitance extracted from the simulation and it is clearly seen that we have a constant value over the frequency. Figure 3-26 Capacitance value extracted for the drain side capacitor As for the gate side capacitor with a 0.61 mm width, the value of the height obtained was 5.25 μm for the height h. Figure 3-27 shows the capacitance extracted from the simulation. 45 Figure 3-27 Capacitance value extracted for the gate side capacitor 3.4.4 Modeling of Package Leads The drain and gate lead in the MRF6S21140H package are similar. They are formed by a copper plate that has an 18.3 mm length, 1.5 mm width and 0.12 mm height. This copper plate is placed over a substrate of 0.52 mm height and has a dielectric constant of material ε r = 9 [12]. The dimensions of this lead are too big that for higher frequencies, it must be treated as circuit of distributed elements. First we will simulate the lead with one input port and a single output port in HFSS and in Momentum (ADS). Then we will compare the result to a simple circuit model composed from an inductance in series with a resistance and a shunt capacitance. The values of these lumped components were extracted from the formulas of parameters of a parallel plate above ground plane (Appendix E). Having all these parameters, the following equivalent circuit values were computed: C= 3.64 pF L= 0.061 nH R= 2 mΩ at 2.14 GHz Figure 3.28 shows the equivalent circuit in ADS, and Figure 3-29 the comparison between HFSS, Momentum and the lumped circuit regarding S11, S22 and S12 parameter. 46 Term Term1 Num=1 Z=50 Ohm L L13 L=0.061 nH R= R R14 R=2 mOhm C C17 C=3.64 pF Term Term2 Num=2 Z=50 Ohm Figure 3-28 Equivalent Lumped circuit Figure 3-29 Comparison Results-S11 Now the lead package will be simulated including four ports, one input port and three internal ports from the lead to the three transistors chips. Figure 3-30 shows the geometry of the lead package with four ports, one input port represented by a wave port, and three internal ports represented by lumped ports. Mention that all the ports are renormalized to 50 ohms. The lumped ports are placed related to the position of the bondwires connected to the lead. Figure 3-30 Geometry of the lead package in HFSS 47 To find a lumped circuit that has the same behavior of the geometry above, we divided the package lead into four parts as in Figure 3-31, then for each part we found a lumped circuit by the same method that we used to find a model for the whole package with two ports. Then we connect all the four circuits together to have a first lumped model of the whole package lead. This model is not the final circuit but it gives us a starting point to begin tuning its parameters to fit the electromagnetic simulation in means of S-parameters. The final circuit is shown in Figure 3-32. Figure 3-31 Partition of the lead package R R9 R=3 mOhm Var Eqn L L9 L=Lp pH {-t} R= C C17 C=Cp pF {-t} Term Term3 Num=3 Z=50 Ohm VAR VAR1 Cp=0.513 {-t} Lp=84.88 {-t} Term L R Term1 R7 Num=1 L7 L=32.95 pH {-t} R=1.5 mOhm Z=50 Ohm R= C C15 C=1.7 pF {t} L R L8 R8 R=1.5 mOhm L=107.8205 pH {-t} R= R R11 R=3 mOhm L L11 L=Lp pH {-t} R= C C16 C=1.083 pF {-t} C C19 C=Cp pF {-t} Term Term2 Num=2 Z=50 Ohm Term Term4 Num=4 Z=50 Ohm Figure 3-32 Final circuit for the gate and drain lead package Note that the total capacitance in the model above is approximately equal to the capacitance of the model of a single capacitance. 48 In the following comparison results between HFSS simulations and lumped model are shown: 49 Figure 3-33 Comparison Results 50 It is clearly seen the good fit between electromagnetic and lumped circuit model. Figure 3-34 shows how the lumped model can predicts almost the same difference between the input port and the output center and side ports. This figure revels that the signal is not uniformly distributed, even if the difference is small, to the three chips. In the next chapters we will study these non-uniform distributing and see how it is affecting the total behavior of the transistor with respect to output power and efficiency. Figure 3-34 Difference between the input port and the output center and side ports The MRF6S2140H package also contains a prematch capacitor on the gate side between the gate lead and the three shunt capacitors before the transistor. This prematch capacitor is a copper plate (20 mmx3 mm) over a substrate of dielectric constant ε r = 9 and a height of 0.49 mm. Figure 3-35 Gate prematch capacitor 51 The same technique in modeling the lead package was followed here in modeling the gate prematch capacitor. First electromagnetic simulations were done in HFSS, and then find a lumped model that fits the simulations results in terms of S-Parameters. As seen from figure 3-35 we have six sets of bondwires connected to this prematch capacitor which implies six internal ports. Figure 3-36 shows how the geometry was implemented in HFSS with six internal lumped ports. Figure 3-36 Gate prematch capacitor geometry in HFSS To find the lumped model the copper plate was divided into six parts and for each part we found a lumped model of an inductance in series with a resistance and a shunt capacitance. Then the six sub models were connected together to obtain the full circuit, and after tuning the parameters of the whole circuit to fit the electromagnetic simulation a final model was found and shown in Figure 3.37. Term Term9 Num=9 Z=50 Ohm C R C4 C=1.7716R5 pF {t} R=2.11 mOhm {-t} Term Term7 Num=7 Z=50 Ohm C R C14 C=1.64 pF R7 R=0.0076 mOhm Term Term11 Num=11 Z=50 Ohm L L5 L=0.87520056 nH {t} R= C R C6 R6{t} C=1.7716 pF R=2.11 mOhm {-t} L L7 L=0.137 nH R= L L6 L=0.87520056 nH {t} R= R R8 R=2.11 mOhm {-t} R R2 R=0.0076 mOhm C C12 C=1.7716 pF {t} L L8 L=0.87520056 nH {t} R= L L2 L=0.137 nH R= R L R9 L9 R=2.11 mOhm {-t}L=0.87520056 nH {t} R= C C3 C=1.64 pF C C13 C=1.7716 pF {t} Figure 3-37 Lumped model of the gate prematch capacitor The comparison results are shown below. 52 Term Term10 Num=10 Z=50 Ohm Term Term8 Num=8 Z=50 Ohm Term Term12 Num=12 Z=50 Ohm Figure 3-38 Comparison Results Figure 3-38 shows a good fit between the lumped model and the electromagnetic simulation up to 5 GHz. A difference less then 10% is presented. 53 The lumped model found also has a good prediction for the difference between the center port and the side ports. Figure 3-39 shows the comparison between the center port and the side ports both in HFSS and ADS, also this difference reveal that the signal is not uniformly distributed inside the prematch capacitor. Figure 3-39 Difference between the center port and the side ports 3.4.5 Modeling for a Prematch Single Chip Circuitry After finding a lumped circuit for each component inside the transistor (Bondwires, leads, prematch capacitors), all the circuits will be connected together to form the full lumped model of the package. Electromagnetic simulation will also be considered for the unmodified three transistor chips and for the transistor modified to single chip. The transistor modified to a single chip is obtained by cutting all the bondwires to the outer chips, the simulations of this transistor were done for both the drain and gate side separately, later we complement the full package by considering the mutual gate-drain sides coupling. Figure 3-40 shows the single chip drain model geometry in HFSS with two excitations, one wave port at the drain lead and one lumped port at the contact between the transistor chip and the bondwires. 54 Figure 3-40 Single chip Drain Model in HFSS The transistor chip is not modeled in the geometry above and it was replaced by a single metal plate that connects all the bondwires together. The lumped model is shown in the figure below with a capacitance of 0.059 pF representing the metal plate connected to port number four. The drain lead was represented by a single capacitance model because here we have a single connection to the transistor chip. Mention that the inductance of Bondwire 4 was slightly decreased from the value found before to have a good fitting. 1 2 Term Term6 Num=6 Z=50 Ohm Ref S2P SNP1 Term Term5 Num=5 Z=50 Ohm Figure 3-41 HFSS Result exported to ADS R R13 R=0.032 Ohm Bondwire 5 Term Term3 Num=3 Z=50 Ohm L R L13 R14 L=0.061 nH R=2 mOhm R= C C17 C=3.643 pF C L C15 L14 C=0.118 pF L=0.325 nH R= R R12 R=0.00266 Ohm L L12 L=0.008 nH R= C C16 C=0.223 pF C C22 C=0.059 pF MUTIND Mutual Mutual2 K= M=44 pH {t} Inductor1="L14" Inductor2="L16" C C20 C=200 pF R R17 R=2 mOhm L R L16 C R15 C19 R=0.00203 OhmL=0.175 nH R= C=0.166 pF R R16 R=0.03 Ohm L L15 L=0.01 nH R= C C21 C=0.166 pF Bondwire 4 Figure 3-42 Equivalent Lumped circuit for a Single chip Drain Model A good fit was found between the two models as shown in figure 3-43 55 Term Term4 Num=4 Z=50 Ohm Figure 3-43 Comparison Results for a Single Chip Drain Circuit Gate equivalent circuit for single chip was also found. Figure 3-44 shows the geometry implemented in HFSS with two excitations, one wave port at the gate lead and one lumped port at the contact between the transistor chip and the bondwires. Figure 3-44 Single chip Gate Model in HFSS Figure 3-45 shows the equivalent lumped circuit, the fit was done using the tuned values as compared to fits to EM simulations of separate components. Mutual inductance between bondwire set 3 and bondwire set 1 was not introduced because it’s negligible and has almost no effect on the circuit behavior. 56 Figure 3-45 Equivalent Lumped circuit for a Single chip Gate Model Figure 3-46 Comparison Results for a Single Chip Gate Circuit 57 3.4.6 Modeling for the Prematch Full Package Circuitry In this section the full package modeling on the drain and gate is discussed separately. The full drain model in HFSS is shown in Figure 3-47. The excitations were assigned as for a single chip but here we have three internal lumped ports at the three transistor chips. The equivalent lumped circuit is shown in figure 3-49 with the port number shown below each port. The fit was done using little bit tuned component values as compared to fits to electromagnetic simulations of separate components. The inductance of bondwire 4 was slightly decreased and the mutual inductances between the bondwires were slightly increased from the values found with Delft Model, and all this tuning was done to find a good fitting between the two simulations. Figure 3-47 Full Drain Geometry Term Term6 Num=6 Z=50 Ohm 4 1 Term Term5 Num=5 Z=50 Ohm 2 3 Ref S4P SNP1 Term Term7 Num=7 Z=50 Ohm Term Term8 Num=8 Z=50 Ohm Figure 3-48 HFSS Result exported to ADS Comparison results between the different ports are shown below. 58 P1 P4 P3 P2 Figure 3-49 Equivalent Lumped Model 59 60 Figure 3-50 Comparison Results for a Full Drain Circuit The comparison results show a good fit between the electromagnetic and lumped simulation especially in the band of interest (2110-2170 MHz). The difference at the resonance frequency 0.5 GHz especially between S (2, 2)-S (6, 6) and S (3, 3)-S (7, 7) is due to an inaccuracy in estimating the loss in the circuit at this frequency. And the reason behind that is probably some approximations made for the nature of some materials inside the transistor (Prematch capacitors layers, Substrate below the leads package) and also some inaccuracy in estimating the skin effect resistances in the bondwires. Figure 3-51 shows the difference between centre and outer chips. It is seen from Figure 351(a) that the difference in magnitude between the signal passing to centre chip and the signal passing to the side chips is small, and later in the following chapters we will discuss this difference and see how it is affecting the behavior of the transistor. 61 Figure 3-51 Difference between centre and outer chips The full gate model in HFSS is shown in Figure 3-52. The excitations were assigned as for a single chip but here we have three internal lumped ports at the three transistor dielectrics. The equivalent lumped circuit is shown in figure 3-53. The fit was approximately done using the component values as compared to fits to electromagnetic simulations of separate components (Appendix A). The mutual inductances between the bondwires were slightly increased from the values found with Delft Model (Appendix B), also mutual inductance between Bondwire 3 and Bondwire 1 were not introduced because of its small value that will not affect the overall behavior of the transistor. Figure 3-52 Full Gate Geometry 62 Figure 3-53 Equivalent Lumped Model The comparison results show a good fit between the electromagnetic and lumped simulation especially in the band of interest (2110-2170 MHz). Figure 3-55 shows the difference between centre and outer chips in HFSS and ADS, and it is clearly seen from the simulations that at the gate side there is a slightly difference between center chip and outer chips. Figure 3-54 Comparison Results for a Full Drain Circuit 63 Figure 3-55 Difference between centre and outer chips Finally the gate side and the drain side were assembled together; the electromagnetic geometry is shown in figure 3-56 with eight excitations, two wave ports at the input and output of the transistor package, and six internal lumped ports representing the contact with the three transistor chips. The transistor chips were modeled as a single metal plate connecting the bondwires together separately one on the drain side and another on the gate side and respectively for the three chips 64 Figure 3-56 Full package model The simulation for the full package model took over twenty six hours in real time and twenty four hours in CPU time. The time for simulation could be reduced if we cut the geometry of the full package in half and assign a symmetry boundary, but as HFSS beginners we decided to make the full simulation in order to avoid any confusion or miscalculation. The lumped model for the whole package is the same as combining the circuit model of the gate and drain side separately but with including the mutual inductances between the bondwires on the same transistor chip at the gate and at the drain found before (3.3.6). Mutual inductances between drain and gate on different chips were found negligible and thus they will be not taken in effect (See Appendix B). 3.5 Conclusion In this chapter, a modeling technique has been introduced and used for modeling the fullwave electromagnetic behavior of MRF6S21140H power transistor package. The resulting equivalent circuit model, which is related to the physical characteristics of the package construction, can be directly inserted into a circuit simulator. It has been demonstrated that the package models play an important role in accurate simulation of the packaged transistor performance. Over a two hundred simulations were done on all the parts of the package. The bond wire inductance value depends on its geometry and it is common for circuit designers to select 65 bondwire’s geometry by trial, which results in a time consuming process. With capability of modeling bond wire inductance accurately, the bond wire shape can be properly selected to realize the desired inductance for the matching circuit. This will allow for firstpass design success on the internal matching circuit. The shunt prematch capacitors were modeled as a single capacitor and the package leads and gate second prematch capacitor were modeled as RLC circuits because of their large sizes. A more accurate model can be extracted if the physical dimensions of the components inside the package were accurately measured in addition of knowing the real characteristics of all the materials that form these components. Finally given the knowledge of the dominating electromagnetic properties of the package obtained in this chapter, it may be helpful for equivalent circuit modeling, PA design, and also for understanding results obtained from measurements. 66 Chapter 4 Design of Class B Power Amplifier Using Modeled Transistor 4.1. Introduction As we have seen in chapter 3, package of MRF6S21140H3 high power transistor was modeled in HFSS and its lumped model was built in ADS. Both models showed consistent results. What has been done so far is the electromagnetic modeling for the package only. This electromagnetic modeling of the package will be combined with an existing very simple die model to obtain a full transistor model, and later apply this transistor model in the design of a power amplifier, study the non-uniform distribution of current and power over chips and estimate how the non-ideal parallel connection degrades output power and efficiency. 4.2. DC simulation and I-V curves The first step of the design is to estimate the I-V characteristics. The DC simulation was performed to depict the input/output I-V transfer characteristics. The I-V curves help us to see, for example, the operation region of the transistor, the maximum drain current, threshold voltage, knee region, etc…Firstly, the DC simulation was performed without the package model, i.e. with the die only. The model of the die consists of the drain-source capacitances and resistances, and the gate-source capacitances and resistances modeled as polynomial equations of different parameters, and the drain source current generator [10]. The built up circuit for DC simulation is shown in figure 4.1. Figure 4-1 DC Simulation setup: The die model consists of drain-source capacitance C5, drain source resistance, R5, gate source capacitance C4, gate source resistance R4, and Drain Source Current Generator SDD2P 67 4.2.1. Results and Discussion For our modeled transistor, Vg= [0-7 V] and Vd= [0-56 V] are swept and the results of the simulation are presented in figure 4.2. Figure 4-2 I-V characteristics As we see from the results, the gate threshold voltage is VgThreshold = 3.6 V; As the MRF6S21140H3 delivers 140 watts for three chips, hence the power per one chip would be 47 watts as approximation. The very highest output power is obtained when the drain current I d is equal to the maximum allowed peak drain current for the transistor I dmax . The supply voltage Vsupply has a value of 28 V, which implies that the maximum instantaneous drain-source voltage of the transistor Vdmax is 56 V. Hence the maximum RF power is equal to: PRFmax = Vdmax * I dmax ; 8 From the equations, the maximum drain current for an ideal model can be found as follows: I dmax = 8 * 68 PRFmax P 47 47 = 4 * RFmax = 8 * = 4* = 6.7A ; Vdmax Vsupply 56 28 The maximum instantaneous drain-source voltage Vdmax is Vsupply + Vload , so the transistor needs a breakdown voltage greater than Vdmax = 2 * Vsupply , and the optimum intrinsic impedance is calculated using equation 1 as follows: R opt = 4.3. (Vdmax − Vknee ) (56 − 1.5)V = = 8.1Ω ; I dmax 6.7A Design of a single chip class B power amplifier The full transistor modified to keep only single transistor chip is applied in the design of a one chip class B power amplifier in order to compute the suitable load impedance. Input and output matching networks have to be built to match the gate and the drain side respectively. The single chip power amplifier consists of the transistor die connected on the left to the gate circuit and input matching network, and on the right to the drain circuit and output matching network. The gate side contains the input gate lead combined with bondwires set1, 2, and 3, connected to the pre-match capacitor. The drain side contains the bondwires set 4 and 5 connected to the output drain lead. Figure 4.3 shows the simulation setup of a single chip power amplifier and an estimation of the load resistance. Figure 4-3 A single chip class B power amplifier 69 4.3.1 Results and Discussion The input matching network consists of a capacitor of 1μF, a matching reactance, and an inductance of 1 μH connected to gate voltage of 3.6 V. The output matching network consists of capacitor of 1 μF, and a series matching reactance. The capacitors of 1 μF at the input and at the output behave as short circuit for RF frequencies and an open circuit for DC. The inductances of 1 μH behave as short circuit for DC and an open circuit for RF frequencies. The goal of designing the output matching network is to provide proper transformation of impedance between power amplifier and load in order to achieve maximum output power. Therefore the output matching network must translate the external load impedance to the value R opt as seen by intrinsic drain. The load resistance that intrinsic drain should see in order to actually utilize the full voltage swing for the maximum power in order to get highest efficiency as possible is the optimal load resistance, R opt .The input power, the input and output matching networks, and the load impedance were tuned in order to maintain the maximum output power and as high efficiency as possible. Some results of simulations are presented in figure 4.4. Figure 4-4 Some significant results of simulations 70 Here, the drain current and drain voltage waveforms are plotted. The load lines are also drawn and as we see from the results, they show consistent results with the current waveform. The dip in the current represents so called a hook in the load lines where the current started to depreciate because of very small instantaneous drain-source voltage until a certain level, and then increased back to the maximum. The output power for a single chip power amplifier is about 49.1 watts. However, this power corresponds to a drain peak current of 9.4A approximately. While as mentioned earlier the transistor MRFS21140H is capable of delivering 140 watts for three chips, which means about 47 watts for a single chip, and that shows that 6.7 A is a good approximation obtained from assuming an ideal class B power amplifier. As for the intrinsic drain impedance, in an ideal class B amplifier, its value was 8.1ohms. The value that we have got from the simulation was (6.3+j*1.7) ohms. So for R opt , the tuning optimization of the simulation gives rather close to that of the ideal model. The output power from the intrinsic transistor, the transistor die, and from the whole power amplifier was calculated. As we see from the results in figure 4.4, the output power from the intrinsic transistor is 58.5 watts, and the output power from the transistor die is 54.8 watts, while the output power of the whole power amplifier is 49.1 watts. This shows how parts of the output power are lost in the output network. The power loss is about 9.4 watts where the drain source resistance takes a large part of this loss. As for the efficiency, the value of 77.8 % for the intrinsic transistor is very close to the ideal value π/4. The value of 65.2 % for the whole power amplifier is considered acceptable despite the non negligible losses in the output network. The results above were obtained after tuning some of the parameters especially the load resistance which after tuning was estimated to have a value of 6.5 Ohms. Another figure of merit to see is the behavior of the efficiency and the output power versus the drain voltage, i.e. sweeping the fundamental RF drain voltage amplitude. This is shown in figure 4.5. Figure 4-5 Efficiency and Output Power versus swept drain voltage 71 4.4. Current Distribution on three chips Class B Power Amplifier 4.4.1. Design of Three chips Class B Power Amplifier The next step is to design class B power amplifier using the full three chips modeled transistor and investigate the signal distribution between the three transistor chips by comparing the drain currents and voltages on the three chips. The three chips class B power amplifier consists of the three transistor chips connected in parallel on the gate and drain side combined with the input and output matching networks Figure 4.6 shows the design setup of a three chips power amplifier. Figure 4-6 A three chips class B power Amplifier 4.4.2. Results and Discussion X2 represents the full gate model which includes the input gate lead, bondwires set 1, the gate pre-match capacitor, bondwires set 2, and bondwires set 3. X1 represents the full drain model which includes bondwires set 4 and 5, and output drain lead. IDS, IDS1, and 72 IDS2 are the intrinsic drain current for the three chips, while Vdout, Vdout1, and Vdout2 are the intrinsic drain voltages for the three chips. Z1P5 and Z1P4 are matching reactance at the input and at the output respectively. Figure 4.7 shows the results of simulation. Figure 4-7 Some significant results of simulation The current and voltages in figure 4.6 are the average values of current and voltage over the three chips. Again we see the consistency between the current waveform and the load lines. In the design of a single chip class B power amplifier, the load impedance was tuned to obtain an output power of 49.1 watts, which then gave an efficiency of 65.2%. In the design of a three chips class B power amplifier, by further tuning, and dividing the load by 3 for parallel connection of transistors, we have got triple output power and almost same efficiency. These results can be seen in figure 4.6, where the efficiency obtained was 65.8 % and output power was almost triple (49.1*3=147.3 watts) while the value obtained was 146.3 watts. The efficiency and output power versus swept fundamental RF drain voltage amplitude are shown in figure 4.7. Dividing the intrinsic load impedance obtained for a single chip power amplifier by 3, 73 (6.3+j*1.7)/3= (2.1+j*0.5) ohms gives close value to the one obtained for three chips power amplifier (1.9+j*0.5) ohms. It is important to mention that the power loss is about 27.5 watts, and that is due to the existence of many resistive elements in the circuit especially the drain source resistance that contributes in a large part of this loss, and due to high skin effect at the gate and drain side, which as mentioned earlier, would be an interesting point for future work. We can also see from the calculated output power of the intrinsic transistor, the transistor die, and the whole power amplifier, how some parts of the output power are lost in the output network. Figure 4-8 Efficiency and Output Power versus swept drain voltage 4.4.3. Current and Voltage Distribution on the Three Chips As we have three transistor chips connected in parallel, it is important to see the distribution of the currents and voltages between the three chips. Figure 4.9 shows the drain currents and drain voltages for the centre and outer chips. Figure 4-9 Drain current and voltage distribution between the three chips 74 4.5. Conclusion In figure 4.6, the average drain current and average drain voltages of the three chips are plotted. In the modeling of the package of the transistor, it was proved that the signal distribution between the three chips is slightly not uniformly distributed. Here, in the design of three chips class B power amplifier, and despite that the difference is slightly small (figure 4.8), we still can say that the current is slightly not uniformly distributed between the three chips due to the non ideality in the parallel connections of the transistors. As we have the symmetry between the outer chips for the model, we do have the symmetry for the three chips power amplifier where the difference in the drain currents and drain voltages in quiet negligible compare to the difference in the drain current and voltage between the center and outer chips. Figure 4.8 proves that the degradation of the efficiency and output power is almost negligible. The difference between drain currents IDS1 and IDS2 is simply a numerical inaccuracy, while the much larger difference to IDS is physical mainly due to the mutual inductances between the different set of bondwires especially on the drain side where the drain bondwires set 4 and set 5 are close in distance and this gives rise to higher mutual coupling. The results of simulation obtained in figure 4-4 and 4-7 are compromise results between different parameters such as output power, efficiency, etc…These results therefore are not very accurate. In addition to that, the accuracy of the modeled transistor is hard to estimate which leaves it as a point to consider in the future. 75 Chapter 5 5.1. off Chip Connection: Design of Output PCB Introduction In this chapter, off chip connection is studied through the design of the Printed circuit Board (PCB). In section 5.2, output PCB at the drain connection is designed. We have also investigated the relation of the output port at the DC block capacitor with respect to its position on the PCB. Crowding effect for PCB traces is explained and later in section 5.3 we have studied the signal distribution between the center and outer chips of the drain circuit combined with the equivalent model of PCB. In section 5.4, we have designed a three chips class B power amplifier combined with the modeled PCB and studied the current distribution between the three chips including the simulations of PCB with different positions of the output port. 5.2. Design of Output PCB 5.2.1. Realization HFSS was used to build the geometry of the output PCB. The PCB geometry consists of the output drain lead connected to an extended drain lead of length 12.12 mm and copper thickness of 0.12 mm, where it is connected to a copper quarter wavelength line of characteristic impedance of 19.6 ohms for isolating the drain power supply connection for RF. The drain lead extension and the quarter wavelength are lying on a substrate of dielectric constant, ε r = 4 The package part of drain lead consists of copper plate of 0.12mm height over a substrate of dielectric constant, ε r = 9 and of 0.52 mm height [12]. The quarter wavelength is short circuited at RF and kept at DC. The way to short circuit the quarter wavelength in HFSS is simply done by introducing a metal plate of finite conductivity drawn vertically from the edge of the quarter wavelength to be connected to ground plane or from the ground plane up to the edge of the quarter wavelength. The PCB plus the transistor package drain lead model is connected by four ports. A lumped port is placed at the output to connect the external load. This is drawn from the ground plane upward to the edge of the substrate of dielectric constant ε r = 4 . Three lumped ports are used to connect the drain lead to the arrays of bondwires set 5. These ports are drawn from ground plane upward to the edge of the drain lead. A lumped port is placed at the output position of the DC block capacitor to connect the external load and has a width of 2.6 mm and height of 0.52 mm. To assign the port 76 correctly, the characteristics impedance has to be found. The characteristic impedance of 85 ohms that corresponds for a width of 2.6 and for a dielectric constant ε r = 4 was found. While the three lumped ports at the drain lead have an equal width of 4.6 mm which corresponds to 49 ohms impedance for a dielectric constant ε r = 9 [21].Figure 5.1 shows the HFSS geometry of PCB and dimensions of different components of the structure Figure 5-1 HFSS Model of PCB The S-parameters of the HFSS simulation are exported to ADS as shown in figure 5.2. Figure 5-2 Exported S-parameters from HFSS 77 5.2.2. Investigation of the position of the output Port Port 1 relates the PCB output connection to the external load, and ports 2, 3, and 4 relate the connection at the drain lead to the drain bondwires set 5. The position of port 1 is investigated in order to examine whether it is of high sensitivity and how it can affect the results. We have chosen three positions: center, right, and left as seen in figure 5.3. These ports can be related to the quarter wavelength, which is connected in a way to isolate the drain power supply connection for RF, through their positions on the PCB, i.e. distance from each port to the quarter wavelength. This affect will be clearly seen in the design of three chips power amplifier in chapter 5.4. Figure 5-3 Positioning of port 1: Center, right, and left. The S-parameters of the HFSS simulation in the three cases are exported to ADS as shown in figure 5.4 and the results of simulation are shown in figure 5.5 where the difference in the S-parameters in the three cases can be considered as negligible. 78 Figure 5-4 S-parameters exported to ADS 79 Figure 5-5 Comparison results at different ports As the HFSS results show, the difference between different positions of lumped port 1 on the PCB is almost negligible. From this, we can conclude that the position of port 1 that connects the output to the external load is of only slight importance and can be considered least sensitive. But further investigation for examining this sensitivity may be done. 5.2.3. Comparison between wave and lumped ports for the PCB design The electromagnetic model of the PCB shown in figure 5.1 was simulated using a lumped port at the output to connect the external lead, and three other lumped ports at the drain lead. However, assigning a wave port at the output could be possible. The electromagnetic model of the PCB using a wave port and the comparison results with the PCB simulation using lumped port is shown in Appendix C. 5.2.4. Crowding effect The crowding effect does play a role in determining the patterns of current flow and therefore the attenuation and characteristic impedance) of micro strip and strip line transmission lines. The crowding effect for PCB traces takes hold at rather low frequencies on the order of a few Megahertz. Below that frequency the magnetic 80 forces due to changing currents in the traces are too small to influence the patterns of current flow. At low frequencies current in a PCB follows the path of least resistance. The path of least resistance for current flowing in a PCB trace fills the volume of the trace, flowing uniformly throughout the conductor. The path of least resistance for that same current as it returns to its source through the power and/or ground planes spreads out in a wide, flat sheet, tending to occupy as much of the surface area of the planes as possible on its way back to the source. That's the least resistance path. Above a few Megahertz, the magnetic forces become very significant, and the current flow patterns change. Above a few Megahertz the inductance of the traces and planes becomes vastly more important than their resistance, and current flows in the least inductance pathway. , The line resistance and inductance show a dependence on frequency due to non-uniform current density in the conductor, additionally to the skin depth effect. The metal resistance rises rapidly with increasing frequency while line inductance is less sensitive to the current crowding effect. The magnetic field generated by neighboring lines changes the current distribution and results in a higher current density at the edges of the metal lines. Current at high frequencies distributes itself to neutralize all internal magnetic forces, which would otherwise shift the patterns of current flow. In our PCB model, a typical 85 ohms micro strip configuration is considered. We will see that at high frequencies the current distributed fairly uniformly around the circumference of a signal-carrying PCB trace, with slightly more current flowing on the side near the reference plane, and slightly less on the back side. The increase in resistance due to this effect (above and beyond simple consideration of the skin depth and trace circumference assuming a uniform current distribution) is on the order of about 30 percent, a percentage that remains fixed as function of frequency. The electromagnetic visualization in ADS is used to generate the current distribution for the PCB. This is done by generating the PCB layout in momentum, and then running the electromagnetic visualization for the design to plot the currents. Figure 5.6 shows how current is distributed on the PCB. Figure 5-6 Current distribution on the PCB 81 5.3. Realization of PCB and the drain model The next step is to connect the output PCB to the drain circuit and see the simulations results and investigate the signal distribution between the three chips in HFSS and ADS respectively. Figure 5.7 shows the lumped model of drain circuit combined with PCB. Figure 5-7 Lumped model 82 The lumped model simply connects the lumped model of the drain circuit to the electromagnetic model of the PCB. We have also found an electromagnetic model for the whole drain circuit using HFSS as shown in figure 5.8. Figure 5-8 HFSS model 5.3.1. Results and Discussion The drain circuit contains the drain bondwires set4 and set5 that connect the transistor chip to the shunt capacitor on the drain side and to the drain lead respectively. The lumped port at the output is drawn from the ground plane upward to the edge of the substrate of dielectric constant, ε r = 4 while the three lumped ports at the transistor chip are drawn from the ground plane upward to the edge of the transistor chip. The metal plate connected to ground plane to short-circuit the quarter wavelength at RF is drawn from the edge of the quarter wavelength downward to the infinite ground plane. The S-parameters of the HFSS simulation of PCB are exported to ADS as a touchstone file and is connected to the drain circuit. Term 1 or Port 1 corresponds to the port that has the same width as the DC block capacitor to connect the external load, and term 2, 3, and 4 or port 2, 3, and 4 are the ports at the transistor chip. The S-parameters of the HFSS simulation of the model in figure 5.7 are exported to ADS as a touchstone file. Figure 5.9 shows the difference in the S-parameters between the center and outer chips, while figure 5.10 shows the same difference in HFSS, and figure 5.11 shows the comparisons in the Sparameters of the center and outer chips in HFSS and ADS. 83 Figure 5-9 Difference between the three chips for lumped model Figure 5-10 Difference between the three chips for electromagnetic model 84 Figure 5-11 Difference for the three chips between electromagnetic and lumped model 5.3.2. Conclusion For the lumped and electromagnetic model of drain circuit including the PCB, the difference between the center and outer chips is very small and we can see that both the lumped model and the electromagnetic model can depict almost the same difference. While comparing the lumped model with the electromagnetic model, the difference is rather small. The drain circuit was modeled in HFSS and its equivalent lumped model was built in ADS and both models show consistent results as we have seen in chapter three. Also the results obtained from the PCB model were very reasonable and we have proved that the sensitivity of the position of the port at the output DC block capacitor is rather small. However, more investigation can be done to study this difference. One way to do the investigation is by including the DC block capacitor at the output port. What also could be done for further investigation is the following. In the HFSS model, we have assigned four ports, one at position of the output DC block capacitor to connect to the external load, and three ports at the transistor chips. However, assigning a fifth port at the quarter wavelength can be considered, but this makes the simulations more complex and time consuming which can be proposed for future work. Another difficulty is that HFSS can not simulate all way down to 0 Hz, so it would be difficult to actually simulate the DCfeed through this port. 85 5.4. Design of Three Chips Class B Power Amplifier combined with modeled PCB This section includes the design of a three chips power amplifier with the output drain PCB connection. The whole power amplifier contains the modeled package combined with the die to obtain a full transistor model and the output PCB. Input and output matching networks are included at the gate and drain side. The whole power amplifier is shown in figure 5.12. Figure 5-12 A complete class B Power Amplifier 86 5.4.1. Results and Discussion The external load impedance in the design above is simply a series of a reactance and a pure resistance. IDS, IDS1, and IDS2 are the intrinsic drain current for the three chips, while Vdout, Vdout1, and Vdout2 are the intrinsic drain voltages for the three chips. X2 represents the full gate circuit that includes bondwires set1, 2, and 3, the input gate lead and the pre-match capacitor. While (X3, X4, and X5) are the drain bondwires set 4 and 5. The SNP4 includes the S-parameters obtained from the electromagnetic model of PCB plus the drain lead. Z1P5 and Z1P4 are matching reactance at the input and at the output respectively. The input drive power and the external load impedance will be tuned to attain maximum nominal output power and as high efficiency as possible. The results of simulation are presented in figure 5.13 Figure 5-13 Results of simulation The load lines are consistent with the average drain currents and voltages of the three chips. The drain current is saturating for a maximum instantaneous intrinsic drain voltage of 59.4 V. The dip in the drain current corresponds to minimum drain voltage. It decreases until a small instantaneous drain voltage and then increased back to maximum. The intrinsic load impedance was obtained of value (1.9+j*0.8) ohms. 87 Comparing this value to the value obtained in section 4.4 (1.9+j*0.5) ohms, we can say that the tuning optimization of the simulation gives rather close values to ideal class B amplifier, 8.1/3=2.7 ohms. The total drain efficiency obtained is 66.4 % for a maximum output power of 147.2 watts. These values were obtained by tuning of input drive power and the external load impedance. The power from the intrinsic transistor, the power from the transistor die, and the power from the whole power amplifier were calculated and the values are presented in figure 5.13, where it shows how some parts of the output power are lost in the output network. The difference in the drain current and voltage between the center and output chips is shown in figure 5.14. Figure 5-14 Drain Currents and voltages distribution for the three chips 88 The difference in the drain current and voltages between the two outer chips is negligible which shows that the symmetry between them is not significantly disturbed by the lambda/4-line. We can also conclude that the PCB has really no noticeable affect on the current distribution between the three chips (compare Fig 5.14 to Fig 4.8). It only acts as a transformer to transform the external load. It can be considered as a point connection to some approximation. Also the existence of the quarter wavelength did not have any affect on the symmetry of the outer chips for the center position of the output port. The next step is to include the simulations of the different position of the output port of the PCB, where it connects to the external load, in the power amplifier design and see whether we see some degradation in the power and efficiency. Figure 5.15 shows the whole power amplifier with the right and left positions of the output port of the PCB. Figure 5.12 shows the whole power amplifier with the center position of the output port of the PCB. 89 Figure 5-15 The power amplifier for right and left position of output port The results of simulations for the two positions right (a) and left (b) are presented in figure 5.16 and will be followed by discussion regarding the results of the three simulations. 90 (a) 91 (b) Figure 5-16 Different results for different positions of the output port of the PCB are observed. (a) Right Position is the position where one outer chip is closer to the quarter wavelength than the (b) other outer chip (left position). 92 As for the results obtained in figure 5.13 and 5.14 where the output port is at its center position, there was not any degradation for the output power or the drain efficiency. A value of 78.1 % for intrinsic drain efficiency is very reasonable compared to the value of the intrinsic efficiency of an ideal class B power amplifier π/4. The output power obtained is the power for the three chips. Since the requirement is an output power of 40 watts per chip, so the transistor model actually is able to deliver an output power of 49 watts per chip. The maximum current obtained was 9.2 A for maximum drain voltage of 59.4 V including the PCB. Comparing this value to the value obtained in the design of three chips power amplifier without the PCB (9.2 A), this also proves that the PCB can be considered as electrical point connection to some approximation. The PCB plus the drain lead electromagnetic simulation with different positions of the output port showed small difference when comparing the S-parameters. The gate and drain electromagnetic and lumped models showed a very good agreement. The PCB connection at the output drain was proved to act as a transformer for load impedance and can approximated as an electrical point connection. Moreover, the same matching procedure was followed as well as same tuning criteria. However, we see in the simulation results for the different positions of the output port a significant difference in the current distribution between the two outer chips (IDS1, and IDS2). Let’s take the case of the right position of the output port (figure 5.15). The center chip (IDS) and one outer chip (IDS1) are closer to the quarter wavelength than the other outer chip. The output port is close to the quarter wavelength as the right outer chip (IDS1) is, and far from the center chip. What could be realized from the drain current distribution for the right position of the output port between the center chip and the right outer chip is that the RF output port has broken the symmetry for the two outer chips. If we look at the drain current in figure 5.16 (a), there is slight difference in the drain current between the center and the right outer chip while there is a much larger difference between the other chips. The same applied for the center chip and the left outer chip figure 5.16 (b) where the port was moved to the other side of PCB. Despite that, the quarter wavelength has kept the symmetry for the current, and hence, it is fairly distributed between the chips. As for the results of simulation for the left position of output port, we can obviously see the degradation in the total drain efficiency though it is very small (65 %). However, this value is very acceptable comparing with the total drain efficiency obtained from the three chips power amplifier with (for center position) and without the PCB. Moreover, a value of 75.3 % for the drain intrinsic efficiency is acceptable compared to ideal class B power amplifier π/4. 93 We can also see how parts of the output power are lost in the output network while looking at the values obtained for the power from the intrinsic transistor (168.7 watts), power from the transistor die (159.6 watts), and from the whole power amplifier (145.6 watts). 5.4.2. Conclusion Different positions of the output port led to different results but not crucial difference. However, from the results we have obtained, the quarter wavelength line introduces a negligible asymmetry between the currents of the outer chips; indeed it gives no significant influence. The position of the output port representing the position of the output coupling capacitor, on the other hand, does give a significant influence, including breaking significantly the symmetry of the distribution of the current between the two outer chips. From that, we conclude that the larger contributor to the difference in the signal distribution between the three chips is the mutual inductances between the different set of bondwires, especially the mutual inductances at the drain side together with an influence from the position of the RF output capacitor. Another significant conclusion that we could draw from those results is that the transistor drain lead can not be exactly considered a point connection, but still such approximation would not be too bad. 94 Chapter 6 6.1. Onchip Current Distribution Introduction In this chapter we will study the onchip interconnection on the transistor chips inside the MRF6S21140H package. The onchip interconnect, which routes the current on the die surface to the different gate and drain fingers, has non-zero impedance. Also, the current paths from the source-region substrate contacts through the substrate to the package ground plane have non-zero impedance. Since the lengths of these current paths are slightly different for fingers located on different parts of the die, different fingers will see slightly different impedance levels. Hence the operating conditions will not be perfectly uniform across the die. A well-designed device may be characterized by having as uniform conditions as possible. 6.2. Onchip Geometry Figure 6.1 shows a top view for a part of the metallization layer of the transistor die. The transistor die has a 5.35 mm length, 1.285 mm width and 0.147 mm thickness. The bondwires on each side (gate and drain) are separately connected together by a two metal plates which are respectively connected to several metal fingers. Between these metal fingers an infinite number of LDMOS transistors are connected. In the following these transistors will be replaced by the model found by Janusz Holowacz (See Figure 6.3), in addition their amount will be limited to a specific number due to simulation and memory limitation. Figure 6-1 Top view of the metallization layer of the transistor die 95 6.3. Equivalent Circuit Several approximations were done for finding an equivalent circuit that represents qualitatively the onchip interconnection but due to lack of information about the transistor die, the results that were found were not so precise and need more accurate description of the metallization layer in addition to a more accurate model of the die. First we will start by creating a model in HFSS and then we will move next to a model implemented in Momentum ADS. After discussing these two models and the simulations result obtained we will build a RLC lumped model to reflect the same behavior of the electromagnetic effect. Finally all the simulations result will be interpreted to study as much as possible the current distribution on the metallization layer. 6.3.1. HFSS Implementation The transistor die will be modeled as a substrate of silicon that has the dimension of the transistor (5.35x1.285x0.147 mm) .The metallization layer will be divided into two separate parts; one is connecting the drain bondwires and the other is connecting the gate bondwires. Figure 6.2 shows the transistor chip geometry in HFSS. Figure 6-2 Transistor Chip Geometry implemented in HFSS Four lumped ports are defined on each finger for the gate and drain metallization and each two opposite ports will be connected together by the LDMOS transistor model found by Janusz Holowacz (Figure 6.3). The output current from this model will be divided by the number of transistors used in the simulation. The number of ports was chosen in respect to memory and time limitations and in addition to reflect as much as possible the real geometry of the transistor which include a much higher number then used in figure above (36 transistors). If we increase the number of ports the current distribution will be studied better but at least this geometry will give us a first approximation. 96 Var Eqn VAR VAR5 A=1.86 ctr=1 D=0.55/(3*ctr) Vpk=4.564 Vg=3.6 P1=1.65 B=0.0098 E=1.435 VT=3.12 Vd=28 Port P1 Num=1 Var Eqn VAR VAR4 Cgs=75.46-5.822*Vg+1.152*Vg^2+2.877*Vg^3-1.2827*Vg^4+0.194*Vg^5-0.01*Vg^6 Cds=74.267-7.0868*Vd+0.351*Vd^2-0.0058*Vd^3 Rds=0.1267-0.0067*Vd+0.0002*Vd^2 Rgs=0.1376+0.0046*Vd SDD2P SDD2P2 I[1,0]=0 I[2,0]=D*((_v1-VT)^2)*((1.001-tanh(VT-_v1))^2)*tanh(A*_v2)*(1+B*_v2) C[1]= Cport[1]= C C33 C=(Cgs/ctr) pF C C32 C=(Cds/ctr) pF R R30 R=(Rgs*ctr) Ohm R R29 R=(Rds*ctr) Ohm Port P2 Num=2 Figure 6-3 LDMOS Model, ctr is the number of transistors on the die The ports are defined with respect to the current path from the metallization layer through the substrate and then to the ground plane. Figure 6.4 shows a closer view of two lumped ports representing the connection of the LDMOS model to the drain and gate metal plates. The integration line represented as a vector from the metallization layer to the ground plane describes the current direction. Figure 6-4 Integration Lines representing the current direction through the port Figure 6.5 shows the geometry of the electromagnetic model built in HFSS including the drain prematch circuitry and the first set of gate bondwires. Our first simulation will be on a geometry including only two lumped ports on the center fingers, one on the drain metallization and the other on the gate metallization which means the use of one LDMOS transistor model. Then we will increase the number of ports to four with the same methodology used for two ports. Figure 6.6 shows the geometry of the two structures built. 97 Figure 6-5 HFSS Geometry of the total model simulated (a) (b) Figure 6-6 (a) Structure with 2 ports (b) Structure with 4 ports The purpose of beginning the simulations with this reduced structures was to see how much will be the difference between the two of them if in the structure that have only two lumped ports we connected two LDMOS transistor models on the same connection point and then comparing the result with the structure that have two separate connections and respectively two LDMOS model. The results of the HFSS simulations done above were extracted to ADS (Figure 6.7). 98 Term Term1 Num=1 Z=50 Ohm 4 1 Term Term3 Num=3 Z=50 Ohm Term Term2 Num=2 Z=50 Ohm 2 3 Ref S4P SNP1 Term Term6 Num=6 Z=50 Ohm Term Term7 Num=7 Z=50 Ohm Term Term4 Num=4 Z=50 Ohm Term Term5 Num=5 Z=50 Ohm S-PARAMETERS S_Param SP1 Start=0 GHz Stop=4 GHz Step=0.2 GHz 6 1 Term Term8 Num=8 Z=50 Ohm Term Term10 Num=10 Z=50 Ohm 5 2 3 4 Ref S6P SNP2 Term Term9 Num=9 Z=50 Ohm Term Term11 Num=11 Z=50 Ohm Term Term12 Num=12 Z=50 Ohm Figure 6-7 HFSS Simulations results exported to ADS Port number 1 and port number 7 represent the gate input wave ports for the two structures above and ports number 2-3 represent the same lumped port at the gate metallization but divided to two ports. Ports number 8-10 represents the two lumped ports at the gate metallization in the structure having four ports. Figure 6.8 shows the comparison between S12 and S78, S79. Figure 6-8 Comparison between real and imaginary S-parameters values of Gate input and Gate metallization ports This figure shows that the difference between two close ports is very small and it will increase with increasing the number of ports. Now if we connect the gate and drain metallization ports to the gate source and drain source capacitance and resistance of the LDMOS transistor model when it is operating as 99 a class B amplifier (Vg=3.6V and Vd=28V), we can see (Figure 6.9) that the difference between the ports is increasing specially at the frequency band of interest (2.11-2.17 GHz) and this is due to a close resonance frequency which is the mainly reason of this difference. Figure 6-9 Comparison between Gate input and metallization ports after connecting them to the gate source capacitance and resistance This difference will be very critical and it will lead to imprecise results when designing a class B power amplifier specially when studying the current distribution on the two LDMOS transistors. In addition to this issue we encountered another problem when using simulations results from HFSS. HFSS is a 3 dimensional FEM simulator that does not simulate at DC level, it only extrapolate from the lowest possible frequency to 0 Hz, and this is very critical when designing a power amplifier using HFSS results, because the extrapolation was in almost all the cases not very precise. So to avoid this extrapolation we had to enter the DC level S-parameters manually and for large number of ports meaning a huge matrix, this process was very hard. In addition to cover at least the eight harmonic or above for a 2.14 GHz center frequency, we should simulate to 18 GHz but up to this frequency we didn’t have convergence. Encountering these two main problems we decided to skip the simulations for an increased number of ports and instead using Momentum in ADS. 6.3.2. Momentum Implementation In ADS Momentum we used the same structure as in HFSS but without the drain prematch circuitry and the first set of gate bondwires. The metallization layer has the same dimensions also. Figure 6.10 shows the structure used in Momentum. 100 P1 P3 P4 P5 P6 P2 Figure 6-10 Momentum Implementation As for ports definition, we have two single mode ports each one of them connected at the center of the drain and gate metallization separately and four internal ports, two connected on a gate finger and two on a drain finger. The results obtained from the simulation of this structure were very similar to the results obtained in HFSS specially when connecting the internal ports to the gate source and drain source capacitance and resistance. Figure 6.11 shows the difference between S14 and S16 with and without connecting port 4 and port 6 to the gate source and drain source capacitance and resistance of the LDMOS model operating as a class B power amplifier. (a) (b) Figure 6-11 Comparison between gate ports without (a) and with (b) connecting them to the gate source and drain source capacitance and resistance 101 Having the same result as in HFSS and encountering the same problem when designing a class B power amplifier, it corroborates that the electromagnetic results are accurate from the geometry point of view. But due to this problematic issue (The exact reason we don’t know, but to obtain a more accurate geometry to start from would be one thing to try) we decided also to skip the phase of increasing the number of internal ports. The results found both in Momentum and HFSS reveals that there is a probability of non uniformity in current distribution. To investigate more our doubts for this non uniformity current distribution we decided to build a RLC lumped model that have the same behavior of the electromagnetic model. 6.3.3. Equivalent Lumped Model The process of finding an equivalent lumped model will begin first by finding a lumped model for two consecutive drain and gate fingers. Figure 6.12 show the structure in ADS and figure 6.15 shows the equivalent circuit. Each drain and gate finger has a 0.12mmx0.9mm dimension and the distance between two consecutive ones is o.145 mm. Figure 6-12 Momentum layout for two consecutive gate and drain fingers MUTIND Mutual Mutual1 K= M=M1 pH C Inductor1="L1" C1 C=C1 pF Inductor2="L2" Term Term1 Num=1 Z=50 Ohm R R1 C R=R1 Ohm C5 C=C2 pF C R C3 C=C1 pF R2 R=R1 Ohm Var Eqn VAR VAR1 C1=0.077 {t} R1=0.0154 {t} M1=4 {t} C2=0.0071 {t} L_1=0.831 {t} L L1 L=L_1 nH R= L L2 L=L_1 nH R= C C2 C=C1 pF C C6 C=C2 pF C C4 C=C1 pF Figure 6-13 Equivalent Lumped Model 102 Term Term2 Num=2 Z=50 Ohm The equivalent lumped model of a single metallization finger is composed of a single inductance in series with a resistance and two capacitors from both sides representing the coupling to the ground. C5 and C6 represent the coupling between the two fingers and M1 is the mutual inductance between the fingers. After tuning all the elements of the circuit to fit the simulation result to the electromagnetic result we found that: L1=L2= 0.831 nH C1=C2=C3=C4= 0.077 pF C5=C6= 0.0071 pF R1=R2= 0.015 Ohm M1= 4 pH Figure 6.14 shows the comparison results between lumped and electromagnetic simulations. Figure 6-14 Comparison results between lumped and electromagnetic simulation for two consecutive fingers The model found for two fingers will be extended for all the fingers but with neglecting the mutual inductances between non-consecutive ones. Next we will find the lumped model for the two identical gate and drain metal plates that connect the bondwires together. The metal plate has a 4.91mmx0.14 mm dimension and is divided into 8 parts and for each part we founded a LC lumped model depending on the height, width of the plate and thickness of the Silicon substrate lying on. This will give us a first approximation for the model and then after tuning to fit the electromagnetic simulation a final model was found. Figure 6.15 shows the layout model and 6.16 the lumped model. After tuning the capacitance and inductance of each part will be equal to: L11= 0.1545 nH and C11= 0.0536 pF 103 Figure 6-15 Layout of the metal plate connecting the bondwires Figure 6-16 Equivalent lumped model The comparison results are shown below: Figure 6-17 Comparison results Now having the lumped models for the fingers and metal plate connecting the bondwires, a full circuit for the onchip metallization can be build (Figure 6.18). 104 Figure 6-18 Full lumped model for the onchip metallization Comparisons with electromagnetic simulation are shown in Figure 6.19. 105 Figure 6-19 Comparison between electromagnetic and lumped model for the full onchip metallization 6.4. Power Amplifier Design and Current Distribution 6.4.1. Gate Current Distribution After finding an equivalent lumped model for the onchip metallization we will use it in designing a simple class B power amplifier. First we will connect three LDMOS transistor model between two fingers (Figure 6.20). Figure 6-20 Three LDMOS models connected between drain and gate fingers Where X1-X21-X20 represent the LDMOS models (See Figure 6.3). A single finger was modeled by a two resistances and inductances that have half of the value found before for a single inductance and resistance. 106 The model above will be extended for each consecutive drain and gate fingers which means that we will have in total 27 sub transistors. Then we will add to it the drain prematch circuitry and the first set of gate bondwires with the 25 pF shunt capacitance. The final circuit will look like in Figure 6.21. 3 2 1 6 5 4 9 8 7 Figure 6-21 Power Amplifier schematic The load impedance and the input matching network will be tuned to almost have maximum output power (46.6 Watts) at the maximum input power allowed for the MRF6S21140H. The input power will be swept between 39 and 41 dBm which are high but on the other hand the LDMOS model does not really give a realistic description of gain so the input should be varied to get appropriate saturation of drain voltage, but in this study the gate circuit is almost linear, so actual levels does not matter. To study the intrinsic gate voltage on different sub transistors a total of nine transistors were picked (see Figure 6.23), three connected to the top fingers, three connected to the middle fingers and three connected to the bottom fingers. The top ones will have Vgate1, Vgate2 and Vgate3 where Vgate1 is the intrinsic gate voltage of the transistor close to the drain 107 side, Vgate2 is the intrinsic gate voltage of the transistor in the middle and Vgate3 is the intrinsic gate voltage of the transistor close to the gate side (As shown in figure 6.23). Respectively in the same order of numbering Vgate4, Vgate5 and Vgate6 will be the intrinsic gate voltages for the transistors connected to the middle fingers and Vgate7, Vgate8 and Vgate9 will be the intrinsic gate voltages for the transistors connected to the bottom fingers. Figure 6.22 shows the difference in magnitude of the gate intrinsic voltages for the three sets of sub transistors in function of the input power. Figure 6-22 Comparison between magnitudes of intrinsic gate voltages for different sub transistors This figure reveals that for the three sets taken above, the sub transistors (1, 4, and 7) close to the drain side have the highest magnitude of intrinsic gate voltage and this magnitude will decrease when closing to the gate side. Also the transistors (3, 6, and 9) close to the gate side have a gate intrinsic voltage magnitude in the range of 1V which is very low and will not drive them, so one third of the sub transistors will be practically off and they will not derive any current to the drain intrinsic. Figure 6.23 shows the comparison for the magnitude of gate intrinsic voltages between the sub transistors connected to different fingers but positioned at the same distance from gate connection. It is clearly seen that the decreasing in voltage form the highest sub-transistor to the lowest one is proportional for the three sets; in other word the sub transistors 108 connected to the top fingers have the highest gate intrinsic voltages and with going down the magnitude will decrease proportionally for the three sets. Figure 6-23 Comparison between magnitudes of intrinsic gate voltages for different sub transistors positioned at the same side We can conclude from these results concerning the gate side that we have a possible non uniform current distribution on the sub transistors and this is due to the large size of metallization which will introduce large inductances effect on the onchip interconnection. Maybe the approximation taken who led to these results is not so accurate and it needs more investigation. Especially in finding more accurate geometry for the metallization layer and more information about the transistor dies. But at least it leads us to a big probability of non uniformity current distribution. 6.4.2. Drain Current Distribution For investigation on the drain onchip current distribution, we had to make an approximation in designing the class B power amplifier. First the LDMOS model (Figure 6.3) was modified so that we have on the gate intrinsic a constant input voltage drive of 3.2 V and a DC voltage of 3.6 V for biasing. In that way all the sub transistors used on the onchip metallization will have the same gate intrinsic voltage. Figure 6.24 shows the new modified model. Another modification was done and that all the circuit representing the gate metallization and the gate prematch circuitry are taken and we had only the circuit representing the drain metallization and the drain prematch circuitry. In addition, on each drain finger we connected two LDMOS modified model (Figure 6.25) so that we have in total 18 sub transistors. 109 Figure 6-24 Modified LDMOS Transistor Model LDMOSCHIPmodified X1 LDMOSCHIPmodified X2 C C8 C=C1 pF R R2 R=R1 Ohm L L2 L=L_1 nH R= C C4 C=C1 pF Figure 6-25 Two LDMOS modified models connected to a drain finger The full circuit of the power amplifier is shown in Figure 6.26 with the load impedance tuned so that we have maximum output power (46.6 Watts) at the load resistance and also to have an intrinsic drain resistance at each sub transistor close to of LDMOS models used in the circuit. 110 R opt times the number 2 1 LDMOSCHIPmodified X2 LDMOSCHIPmodified X1 C C C8 C=C1 pF R L R2 R=R1 Ohm L2 L=L_1 nH C C4 C=C1 pF R= LDMOS Modified Models C90 C=C11 pF L L34 L=L_2 nH R= C C9 C=C1 pF LDMOSCHIPmodified LDMOSCHIPmodified X3 X4 L R R4 R=R1 Ohm C L4 L=L_1 nH R= C C11 C=C1 pF C89 C=C11 pF L L33 L=L_2 nH R= LDMOSCHIPmodified LDMOSCHIPmodified X5 X6 1 2 3 C C15 C=C1 pF R L R6 R=R1 Ohm L6 L=L_1 nH R= 4 C C17 C C88 C=C1 pF C=C11 pF 5 6 7 L L32 8 L=L_2 nH R= 9 L L35 L=0.061 nH 10 11 LDMOSCHIPmodified X7 C C41 C=C1 pF 12 LDMOSCHIPmodified X8 R R12 L L12 R=R1 Ohm L=L_1 nH R= R R31 R=0.002 Ohm C Vload ILoad C C43 C=C1 pF C C87 C=C11 pF 14 DC_Feed 15 DC_Feed1 Var Eqn 17 C C40 C=C1 pF R=R1 Ohm L30 L=L_2 nH R= C34 C=C1 pF LDMOSCHIPmodified LDMOSCHIPmodified X11 X12 L R R7 R=R1 Ohm L7 L=L_1 nH R= LDMOSCHIPmodified X13 C C63 C=C1 pF C C C32 C86 C=C1 pF C=C11 pF LDMOSCHIPmodified X14 R R18 L L18 R=R1 Ohm L=L_1 nH R= Load Impedance C38 C=C1 pF L C C C C93 C=C11 pF C Xi=8.1 {t} Vdrive=0 SRC1 Vdc=28 V C91 C=200 pF LDMOSCHIPmodified X10 L L9 L=L_1 nH R= R R9 L=L_2 nH R= VAR VAR2 V_DC BONDW19 WIRESET1 L31 R32 R=4.3 Ohm {t} 16 18 3 S1P_Eqn S1P1 S[1,1]= Z[1]=(Xi*j) Ohm 19 4 DC_Block DC_Block1 13 L LDMOSCHIPmodified X9 R I_Probe C92 C=3.643 pF R= Drain Prematch Circuitry L L29 L=L_2 nH R= C C C65 C=C1 pF C85 C=C11 pF L L28 L=L_2 nH R= LDMOSCHIPmodified X18 LDMOSCHIPmodified X15 C C62 C=C1 pF L L15 R R15 R=R1 Ohm C C C60 C=C1 pF L=L_1 nH R= C84 C=C11 pF L L27 L=L_2 nH R= C C56 C=C1 pF 6 5 LDMOSCHIPmodified LDMOSCHIPmodified X17 X16 R L R13 R=R1 Ohm L13 L=L_1 nH R= C C54 C C83 C=C1 pF C=C11 pF Drain Onchip Metallization Figure 6-26 Class B Power Amplifier circuit Design The load impedance obtained after tuning is equal to: R load = 4.3 – j*7.9 ( Ω ) Table 6.1 shows the output RF power at the load impedance, the DC power, the DC current and the efficiency obtained. Table 6-1 Efficiency, Rf Power, DC Power and DC Current obtained from the designed Power Amplifier 111 To study the current distribution on the drain metallization, a total of six sub transistors were taken (Figure 6.26), two connected to the top finger having Idrain1-Idrain2 as intrinsic drain current and voltage, two connected to the middle finger having Idrain3Idrain4 as intrinsic drain current and voltage, and two connected to the bottom finger having Idrain5-Idrain6 as intrinsic drain current and voltage. In the following the results obtained from simulation are shown. Figure 6-27 Intrinsic Drain Current and Voltage of the six Sub Transistors 112 Figure 6-28 Intrinsic Drain Current and Voltage of the three Sub Transistors connected to the edge of the fingers Figure 6-29 Intrinsic Drain Current and Voltage of the three Sub Transistors close to the drain side 113 Figure 6.29 shows the intrinsic drain currents and voltages in time domain for the six sub transistors chosen. Idrain1, Idrain3 and Idrain5 are the currents for the sub transistors close to the drain side and respectively Idrain2, Idrain4 and Idrain6 are the currents for the transistors connected to the other side. Figure 6.30 and 6.31 shows that we have almost constant current and voltage at all drain sub transistors on each side of the fingers separately and also that we have maximum current approximately at minimum voltage for all the sub transistors and this will definitively increase the output power and respectively the efficiency. Another conclusion to be made is that we have voltage saturation for the intrinsic drain currents at all the sub transistors (2, 4, 6 see figure 6.29) connected to the edge of the finger while for sub transistors close the drain side (1, 3, 5) the current is reaching his maximum without saturating. This difference is probably due to the large inductance of the metallization finger which also affects the drain intrinsic voltages for the two sub transistors connected to it. (At Sub transistors 2, 4 and 6 drains we have bigger voltage magnitude then at sub transistors 1, 3 and 5). An important fact to add is that when sub transistors close to the gate connection are already in significant voltage saturation, sub transistors close to drain connection are still approximately 5V from voltage saturation, so approximately 5V of the supply voltage is simply wasted for those sub transistors, leading to degradation of output power and efficiency ( ≈ 65% to ≈ 62%). But of course the model only including the drain side is not very realistic but still gives some interesting results. 6.5. Conclusion From the electromagnetic model to the equivalent lumped model for the onchip metallization we can conclude that there is a big probability of none uniform current distribution on the gate and drain metallization especially on the sub transistors connected to the same fingers due to the effect of their large inductances. To study and investigate more deeply these onchip non-uniformity current distribution and how they affect the output power and efficiency of the transistor we need to have more information about the transistors dies and have more accurate geometry for the onchip metallization layer. The results obtained are still interesting however, and can be taken as a starting point for future studies. 114 Chapter 7 • Summary A theoretical introduction for high RF Power amplifiers, operating classes, and Si-LDMOS transistors was presented. • A modeling strategy (Segmentation) was introduced. • The geometries of the package, die and PCB test board were presented. • Electromagnetic models and equivalent lumped circuits were found for all the components of the MRF6S21140H package (the die, the prematch capacitors, the bondwires, the drain and gate lead). • Good fit between electromagnetic and lumped simulations was found. • Given the knowledge of the dominating electromagnetic properties of the package obtained , it may be helpful for equivalent circuit modeling, PA design, and also for understanding results obtained from measurement • A single chip and three chips class B power amplifier was designed, matching networks were introduced; different parameters were investigated to assure the quality results obtained from the modeling and from the power amplifier. • Off chip connection geometry was introduced and an equivalent electromagnetic model was found. • Sensitivity due to the position of the DC block capacitor or precisely position of the output port was investigated. Further investigation about the position of the output port in the design of power amplifier is needed to study how it can affect the behavior of the power amplifier. • Onchip interconnection geometry was presented and an equivalent lumped model for the metallization layer was found. • Possible non uniform current distribution on the drain and gate metallization was proofed. • More investigation about the nature of the transistor chips die and the metallization layer is needed to see how the onchip nonuniform current distribution is affecting the behavior of the transistor specially the output power and efficiency. 115 Chapter 8 Conclusion In this report we presented an overview about high RF Power Amplifiers and we took a close view about the LDMOS transistors. The segmentation method followed in modeling the inside package leads us to consistent results and it may be a helpful strategy for equivalent circuit modeling. Using HFSS for electromagnetic simulations and ADS to build equivalent lumped models, we presented a good fit between results. We showed that mutual inductances between close bondwires have an effect on the total behavior of the model. Also we concluded that the coupling capacitance between bondwires and ground plane was small and has a small effect but accurate extraction of the value remains a point for future work. Also accurate calculation for the loss inside the package remains a point for future work and needs a more detailed study about the nature of the materials inside the package. The main issue that we face in the electromagnetic simulations is the extrapolation at DC level because HFSS cannot compute DC solutions and the extrapolation done by the software was often not so accurate. It is important to note that for a correct description of the electrical behavior, the thermal behavior which was not included in our work must also be considered since a substantial amount of electrical power is dissipated, introducing an increase in temperature. The modeled transistor was applied in the design of a power amplifier and it has worked with all its characteristics. The symmetry between the two outer chips for a three chips power amplifier was proved and a small non uniform current distribution between center and outer chip was detected and found that this non uniformity is mainly due to non ideal connection caused by mutual inductances between different sets of bondwires especially on the drain side. Electromagnetic model for the output drain PCB was built, and an important conclusion that we have drawn from the simulations is that the PCB connection can as a first approximation be taken as electrical point connection. As the drain model showed a rather small difference in the signal distribution between the three chips, again this has been proved through the realization of the drain model combined with PCB. Different positions for the output port to connect the external load were investigated. We have shown that these positions can give a significant difference from the first-order-point contact approximation when considering the design of a complete three chips power amplifier. Still this effect gives rather negligible efficiency degradation. Further investigation can be considered for future work regarding the position of the quarter wavelength, and whether placing a port at the quarter wavelength can lead to better and convenient results. 116 A lumped model for the onchip interconnection was found and used in two power amplifiers designs. The results lead to a big possibility of non uniform current distribution on the metallization layer especially on the metallization fingers but more investigation and studies for the transistor dies and metallization layer are needed to see how this non uniformity is affecting the output power and efficiency. All in all, there is a possibility that even on the same die, different transistor elements have sufficiently different conditions. Even if they are identical on the die, the integration of multiple transistor elements and their simultaneous operation cause different electrical characteristics in different transistor elements. 117 Chapter 9 References [1] A. Wood, W. Brakensiek, C. Dragon, W. Burger, “120W, 2GHz, Si LDMOS RF Power Transistor For PCS Base Station Applications”, IEEE MTT-S Digest, 1998 [2] K. Mouthaan, Modeling of RF High Power Bipolar Transistors. Ph.D. dissertation, ISBN 90-407-2145-9, Delft University of Technology, 2001. To obtain a copy, visit the internet site: http://www.DevilsFoot.com. [3] ‘’Quasistatic electromagnetic modeling of PTF10136’’-Johan Sjöström, Torkel Arnborg, 2001. [4] Evaluation of Si-LDMOS transistor for RF power amplifier in 2-6 GHz frequency range, Department of Electrical Engineering, Linkoping University, Grigori Doudorov Reg nr: LiTH-ISY-EX-3435-2003 [5] F.M. Rotella at al., Modeling, Analysis and Design of RF LDMOS Devices Using Harmonic-Balance Device Simulation, IEEE Transactions on microwave theory and techniques. Vol.48, No.6, 2000 [6] Philips Semiconductors, RF transmitting transistor and power amplifier fundamentals, March 1998. [7] 120 Watt, 2 GHz, Si LDMOS RF power transistor for PCS base station applications Wood, A.; Brakensick, W.; Dragon, C.; Burger, W. Microwave Symposium Digest, 1998 IEEE MTT-S International Volume 2, Issue , 7-12 Jun 1998 Page(s):707 - 710 vol.2 [8] Design and Modeling of High-Frequency LDMOS Transistor by Lars Vestling, Comprehensive Summaries of Uppsala Dissertation from the Faculty of Science and Technology 681-2003. [9] Freescale Semiconductor, www.freescale.com/rf Technical date sheet of MRF6S21140H3; [10] S. C. Cripps, RF Power Amplifiers for Wireless Communication, Norwood, MA, Artech House, 1999 [11] RF and Microwave Power Amplifier Design-McGraw Hill Professional Engineering. By Andrei Grebennikov-2005. [12] LDMOS Model created by Janusz Holowacz [13] ‘’Gate Equivalent Circuit for Single Chip LDMOS MRF6S21140H’’-Janusz Holowacz. Ericsson Internal technical report-2006. [14] ‘’Equivalent-Circuit Modeling and Verification of Metal–Ceramic Packages for RF and Microwave Power Transistors’’ Tao Liang, Jaime A. Pl´a, Peter H. Aaen, and Mali Mahalingam-IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, VOL. 47, NO. 6, JUNE 1999 [15] T. Itoh, G. Pelosi, and p. Silvestre, Eds., Finite Element Software for Microwave Engineering. New York: Wiley, 1996. [16] A. Polycarpou, P. Tirkas, and C. Balanis, “The finite-element method for modeling circuits and interconnects for electronic packaging,” IEEE Trans. Microwave Theory Tech., vol. 45, pp. 1868–1874, Oct. 1997. [17] 118 HFSS Online help. www.hfss.com [18] ’’Microwave Wirebond Model from Die to Laminate’’ Jimmy Hoang, Ryan Lee, 20 February 2005, HFSS Workshop. [19] ADS Documentation help 2006 edition. [20] A.E. Ruehli, “Inductance calculations in a complex integrated circuit environment,” IBM J. Res. Develop, pp. 470-481, September 1972. [21] http://chemandy.com/calculators/microstrip_transmission_line_calculator.ht 119 Appendix A Bondwire Modeling Bondwire Set 1 Figure a.1: HFSS Input Geometry Table a.1: Frequency Dependent Parameters values 120 Vacuum Box 1 and Vacuum Box 2 introduce two small inductances and capacitances which can be calculated analytically: C (Vacuum Box 1) = 0.034 pF L (Vacuum Box1) =0.04 nH C (Vacuum Box 2) = 0.025 pF L (Vacuum Box2) =0.03 nH The final lumped model of bondwire set1 will look as figure a.2 R R1 R=0.0114 Ohm Term Term1 Num=1 Z=50 Ohm C C1 C=0.088 pF L L2 L=0.006 nH R= L R L1 R2 R=0.00184 Ohm L=0.139 nH R= C C2 C=0.099 pF Term Term2 Num=2 Z=50 Ohm Bondwire Set 1 Figure a.2: Equivalent Lumped Model V R AC =0.0114 Ω R DC = 0.00184 Ω L1= 0.139 nH C2 (Drain Side) = 0.099 pF L2= 0.006 nH C1 (Gate Side) = 0.088 pF Figure a.3: Comparison Results between Lumped and Electromagnetic Model 121 Bondwire Set 2 Figure b.1: HFSS Input Geometry V The values of the parameters listed in Appendix A for the final lumped models are the exact values (after tuning) used in the simulations 122 Table b.1: Frequency Dependent Parameters values Vacuum Box 1 and Vacuum Box 2 introduce two small inductances and capacitances which can be calculated analytically: C (Vacuum Box 1) = 0.034 pF L (Vacuum Box1) =0.04 nH C (Vacuum Box 2) = 0.075 pF L (Vacuum Box2) =0.0092 nH The final lumped model of bondwire set1 will look as figure b.2 R R1 R=0.018 Ohm Term Term1 Num=1 Z=50 Ohm C C1 C=0.163 pF L L2 L=0.005 nH R= L R L1 R2 R=0.00451 Ohm L=0.235 nH R= C C2 C=0.347 pF Term Term2 Num=2 Z=50 Ohm Bondwire Set 2 Figure b.2: Equivalent Lumped Model R AC = 0.018 Ω R DC = 0.00451 Ω L1= 0.235 nH C2 (Drain Side) = 0.347 pF L2= 0.005 nH C1 (Gate Side) = 0.163 pF Figure b.3: Comparison Results between Lumped and Electromagnetic Model 123 Bondwire Set 3 Figure c.1: HFSS Input Geometry Table c.1: Frequency Dependent Parameters values 124 Vacuum Box 1 and Vacuum Box 2 introduce two small inductances and capacitances which can be calculated analytically: C (Vacuum Box 1) = 0.037 pF L (Vacuum Box1) =0.01 nH C (Vacuum Box 2) = 0.037 pF L (Vacuum Box2) =0.01 nH The final lumped model of bondwire set1 will look as figure c.2 R R1 R=0.025 Ohm Term Term1 Num=1 Z=50 Ohm C C1 C=0.165 pF L L2 L=0.006 nH R= L R L1 R2 R=0.00173 Ohm L=0.19 nH R= C C2 C=0.166 pF Term Term2 Num=2 Z=50 Ohm Bondwire Set 3 Figure c.2: Equivalent Lumped Model R DC = 0.00173 Ω R AC = 0.025 Ω L1= 0.19 nH L2= 0.006 nH C2 (Drain Side) = 0.166 pF C1 (Gate Side) = 0.165 pF Figure c.3: Comparison Results between Lumped and Electromagnetic Model 125 Bondwire Set 5 Figure d.1: HFSS Input Geometry Table d.1: Frequency Dependent Parameters values 126 Vacuum Box 1 and Vacuum Box 2 introduce two small inductances and capacitances which can be calculated analytically: C (Vacuum Box 1) = 0.035 pF L (Vacuum Box1) =0.015 nH C (Vacuum Box 2) = 0.061 pF L (Vacuum Box2) =0.01 nH The final lumped model of bondwire set1 will look as figure d.2 R R1 R=0.032 Ohm Term Term1 Num=1 Z=50 Ohm C C1 C=0.119 pF L L2 L=0.008 nH R= L R L1 R2 R=0.00266 Ohm L=0.325 nH R= C C2 C=0.223 pF Term Term2 Num=2 Z=50 Ohm Bondwire Set 5 Figure d.2: Equivalent Lumped Model R DC = 0.00266 Ω R AC = 0.032 Ω L1= 0.325 nH C2 (Drain Side) = 0.223 pF L2= 0.008 nH C1 (Gate Side) = 0.119 pF Figure d.3: Comparison Results between Lumped and Electromagnetic Model 127 Appendix B Mutual Inductances a. Drain Mutual Inductances: The naming convention for mutual inductance will be as follow: M ab_cd Where a, b are the bondwires set numbers and c, d the transistor chip numbers (For chip numbers: 2 is the number of the middle chip and 1, 3 the numbers of the side chips). For example M 45_12 is the mutual inductance between bondwire set 4 and bondwire set 5 connected respectively to chip number 1 and chip number 2. M 44_12 = M 44_23 M 44_13 = 0.239 pH M 55_12 = M 55_13 = 9.48 pH M 45_11 = M 45_22 = M 45_33 = 44 pH M 45_12 = M 45_23 = M 54_12 = M 45_13 = M 54_13 = 0.24 pH M 55_23 = 2.482 pH = 19.988 pH M 54_23 = 4.87 pH b. Drain-Gate Mutual Inductances: 128 M 53_11 = M 53_22 = M 53_33 = 0.254 pH M 53_12 = M 53_23 = M 53_21 = M 53_13 = M 53_31 = 0.044 pH M 43_11 = M 43_22 = M 43_33 = 1.815 pH M 43_12 = M 43_23 = M 43_21 = M 43_13 = M 43_31 = 0.081 pH M 53_32 M 43_32 =0.215 pH =0.8 pH c. Gate Mutual Inductances: M 11_12 = M 11_12 M 11_13 = 0.434 pH M 22_12 = M 22_13 = 2.19 pH M 33_12 = M 33_13 = 0.064 pH M 12_11 = M 12_22 = M 12_12 = M 12_23 = 2.37 pH M 12_13 = 0.953 pH M 32_11 = M 32_22 = M 32_12 = M 32_23 = 0.524 pH M 32_13 = 0.045 pH M 31_11 = M 31_22 = M 31_12 = M 31_23 = 0.024 pH M 31_13 = 0.001 pH = 1.519 pH M 22_23 M 33_23 = 6.735 pH = 0.884 pH M 12_33 M 32_33 M 31_33 = 6.26 pH = 6 pH = 0.322 pH 129 Appendix C Comparison between wave port and lumped port for PCB Realization of PCB with wave port Figure C1 shows the electromagnetic realization of the PCB with a wave port assigned at the output to connect the external load. The wave port is drawn as a rectangle along the width of the drain lead and of the same height as the air box. While figure 5.1(page 80) shows the electromagnetic realization of the PCB with a lumped port at the output. Figure C1: Assigning wave port for PCB at the output The S-parameters of simulation of the model in figure C1 are exported to ADS and compared to the S-parameters where a lumped port was assigned at the output. The comparison results are shown in figure C2. 130 Figure C2: Comparison results Both lumped and wave port show consistent results. From that we conclude that assigning wave port or lumped port at the output will not have affect on the signal distribution between the three chips in the realization of drain and PCB and in the design of a three chips power amplifier if the port is placed at the center of the PCB. The main purpose of using a lumped port is that we wanted to study the affect of the position of the output port on the simulation, and to avoid complexity in simulation with wave port due to the different environment of assigning the wave port and the lumped port. 131 Appendix D: Ports Definition: In HFSS we can find several types of ports .Wave ports, Lumped ports, Incident wave, Voltage, Current, and Magnetic Bias. In our simulations we used only two types of ports: Wave and Lumped Ports. Wave Ports: By default, the interface between all 3D objects and the background in HFSS is a perfect E boundary (perfectly conducting surfaces) through which no energy may enter or exit. Wave ports are typically placed on this interface to provide a window that couples the model device to the external world [17]. HFSS assumes that each wave port we define is connected to a semi-infinitely long waveguide that has the same cross-section and material properties as the port. When solving for the S-parameters, HFSS assumes that the structure is excited by the natural field patterns (modes) associated with these cross-sections. The 2D field solutions generated for each wave port serve as boundary conditions at those ports for the 3D problem. The final field solution computed must match the 2D field pattern at each port. HFSS generates a solution by exciting each wave port individually. Each mode incident on a port contains one watt of time-averaged power. Port 1 is excited by a signal of one watt, and the other ports are set to zero watts. After a solution is generated, port 2 is set to one watt, and the other ports to zero watts and so forth. Lumped Ports: Lumped ports are similar to traditional wave ports, but they can be located internally and have complex user-defined impedance. Lumped ports compute S-parameters directly at the port. A lumped port can be defined as a rectangle from the edge of the trace to the ground or as a traditional wave port. The default boundary is perfect H (surface on which the tangential component of the H-field is the same on both sides) on all edges that do not come in contact with the metal or with another boundary condition. The complex impedance Zs defined for a lumped port serves as the reference impedance of the S-matrix on the lumped port. The impedance Zs has the characteristics of a wave impedance; it is used to determine the strength of a source, such as the modal voltage V and modal current I, through complex power normalization. (The magnitude of the complex power is normalized to 1) In either case, you would get an identical S-matrix by solving a problem using a complex impedance for a lumped Zs or renormalizing an existing solution to the same complex impedance. 132 When the reference impedance is a complex value, the magnitude of the S-matrix is not always less than or equal to 1, even for a passive device. When a lumped port is used as an internal port, the conducting cap required for a traditional wave port must be removed to prevent short-circuiting the source. When assigning a lumped port an integration line must be defined. An integration line is a vector that can represent the following: -A calibration line that specifies the direction of the excitation field pattern at a port. If we you are analyzing more than one mode at a port, we must define a separate set of integration lines for each mode; the orientation of the electric field differs from mode to mode. -An impedance line along which to compute the impedance for a port. In this case, we select two points at which the voltage differential is expected to be at a maximum. For example, on a microstrip port, we place one point in the center of the microstrip, and the other directly underneath it on the ground plane. In a rectangular waveguide, we place the two points in the center of the longer sides. HFSS starts by defining a mesh in the structure. To excite the structure a 2D solver computes the TEM modes at the lumped ports. These modes are the excitation of the 3D structure. The 3D solver computes the fields in the structure and the scattering parameters of the structure in a first pass. At the second pass the mesh is refined automatically based on an error criterion, and fields and scattering parameters are recomputed. This process is repeated until the S-parameters have stabilized [8]. 133 Appendix E Geometry of Bondwires In this section we will show the physical geometry of each set of bondwires by means of radius, length, distance between each other and height above ground plane. As we said earlier we have five sets of bondwires (Figure E-1) which will be discussed in details in the following. Figure E-0-1 Bondwires positions inside the package Bondwire Set 1: This set connects the gate lead to the first gate prematch capacitor. It is formed by three arrays and each array has sixteen parallel bondwires with a separation distance of 0.28 mm. Figure E-2 shows the mounting of these bondwires in the package. Figure E-0-2 Bondwire Set 1 The distance between two consecutive arrays is 1.9 mm and distance from the edge of the gate lead to the first bondwire of the array on the side is 0.93 mm (Figure E-3). 134 Figure E-0-3 Different Distances related to Bondwire Set 1 Figure E-4 shows the geometry of a single bondwire of set 1 which is divided into three straight segments, their lengths and heights above ground plane are also shown. Figure E-0-4 Geometry of Bondwire Set 1 Bondwire Set 2: This set connects the first gate prematch capacitor to the shunt capacitor before the transistor on the gate side. It is formed by three arrays and each array has sixteen parallel bondwires with a separation distance of 0.28 mm between them. Figure E-5 shows the mounting of these bondwires in the package. Figure E-0-5 Bondwire Set 2 135 The distance between two consecutive arrays is 1.9 mm and distance from the edge of the gate prematch capacitor to the first bondwire of the array on the side is 1.78 mm (Figure E6). Figure E-0-6 Different Distances related to Bondwire Set 2 Figure E-7 shows the geometry of a single bondwire of set 2 which is divided into five straight segments, their lengths and heights above ground plane are also shown. Figure E-0-7 Geometry of Bondwire Set 2 Bondwire Set 3: This set connects the shunt capacitor on the gate side to the transistor chip. It is formed by three arrays and each array has eight parallel bondwires with a separation distance of 0.6 mm between them. Figure E-8 shows the mounting of these bondwires in the package. Figure E-0-8 Bondwire Set 3 136 The distance between two consecutive arrays is 2.18 mm and distance from the edge of the shunt capacitor to the first bondwire of the array on the side is 0.7 mm (Figure E-9). Figure E-0-9 Different Distances related to Bondwire Set 3 Figure E-10 shows the geometry of a single bondwire of set 3 which is divided into four straight segments, their lengths and heights above ground plane are also shown. Figure E-0-10 Geometry of Bondwire Set 3 Bondwire Set 4-Set 5: Bondwire set 4 connects the transistor chip to the shunt capacitor on the drain side. It is formed by three arrays and each array has ten parallel bondwires with a separation distance of 0.5 mm between them. Bondwire set 5 relates the transistor chip to the drain lead. It is formed by three arrays and each array has nine parallel bondwires with a separation distance of 0.5 mm between them. Figure E-11 shows the mounting of these bondwires in the package. Figure E-0-11 Bondwire Set 4 and Set 5 The distance between two consecutive arrays of set 4 is 1.339 mm and distance from the edge of the shunt capacitor to the first bondwire of the array on the side is 0.29 mm. 137 The distance between two consecutive arrays of set 5 is 1.854 mm and distance from the edge of the shunt capacitor to the first bondwire of the array on the side is 1.128 mm (Figure E-12). Figure E-0-12 Different Distances related to Bondwire Set 4 & Set 5 Figure E-13 shows the geometry of a single bondwire of set 4 which is divided into five straight segments, their lengths and heights above ground plane are also shown. Figure E-0-13 Geometry of Bondwire Set 4 Fig E-14 shows the geometry of a single bondwire of set 5 which is divided into two straight segments, their lengths and heights above ground plane are also shown. 138 Figure E-0-14 Geometry of Bondwire Set 5 Parameters of a Parallel Plate above Ground Plane ε0 * εr * w * l h μ*l*h L= w ω*μ l R = 2* * σ w C= Where w is the width, l is the length, h the height, μ and ε r are respectively the permeability and dielectric constant of the substrate between the plate and the ground plane, σ is the conductivity of the conductor. 139

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