MT-025

MT-025
MT-025
TUTORIAL
ADC Architectures VI: Folding ADCs
by Walt Kester
INTRODUCTION
The "folding" architecture is one of a number of possible serial or bit-per-stage architectures.
Various architectures exist for performing A/D conversion using one stage per bit, and the
overall concept is shown in Figure 1. A multistage pipelined subranging ADC with one bit per
stage and no error correction is basically a bit-per-stage converter. In practice, this type of
pipelined converter generally uses a 1.5 bit per stage approach to provide error correction (this is
discussed in more detail in Reference 1).
In the bit-per-stage ADC, the input signal must be held constant during the entire conversion
cycle. There are N stages, each of which have a "bit" output and a "residue" output. The residue
output of one stage is the input to the next. The last bit is detected with a single comparator as
shown.
VREF
ANALOG
INPUT
SHA
STAGE
1
BIT 1
MSB
R1
STAGE
2
BIT 2
R2
STAGE
N-1
BIT N-1
+
BIT N
LSB
DECODE LOGIC AND OUTPUT REGISTERS
N
B. D. Smith, "An Unusual Electronic Analog-Digital Conversion Method,"
IRE Transactions on Instrumentation, June 1956, pp. 155-160.
Figure 1: Generalized Bit-Per-Stage ADC Architecture
It is possible to combine the bit-per-stage architecture with other architectures. For example, the
residue output of the final stage can be further digitized by a flash converter, thereby providing
more resolution.
One of the first references to these architectures appeared in an article by B. D. Smith in 1956
(Reference 2). Smith indicates, however, that previous work had been done at M.I.T. by R. P.
Sallen in a 1949 thesis. In the article, Smith describes both the binary and the Gray (or folding)
transfer functions required to implement the A/D conversion.
Rev.A, 10/08, WK
Page 1 of 12
MT-025
BINARY AND FOLDING BIT-PER-STAGE (SERIAL) ADCs
The basic stage for performing a single binary bit conversion is shown in Figure 2. It consists of
a gain-of-two amplifier, a comparator, and a 1-bit DAC (changeover switch). Assume that this is
the first stage of the ADC. The MSB is simply the polarity of the input, and that is detected with
the comparator which also controls the 1-bit DAC. The 1-bit DAC output is summed with the
output of the gain-of-two amplifier. The resulting residue output is then applied to the next stage.
In order to better understand how the circuit works, the diagram shows the residue output for the
case of a linear ramp input voltage which traverses the entire ADC range, –VR to +VR. Notice
that the polarity of the residue output determines the binary bit output of the next stage.
+VR
RESIDUE
INPUT
Σ
G=2
INPUT
t
0
+
-VR
-
+VR
+VR
-VR
SWITCH POSITION
SHOWN FOR
NEGATIVE INPUT
RESIDUE
0
t
-VR
BIT OUTPUT
(BINARY CODE)
Figure 2: Single-Stage Transfer Function for Binary ADC
A simplified 3-bit serial-binary bit-per-stage ADC is shown in Figure 3, and the residue outputs
are shown in Figure 4. Again, the case is shown for a linear ramp input voltage whose range is
between –VR and +VR. Each residue output signal has discontinuities which correspond to the
point where the comparator changes state and causes the DAC to switch. The fundamental
problem with this architecture is the discontinuity in the residue output waveforms. Adequate
settling time must be allowed for these transients to propagate through all the stages and settle at
the final comparator input. As presented here, the prospects of making this architecture operate at
high speed are dismal. However using the 1.5-bit-per stage pipelined architecture (see Reference
1) makes it much more attractive at high speeds.
Page 2 of 12
MT-025
±VR
ANALOG
INPUT
R1
R2
STAGE
2
STAGE
1
SHA
BIT 1
+
-
BIT 2
BIT 3
OUTPUT REGISTER
3
Figure 3: 3-bit Serial ADC with Binary Output
+VR
INPUT
t
0
–VR
R1
+VR
+VR
0
t
–VR
–VR
+VR
R2
+VR
0
t
–VR
–VR
BINARY
CODE
000
001
010
011
100
101
110
111
Figure 4: Input and Residue Waveforms of 3-Bit Binary Ripple ADC
Although the binary method is discussed in his paper, B. D. Smith also describes a much
preferred bit-per-stage architecture based on absolute value amplifiers (magnitude amplifiers, or
simply MagAMPs™). This scheme has often been referred to as serial-Gray (since the output
coding is in Gray code), or folding converter because of the shape of the transfer function.
Performing the conversion using a transfer function that produces an initial Gray code output has
the advantage of minimizing discontinuities in the residue output waveforms and offers the
potential of operating at much higher speeds than the binary approach.
Page 3 of 12
MT-025
The basic folding stage is shown functionally in Figure 5 along with its transfer function. The
input to the stage is assumed to be a linear ramp voltage whose range is between –VR and +VR.
The comparator detects the polarity of the input signal and provides the Gray bit output for the
stage. It also determines whether the overall stage gain is +2 or –2. The reference voltage VR is
summed with the switch output to generate the residue signal which is applied to the next stage.
The polarity of the residue signal determines the Gray bit for the next stage. The transfer
function for the folding stage is also shown in Figure 5.
VR
INPUT
+VR
G = +2
INPUT
Σ
RESIDUE
0
t
G = -2
SWITCH POSITION
SHOWN FOR
NEGATIVE INPUT
-VR
+VR
+
RESIDUE
0
t
BIT OUTPUT
(GRAY CODE)
-VR
Figure 5: Folding Stage Functional Equivalent Circuit
A 3-bit MagAMP folding ADC is shown in Figure 6, and the corresponding residue waveforms
in Figure 7. As in the case of the binary bit-per-stage ADC, the polarity of the residue output
signal of a stage determines the value of the Gray bit for the next stage. The polarity of the input
to the first stage determines the Gray MSB; the polarity of R1 output determines the Gray bit-2;
and the polarity of R2 output determines the Gray bit-3. Notice that unlike the binary ripple
ADC, there is no abrupt transition in any of the folding stage residue output waveforms. This
makes operation at high speeds quite feasible.
Page 4 of 12
MT-025
±VR
ANALOG
INPUT
MAGAMP
2
MAGAMP
1
SHA
BIT 1
+
-
BIT 2
BIT 3
GRAY CODE REGISTER
3
GRAY-TO-BINARY CONVERTER
3
OUTPUT REGISTER
3
Figure 6: 3-bit Folding ADC Block Diagram
+VR
INPUT
t
0
–VR
R1
+VR
0
t
–VR
–VR
+VR
R2
+VR
0
t
–VR
GRAY
CODE
–VR
–VR
000
001
011
010
110
111
101
100
Figure 7: Input and Residue Waveforms for 3-Bit Folding ADC
The key to operating this architecture at high speeds is the folding stage. N. E. Chasek of Bell
Telephone Labs describes a circuit for generating the folding transfer function using nested diode
bridges in a patent filed in 1960 (Reference 3). This circuit made use of solid-state devices, but
required different reference voltages for each stage (see Figure 8). Chasek's circuit also suffered
from loss of headroom and gain when several stages were cascaded to form higher resolution
Page 5 of 12
MT-025
converters as shown in Figure 9. What is really needed to make the folding ADC work at high
resolutions is nearly ideal voltage or current rectification.
GRAY CODE OUTPUT
BIT 2
BIT 1
BIT 3
BIAS
BIAS
+
+
BALANCED
INPUT
R1
R2
+
+
BIAS
BIAS
Adapted from: N. E. Chasek, "Pulse Code Modulation Encoder,"
U.S. Patent 3,035,258, Filed November 14, 1960, Issued May 15, 1962
Figure 8: 3-Bit Folding ADC Based on N. E. Chasek's Design
+VR
INPUT
t
0
–VR
+VR/2
R1
0
t
–VR/2
–VR/2
+VR/4
R2
0
–VR/4
t
–VR/4
–VR
GRAY
CODE
000
001
011
010
110
111
101
100
Figure 9: Single-Ended Waveforms in Chasek's Folding ADC
Page 6 of 12
MT-025
F. D. Waldhaur of Bell Telephone Labs remedied the problems of Chasek's nested diode bridge
circuits in a classic patent filed in 1962 (Reference 4). Figure 10 shows Waldhaur's elegant
implementation of the folding transfer function using solid state op amps with diodes in the
feedback loop. The gain-of-two op amps allow the same reference voltages to be used for each
stage and maintain the same signal level at each residue output with nearly ideal rectification.
2R
R
IOFFSET
I
R
–
i
+
2R
BALANCED
INPUT
i
i
2i
R
2i – I
2i
BIT
OUTPUT
R
2R
BALANCED
OUTPUT
2i
i
3i
–
R
3i
2i
2i – I
+
2R
R
IOFFSET
I
Extracted from: F. D. Waldhauer, "Analog-to-digital Converter,"
U.S. Patent 3,187,325, Filed July 2, 1962, Issued June 1, 1965
Figure 10: F. D. Waldhaur's Classic Folding Stage using Rectifier Amplifiers
J. O. Edson and H. H. Henning describe the operation and performance of this type of ADC in
greater detail in a 1965 Bell System Technical Journal article (Reference 5). An operational 9-bit,
6-MSPS ADC of this type was used in experimental studies on 224-Mbit/second PCM terminals.
These terminals were supposed to handle data as well as voice signals. The voiceband objective
was to digitize an entire 600-channel, 2.4-MHz FDM band, therefore requiring a minimum
sampling rate of approximately 6 MSPS.
It is interesting to note that the experimental terminal was also supposed to handle video as well,
which required a higher sampling rate of approximately 12-MSPS. For this requirement, the
latest (and final) generation Bell Labs' electron beam coder (see Tutorial MT-020) was needed to
meet the ADC requirement, as the solid-state coder based on Waldhaur's patent did not have the
necessary accuracy at the higher sampling rates.
The first commercial ADC using Waldhaur's Gray code architecture was the 8-bit, 10-MSPS HS810 from Computer Labs, Inc., in 1966. The instrument used all discrete transistor circuits (no
ICs) and was designed to be mounted in a 19" rack as shown in Figure 11 for an early
experimental digital radar receiver application. The 8-bit, 10-MSPS converter contained its own
linear power supply, dissipated nearly 150 watts, and sold for approximately $10,000. The same
technology was used to produce 9-bit, 5-MSPS and 10-bit 3-MSPS versions. Although the next
Page 7 of 12
MT-025
generation of Computer Labs' designs would take advantage of modular op amps (Computer
Labs OA-125 and FS-125), ICs such as the Fairchild µA710/711 comparators, as well as 7400
TTL logic, the first ADCs offered used all discrete devices. These early high speed ADCs
produced by Computer Labs were primarily used in research and development projects
associated with radar receiver development by companies such as Raytheon, General Electric,
and MIT Lincoln Labs.
19" RACK-MOUNTED, 150W, $10,000.00
INSTALLATION OF 12 ADCs
IN EXPERIMENTAL DIGITAL
RADAR RECEIVER
Figure 11: HS-810, 8-bit, 10-MSPS ADC Released by Computer Labs, Inc. in 1966
The folding Gray code architecture was used in a few instrument and modular ADCs in the early
1970s, such as the HS-810, but commercial high speed ADCs primarily used either the flash or
the error-corrected subranging architecture in the 1980s. With improvements in IC processes,
there was, however, continued interest in the folding architecture in the late 1970s and
throughout the 1980s—with quite a number of experimental designs reported in the various
journals over the period (References 6-10).
Analog Devices developed the first high speed fully complementary bipolar (CB) process in the
mid-1980s, and in 1994 Frank Murden and Carl Moreland filed patents on a significantly
improved current-steering architecture for a Gray code MagAMP™-based ADC (References 1115). The technique was first implemented for building block cores in the AD9042 12-bit, 41MSPS ADC released in 1995, and refinements of the technique and a higher speed CB process,
XFCB, (References 16 and 17) pushed the core technology to 14-bits with the release of the
AD6644 14-bit 65-MSPS ADC in 1999, the AD6645 14-bit 80-MSPS ADC in 2001, and a 105MSPS version of the AD6645 in 2003. Although these ADCs use the error-corrected pipelined
subranging architecture, the internal building block core ADCs utilize the MagAMP™
architecture.
Page 8 of 12
MT-025
Modern IC circuit designs implement the transfer function using current-steering open-loop gain
techniques which can be made to operate much faster. Fully differential stages (including the
SHA) also provide speed, lower distortion, and yield 8-bit accurate folding stages with no
requirement for thin film resistor laser trimming.
An example of a fully differential gain-of-two MagAMP folding stage is shown in Figure 12 (see
References 11, 12, 14). The differential input signal is applied to the degenerated-emitter
differential pair Q1,Q2 and the comparator. The differential input voltage is converted into a
differential current which flows in the collectors of Q1, Q2. If +IN is greater than –IN, cascodeconnected transistors Q3, Q6 are on, and Q4, Q6 are off. The differential signal currents
therefore flow through the collectors of Q3, Q6 into level-shifting transistors Q7, Q8 and into the
output load resistors, developing the differential output voltage between +OUT and –OUT. The
overall differential voltage gain of the circuit is two.
2I - IOFF
2I + IOFF
Q7
VBIAS
Q3
Q8
VBIAS
Q4
Q5
Q6
+OUT
-OUT
i+
GRAY
-
+
+IN
i-
GRAY
-IN
Q2
Q1
R
R
I
R
I
Figure 12: A Modern Current-Steering MagAMP™ Stage
If +IN is less than –IN (negative differential input voltage), the comparator changes state and
turns Q4, Q5 on and Q3, Q6 off. The differential signal currents flow from Q5 to Q7 and from
Q4 to Q8, thereby maintaining the same relative polarity at the differential output as for a
positive differential input voltage. The required offset voltage is developed by adding a current
IOFF to the emitter current of Q7 and subtracting it from the emitter current of Q8.
The differential residue output voltage of the stage drives the next stage input, and the
comparator output represents the Gray code output for the stage.
Page 9 of 12
MT-025
The MagAMP architecture offers lower power and can be extended to sampling rates previously
dominated by flash converters. For example, the AD9054A 8-bit, 200-MSPS ADC is shown in
Figure 13 and was first introduced in 1997. The device is fabricated on a high speed
complementary bipolar process, and power dissipation is 500 mW. The first five bits (Gray code)
are derived from five differential MagAMP stages. The differential residue output of the fifth
MagAMP stage drives a 3-bit flash converter, rather than a single comparator.
The Gray-code output of the five MagAMPs and the binary-code output of the 3-bit flash are
latched, all converted into binary, and latched again in the output data register. Because of the
high data rate, a demultiplexed output option is provided.
ANALOG
INPUT
SHA
DIFFERENTIAL
OUTPUTS ON
BITS 1 - 5
MAGAMP
1
MAGAMP
2
BIT
1
GRAY
BIT
2
GRAY
MAGAMP
3
BIT
3
GRAY
REGISTER
MAGAMP
4
MAGAMP
5
BIT
4
GRAY
BIT
5
GRAY
3-BIT
FLASH
ADC
3
BINARY
5
GRAY-TO-BINARY CONVERTER
3
5
OUTPUT REGISTERS
8
Figure 13: AD9054A 8-bit, 200-MSPS ADC Introduced in 1997
Recent introductions in the 8-bit high speed area have utilized CMOS processes and the
pipelined subranging architecture, such as the 8-bit 250 MSPS, AD9480 (LVDS outputs) and
AD9481 (demuxed CMOS outputs) which dissipate 700 mW and 600 mW, respectively.
SUMMARY
Although initially used in pioneering instrument ADCs at Bell Labs and Computer Labs in the
1960s, the flash the pipelined subranging architectures have dominated the high speed ADC
marketplace. Although there have been a number of ICs designed using the folding architecture,
it has never attained the popularity of the pipelined subranging ADC. Nevertheless, it is
important to know that it exists because it may regain popularity in the future as IC processes
evolve.
Page 10 of 12
MT-025
REFERENCES
1.
Walt Kester, Analog-Digital Conversion, Analog Devices, 2004, ISBN 0-916550-27-3, Chapter 3.
available as The Data Conversion Handbook, Elsevier/Newnes, 2005, ISBN 0-7506-7841-0, Chapter 3.
Also
2.
B. D. Smith, "An Unusual Electronic Analog-Digital Conversion Method," IRE Transactions on
Instrumentation, June 1956, pp. 155-160. (possibly the first published description of the binary-coded and
Gray-coded bit-per-stage ADC architectures. Smith mentions similar work partially covered in R. P. Sallen's
1949 thesis at M.I.T.).
3.
N. E. Chasek, "Pulse Code Modulation Encoder," U.S. Patent 3,035,258, filed November 14, 1960, issued May
15, 1962. (an early patent showing a diode-based circuit for realizing the Gray code folding transfer function).
4.
F. D. Waldhauer, "Analog-to-Digital Converter," U.S. Patent 3,187,325, filed July 2, 1962, issued June 1, 1965.
(a classic patent using op amps with diode switches in the feedback loops to implement the Gray code folding
transfer function).
5.
J. O. Edson and H. H. Henning, "Broadband Codecs for an Experimental 224Mb/s PCM Terminal," Bell System
Technical Journal, Vol. 44, pp. 1887-1940, Nov. 1965. (a further description of a 9-bit ADC based on
Waldhauer's folding stage).
6.
Udo Fiedler and Dieter Seitzer, "A High-Speed 8 Bit A/D Converter Based on a Gray-Code Multiple Folding
Circuit," IEEE Journal of Solid-State Circuits, Vol. SC-14, No. 3, June 1979, pp. 547-551. (an early monolithic
folding ADC).
7.
Rudy J. van de Plassche and Rob E. J. van de Grift, "A High-Speed 7 Bit A/D Converter," IEEE Journal of
Solid-State Circuits, Vol. SC-14, No. 6, December 1979, pp. 938-943. (a monolithic folding ADC).
8.
Rob. E. J. van de Grift and Rudy J. van de Plassche, "A Monolithic 8-bit Video A/D Converter, IEEE Journal
of Solid State Circuits, Vol. SC-19, No. 3, June 1984, pp. 374-378. (a monolithic folding ADC).
9.
Rob. E. J. van de Grift, Ivo W. J. M. Rutten and Martien van der Veen, "An 8-bit Video ADC Incorporating
Folding and Interpolation Techniques," IEEE Journal of Solid State Circuits, Vol. SC-22, No. 6, December
1987, pp. 944-953. (another monolithic folding ADC).
10. Rudy van de Plassche, Integrated Analog-to-Digital and Digital-to-Analog Converters, Kluwer Academic
Publishers, 1994, pp. 148-187. (a good textbook on ADCs and DACs with a section on folding ADCs indicated
by the referenced page numbers).
11. Carl Moreland, "An 8-bit 150 MSPS Serial ADC," 1995 ISSCC Digest of Technical Papers, Vol. 38, p. 272. (a
description of an 8-bit ADC with 5 folding stages followed by a 3-bit flash converter).
12. Carl Moreland, An Analog-to-Digital Converter Using Serial-Ripple Architecture, Masters' Thesis, Florida
State University College of Engineering, Department of Electrical Engineering, 1995. (Moreland's early work
on folding ADCs).
13. Frank Murden, "Analog to Digital Converter Using Complementary Differential Emitter Pairs," U.S. Patent
5,550,492, filed December 1, 1994, issued August 27, 1996. (a description of an ADC based on the MagAMP
folding stage).
14. Carl W. Moreland, "Analog to Digital Converter Having a Magnitude Amplifier with an Improved Differential
Input Amplifier," U.S. Patent 5,554,943, filed December 1, 1994, issued September 10, 1996. (a description of
an 8-bit ADC with 5 folding stages followed by a 3-bit flash converter).
Page 11 of 12
MT-025
15. Frank Murden and Carl W. Moreland, "N-bit Analog-to-Digital Converter with N-1 Magnitude Amplifiers and
N Comparators," U.S. Patent 5,684,419, filed December 1, 1994, issued November 4, 1997. (another patent on
the MagAMP folding architecture applied to an ADC).
16. Carl Moreland, Frank Murden, Michael Elliott, Joe Young, Mike Hensley, and Russell Stop, "A 14-bit 100Msample/s Subranging ADC, IEEE Journal of Solid State Circuits, Vol. 35, No. 12, December 2000, pp. 17911798. (describes the architecture used in the 14-bit AD6645 ADC).
17. Frank Murden and Michael R. Elliott, "Linearizing Structures and Methods for Adjustable-Gain Folding
Amplifiers," U.S. Patent 6,172,636B1, filed July 13, 1999, issued January 9, 2001. (describes methods for
trimming the folding amplifiers in an ADC).
Copyright 2009, Analog Devices, Inc. All rights reserved. Analog Devices assumes no responsibility for customer
product design or the use or application of customers’ products or for any infringements of patents or rights of others
which may result from Analog Devices assistance. All trademarks and logos are property of their respective holders.
Information furnished by Analog Devices applications and development tools engineers is believed to be accurate
and reliable, however no responsibility is assumed by Analog Devices regarding technical accuracy and topicality of
the content provided in Analog Devices Tutorials.
Page 12 of 12
Was this manual useful for you? yes no
Thank you for your participation!

* Your assessment is very important for improving the work of artificial intelligence, which forms the content of this project

Download PDF

advertisement