Low Power, 8-/16-Channel, 31.25 kSPS, 24-Bit, Highly Integrated Sigma-Delta ADC AD7173-8 Data Sheet

Data Sheet

Low Power, 8-/16-Channel, 31.25 kSPS,

24-Bit, Highly Integrated Sigma-Delta ADC

AD7173-8

FEATURES

Low power, 8-/16-channel, highly integrated multiplexed analog-to-digital converter (ADC)

Integration

Precision analog input buffers and reference input buffers

2.5 V precision reference (3.5 ppm/°C)

Cross point multiplexer (enable system diagnostic)

8 full differential or 16 single-ended channels

Clock oscillator

GPIO and GPO pins with automatic external mux control

Fast and flexible output rate: 1.25 SPS to 31.25 kSPS

Channel scan data rate: 6.21 kSPS/channel (161 µs settling)

Performance specifications

17.5 noise free bits at 31.25 kSPS

24 noise free bits at 1.25 SPS

INL: ±3 ppm/FSR

85 dB rejection of 50 Hz and 60 Hz with 50 ms settling

Operates with either 3.3 V or5 V supply

Single supply

3.3 V or 5 V AVDD1, 2 V to 5 V AVDD2, and 2 V to 5 V IOVDD

Optional split supply

AVDD1 and AVSS ± 2.5 V or AVDD1 and AVSS ± 1.65 V

Current: 1.4 mA

3-/4-wire serial digital interface (Schmitt trigger on SCLK)

CRC error checking

SPI, QSPI, MICROWIRE, and DSP compatible

Package: 40-lead 6 mm × 6 mm LFCSP

Temperature range: −40°C to +105°C

APPLICATIONS

Process control: PLC/DCS modules

Voltage, current, temperature, and pressure measurement

Flow meters

Medical and scientific multichannel instrumentation

Seismic instrumentation

Chemical analysis instrumentation: chromatography

GENERAL DESCRIPTION

Fast settling, highly accurate, low power, 8-/16-channel, multiplexed ADC for low bandwidth input signals with integrated input buffers.

Integrated precision, 2.5 V, low drift (3.5 ppm/°C), band gap reference and integrated oscillator.

Eight flexible setups with configurability for output data rate, digital filter mode, offset/gain error correction, reference selection, buffer enables and more. This per channel configurability extends to the output data rate used for each channel when using sinc5 + sinc1 filter.

Sinc5 + sinc1 filter maximizes channel scan rate, and sinc3 filter maximizes resolution and enhanced 50 Hz/60 Hz rejection, with four selectable options to maximize rejection.

Integrated diagnostic features, including CRC, register checksum, temperature sensor, crosspoint multiplexer, burnout currents, and GPIOs/GPOs.

FUNCTIONAL BLOCK DIAGRAM

AVDD1 AVDD2 REGCAPA REF– REF+ REFOUT IOVDD REGCAPD

1.8V

LDO

CROSSPOINT

MULTIPLEXER

REFERENCE

INPUT

BUFFERS

BUFFERED

PRECISION

REFERENCE

1.8V

LDO

INT

REF

AIN0/REF2–

AVDD ANALOG

INPUT

BUFFERS

AIN1/REF2+

AIN15

Σ-Δ ADC

DIGITAL

FILTER

SERIAL

INTERFACE

AND CONTROL

CS

SCLK

DIN

DOUT/RDY

SYNC

ERROR

AIN16

AVSS

I/O AND EXTERNAL

MUX CONTROL

XTAL AND INTERNAL

CLOCK OSCILLATOR

CIRCUITRY

AD7173-8

TEMPERATURE

SENSOR

AVSS PDSW GPIO0 GPIO1 GPO2 GPO3

Figure 1.

XTAL1 XTAL2/CLKIO

Rev. A Document Feedback

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Tel: 781.329.4700

Technical Support

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AD7173-8

TABLE OF CONTENTS

Features .............................................................................................. 1

Applications ....................................................................................... 1

General Description ......................................................................... 1

Functional Block Diagram .............................................................. 1

Revision History ............................................................................... 3

Specifications ..................................................................................... 4

Timing Characteristics ................................................................ 8

Absolute Maximum Ratings ............................................................ 9

Thermal Resistance ...................................................................... 9

ESD Caution .................................................................................. 9

Pin Configuration and Function Descriptions ........................... 10

Typical Performance Characteristics ........................................... 12

Noise Performance and Resolution .............................................. 18

Getting Started ................................................................................ 19

Power Supplies ............................................................................ 20

Digital Communication ............................................................. 20

Configuration Overview ........................................................... 22

Circuit Description ......................................................................... 27

Analog Input ............................................................................... 27

Reference Options ...................................................................... 29

Clock Source ............................................................................... 29

Digital Filters ................................................................................... 31

Sinc5 + Sinc1 Filter ..................................................................... 31

Sinc3 Filter ................................................................................... 32

Single Cycle Settling ................................................................... 33

Enhanced 50 Hz and 60 Hz Rejection Filters ......................... 33

Operating Modes ............................................................................ 36

Continuous Conversion Mode ................................................. 36

Continuous Read Mode ............................................................. 37

Single Conversion Mode ........................................................... 38

Standby and Power-Down Modes ............................................ 39

Calibration Modes ...................................................................... 39

Digital Interface .............................................................................. 40

Checksum Protection ................................................................. 40

CRC Calculation ......................................................................... 41

Integrated Functions ...................................................................... 43

Data Sheet

General-Purpose I/O ................................................................. 43

External Multiplexer Control ................................................... 43

Delay ............................................................................................ 43

16-Bit/24-Bit Conversions ......................................................... 43

Serial Interface Reset (DOUT_RESET) .................................. 43

Synchronization .......................................................................... 43

Error Flags ................................................................................... 44

DATA_STAT ............................................................................... 44

IOSTRENGTH Bit ..................................................................... 44

Grounding and Layout .................................................................. 45

Register Summary .......................................................................... 46

Register Details ............................................................................... 48

Communications Register ......................................................... 48

Status Register ............................................................................. 50

ADC Mode Register ................................................................... 51

Interface Mode Register ............................................................ 52

Register Check ............................................................................ 53

Data Register ............................................................................... 53

GPIO Configuration Register ................................................... 54

ID Register................................................................................... 55

Channel Register 0 ..................................................................... 55

Channel Register 1 to Channel Register 15 ............................ 57

Setup Configuration Register 0 ................................................ 58

Setup Configuration Register 1 to Setup Configuration

Register 7 ..................................................................................... 59

Filter Configuration Register 0 ................................................. 60

Filter Configuration Register 1 to Filter Configuration

Register 7 ..................................................................................... 61

Offset Register 0 ......................................................................... 62

Offset Register 1 to Offset Register 7 ....................................... 62

Gain Register 0............................................................................ 62

Gain Register 1 to Gain Register 7 ........................................... 62

Outline Dimensions ....................................................................... 63

Ordering Guide .......................................................................... 63

Rev. A | Page 2 of 64

Data Sheet

REVISION HISTORY

4/14—Rev. 0 to Rev. A

Changes to General Description and Functional Block

Diagram .............................................................................................. 1

Moved Revision History ................................................................... 3

Changes to Figure 18 ...................................................................... 14

Changes to Getting Started Section .............................................. 19

Change to Table 11 .......................................................................... 23

Change to Table 17 .......................................................................... 29

Changes to Digital Filters Section ................................................. 31

Replaced Diagnostics Section with Integrated Function

Section .............................................................................................. 43

Changes to Address 0x02, Table 22 ............................................... 46

Changes to Bit 10, Table 26 ............................................................ 52

Changes to Bits[6:5], Table 35 ....................................................... 60

10/13—Revision 0: Initial Version

AD7173-8


AD7173-8 Data Sheet

SPECIFICATIONS

AVDD1 = 3.0 V to 5.5 V, AVDD2 = 2 V to 5.5 V, IOVDD = 2 V to 5.5 V, AVSS = DGND = 0 V, REF+ = 2.5 V, REF− = AVSS, internal master clock = 2 MHz, T

A

= T

MIN

to T

MAX

, unless otherwise noted.

Table 1.

Parameter

ADC SPEED AND PERFORMANCE

Output Data Rate (ODR)

No Missing Codes 1

Resolution

Noise

Noise Free Resolution

Test Conditions/Comments

Excluding sinc3 filter at 31.25 kSPS

See Table 6

See Table 6

Sinc5 + sinc1 filter (default)

31.25 kSPS, REF+ = 5 V

2.6 kSPS, REF+ = 5 V

1.25 SPS, REF+ = 5 V

Min

1.25

24

Typ

17.5

18.4

24

Max

31250

Unit

SPS

Bits

Bits

Bits

Bits

ACCURACY

Integral Nonlinearity (INL) ±7.5

Offset Error 2

Offset Drift

Offset Drift vs. Time 3

Gain Error 2

Gain Drift vs. Temperature 1

Gain Drift vs. Time

3

2.5 V reference

5 V reference

Internal short

Internal short

25°C, AVDD1 = 5 V

±3

±5

±40

±350

±450

±10

±0.5

±3

±50

±1 ppm/FSR ppm/FSR

µV nV/°C nV/1000 hrs ppm/FSR ppm/FSR/°C ppm/FSR/

1000 hrs

REJECTION

Power Supply Rejection

Common-Mode Rejection

At DC

At 50 Hz and 60 Hz

1

AVDD1 and AVDD2, V

IN

= 1 V

V

IN

= 0.1 V

95

120

90 dB dB dB

Normal Mode Rejection 1

20 SPS ODR (post filter); 50 Hz ± 1 Hz and

60 Hz ± 1 Hz

50 Hz ± 1 Hz and 60 Hz ± 1 Hz

Internal clock, 20 SPS ODR (post filter)

External clock, 20 SPS ODR (post filter)

71

85

90

90 dB dB

ANALOG INPUTS

Differential Input Voltage Range

Absolute AIN Voltage Limits 1

Buffers Disabled

Buffers Enabled

Analog Input Current

Buffers Enabled

Input Current

Input Current Drift

Buffers Disabled

Input Current

Input Current Drift

Crosstalk

INTERNAL REFERENCE

Output Voltage

Initial Accuracy 1

Temperature Coefficient

0°C to +105°C

−40°C to +105°C

Reference Load Current, I

LOAD

Single cycle settling enabled (default)

External clock

Internal clock (±2.5% clock)

1 kHz input

100 nF external capacitor on REFOUT to AVSS

REFOUT with respect to AVSS

T

A

= 25°C 4

I

L

AVSS − 0.05

AVSS

−0.1

−10

±V

REF

±2

±25

±6

±0.1

±0.5

−120

2.5

3.5

3.5

V

AVDD1 + 0.05 V

AVDD1 − 1.1 V

+0.1

8

10

+10 nA pA/°C

µA/V nA/V/°C nA/V/°C dB

V

% of V ppm/°C ppm/°C mA


Data Sheet AD7173-8

Parameter

Power Supply Rejection

(Line Regulation)

Load Regulation

Voltage Noise

Voltage Noise Density

Turn-On Settling Time

Long-Term Stability

3

Short Circuit

EXTERNAL REFERENCE

Reference Input Voltage

Absolute Reference Input Voltage

Limits 1

Buffers Disabled

Buffers Enabled

Average Reference Input Current

I


AVDD1 and AVDD2

∆V e

N

OUT

/∆I

L

, 0.1 Hz to 10 Hz e

N

, 1 kHz

100 nF capacitor

1000 hours

SC

Reference input = (REF+) − (REF−)

Buffers Disabled

Buffers Enabled

Average Reference Input Current Drift Buffers disabled

External clock

Internal clock

Normal Mode Rejection 1

Common-Mode Rejection

See the Rejection parameter

TEMPERATURE SENSOR

Accuracy

Sensitivity

After user calibration at 25°C

BURNOUT CURRENTS

Source/Sink Current

BRIDGE POWER-DOWN SWITCH

R

ON

Allowable Currents

GENERAL-PURPOSE I/O (GPIO0, GPIO1,

GPO2, GPO3)

Input Mode Leakage Current 1

Floating State Output Capacitance

AVDD1 − AVSS = 5 V

Output High Voltage, V

OH

1

Output Low Voltage, V

OL

1

Input High Voltage, V

IH

1

Input Low Voltage, V

IL

1

AVDD1 − AVSS = 3.3 V


OH

1


OL

1


IH

1


IL

1

CLOCK

Internal Clock

Frequency

Accuracy

Duty Cycle


OL


OH

Crystal

Frequency

Start-Up Time

External Clock (CLKIO)

Duty Cycle

1

I

I

I

I

Analog input buffers must be enabled

With respect to AVSS

SOURCE

SINK

= 800 µA

SOURCE

SINK

= 200 µA

= 200 µA

= 800 µA

Typical duty cycle 50:50 (maximum:minimum)

Min

1

AVSS − 0.05

AVSS

−10

AVSS + 4

AVSS + 3

AVSS + 2.7

AVSS + 2

−2.5

0.8 × IOVDD

14

30:70


5

2

50:50

16

10

2

50:50

Typ

90

140

6.5

215

60

460

25

2.5

±9

±50

±5

±6

83

±2

477

±10

24

Max

AVDD1

AVDD1 + 0.05 V

AVDD1 V

µA/V nA nA/V/°C nA/V/°C dB

16

°C

µV/°C

µA

Ω mA

+10

AVSS + 0.4

AVSS + 0.7

AVSS + 0.27

AVSS + 0.45

+2.5

0.4

16.384

2.048

70:30

MHz

%

V

V

MHz

µs

MHz

Unit

dB ppm/mA

µV rms nV/√Hz

µs ppm mA

V

µA pF

V

V

V

V

V

V

V

V

AD7173-8

Parameter

LOGIC INPUTS


INH

1


INL

1

Hysteresis 1

Leakage Currents

LOGIC OUTPUT (DOUT/RDY)


OH

1


OL

1

Leakage Current

Output Capacitance

SYSTEM CALIBRATION 1

Full-Scale Calibration Limit

Zero-Scale Calibration Limit

Input Span

POWER REQUIREMENTS

Power Supply Voltage

AVDD1 − AVSS

AVDD2 − AVSS

AVSS − DGND

IOVDD − DGND

IOVDD − AVSS

POWER SUPPLY CURRENTS

Full Operating Mode

AVDD1 Current

AVDD1 = 5 V Typical,

5.5 V Maximum

AVDD1 = 3.3 V Typical,

3.6 V Maximum 1

AVDD2 Current

IOVDD Current

Standby Mode

Standby (LDO on)

Power-Down Mode


2 V ≤ IOVDD ≤ 2.3 V

2.3 V ≤ IOVDD ≤ 5.5 V

2 V ≤ IOVDD ≤ 2.3 V

2.3 V ≤ IOVDD ≤ 5.5 V

IOVDD > 2.7 V

IOVDD < 2.7 V

IOVDD ≥ 4.5 V, I

SOURCE

= 1 mA

2.7 V ≤ IOVDD < 4.5 V, I

SOURCE

= 500 μA

IOVDD < 2.7 V, I

SOURCE

= 200 μA

IOVDD ≥ 4.5 V, I

SINK

= 2 mA

2.7 V ≤ IOVDD < 4.5 V, I

SINK

= 1 mA

IOVDD < 2.7 V, I

SINK

= 400 μA

Floating state

Floating state

For AVSS < DGND

All outputs unloaded

AIN± and REF± buffers disabled; external reference

AIN± and REF± buffers disabled; internal reference

AIN± and REF± buffers enabled; external reference

Each enabled buffered pair: AIN+, AIN− and

REF+, REF−

AIN± and REF± buffers disabled; external reference

AIN± and REF± buffers disabled; internal reference

AIN± and REF± buffers enabled; external reference

Each enabled buffered pair: AIN+, AIN− and

REF+, REF−

External reference

Internal reference

External clock

Internal clock

External crystal

Reference off, total current consumption

Reference on, total current consumption

Full power-down, LDO, REF±


3.0

2

−2.75

2

Min

0.65 × IOVDD

0.7 × IOVDD

Typ

0.08

0.04

−10

0.8 × IOVDD

0.8 × IOVDD

0.8 × IOVDD

−10

−1.05 × FS

0.8 × FS

10

Data Sheet

Max Unit

V

V

0.35 × IOVDD V

0.7

0.25

0.2

+10

V

V

V

µA

0.4

0.4

0.4

+10

1.05 × FS

2.1 × FS

V

V

V

V

V

µA pF

V

V

V

V

5.5

5.5

0

5.5

6.35

V

V

V

V

V

0.16

0.34

1.9

0.87

1

1.25

0.24

0.52

0.9

0.23

0.42

2.12

0.945

25

400

2

0.19

0.4

2.45

1.13

1.15

1.4

0.39

0.76

0.27

0.49

2.71

1.22

10 mA mA mA mA mA mA mA mA mA mA mA mA mA

µA

µA

µA


Parameter

POWER DISSIPATION

Full Operating Mode

Standby Mode

Power-Down Mode


Unbuffered, external clock and reference;

AVDD1 = 3.3 V, AVDD2 = 2 V, IOVDD = 2 V

Unbuffered, external clock and reference; all supplies = 5 V

Unbuffered, external clock and reference; all supplies = 5.5 V

Fully buffered, internal clock and reference

(note that REFOUT has no load); AVDD1 = 3.3 V,

AVDD2 = 2 V, IOVDD = 2 V


(note that REFOUT has no load); all supplies =

5 V


(note that REFOUT has no load); all supplies =

5.5 V

Reference off, all supplies = 5 V

Reference on, all supplies = 5 V

Full power-down, all supplies = 5 V

Full power-down, all supplies = 5.5 V

Min Typ

3

7.35

10.4

20.4

125

2

10

Max

9.96

28

Unit

mW mW mW mW mW mW

µW mW

µW

µW 55

1

Specification is not production tested but is supported by characterization data at the initial product release.

2 Following a system or internal zero-scale calibration, the offset error is in the order of the noise for the programmed output data rate selected. A system full-scale

3 calibration reduces the gain error to the order of the noise for the programmed output data rate.

This specification is noncumulative and includes MSL preconditioning effects.

4

This specification includes MSL preconditioning effects.



TIMING CHARACTERISTICS

IOVDD = 2 V to 5.5 V, DGND = 0 V, Input Logic 0 = 0 V, Input Logic 1 = IOVDD, C

LOAD

= 20 pF, unless otherwise noted.

Table 2.

Parameter

SCLK PULSE WIDTH t

3 t

4

READ OPERATION t

1

Limit at T

MIN

, T

MAX

25

25

Unit

ns min ns min

Test Conditions/Comments 1, 2

SCLK high pulse width

SCLK low pulse width

t

2

3

t

5

5

0

15

40

0

12

25

2.5

20

0

10 ns min ns max ns max ns min ns max ns max ns min ns max ns min ns min

CS falling edge to DOUT/RDY active time

IOVDD = 4.5 V to 5.5 V

IOVDD = 2 V to 3.6 V

SCLK active edge to data valid delay 4

IOVDD = 4.5 V to 5.5 V

IOVDD = 2 V to 3.6 V

Bus relinquish time after CS inactive edge

SCLK inactive edge to CS inactive edge

SCLK inactive edge to DOUT/RDY high/low t

6 t

7

WRITE OPERATION t

8 t

9 t

10 t

11

0

8

8

5 ns min ns min ns min ns min

CS falling edge to SCLK active edge setup time 4

Data valid to SCLK edge setup time

Data valid to SCLK edge hold time

CS rising edge to SCLK edge hold time

1 Sample tested during initial release to ensure compliance.

2

See Figure 2 and Figure 3.

3 The time required for the output to cross the V

OL

or V

4 The SCLK active edge is the falling edge of SCLK.

OH

limits.

5 RDY returns high after a read of the data register. In single conversion mode and continuous conversion mode, the same data can be read again, if required, while RDY is high. It is important to ensure that subsequent reads do not occur close to the next output update. If the continuous read feature is enabled, the digital word can be read only once.

Timing Diagrams

CS (I) t

6 t

1 t

5

DOUT/RDY (O)

MSB t

2

LSB t

7 t

3

SCLK (I) t

4

I = INPUT, O = OUTPUT

Figure 2. Read Cycle Timing Diagram

CS (I) t

8 t

11

SCLK (I)

DIN (I) t

9 t

10

MSB LSB

I = INPUT, O = OUTPUT

Figure 3. Write Cycle Timing Diagram


Data Sheet

ABSOLUTE MAXIMUM RATINGS

T

A

= 25°C, unless otherwise noted.

Table 3.

Parameter

AVDD1, AVDD2 to AVSS

AVDD1 to DGND

IOVDD to DGND

IOVDD to AVSS

AVSS to DGND

Analog Input Voltage to AVSS

Reference Input Voltage to AVSS

Digital Input Voltage to DGND

Digital Output Voltage to DGND

AIN[16:0] or Digital Input Current

Operating Temperature Range

Storage Temperature Range

Maximum Junction Temperature

Lead Soldering, Reflow Temperature

ESD Rating (HBM)

Rating

−0.3 V to +6.5 V

−0.3 V to +6.5 V

−0.3 V to +6.5 V

−0.3 V to +7.5 V

−3.25 V to +0.3 V

−0.3 V to AVDD1 + 0.3 V

−0.3 V to AVDD1 + 0.3 V

−0.3 V to IOVDD + 0.3 V

−0.3 V to IOVDD + 0.3 V

10 mA

−40°C to +105°C

−65°C to +150°C

150°C

260°C

4 kV

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

AD7173-8

THERMAL RESISTANCE

θ

JA

is specified for a device soldered on a JEDEC test board for

surface-mount packages. The values listed in Table 4 are based

on simulated data.

Table 4. Thermal Resistance

Package Type θ

JA

Unit

40-Lead, 6 mm × 6 mm LFCSP

1-Layer JEDEC Board 114 °C/W

4-Layer JEDEC Board 54

4-Layer JEDEC Board with 16 Thermal Vias 34

°C/W

°C/W

ESD CAUTION


AD7173-8

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

AIN16

AIN0/REF2–

AIN1/REF2+

AIN2

AIN3

REFOUT

REGCAPA

AVSS

AVDD1

AVDD2

8

9

10

5

6

7

1

2

3

4

AD7173-8

TOP VIEW

(Not to Scale)

30 AIN8

29 AIN7

28 AIN6

27 AIN5

26 AIN4

25 GPO2

24 GPIO1

23 GPIO0

22 REGCAPD

21 DGND

Data Sheet

NOTES

1. THE EXPOSED PAD SHOULD BE SOLDERED TO A SIMILAR PAD ON THE PCB

UNDER THE EXPOSED PAD TO CONFER MECHANICAL STRENGTH AND FOR

HEAT DISSIPATION. THE EXPOSED PAD MUST BE CONNECTED TO AVSS

THROUGH THIS PAD ON THE PCB.

Figure 4. Pin Configuration

8

9

10

11

4

5

6

7

12

13

Table 5. Pin Function Descriptions

Pin

No. Mnemonic

Type 1 Description

1

2

3

14

AIN16

AIN0/REF2−

AIN1/REF2+

AIN2

AIN3

REFOUT

REGCAPA

AVSS

AVDD1

AVDD2

PDSW

AI

AI

AI

AI

AI

AO

AO

P

P

P

AO

Analog Input 16. Selectable through cross point mux.

Analog Input 0 (AIN0)/Reference 2, Negative Input (REF2−). An external reference can be applied between

REF2+ and REF2−. REF2− can span from AVSS to AVDD1 − 1 V. Analog Input 0 is selectable through cross point mux. Reference 2 can be selected through the REFSEL bits in the setup configuration register.

Analog Input 1 (AIN0)/Reference 2, Positive Input (REF2+). An external reference can be applied between

REF2+ and REF2−. REF2+ can span from AVDD1 to AVSS + 1 V. Analog Input 1 is selectable through cross point mux. Reference 2 can be selected through the REFSEL bits in the setup configuration register.



Buffered Output of Internal Reference. The output is 2.5 V with respect to AVSS.

Analog LDO Regulator Output. Decouple this pin to AVSS using a 1 µF capacitor.

Negative Analog Supply. This supply ranges from 0 V to −2.75 V and is nominally set to 0 V.

Analog Supply Voltage 1. This voltage ranges from 3.0 V minimum to 5.5 V maximum with respect to AVSS.

Analog Supply Voltage 2. This voltage ranges from 2 V to AVDD1 with respect to AVSS.

Power-Down Switch Connected to AVSS. This pin is controlled by the PDSW bit in the GPIOCON register.

XTAL1 AI Input 1 for Crystal.

XTAL2/CLKIO AI/DI Input 2 for Crystal (XTAL2)/Clock Input or Output (CLKIO). See the CLOCKSEL bit settings in the ADCMODE

register (Table 25) for more information.

DOUT/RDY DO Serial Data Output (DOUT)/Data Ready Output (RDY). This pin serves a dual purpose. It functions as a serial data output pin to access the output shift register of the ADC. The output shift register can contain data from any of the on-chip data or control registers. The data-word/control word information is placed on the

DOUT/RDY pin on the SCLK falling edge and is valid on the SCLK rising edge. When CS is high, the DOUT/RDY output is tristated. When CS is low, and a register is not being read, DOUT/RDY operates as a data ready pin, going low to indicate the completion of a conversion. If the data is not read after the conversion, the pin goes high before the next update occurs. The DOUT/RDY falling edge can be used as an interrupt to a processor, indicating that valid data is available.



33

34

35

36

29

30

31

32

23

24

25

26

27

28

37

38

39

GPIO0

GPIO1

GPO2

AIN4

AIN5

AIN6

AIN7

AIN8

AIN9

AIN10

AIN11

AIN12

AIN13

AIN14

AIN15

GPO3

REF−

Pin

No.

15

16

17

18

19

20

21

22

40

Mnemonic

DIN

SCLK

CS

ERROR

SYNC

IOVDD

DGND

REGCAPD

REF+

EP

Type 1 Description

DI

DI

Serial Data Input to the Input Shift Register on the ADC. Data in this shift register is transferred to the control registers in the ADC, with the register address (RA) bits of the communications register identifying the appropriate register. Data is clocked in on the rising edge of SCLK.

Serial Clock Input. This serial clock input is for data transfers to and from the ADC. SCLK has a Schmitt trigger input, making the interface suitable for opto-isolated applications.

DI Chip Select Input. This is an active low logic input used to select the ADC. CS can be used to select the ADC in systems with more than one device on the serial bus. CS can be hardwired low, allowing the ADC to operate in 3-wire mode with SCLK, DIN, and DOUT used to interface with the device. When CS is high, the

DOUT/RDY output is tristated.

DI/O This pin can be used in one of the following three modes:

Active low error input mode. This mode sets the ADC_ERROR bit in the STATUS register.

Active low, open-drain error output mode. The STATUS register error bits are mapped to the ERROR pin.

The ERROR pins of multiple devices can be wired together to a common pull-up resistor so that an error on any device can be observed.

General-purpose output mode. The status of the pin is controlled by the ERR_DAT bit in the GPIOCON register.

The pin is referenced between IOVDD and DGND, as opposed to the AVDD1 and AVSS levels used by the

GPIO1 and GPIO2 pins. The ERROR pin has an active pull-up in this case.

AI

AI

AI

AI

AI

DO

AI

AI

AI

AI

AI

AI

AI

AI

DI

P

P

AO

Synchronization Input. Allows synchronization of the digital filters and analog modulators when using multiple AD7173-8 devices.

Digital I/O Supply Voltage. IOVDD voltage ranges from 2 V to 5 V. IOVDD is independent of AVDD1 and

AVDD2. For example, IOVDD can be operated at 3.3 V when AVDD1 or AVDD2 equals 5 V, or vice versa. If

AVSS is set to −2.5 V, the voltage on IOVDD must not exceed 3.6 V.

Digital Ground.

Digital LDO Regulator Output. This pin is for decoupling purposes only. Decouple this pin to DGND using a 1 µF capacitor.

DI/O General-Purpose Input/Output. Logic input/output on this this pin is referred to the AVDD1 and AVSS supplies.

DI/O General-Purpose Input/Output. Logic input/output on this this pin is referred to the AVDD1 and AVSS supplies.

DO General-Purpose Output. Logic output on this this pin is referred to the AVDD1 and AVSS supplies.








AI

P






General-Purpose Output. Logic output on this this pin is referred to the AVDD1 and AVSS supplies.

Reference 1 Input Negative Terminal. REF− can span from AVSS to AVDD1 − 1 V. Reference 1 can be selected through the REFSEL bits in the SETUP CONFIGURATION register.

Reference 1 Input Positive Terminal. An external reference can be applied between REF+ and REF−. REF+ can span from AVDD1 to AVSS + 1 V. Reference 1 can be selected through the REFSEL bits in the SETUP

CONFIGURATION register.

Exposed Pad. The exposed pad should be soldered to a similar pad on the PCB under the exposed paddle to confer mechanical strength to the package and for heat dissipation. The exposed pad must be connected to AVSS through this pad on the PCB.

1 AI = analog input, AO = analog output, DI/O = bidirectional digital input/output, DO = digital output, DI = digital input, P = power supply.


AD7173-8

TYPICAL PERFORMANCE CHARACTERISTICS

AVDD1 = 5 V, AVDD2 = 5 V, IOVDD = 3.3 V, unless otherwise noted.

8388539

Data Sheet

8388538

8388537

8388536

0 100 200 300 400 500 600 700 800 900 1000

SAMPLE

Figure 5. Noise

(Output Data Rate = 1.25 SPS, Analog Input Buffers Disabled)

8388551

8388550

8388549

8388548

0 100 200 300 400 500 600 700 800 900 1000

SAMPLE

Figure 6. Noise

(Output Data Rate = 1.25 SPS, Analog Input Buffers Enabled)

8388580

8388570

8388560

8388550

8388540

8388530

8388520

8388510

8388500

8388490

0 100 200 300 400 500 600 700 800 900 1000

SAMPLE

Figure 7. Noise

(Output Data Rate = 10 kSPS, Analog Input Buffers Disabled)


50

40

30

20

10

0

700

600

500

400

300

200

100

0

8388536 8388537 8388538

ADC CODE

8388539

Figure 8. Noise Distribution Histogram

(Output Data Rate = 1.25 SPS, Analog Input Buffers Disabled))

600

500

400

300

200

100

0

8388548 8388549 8388550

ADC CODE

8388551


(Output Data Rate = 1.25 SPS, Analog Input Buffers Enabled)

60

ADC CODE


(Output Data Rate = 10 kSPS, Analog Input Buffers Disabled))

Data Sheet

8388610

8388600

8388590

8388580

8388570

8388560

8388550

8388540

8388530

8388520

8388510

8388500

0 100 200 300 400 500 600 700 800 900 1000

SAMPLE NUMBER

Figure 11. Noise

(Output Data Rate = 10 kSPS, Analog Input Buffers Enabled)

8388580

8388570

8388560

8388550

8388540

8388530

8388520

8388510

8388500

8388490

0 100 200 300 400 500 600 700 800 900 1000

SAMPLE NUMBER

Figure 12. Noise

(Output Data Rate = 31.25 kSPS, Analog Input Buffers Disabled)

8388620

8388600

8388580

8388560

8388540

8388520

8388500

8388480

0 100 200 300 400 500 600 700 800 900 1000

SAMPLE NUMBER

Figure 13. Noise

(Output Data Rate = 31.25 kSPS, Analog Input Buffers Enabled)


50

45

40

35

30

25

20

15

10

5

0

AD7173-8

15

10

5

0

30

25

20

45

40

35

ADC CODE


(Output Data Rate = 10 kSPS, Analog Input Buffers Enabled))

ADC CODE


(Output Data Rate = 31.25 kSPS, Analog Input Buffers Disabled)

40

35

30

25

20

5

0

15

10

ADC CODE



AD7173-8

14

12

10

8

6

4

2

BUFFER ON, DEVICE 1

BUFFER OFF, DEVICE 1





0

0 1 2

V

CM

(V)

3 4

Figure 17. RMS Noise vs. Common-Mode Input Voltage

5

20

18

16

14

12

10

8

6

4

2

0

0 1

FREQUENCY (MHz)

2

Figure 18. RMS Noise vs. Master Clock Frequency


–60

–80

–100

–120

–140

–160

0

–20

–40

–180

–200

0 0.5

1.0

1.5

2.0

2.5

3.0

FREQUENCY (kHz)

3.5

4.0

4.5

5.0

Figure 19. ADC Output FFT; 1 kHz Input Tone, −0.5 dBFS Input FFT

(Output Data Rate = 10 kSPS, External Reference,

External Clock, Buffers Enabled)


Data Sheet

0

–20

–40

–60

–80

–100

–120

–140

–160

–180

–200

0 0.5

1.0

1.5

2.0

2.5

3.0

FREQUENCY (kHz)

3.5

4.0

4.5

5.0

Figure 20. ADC Output FFT; 1 kHz Input Tone, −6 dBFS Input FFT

(Output Data Rate = 10 kSPS, External Reference,


–60

–80

–100

–120

–140

–160

0

–20

–40

–180

–200

0 2 4 6 8

FREQUENCY (kHz)

10 12 14

Figure 21. ADC Output FFT; 1 kHz Input Tone, −0.5 dBFS Input FFT

(Output Data Rate = 31.25 kSPS, External Reference,


0

–20

–100

–120

–140

–40

–60

–80

–160

–180

–200

0 2 4 6 8

FREQUENCY (kHz)

10 12 14

Figure 22. ADC Output FFT; 1 kHz Input Tone, −6 dBFS Input FFT

(Output Data Rate = 31.25 kSPS, External Reference,


Data Sheet

1.0

0.5

FROM POWER-DOWN

0

FROM STANDBY – REFERENCE OFF

–0.5

–1.0

0.00001

0.0001

0.001

TIME (Seconds)

0.01

Figure 23. Internal Reference Settling Time

0.10

0.1

0.05

0

–0.05

–0.10

0 10 20 30

TIME (Seconds)

40

Figure 24. Internal Reference Settling Time (Extended)

50

–120

–125

–130

–135

–100

–105

–110

–115

UNIT 1 BUFFERS OFF

UNIT 1 BUFFERS ON



–140

10 20 30 40

FREQUENCY (Hz)

50 60 70

Figure 25. Common-Mode Rejection Ratio (10 Hz to 70 Hz) vs. Frequency

(20 SPS Enhanced Filter)

AD7173-8

0

–20

–40

–60

–80







–100

–120

–140

0 50k 100k

FREQUENCY (Hz)

150k

Figure 26. Common-Mode Rejection Ratio vs. Frequency

(Output Data Rate = 31.25 kSPS)

200k

0

–20

–40

–60





–80

–100

–120

–140

1 10 100 1k 10k

FREQUENCY (Hz)

100k 1M

Figure 27. Power Supply Rejection Ratio vs. Frequency

10M


AD7173-8

6

5

4

3

2

1







0

1.0

1.5

2.0

2.5

3.0

3.5

REFERENCE VOLTAGE (V)

4.0

4.5

5.0

Figure 28. Integral Nonlinearity (INL) Error vs. Reference Voltage

(Differential Input, External Reference)

30

25

20

15

10

5

0

1.0

1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8

4.0

INL ERROR (ppm)

Figure 29. Integral Nonlinearity (INL) Distribution Histogram

(Differential Input, V

REF

= 2.5 V External)

25

20

15

10

5

0

2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0 4.2 4.4 4.6 4.8 5.0 5.2

INL ERROR (ppm)

Figure 30. Integral Nonlinearity (INL) Distribution Histogram


REF

= 5 V External)


Data Sheet

10

9

8

7

6

5

4

3

2

1

0

–40 –30 –20 –10 0 10 20 30 40 50 60 70 80 90 100

TEMPERATURE (°C)

Figure 31. Integral Nonlinearity (INL) Error vs. Temperature


REF

= 2.5 V)

16.02

16.00

15.98

15.96

15.94

15.92

15.90

15.88

15.86

DEVICE 1

DEVICE 2

DEVICE 3

15.84

15.82

–40 –20 0 20 40


60 80

Figure 32. Internal Oscillator Frequency vs. Temperature

100

2.5010

2.5008

2.5006

2.5004

2.5002

2.5000

2.4998

2.4996

2.4994

DEVICE 1

DEVICE 2

DEVICE 3

2.4992

2.4990

–40 –20 0 20 40


60 80

Figure 33. Internal Reference Voltage vs. Temperature

100

Data Sheet

35

30

25

20

15

10

5

0

16

14

12

10

8

6

4

2

0

–48 –46 –44 –42 –40 –38 –36 –34 –32 –30 –28 –26 –24 –22 –20 –18

VOLTAGE (µV)

Figure 34. Offset Error Distribution Histogram

(Internal Short)

7

6

5

4

3

2

1

0

250 300 350

OFFSET DRIFT (nV/°C)

400

Figure 35. Offset Error Drift Distribution Histogram

(Internal Short)

450

GAIN ERROR (ppm)

Figure 36. Gain Error Distribution Histogram


AD7173-8

6

5

4

3

2

1

0

9

8

7

GAIN ERROR DRIFT (ppm/°C)

Figure 37. Gain Error Drift Distribution Histogram

6

5

4

3

2

DEVICE 1

DEVICE 2

DEVICE 3

1

0

–40 –30 –20 –10 0 10 20 30 40 50 60 70 80 90 100


Figure 38. Current Consumption vs. Temperature

(Continuous Conversion Mode, Buffers Enabled,

Internal Reference, Internal Clock)

5.0

4.5

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

DEVICE 1

DEVICE 2

DEVICE 3

0

–40 –30 –20 –10 0 10 20 30 40 50 60 70 80 90 100


Figure 39. Current Consumption vs. Temperature

(Power-Down Mode)

AD7173-8

NOISE PERFORMANCE AND RESOLUTION

Table 6 shows the rms noise, peak-to-peak noise, effective

resolution, and the noise free (peak-to-peak) resolution of the

AD7173-8 for various output data rates and filters. The values listed are for the bipolar input range with an external 5 V reference.

These values are typical and are generated with a differential input voltage of 0 V when the ADC is continuously converting

Data Sheet

on a single channel. It is important to note that the peak-topeak resolution is calculated based on the peak-to-peak noise.

The peak-to-peak resolution represents the resolution for which there is no code flicker. Using the sinc3 filter at the fastest rate results in the noise being quantization limited. This limitation degrades the noise specification at this rate and does not give a result of 24 bits, no missing codes.

Table 6. RMS Noise and Peak-to-Peak Resolution vs. Output Data Rate using Sinc5 + Sinc1 Filter (Default)

1

Sinc5 + Sinc1 Filter (Default)

Output Data Rate (SPS)

RMS Noise (µV rms) Effective Resolution (Bits)

Peak-to-Peak

Noise (µV rms)

Peak-to-Peak

Resolution (Bits)

31,250

5208

1007

381

100.5

20.01

5

8.0

4.5

2.2

1.3

0.71

0.32

0.15

1.25 0.07

1 Selected rates only; 1000 samples.

20.2

21.1

22.2

22.9

23.8

24

24

24

67

30

15

8.9

5.1

1.7

0.75

0.32

17.5

18.3

19.3

20.1

21

22.2

23.4

24

Table 7. RMS Noise and Peak-to-Peak Resolution vs. Output Data Rate using Sinc3 Filter 1

Sinc3 Filter

Output Data Rate (SPS)

31,250

5208

1008

400.6

100.5

20.01

RMS Noise (µV rms)

210

3.6

1.5

1

0.55

0.25

5

1.25

1

Selected rates only; 1000 samples.

0.11

0.07

Effective Resolution (Bits)

15.5

21.4

22.7

23.3

24

24

24

24

Peak-to-Peak

Noise (µV rms)

1665

28

12

6.6

3.5

1.2

0.56

0.27

Peak-to-Peak


12.8

18.7

19.9

20.5

21.4

22.4

23.4

24


Data Sheet

GETTING STARTED

The AD7173-8 offers the user a fast settling, high resolution, multiplexed ADC with high levels of configurability.

•

Eight fully differential or 16 single-ended analog inputs.

•

Cross point mux. Selects any analog input combination as a pairing to be converted. The signals are routed to the input buffers and onto the modulator positive or negative input.

•

ADC input. Selectable as a fully differential input or as a single-ended input.

•

Per setup configurability. Up to eight different setups can be defined. A separate setup can be mapped to each of the channels. Each setup allows the user to configure the following:

•

Output data rate when using sinc5 + sinc1 filter

•

Digital filter mode

•

Offset/gain error correction

•

Reference source selection (internal/external)

•

Analog and reference input buffer enables

•

Digital output coding

AD7173-8

The AD7173-8 includes a precision 2.5 V low drift (3.5 ppm/°C) band gap internal reference. This reference can be selected to be used for the ADC conversions, reducing the external component count. When enabled, the internal reference is output to the REFOUT pin and can be used as a low noise biasing voltage for the external circuitry. An example of this is using the REFOUT signal to set the input common mode for an external single-ended to differential amplifier.

The AD7173-8 includes two separate linear regulator blocks for both the analog and digital circuitry. The analog LDO regulates the AVDD2 supply to 1.8 V, supplying the ADC core. The user can tie the AVDD1 and AVDD2 supplies together for easiest connection. If a clean analog supply rail is in the system in the range of 2 V to 5.5 V (minimum to maximum), the user can also choose to connect this supply rail to the AVDD2 input, allowing for lower power dissipation.

SEE ANALOG INPUT SECTION FOR FURTHER DETAILS

2 AIN0/REF2–

3 AIN1/REF2+

36

AIN14

XTAL1

12

XTAL2/CLKIO

13

DOUT/RDY

14

DIN 15

SCLK 16

CS

17

16MHz

CX1 CX2

OPTIONAL EXTERNAL

CRYSTAL CIRCUITRY

CAPACITORS

DOUT/RDY

CLKIN

OPTIONAL

EXTERNAL

CLOCK

INPUT

DIN

SCLK

CS

37

AIN15

1 AIN16

VIN

4.7µF 0.1µF

2

V

IN

1 3

NC 7

ADR44xBRZ

4

GND

5

VOUT 6

8

0.1µF 4.7µF 0.1µF

40 REF+

39

REF–

AD7173-8

AVSS

8

Figure 40. Typical Connection Diagram

IOVDD

IOVDD 20

DGND

21

0.1µF

REGCAPD

22

0.1µF

AVDD1

9

1µF

0.1µF

AVDD1

AVDD2

AVDD2 10

0.1µF

REGCAPA 7

0.1µF 1µF


AD7173-8

The linear regulator for the digital IOVDD supply performs a similar function, regulating the input voltage applied at the

IOVDD pin to 1.8 V for the internal digital filtering. The serial interface signals always operate from the IOVDD supply seen at the pin. This means that if 3.3 V is applied to the IOVDD pin, the interface logic inputs and outputs operate at this level.

The AD7173-8 can be used across a wide variety of applications, providing high resolution and accuracy. A sample of these scenarios follows:

•

Fast scanning of analog input channels using the internal mux

•

Fast scanning of analog input channels using an external mux

•

High resolution at lower speeds in either multichannel or

ADC per channel applications

•

Single ADC per channel; the fast low latency output allows further application specific filtering in an external microcontroller, DSP, or FPGA

POWER SUPPLIES

The AD7173-8 can run from either a 3.3 V or 5 V supply voltage.

The device has three independent power supply pins: AVDD1,

AVDD2, and IOVDD.

•

AVDD1 and AVDD2 are referred to AVSS.

•

AVDD2 powers the internal regulator supplying the ADC.

•

AVDD1 and AVDD2 can be tied together for convenience.

•

IOVDD is referred to DGND. The supply sets the interface logic levels on the SPI interface and powers an internal regulator for operation of the digital processing.

Single Supply Operation (AVSS = DGND)

When the AD7173-8 is powered from a single supply that is connected to AVDD1, the supply can be either 3.3 V or 5 V.

In this configuration, AVSS and DGND can be shorted together on one single ground plane. With this setup, an external level shifting circuit is required to use fully differential inputs to shift the common-mode voltage.

Data Sheet

AVDD2 is the input to the internal voltage regulator. Connect

AVDD2 to AVDD1 for convenience. Otherwise, if a separate supply is available in the system, a voltage from 2 V to 5.5 V can be applied. IOVDD can range from 2 V to 5.5 V in this unipolar input configuration.

Split Supply Operation (AVSS ≠ DGND)

The AD7173-8 device has the ability to operate with AVSS set to a negative voltage, allowing true bipolar inputs to be applied. This allows for a fully differential input signal centered around 0 V and eliminates the need for an external level shifting circuit. For example, with a 5 V split supply, AVDD1 = 2.5 V and AVSS =

−2.5 V. In this use case, the AD7173-8 internally level shifts the signals, allowing the digital output to function between DGND

(nominally 0 V) and IOVDD.

When using a split supply for AVDD1 and AVSS, the absolute

maximum ratings must be considered (refer to the Absolute

Maximum Ratings section). Ensure that IOVDD is set below

3.6 V to stay within the absolute maximum rating for the device.

DIGITAL COMMUNICATION

The AD7173-8 has a 3-wire or 4-wire SPI interface that is compatible with QSPI™, MICROWIRE®, and DSPs. The interface operates in SPI Mode 3 and can be operated with CS tied low. In

SPI Mode 3, SCLK idles high, the falling edge of SCLK is the drive edge, and the rising edge of SCLK is the sample edge. This means that data is clocked out on the falling/drive edge and data is clocked in on the rising/sample edge.

DRIVE EDGE SAMPLE EDGE

Figure 41. SPI Mode 3 SCLK Edges


Data Sheet

Accessing the ADC Register Map

The communications register controls access to the full register map of the ADC. This register is an 8-bit write only register. On power-up or after a reset, the digital interface defaults to a state where it is expecting a write to the communications register; therefore, all communication begins by writing to the communications register.

The data written to the communications register determines which register is being accessed and if the next operation is a read or write. The register address bits (RA[5:0]) determine the specific register to which the read or write operation applies.

When the read or write operation to the selected register is complete, the interface returns to its default state, where it expects a write operation to the communications register.

In situations where interface synchronization is lost, a write operation of at least 64 serial clock cycles with DIN high returns the ADC to its default state by resetting the entire part, including the register contents. Alternatively, if CS is being used with the digital interface, returning CS high resets the digital interface to its default state and aborts any current operation.

Figure 42 and Figure 43 illustrate writing to and reading from a

register by first writing the 8-bit command to the communications register followed by the data for the addressed register.

Reading the ID register is the recommended method for verifying correct communication with the part. The ID register is a read only register and contains the value 0x30DX for the AD7173-8 .

The communication register and ID register details are described

in Table 8 and Table 9.

Table 8. Communications Register Bit Map

Reg Name Bits Bit 7 Bit 6

0x00 COMMS [7:0] WEN R/W

Table 9. ID Register Bit Map

Reg Name Bits

0x07 ID [15:8]

[7:0]

1

X = don’t care.

Bit 7 Bit 6

Bit 5

Bit 5

CS

DIN

Bit 4

ID[15:8]

Bit 3

ID[7:0]

8-BIT COMMAND

CMD DATA

SCLK

Figure 42. Writing to a Register

(8-Bit Command with Register Address Followed by Data of 8, 16, or 24 Bits;

Data Length Is Dependent on the Register Selected)

8-BIT COMMAND

8 BITS, 16 BITS,

24 BITS, OR

32 BITS OUTPUT

CS

DIN

DOUT/RDY

Bit 4

SCLK

Figure 43. Reading from a Register

(8-Bit Command with Register Address Followed by Data of 8, 16, or 24 Bits;

Data Length on DOUT Is Dependent on the Register Selected)

Bit 3

RA

Bit 2 Bit 1 Bit 0 Reset

0x00

RW

W

Bit 2

CMD

AD7173-8

8 BITS, 16 BITS,

OR 24 BITS OF DATA

DATA

Bit 1 Bit 0 Reset RW

0x30DX 1

R


AD7173-8

CONFIGURATION OVERVIEW

After power on-or reset, the AD7173-8 default configuration is as follows:

 Channel configuration. CH0 is enabled, AIN0 is selected as the positive input, and AIN1 is selected as the negative input. Setup 0 is selected.

 Setup configuration. The input buffers are disabled, and the external reference is selected.

 ADC mode. Continuous conversion mode, the internal oscillator, and single cycle settling are enabled.

 Interface mode. CRC is disabled, and data + status output is disabled.

Note that only a few of the register setting options are shown; this list is just an example. For full register information, see the

Register Details section.

Figure 44 shows an overview of the suggested flow for changing

the ADC configuration, divided into the following three blocks:

 Channel configuration (see Box A in Figure 44)

 Setup configuration (see Box B in Figure 44)

 ADC mode and interface mode configuration (see Box C

in Figure 44)

A

Data Sheet

Channel Configuration

The AD7173-8 has 16 independent channels and eight independent setups. The user can select any of the analog input pairs on any channel, as well as any of the eight setups for any channel, giving the user full flexibility in the channel configuration. This also allows per channel configuration when using eight differential inputs because each channel can have its own dedicated setup.

Channel Registers

The channel registers are used to select which of the 17 analog input pins (AIN0 to AIN16) are used as either the positive analog input or the negative analog input for that channel. This register also contains a channel enable/disable bit and the setup selection bits, which are used to pick which of the eight available setups are used for this channel.

When the AD7173-8 is operating with more than one channel enabled, the channel sequencer cycles through the enabled channels in sequential order, from Channel 0 to Channel 15. If a channel is disabled, it is skipped by the sequencer. Details of the

channel register for Channel 0 are shown in Table 10.

CHANNEL CONFIGURATION

SELECT POSITIVE AND NEGATIVE INPUT FOR EACH ADC CHANNEL

SELECT ONE OF 8 SETUPS FOR ADC CHANNEL

B

SETUP CONFIGURATION

8 POSSIBLE ADC SETUPS

SELECT FILTER ORDER, OUTPUT DATA RATE, AND MORE

C

ADC MODE AND INTERFACE MODE CONFIGURATION

SELECT ADC OPERATING MODE, CLOCK SOURCE,

ENABLE CRC, DATA + STATUS, AND MORE

Figure 44. Suggested ADC Configuration Flow

Table 10. Channel 0 Register Bit Map

Reg Name

0x10 CH0

Bits Bit 7

[15:8] CH_EN0

[7:0]

Bit 6 Bit 5 Bit 4

SETUP_SEL[2:0]

AINPOS0[2:0]

Bit 3 Bit 2

RESERVED

Bit 1

AINNEG0

Bit 0

AINPOS0[4:3]

Reset

RW

0x8001 RW



ADC Setups

The AD7173-8 has eight independent setups. Each setup consists of the following four registers:

•

Setup configuration register

•

Filter configuration register

•

Offset register

•

Gain register

For example, Setup 0 consists of Setup Configuration Register 0,

Filter Configuration Register 0, Offset Register 0, and Gain

Register 0. Figure 45 shows the grouping of these registers The

setup is selectable from the channel registers detailed in the

Channel Configuration section. This allows each channel to be

assigned to one of 8 separate setups. Table 11 through Table 14

show the four registers that are associated with Setup 0. This structure is repeated for Setup 1 to Setup 7.

SETUP CONFIG

REGISTERS

SETUPCON0

0x20

SETUPCON1

0x21

SETUPCON2

0x22

SETUPCON3

0x23

SETUPCON4

0x24

SETUPCON5

0x25

SETUPCON6

0x26

SETUPCON7

0x27

SELECT PERIPHERAL

FUNCTIONS FOR

ADC CHANNEL

AIN BUFFERS

REF BUFFERS

BURNOUT

REFERENCE SOURCE

Setup Configuration Registers

The setup configuration registers allow the user to select the output coding of the ADC by selecting between bipolar and unipolar. In bipolar mode, the ADC accepts negative differential input voltages, and the output coding is offset binary. In unipolar mode, the ADC accepts only positive differential voltages, and the coding is straight binary. In either case, the input voltage must be within the AVDD1/

AVSS supply voltages. The user can also select the reference source using this register. Four options are available: an internal 2.5 V reference, an external reference connected between the REF+ and REF− pins, an external reference connected between

AIN0/REF2− and AIN1/REF2+, or AVDD1 − AVSS. The analog input buffers and reference input buffers for the setup can also be enabled using this register.

Filter Configuration Registers

The filter configuration register selects which digital filter is used at the output of the ADC modulator. The order of the filter and the output data rate is selected by setting the bits in this

register. For more information, see the Digital Filters section.

FILTER CONFIG

REGISTERS GAIN REGISTERS* OFFSET REGISTERS

FILTCON0

0x28

FILTCON1

0x29

FILTCON2

0x2A

FILTCON3

0x2B

FILTCON4

0x2C

FILTCON5

0x2D

FILTCON6

0x2E

FILTCON7

0x2F

GAIN0

GAIN1

GAIN2

GAIN3

GAIN4

GAIN5

GAIN6

GAIN7

0x38

0x39

0x3A

0x3B

0x3C

0x3D

0x3E

0x3F

SELECT DIGITAL

FILTER TYPE

AND OUTPUT DATA RATE

GAIN CORRECTION

OPTIONALLY

PROGRAMMED

PER SETUP AS REQUIRED

(*FACTORY CALIBRATED)

SINC5 + SINC1

SINC3

SINC3 MAP

ENHANCED 50/60

Figure 45. ADC Setup Register Grouping

OFFSET0

OFFSET6

0x30

OFFSET1

OFFSET5

0x31

OFFSET2

OFFSET4

0x32

OFFSET3

0x33

0x34

0x35

0x36

OFFSET7

0x37

OFFSET CORRECTION

OPTIONALLY PROGRAMMED


Table 11. Setup Configuration 0 Register Bit Map


0x20 SETUPCON0 [15:8] RESERVED

[7:0] BURNOUT_EN0 BUFCHOPMAX0

Bit 5 Bit 4

BI_UNIPOLAR0

Bit 3 Bit 2

REF_BUF 0[1:0]

REF_SEL0

Bit 1 Bit 0

AIN_BUF 0[1:0]

RESERVED

Reset RW

0x1000 RW

Table 12. Filter Configuration 0 Register Bit Map

Reg Name Bits Bit 7 Bit 6 Bit 5

0x28 FILTCON0 SINC3_MAP0 RESERVED

ORDER0

Bit 4

Table 13. Offset Configuration 0 Register Bit Map

Reg Name Bits

0x30 OFFSET0 [23:0]

Table 14. Gain Configuration 0 Register Bit Map

Reg Name Bits

0x38 GAIN0 [23:0]

Bit[23:0]

OFFSET0[23:0]

Bit[23:0]

GAIN0[23:0]

Bit 3

ENHFILTEN0

Bit 2

ODR0

Bit 1

ENHFILT0

Bit 0 Reset RW

0x0000 RW

Reset RW

0x800000 RW

Reset RW

0x5XXXX0 RW



Offset Registers

The offset register holds the offset calibration coefficient for the

ADC. The power-on reset value of the offset register is 0x800000.

The offset register is a 24-bit read/write register. The power-on reset value is automatically overwritten if an internal or system zero-scale calibration is initiated by the user or if the offset register is written to by the user.

Gain Registers

The gain register is a 24-bit register that holds the gain calibration coefficient for the ADC. The gain registers are read/write registers. These registers are configured at power-on with factory calibrated coefficients. Therefore, every device has different default coefficients. The default value is automatically overwritten if a system full-scale calibration is initiated by the user or if the gain register is written to by the user. For more

information on calibration, see the Operating Modes section.

ADC Mode and Interface Mode Configuration

The ADC mode register and the interface mode register configure the core peripherals for use by the AD7173-8 and the mode for the digital interface.

ADC Mode Register

The ADC mode register is used primarily to set the conversion mode of the ADC to either continuous or single conversion.

The user can also select the standby and power-down modes, as well as any of the calibration modes. In addition, this register contains the clock source select bits and the internal reference enable bits. The reference select bits are contained in the setup

configuration registers (see the ADC Setups section for more

information).

Interface Mode Register

The interface mode register configures the digital interface operation. This register allows the user to control data-word length, CRC enable, data + status read and continuous read mode.

The details of both registers are shown in Table 15 and Table 16.

For more information, see the Digital Interface section.

Table 15. ADC Mode Register Bit Map

Reg Name Bits Bit 7

0x01 ADCMODE [15:8] REF_EN

[7:0] RESERVED

Bit 6 Bit 5

RESERVED SING_CYC

MODE

Table 16. Interface Mode Register Bit Map

Reg Name Bits

0x02 IFMODE [15:8]

Bit 7 Bit 6

RESERVED

[7:0] CONTREAD DATA_

STAT

Bit 5

REG_

CHECK

Bit 4 Bit 3

RESERVED

Bit 2

CLOCKSEL

Bit 4 Bit 3 Bit 2

ALT_SYNC IOSTRENGTH HIDE_DELAY

RESERVED CRC_EN

Bit 1 Bit 0

DELAY

RESERVED

Bit 1

RESERVED

RESERVED

Reset RW

0x2000 RW

Bit 0 Reset RW

DOUT_RESET 0x0000 RW

WL16



Understanding Configuration Flexibility

The most straightforward implementation of the AD7173-8 is to use eight differential inputs with adjacent analog inputs and run all of them with the same setup, gain correction, and offset correction register. In this case, the user selects the following differential inputs: AIN0/AIN1, AIN2/AIN3, AIN4/AIN5,

AIN6/AIN7, AIN8/AIN9. AIN10/AIN11, AIN12/AIN13,

AIN14/AIN15. In Figure 46, the registers shown in black font

must be programmed for such a configuration. The registers that are shown in gray font are redundant in this configuration.

AIN0

AIN1

AIN2

AIN3

AIN4

AIN5

AIN6

AIN7

AIN8

AIN9

AIN10

AIN11

AIN12

AIN13

AIN14

AIN15

AIN16

Programming the gain and offset registers is optional for any use case, as indicated by the dashed lines between the register blocks.

An alternative way to implement these eight fully differential inputs is by taking advantage of the eight available setups.

Motivation for doing this includes having is a different speed/noise requirement on some of the eight differential inputs vs. other inputs, or there may be a specific offset or gain correction for

particular channels. Figure 47 shows how each of the differential

inputs may use a separate setup, allowing full flexibility in the configuration of each channel.

CHANNEL

REGISTERS

CH0

0x10

CH1

0x11

CH2

0x12

CH3

0x13

CH4

0x14

CH5

0x15

CH6

0x16

CH7

0x17

CH8

0x18

CH9

0x19

CH10

0x1A

CH11

0x1B

CH12

0x1C

CH13

0x1D

CH14

0x1E

CH15

0x1F

SETUP CONFIG

REGISTERS

SETUPCON0

0x20

SETUPCON1

0x21

SETUPCON2

0x22

SETUPCON3

0x23

SETUPCON4

0x24

SETUPCON5

0x25

SETUPCON6

0x26

SETUPCON7

0x27


FUNCTIONS FOR

ADC CHANNEL

FILTER CONFIG

REGISTERS

FILTCON0

0x28

FILTCON1

0x29

FILTCON2

0x2A

FILTCON3

0x2B

FILTCON4

0x2C

FILTCON5

0x2D

FILTCON6

0x2E

FILTCON7

0x2F

SELECT DIGITAL

FILTER TYPE


GAIN REGISTERS* OFFSET REGISTERS

GAIN0

GAIN1

0x38

0x39

OFFSET0

0x30

OFFSET1

0x31

OFFSET2

0x32

GAIN2

0x3A

GAIN3

GAIN4

GAIN5

GAIN6

GAIN7

0x3B

0x3C

0x3D

0x3E

0x3F

OFFSET3

0x33

OFFSET4

0x34

OFFSET5

0x35

OFFSET6

0x36

OFFSET7

0x37

GAIN CORRECTION

OPTIONALLY

PROGRAMMED






SELECT ANALOG INPUT PARTS

ENABLE THE CHANNEL

SELECT SETUP 0

AIN BUFFERS

REF BUFFERS

BURNOUT


31.25kSPS TO 1.25SPS

SINC5 + SINC1

SINC3

SINC3 MAP

ENHANCED 50/60

Figure 46. Eight Fully Differential Inputs, All Using a Single Setup (SETUPCON0; FILTCON0; GAIN0; OFFSET0)

AIN9

AIN10

AIN11

AIN12

AIN13

AIN14

AIN15

AIN16

AIN0

AIN1

AIN2

AIN3

AIN4

AIN5

AIN6

AIN7

AIN8

CHANNEL

REGISTERS

CH0

0x10

CH1

0x11

CH2

0x12

CH3

0x13

CH4

0x14

CH5

0x15

CH6

0x16

CH7

0x17

CH8

0x18

CH9

0x19

CH10

0x1A

CH11

0x1B

CH12

0x1C

CH13

0x1D

CH14

0x1E

CH15

0x1F



SELECT SETUP

SETUP CONFIG

REGISTERS

SETUPCON0

0x20

SETUPCON1

0x21

SETUPCON2

0x22

SETUPCON3

0x23

SETUPCON4

0x24

SETUPCON5

0x25

SETUPCON6

0x26

SETUPCON7

0x27

FILTER CONFIG

REGISTERS

FILTCON0

0x28

FILTCON1

0x29

FILTCON2

0x2A

FILTCON3

0x2B

FILTCON4

0x2C

FILTCON5

0x2D

FILTCON6

0x2E

FILTCON7

0x2F

GAIN REGISTERS*

GAIN0

0x38

GAIN1

0x39

GAIN2

GAIN3

0x3A

0x3B

GAIN4

GAIN5

0x3C

0x3D

GAIN6

GAIN7

0x3E

0x3F

OFFSET REGISTERS

OFFSET0

0x30

OFFSET1

OFFSET6

0x31

OFFSET2

OFFSET4

0x32

OFFSET3

0x33

0x34

OFFSET5

0x35

0x36

OFFSET7

0x37


FUNCTIONS FOR

ADC CHANNEL

AIN BUFFERS

REF BUFFERS

BURNOUT


SELECT DIGITAL

FILTER TYPE


GAIN CORRECTION

OPTIONALLY

PROGRAMMED






31.25kSPS TO 1.25SPS

SINC5 + SINC1

SINC3

SINC3 MAP

ENHANCED 50/60

Figure 47. Eight Fully Differential Inputs with a Setup per Channel


AD7173-8

Figure 48 shows an example of how the channel registers span

between the analog input pins and the setup configurations downstream. In this random example, seven differential inputs and two single-ended inputs are required. The single-ended inputs are the AIN8/AIN16 and AIN15/AIN16 combinations. The first five differential input pairs (AIN0/AIN1, AIN2/AIN3, AIN4/AIN5,

AIN6/AIN7, AIN9/AIN10) use the same setup: SETUPCON0.

The two single-ended input pairs (AIN8/AIN16 and AIN15/

AIN16) are set up as a diagnostics; therefore, use a separate setup:

SETUPCON1. The final two differential inputs (AIN11/AIN12 and AIN13/AIN14) also use a separate setup: SETUPCON2.

Given that three setups are selected for use, the SETUPCON0,

Data Sheet

SETUPCON1, and SETUPCON2 registers are programmed as required, and the FILTCON0, FILTCON1, and FILTCON2 registers are also programmed as desired. Optional gain and offset correction can be employed on a per setup basis by programming the GAIN0, GAIN1, and GAIN2 registers and the OFFSET0, OFFSET1, and OFFSET2 registers.

In the example shown in Figure 48, the CH0 to CH8 registers

are used. Setting the MSB in each of these registers, the CH_EN0 to CH_EN8 bits enable the nine combinations via the cross point mux. When the AD7173-8 converts, the sequencer transitions in ascending sequential order from CH0 to CH1 to CH2, and then on to CH8 before looping back to CH0 to repeat the sequence.

AIN0

AIN1

AIN2

AIN3

AIN4

AIN5

AIN6

AIN7

AIN8

AIN9

AIN10

AIN11

AIN12

AIN13

AIN14

AIN15

AIN16

CHANNEL

REGISTERS

CH0

0x10

CH1

0x11

CH2

0x12

CH3

0x13

SETUP CONFIG

REGISTERS

FILTER CONFIG

REGISTERS GAIN REGISTERS* OFFSET REGISTERS

CH4

0x14

SETUPCON0

0x20

FILTCON0

0x28

GAIN0

0x38

OFFSET0

0x30

CH5

0x15

CH7

CH8

0x18

SETUPCON1

0x21

FILTCON1

0x29

GAIN1

0x39

OFFSET1

0x31

CH6

0x16

0x17

SETUPCON2

0x22

SETUPCON3

0x23

SETUPCON4

0x24

FILTCON2

0x2A

FILTCON3

0x2B

FILTCON4

0x2C

GAIN2

GAIN3

GAIN4

0x3A

0x3B

0x3C

OFFSET2

OFFSET3

OFFSET4

0x32

0x33

0x34

CH9

0x19

SETUPCON5

0x25

FILTCON5

0x2D

GAIN5

0x3D

OFFSET5

0x35

CH10

0x1A

CH11

0x1B

CH14

0x1E

SETUPCON6

0x26

SETUPCON7

0x27

FILTCON6

0x2E

FILTCON7

0x2F

GAIN6

GAIN7

0x3E

0x3F

OFFSET6

OFFSET7

0x36

0x37

CH12

0x1C

CH13

0x1D

CH15

0x1F


FUNCTIONS FOR

ADC CHANNEL

AIN BUFFERS

REF BUFFERS

BURNOUT


SELECT DIGITAL

FILTER TYPE


GAIN CORRECTION

OPTIONALLY

PROGRAMMED








SELECT SETUP

31.25kSPS TO 1.25SPS

SINC5 + SINC1

SINC3

SINC3 MAP

ENHANCED 50/60

Figure 48. Mixed Differential and Single-Ended Configuration Using Multiple Shared Setups



CIRCUIT DESCRIPTION

ANALOG INPUT

Buffered Analog Input

The AD7173-8 integrates precision unity gain buffers on the

ADC inputs. The output of the integrated cross point mux is connected to the ADC via these precision buffers. The buffers provide the benefit of giving the user high input impedance and fully drive the internal ADC switch capacitor sampling network.

There is a buffer on both the positive and negative analog inputs to the ADC. The input signals of the AIN pair that is selected via control of the cross point mux (BUF+, BUF−) pass to the buffer inputs, which drive the ADC sampling capacitor circuitry. Each analog input buffer has an input voltage range as shown in

Figure 49. Each buffer can operate with an input signal down to

AVSS (analog ground) or up to an input voltage of 1.1 V from the AVDD1 supply.

Fully Differential Inputs

The AIN0 to AIN16 analog inputs are connected to a cross point mux. Any combination of signals can be used to create an analog input pair. This allows the user to select eight fully differential inputs or 16 single-ended inputs. If all signals to the AD7173-8 are fully differential, it is recommended that the traces of the inputs be of the same length. The most reliable and efficient way to do

AVDD1

1.1V

AVDD1 REF– REF+ REFOUT

this is by using adjacent input pins as the differential pair. All analog inputs decoupling capacitors connect to AVSS.

Single-Ended Inputs

The user can also choose to measure 16 different single-ended analog inputs. In this case, each of the analog inputs is converted as being the difference between the single-ended input to be measured and a set analog input common pin. Because there is a cross point mux, the user can set any of the analog inputs as the common pin. An example of such a scenario is to connect the

AIN16 pin to AVSS or to the REFOUT voltage (that is, AVSS +

2.5 V) and select this input when configuring the cross point mux. When using the AD7173-8 with single-ended inputs, the

INL specification is degraded.

When the user requires a buffered input in either the fully differential or single-ended case, the user is required to turn on the analog input buffers as a pair. This means that, even where an input pin is connected to AVSS, the input buffer of this channel is turned on if the other pin making up the differential input is going to be buffered.

USABLE

INPUT VOLTAGE RANGE:

BUFFERS ON

(AVDD1 – 1.1V) – (AVSS)

AIN X

AIN Y

CROSSPOINT

MULTIPLEXER

REFERENCE

INPUT

BUFFERS

BUF+

ANALOG

INPUT

BUFFERS

ON

Σ-Δ ADC

BUF–

ON

INT

REF

DIGITAL

FILTER

SERIAL

INTERFACE

AND CONTROL

CS

SCLK

DIN

DOUT/RDY

AVSS

TEMPERATURE

SENSOR

AVSS

Figure 49. Analog Input Voltage Range with Analog Input Buffers Enabled


AD7173-8

Buffer Chopping, Noise, and Input Current

Each analog input buffer amplifier is fully chopped, meaning that it minimizes the offset error drift and 1/f noise of the signal chain.

The 1/f noise profile is shown in Figure 51.

The noise performance of the buffer at certain output data rates can be improved by increasing the chopping rate of the buffer, giving a corresponding increase in input current. This is done by setting the BUFCHOPMAXx bit in the setup configuration register of the selected setup.

Running with Single Cycle = 0

The output data rate can be maximized when using only a single channel by setting the SING_CYC bit to 0. However, the analog input current changes in magnitude, depending on the output data rate selected. In this condition, the input current increases by approximately 32× for output data rates selected at >2.6 kSPS.

Set the SING_CYC bit to 0 only in this specific use case. Figure 52 and Figure 53 show rms noise and input current vs. output data

rate for various conditions.

Using External Buffers

The analog input buffers can be disabled. When they are disabled, the input voltage range on the analog inputs is AVDD1 – AVSS.

The analog input switched capacitor input is then exposed to the user. A suitable external amplifier is required to sufficiently drive and settle the analog input in such cases. The CS1 and CS2 capacitors each have a magnitude in the order of a number of picofarads (pF). This capacitance is the combination of both the sampling capacitance and the parasitic capacitance.

AVDD1

AIN0

AVDD1

AVSS

Ø1

+IN

AIN1

CS1

AVSS

Ø2

Ø2

AVDD1

CS2

AIN14

Ø1

AVDD1

AVSS

–IN

AIN15

AVSS

AVDD1

AIN16

AVSS

Figure 50. Simplfied Analog Input Circuit

Data Sheet

The average input current to the AD7173-8 changes linearly with the differential input voltage at a rate of 6 µA/V. Each analog input must be buffered externally, not only to provide the varying input current with differential input amplitude, but also to settle the switched capacitor input to allow accurate sampling.

The simplified analog input circuit for this situation is shown in

Figure 50.

0

–50

–100

–150

–200


–250

0.1

1 10 100

FREQUENCY (Hz)

Figure 51. Shorted Input FFT

1k 10k

12

10

8

6

4

2

BUFCHOP MAX = 0

BUFCHOP MAX = 1

0

1

10

100

ODR (SPS)

1k

Figure 52. RMS Noise vs. Output Data Rate

(Sinc5 + Sinc1 Filter)

10k

14

12

10

8

6

4

–2

–4

2

0

SINGLE CHANNEL AND SING_CYC = 0

BUFCHOPMAX = 1

SING_CYC = 1

–6

1 10 100 1k 10k

ODR (SPS)

Figure 53. Typical Analog Input Current vs. Output Data Rate

(2.5 V Common Mode)

Data Sheet

REFERENCE OPTIONS

The AD7173-8 offers the user the option of either supplying an external reference to the REF+ and REF− pins of the device or allowing the use of the internal 2.5 V, low noise, low drift reference.

Select the reference source to be used by the analog input by setting the REF_SELx bits (Bits[5:4]) in the setup configuration registers appropriately. The structure of the Setup Configuration 0 register

is shown in Table 17. The

AD7173-8 defaults on power-up to use of an external reference.

External Reference

The AD7173-8 has a fully differential reference input applied through the REF+ and REF− pins. Standard low noise, low drift voltage references, such as the ADR445 , ADR444 , and ADR441 , are recommended for use. Apply the external reference to the

AD7173-8

reference pins as shown in Figure 54. Decouple the

output of any external reference is to AVSS. As shown in

Figure 54, the

ADR441 output is decoupled with a 0.1 μF capacitor at its output for stability purposes. The output is then connected to a 4.7 μF capacitor, which acts as a reservoir for any dynamic charge required by the ADC, and followed by a 0.1 μF decoupling capacitor at the REF+ input. This capacitor is placed as close as possible to the REF+ and REF− pins. The REF− pin is connected directly to the AVSS potential.

AD7173-8

Internal Reference

The AD7173-8 includes its own low noise, low drift voltage reference. On power-up, the internal reference is disabled by default and a register write is required to select it as the reference source for the ADC. Write to the REF_EN bit (Bit 15) in the ADC

mode register to enable it (see Table 18). The internal reference

has a 2.5 V output and is output on the REFOUT pin after the

REF_EN bit is set in the ADC mode register. Decouple the internal reference to AVSS with a 0.1 μF capacitor.

The REFOUT signal is buffered prior to being output to the pin.

The signal can be used externally in the circuit as a common-mode source for external amplifier configurations.

CLOCK SOURCE

The AD7173-8 requires a master clock of 2 MHz. The AD7173-8 can use one of the following sources as its sampling clock:

 Internal oscillator

 External crystal (use a 16 MHz crystal, automatically divided internally to set the 2 MHz clock)

 External clock source

All output data rates listed in the data sheet relate to a master clock rate of 2 MHz. Using a lower clock frequency from, for example, an external source proportionally scales any listed data rate. To achieve the specified data rates, particularly rates for rejection of 50 Hz and 60 Hz, a use a 2 MHz clock. The source of the master clock is selected by setting the CLOCKSEL bits in the ADCMODE

register, as shown in Table 25. The default, on power-up and reset,

is to operate with the internal oscillator.

AD7173-8

3V TO 18V

*

0.1µF

ADR441

**

2.5V VREF

* *

0.1µF

40

REF+

4.7µF

0.1µF

* *

39 REF–

*ALL DECOUPLING IS TO AVSS.

**ANY OF THE ADR44x FAMILY REFERENCES CAN BE USED.

ADR441 ENABLES REUSE OF THE 3.3V ANALOG SUPPLY

NEEDED FOR AVDD1 TO POWER THE REFERENCE VIN.

Figure 54. External Reference ADR441 Connected to AD7173-8 Reference Pins

Table 17. Setup Configuration 0 Register

Reg Name Bits Bit 7

0x20 SETUPCON0 [15:8]

Bit 6

RESERVED

Bit 5 Bit 4

RESERVED BI_UNIPOLAR

BURNOUT_EN REF_SEL0

Bit 3 Bit 2

REF_BUF 0[1:0]

Bit 1 Bit 0

AIN_BUF 0[1:0] 0x1000

RESERVED

Reset RW

RW

0

Table 18. ADC Mode Register

Reg Name Bits Bit 7 Bit 6 Bit 5

0x01 ADCMODE [15:8] INT_REF_EN RESERVED SING_CYC

Bit 4

MODE

Bit 3

RESERVED

Bit 2

CLOCKSEL

Bit 1

DELAY

Bit 0 Reset RW

0x2000 RW

RESERVED


AD7173-8

Internal Oscillator

The internal oscillator is used as the ADC master clock by default. The clock used for the ADC sampling is 2 MHz (this is divided down from a higher frequency in the case of the internal oscillator use). It is the default clock source for the AD7173-8 and is specified with an accuracy of ±2.5%.

There is an option to allow the internal clock oscillator to be output on the XTAL2/CLKIO pin. The clock output is driven to the IOVDD logic level. Use of this option may affect the dc performance of the AD7173-8 due to a disturbance that may be introduced by the output driver. The extent to which the performance is affected depends on the IOVDD voltage supply.

Higher IOVDD voltages create a wider logic output swing from the driver and may affect performance to a greater extent. This effect may be further exaggerated if the IOSTRENGTH bit

(Register 0x02, Bit 11) is set at higher IOVDD levels (see Table 26

for more information).

External Crystal

If higher precision, lower jitter clock sources are required, the

AD7173-8 has the ability to use an external crystal to generate the master clock. For the AD7173-8 the required crystal frequency is 16 MHz. Internally this is automatically divided to create the 2 MHz needed for sampling the ADC input.

The crystal is connected to the XTAL1 and XTAL2/CLKIO pins. A recommended crystal for use is the FA-20H: a 16 MHz,

10 ppm, 9 pF crystal from Epson-Toyocom, which is available in a surface-mounted package.

Data Sheet

As shown in Figure 55, allow two capacitors to be inserted from

the traces connecting the crystal to the XTAL1 and XTAL2/CLKIO pins. These capacitors enable circuit tuning. Connect these capacitors to the DGND pin. The value for these capacitors depends on the length and capacitance of the trace connections between the crystal and the XTAL1 and XTAL2/CLKIO pins.

Therefore, the values of these capacitors differ depending on the

PCB layout and the crystal employed. As a result, empirical testing of the circuit is required.

AD7173-8

XTAL1

12

*

CX1

CLKIO/XTAL2

13

CX2

*

*DECOUPLE TO GND

Figure 55. External Crystal Connections

External Clock

The AD7173-8 can also use an externally supplied clock. In systems where this is desirable, the external clock is routed to the XTAL2/CLKIO pin. In this configuration, the XTAL2/

CLKIO pin accepts the externally sourced clock and routes it to the modulator. The logic level of this clock input is defined by the voltage applied to the IOVDD pin.



DIGITAL FILTERS

The AD7173-8 provides the following three flexible filter options to allow optimization of settling time, noise, and rejection:

•

Sinc5 + sinc1 filter

•

Sinc3 filter

•

Enhanced 50 Hz and 60 Hz rejection filters of 2.6 kSPS and lower. The sinc5 block output is fixed at the maximum rate of 31.25 kSPS, and the sinc1 block output data rate

can be varied to control the final ADC output data rate. Figure 57

shows the frequency domain response of the sinc5 + sinc1 filter at a 50 SPS output data rate. The sinc5 + sinc1 filter has a slow roll-off over frequency and narrow notches.

0

50Hz AND 60Hz

REJECTION

FILTERS

–20

SINC5

SINC1

–40

SINC3

–60

Figure 56. Digital Filter Block Diagram

The filter and output data rate are configured by setting the appropriate bits in the filter configuration register for the selected setup. When using the sinc5 + sinc1 filter, it is possible to select different output data rates per channel. When using the sinc3 filter, the user must select the sinc3 filter and use the same output

data rate for all enabled channels. See the Register Details

section for more information.

SINC5 + SINC1 FILTER

The sinc5 + sinc1 filter is targeted at fast switching multiplexed applications and achieves single cycle settling at output data rates

–80

–100

–120

0 50 100

FREQUENCY (Hz)

150

Figure 57. Sinc5 + Sinc1 Filter Response at 50 SPS ODR

The output data rates with the accompanying settling time and

rms noise for the sinc5 + sinc1 filter are listed in Table 19.

6211

5181

4444

3115

2597

1007

503.8

381

200.3

100.5

59.52

49.68

20.01

16.63

10

5

2.5

1.25

Table 19. Output Data Rate (ODR), Settling Time (t

SETTLE

), and Noise Using the Sinc5 + Sinc1 Filter

Default Output

Data Rate

(SPS/Channel);

1

SING_CYC = 1 or with Multiple

Channels Enabled

Output Data

Rate (SPS); 1

SING_CYC = 0 and

Single Channel

Enabled

Settling

Time 1

Notch

Frequency

(Hz)

Noise

(µV rms)

Noise

(µV p-p) 2

Effective

Resolution with

5 V Reference

(Bits)

31,250

15,625

10,417

5208

2597

1007

503.8

381

200.3

100.5

59.52

49.68

20.01

16.63

10

5

2.5

1.25

161 µs

31250

193 µs

15625

225 µs

10417

321 µs

5208

385 µs

3890

993 µs

1156

1.99 ms

539

2.63 ms

401

4.99 ms

206

9.95 ms

102

16.8 ms

60

20.13 ms

50

49.98 ms

20

60.13 ms

16.67

100 ms

10

200 ms

400 ms

5

2.5

800 ms 1.25

22.7

22.9

23.3

23.8

24

24

24

20.2

20.4

20.7

21.1

21.3

22.2

24

24

24

24

24

11

8.9

6.6

5.1

3.3

3

1.7

67

52

40

30

27

15

1.6

1.1

0.75

0.32

0.32

1.5

1.3

0.99

0.71

0.57

0.52

0.32

8.0

6.9

6.0

4.5

3.9

2.2

0.3

0.22

0.15

0.08

0.07

21.4

21.4

22.2

22.4

22.7

23.4

24

24

17.9

18.3

18.5

19.3

19.9

20.1

20.5

21

Peak-to-Peak

Resolution with

5 V Reference

(Bits)

17.5

17.7

1 The settling time (t

SETTLE

) is rounded to the nearest microsecond (µs). This is reflected in the output data rate and switching rate. Switching rate = 1 ÷ t

2 1000 samples.

SETTLE

.



–20

–30

–40

–50

–60

–70

–80

–90

–100

–110

–120

0

SINC3 FILTER

The sinc3 filter achieves the best single-channel noise performance at lower rates and is, therefore, most suitable for single-channel applications. When using the sinc3 filter, the user must select the sinc3 filter and use the same output data rate for all enabled channels. The sinc3 filter always has a settling time equal to

t

SETTLE

= 3/Output Data Rate

Figure 58 shows the frequency domain filter response for the

sinc3 filter. The sinc3 filter has good roll-off over frequency and has wide notches for good notch frequency rejection.

0

–10

150 50

FREQUENCY (Hz)

100

Figure 58. Sinc3 Filter Response

The output data rates with the accompanying settling time and

rms noise for the sinc3 filter are shown in Table 20.

It is possible to fine-tune the output data rate for the sinc3 filter by setting the SINC3_MAPx bit in the Filter Configuration x register.

If this bit is set, the mapping of the filter register changes to directly program the decimation rate of the sinc3 filter. All other options are eliminated. The data rate, when on a single channel, can be calculated using the following equation:

Output Data Rate =

32

f

MOD

×

FILTCONx[1 4:0]

where:

f

MOD

is the modulator rate and is equal to 1 MHz.

FILTCONx[14:0] is the contents of the filter configuration register, excluding the MSB.

For example, an output data rate of 50 SPS can be achieved with

SINC3_MAPx enabled by setting the FILTCONx[14:0] bits to a value of 625.

Table 20. Output Data Rate (ODR), Settling Time (t

SETTLE

), and Noise Using the Sinc3 Filter

Default Output

Data Rate

(SPS/Channel); 1

SING_CYC = 1 or with Multiple

Channels Enabled

10417

5208

3472

1736

868

336

168

133.53

67.76

33.5

19.99

16.67

6.67

5.56

3.33

1.67

0.83

0.42

Output Data

Rate (SPS); 1

SING_CYC = 0 and Single

Channel Enabled

400.6

200.3

100.5

59.98

50

20.01

16.67

31,250

15,625

10,417

5208

2,604

1,008

504

10

5

2.5

1.25

Settling

Time 1

Notch

Frequency

(Hz)

96 µs

192 µs

288 µs

576 µs

1.15 ms

2.98 ms

5.95 ms

7.49 ms 400.6

14.99 ms 200.3

29.85 ms 100.5

50.02 ms 59.98

60 ms 50

149.93 ms 20.01

179.96 ms 16.67

300 ms

600 ms

1.2 sec

2.4 sec

31,250

15,625

10,417

5208

2,604

1,008

504

10

5

2.5

1.25

Noise

(µV rms)

1

0.73

0.55

0.44

0.42

0.25

0.21

210

27

7.8

3.6

2.4

1.5

1.1

0.16

0.11

0.08

0.07

Noise

(µV p-p)

7.6

5.1

3.5

2.5

2.3

1.2

1.1

1665

206

63

28

20

12

8

0.83

0.56

0.41

0.27

24

24

24

24

24

24

24

21.4

22

22.7

23.1

23.3

23.8

24

24

Effective

Resolution with

5 V Reference

(Bits)

15.5

18.5

20.3

21.7

22.4

22.6

22.9

23.4

24

24

18.7

19.2

19.9

20.4

20.5

21.2

21.4

21.6

Peak-to-Peak

Resolution with

5 V Reference

(Bits)

12.8

15.7

17.5

1 The settling time (t

SETTLE

) is rounded to the nearest microsecond (µs). This settling time is reflected in the output data rate and switching rate. Switching rate = 1 ÷ t

SETTLE

.



SINGLE CYCLE SETTLING

By default, the AD7173-8 is configured with the SING_CYC bit in the ADC Mode Register. This means that only fully settled data is output, thus putting the ADC into a single cycle settling mode.

This mode achieves single cycle settling by reducing the output data rate to be equal to the settling time of the ADC for the selected output data rate. This bit has no effect with the sinc5 + sinc1 at output data rates of 2.6 kSPS and lower or when multiple channels are enabled.

Figure 59 shows the same step on the analog input but with

single cycle settling enabled. At least a single cycle is required for the output to be fully settled. The output data rate is equal to the settling time of the filter at the selected output data rate.

ANALOG

INPUT

ADC

OUTPUT

FULLY

SETTLED t

SETTLE

Figure 59. Step Input with Single Cycle Settling

Figure 60 shows a step on the analog input with this mode

disabled, one channel enabled and the Sinc3 filter selected.

At least three cycles are required after the step change for the output to reach the final settled value. However, the ADC can then output a new conversion result at the higher rate of 1/ODR.

ANALOG

INPUT

FULLY

SETTLED

ADC

OUTPUT

1/ODR

Figure 60. Step Input Without Single Cycle Settling

ENHANCED 50 Hz AND 60 Hz REJECTION FILTERS

The enhanced filters are designed to provide rejection of 50 Hz and 60 Hz simultaneously and to allow the user to trade off settling time and rejection. These filters can operate up to 27.27 SPS or can reject up to 90 dB of 50 Hz ± 1 Hz and 60 Hz ± 1 Hz interference. These filters are realized by post filtering the output of the sinc5 + sinc1 filter. For this reason, the sinc5 + sinc1 filter

must be selected when using the enhanced filters. Table 21 shows

the output data rates with the accompanying settling time,

rejection, and rms noise. Figure 61 to Figure 68 show the

frequency domain plots of the responses from the enhanced filters.

Table 21. Enhanced Filter Output Data Rate (ODR), Noise, Settling Time (t

SETTLE

), and Rejection Using the Enhanced Filters

Output

Data

Rate (SPS)

Settling

Time (ms)

Simultaneous

Rejection of

50 Hz ± 1 Hz and

60 Hz ± 1 Hz (dB)

1

Noise

(µV rms)

Noise

(µV p-p)

Effective


Peak-to-Peak

Resolution (Bits) Reference

27.27 36.67 47 0.45 3.6 24.4 21.4

See Figure 61 and Figure 64

25

20

16.67

40.0

50.0

60.0

62

85

90

0.44

0.41

0.41

3.6

3.0

3.0

24.4

24.5

24.5

21.4

21.7

21.7




1

Master clock = 2 MHz.


AD7173-8

50 Hz and 60 Hz Rejection Filter Frequency Domain Plots

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

0 100 200 300

FREQUENCY (Hz)

400 500

Figure 61. 27.27 SPS ODR, 36.67 ms Settling Time

600

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

0 100 200 300

FREQUENCY (Hz)

400 500

Figure 62. 25 SPS ODR, 40 ms Settling Time

600

–50

–60

–70

–80

–90

–100

0

0

–10

–20

–30

–40

100 200 300

FREQUENCY (Hz)

400 500


600


Data Sheet

–40

–50

–60

–70

–80

–90

0

–10

–20

–30

–100

40 45 50 55

FREQUENCY (Hz)

60 65

Figure 64. 27.27 SPS ODR, 36.67 ms Settling Time

70

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

40 45 50 55

FREQUENCY (Hz)

60 65


70

–50

–60

–70

–80

–90

–100

40

0

–10

–20

–30

–40

45 50 55

FREQUENCY (Hz)

60 65


70

Data Sheet

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

0 100 200 300

FREQUENCY (Hz)

400 500

Figure 67. 16.667 SPS ODR, 60 ms Settling Time

600

AD7173-8

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

40 45 50 55

FREQUENCY (Hz)

60 65

Figure 68. 16.667 SPS ODR, 60 ms Settling Time

70


AD7173-8

OPERATING MODES

CONTINUOUS CONVERSION MODE

Continuous conversion (see Figure 69) is the default power-up

mode. The AD7173-8 converts continuously, and the RDY bit in the status register goes low each time a conversion is complete.

If CS is low, the DOUT/RDY line also goes low when a conversion is complete. To read a conversion, the user writes to the communications register, indicating that the next operation is a read of the data register. When the data-word has been read from the data register, DOUT/RDY goes high. The user can read this register additional times, if required. However, the user must ensure that the data register is not being accessed at the completion of the next conversion.

Data Sheet

When several channels are enabled, the ADC automatically sequences through the enabled channels, performing one conversion on each channel. When all channels are converted, the sequence starts again with the first channel. The channels are converted, in order, from lowest enabled channel to highest enabled channel. The data register is updated as soon as each conversion is available. The DOUT/RDY pin pulses low each time a conversion is available. The user must then read the conversion result while the ADC converts the next enabled channel; otherwise, the new conversion result is lost.

If the DATA_STAT bit in the interface mode register is set to 1, the contents of the status register, along with the conversion data, are output each time the data register is read. The status register indicates the channel to which the conversion corresponds.

CS

0x44 0x44

DIN

DOUT/RDY

SCLK

DATA DATA

Figure 69. Continuous Conversion Mode


Data Sheet

CONTINUOUS READ MODE

In continuous read mode (see Figure 70), it is not required that

the communications register be written to before the ADC data is read. Instead, apply the required number of SCLKs after

DOUT/RDY goes low to indicate the end of a conversion.

When the conversion is read, DOUT/RDY returns high until the next conversion is available. In this mode, the data can be read only once. The user must also ensure that the data-word is read before the next conversion is complete. If the user has not read the conversion before the completion of the next conversion or if insufficient serial clocks are applied to the AD7173-8 to read the word, the serial output register is reset shortly before the next conversion is complete, and the new conversion is placed in the output serial register. To use continuous read mode, the

ADC must be configured for continuous conversion mode.

CS

AD7173-8

To enable continuous read mode, set the CONTREAD bit in the interface mode register. When this bit is set, the only serial interface operations possible are reads from the data register. To exit continuous read mode, issue a dummy read of the ADC data register command (0x44) while RDY is low. Alternatively, apply a software reset, that is, 64 SCLKs with CS = 0 and DIN = 1. This resets the

ADC and all register contents. These are the only commands that the interface recognizes after it is placed in continuous read mode. Hold DIN low in continuous read mode until an instruction is to be written to the device.

If multiple ADC channels are enabled, each channel is output in turn, with the status bits being appended to the data if the

DATA_STAT bit is set in the interface mode register. The status register indicates the channel to which the conversion corresponds.

0x02

0x0080

DIN

DOUT/RDY

SCLK

DATA

DATA DATA

Figure 70. Continuous Read Mode


AD7173-8

SINGLE CONVERSION MODE

In single conversion mode (see Figure 71), the

AD7173-8 performs a single conversion and is placed in standby mode after the conversion is complete. DOUT/RDY goes low to indicate the completion of a conversion. After the data-word is read from the data register, DOUT/RDY goes high. The data register can be read several times, if required, even when DOUT/RDY is high.

If several channels are enabled, the ADC automatically sequences through the enabled channels and performs a conversion on each channel. When a conversion is started, DOUT/RDY goes high and remains high until a valid conversion is available and CS is low. As soon as the conversion is available, DOUT/RDY goes low. The

CS

Data Sheet

ADC then selects the next channel and begins a conversion. The user must read the present conversion while the next conversion is being performed. As soon as the next conversion is complete, the data register is updated; therefore, the period in which to read the conversion is limited. After the ADC performs a single conversion on each of the selected channels, it returns to standby mode.

If the DATA_STAT bit in the interface mode register is set to 1, the contents of the status register, along with the conversion, are output each time the data register is read. The four LSBs of the status register indicate the channel to which the conversion corresponds.

0x44 0x01 0x2010

DIN

DOUT/RDY

SCLK

DATA

Figure 71. Single Conversion Mode


Data Sheet

STANDBY AND POWER-DOWN MODES

In standby mode, most blocks are powered down. The LDOs remain active such that the registers maintain their contents.

The internal reference remains active, if enabled; and the crystal oscillator remains active, if selected. To power down the reference in standby mode, set the REF_EN bit in the ADC mode register to 0. To power down the clock in standby mode, set the CLOCKSEL bits in the ADC mode register to 00

(internal oscillator).

In power-down mode, all blocks are powered down, including the LDOs. All registers lose their contents, and the GPIO outputs are placed in tristate. To prevent accidental entry to power-down mode, the ADC must first be placed into standby mode. Exiting power-down mode requires 64 SCLKs with CS = 0 and DIN = 1, that is, a serial interface reset. A delay of 500 µs is recommended before issuing a subsequent serial interface command to allow the LDO to power up.

CALIBRATION MODES

The AD7173-8 provides three calibration modes that can be used to eliminate the offset and gain errors on a per setup basis:

•

Internal zero-scale calibration mode

•

System zero-scale calibration mode

•

System full-scale calibration mode

Only one channel can be active during calibration. After each conversion, the ADC conversion result is scaled using the ADC calibration registers before being written to the data register.

The default value of the offset register is 0x800000, and the nominal value of the gain register is 0x555555. The calibration range of the ADC gain is from 0.4 × V

REF

to 1.05 × V

REF

. The following equations show the calculations that are used. In unipolar mode, the ideal relationship—that is, not taking into account the ADC gain error and offset error—is as follows:

Data

=





0 .

75

×

V

REF

V

IN

×

2

23 −

(

Offset

−

0x800000 )





×

Gain

0x400000

×

2

In bipolar mode, the ideal relationship—that is, not taking into account the ADC gain error and offset error—is as follows:

Data

=







0.75

×

V

REF

V

IN

×

2

23 −

(

Offset

−

0x800000)







×

Gain

0x400000

+

0x800000

AD7173-8

To start a calibration, write the relevant value to the MODE bits in the ADC mode register. The DOUT/RDY pin and the RDY bit in the status register go high when the calibration initiates. When the calibration is complete, the contents of the corresponding offset or gain register are updated, the RDY bit in the status register is set, the DOUT/RDY pin returns low (if CS is low), and the AD7173-8 reverts to standby mode.

During an internal offset calibration, the selected positive analog input pin is disconnected, and both modulator inputs are connected internally to the selected negative analog input pin. For this reason, it is necessary to ensure that the voltage on the selected negative analog input pin does not exceed the allowed limits and is free from excessive noise and interference.

System calibrations, however, expect the system zero-scale

(offset) and system full-scale (gain) voltages to be applied to the

ADC pins before initiating the calibration modes. As a result, errors external to the ADC are removed.

From an operational point of view, treat a calibration like another ADC conversion. An offset calibration, if required, must always be performed before a full-scale calibration. Set the system software to monitor the RDY bit in the status register or the DOUT/RDY pin to determine the end of a calibration via a polling sequence or an interrupt-driven routine. All calibrations require a time that is equal to the settling time of the selected filter and the output data rate to be completed.

An internal offset calibration, system zero-scale calibration, and system full-scale calibration can be performed at any output data rate. Using lower output data rates results in better calibration accuracy and is accurate for all output data rates. A new calibration is required for a given channel if the reference source for that channel is changed.

The offset error is typically ±40 µV, and an offset calibration reduces the offset error to the order of the noise. The gain error is factory calibrated at ambient temperature. Following this calibration, the gain error is typically ±0.001%.

The AD7173-8 provides the user with access to the on-chip calibration registers, allowing the microprocessor to read the calibration coefficients of the device and to write its own calibration coefficients. A read or write of the offset and gain registers can be performed at any time except during an internal or self calibration.


AD7173-8

DIGITAL INTERFACE

The programmable functions of the AD7173-8 are via the SPI serial interface. The serial interface of the AD7173-8 consists of four signals: CS, DIN, SCLK, and DOUT/RDY. The DIN line is used to transfer data into the on-chip registers, and DOUT/RDY is used to access data from the on-chip registers. SCLK is the serial clock input for the device, and all data transfers (either on DIN or on DOUT/RDY) occur with respect to the SCLK signal.

The DOUT/RDY pin also functions as a data-ready signal, with the line going low if CS is low when a new data-word is available in the data register. The pin is reset high when a read operation from the data register is complete. The DOUT/RDY pin also goes high before updating the data register to indicate when not to read from the device to ensure that a data read is not attempted while the register is being updated. Take care to avoid reading from the data register when DOUT/RDY is about to go low. The best method to ensure that no data read occurs is to always monitor the DOUT/RDY line; start reading the data register as soon as

DOUT/RDY goes low; and ensure a sufficient SCLK rate, such that the read is completed before the next conversion result. CS is used to select a device. It can be used to decode the AD7173-8 in systems where several components are connected to the serial bus.

Figure 2 and Figure 3 show timing diagrams for interfacing to

the AD7173-8

using CS to decode the part. Figure 2 shows the

timing for a read operation from the AD7173-8

, and Figure 3

shows the timing for a write operation to the AD7173-8 . It is possible to read from the data register several times, even though the DOUT/RDY line returns high after the first read operation.

However, take care to ensure that the read operations are completed before the next output update occurs. In continuous read mode, the data register can be read only once.

The serial interface can operate in 3-wire mode by tying CS low.

In this case, the SCLK, DIN, and DOUT/RDY lines are used to communicate with the AD7173-8 . The end of the conversion can also be monitored using the RDY bit in the status register.

The serial interface can be reset by writing 64 SCLKs with CS =

0 and DIN = 1. A reset returns the interface to the state in which it expects a write to the communications register. This operation resets the contents of all registers to their power-on values.

Following a reset, allow a period of 500 µs before addressing the serial interface.

CHECKSUM PROTECTION

The AD7173-8 has a checksum mode that can be used to improve interface robustness. Using the checksum ensures that only valid data is written to a register and allows data read from a register to be validated. If an error occurs during a register write, the CRC_ERROR bit is set in the status register. However,

Data Sheet

to ensure that the register write was successful, it is important to read back the register and verify the checksum.

For CRC checksum calculations during a write operation, the following polynomial is always used:

x

8 + x 2 + x + 1

During read operations, the user can select between this polynomial and a similar XOR function. The XOR function requires less time to process on the host microcontroller than the polynomial-based checksum. The CRC_EN bits in the interface mode register enable and disable the checksum and allow the user to select between the polynomial check and the simple XOR check.

The checksum is appended to the end of each read and write transaction. The checksum calculation for the write transaction is calculated using the 8-bit command word and the 8- to 24-bit data. For a read transaction, the checksum is calculated using

the command word and the 8- to 32-bit data output. Figure 72 and Figure 73 show SPI write and read transactions, respectively.

8-BIT COMMAND UP TO 24-BIT INPUT 8-BIT CRC

CS

DIN

SCLK

CMD DATA CRC

Figure 72. SPI Write Transaction with CRC

CS

8-BIT COMMAND UP TO 32-BIT OUTPUT 8-BIT CRC

DIN

CMD

DOUT/

RDY

DATA CRC

SCLK

Figure 73. SPI Read Transaction with CRC

If checksum protection is enabled when continuous read mode is active, there is an implied read data command of 0x44 before every data transmission that must be accounted for when calculating the checksum value. This ensures a nonzero checksum value even if the ADC data equals 0x000000.



CRC CALCULATION

Polynomial

The checksum, which is eight bits wide, is generated using the following polynomial:

x

8

+ x

2

+ x + 1

To generate the checksum, the data is left shifted by eight bits to create a number ending in eight Logic 0s. The polynomial is aligned such that its MSB is adjacent to the leftmost Logic 1 of the data. An exclusive OR (XOR) function is applied to the data to produce a new, shorter number. The polynomial is again aligned so that its MSB is adjacent to the leftmost Logic 1 of the new result, and the procedure is repeated. This process is repeated until the original data is reduced to a value less than the polynomial.

This is the 8-bit checksum.

Example of a Polynomial CRC Calculation—24-Bit Word: 0x654321 (Eight Command Bits and 16-Bit Data)

An example of generating the 8-bit checksum using the polynomial based checksum is as follows:

Initial value 011001010100001100100001

01100101010000110010000100000000 left shifted eight bits polynomial x 8 + x 2 + x + 1 = 100000111

100100100000110010000100000000

100000111

100011000110010000100000000

100000111

11111110010000100000000

100000111

1111101110000100000000

100000111

111100000000100000000

100000111

11100111000100000000

100000111

1100100100100000000

100000111

100101010100000000

100000111

101101100000000

100000111

1101011000000

100000111

101010110000

100000111

1010001000

100000111

10000110

XOR result polynomial

XOR result polynomial

XOR result polynomial value









XOR result polynomial value checksum = 0x86.



XOR Calculation

The checksum, which is 8-bits wide, is generated by splitting the data into bytes and then performing an XOR of the bytes.

Example of an XOR Calculation—24-Bit Word: 0x654321 (Eight Command Bits and 16-Bit Data)

Using the previous example,

Divide into three bytes: 0x65, 0x43, and 0x21

01100101

01000011

0x65

0x43

00100110

00100001

00000111

XOR result

0x21

CRC


Data Sheet

INTEGRATED FUNCTIONS

The AD7173-8 has a number of integrated functions that can be used to improve usefulness in a number of applications, as well as for diagnostic purposes in safety conscious applications.

GENERAL-PURPOSE I/O

The AD7173-8 has two general-purpose digital input/output pins (GPIO0, GPIO1) and two general-purpose digital output pins (GPO2, GPO3). As the naming convention suggests, the

GPIO0 and GPIO1 pins can be configured as inputs or outputs, but GPO2 and GPO3 are outputs only. The GPIO and GPO pins are enabled using the following bits in the GPIOCON register:

IP_EN0, IP_EN1 (or OP_EN0, OP_EN1) for GPIO0 and

GPIO1, and OP_EN2_3 for GPO2 and GPO3.

When the GPIO0 or GPIO1 pin is enabled as an input, the logic level at the pin is contained in the GP_DATA0 or GP_DATA1 bit, respectively. When the GPIO0, GPIO1, GPO2, or GPO3 pin is enabled as an output, the GP_DATA0, GP_DATA1, GP_DATA2, or GP_DATA3 bit, respectively, determines the logic level output at the pin. The logic levels for these pins are referenced to AVDD1 and AVSS; therefore, outputs have an amplitude of either 5 V or

3.3 V depending on the AVDD1 − AVSS voltage.

The ERROR pin can also be used as a general-purpose output if the ERR_EN bits in the GPIOCON register are set to 11. In this configuration, the ERR_DAT bit in the GPIOCON register determines the logic level output at the ERROR pin. The logic level for the pin is referenced to IOVDD and DGND, and the

ERROR pin has an active pull-up.

EXTERNAL MULTIPLEXER CONTROL

If an external multiplexer is used to increase the channel count, the multiplexer logic pins can be controlled using the AD7173-8

GPIO and GPO pins. When the MUX_IO bit is set in the

GPIOCON register (Address 0x06, Bit 12), the timing of the

GPIO pins is controlled by the ADC; therefore, the channel change is synchronized with the ADC, eliminating any need for external synchronization.

DELAY

It is possible to insert a programmable delay before the AD7173-8 begins taking samples when using the sinc5 + sinc1 filter. This allows for an external amplifier or multiplexer to settle and can also relax the specification requirements for the external amplifier or multiplexer. There are 8 programmable settings ranging from

0 μs to 8 ms which can be set using the DELAY bits in the ADC

Mode Register (Address 0x01, Bits[10:8]).

If a delay greater than 0 μs is selected and HIDE_DELAY in the

Interface Mode Register (Address 0x02, Bit 10) is set to 1, then this delay is added to the conversion time for each sample regardless of selected output data rate.

If HIDE_DELAY is set to 0 and the selected delay is less than half of the conversion time, then the delay can be absorbed by reducing the number of averages performed. This keeps the

AD7173-8

conversion time the same but may affect the noise performance, depending on the length of the delay compared to the conversion time. It is only possible to absorb the delay for output data rates less than 2.6 kSPS, with the exception of four rates which cannot absorb any delay: 381 SPS, 59.52 SPS, 49.68 SPS and 16.63 SPS.

16-BIT/24-BIT CONVERSIONS

By default, the AD7173-8 generates 24-bit conversions. However, the width of the conversions can be reduced to 16 bits. Setting

Bit WL16 in the interface mode register to 1 rounds all data conversions to 16 bits. Clearing this bit sets the width of the data conversions to 24 bits.

SERIAL INTERFACE RESET (DOUT_RESET)

The serial interface is reset when each read operation is complete.

The instant at which the serial interface is reset is programmable.

By default, the serial interface is reset after a short period of time following the last SCLK rising edge, the SCLK edge on which the LSB is read by the processor. By setting the DOUT_RESET bit to 1 in the interface mode register, the instant at which the interface is reset is controlled by the CS rising edge. In this case, the DOUT/RDY pin continues to output the LSB of the register being read until CS is taken high. Only on the CS rising edge is the interface reset. This configuration is useful if the CS signal is used to frame all read operations. If CS is not used to frame all read operations, DOUT_RESET must be set to 0 so that the interface is reset following the last SCLK edge in the read operation.

SYNCHRONIZATION

Normal Synchronization

When the SYNC_EN bit in the GPIOCON register is set to 1, the SYNC pin functions as a synchronization pin. The SYNC input allows the user to reset the modulator and the digital filter without affecting any of the setup conditions on the part.

This allows the user to start gathering samples of the analog input from a known point in time, that is, the rising edge of

SYNC. This pin must be low for at least one master clock cycle to ensure that synchronization occurs. If multiple channels are enabled, the sequencer is reset to the first enabled channel.

If multiple AD7173-8 devices are operated from a common master clock, they can be synchronized so that their data registers are updated simultaneously. This is normally done after each

AD7173-8 has performed its own calibration or has calibration coefficients loaded into its calibration registers. A falling edge on the SYNC pin resets the digital filter and the analog modulator and places the AD7173-8 into a consistent known state. While the SYNC pin is low, the AD7173-8 is maintained in this state.

On the SYNC rising edge, the modulator and filter are taken out of this reset state, and on the next master clock edge, the part starts to gather input samples again.

The part is taken out of reset on the master clock falling edge following the SYNC low-to-high transition. Therefore, when



multiple devices are being synchronized, take the SYNC pin high on the master clock rising edge to ensure that all devices begin sampling on the master clock falling edge. If the SYNC pin is not taken high in sufficient time, it is possible to have a difference of one master clock cycle between the devices; that is, the instant at which conversions are available differs from part to part by a maximum of one master clock cycle.

The SYNC pin can also be used as a start conversion command.

In this mode, the rising edge of SYNC starts a conversion, and the falling edge of RDY indicates when the conversion is complete.

The settling time of the filter must be allowed for each data register update.

Alternate Synchronization

Setting Bit ALT_SYNC in the interface mode register to 1 enables an alternate synchronization scheme. The SYNC_EN bit in the

GPIOCON register must be set to 1 to enable this alternate scheme.

In this mode, the SYNC pin operates as a start conversion command when several channels of the AD7173-8 are enabled. When

SYNC is taken low, the ADC completes the conversion on the current channel, selects the next channel in the sequence, and then waits until SYNC is taken high to commence the conversion.

The RDY pin goes low when the conversion is complete on the current channel, and the data register is updated with the corresponding conversion. Therefore, the SYNC command does not interfere with the sampling on the currently selected channel but allows the user to control the instant at which the conversion begins on the next channel in the sequence.

This mode can be used only when several channels are enabled.

It is not recommended to use this mode when a single channel is enabled.

ERROR FLAGS

The status register contains three error bits—ADC_ERROR,

CRC_ERROR, and REG_ERROR—that flag errors with the

ADC conversion, errors with the CRC check, and errors due to changes in the registers, respectively. In addition, the ERROR pin can indicate that an error has occurred.

ADC_ERROR

The ADC_ERROR bit in the status register flags any errors that occur during the conversion process. The flag is set when an overrange or underrange occurs at the output of the ADC. When an underrange or overrange occurs, the ADC also outputs all 0s or all

1s, respectively. This flag is reset only when the underrange or overrange is removed. It is not reset by a read of the data register.

CRC_ERROR

If the CRC value that accompanies a write operation does not correspond with the information sent, the CRC_ERROR flag is set. The flag is reset as soon as the status register is explicitly read.

REG_ERROR

This flag is used in conjunction with the REG_CHECK bit in the interface mode register. When the REG_CHECK bit is set,

Rev. A | Page 44 of 64 the AD7173-8 monitors the values in the on-chip registers. If a bit changes, the REG_ERROR bit is set. Therefore, for writes to the on-chip registers, ensure that REG_CHECK is set to 0.

When the registers have been updated, the REF_CHK bit can be set to 1. The AD7173-8 calculates a checksum of the on-chip registers. If one of the register values has changed, the

REG_ERROR bit is set. If an error is flagged, the REG_CHECK bit must be set to 0 to clear the REG_ERROR bit in the status register. The register check function does not monitor the data register, status register, or interface mode register.

ERROR Pin

The ERROR pin functions as an error input/output pin or a general-purpose output pin. The ERR_EN bits in the GPIOCON register determine the function of the pin.

When the ERR_EN bits are set to 10, the pin functions as an open-drain error output pin. The three error bits in the status register (ADC_ERROR, CRC_ERROR, and REG_ERROR) are

OR’ed, inverted, and mapped to the ERROR pin. Therefore, the

ERROR pin indicates that an error has occurred. To identify the error source, read the status register.

When ERR_EN bits are set to 01, the ERROR pin functions as an error input pin. The error pin of another component can be connected to the AD7173-8 ERROR pin so that the AD7173-8 indicates when an error occurs on either itself or the external component.

The value on the ERROR pin is inverted and OR’ed with the errors from the ADC conversion, and the result is indicated via the

ADC_ERROR bit in the status register. The value of the ERROR pin is reflected in the ERR_DAT bit in the status register.

The ERROR pin is disabled when the ERR_EN bits are set to 00.

When the ERR_EN1 bits are set to 11, the ERROR pin operates as a general-purpose output.

DATA_STAT

The contents of the status register can be appended to each conversion on the AD7173-8 . This is a useful function if several channels are enabled. Each time a conversion is output, the contents of the status register are appended. The four LSBs of the status register indicate to which channel the conversion corresponds. In addition, the user can determine if any errors are being flagged by the error bits.

IOSTRENGTH BIT

The serial interface can operate with a power supply as low as

2 V. At higher speeds (from 10 MHz to 15 MHz upward), the

DOUT/RDY pin may not have sufficient drive strength if there is moderate parasitic capacitance on the board. The IOSTRENGTH bit in the interface mode register increases the drive strength of the DOUT/RDY pin. It is recommended that this bit be kept to its default value unless a high frequency SPI SCLK (that is,

~15 MHz upward) is being used.

Data Sheet

GROUNDING AND LAYOUT

The analog inputs and reference inputs are differential and, therefore, most of the voltages in the analog modulator are common-mode voltages. The high common-mode rejection of the part removes common-mode noise on these inputs. The analog and digital supplies to the AD7173-8 are independent and separately pinned out to minimize coupling between the analog and digital sections of the device. The digital filter provides rejection of broadband noise on the power supplies, except at integer multiples of the master clock frequency.

The digital filter also removes noise from the analog and reference inputs, provided that these noise sources do not saturate the analog modulator. As a result, the AD7173-8 is more immune to noise interference than a conventional high resolution converter. However, because the resolution of the

AD7173-8 is high and the noise levels from the converter are so low, take care with regard to grounding and layout.

The printed circuit board (PCB) that houses the ADC must be designed so that the analog and digital sections are separated and confined to certain areas of the board. A minimum etch technique is generally best for ground planes because it results in the best shielding.

In any layout, the user must keep in mind the flow of currents in the system, ensuring that the paths for all return currents are as close as possible to the paths the currents took to reach their destinations.

Avoid running digital lines under the device because this couples noise onto the die and allows the analog ground plane to run under the AD7173-8 to prevent noise coupling. The power supply lines to the AD7173-8 must use as wide a trace as possible to provide low impedance paths and reduce glitches on the power supply line. Shield fast switching signals like clocks

AD7173-8

with digital ground to prevent radiating noise to other sections of the board and never run clock signals near the analog inputs.

Avoid crossover of digital and analog signals. Run traces on opposite sides of the board at right angles to each other. This reduces the effects of feedthrough on the board. A microstrip technique is by far the best but is not always possible with a double-sided board. In this technique, the component side of the board is dedicated to ground planes, whereas signals are placed on the solder side.

Good decoupling is important when using high resolution ADCs.

The AD7173-8 has three power supply pins: AVDD1, AVDD2, and IOVDD. The AVDD1 and AVDD2 pins are referenced to

AVSS, and the IOVDD pin is referenced to DGND. Decouple

AVDD1 and AVDD2 with a 10 μF tantalum capacitor in parallel with a 0.1 μF capacitor to AVSS on each pin. Place the 0.1 μF capacitor as near as possible to the device on each supply, ideally right up against the device. Decouple IOVDD with a 10 μF tantalum capacitor, in parallel with a 0.1 μF capacitor to DGND.

Decouple all analog inputs to AVSS. If an external reference is used, decouple the REF+ and REF− pins to AVSS.

The AD7173-8 also has two on-board LDO regulators—one that regulates the AVDD2 supply and one that regulates the

IOVDD supply. For the REGCAPA pin, it is recommended that

1 μF and 0.1 μF capacitors to AVSS be used. Similarly, for the

REGCAPD pin, it is recommended that 1 μF and 0.1 μF capacitors to DGND be used.

If using the AD7173-8 for split supply operation, a separate plane must be used for AVSS. As an example, the EVAL-AD7173-8SDZ customer evaluation board uses a 4-layer PCB, with the largest

central section of Layer 3 used as the AVSS plane. Figure 74 shows

the PCB layout of this layer.

Figure 74. EVAL-AD7173-8SDZ , PCB Layer 3


AD7173-8

REGISTER SUMMARY

Table 22. Register Summary


0x00 COMMS [7:0] WEN R/W

0x00 STATUS [7:0] RDY

Bit 5 Bit 4

ADC_ERROR CRC_ERROR REG_ERROR

Bit 3 Bit 2 Bit 1

CHANNEL

Bit 0

Data Sheet

Reset

0x80

RW

R

0x02 IFMODE [15:8]

MODE CLOCKSEL RESERVED

IOSTRENGTH RW

0x03 REGCHECK [23:16]

[15:8]

[7:0]

0x04 DATA [23:0]

0x06 GPIOCON [15:8] RESERVED PDSW

0x07 ID [15:8]

0x10 CH0

0x11 CH1

0x12 CH2

0x13 CH3

0x14 CH4

0x15 CH5

0x16 CH6

0x17 CH7

0x18 CH8

0x19 CH9

0x1A CH10

0x1B CH11

[7:0]

[15:8] CH_EN0

[7:0]

[15:8] CH_EN1

[7:0]

[15:8] CH_EN2

[7:0]

[15:8] CH_EN3

[7:0]

[15:8] CH_EN4

[7:0]

[15:8] CH_EN5

[7:0]

[15:8] CH_EN6

[7:0]

[15:8] CH_EN7

[7:0]

[15:8] CH_EN8

[7:0]

[15:8] CH_EN9

[7:0]

[15:8] CH_EN10

[7:0]

[15:8] CH_EN11

REGISTER_CHECK[15:8]

REGISTER_CHECK[7:0]

OP_EN2_3 MUX_IO

SETUP_SEL0

AINPOS0[2:0]

SETUP_SEL1

AINPOS1[2:0]

SETUP_SEL2

AINPOS2[2:0]

SETUP_SEL3

AINPOS3[2:0]

SETUP_SEL4

AINPOS4[2:0]

SETUP_SEL5

AINPOS5[2:0]

SETUP_SEL6

AINPOS6[2:0]

SETUP_SEL7

AINPOS7[2:0]

SETUP_SEL8

AINPOS8[2:0]

SETUP_SEL9

AINPOS9[2:0]

AINPOS10[2:0]

ID[15:8]

ID[7:0]

CRC_EN

SYNC_EN

RESERVED

ERR_EN

AINNEG0

AINNEG1

AINNEG2

AINNEG3

AINNEG4

AINNEG5

AINNEG6

AINNEG7

AINNEG8

AINNEG9

AINNEG10

ERR_DAT 0x0800 RW

0x30DX 1 R

AINPOS11[2:0] AINNEG11

0x1C CH12

0x1D CH13

0x1E CH14

0x1F CH15

[7:0]

[15:8] CH_EN12

[7:0]

[15:8] CH_EN13

[7:0]

[15:8] CH_EN14

[7:0]

[15:8] CH_EN15

[7:0]

AINPOS12[2:0]

AINPOS13[2:0]

AINPOS14[2:0]

AINPOS15[2:0]

RESERVED BI_

UNIPOLAR0

AINNEG12

AINNEG13

AINNEG14

AINNEG15

REF_BUF 0[1:0] AIN_BUF 0[1:0] 0x1000

REF_SEL0 RESERVED

RW

EN0

EN1

EN2

BUFCHOPMAX

0

RESERVED

BUFCHOPMAX

1

RESERVED

BUFCHOPMAX

2

BI_UNIPOLAR1 REF_BUF 1[1:0]

REFSEL1 RESERVED


AIN_BUF 1[1:0]

AIN_BUF 2[1:0]

0x1000

0x1000

REFSEL2 RESERVED

RW

RW



Reg Name Bits Bit 7

EN3

Bit 6

RESERVED

Bit 5

BUFCHOPMAX

3

Bit 4

BI_UNIPOLAR3

Bit 3 Bit 2

REF_BUF 3[1:0]

Bit 1 Bit 0

AIN_BUF 3[1:0]

Reset

0x1000

REFSEL3 RESERVED

RW

RW

EN4

EN5

RESERVED

BUFCHOPMAX

4

RESERVED

BUFCHOPMAX

5

RESERVED

BUFCHOPMAX

6

BI_UNIPOLAR4 REF_BUF 4[1:0] AIN_BUF 4[1:0] 0x1000

REFSEL4 RESERVED


REFSEL5 RESERVED


REFSEL6 RESERVED

RW

RW

RW

EN6

RESERVED

EN7

0x28 FILTCON0 [15:8] SINC3_MAP0

BUFCHOPMAX

7

AIN_BUF 7[1:0] 0x1000

REFSEL7 RESERVED

RESERVED


ENHFILTEN0 ENHFILT0

RW

0x0000 RW


0x2A FILTCON2 [15:8] SINC3_MAP2

0x2B FILTCON3 [15:8] SINC3_MAP3

0x2C FILTCON4 [15:8] SINC3_MAP4

0x2D FILTCON5 [15:8] SINC3_MAP5

0x2E FILTCON6 [15:8] SINC3_MAP6

0x2F FILTCON7 [15:8] SINC3_MAP7

0x30 OFFSET0 [23:0]

0x31 OFFSET1 [23:0]

0x32 OFFSET2 [23:0]

0x33 OFFSET3 [23:0]

ORDER0

RESERVED

ORDER1

RESERVED

ORDER2

RESERVED

ORDER3

RESERVED

ORDER4

RESERVED

ORDER5

RESERVED

ORDER6

RESERVED

ORDER7

ENHFILTEN1

ENHFILTEN2

ENHFILTEN3

ENHFILTEN4

ENHFILTEN5

ENHFILTEN6

ENHFILTEN7

ODR0

ODR1

ODR2

ODR3

ODR4

ODR5

ODR6

ODR7

ENHFILT1

ENHFILT2

ENHFILT3

ENHFILT4

ENHFILT5

ENHFILT6

ENHFILT7

0x0000 RW

0x0000 RW

0x0000 RW

0x0000 RW

0x0000 RW

0x0000 RW

0x0000 RW

0x34 OFFSET4 [23:0]

0x35 OFFSET5 [23:0]

0x36 OFFSET6 [23:0]

0x37 OFFSET7 [23:0]

0x38 GAIN0 [23:0]

0x39 GAIN1 [23:0]

GAIN0[23:0]

GAIN1[23:0]

0x3A GAIN2

0x3B GAIN3

0x3C GAIN4

0x3D GAIN5

[23:0]

[23:0]

GAIN3[23:0]

GAIN5[23:0]

0x5XXXX0

2

RW

0x5XXXX0

2

RW

0x5XXXX0

2

RW

0x5XXXX0

2

RW

0x5XXXX0

2

RW

0x5XXXX0

2

RW

0x3E GAIN6 [23:0] GAIN6[23:0]

2

RW

0x3F GAIN7 [23:0] GAIN7[23:0]

0x5XXXX0

2

RW

1

X = don’t care. The value of X is specific to the ADC.

2 The value of X varies, depending on the IC that is used.


AD7173-8

REGISTER DETAILS

COMMUNICATIONS REGISTER

Address: 0x00, Reset: 0x00, Name: COMMS

Table 23. Bit Descriptions for COMMS

Bits Bit Name Settings

7

WEN

6 R/W

[5:0] RA

Description

This bit must be low to begin communications with the ADC.

This bit determines if the command is a read or write operation.

The register address bits determine which register is to be read from or written to as part of the current communication.

000000 register

000001 ADC mode register

000010 Interface mode register

000011 Register checksum register

000110 GPIO configuration register

010000 Channel 0 register
















100000 Setup Configuration 0 register








101000 Filter Configuration 0 register








110000 Offset 0 register



Data Sheet

Reset

0x0

Access

W

0x0 W

0x00 W

Data Sheet

Bits Bit Name Settings Description







111000 Gain 0 register








AD7173-8

Reset Access



STATUS REGISTER

Address: 0x00, Reset: 0x80, Name: STATUS

The status register is an 8-bit register that contains ADC and serial interface status information. It can optionally be appended to the data register by setting the DATA_STAT bit in the interface mode register (Bit 6, Register 0x02).

Table 24. Bit Descriptions for STATUS

Bits

7

Bit Name

RDY

Settings Description

The status of RDY is output to the DOUT/RDYpin whenever CS is low and a register is not being read. This bit goes low when the ADC has written a new result to the data register. In ADC calibration modes, this bit goes low when the ADC has written the calibration result. RDY is brought high automatically by a read of the data register.

0 New data result available

1 Awaiting new data result

6 ADC_ERROR This bit, by default, indicates if an ADC overrange or underrange has occurred. The ADC result is clamped to ± full scale if an overrange or underrange occurs. This bit is updated when the ADC result is written and is cleared by removing the overrange or underrange condition on the analog inputs.

5 CRC_ERROR This bit indicates if a CRC error has occurred during a register write. For register reads, the host microcontroller determines if a CRC error has occurred. This bit is cleared by a read of this register.

4 REG_ERROR This bit indicates if the content of one of the internal registers has changed from the value calculated when the register integrity check was activated. The check is activated by setting the REG_CHECK bit in the interface mode register. This bit is cleared by clearing the REG_CHECK bit.

[3:0] CHANNEL These bits indicate which channel was active for the ADC conversion whose result is currently in the data register. This may be different from the channel currently being converted. The bits are a direct mapping from the Channel x registers; therefore, Channel 0 results in 0x0 and Channel 15 results in 0x1F.


0x1 R

0x0 R

0x0 R

0x0 R

0x0 R



ADC MODE REGISTER

Address: 0x01, Reset: 0x2000, Name: ADCMODE

The ADC mode register controls the operating mode of the ADC and the master clock selection. A write to the ADC mode register resets the filter and the RDY bits and starts a new conversion or calibration.

Table 25. Bit Descriptions for ADCMODE

Bits

15

Bit Name

REF_EN

Settings Description Reset

Enables internal reference and outputs a buffered 2.5 V to the REFOUT pin. 0x0

Access

RW

14 RESERVED

13 SING_CYC

This bit is reserved. Set to 0.

This bit can be used when only a single channel is active to set the ADC to output only at the settled filter data rate.

0x0 R

0x1 RW

[12:11] RESERVED

[10:8] DELAY

These bits are reserved. Set to 0.

These bits allow a programmable delay to be added after a channel switch to allow settling of external circuitry before the ADC starts processing its input.

0x0 R

0x0 RW

7 RESERVED

[6:4] MODE


These bits control the operating mode of the ADC. Details can be found in

the Operating Modes section.

000 Continuous conversion mode

001 Single conversion mode

0x0 R

0x0 RW

100 Internal offset calibration

110 System offset calibration

111 System gain calibration

[3:2] CLOCKSEL This bit is used to select the ADC clock source. Selecting the internal oscillator also enables the internal oscillator.

0x0 RW

[1:0] RESERVED

01 Internal oscillator output on XTAL2/CLKIO pin

10 External clock input on XTAL2/CLKIO pin

11 External crystal on XTAL1 and XTAL2/CLKIO pins

These bits are reserved. Set to 0. 0x0 R


AD7173-8

INTERFACE MODE REGISTER

Address: 0x02, Reset: 0x0000, Name: IFMODE

The interface mode register configures various serial interface options.

Data Sheet

Table 26. Bit Descriptions for IFMODE

Bits Bit Name

[15:13] RESERVED

Settings

12 ALT_SYNC

Description


This bit enables a different behavior of the SYNC pin to allow the use of

SYNC as a control for conversions when cycling channels. (For details, see

the description of the SYNC_EN bit in the GPIO Configuration Register.)

11 IOSTRENGTH This bit controls the drive strength of the DOUT (DOUT/RDY) pin and the

XTAL2/CLKIO pin. Set this bit to 1 when reading from the serial interface at high speed with low IOVDD supply and moderate capacitance.

10 HIDE_DELAY If a programmable delay is set using the DELAY bits in the ADC mode register, then this bit allows for the delay to be hidden by absorbing the

delay into the conversion time for selected data rates. See the Delay

section for more details.

9 RESERVED

8 DOUT_RESET


This bit prevents the DOUT/RDY pin from switching from outputting DOUT to outputting RDY soon after the last rising edge of SCLK during a read operation. Instead, the DOUT/RDY pin continues to output the LSB of the data until CS goes high, providing longer hold times for the SPI master to sample the LSB of the data. When this bit is set, CS must not be tied low.

7 CONTREAD This bit enables continuous read of the ADC data register. To use continuous read, configure the ADC in continuous conversion mode. For more details,

see the Operating Modes section.

6 DATA_STAT This bit enables the status register to be appended to the data register when read so that channel and status information is transmitted with the data. This is the only way to ensure that the channel bits read from the status register correspond to the data in the data register.

5 REG_CHECK This bit enables a register integrity checker that can be used to monitor any change in the value of the user registers. To use this feature, configure all other registers as desired, with this bit cleared. Then write to this register to set the REG_CHECK bit to 1. If the contents of any of the registers change, the REG_ERROR bit is set in the status register. To clear the error, set the

REG_CHECK bit to 0. Neither the interface mode register nor the ADC data or status register is included in the registers that are checked. If a register must have a new value written, clear this bit first; otherwise, an error is flagged when the new register contents are written.

4 RESERVED This bit is reserved. Set to 0.

Reset

0x0

Access

R

0x0 RW

0x0 RW

0x0 RW

0x0 R

0x0 RW

0x0 RW

0x0 RW

0x0 RW

0x0 R




[3:2] CRC_EN


Enables CRC protection of register reads/writes. CRC increases the number of

bytes in a serial interface transfer by one. See the CRC Calculation section

for more details.


0x00 RW

1 RESERVED

0 WL16 use CRC with these bits set.

10 CRC checksum enabled for read and write transactions.


Changes the ADC data register to 16 bits. The ADC is not reset by a write to the interface mode register; therefore, the ADC result is not rounded to the correct word length immediately after writing to these bits. The first new ADC result is correct.

0 data

1 data

0x0 R

0x0 RW

REGISTER CHECK

Address: 0x03, Reset: 0x000000, Name: REGCHECK

The register check register is a 24-bit checksum calculated by XOR'ing the contents of the user registers and some nonaccessible registers.

The REG_CHECK bit in the interface mode register must be set for this to operate; otherwise, the register reads 0.

Table 27. Bit Descriptions for REGCHECK


[23:0] REGISTER_CHECK

Description

This register contains the 24-bit checksum of user registers when the

REG_CHECK bit is set in the interface mode register.


0x000000 R

DATA REGISTER

Address: 0x04, Reset: 0x000000, Name: DATA

The data register contains the ADC conversion result. The encoding is offset binary; however, it can be changed to unipolar by the

BI_UNIPOLAR bit in the setup configuration register. Reading the data register brings the RDY bit and pin high if they are low. The

ADC result can be read multiple times; however, because RDY has been brought high, it is not possible to know if another ADC result is imminent. The ADC does not write a new result into the data register if the register is currently being read.

Table 28. Bit Descriptions for DATA


[23:0] DATA

Description

This register contains the ADC conversion result. If the DATA_STAT bit is set in the interface mode register, the status register is appended to this register when read, making this a 32-bit register. If WL16 is set in the interface mode register, this register is set to a length of 16 bits.


0x000000 R


AD7173-8

GPIO CONFIGURATION REGISTER

Address: 0x06, Reset: 0x0800, Name: GPIOCON

The GPIO configuration register controls the general-purpose I/O pins of the ADC.

Data Sheet

Table 29. Bit Descriptions for GPIOCON

Bits Bit Name Settings Description

15 RESERVED This bit is reserved. Set to 0.

14 PDSW

13 OP_EN2_3

12 MUX_IO

11 SYNC_EN

This bit enables/disables the power-down switch function. Setting the bit allows the pin to sink current. This function can be used for bridge sensor applications where the switch controls the power-up/power-down of the bridge.

This bit enables the GPO2 and GPO3 pins. Outputs are referenced between

AVDD1 and AVSS.

This bit allows the ADC to control an external multiplexer, using GPIO0/GPIO1/

GPO2/GPO3 in sync with the internal channel sequencing. The analog input pins used for a channel can still be selected on a per channel basis. Therefore, it is possible to have a 16-channel multiplexer in front of each analog input pair (AIN0/AIN1 to AIN14/AIN15), giving a total of 128 differential channels.

However, only 16 channels at a time can be automatically sequenced. Following the sequence of 16 channels, the user changes the analog input to the next pair of input channels, and it sequences through the next 16 channels.

There is a delay function that allows extra time for the analog input to settle, in conjunction with any switching an external multiplexer (see the delay bits in

the ADC Mode Register).

This bit enables the SYNC pin as a sync input. When set low, the SYNC pin holds the ADC and filter in reset until SYNC goes high. An alternative operation of the SYNC pin is available when the ALT_SYNC bit in the interface mode register is set. This mode works only when multiple channels are enabled.

In such cases, a low on the SYNC pin does not immediately reset the filter/ modulator. Instead, if the SYNC pin is low when the channel is due to be switched, the modulator and filter are prevented from starting a new conversion. Bringing SYNC high begins the next conversion. This alternative sync mode allows SYNC to be used while cycling through channels.

[10:9] ERR_EN These bits enable the ERROR pin as an error input/output. error sources and is available in the ADC_ERROR bit in the status register. The

ERROR pin state can also be read from the ERR_DAT bit in this register.

OR'ed, inverted, and mapped to the ERROR pin. ERROR pins of multiple devices can be wired together to a common pull-up resistor so that an error on any device can be observed.

8 ERR_DAT

7

6

GP_DATA3

GP_DATA2

5 IP_EN1 the ERR_DAT bit in this register. This is referenced between IOVDD and

DGND, as opposed to the AVDD1 and AVSS levels used by the generalpurpose I/O pins. It has an active pull-up in this case.

This bit determines the logic level at the ERROR pin if the pin is enabled as a general-purpose output. It reflects the readback status of the pin if the pin is enabled as an input.

This bit is the write data for GPO3.

This bit is the write data for GPO2.

This bit turns GPIO1 into an input. Input should equal AVDD1 or AVSS.

Reset

0x0

Access

R

0x0 RW

0x0 RW

0x0 RW

0x1 RW

0x0 RW

0x0 RW

0x0

0x0

W

W

0x0 RW


Data Sheet

Bits

4

Bit Name

IP_EN0


This bit turns GPIO0 into an input. Input should equal AVDD1 or AVSS.

AD7173-8

Reset

0x0

Access

RW

3

2

OP_EN1

OP_EN0

This bit turns GPIO1 into an output. Outputs are referenced between

AVDD1 and AVSS.

This bit turns GPIO0 into an output. Outputs are referenced between

AVDD1 and AVSS.

0x0 RW

0x0 RW

1

0

GP_DATA1

GP_DATA0

This bit is the readback or write data for GPIO1.

This bit is the readback or write data for GPIO0.

0x0

0x0

RW

RW

ID REGISTER

Address: 0x07, Reset: 0x30DX, Name: ID

The ID register returns a 16-bit ID. For the AD7173-8 , this is 0x30DX.

Table 30. Bit Descriptions for ID


[15:0] ID


The ID register returns a 16-bit ID code that is specific to the ADC.


0x30DX

1

R

1 X = don’t care.

CHANNEL REGISTER 0

Address: 0x10, Reset: 0x8001, Name: CH0

The channel registers are 16-bit registers that are used to select which channels are currently active, which inputs are selected for each channel, and which setup should be used to configure the ADC for that channel.

Table 31. Bit Descriptions for CH0


15 CH_EN0


This bit enables Channel 0. If more than one channel is enabled, the ADC automatically sequences between them.

Reset

0x1

Access

RW

[14:12] SETUP_SEL0

[11:10] RESERVED

These bits identify which of the eight setups are used to configure the

ADC for this channel.

A setup comprises a set of four registers: the setup configuration register, the filter configuration register, the offset register, and the gain register.

All channels can use the same setup, in which case the same 3-bit value is written to these bits on all active channels; alternatively, up to eight channels can be configured differently.

000 0

001 1

010 2

011 3

100 4

101 5

110 6

111 7


0x0

0x0


RW

R

AD7173-8


[9:5] AINPOS0

[4:0] AINNEG0

Data Sheet


These bits select which of the analog inputs is connected to the positive input of the ADC for this channel. TEMP SENSOR ± is an internal temperature sensor.


0x0 RW

10001

10010

+

−

These bits select which of the analog inputs is connected to the negative input of the ADC for this channel.

0x1 RW

10001

10010

+

−



CHANNEL REGISTER 1 TO CHANNEL REGISTER 15

Address Range: 0x11 to 0x1F, Reset: 0x0001, Name: CH1 to CH15

Subsequent channel registers, CH1 to CH15, use the same structure as the CH0 register. They are disabled by default (MSB = 0). Each channel created can be referred to one of eight setups. The sequencer progresses through each of the enabled channels in order.

Table 32 shows the summary of these registers, their addresses, and their reset values.

0x12 CH2

0x13 CH3

0x14 CH4

0x15 CH5

0x16 CH6

0x17 CH7

0x18 CH8

0x19 CH9

0x1A CH10

0x1B CH11

0x1C CH12

0x1D CH13

0x1E CH14

0x1F CH15

Table 32. Summary of CH1 to CH15

Reg Name

0x11 CH1

Bits Bit 7

[15:8] CH_EN1

[7:0]

Bit 6 Bit 5

AINPOS1[2:0]

[15:8] CH_EN2

[7:0]

[15:8] CH_EN3

[7:0]

[15:8] CH_EN4

[7:0]

[15:8] CH_EN5

[7:0]

[15:8] CH_EN6

[7:0]

[15:8] CH_EN7

[7:0]

AINPOS2[2:0]

AINPOS3[2:0]

AINPOS4[2:0]

AINPOS5[2:0]

AINPOS6[2:0]

AINPOS7[2:0]

[15:8] CH_EN8

[7:0]

[15:8] CH_EN9

[7:0]

[15:8] CH_EN10

[7:0]

AINPOS8[2:0]

AINPOS9[2:0]

AINPOS10[2:0]

[15:8] CH_EN11

[7:0]

[15:8] CH_EN12

AINPOS11[2:0]

[7:0]

[15:8] CH_EN13

[7:0]

[15:8] CH_EN14

AINPOS12[2:0]

AINPOS13[2:0]

[7:0]

[15:8] CH_EN15

[7:0]

AINPOS14[2:0]

AINPOS15[2:0]

Bit 4 Bit 3 Bit 2 Bit 1

AINNEG1

AINNEG2

AINNEG3

AINNEG4

AINNEG5

AINNEG6

AINNEG7

AINNEG8

AINNEG9

AINNEG10

AINNEG11

AINNEG12

AINNEG13

AINNEG14

AINNEG15

Bit 0 Reset RW



SETUP CONFIGURATION REGISTER 0

Address: 0x20, Reset: 0x1000, Name: SETUPCON0

The setup configuration registers are 16-bit registers that configure the reference selection, input buffers, burnout currents, and output coding of the ADC.

Table 33. Bit Descriptions for SETUPCON0


[15:13] RESERVED



12 BI_UNIPOLAR0

[11:10] REF_BUF_0[1:0]

[9:8] AIN_BUF_0[1:0]

7 BURNOUT_EN0

6 BUFCHOPMAX0

This bit sets the output coding of the ADC for Setup 0.

0 Unipolar coded output

1 Offset binary coded output

Reference input buffer enable. These bits turn on the buffers of the positive and negative reference inputs. This offers a high impedance input for an external reference source and isolates it from the switch capacitor reference sampling input of the ADC. Use both reference buffers together.

00 Reference input buffers disabled

11 Reference input buffers enabled

Analog input buffer enable. These bits turn on the buffers of the positive and negative analog inputs. This offers a high impedance input to the device and isolates the sensor/signal for measurement from the switch capacitor sampling input of the ADC. Use both analog input buffers together.

00 Analog input buffers disabled

11 Analog input buffers enabled

This bit enables a 10 μA current source on the positive analog input selected and a 10 μA current sink on the negative analog input selected.

The burnout currents are useful in diagnosis of an open wire, whereby the

ADC result goes to full scale. Enabling the BURNOUT currents during measurement results in an offset voltage on the ADC reading of approximately 1 μV. This means the strategy for diagnosing an open wire operates best by turning on the BURNOUT currents at intervals, before or after precision measurements.

This bit enables the maximum buffer chop frequency, increasing AIN input current and reducing buffer noise.

[5:4] REF_SEL0

These bits allow selection of the reference source for ADC conversion on

Setup 0.

00 External reference supplied to REF+ and REF− pins

01 External Reference 2 supplied to AIN1/REF2+ and AIN0/REF2− pins

Reset

0x0

0x1

Access

R

RW

0x0 RW

0x0 RW

0x0 RW

0x0 RW

0x0 RW register

RESERVED reference values

These bits are reserved. Set to 0. 0x0 R [3:0]



SETUP CONFIGURATION REGISTER 1 TO SETUP CONFIGURATION REGISTER 7

Address: 0x21 to 0x27, Reset: 0x1000, Name: SETUPCON1 to SETUPCON7

The remaining seven setup configuration registers share the same 16-bit register layout as SETUPCON0. They configure the reference selection, input buffers, burnout currents, and output coding of the ADC.

Table 34. Summary of SETUPCON1 to SETUPCON7

Reg Name Bits Bit 7


Bit 6

RESERVED

RESERVED 0x22 SETUPCON2 [15:8]






RESERVED

RESERVED

RESERVED

RESERVED

RESERVED

Bit 5 Bit 4

BI_UNIPOLAR1

BI_UNIPOLAR2

BI_UNIPOLAR3

BI_UNIPOLAR4

BI_UNIPOLAR5

BI_UNIPOLAR6

BI_UNIPOLAR7

Bit 3 Bit 2

REF_BUF 1[1:0]

Bit 1 Bit 0

AIN_BUF 1[1:0]

Reset

0x1000

RW

RW

RESERVED

REF_BUF 2[1:0] AIN_BUF 2[1:0] 0x1000 RW

RESERVED


RESERVED


RESERVED


RESERVED


RESERVED


RESERVED


[4:0] ODR0


FILTER CONFIGURATION REGISTER 0

Address: 0x28, Reset: 0x0000, Name: FILTCON0

The filter configuration registers are 16-bit registers that configure the ADC data rate and filter options. Writing to any of these registers resets any active ADC conversion and restarts converting at the first channel in the sequence.

Table 35. Bit Descriptions for FILTCON0


15 SINC3_MAP0

Description

If this bit is set, the mapping of the filter configuration register changes to directly program the decimation rate of the sinc3 filter for Setup 0. All other options are eliminated. This allows fine tuning of the output data rate and filter notch for rejection of specific frequencies. The data rate when on a single channel, with single cycle settling disabled, equals

FMOD/(32 × FILTCON0[14:0]).

[14:12] RESERVED

11 ENHFILTEN0


This bit enables various post filters for enhanced 50 Hz/60 Hz rejection for

Setup 0. For this setting to function, the ORDERx bits must also be set to

00 to select the sinc5 + sinc1 filter.

[10:8] ENHFILT0

7 RESERVED

[6:5] ORDER0

These bits select between various post filters for enhanced 50 Hz/60 Hz rejection for Setup 0.

010 27.27 SPS, 47 dB rejection, 36.67 ms settling

011 25 SPS, 62 dB rejection, 40 ms settling

101 20 SPS, 86 dB rejection, 50 ms settling

110 16.67 SPS, 92 dB rejection, 60 ms settling


These bits control the order of the digital filter that processes the modulator data for Setup 0.

00 Sinc5 + sinc1 (default)


0x0 RW

0x0 R

0x0 RW

0x0 RW

0x0 R

0x0 RW use the same output data rate for all enabled channels.

These bits control the output data rate of the ADC and, therefore, the settling time and noise for Setup 0.

01001 2597 SPS (2604 SPS for sinc3)

01010 1007 SPS (1008 SPS for sinc3)

01011 503.8 SPS (504 SPS for sinc3)

01100 381 SPS (400.6 SPS for sinc3)

01111 59.52 SPS (59.98 SPS for sinc3)

10000 49.68 SPS (50 SPS for sinc3)

10010 16.63 SPS (16.67 SPS for sinc3)

0x0 RW



FILTER CONFIGURATION REGISTER 1 TO FILTER CONFIGURATION REGISTER 7

Address Range: 0x29 to 0x2F, Reset: 0x0000, Name: FILTCON1 to FILTCON7

The remaining seven filter configuration registers share the same 16-bit register layout as FILTCON0. They configure the ADC data rate and filter options and map as per their number. Writing to any of these registers resets any active ADC conversion and restarts converting at the first channel in the sequence.

Table 36. Summary of FILTCON1 to FILTCON7

Reg Name Bits Bit 7 Bit 6 Bit 5


0x2A FILTCON2 [15:8] SINC3_MAP2

0x2B FILTCON3 [15:8] SINC3_MAP3

0x2C FILTCON4 [15:8] SINC3_MAP4

0x2D FILTCON5 [15:8] SINC3_MAP5

0x2E FILTCON6 [15:8] SINC3_MAP6

0x2F FILTCON7 [15:8] SINC3_MAP7

ORDER1

ORDER2

ORDER3

ORDER4

ORDER5

ORDER6

ORDER7

Bit 4 Bit 3 Bit 2 Bit 1

ODR1

ODR2

ODR3

ODR4

ODR5

ODR6

ODR7

Bit 0 Reset RW



OFFSET REGISTER 0

Address: 0x30, Reset: 0x800000, Name: OFFSET0

The offset (zero-scale) registers are 24-bit registers that can be used to compensate for any offset error in the ADC or in the system.

Table 37. Bit Descriptions for OFFSET0


[23:0] OFFSET0


Offset calibration coefficient for Setup 0.


0x800000 RW

OFFSET REGISTER 1 TO OFFSET REGISTER 7

Address Range: 0x31to 0x37, Reset: 0x800000, Name: OFFSET1 to OFFSET7

The offset (zero-scale) registers, OFFSET1 to OFFSET7, share the same structure (24-bit) as OFFSET0. They can be used individually to compensate for any offset error in the ADC or in the system.

Table 38. Summary of OFFSET1 to OFFSET7

Bit[23:0]

OFFSET1[23:0]

OFFSET2[23:0]

OFFSET3[23:0]

OFFSET4[23:0]

OFFSET5[23:0]

OFFSET6[23:0]

OFFSET7[23:0]

Reset RW

GAIN REGISTER 0

Address: 0x38, Reset: 0x5XXXX0, Name: GAIN0

The gain (full-scale) registers are 24-bit registers that can be used to compensate for any gain error in the ADC or in the system.

Table 39. Bit Descriptions for GAIN0


[23:0] GAIN0


1 The value of X varies, depending on the IC that is used.

GAIN REGISTER 1 TO GAIN REGISTER 7

Reset 1

Access

0x5XXXX0 RW

Address Range: 0x39 to 0x3F, Reset: 0x5XXXX0, Name: GAIN1 to GAIN7

The gain (full-scale) registers for GAIN1 to GAIN7 share the same 24-bit structure as that shown by GAIN0 register. They can be used to compensate for any gain error in the ADC or in the system and are assigned as per their number to a given setup.

Table 40. Summary of GAIN1 to GAIN7

Reg Name Bits

0x39 GAIN1 [23:0]

0x3A GAIN2 [23:0]

0x3B GAIN3 [23:0]

0x3C GAIN4 [23:0]

0x3D GAIN5 [23:0]

0x3E GAIN6 [23:0]

0x3F GAIN7 [23:0]

1

The value of X varies, depending on the IC that is used.

Bit[23:0]

GAIN1[23:0]

GAIN2[23:0]

GAIN3[[23:0]

GAIN4[23:0]

GAIN5[23:0]

GAIN6[23:0]

GAIN7[23:0]

Reset

1

RW


Data Sheet

OUTLINE DIMENSIONS

PIN 1

INDICATOR

6.10

6.00 SQ

5.90

0.30

0.25

0.18

31

30

40

1

PIN 1

INDICATOR

0.50

BSC

EXPOSED

PAD

4.05

3.90 SQ

3.75

0.80

0.75

0.70

TOP VIEW

0.45

0.40

0.35

0.05 MAX

0.02 NOM

COPLANARITY

0.08

0.20 REF

20

21

BOTTOM VIEW

10

11

0.25 MIN

FOR PROPER CONNECTION OF

THE EXPOSED PAD, REFER TO

THE PIN CONFIGURATION AND

FUNCTION DESCRIPTIONS

SECTION OF THIS DATA SHEET.

SEATING

PLANE

COMPLIANT TO JEDEC STANDARDS MO-220-WJJD.

Figure 75. 40-Lead Lead Frame Chip Scale Package [LFCSP_WQ]

6 mm × 6 mm Body, Very Very Thin Quad

(CP-40-14)

Dimensions shown in millimeters

ORDERING GUIDE

Models

1

AD7173-8BCPZ

AD7173-8BCPZ-RL

Temperature Range

−40°C to +105°C

−40°C to +105°C

EVAL-AD7173-8SDZ

EVAL-SDP-CB1Z

1

Z = RoHS Compliant Part.

Package Description

40-Lead LFCSP_WQ

40-Lead LFCSP_WQ

Package Option

CP-40-14

CP-40-14

Evaluation

Evaluation Controller Board

AD7173-8


AD7173-8

NOTES

Data Sheet

©2013–2014 Analog Devices, Inc. All rights reserved. Trademarks and

registered trademarks are the property of their respective owners.

D11773-0-4/14(A)


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