EVAL-AD7124-8SDZ User Guide UG-856

EVAL-AD7124-8SDZ User Guide UG-856
EVAL-AD7124-8SDZ User Guide
UG-856
One Technology Way • P.O. Box 9106 • Norwood, MA 02062-9106, U.S.A. • Tel: 781.329.4700 • Fax: 781.461.3113 • www.analog.com
Evaluation Board for the AD7124-8 8-Channel, Low Noise, Low Power,
24-bit Σ-Δ ADC with In-Amp and Reference
FEATURES
GENERAL DESCRIPTION
Full featured evaluation board for the AD7124-8
PC control in conjunction with Analog Devices, Inc. System
Demonstration Platform (EVAL-SDP-CB1Z)
PC software for control and data analysis (time domain)
Standalone capability
The EVAL-AD7124-8SDZ evaluation kit features the AD7124-8
24-bit, low power, low noise analog-to-digital converter (ADC).
EVALUATION KIT CONTENTS
EVAL-AD7124-8SDZ evaluation board
Evaluation software CD for the AD7124-8
ONLINE RESOURCES
Documents Needed
AD7124-8 data sheet
EVAL-AD7124-8SDZ user guide
Required Software
AD7124-8 EVAL+ Software
EQUIPMENT NEEDED
EVAL-AD7124-8SDZ evaluation board
EVAL-SDP-CB1Z System Demonstration Platform
DC signal source
USB cable
PC running Windows with USB 2.0 port
PLEASE SEE THE LAST PAGE FOR AN IMPORTANT
WARNING AND LEGAL TERMS AND CONDITIONS.
A 7 V to 9 V external supply is regulated to 3.3 V to supply the
AD7124-8 and support all necessary components. The EVALAD7124-8SDZ board connects to the USB port of the PC by
connecting to the EVAL-SDP-CB1Z motherboard.
The AD7124-8 EVAL+ Software fully configures the AD7124-8
device register functionality and provides dc time domain
analysis in the form of waveform graphs, histograms, and
associated noise analysis for ADC performance evaluation.
The EVAL-AD7124-8SDZ is an evaluation board that allows the
user to evaluate the features of the ADC. The user PC software
executable controls the AD7124-8 over the USB through the
EVAL-SDP-CB1Z System Demonstration Platform (SDP) board.
Full specifications on the AD7124-8 are available in the product
data sheet, which should be consulted in conjunction with this
user guide when working with the evaluation board.
Rev. 0 | Page 1 of 30
7V TO 9V
VIN
AVDD
1.9V
LDO
AIN0/IOUT/VBIAS
AIN1/IOUT/VBIAS
AIN2/IOUT/VBIAS/P1
AIN3/IOUT/VBIAS/P2
AIN4/IOUT/VBIAS/P3
AIN5/IOUT/VBIAS/P4
AIN6/IOUT/VBIAS
AIN7/IOUT/VBIAS
AIN8/IOUT/VBIAS
AIN9/IOUT/VBIAS
AIN10/IOUT/VBIAS
AIN11/IOUT/VBIAS
AIN12/IOUT/VBIAS
AIN13/IOUT/VBIAS
AIN14/IOUT/VBIAS/REFIN2(+)
AIN15/IOUT/VBIAS/REFIN2(–)
NC
OUT
GND
NC
EN
GND
GND
NC
NC
REFOUT
VBIAS
57.6kΩ
VOUT
REGCAPA
BANDGAP
REF
1.8V OUTPUT
GND
OUT
GND
EN
GND
REFIN2(+)
REFIN2(–)
AVSS
AVDD
GND
IN
REFIN1(–) IOVDD
REFIN1(+)
AVDD
AVSS
CROSSPOINT
MUX
REGCAPD
1.8V
LDO
REFERENCE
BUFFERS
SDP-B
DOUT/RDY
BUF
BURNOUT
DETECT
PGA1
24-BIT
Σ-Δ ADC
PGA2
BUF
VARIABLE
DIGITAL
FILTER
SERIAL
INTERFACE
AND
CONTROL
LOGIC
X-MUX
ANALOG
BUFFERS
AVSS
GPOs
DIN
SCLK
CS
SYNC
CHANNEL
SEQUENCER
ADSP-BF527
POWER
LED
USB
STATUS
DIAGNOSTICS
TEMPERATURE
SENSOR
COMMUNICATIONS
POWER SUPPLY
SIGNAL CHAIN
DIGITAL
AVDD
DIAGNOSTICS
POWER
SWITCH
CLK
AD7124-8
AVSS
AVSS
NOTES
1. FOR SIMPLICITY, DECOUPLING NOT SHOWN.
INTERNAL
CLOCK
EXCITATION
CURRENTS
DGND
13305-001
PSW
2.5V OUTPUT
IN
ADJ
TP
ADR4525
LED
ON-BOARD
NOISE TEST
AIN0 TO AIN1
ADP1720ARMZ-R7
27kΩ
GND ADP1720 GND
3.3V OUTPUT
IN
GND
13305-002
EVAL-AD7124-8SDZ User Guide
UG-856
EVALUATION BOARD HARDWARE
DEVICE DESCRIPTION
The AD7124-8 is a low power, low noise, complete analog front
end for high precision measurement applications. It contains a
low noise, 24-bit Σ-Δ ADC. It can be configured to have eight
differential inputs or 15 single-ended or pseudo-differential
inputs. The on-chip low noise instrumentation amplifier means
that signals of small amplitude can interface directly to the
ADC. Other on-chip features include a low drift 2.5 V reference,
excitation currents, reference buffers, multiple filter options,
and many diagnostic features.
Complete specifications for the AD7124-8 are provided in the
product data sheet and must be consulted in conjunction with
this user guide when using the evaluation board. Full details
about the EVAL-SDP-CB1Z are available at analog.com.
HARDWARE LINK OPTIONS
The default link options are listed in Table 1. By default, the
board operates from a wall wart (dc plug) power supply via
Connector J5. The supply required for the AD7124-8 comes
from the on-board ADP1720 low dropout regulators (LDOs),
which generate their voltage from Connector J5.
Table 1. Default Link and Solder Link Options
Link No.
LK1
Default
Option
A
LK2
B
LK3
LK4
Inserted
2.5 V
LK5
Inserted
LK6
Inserted
SL2
A
SL3, SL7
A, A
SL5
B
AVSS to
AGND
Description
Connects the AVDD voltage to the power supply sequencer, ADM1185.
When AVDD equals 3.3 V, LK1 must be in Position A.
When AVDD equals 1.8 V, LK1 must be in Position B.
Selects the connector for the external 7 V to 9 V power supply.
In Position A, this link selects the external 7 V to 9 V power supply to come from Connector J3.
In Position B, this link selects the external 7 V to 9 V power supply to come from Connector J5.
Inserting this link connects REFIN(−) to AVSS.
Selects the reference source for the ADC.
In position 2.5 V, REFIN1(+) is connected to the external 2.5 V reference (ADR4525).
In position INT REF, REFIN1(+) is connected to the REFOUT pin of the AD7124-8. This allows the internal
reference of the AD7124-8 to connect as an external reference.
This link shorts AIN0 to AIN1. This is useful to perform noise tests on the AD7124-8. It is possible to enable the
internal bias on AIN0 or AIN1 so that AIN0 and AIN1 are at an appropriate voltage for the noise test.
LK6 can be used to connect the AIN4 and AIN5 channels to external components such as an external amplifier.
Jumpers in position A and B at LK6 must be opened to include the external component on the front end.
Jumper A and Jumper B of this link can be used to connect the AIN4 and AIN5 channels to external components
such as an external amplifier. For this, the jumpers must be open.
When Jumper A and Jumper B are in place, connect AIN4 and AIN5 to the on-board thermistor used for cold
junction measurements.
Sets the voltage applied to the AVDD pin.
In Position A, this link sets the voltage applied to the AVDD pin to be a 3.3 V supply from the ADP1720-3.3 (U7)
regulator or a 1.8 V supply from the ADP1720 (U4) regulator.
In Position B, this link supplies the voltage to the AVDD pin from an external voltage source via Connector J9.
With SL3 and SL7 in Position A, the ADP1720-3.3 (U7) regulator supplies AVDD with 3.3 V.
With SL3 and SL7 in Position B, the ADP1720 (U4) regulator supplies AVDD with 1.8 V.
With this link in Position A, the IOVDD supply is provided from an external source via Connector J9.
With this link in Position B, the 3.3 V supply is generated by the ADP1720-3.3 (U10) regulator.
The evaluation system operates with 3.3 V logic.
Inserting these links ties AVSS to AGND. When setting AVSS to −1.8 V, remove these links.
Rev. 0 | Page 5 of 30


13305-004
13305-003
13305-007
13305-005
13305-006


13305-011
13305-009
13305-010
13305-008
13305-014
13305-015
13305-013
13305-012
13305-018
13305-017




13305-016
13305-019
EVAL-AD7124-8SDZ User Guide
UG-856
Selecting External Reference
Configuration Pop-Up Button
There are two options to select the external reference on the
AD7124-8 EVAL+ Software: AVdd and Refin1(+/−) (Label 3).
The Refin1(+/−) field sets the external reference voltage that is
connected between REFIN1+ and REFIN1−. The AVdd field
sets the AVDD voltage level for the AD7124-8. Using EVALAD7124-8SDZ evaluation board, the AVDD voltage is 3.3 V.
Either of these voltage levels can be used to calculate the results
on the Waveform and Histogram tabs. The evaluation board
has an external 2.5 V ADR4525 reference; this reference
selection can be bypassed on the evaluation board. If bypassing
the ADR4525 on board, change the external reference voltage
value in Refin1(+/−) to ensure correct calculation of results in the
Waveform and Histogram tabs.
Each configuration pop-up button (Label 6) opens a different
window to configure the relevant functional block.
Tutorial Button
Click the TUTORIAL button (Label 4) to open a tutorial on using
the software and additional information on using the AD7124-8
EVAL+ Software.
Functional Block Diagram
The functional block diagram of the ADC (Label 5) shows each
of the functional blocks within the ADC. Clicking a
configuration button on this graph opens the configuration
pop-up window for that block.
Config Summary
Clicking the CONFIG SUMMARY button (Label 7) displays the
channel configuration information on each of the individual setups
as well as information on any error present. These tabs can be used
to quickly check how the ADC channels are configured, as well as
any errors that are present.
Demo Modes
The AD7124-8 EVAL+ Software supports a number of demo
modes (Label 8); these demo modes configure the AD7124-8
for each of the modes shown. A help file is available for each demo
mode; to access this help file, click the question mark button.
Status Bar
The status bar (Label 9) displays status updates such as Analysis
Completed, Reset Completed, and Configuring Demo Mode
during software use, as well as the software version and the
Busy indicator.
1
2
3
3
4
7
5
6
8
13305-020
9
Figure 20. Configuration Tab of the AD7124-8 EVAL+ Software
Rev. 0 | Page 13 of 30
4
5
6
7
1
3
2
10
8
13305-021
9
3
13305-022
1
6
2
4
5
13305-023
1
3
4
5
2
13305-024
13305-025
13305-026
13305-027
13305-028
13305-029
13305-031
13305-030
13305-033
13305-032
13305-034
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