Integrated Synthesizer and VCO ADF4360-7 Data Sheet FEATURES

Integrated Synthesizer and VCO ADF4360-7 Data Sheet FEATURES
Integrated Synthesizer and VCO
ADF4360-7
Data Sheet
FEATURES
GENERAL DESCRIPTION
Output frequency range: 350 MHz to 1800 MHz
Divide-by-2 output
3.0 V to 3.6 V power supply
1.8 V logic compatibility
Integer-N synthesizer
Programmable dual-modulus prescaler 8/9, 16/17
Programmable output power level
3-wire serial interface
Analog and digital lock detect
Hardware and software power-down mode
The ADF4360-7 is an integrated integer-N synthesizer and
voltage controlled oscillator (VCO). The ADF4360-7 center
frequency is set by external inductors. This allows a frequency
range of between 350 MHz to 1800 MHz. In addition, a divideby-2 option is available, whereby the user receives an RF output
of between 175 MHz and 900 MHz.
Control of all the on-chip registers is through a simple 3-wire
interface. The device operates with a power supply ranging from
3.0 V to 3.6 V and can be powered down when not in use.
APPLICATIONS
Wireless handsets (DECT, GSM, PCS, DCS, WCDMA)
Test equipment
Wireless LANs
CATV equipment
FUNCTIONAL BLOCK DIAGRAM
AVDD
RSET
DVDD
CE
ADF4360-7
MUXOUT
MULTIPLEXER
14-BIT R
COUNTER
REFIN
LOCK
DETECT
CLK
DATA
MUTE
24-BIT
FUNCTION
LATCH
24-BIT
DATA REGISTER
LE
CHARGE
PUMP
CP
PHASE
COMPARATOR
VVCO
VTUNE
L1
L2
CC
CN
INTEGER
REGISTER
RFOUTA
VCO
CORE
13-BIT B
COUNTER
5-BIT A
COUNTER
MULTIPLEXER
N = (BP + A)
RFOUTB
LOAD
LOAD
AGND
DGND
DIVSEL = 1
DIVSEL = 2
÷2
04441-001
PRESCALER
P/P+1
OUTPUT
STAGE
CPGND
Figure 1.
Rev. E
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ADF4360-7
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
MUXOUT and Lock Detect...................................................... 11
Applications ....................................................................................... 1
Input Shift Register .................................................................... 11
General Description ......................................................................... 1
VCO ............................................................................................. 11
Functional Block Diagram .............................................................. 1
Output Stage................................................................................ 12
Revision History ............................................................................... 2
Latch Structure ........................................................................... 13
Specifications..................................................................................... 3
Power-Up ..................................................................................... 17
Timing Characteristics..................................................................... 5
Control Latch .............................................................................. 19
Absolute Maximum Ratings............................................................ 6
N Counter Latch ......................................................................... 20
Transistor Count ........................................................................... 6
R Counter Latch ......................................................................... 20
ESD Caution .................................................................................. 6
Applications Information .............................................................. 21
Pin Configuration and Function Descriptions ............................. 7
Frequency Generator ................................................................. 21
Typical Performance Characteristics ............................................. 8
Choosing the Correct Inductance Value ................................. 22
Circuit Description ......................................................................... 10
Fixed Frequency LO ................................................................... 22
Reference Input Section ............................................................. 10
Interfacing ................................................................................... 23
Prescaler (P/P + 1)...................................................................... 10
PCB Design Guidelines for Chip Scale Package........................... 23
A and B Counters ....................................................................... 10
Output Matching ........................................................................ 24
R Counter .................................................................................... 10
Outline Dimensions ....................................................................... 25
PFD and Charge Pump .............................................................. 10
Ordering Guide .......................................................................... 25
REVISION HISTORY
4/16—Rev. D to Rev. E
Changed ADF4360 Family to ADF4360-7, ADSP-21xx
to ADSP-2181, and EV-ADF4360-xEB1 to
EV-ADF4360-7EB1Z..................................................... Throughout
Changes to Figure 3 .......................................................................... 7
Updated Outline Dimensions ....................................................... 25
Changes to Ordering Guide .......................................................... 25
3/13—Rev. C to Rev. D
Changes to Prescaler (P/P + 1) Section ....................................... 10
11/12—Rev. B to Rev. C
Changes to Table 3 ............................................................................ 6
Updated Outline Dimensions ....................................................... 25
2/12—Rev. A to Rev. B
Changes to Figure 3 and Table 4 ......................................................8
Changes to Output Matching Section ......................................... 24
Updated Outline Dimensions ....................................................... 25
Changes to Ordering Guide .......................................................... 25
11/04—Rev. 0 to Rev. A
Updated Format .................................................................. Universal
Changes to General Description .....................................................1
Changes to Specifications .................................................................3
Changes to the Reference Input Section...................................... 10
Changes to Power-Up Section ...................................................... 17
Added Table 10 ............................................................................... 17
Added Figure 22 ............................................................................. 17
Updated Outline Dimensions ....................................................... 25
2/04—Revision 0: Initial Version
Rev. E | Page 2 of 28
Data Sheet
ADF4360-7
SPECIFICATIONS 1
AVDD = DVDD = VVCO = 3.3 V ± 10%; AGND = DGND = 0 V; TA = TMIN to TMAX, unless otherwise noted.
Table 1.
Parameter
REFIN CHARACTERISTICS
REFIN Input Frequency
REFIN Input Sensitivity
REFIN Input Capacitance
REFIN Input Current
PHASE DETECTOR
Phase Detector Frequency 2
CHARGE PUMP
ICP Sink/Source 3
High Value
Low Value
RSET Range
ICP Three-State Leakage Current
Sink and Source Current Matching
ICP vs. VCP
ICP vs. Temperature
LOGIC INPUTS
VINH, Input High Voltage
VINL, Input Low Voltage
IINH/IINL, Input Current
CIN, Input Capacitance
LOGIC OUTPUTS
VOH, Output High Voltage
IOH, Output High Current
VOL, Output Low Voltage
POWER SUPPLIES
AVDD
DVDD
VVCO
AIDD 4
DIDD4
IVCO4, 5
IRFOUT4
Low Power Sleep Mode
B Version
Unit
Test Conditions/Comments
10/250
MHz min/max
0.7/AVDD
0 to AVDD
5.0
±60
V p-p min/max
V max
pF max
µA max
For f < 10 MHz, use a dc-coupled CMOS-compatible
square wave, slew rate > 21 V/µs.
AC-coupled.
CMOS compatible.
8
MHz max
2.5
0.312
2.7/10
0.2
2
1.5
2
mA typ
mA typ
kΩ
nA typ
% typ
% typ
% typ
1.5
0.6
±1
3.0
V min
V max
µA max
pF max
DVDD – 0.4
500
0.4
V min
µA max
V max
3.0/3.6
AVDD
AVDD
10
2.5
14.0
3.5 to 11.0
7
V min/V max
With RSET = 4.7 kΩ.
mA typ
mA typ
mA typ
mA typ
µA typ
1.25 V ≤ VCP ≤ 2.5 V.
1.25 V ≤ VCP ≤ 2.5 V.
VCP = 2.0 V.
CMOS output chosen.
IOL = 500 µA.
ICORE = 5 mA.
RF output stage is programmable.
Rev. E | Page 3 of 28
ADF4360-7
Parameter
RF OUTPUT CHARACTERISTICS5
Maximum VCO Output Frequency
Data Sheet
B Version
Unit
Test Conditions/Comments
1800
MHz
ICORE = 5 mA. Depending on L. See the Choosing the Correct
Inductance Value section.
Minimum VCO Output Frequency
VCO Output Frequency
350
490/585
MHz
MHz min/max
VCO Frequency Range
VCO Sensitivity
1.2
12
Ratio
MHz/V typ
400
6
15
−19
−9
−14/−5
±3
1.25/2.5
µs typ
MHz/V typ
kHz typ
dBc typ
dBc typ
dBm typ
dB typ
V min/max
−116
−138
−144
−148
−172
−163
−147
−92
0.3
−70
dBc/Hz typ
dBc/Hz typ
dBc/Hz typ
dBc/Hz typ
dBc/Hz typ
dBc/Hz typ
dBc/Hz typ
dBc/Hz typ
Degrees typ
dBc typ
−44
dBm typ
Lock Time 6
Frequency Pushing (Open Loop)
Frequency Pulling (Open Loop)
Harmonic Content (Second)
Harmonic Content (Third)
Output Power5, 7
Output Power Variation
VCO Tuning Range
NOISE CHARACTERISTIC5
VCO Phase-Noise Performance 8
Synthesizer Phase-Noise Floor 9
In-Band Phase Noise 10, 11
RMS Integrated Phase Error 12
Spurious Signals due to PFD Frequency11, 13
Level of Unlocked Signal with
MTLD Enabled
L1, L2 = 13 nH. See the Choosing the Correct Inductance Value
section for other frequency values.
FMAX/FMIN
L1, L2 = 13 nH. See the Choosing the Correct Inductance Value
section for other sensitivity values.
To within 10 Hz of final frequency.
Into 2.00 VSWR load.
Programmable in 3 dB steps. See Table 7.
For tuned loads, see Output Matching section.
At 100 kHz offset from carrier.
At 1 MHz offset from carrier.
At 3 MHz offset from carrier.
At 10 MHz offset from carrier.
At 25 kHz PFD frequency.
At 200 kHz PFD frequency.
At 8 MHz PFD frequency.
At 1 kHz offset from carrier.
100 Hz to 100 kHz.
Operating temperature range is –40°C to +85°C.
Guaranteed by design. Sample tested to ensure compliance.
ICP is internally modified to maintain constant loop gain over the frequency range.
4
TA = 25°C; AVDD = DVDD = VVCO = 3.3 V; P = 32.
5
Unless otherwise stated, these characteristics are guaranteed for VCO core power = 5 mA. L1, L2 = 13 nH, 470 Ω resistors to GND in parallel with L1, L2.
6
Jumping from 490 MHz to 585 MHz. PFD frequency = 200 kHz; loop bandwidth = 10 kHz.
7
Using 50 Ω resistors to VVCO, into a 50 Ω load. For tuned loads, see the Output Matching section.
8
The noise of the VCO is measured in open-loop conditions.
9
The synthesizer phase-noise floor is estimated by measuring the in-band phase noise at the output of the VCO and subtracting 20 log N (where N is the N divider value).
10
The phase noise is measured with the EV-ADF4360-7EB1Z Evaluation Board and the HP 8562E Spectrum Analyzer. The Spectrum Analyzer provides the REFIN for the
synthesizer; offset frequency = 1 kHz.
11
fREFIN = 10 MHz; fPFD = 200 kHz; N = 2500; loop B/W = 10 kHz.
12
fREFIN = 10 MHz; fPFD = 1 MHz; N = 500; loop B/W = 25 kHz.
13
The spurious signals are measured with the EV-ADF4360-7EB1Z Evaluation Board and the HP 8562E Spectrum Analyzer. The Spectrum Analyzer provides the REFIN for
the synthesizer; fREFOUT = 10 MHz at 0 dBm.
1
2
3
Rev. E | Page 4 of 28
Data Sheet
ADF4360-7
TIMING CHARACTERISTICS1
AVDD = DVDD = VVCO = 3.3 V ± 10%; AGND = DGND = 0 V; 1.8 V and 3 V logic levels used; TA = TMIN to TMAX, unless otherwise noted.
Table 2.
Parameter
t1
t2
t3
t4
t5
t6
t7
Unit
ns min
ns min
ns min
ns min
ns min
ns min
ns min
Test Conditions/Comments
LE Setup Time
DATA to CLOCK Setup Time
DATA to CLOCK Hold Time
CLOCK High Duration
CLOCK Low Duration
CLOCK to LE Setup Time
LE Pulse Width
Refer to the Power-Up section for the recommended power-up procedure for this device.
t4
t5
CLOCK
t2
DATA
DB23 (MSB)
t3
DB22
DB2
DB1
(CONTROL BIT C2)
DB0 (LSB)
(CONTROL BIT C1)
t7
LE
t1
t6
04441-002
1
Limit at TMIN to TMAX (B Version)
20
10
10
25
25
10
20
LE
Figure 2. Timing Diagram
Rev. E | Page 5 of 28
ADF4360-7
Data Sheet
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 3.
Parameter
AVDD to GND 1
AVDD to DVDD
VVCO to GND
VVCO to AVDD
Digital I/O Voltage to GND
Analog I/O Voltage to GND
REFIN to GND
Operating Temperature
Maximum Junction Temperature
CSP θJA Thermal Impedance
Paddle Soldered
Paddle Not Soldered
Peak Soldering Reflow Temperature
1
Rating
−0.3 V to +3.9 V
−0.3 V to +0.3 V
−0.3 V to +3.9 V
−0.3 V to +0.3 V
−0.3 V to VDD + 0.3 V
−0.3 V to VDD + 0.3 V
−0.3 V to VDD + 0.3 V
150°C
50°C/W
88°C/W
260°C
Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
This device is a high performance RF integrated circuit with an
ESD rating of <1 kV, and it is ESD sensitive. Proper precautions
should be taken for handling and assembly.
TRANSISTOR COUNT
12543 (CMOS) and 700 (Bipolar)
ESD CAUTION
GND = AGND = DGND = 0 V.
Rev. E | Page 6 of 28
Data Sheet
ADF4360-7
20 MUXOUT
19 LE
22 AGND
21 DVDD
23 CE
PIN 1
IDENTIFIER
24 CP
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
18 DATA
CPGND 1
AVDD 2
ADF4360-7
TOP VIEW
(Not to Scale)
15 DGND
14 CN
VVCO 6
CC 12
L2 10
AGND 11
VTUNE 7
AGND 8
L1 9
13 RSET
NOTES
1. THE EXPOSED PAD MUST BE CONNECTED
TO AGND.
04441-003
AGND 3
RFOUTA 4
RFOUTB 5
17 CLK
16 REFIN
Figure 3. Pin Configuration
Table 4. Pin Function Descriptions
Pin No.
Mnemonic
Description
1
2
CPGND
AVDD
3, 8, 11, 22
4
AGND
RFOUTA
5
RFOUTB
6
VVCO
7
9
VTUNE
L1
10
L2
12
13
CC
RSET
Charge Pump Ground. This is the ground return path for the charge pump.
Analog Power Supply. This ranges from 3.0 V to 3.6 V. Decoupling capacitors to the analog ground plane should be
placed as close as possible to this pin. AVDD must have the same value as DVDD.
Analog Ground. This is the ground return path of the prescaler and VCO.
VCO Output. The output level is programmable from −5 dBm to −14 dBm. See the Output Matching section for a description of the various output stages.
VCO Complementary Output. The output level is programmable from −5 dBm to −14 dBm. See the Output Matching
section for a description of the various output stages.
Power Supply for the VCO. This ranges from 3.0 V to 3.6 V. Decoupling capacitors to the analog ground plane should
be placed as close as possible to this pin. VVCO must have the same value as AVDD.
Control Input to the VCO. This voltage determines the output frequency and is derived from filtering the CP output voltage.
An external inductor to AGND should be connected to this pin to set the ADF4360-7 output frequency. L1 and L2 need
to be the same value. For inductances greater than 3.3 nH, a 470 Ω resistor should be added in parallel to AGND.
An external inductor to AGND should be connected to this pin to set the ADF4360-7 output frequency. L1 and L2 need
to be the same value. For inductances greater than 3.3 nH, a 470 Ω resistor should be added in parallel to AGND.
Internal Compensation Node. This pin must be decoupled to ground with a 10 nF capacitor.
Connecting a resistor between this pin and CPGND sets the maximum charge pump output current for the synthesizer. The
nominal voltage potential at the RSET pin is 0.6 V. The relationship between ICP and RSET is
I CPmax 
14
15
16
CN
DGND
REFIN
17
CLK
18
DATA
19
LE
20
21
MUXOUT
DVDD
23
CE
24
0
CP
EP
11.75
RSET
where RSET = 4.7 kΩ, and ICPmax = 2.5 mA.
Internal Compensation Node. This pin must be decoupled to VVCO with a 10 μF capacitor.
Digital Ground.
Reference Input. This is a CMOS input with a nominal threshold of VDD/2 and a dc equivalent input resistance of 100 kΩ
(see Figure 16). This input can be driven from a TTL or CMOS crystal oscillator, or it can be ac-coupled.
Serial Clock Input. This serial clock is used to clock in the serial data to the registers. The data is latched into the 24-bit
shift register on the CLK rising edge. This input is a high impedance CMOS input.
Serial Data Input. The serial data is loaded MSB first with the two LSBs being the control bits. This input is a high impedance CMOS input.
Load Enable, CMOS Input. When LE goes high, the data stored in the shift registers is loaded into one of the four latches, and
the relevant latch is selected using the control bits.
This multiplexer output lets either the lock detect, the scaled RF, or the scaled reference frequency be accessed externally.
Digital Power Supply. This ranges from 3.0 V to 3.6 V. Decoupling capacitors to the digital ground plane should be
placed as close as possible to this pin. DVDD must have the same value as AVDD.
Chip Enable. A logic low on this pin powers down the device and puts the charge pump into three-state mode. Taking
the pin high powers up the device depending on the status of the power-down bits.
Charge Pump Output. When enabled, this provides ± ICP to the external loop filter, which in turn drives the internal VCO.
Exposed Pad. The exposed pad must be connected to AGND.
Rev. E | Page 7 of 28
ADF4360-7
Data Sheet
TYPICAL PERFORMANCE CHARACTERISTICS
–40
0
–50
–10
–20
–70
OUTPUT POWER (dB)
–80
–90
–100
–110
–120
–130
–30
–40
–50
–60
–96.4dBc/Hz
–70
04441-004
–80
–140
–150
100
1k
10k
100k
FREQUENCY OFFSET (Hz)
1M
–90
10M
–2kHz
Figure 4. Open-Loop VCO Phase Noise, L1, L2 = 13 nH
–1kHz
500MHz
–20
OUTPUT POWER (dB)
–105
–110
–115
–120
–125
–130
–135
–30
VDD = 3.3V, VVCO = 3.3V
ICP = 2.5mA
PFD FREQUENCY = 200kHz
LOOP BANDWIDTH = 10kHz
RES. BANDWIDTH = 1kHz
VIDEO BANDWIDTH = 1kHz
AVERAGES = 20
–40
–50
–60
–74dBc
–70
–80
04441-005
–140
1k
10k
100k
FREQUENCY OFFSET (Hz)
1M
04441-008
OUTPUT POWER (dB)
REFERENCE
LEVEL = –3dBm
–10
–80
–85
–90
–95
–100
–90
10M
–0.25MHz
Figure 5. VCO Phase Noise, 500 MHz, 200 kHz PFD, 10 kHz Loop Bandwidth
–0.1MHz
1250MHz
0.1MHz
0.25MHz
Figure 8. Reference Spurs at 500 MHz
(200 kHz Channel Spacing, 10 kHz Loop Bandwidth)
–70
0
–75
REFERENCE
LEVEL = –3dBm
–10
–80
–85
–90
–95
–100
OUTPUT POWER (dB)
–20
–105
–110
–115
–120
–125
–130
–30
–40
VDD = 3.3V, VVCO = 3.3V
ICP = 2.5mA
PFD FREQUENCY = 1MHz
LOOP BANDWIDTH = 25kHz
RES. BANDWIDTH = 1kHz
VIDEO BANDWIDTH = 1kHz
SWEEP = 4.2 SECONDS
AVERAGES = 20
–50
–60
–79dBc
–70
04441-006
–140
1k
10k
100k
FREQUENCY OFFSET (Hz)
1M
04441-009
–80
–135
–145
–150
100
2kHz
0
–75
–145
–150
100
1kHz
Figure 7. Close-In Phase Noise at 500 MHz (200 kHz Channel Spacing)
–70
OUTPUT POWER (dB)
VDD = 3.3V, VVCO = 3.3V
ICP = 2.5mA
PFD FREQUENCY = 200kHz
LOOP BANDWIDTH = 10kHz
RES. BANDWIDTH = 30Hz
VIDEO BANDWIDTH = 30Hz
SWEEP = 1.9 SECONDS
AVERAGES = 10
04441-007
OUTPUT POWER (dB)
–60
REFERENCE
LEVEL = –3.5dBm
–90
10M
–1.1MHz
Figure 6. VCO Phase Noise, 250 MHz,
Divide-by-2 Enabled 200 kHz PFD, 10 kHz Loop Bandwidth
–0.55MHz
500MHz
0.55MHz
Figure 9. Reference Spurs at 500 MHz
(1 MHz Channel Spacing, 25 kHz Loop Bandwidth)
Rev. E | Page 8 of 28
1.1MHz
ADF4360-7
–40
0
–50
–10
–60
–20
–70
OUTPUT POWER (dB)
–80
–90
–100
–110
–120
–50
–60
1k
10k
100k
FREQUENCY OFFSET (Hz)
1M
–70
–2kHz
10M
1.25GHz
1kHz
2kHz
0
–75
REFERENCE
LEVEL = –3dBm
–10
–80
–85
–90
–95
–100
OUTPUT POWER (dB)
–20
–105
–110
–115
–120
–125
–130
–30
VDD = 3.3V, VVCO = 3.3V
ICP = 2.5mA
PFD FREQUENCY = 200kHz
LOOP BANDWIDTH = 10kHz
RES. BANDWIDTH = 1kHz
VIDEO BANDWIDTH = 1kHz
AVERAGES = 20
–40
–50
–60
–79dBc
–70
04441-011
–140
1k
10k
100k
FREQUENCY OFFSET (Hz)
1M
04441-014
–80
–135
–90
10M
–0.25MHz
–0.1MHz
1250MHz
0.1MHz
0.25MHz
Figure 14. Reference Spurs at 1250 MHz
(200 kHz Channel Spacing, 10 kHz Loop Bandwidth)
Figure 11. VCO Phase Noise, 1250 MHz, 200 kHz PFD, 10 kHz Loop Bandwidth
0
–70
–75
REFERENCE
LEVEL = –3dBm
–10
–80
–85
–90
–95
–100
OUTPUT POWER (dB)
–20
–105
–110
–115
–120
–125
–130
–30
–40
VDD = 3.3V, VVCO = 3.3V
ICP = 2.5mA
PFD FREQUENCY = 1MHz
LOOP BANDWIDTH = 25kHz
RES. BANDWIDTH = 1kHz
VIDEO BANDWIDTH = 1kHz
SWEEP = 4.2 SECONDS
AVERAGES = 20
–50
–60
–79dBc
–70
–80
–135
–140
04441-012
OUTPUT POWER (dB)
–1kHz
Figure 13. Close-In Phase Noise at 1250 MHz (200 kHz Channel Spacing)
–70
–145
–150
100
–87.5dBc/Hz
–90
Figure 10. Open-Loop VCO Phase Noise, L1 and L2 = 1.0 nH
OUTPUT POWER (dB)
–40
04441-013
04441-010
–140
–145
–150
100
–30
VDD = 3.3V, VVCO = 3.3V
ICP = 2.5mA
PFD FREQUENCY = 200kHz
LOOP BANDWIDTH = 10kHz
RES. BANDWIDTH = 30Hz
VIDEO BANDWIDTH = 30Hz
SWEEP = 1.9 SECONDS
AVERAGES = 20
–80
–130
–150
100
REFERENCE
LEVEL = –3.5dBm
1k
10k
100k
FREQUENCY OFFSET (Hz)
1M
04441-015
OUTPUT POWER (dB)
Data Sheet
–90
–1.1MHz
10M
Figure 12. VCO Phase Noise, 625 MHz,
Divide-by-2 Enabled 200 kHz PFD, 10 kHz Loop Bandwidth
–0.55MHz
1250MHz
0.55MHz
Figure 15. Reference Spurs at 1250 MHz
(1 MHz Channel Spacing, 25 kHz Loop Bandwidth)
Rev. E | Page 9 of 28
1.1MHz
ADF4360-7
Data Sheet
CIRCUIT DESCRIPTION
REFERENCE INPUT SECTION
N = BP + A
The reference input stage is shown in Figure 16. SW1 and SW2
are normally closed switches. SW3 is normally open. When
power-down is initiated, SW3 is closed, and SW1 and SW2 are
opened. This ensures that there is no loading of the REFIN pin
on power-down.
13-BIT B
COUNTER
LOAD
PRESCALER
P/P+1
FROM VCO
LOAD
5-BIT A
COUNTER
MODULUS
CONTROL
04441-017
POWER-DOWN
CONTROL
N DIVIDER
100k
Figure 17. A and B Counters
SW2
REFIN NC
TO R COUNTER
R COUNTER
BUFFER
SW3
NO
04441-016
SW1
The 14-bit R counter allows the input reference frequency to
be divided down to produce the reference clock to the phase
frequency detector (PFD). Division ratios from 1 to 16,383 are
allowed.
Figure 16. Reference Input Stage
PRESCALER (P/P + 1)
The dual-modulus prescaler (P/P + 1), along with the A and B
counters, enables the large division ratio, N, to be realized
(N = BP + A). The dual-modulus prescaler, operating at CML
levels, takes the clock from the VCO and divides it down to a
manageable frequency for the CMOS A and B counters. The
prescaler is programmable. It can be set in software to 8/9,
16/17, or 32/33 and is based on a synchronous 4/5 core. There is
a minimum divide ratio possible for fully contiguous output
frequencies; this minimum is determined by P, the prescaler
value, and is given by (P2 − P).
PFD AND CHARGE PUMP
The PFD takes inputs from the R counter and N counter
(N = BP + A) and produces an output proportional to the phase
and frequency difference between them. Figure 18 is a simplified schematic. The PFD includes a programmable delay element that controls the width of the antibacklash pulse. This
pulse ensures that there is no dead zone in the PFD transfer
function and minimizes phase noise and reference spurs. Two
bits in the R counter latch, ABP2 and ABP1, control the width
of the pulse (see Table 9).
A AND B COUNTERS
VP
The A and B CMOS counters combine with the dual-modulus
prescaler to allow a wide range division ratio in the PLL feedback counter. The counters are specified to work when the
prescaler output is 300 MHz or less. Thus, with a VCO
frequency of 2.5 GHz, a prescaler value of 16/17 is valid, but a
value of 8/9 is not valid. At fundamental VCO frequencies less
than 700 MHz, a value of 8/9 is best.
HI
D1
Q1
UP
U1
R DIVIDER
CLR1
PROGRAMMABLE
DELAY
Pulse Swallow Function
ABP1
The A and B counters, in conjunction with the dual-modulus
prescaler, make it possible to generate output frequencies that
are spaced only by the reference frequency divided by R. The
VCO frequency equation is
CLR2
HI
D2
Q2
CP
U3
ABP2
DOWN
U2
N DIVIDER
fVCO  P  B   A f REFIN /R
where:
CHARGE
PUMP
CPGND
R DIVIDER
fVCO is the output frequency of the VCO.
P is the preset modulus of the dual-modulus prescaler
(8/9 or 16/17).
B is the preset divide ratio of the binary 13-bit counter (3 to 8191).
A is the preset divide ratio of the binary 5-bit swallow counter
(0 to 31).
fREFIN is the external reference frequency oscillator.
N DIVIDER
CP OUTPUT
Rev. E | Page 10 of 28
Figure 18. PFD Simplified Schematic and Timing (In Lock)
04441-018
NC
TO PFD
Data Sheet
ADF4360-7
Table 5. C2 and C1 Truth Table
MUXOUT AND LOCK DETECT
The output multiplexer on the ADF4360-7 allows the
user to access various internal points on the chip. The state of
MUXOUT is controlled by M3, M2, and M1 in the function
latch. The full truth table is shown in Table 7. Figure 19 shows
the MUXOUT section in block diagram form.
Control Bits
C1
0
1
0
1
C2
0
0
1
1
Lock Detect
MUXOUT can be programmed for two types of lock detect:
digital and analog. Digital lock detect is active high. When LDP
in the R counter latch is set to 0, digital lock detect is set high
when the phase error on three consecutive phase detector cycles
is less than 15 ns.
With LDP set to 1, five consecutive cycles of less than 15 ns
phase error are required to set the lock detect. It stays set high
until a phase error of greater than 25 ns is detected on any
subsequent PD cycle.
VCO
The VCO core in the ADF4360-7 uses eight overlapping bands,
as shown in Figure 20, to allow a wide frequency range to be
covered without a large VCO sensitivity (KV) and resultant poor
phase noise and spurious performance.
The correct band is chosen automatically by the band select logic at
power-up or whenever the N counter latch is updated. It is important that the correct write sequence be followed at power-up.
This sequence is:
The N-channel open-drain analog lock detect should be
operated with an external pull-up resistor of 10 kΩ nominal.
When a lock has been detected, this output is high with narrow
low-going pulses.
1.
2.
3.
R counter latch
Control latch
N counter latch
During band select, which takes five PFD cycles, the VCO VTUNE
is disconnected from the output of the loop filter and connected
to an internal reference voltage.
DVDD
ANALOG LOCK DETECT
DIGITAL LOCK DETECT
R COUNTER OUTPUT
Data Latch
Control Latch
R Counter
N Counter (A and B)
Test Mode Latch
3.0
MUX
MUXOUT
CONTROL
N COUNTER OUTPUT
2.5
Figure 19. MUXOUT Circuit
VOLTAGE (V)
DGND
04441-019
SDOUT
2.0
1.5
INPUT SHIFT REGISTER
The truth table for these bits is shown in Table 5. Table 6 shows
a summary of how the latches are programmed. Note that the
test mode latch is used for factory testing and should not be
programmed by the user.
1.0
0.5
450
04441-020
The digital section of the ADF4360-7 includes a 24-bit input
shift register, a 14-bit R counter, and an 18-bit N counter
comprised of a 5-bit A counter and a 13-bit B counter. Data is
clocked into the 24-bit shift register on each rising edge of CLK.
The data is clocked in MSB first. Data is transferred from the
shift register to one of four latches on the rising edge of LE. The
destination latch is determined by the state of the two control
bits (C2, C1) in the shift register. These are the two LSBs, DB1
and DB0, shown in Figure 2.
500
550
FREQUENCY (MHz)
600
650
Figure 20. Frequency vs. VTUNE, ADF4360-7
The R counter output is used as the clock for the band select
logic and should not exceed 1 MHz. A programmable divider is
provided at the R counter input to allow division by 1, 2, 4, or 8 and
is controlled by Bits BSC1 and BSC2 in the R counter latch. Where
the required PFD frequency exceeds 1 MHz, the divide ratio should
be set to allow enough time for correct band selection.
Rev. E | Page 11 of 28
ADF4360-7
Data Sheet
After band selection, normal PLL action resumes. The value of
KV is determined by the value of inductors used (see the Choosing
the Correct Inductance section). If divide-by-2 operation has
been selected (by programming DIV2 [DB22] high in the N
counter latch), the value is halved. The ADF4360-7 contains
linearization circuitry to minimize any variation of the product
of ICP and KV.
If the outputs are used individually, the optimum output stage
consists of a shunt inductor to VDD.
Another feature of the ADF4360-7 is that the supply current
to the RF output stage is shut down until the device achieves lock as
measured by the digital lock detect circuitry. This is enabled by the
mute-till-lock detect (MTLD) bit in the control latch.
RFOUTA
The operating current in the VCO core is programmable in four
steps: 5 mA, 10 mA, 15 mA, and 20 mA. This is controlled by
Bits PC1 and PC2 in the control latch.
VCO
The RFOUTA and RFOUTB pins of the ADF4360-7 are connected
to the collectors of an NPN differential pair driven by buffered
outputs of the VCO, as shown in Figure 21. To allow the user to
optimize the power dissipation vs. the output power requirements, the tail current of the differential pair is programmable
via Bits PL1 and PL2 in the control latch. Four current levels
may be set: 3.5 mA, 5 mA, 7.5 mA, and 11 mA. These levels give
output power levels of −14 dBm, −11 dBm, −8 dBm, and −5 dBm,
respectively, using a 50 Ω resistor to VDD and ac coupling into a
50 Ω load. Alternatively, both outputs can be combined in a
1 + 1:1 transformer or a 180° microstrip coupler (see the
Output Matching section).
Rev. E | Page 12 of 28
BUFFER/
DIVIDE BY 2
04441-021
OUTPUT STAGE
RFOUTB
Figure 21. Output Stage ADF4360-7
Data Sheet
ADF4360-7
LATCH STRUCTURE
Table 6 shows the three on-chip latches for the ADF4360-7. The two LSBs decide which latch is programmed.
Table 6. Latch Structure
DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10
P2
P1
PD2
PD1
CPI6
CPI5
CPI4 CPI3
CPI2
CPI1
PL2
PL1 MTLD CPG
MUXOUT
CONTROL
COUNTER
RESET
CP
THREESTATE
PHASE
DETECTOR
POLARITY
OUTPUT
POWER
LEVEL
CURRENT
SETTING 1
CP GAIN
CURRENT
SETTING 2
MUTE-TILLLD
POWERDOWN 1
PRESCALER
VALUE
POWERDOWN 2
CONTROL LATCH
CORE
POWER
LEVEL
CONTROL
BITS
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
CP
PDP
M3
M2
M1
CR
PC2
PC1 C2 (0) C1 (0)
DB1
DB0
RESERVED
CP GAIN
DIVIDEBY-2
DIVIDE-BY2 SELECT
N COUNTER LATCH
13-BIT B COUNTER
DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10
DIVSEL DIV2
CPG
B13
B12
B11
B10
B9
B8
B7
B6
B5
B4
B3
CONTROL
BITS
5-BIT A COUNTER
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
B2
B1
RSV
A5
A4
A3
A2
A1
DB1
DB0
C2 (1) C1 (0)
ANTIBACKLASH
PULSE
WIDTH
DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10
RSV
RSV BSC2 BSC1 TMB
LDP ABP2 ABP1
CONTROL
BITS
14-BIT REFERENCE COUNTER
R14
R13
R12
R11
R10
R9
Rev. E | Page 13 of 28
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
R8
R7
R6
R5
R4
R3
R2
R1
DB1
DB0
C2 (0) C1 (1)
04441-022
BAND
SELECT
CLOCK
TEST
MODE
BIT
LOCK
DETECT
PRECISION
RESERVED
RESERVED
R COUNTER LATCH
ADF4360-7
Data Sheet
DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10
P2
P1
PD2
PD1
CPI6
CPI5
CPI4 CPI3
CPI2
CPI1
PL2
PL1 MTLD CPG
COUNTER
RESET
OUTPUT
POWER
LEVEL
CP
THREESTATE
PHASE
DETECTOR
POLARITY
CURRENT
SETTING 1
CP GAIN
CURRENT
SETTING 2
MUTE-TILLLD
POWERDOWN 1
PRESCALER
VALUE
POWERDOWN 2
Table 7. Control Latch
MUXOUT
CONTROL
CORE
POWER
LEVEL
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
CP
PDP
M3
M2
M1
CR
PC2
PC1 C2 (0) C1 (0)
PC2
0
0
1
1
CPI6
CPI5
CPI4
ICP(mA)
CPI3
0
0
0
0
1
1
1
1
CPI2
0
0
1
1
0
0
1
1
CPI1
0
1
0
1
0
1
0
1
4.7kΩ
0.31
0.62
0.93
1.25
1.56
1.87
2.18
2.50
PDP
0
1
CP
0
1
CPG
0
1
MTLD
0
1
PL2
0
0
1
1
P2
0
0
1
1
P1
0
1
0
1
PD2
X
X
0
1
PD1
X
0
1
1
PRESCALER VALUE
8/9
16/17
32/33
32/33
OUTPUT POWER LEVEL
0
1
0
1
CURRENT
3.5mA
5.0mA
7.5mA
11.0mA
PHASE DETECTOR
POLARITY
NEGATIVE
POSITIVE
PC1
0
1
0
1
DB1
DB0
CORE POWER LEVEL
5mA
10mA
15mA
20mA
COUNTER
OPERATION
CR
0
1
NORMAL
R, A, B COUNTERS
HELD IN RESET
CHARGE PUMP
OUTPUT
NORMAL
THREE-STATE
CP GAIN
CURRENT SETTING 1
CURRENT SETTING 2
MUTE-TILL-LOCK DETECT
DISABLED
ENABLED
POWER INTO 50Ω (USING 50Ω TO VVCO)
–14dBm
–11dBm
–8dBm
–5dBm
MODE
ASYNCHRONOUS POWER-DOWN
NORMAL OPERATION
ASYNCHRONOUS POWER-DOWN
SYNCHRONOUS POWER-DOWN
04441-023
CE PIN
0
1
1
1
PL1
CONTROL
BITS
Rev. E | Page 14 of 28
M3
0
0
M2
0
0
M1
0
1
0
0
1
1
0
1
1
1
0
0
0
1
1
1
1
1
0
1
OUTPUT
THREE-STATE OUTPUT
DIGITAL LOCK DETECT
(ACTIVE HIGH)
N DIVIDER OUTPUT
DVDD
R DIVIDER OUTPUT
N-CHANNEL OPEN-DRAIN
LOCK DETECT
SERIAL DATA OUTPUT
DGND
Data Sheet
ADF4360-7
RESERVED
CP GAIN
DIVIDEBY-2
DIVIDE-BY2 SELECT
Table 8. N Counter Latch
13-BIT B COUNTER
CONTROL
BITS
5-BIT A COUNTER
DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DIVSEL DIV2
B2
B1
RSV
A5
A4
A3
A2
A1
CPG
B13
B12
B11
B10
B9
B8
B7
B6
B5
B4
B3
DB1
DB0
C2 (1) C1 (0)
THIS BIT IS NOT USED
BY THE DEVICE AND
IS A DON'T CARE BIT.
A5
0
0
0
0
.
.
.
1
1
1
1
B12
0
0
0
0
.
.
.
1
1
1
1
B11
0
0
0
0
.
.
.
1
1
1
1
..........
..........
..........
..........
..........
..........
..........
..........
..........
..........
..........
B3
0
0
0
1
.
.
.
1
1
1
1
B2
0
0
1
1
.
.
.
0
0
1
1
B1
0
1
0
1
.
.
.
0
1
0
1
F4 (FUNCTION LATCH)
FASTLOCK ENABLE
CP GAIN
OPERATION
0
0
0
1
CHARGE PUMP CURRENT SETTING 1
IS PERMANENTLY USED
CHARGE PUMP CURRENT SETTING 2
IS PERMANENTLY USED
..........
A2
A1
0
0
0
0
.
.
.
1
1
1
1
..........
..........
..........
..........
..........
..........
..........
..........
..........
..........
..........
0
0
1
1
.
.
.
0
0
1
1
0
1
0
1
.
.
.
0
1
0
1
A COUNTER
DIVIDE RATIO
0
1
2
3
.
.
.
28
29
30
31
B COUNTER DIVIDE RATIO
NOT ALLOWED
NOT ALLOWED
NOT ALLOWED
3
.
.
.
8188
8189
8190
8191
N = BP + A; P IS PRESCALER VALUE SET IN THE CONTROL LATCH.
B MUST BE GREATER THAN OR EQUAL TO A. FOR CONTINUOUSLY
ADJACENT VALUES OF (N × FREF), AT THE OUTPUT, NMIN IS (P2–P).
DIV2
0
1
DIVSEL
0
1
DIVIDE-BY-2
FUNDAMENTAL OUTPUT
DIVIDE-BY-2
DIVIDE-BY-2 SELECT (PRESCALER INPUT)
FUNDAMENTAL OUTPUT SELECTED
DIVIDE-BY-2 SELECTED
Rev. E | Page 15 of 28
04441-024
B13
0
0
0
0
.
.
.
1
1
1
1
A4
ADF4360-7
Data Sheet
TEST
MODE
BIT
LOCK
DETECT
PRECISION
RESERVED
RESERVED
Table 9. R Counter Latch
BAND
SELECT
CLOCK
ANTIBACKLASH
PULSE
WIDTH
CONTROL
BITS
14-BIT REFERENCE COUNTER
DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
RSV
R8
R7
R6
R5
R4
R3
R2
R1
RSV BSC2 BSC1 TMB
TEST MODE
BIT SHOULD
BE SET TO 0
FOR NORMAL
OPERATION.
LDP
0
1
BSC1
0
1
0
1
R13
R12
R11
R10
R14
0
0
0
0
.
.
.
1
1
1
1
ABP2
0
0
1
1
BSC2
0
0
1
1
R14
ABP1
0
1
0
1
ANTIBACKLASH PULSE WIDTH
3.0ns
1.3ns
6.0ns
3.0ns
LOCK DETECT PRECISION
THREE CONSECUTIVE CYCLES OF PHASE DELAY LESS THAN
15ns MUST OCCUR BEFORE LOCK DETECT IS SET.
FIVE CONSECUTIVE CYCLES OF PHASE DELAY LESS THAN
15ns MUST OCCUR BEFORE LOCK DETECT IS SET.
BAND SELECT CLOCK DIVIDER
1
2
4
8
04441-025
THESE BITS ARE NOT
USED BY THE DEVICE
AND ARE DON'T CARE
BITS.
LDP ABP2 ABP1
Rev. E | Page 16 of 28
R9
R13
0
0
0
0
.
.
.
1
1
1
1
R12
0
0
0
0
.
.
.
1
1
1
1
..........
..........
..........
..........
..........
..........
..........
..........
..........
..........
..........
R3
0
0
0
1
.
.
.
1
1
1
1
R2
0
1
1
0
.
.
.
0
0
1
1
R1
1
0
1
0
.
.
.
0
1
0
1
DB1
DB0
C2 (0) C1 (1)
DIVIDE RATIO
1
2
3
4
.
.
.
16380
16381
16382
16383
Data Sheet
ADF4360-7
POWER-UP
Power-Up Sequence
The correct programming sequence for the ADF4360-7 after
power-up is:
1.
2.
3.
R counter latch
Control latch
N counter latch
Initial Power-Up
Initial power-up refers to programming the device after the
application of voltage to the AVDD, DVDD, VVCO and CE pins. On
initial power-up, an interval is required between programming
the control latch and programming the N counter latch. This
interval is necessary to allow the transient behavior of the
ADF4360-7 during initial power-up to settle.
During initial power-up, a write to the control latch powers up
the device, and the bias currents of the VCO begin to settle. If
these currents have not settled to within 10% of their steadystate value, and if the N counter latch is then programmed, the
VCO may not oscillate at the desired frequency, which does not
allow the band select logic to choose the correct frequency
band, and the ADF4360-7 may not achieve lock. If the recommended interval is inserted, and the N counter latch is programmed, the band select logic can choose the correct frequency band, and the device locks to the correct frequency.
The duration of this interval is affected by the value of the capacitor on the CN pin (Pin 14). This capacitor is used to reduce
the close-in noise of the ADF4360-7 VCO. The recommended
value of this capacitor is 10 µF. Using this value requires an interval of ≥10 ms between the latching in of the control latch bits
and latching in of the N counter latch bits. If a shorter delay is
required, the capacitor can be reduced. A slight phase noise
penalty is incurred by this change, which is further explained in
the Table 10.
Table 10. CN Capacitance vs. Interval and Phase Noise
Recommended Interval Between
Control Latch and N Counter Latch
≥10 ms
≥ 600 µs
Open-Loop Phase Noise at 10 kHz
Offset (L1 and L2 = 1.0 nH)
−90 dBc
−88 dBc
Open-Loop Phase Noise at 10 kHz
Offset (L1 and L2 = 13.0 nH)
−99 dBc
−97 dBc
POWER-UP
CLOCK
DATA
R COUNTER
LATCH DATA
CONTROL
LATCH DATA
N COUNTER
LATCH DATA
LE
REQUIRED INTERVAL
CONTROL LATCH WRITE TO
N COUNTER LATCH WRITE
Figure 22. ADF4360-7 Power-Up Timing
Rev. E | Page 17 of 28
04441-026
CN Value
10 µF
440 nF
ADF4360-7
Data Sheet
Hardware Power-Up/Power-Down
Software Power-Up/Power-Down
If the device is powered down via the hardware (using the
CE pin) and powered up again without any change to the
N counter register during power-down, the device locks at the
correct frequency, because the device is already in the correct
frequency band. The lock time depends on the value of capacitance on the CN pin, which is <10 ms for 10 µF capacitance. The
smaller capacitance of 440 nF on this pin enables lock times of
<600 µs.
If the device is powered down via the software (using the control latch) and powered up again without any change to the N
counter latch during power-down, the device locks at the correct frequency, because the device is already in the correct frequency band. The lock time depends on the value of capacitance on the CN pin, which is <10 ms for 10 µF capacitance. The
smaller capacitance of 440 nF on this pin enables lock times of
<600 µs.
The N counter value cannot be changed while the device is in
power-down, since the device may not lock to the correct
frequency on power-up. If it is updated, the correct programming sequence for the device after power-up is the R counter
latch, followed by the control latch, and finally the N counter
latch, with the required interval between the control latch and
N counter latch, as described in the Initial Power-Up section.
The N counter value cannot be changed while the device is in
power-down, because the device may not lock to the correct
frequency on power-up. If it is updated, the correct programming sequence for the device after power-up is to the R counter
latch, followed by the control latch, and finally the N counter
latch, with the required interval between the control latch and
N counter latch, as described in the Initial Power-Up section.
Rev. E | Page 18 of 28
Data Sheet
ADF4360-7
CONTROL LATCH
Charge Pump Currents
With (C2, C1) = (0, 0), the control latch is programmed. Table 7
shows the input data format for programming the control latch.
CPI3, CPI2, and CPI1 in the ADF4360-7 determine
Current Setting 1.
Prescaler Value
CPI6, CPI5, and CPI4 determine Current Setting 2. See the
truth table in Table 7.
In the ADF4360-7, P2 and P1 in the control latch set the prescaler values.
Power-Down
DB21 (PD2) and DB20 (PD1) provide programmable powerdown
modes.
In the programmed asynchronous power-down, the device
powers down immediately after latching a 1 into Bit PD1, with
the condition that PD2 has been loaded with a 0. In the programmed synchronous power-down, the device power-down is
gated by the charge pump to prevent unwanted frequency
jumps. Once the power-down is enabled by writing a 1 into
Bit PD1 (on the condition that a 1 has also been loaded to PD2),
the device goes into power-down on the second rising edge of
the R counter output, after LE goes high. When the CE pin is
low, the device is immediately disabled regardless of the state of
PD1 or PD2.
When a power-down is activated (either synchronous or
asynchronous mode), the following events occur:
•
•
•
•
•
•
•
Output Power Level
Bits PL1 and PL2 set the output power level of the VCO. See the
truth table in Table 7.
Mute-Till-Lock Detect
DB11 of the control latch in the ADF4360-7 is the mute-tilllock detect bit. This function, when enabled, ensures that the
RF outputs are not switched on until the PLL is locked.
CP Gain
DB10 of the control latch in the ADF4360-7 is the charge pump
gain bit. When it is programmed to 1, Current Setting 2 is used.
When it is programmed to 0, Current Setting 1 is used.
Charge Pump Three-State
This bit puts the charge pump into three-state mode when
programmed to a 1. It should be set to 0 for normal operation.
Phase Detector Polarity
All active dc current paths are removed.
The R, N, and timeout counters are forced to their load
state conditions.
The charge pump is forced into three-state mode.
The digital lock detect circuitry is reset.
The RF outputs are debiased to a high impedance state.
The reference input buffer circuitry is disabled.
The input register remains active and capable of loading
and latching data.
The PDP bit in the ADF4360-7 sets the phase detector polarity.
The positive setting enabled by programming a 1 is used when
using the on-chip VCO with a passive loop filter or with an
active noninverting filter. It can also be set to 0, which is required if an active inverting loop filter is used.
MUXOUT Control
The on-chip multiplexer is controlled by M3, M2, and M1.
See the truth table in Table 7.
Counter Reset
DB4 is the counter reset bit for the ADF4360-7. When this is 1,
the R counter and the A, B counters are reset. For normal operation, this bit should be 0.
Core Power Level
PC1 and PC2 set the power level in the VCO core. The recommended setting is 5 mA. See the truth table in Table 7.
Rev. E | Page 19 of 28
ADF4360-7
Data Sheet
N COUNTER LATCH
R COUNTER LATCH
Table 8 shows the input data format for programming the
N counter latch.
With (C2, C1) = (0, 1), the R counter latch is programmed.
Table 9 shows the input data format for programming the
R counter latch.
A Counter Latch
R Counter
A5 to A1 program the 5-bit A counter. The divide range is
0 (00000) to 31 (11111).
R1 to R14 set the counter divide ratio. The divide range is
1 (00......001) to 16383 (111......111).
Reserved Bits
DB7 is a spare bit that is reserved. It should be programmed to 0.
Antibacklash Pulse Width
DB16 and DB17 set the antibacklash pulse width.
B Counter Latch
Lock Detect Precision
B13 to B1 program the B counter. The divide range is 3
(00.....0011) to 8191 (11....111).
Overall Divide Range
The overall divide range is defined by ((P × B) + A), where P is
the prescaler value.
CP Gain
DB21 of the N counter latch in the ADF4360-7 is the charge
pump gain bit. When this is programmed to 1, Current Setting 2
is used. When programmed to 0, Current Setting 1 is used. This bit
can also be programmed through DB10 of the control latch. The bit
always reflects the latest value written to it, whether this is through
the control latch or the N counter latch.
Divide-by-2
DB22 is the divide-by-2 bit. When set to 1, the output divide-by-2
function is chosen. When it is set to 0, normal operation occurs.
Divide-by-2 Select
DB23 is the divide-by-2 select bit. When programmed to 1, the
divide-by-2 output is selected as the prescaler input. When set
to 0, the fundamental is used as the prescaler input. For example, using the output divide-by-2 feature and a PFD frequency
of 200 kHz, the user needs a value of N = 5,000 to generate
500 MHz. With the divide-by-2 select bit high, the user may
keep N = 2,500.
DB18 is the lock detect precision bit. This bit sets the number of
reference cycles with less than 15 ns phase error for entering the
locked state. With LDP at 1, five cycles are taken; with LDP at 0,
three cycles are taken.
Test Mode Bit
DB19 is the test mode bit (TMB) and should be set to 0. With
TMB = 0, the contents of the test mode latch are ignored and
normal operation occurs as determined by the contents of the
control latch, R counter latch, and N counter latch. Note that
test modes are for factory testing only and should not be programmed by the user.
Band Select Clock
These bits set a divider for the band select logic clock input. The
output of the R counter is by default the value used to clock the
band select logic, but if this value is too high (>1 MHz), a
divider can be switched on to divide the R counter output to a
smaller value (see Table 9).
Reserved Bits
DB23 to DB22 are spare bits that are reserved. They should be
programmed to 0.
Rev. E | Page 20 of 28
Data Sheet
ADF4360-7
APPLICATIONS INFORMATION
FREQUENCY GENERATOR
This allows frequencies as low as 8 MHz and as high as
137 MHz to be generated using a single system. In the circuit
drawn in Figure 23, the ADF4360-7 is being used to generate
1024 MHz, and the ADF4007 is being used to divide by 8. To
provide a channel spacing of 100 kHz, a PFD frequency of
800 kHz is used for the ADF4360-7 PLL. The loop bandwidth
is chosen to be 20 kHz.
The wide frequency range of the ADF4360-7, plus the on-chip
divider, make it an ideal choice for implementing any general
purpose clock generator or LO.
To implement a clock generator in the FM band, it is necessary
to use an external divider. The ADF4007 contains a hardwareprogrammable N divider, allowing division ratios of 8, 16, 32,
and 64. This divided-down signal is accessed from the MUXOUT pin of the ADF4007.
The output range of the system in Figure 23 is approximately
120 MHz to 135 MHz. The output phase noise is −104 dBc/Hz
at 1 kHz offset. Using different inductor values allows the
ADF4360-7 to be used to synthesize any different range of
frequencies over the operation of the device (235 MHz to
1800 MHz).
The minimum frequency that can be fed to the ADF4007 is
500 MHz. Therefore, 2.2 nH inductors were used to set the
fundamental frequency of oscillation at 1 GHz, with a range
from 950 MHz to 1100 MHz.
VDD
LOCK
DETECT
VDD
VVCO
4.7kΩ
RSET
6
SPI COMPATIBLE SERIAL BUS
FREFIN
21
2
23
VVCO DVDD AVDD CE MUXOUT VTUNE 7
14 CN
CP 24
1nF 1nF
16 REFIN
51Ω
1nF
17
CLK
18
DATA
19
LE
12
CC
13
RSET
CHARGE
PUMP
13kΩ
VP
VDD
M1
M2
PHASE
FREQUENCY
DETECTOR
TO LO
PORT
MUX
MUXOUT
6.8nF
220pF
470pF
6.2kΩ
ADF4360-7
ADF4007
VVCO
51Ω
REFIN
51Ω
100pF
RFOUTA 4
4.7kΩ
3
8
11 22
15
9
10
2.2nH
R COUNTER
÷2
RFINA
RFINB
AGND DGND L1 L2 RF
OUTB 5
CPGND
1
CP
20
N COUNTER
÷8, ÷16,
÷32, ÷64
100pF
CPGND GND
2.2nH
Figure 23. Frequency Generator
Rev. E | Page 21 of 28
N1
N2
04441-027
10µF
ADF4360-7
Data Sheet
CHOOSING THE CORRECT INDUCTANCE VALUE
35
The ADF4360-7 can be used at many different frequencies
simply by choosing the external inductors to give the correct
output frequency. Figure 24 shows a graph of both minimum
and maximum frequency vs. the external inductor value. The
correct inductor should cover the maximum and minimum
frequencies desired. The inductors used are the 0402 CS type
from Coilcraft. To reduce mutual coupling, place the inductors
at right angles to one another.
30
FO =
SENSITIVITY (MHz/V)
15
10
5
0
0
10
20
EXT INDUCTANCE (nH)
30
40
Figure 25. Tuning Sensitivity (in MHz/V) vs. Inductance (nH)
FIXED FREQUENCY LO
Figure 26 shows the ADF4360-7 used as a fixed frequency LO at
500 MHz. The low-pass filter was designed using ADIsimPLL
for a channel spacing of 8 MHz and an open-loop bandwidth of
30 kHz. The maximum PFD frequency of the ADF4360-7 is
8 MHz. Because using a larger PFD frequency allows the use of
a smaller N, the in-band phase noise is reduced to as low as
possible, −109 dBc/Hz. The typical rms phase noise (100 Hz to
100 kHz) of the LO in this configuration is 0.3°. The reference
frequency is from a 16 MHz TCXO from Fox; thus, an R value of
2 is programmed. Taking into account the high PFD frequency
and its effect on the band select logic, the band select clock
divider is enabled. In this case, a value of 8 is chosen. A very simple pull-up resistor and dc blocking capacitor complete the RF
output stage.
1
2π 6.2 pF(0.9 nH + L EXT )
where FO is the center frequency, and LEXT is the external inductance.
1500
1400
1300
1200
FREQUENCY (MHz)
20
04441-029
As shown in Figure 24, the lowest commercially available value of
inductance, 1.0 nH, sets the center frequency at approximately
1300 MHz. For inductances less than 2.4 nH, use a PCB trace, a
direct short. The lowest center frequency of oscillation possible
is approximately 350 MHz, which is achieved using 30 nH inductors. This relationship can be expressed by
25
1100
1000
900
800
700
600
LOCK
DETECT
VVDD
VVCO
300
0
5
10
15
20
EXT INDUCTANCE (nH)
25
6
10µF
30
FOX
801BE-160
16MHz
Figure 24. Output Center Frequency vs. External Inductor Value
The approximate value of capacitance at the midpoint of the
center band of the VCO is 6.2 pF, and the approximate value of
internal inductance due to the bond wires is 0.9 nH. The VCO
sensitivity is a measure of the frequency change vs. the tuning
voltage. It is a very important parameter for the low-pass filter.
Figure 25 shows a graph of the tuning sensitivity (in MHz/V)
vs. the inductance (nH). It can be seen that as the inductance
increases, the sensitivity decreases. This relationship can be
derived from the previous equation; that is, because the inductance has increased, the change in capacitance from the varactor
has less of an effect on the frequency.
SPI COMPATIBLE SERIAL BUS
400
Rev. E | Page 22 of 28
21
2
23
20
VVCO DVDD AVDD CE MUXOUT VTUNE 7
14 CN
CP 24
1nF 1nF
16 REFIN
51Ω
1nF
17
CLK
18
DATA
19
LE
12
CC
13
RSET
2.7nF
820pF
510Ω
ADF4360-7
VVCO
51Ω
51Ω
100pF
RFOUTA 4
4.7kΩ
AGND DGND L1 L2 RF
OUTB 5
CPGND
1
910Ω
27nF
3
8
11 22
15
9
10
13nH
100pF
470Ω
470Ω
13nH
04441-030
04441-028
500
Figure 26. Fixed Frequency LO
Data Sheet
ADF4360-7
INTERFACING
ADSP-2181 Interface
The ADF4360-7 has a simple SPI®-compatible serial interface
for writing to the device. CLK, DATA, and LE control the data
transfer. When LE goes high, the 24 bits that have been clocked
into the appropriate register on each rising edge of CLK are
transferred to the appropriate latch. See Figure 2 for the timing
diagram and Table 5 for the latch truth table.
Figure 28 shows the interface between the ADF4360-7 and the
ADSP-2181 digital signal processor. The ADF4360-7 needs a
24-bit serial word for each latch write. The easiest way to accomplish this using the ADSP-2181 is to use the autobuffered
transmit mode of operation with alternate framing. This provides a means for transmitting an entire block of serial data
before an interrupt is generated.
SCLOCK
MOSI
TFS
ADSP-2181
I/O PORTS
ADuC812 Interface
Figure 27 shows the interface between the ADF4360-7 and the
ADuC812 MicroConverter®. Because the ADuC812 is based on
an 8051 core, this interface can be used with any 8051-based
microcontroller. The MicroConverter is set up for SPI master
mode with CPHA = 0. To initiate the operation, the I/O port
driving LE is brought low. Each latch of the ADF4360-7 needs a
24-bit word, which is accomplished by writing three 8-bit bytes
from the MicroConverter to the device. After the third byte has
been written, the LE input should be brought high to complete
the transfer.
MOSI
ADuC812
I/O PORTS
SDATA
LE
ADF4360-7
CE
MUXOUT
(LOCK DETECT)
LE
ADF4360-7
CE
MUXOUT
(LOCK DETECT)
Figure 28. ADSP-2181 to ADF4360-7 Interface
Set up the word length for 8 bits and use three memory locations for each 24-bit word. To program each 24-bit latch, store
the 8-bit bytes, enable the autobuffered mode, and write to the
transmit register of the DSP. This last operation initiates the
autobuffer transfer.
PCB DESIGN GUIDELINES FOR CHIP SCALE PACKAGE
The leads on the chip scale package (CP-24) are rectangular.
The printed circuit board pad for these should be 0.1 mm longer than the package lead length and 0.05 mm wider than the
package lead width. The lead should be centered on the pad to
ensure that the solder joint size is maximized.
SCLK
04441-031
SCLOCK
SCLK
SDATA
04441-032
The maximum allowable serial clock rate is 20 MHz. This
means that the maximum update rate possible is 833 kHz or
one update every 1.2 μs. This is certainly more than adequate
for systems that have typical lock times in hundreds of microseconds.
Figure 27. ADuC812 to ADF4360-7 Interface
I/O port lines on the ADuC812 are also used to control powerdown (CE input) and detect lock (MUXOUT configured as
lock detect and polled by the port input). When operating in
the described mode, the maximum SCLOCK rate of the
ADuC812 is 4 MHz. This means that the maximum rate at
which the output frequency can be changed is 166 kHz.
The bottom of the chip scale package has a central thermal pad.
The thermal pad on the printed circuit board should be at least
as large as this exposed pad. On the printed circuit board, there
should be a clearance of at least 0.25 mm between the thermal
pad and the inner edges of the pad pattern to ensure that shorting is avoided.
Thermal vias may be used on the printed circuit board thermal
pad to improve thermal performance of the package. If vias
are used, they should be incorporated into the thermal pad at a
1.2 mm pitch grid. The via diameter should be between 0.3 mm
and 0.33 mm, and the via barrel should be plated with 1 ounce
of copper to plug the via.
The user should connect the printed circuit thermal pad to
AGND. This is internally connected to AGND.
Rev. E | Page 23 of 28
ADF4360-7
Data Sheet
There are a number of ways to match the output of the
ADF4360-7 for optimum operation; the most basic is to use a
50 Ω resistor to VVCO. A dc bypass capacitor of 100 pF is connected in series, as shown in Figure 29. Because the resistor is
not frequency dependent, this provides a good broadband
match. The output power in this circuit typically gives
−5 dBm output power into a 50 Ω load.
If the user does not need the differential outputs available
on the ADF4360-7, the user may either terminate the unused
output or combine both outputs using a balun. The circuit in
Figure 31 shows how best to combine the outputs.
VVCO
7.5nH
RFOUTA
9.0nH
47nH
3.3pF
100pF
VVCO
9.0nH
51Ω
RFOUTB
3.3pF
RFOUT
50Ω
04441-033
100pF
Figure 31. Balun for Combining ADF4360-7 RF Outputs
Figure 29. Simple ADF4360-7 Output Stage
A better solution is to use a shunt inductor (acting as an RF
choke) to VVCO. This gives a better match and, therefore, more
output power. Additionally, a series inductor is added after the
dc bypass capacitor to provide a resonant LC circuit. This tunes
the oscillator output and provides approximately 10 dB additional rejection of the second harmonic. The shunt inductor
needs to be a relatively high value (>40 nH).
Experiments have shown that the circuit shown in Figure 30
provides an excellent match to 50 Ω over a limited operating
range of the ADF4360-7 (850 MHz to 950 MHz). This gives
approximately −2 dBm output power across the specific
frequency range of the ADF4360-7 using 3.9 nH. For other
frequencies, a tuned LC is recommended. Both complementary
architectures can be examined using the EV-ADF4360-7EB1Z
evaluation board.
The circuit in Figure 31 is a lumped-lattice-type LC balun. It
is designed for a center frequency of 900 MHz and outputs
5.0 dBm at this frequency. The series 7.5 nH inductor is used to
tune out any parasitic capacitance due to the board layout from
each input, and the remainder of the circuit is used to shift the
output of one RF input by +90° and the second by −90°, thus
combining the two. The action of the 9.0 nH inductor and the
3.3 pF capacitor accomplishes this. The 47 nH is used to provide an RF choke to feed the supply voltage, and the 100 pF
capacitor provides the necessary dc block. To ensure good RF
performance, the circuits in Figure 30 and Figure 31 are implemented with Coilcraft 0402/0603 inductors and AVX 0402 thinfilm capacitors.
Alternatively, instead of the LC balun shown in Figure 31, both
outputs may be combined using a 180° rat-race coupler.
VVCO
47nH
50Ω
04441-034
3.9pF 7.5nH
RFOUT
50Ω
7.5nH
04441-035
OUTPUT MATCHING
Figure 30. Optimum ADF4360-7 Output Stage
Rev. E | Page 24 of 28
Data Sheet
ADF4360-7
OUTLINE DIMENSIONS
4.10
4.00 SQ
3.90
PIN 1
INDICATOR
0.50
BSC
24
19
18
PIN 1
INDICATOR
1
2.40
2.30 SQ
2.20
EXPOSED
PAD
6
13
0.80
0.75
0.70
SEATING
PLANE
0.30
0.25
0.20
0.50
0.40
0.30
12
7
BOTTOM VIEW
0.05 MAX
0.02 NOM
COPLANARITY
0.08
0.203 REF
0.20 MIN
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
COMPLIANT TO JEDEC STANDARDS MO-220-WGGD-8.
01-18-2012-A
TOP VIEW
Figure 32. 24-Lead Lead Frame Chip Scale Package [LFCSP]
4 mm × 4 mm and 0.75 mm Package Height
(CP-24-14)
Dimensions shown in millimeters
ORDERING GUIDE
Model 1
ADF4360-7BCPZ
ADF4360-7BCPZRL
ADF4360-7BCPZRL7
EV-ADF4360-7EB1Z
Temperature Range
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
Frequency Range
350 MHz to 1800 MHz
350 MHz to 1800 MHz
350 MHz to 1800 MHz
Package Description
24-Lead Lead Frame Chip Scale Package [LFCSP]
24-Lead Lead Frame Chip Scale Package [LFCSP]
24-Lead Lead Frame Chip Scale Package [LFCSP]
Evaluation Board
Z = RoHS Compliant Part.
1
Rev. E | Page 25 of 28
Package Option
CP-24-14
CP-24-14
CP-24-14
ADF4360-7
Data Sheet
NOTES
Rev. E | Page 26 of 28
Data Sheet
ADF4360-7
NOTES
Rev. E | Page 27 of 28
ADF4360-7
Data Sheet
NOTES
I2C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors).
©2004–2016 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D04441-0-4/16(E)
Rev. E | Page 28 of 28
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