Microwave Wideband Synthesizer with Integrated VCO ADF4355 Data Sheet

Microwave Wideband Synthesizer with Integrated VCO ADF4355 Data Sheet
Microwave Wideband Synthesizer
with Integrated VCO
ADF4355
Data Sheet
FEATURES
GENERAL DESCRIPTION
RF output frequency range: 54 MHz to 6800 MHz
Fractional-N synthesizer and integer-N synthesizer
High resolution 38-bit modulus
Low phase noise, voltage controlled oscillator (VCO)
Programmable divide by 1, 2, 4, 8, 16, 32, or 64 output
Analog and digital power supplies: 3.3 V
Charge pump and VCO power supplies: 5.0 V typical
Logic compatibility: 1.8 V
Programmable dual modulus prescaler of 4/5 or 8/9
Programmable output power level
RF output mute function
3-wire serial interface
Analog and digital lock detect
The ADF4355 allows implementation of fractional-N or
integer-N phase-locked loop (PLL) frequency synthesizers
when used with an external loop filter and an external reference
frequency. A series of frequency dividers permits operation
from 54 MHz to 6800 MHz.
The ADF4355 has an integrated VCO with a fundamental
output frequency ranging from 3400 MHz to 6800 MHz. In
addition, the VCO frequency is connected to divide by 1, 2, 4, 8,
16, 32, or 64 circuits that allow the user to generate radio frequency
(RF) output frequencies as low as 54 MHz. For applications that
require isolation, the RF output stage can be muted. The mute
function is both pin and software controllable.
Control of all on-chip registers is through a simple 3-wire interface.
The ADF4355 operates with analog and digital power supplies
ranging from 3.15 V to 3.45 V, with charge pump and VCO
supplies from 4.75 V to 5.25 V. The ADF4355 also contains
hardware and software power-down modes.
APPLICATIONS
Wireless infrastructure (W-CDMA, TD-SCDMA, WiMAX, GSM,
PCS, DCS, DECT)
Point to point/point to multipoint microwave links
Satellites/VSATs
Test equipment/instrumentation
Clock generation
FUNCTIONAL BLOCK DIAGRAM
AV DD
CE
REFIN A
REFIN B
CLK
DATA
LE
×2
DOUBLER
10-BIT R
COUNTER
DVDD
VP
RSET
VVCO
VRF
AVDD
MULTIPLEXER
÷2
DIVIDER
MUXOUT
LOCK
DETECT
CREG 1
CREG 2
DATA REGISTER
FUNCTION
LATCH
CHARGE
PUMP
CPOUT
PHASE
COMPARATOR
INTEGER
REGISTER
FRACTION
REGISTER
VTUNE
VREF
VBIAS
VCO
CORE
MODULUS
REGISTER
VREGVCO
1/2/4/8
÷
16/32/64
THIRD-ORDER
FRACTIONAL
INTERPOLATOR
OUTPUT
STAGE
RFOUTA+
RFOUTA–
PDBRF
MULTIPLEXER
AGND
CPGND
AGNDRF
SDGND
ADF4355
AGNDVCO
RFOUTB+
RFOUTB–
12910-001
OUTPUT
STAGE
N COUNTER
Figure 1.
Rev. A
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ADF4355
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Register 4 ..................................................................................... 22
Applications ....................................................................................... 1
Register 5 ..................................................................................... 23
General Description ......................................................................... 1
Register 6 ..................................................................................... 24
Functional Block Diagram .............................................................. 1
Register 7 ..................................................................................... 26
Revision History ............................................................................... 2
Register 8 ..................................................................................... 27
Specifications..................................................................................... 3
Register 9 ..................................................................................... 27
Timing Characteristics ................................................................ 5
Register 10 ................................................................................... 28
Absolute Maximum Ratings ............................................................ 6
Register 11 ................................................................................... 28
Transistor Count ........................................................................... 6
Register 12 ................................................................................... 29
ESD Caution .................................................................................. 6
Register Initialization Sequence ............................................... 29
Pin Configuration and Function Descriptions ............................. 7
Frequency Update Sequence ..................................................... 29
Typical Performance Characteristics ............................................. 9
RF Synthesizer—A Worked Example ...................................... 30
Circuit Description ......................................................................... 12
Reference Doubler and Reference Divider ............................. 30
Reference Input Section ............................................................. 12
Spurious Optimization and Fast Lock ..................................... 30
RF N Divider ............................................................................... 12
Optimizing Jitter ......................................................................... 31
Phase Frequency Detector (PFD) and Charge Pump ............ 13
Spur Mechanisms ....................................................................... 31
MUXOUT and Lock Detect ...................................................... 13
Lock Time.................................................................................... 31
Input Shift Registers ................................................................... 13
Applications Information .............................................................. 32
Program Modes .......................................................................... 13
Direct Conversion Modulator .................................................. 32
VCO.............................................................................................. 14
Power Supplies ............................................................................ 33
Output Stage ................................................................................ 14
Register Maps .................................................................................. 16
Printed Circuit Board (PCB) Design Guidelines for a ChipScale Package .............................................................................. 33
Register 0 ..................................................................................... 18
Output Matching ........................................................................ 34
Register 1 ..................................................................................... 19
Outline Dimensions ....................................................................... 35
Register 2 ..................................................................................... 20
Ordering Guide .......................................................................... 35
Register 3 ..................................................................................... 21
REVISION HISTORY
3/16—Rev. 0 to Rev. A
Added Doubler Enabled Parameter, Table 1 ................................. 3
Changes to Table 2 ............................................................................ 5
Deleted VP, VVCO to AVDD Parameter, Table 3 ........................ 6
Changes to Table 4 ............................................................................ 7
Changes to Reference Input Section and INT, FRAC1, FRAC2,
MOD1, MOD2, and R Counter Relationship Section Title ...... 12
Changes to Figure 28 ...................................................................... 16
Changes to Automatic Calibration (Autocalibration) Section
and Prescaler Section ..................................................................... 18
Changes to Phase Resync Section ................................................ 21
Changes to Negative Bleed Section .............................................. 24
Change to Figure 36 ....................................................................... 24
Change to Reserved Section.......................................................... 25
Changes to Loss of Lock (LOL) Mode Section ........................... 26
Changes to ADC Clock Divider (ADC_CLK_DIV) Section ... 28
Changes to Register Initialization Sequence Section and
Changes to Frequency Update Sequence Section ...................... 29
Changes to RF Synthesizer—A Worked Example Section ........ 30
Change to Figure 44 ....................................................................... 32
Changes to Power Supplies Section and Figure 45 .................... 33
4/15—Revision 0: Initial Version
Rev. A | Page 2 of 35
Data Sheet
ADF4355
SPECIFICATIONS
AVDD = DVDD = VRF = 3.3 V ± 5%, 4.75 V ≤ VP = VVCO ≤ 5.25 V, AGND = CPGND = AGNDVCO = SDGND = AGNDRF = 0 V, RSET = 5.1 kΩ,
dBm referred to 50 Ω, TA = TMIN to TMAX, unless otherwise noted.
Table 1.
Parameter
REFINA/REFINB CHARACTERISTICS
Input Frequency
Single-Ended Mode
Differential Mode
Doubler Enabled
Input Sensitivity
Single-Ended Mode
Symbol
Min
Typ
Max
Unit
250
600
100
MHz
MHz
MHz
0.4
AVDD
V p-p
0.4
1.8
V p-p
±60
±250
125
pF
pF
µA
µA
MHz
For f < 10 MHz, ensure slew rate > 21 V/µs
10
10
Differential Mode
Input Capacitance
Single-Ended Mode
Differential Mode
Input Current
Phase Detector Frequency
CHARGE PUMP (CP)
Charge Pump Current, Sink/Source
High Value
Low Value
RSET Range
Current Matching
ICP vs. VCP 1
ICP vs. Temperature
LOGIC INPUTS
Input High Voltage
Input Low Voltage
Input Current
Input Capacitance
LOGIC OUTPUTS
Output High Voltage
Output High Current
Output Low Voltage
POWER SUPPLIES
Analog Power
Digital Power and RF Supply Voltage
Charge Pump and VCO Voltage
Charge Pump Supply Power Current
Digital Power Supply Current +
Analog Power Supply Curent 3
Output Dividers
Supply Current
RFOUTA±/RFOUTB± Supply Current
Low Power Sleep Mode
Test Conditions/Comments
6.9
1.4
ICP
VINH
VINL
IINH/IINL
CIN
1.5
VOH
DVDD − 0.4
1.5
mA
mA
kΩ
%
%
%
0.6
±1
3.0
Single-ended reference programmed
Differential reference programmed
3.15
4.75
AVDD
5.0
8
62
6 to 36
70
16/20/
42/55
500
1000
500
0.4
3.45
V
5.25
9
69
V
Rev. A | Page 3 of 35
85
20/35/
50/70
Fixed
0.5 V ≤ VCP1 ≤ VP − 0.5 V
0.5 V ≤ VCP1 ≤ VP − 0.5 V
VCP1 = 2.5 V
V
V
µA
pF
V
V
µA
V
1.8
IOH
VOL
IVCO
IRFOUT x ±
REFINA biased at AVDD/2; ac coupling
ensures AVDD/2 bias
LVDS and LVPECL compatible,
REFINA/REFINB biased at 2.1 V;
ac coupling ensures 2.1 V bias
RSET = 5.1 kΩ
4.8
0.3
5.1
3
3
1.5
AVDD
DVDD, VRF
VP, VVCO
IP
DIDD, AIDD
Doubler is set in Register 4, Bit DB26
1.8 V output selected
IOL 2 = 500 µA
Voltages must equal AVDD
VP must equal VVCO
mA
mA
mA
mA
µA
µA
Each output divide by 2 consumes 6 mA
RF output stage is programmable;
RFOUTB+/RFOUTB− powered off
Hardware power-down
Software power-down
ADF4355
Parameter
RF OUTPUT CHARACTERISTICS
VCO Frequency Range
RF Output Frequency
VCO Sensitivity
Frequency Pushing (Open-Loop)
Frequency Pulling (Open-Loop)
Harmonic Content
Second
Third
RF Output Power 4
RF Output Power Variation
RF Output Power Variation (over
Frequency)
Level of Signal with RF Output
Disabled
Data Sheet
Symbol
Min
Typ
Max
Unit
Test Conditions/Comments
6800
6800
Fundamental VCO range
15
15
0.5
MHz
MHz
MHz/V
MHz/V
MHz
−27
−22
−20
−12
+8
+3
±1
±3
dBc
dBc
dBc
dBc
dBm
dBm
dB
dB
Fundamental VCO output (RFOUTA+)
Divided VCO output (RFOUTA+)
Fundamental VCO output (RFOUTA+)
Divided VCO output (RFOUTA+)
RFOUTA+ = 1 GHz
RFOUTA+/RFOUTA− = 4.4 GHz
RFOUTA+/RFOUTA− = 4.4 GHz
RFOUTA+/RFOUTA− = 1 GHz to 4.4 GHz
−60
dBm
RFOUTA+/RFOUTA− = 1 GHz, VCO = 4 GHz
−30
dBm
RFOUTA+/RFOUTA− = 4.4 GHz, VCO = 4.4 GHz
3400
53.125
KV
NOISE CHARACTERISTICS
Fundamental VCO Phase Noise
Performance
Normalized In-Band Phase Noise Floor
Fractional Channel 5
Integer Channel 6
Normalized 1/f Noise, PN1_f 7
Integrated RMS Jitter
Spurious Signals due to Phase
Frequency Detector (PFD) Frequency
Voltage standing wave ratio (VSWR) = 2:1
VCO noise in open-loop conditions
−116
−136
−138
−155
−113
−133
−135
−153
−110
−130
−132
−150
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
100 kHz offset from 3.4 GHz carrier
800 kHz offset from 3.4 GHz carrier
1 MHz offset from 3.4 GHz carrier
10 MHz offset from 3.4 GHz carrier
100 kHz offset from 5.0 GHz carrier
800 kHz offset from 5.0 GHz carrier
1 MHz offset from 5.0 GHz carrier
10 MHz offset from 5.0 GHz carrier
100 kHz offset from 6.8 GHz carrier
800 kHz offset from 6.8 GHz carrier
1 MHz offset from 6.8 GHz carrier
10 MHz offset from 6.8 GHz carrier
−221
−223
−116
150
−80
dBc/Hz
dBc/Hz
dBc/Hz
fs
dBc
10 kHz offset; normalized to 1 GHz
VCP is the voltage at the CPOUT pin.
IOL is the output low current.
3
TA = 25°C; AVDD = DVDD = VRF = 3.3 V; VVCO = VP = 5.0 V; prescaler = 4/5; fREFIN = 122.88 MHz; fPFD = 61.44 MHz; and fRF = 1650 MHz.
4
RF output power using the EV-ADF4355SD1Z evaluation board measured into a spectrum analyzer, with board and cable losses de-embedded. The EV-ADF4355SD1Z
RF outputs are pulled up externally using a 4.7 nH inductor. Unused RF output pins are terminated in 50 Ω.
5
Use this figure to calculate the phase noise for any application. To calculate in-band phase noise performance as seen at the VCO output, use the following formula:
−221 + 10log(fPFD) + 20logN. The value given is the lowest noise mode for the fractional channel.
6
Use this figure to calculate the phase noise for any application. To calculate in-band phase noise performance as seen at the VCO output, use the following formula:
−223 + 10log(fPFD) + 20logN. The value given is the lowest noise mode for the integer channel.
7
The PLL phase noise is composed of 1/f (flicker) noise plus the normalized PLL noise floor. The formula for calculating the 1/f noise contribution at an RF frequency (fRF)
and at a frequency offset (f) is given by PN = P1_f + 10log(10 kHz/f) + 20log(fRF/1 GHz). Both the normalized phase noise floor and flicker noise are modeled in the
ADIsimPLL design tool.
1
2
Rev. A | Page 4 of 35
Data Sheet
ADF4355
TIMING CHARACTERISTICS
AVDD = DVDD =VRF = 3.3 V ± 5%, 4.75 V ≤ VP = VVCO ≤ 5.25 V, AGND = CPGND = AGNDVCO = SDGND = AGNDRF = 0 V, RSET = 5.1 kΩ,
dBm referred to 50 Ω, TA = TMIN to TMAX, unless otherwise noted.
Table 2. Write Timing
Parameter
fCLK
t1
t2
t3
t4
t5
t6
t7
Limit
50
10
5
5
10
10
5
20 or (2/fPFD), whichever is longer
Unit
MHz max
ns min
ns min
ns min
ns min
ns min
ns min
ns min
Description
Serial peripheral interface CLK frequency
LE setup time
DATA to CLK setup time
DATA to CLK hold time
CLK high duration
CLK low duration
CLK to LE setup time
LE pulse width
Write Timing Diagram
t4
t5
CLK
t2
DATA
DB31 (MSB)
t3
DB30
DB3
(CONTROL BIT C4)
DB2
(CONTROL BIT C3)
DB1
(CONTROL BIT C2)
DB0 (LSB)
(CONTROL BIT C1)
t7
t1
t6
Figure 2. Write Timing Diagram
Rev. A | Page 5 of 35
12910-002
LE
ADF4355
Data Sheet
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 3.
Parameter
VRF, DVDD, AVDD to GND1
AVDD to DVDD
VP, VVCO to GND1
CPOUT to GND1
Digital Input/Output Voltage to GND1
Analog Input/Output Voltage to GND1
REFINA, REFINB to GND1
REFINA to REFINB
Operating Temperature Range
Storage Temperature Range
Maximum Junction Temperature
θJA, Thermal Impedance Pad Soldered
to GND1
Reflow Soldering
Peak Temperature
Time at Peak Temperature
Electrostatic Discharge (ESD)
Charged Device Model
Human Body Model
1
Rating
−0.3 V to +3.6 V
−0.3 V to +0.3 V
−0.3 V to +5.8 V
−0.3 V to VP + 0.3 V
−0.3 V to DVDD + 0.3 V
−0.3 V to AVDD + 0.3 V
−0.3 V to AVDD + 0.3 V
±2.1 V
−40°C to +85°C
−65°C to +125°C
150°C
27.3°C/W
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
The ADF4355 is a high performance RF integrated circuit with
an ESD rating of 2500 V and is ESD sensitive. Take proper
precautions for handling and assembly.
TRANSISTOR COUNT
The transistor count for the ADF4355 is 103,665 (CMOS) and
3214 (bipolar).
ESD CAUTION
260°C
40 sec
1000 V
2500 V
GND = AGND = SDGND = AGNDRF = AGNDVCO = CPGND = 0 V.
Rev. A | Page 6 of 35
Data Sheet
ADF4355
32
31
30
29
28
27
26
25
CREG 2
SDGND
MUXOUT
REFINA
REFINB
DVDD
PDBRF
CREG 1
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
1
2
3
4
5
6
7
8
ADF4355
TOP VIEW
(Not to Scale)
24
23
22
21
20
19
18
17
VBIAS
VREF
RSET
AGNDVCO
VTUNE
VREGVCO
AGNDVCO
VVCO
NOTES
1. THE EXPOSED PAD MUST BE CONNECTED TO AGND.
12910-003
AGND
VRF
RFOUTA+
RFOUTA−
AGNDRF
RFOUTB+
RFOUTB−
AV DD
9
10
11
12
13
14
15
16
CLK
DATA
LE
CE
AVDD
VP
CPOUT
CPGND
Figure 3. Pin Configuration
Table 4. Pin Function Descriptions
Pin No.
1
Mnemonic
CLK
2
DATA
3
LE
4
CE
5, 16
AVDD
6
VP
7
CPOUT
8
9
10
CPGND
AGND
VRF
11
12
RFOUTA+
RFOUTA−
13
14
AGNDRF
RFOUTB+
15
RFOUTB−
17
VVCO
18, 21
19
AGNDVCO
VREGVCO
20
VTUNE
22
23
RSET
VREF
24
VBIAS
Description
Serial Clock Input. Data is clocked into the 32-bit shift register on the CLK rising edge. This input is a high
impedance CMOS input.
Serial Data Input. The serial data is loaded most significant bit (MSB) first with the four least significant bits (LSBs)
as the control bits. This input is a high impedance CMOS input.
Load Enable, CMOS Input. When LE goes high, the data stored in the shift register is loaded into the register
selected by the four LSBs.
Chip Enable. A logic low on this pin powers down the device and puts the charge pump into three-state mode. A
logic high on this pin powers up the device, depending on the status of the power-down bits.
Analog Power Supply. This pin ranges from 3.15 V to 3.45 V. Connect decoupling capacitors to the analog ground
plane as close to this pin as possible. AVDD must have the same value as DVDD.
Charge Pump Power Supply. VP must have the same value as VVCO. Connect decoupling capacitors to the ground
plane as close to VP as possible.
Charge Pump Output. When enabled, this output provides ±ICP to the external loop filter. The output of the loop
filter is connected to VTUNE to drive the internal VCO.
Charge Pump Ground. This output is the ground return pin for CPOUT.
Analog Ground. Ground return pin for AVDD.
Power Supply for the RF Output. Connect decoupling capacitors to the analog ground plane as close to this pin
as possible. VRF must have the same value as AVDD.
VCO Output. The output level is programmable. The VCO fundamental output or a divided down version is available.
Complementary VCO Output. The output level is programmable. The VCO fundamental output or a divided down
version is available.
RF Output Stage Ground. Ground return pins for the RF output stage.
Auxiliary VCO Output. The output level is programmable. The VCO fundamental output or a divided down version
is available.
Complementary Auxiliary VCO Output. The output level is programmable. The VCO fundamental output or a
divided down version is available.
Power Supply for the VCO. The voltage on this pin ranges from 4.75 V to 5.25 V. Connect decoupling capacitors to
the analog ground plane as close to this pin as possible.
VCO Ground. Ground return path for the VCO.
VCO Compensation Node. Connect decoupling capacitors to the ground plane as close to this pin as possible.
Connect VREGVCO directly to VVCO.
Control Input to the VCO. This voltage determines the output frequency and is derived from filtering the CPOUT
output voltage. The capacitance at this pin (VTUNE input capacitance) is 9 pF.
Bias Current Resistor. Connecting a resistor between this pin and ground sets the charge pump output current.
Internal Compensation Node. DC biased at half the tuning range. Connect decoupling capacitors to the ground
plane as close to this pin as possible.
Reference Voltage. Connect a 100 nF decoupling capacitor to the ground plane as close to this pin as possible.
Rev. A | Page 7 of 35
ADF4355
Pin No.
25, 32
Mnemonic
CREG1, CREG2
26
27
PDBRF
DVDD
28
29
30
REFINB
REFINA
MUXOUT
31
SDGND
EP
Data Sheet
Description
Outputs from the LDO Regulator. CREG1 and CREG2 are the supply voltages to the digital circuits and have a
nominal voltage of 1.8 V. Decoupling capacitors of 100 nF connected to AGND are required for these pins.
RF Power-Down. A logic low on this pin mutes the RF outputs. This mute function is also software controllable.
Digital Power Supply. This pin must be at the same voltage as AVDD. Place decoupling capacitors to the ground
plane as close to this pin as possible.
Complementary Reference Input. If unused, ac-couple this pin to AGND.
Reference Input.
Multiplexer Output. The multiplexer output allows the digital lock detect, the analog lock detect, scaled RF, or the
scaled reference frequency to be externally accessible.
Digital Σ-Δ Modulator Ground. SDGND is the ground return path for the Σ-Δ modulator.
Exposed Pad. The exposed pad must be connected to AGND.
Rev. A | Page 8 of 35
Data Sheet
ADF4355
–50
–50
–70
–70
PHASE NOISE (dBc/Hz)
–90
–110
–130
–150
10k
100k
1M
10M
100M
Figure 4. Open-Loop VCO Phase Noise, 3.4 GHz
–130
–170
1k
–50
–70
–70
–90
–110
–130
–150
1M
10M
100M
÷1
÷2
÷4
÷8
÷16
÷32
÷64
–90
–110
–130
10k
100k
1M
10M
100M
–170
12910-005
1k
Figure 5. Open-Loop VCO Phase Noise, 5.0 GHz
1k
10k
100k
1M
10M
100M
FREQUENCY (Hz)
12910-008
–150
FREQUENCY (Hz)
Figure 8. Closed-Loop Phase Noise, RFOUTA+, Fundamental VCO and Dividers,
VCO = 5.0 GHz, PFD = 61.44 MHz, Loop Bandwidth = 20 kHz
–50
–70
–70
PHASE NOISE (dBc/Hz)
–50
–90
–110
–130
–150
÷1
÷2
÷4
÷8
÷16
÷32
÷64
–90
–110
–130
–150
1k
10k
100k
1M
10M
FREQUENCY (Hz)
Figure 6. Open-Loop VCO Phase Noise, 6.8 GHz
100M
–170
12910-006
–170
100k
Figure 7. Closed-Loop Phase Noise, RFOUTA+, Fundamental VCO and Dividers,
VCO = 3.4 GHz, PFD = 61.44 MHz, Loop Bandwidth = 20 kHz
–50
–170
10k
FREQUENCY (Hz)
PHASE NOISE (dBc/Hz)
PHASE NOISE (dBc/Hz)
–110
12910-007
1k
FREQUENCY (Hz)
PHASE NOISE (dBc/Hz)
–90
–150
12910-004
–170
÷1
÷2
÷4
÷8
÷16
÷32
÷64
1k
10k
100k
1M
FREQUENCY (Hz)
10M
100M
12910-009
PHASE NOISE (dBc/Hz)
TYPICAL PERFORMANCE CHARACTERISTICS
Figure 9. Closed-Loop Phase Noise, RFOUTA+, Fundamental VCO and Dividers,
VCO = 6.8 GHz, PFD = 61.44 MHz, Loop Bandwidth = 20 kHz
Rev. A | Page 9 of 35
ADF4355
÷1
÷2
OUTPUT POWER (dBm)
PHASE NOISE (dBc/Hz)
–70
–90
–110
–130
–170
1k
10k
100k
1M
10M
100M
FREQUENCY (Hz)
12910-010
–150
Figure 10. Closed-Loop Phase Noise, RFOUTA+, Fundamental VCO and
Divide by 2, VCO = 3.4 GHz, PFD = 61.44 MHz, Loop Bandwidth = 2 kHz
–50
10
9
8
7
6
5
4
3
2
1
0
–1
–2
–3
–4
–5
–6
–7
–8
–9
–10
1
2
3
4
5
6
7
FREQUENCY (GHz)
Figure 13. Output Power vs. Frequency, RFOUTA+/RFOUTA− (7.5 nH Inductors,
10 pF Bypass Capacitors, Board Losses De-Embedded)
0
÷1
÷2
SECOND HARMONIC
THIRD HARMONIC
–5
–70
–10
–15
–90
POWER (dBc)
PHASE NOISE (dBc/Hz)
–40°C
+25°C
+85°C
12910-016
–50
Data Sheet
–110
–130
–20
–25
–30
–35
–40
–150
1k
10k
100k
1M
10M
100M
FREQUENCY (Hz)
Figure 11. Closed-Loop Phase Noise, RFOUTA+, Fundamental VCO and
Divide by 2, VCO = 5.0 GHz, PFD = 61.44 MHz, Loop Bandwidth = 2 kHz
–50
–50
12910-011
–170
2
3
4
5
6
7
FREQUENCY (GHz)
Figure 14. RFOUTA+/RFOUTA− Harmonics vs. Frequency (7.5 nH Inductors,
10 pF Bypass Capacitors, Board Losses De-Embedded)
10
÷1
÷2
8
–70
6
4
–90
POWER (dBm)
PHASE NOISE (dBc/Hz)
1
12910-017
–45
–110
–130
2
0
–2
–4
–6
–150
10k
100k
1M
FREQUENCY (Hz)
10M
100M
12910-012
1k
–10
Figure 12. Closed-Loop Phase Noise, RFOUTA+, Fundamental VCO and
Divide by 2, VCO = 6.8 GHz, PFD = 61.44 MHz, Loop Bandwidth = 2 kHz
0
1
2
3
4
FREQUENCY (GHz)
5
6
7
12910-018
–8
–170
Figure 15. RFOUTA+/RFOUTA− Power vs. Frequency (100 nH Inductors, 100 pF
Bypass Capacitors, Board Measurement)
Rev. A | Page 10 of 35
Data Sheet
0.40
–100
–110
0.30
0.25
–120
0.20
–130
0.15
–140
0.10
–150
0.05
1.8
2.8
3.8
4.8
6.8
5.8
–160
12910-021
0
0.8
OUTPUT FREQUENCY (GHz)
1M
10M
100M
Figure 19. Fractional-N Spur Performance, W-CDMA Band, RFOUTA+ =
2113.5 MHz, REFIN = 122.88 MHz, PFD = 61.44 MHz, Output Divide by 2
Selected, Loop Filter Bandwidth = 20 kHz, Channel Spacing = 20 kHz
NOISE AND SPUR POWER (dBc/Hz)
–90
–100
–70
–110
–120
–80
–130
–90
–140
–100
0
1
2
3
4
5
6
RFOUTA+/RFOUTA– OUTPUT FREQUENCY (GHz)
7
–160
10k
100k
1M
10M
100M
FREQUENCY (Hz)
Figure 17. PFD Spur Amplitude vs. RFOUTA+/RFOUTA− Output Frequency,
PFD = 15.36 MHz, PFD = 30.72 MHz, PFD = 61.44 MHz, Loop Filter = 20 kHz
Figure 20. Fractional-N Spur Performance, RFOUTA+ = 2.591 GHz,
REFIN = 122.88 MHz, PFD = 61.44 MHz, Output Divide-by-2 Selected,
Loop Filter Bandwidth = 20 kHz, Channel Spacing = 20 kHz
–80
4.65
4.60
–90
4.55
FREQUENCY (GHz)
–100
–110
–120
–130
–140
4.50
4.45
1
4.40
4.35
4.30
4.25
–150
4.20
1k
10k
100k
1M
FREQUENCY (Hz)
10M
100M
4.15
–1
12910-024
–160
1k
12910-026
–150
12910-022
–110
NOISE AND SPUR POWER (dBc/Hz)
100k
–80
PFD = 15.36MHz
PFD = 30.72MHz
PFD = 61.44MHz
–60
10k
FREQUENCY (Hz)
Figure 16. RMS Jitter vs. Output Frequency, PFD Frequency = 61.44 MHz,
Loop Filter = 20 kHz
–50
1k
Figure 18. Fractional-N Spur Performance, GSM1800 Band, RFOUTA+ =
1550.2 MHz, REFIN = 122.88 MHz, PFD = 61.44 MHz, Output Divide by 4
Selected, Loop Filter Bandwidth = 20 kHz, Channel Spacing = 20 kHz
0
1
TIME (ms)
2
3
4
12910-128
RMS JITTER (ps)
0.35
PFD SPUR AMPLITUDE (dBc)
–90
12910-025
0.45
–80
RMS JITTER (ps) 1kHz TO 20MHz
RMS JITTER (ps) 12kHz TO 20MHz
NOISE AND SPUR POWER (dBc/Hz)
0.50
ADF4355
Figure 21. Lock Time for 250 MHz Jump from 4150 MHz to 4400 MHz,
Loop Bandwidth = 20 kHz
Rev. A | Page 11 of 35
ADF4355
Data Sheet
CIRCUIT DESCRIPTION
REFERENCE INPUT SECTION
Figure 22 shows the reference input stage. The reference input
can accept both single-ended and differential signals. Use the
reference mode bit (Register 4, Bit DB9) to select the signal. To
use a differential signal on the reference input, program this bit
high. In this case, SW1 and SW2 are open, SW3 and SW4 are
closed, and the current source that drives the differential pair of
transistors switches on. The differential signal buffers and provides
an emitter-coupled logic (ECL) to the CMOS converter. When a
single-ended signal is used as the reference, program Bit DB9
in Register 4 to 0. Connect the single-ended reference signal to
REFINA. In this case, SW1 and SW2 are closed, SW3 and SW4
are open, and the current source that drives the differential pair
of transistors switches off.
REFERENCE
INPUT MODE
85kΩ
SW2
SW3
MULTIPLEXER
The INT, FRAC1, FRAC2, MOD1, and MOD2 values, in
conjunction with the R counter, make it possible to generate
output frequencies spaced by fractions of the PFD frequency
(fPFD). For more information, see the RF Synthesizer—A Worked
Example section.
Calculate the RF VCO frequency (VCOOUT) by
VCOOUT = fPFD × N
(1)
where:
VCOOUT is the output frequency of the VCO (without using the
output divider).
fPFD is the frequency of the phase frequency detector.
N is the desired value of the feedback counter, N.
Calculate fPFD by
(2)
fPFD = REFIN × [(1 + D)/(R × (1 + T))]
where:
REFIN is the reference input frequency.
D is the REFIN doubler bit.
R is the preset divide ratio of the binary 10-bit programmable
reference counter (1 to 1023).
T is the REFIN divide by 2 bit (0 or 1).
BUFFER
SW1
INT, FRAC1, FRAC2, MOD1, MOD2, and R Counter
Relationship
TO
R COUNTER
AVDD
N comprises
ECL TO CMOS
CONVERTER
REFINA
N = INT +
REFINB
2.5kΩ
2.5kΩ
12910-226
SW4
BIAS
GENERATOR
Figure 22. Reference Input Stage
RF N DIVIDER
The RF N divider allows a division ratio in the PLL feedback
path. Determine the division ratio by the INT, FRAC1, FRAC2,
and MOD2 values that this divider comprises.
RF N COUNTER
FRAC1 +
N = INT +
MOD2
MOD1
TO PFD
N COUNTER
THIRD-ORDER
FRACTIONAL
INTERPOLATOR
INT
REGISTER
FRAC1
REGISTER
FRAC2
VALUE
MOD2
VALUE
(3)
where:
INT is the 16-bit integer value (23 to 32,767 for the 4/5
prescaler, 75 to 65,535 for the 8/9 prescaler).
FRAC1 is the numerator of the primary modulus (0 to 16,777,215).
FRAC2 is the numerator of the 14-bit auxiliary modulus
(0 to 16,383).
MOD2 is the programmable, 14-bit auxiliary fractional
modulus (2 to 16,383).
MOD1 is a 24-bit primary modulus with a fixed value of 224 =
16,777,216.
Equation 3 results in a very fine frequency resolution with no
residual frequency error. To apply this formula, take the
following steps:
1. Calculate N by dividing VCOOUT/fPFD.
2. The integer value of this number forms INT.
3. Subtract the INT value from the full N value.
4. Multiply the remainder by 224.
5. The integer value of this number forms FRAC1.
6. Calculate MOD2 based on the channel spacing (fCHSP) by
12910-027
FROM
VCO OUTPUT/
OUTPUT DIVIDERS
FRAC2
FRAC2
MOD2
MOD1
FRAC1 +
Figure 23. RF N Divider
Rev. A | Page 12 of 35
MOD2 = fPFD/GCD(fPFD, fCHSP)
(4)
where:
GCD(fPFD, fCHSP) is the greatest common divider of the PFD
frequency and the channel spacing frequency.
fCHSP is the desired channel spacing frequency.
Data Sheet
DVDD
Calculate FRAC2 by the following equation:
FRAC2 = [(N − INT) × 224 − FRAC1)] × MOD2
(5)
THREE-STATE OUTPUT
The FRAC2 and MOD2 fraction results in outputs with zero
frequency error for channel spacings when
fPFD/GCD(fPFD/fCHSP) < 16,383
DVDD
SDGND
(6)
R DIVIDER OUTPUT
N DIVIDER OUTPUT
where:
fPFD is the frequency of the phase frequency detector.
GCD is a greatest common denominator function.
fCHSP is the desired channel spacing frequency.
MUX
CONTROL
MUXOUT
ANALOG LOCK DETECT
DIGITAL LOCK DETECT
RESERVED
If zero frequency error is not required, the MOD1 and MOD2
denominators operate together to create a 38-bit resolution
modulus.
SDGND
12910-029
7.
ADF4355
Figure 25. MUXOUT Block Diagram
INT N Mode
INPUT SHIFT REGISTERS
When FRAC1 and FRAC2 = 0, the synthesizer operates in
integer-N mode.
The ADF4355 digital section includes a 10-bit R counter, a
16-bit RF integer-N counter, a 24-bit FRAC1 counter, a 14-bit
auxiliary fractional counter, and a 14-bit auxiliary modulus
counter. Data clocks into the 32-bit shift register on each rising
edge of CLK. The data clocks in MSB first. Data transfers from
the shift register to one of 12 latches on the rising edge of LE.
The state of the four control bits (C4, C3, C2, and C1) in the
shift register determines the destination latch. As shown in
Figure 2, the four least significant bits (LSBs) are DB3, DB2,
DB1, and DB0. The truth table for these bits is shown in Table 5.
Figure 28 and Figure 29 summarize the programing of the latches.
R Counter
The 10-bit R counter allows the input reference frequency
(REFIN) to be divided down to produce the reference clock to
the PFD. Division ratios from 1 to 1023 are allowed.
PHASE FREQUENCY DETECTOR (PFD) AND
CHARGE PUMP
The PFD takes inputs from the R counter and N counter and
produces an output proportional to the phase and frequency
difference between them. Figure 24 is a simplified schematic
of the PFD. The PFD includes a fixed delay element that sets the
width of the antibacklash pulse. This pulse ensures that there is
no dead zone in the PFD transfer function and provides a
consistent reference spur level. Set the phase detector polarity to
positive on this device because of the positive tuning of the VCO.
HIGH
D1
Q1
UP
U1
CLR1
DELAY
HIGH
U3
CHARGE
PUMP
CP
CLR2
DOWN
D2
Q2
U2
–IN
12910-028
+IN
Figure 24. PFD Simplified Schematic
Table 5. Truth Table for the C4, C3, C2, and C1 Control Bits
C4
0
0
0
0
0
0
0
0
1
1
1
1
1
C3
0
0
0
0
1
1
1
1
0
0
0
0
1
Control Bits
C2
0
0
1
1
0
0
1
1
0
0
1
1
0
C1
0
1
0
1
0
1
0
1
0
1
0
1
0
Register
Register 0
Register 1
Register 2
Register 3
Register 4
Register 5
Register 6
Register 7
Register 8
Register 9
Register 10
Register 11
Register 12
PROGRAM MODES
Table 5 and Figure 28 through Figure 42 show the program
modes that must be set up in the ADF4355.
MUXOUT AND LOCK DETECT
The output multiplexer on the ADF4355 allows the user to access
various internal points on the chip. The M3, M2, and M1 bits in
Register 4 control the state of MUXOUT. Figure 25 shows the
MUXOUT section in block diagram form.
The following settings in the ADF4355 are double buffered: main
fractional value (FRAC1), auxiliary modulus value (MOD2),
auxiliary fractional value (FRAC2), reference doubler, reference
divide by 2 (RDIV2), R counter value, and charge pump current
setting. Two events must occur before the ADF4355 uses a new
value for any of the double buffered settings. First, the new value
must latch into the device by writing to the appropriate register,
and second, a new write to Register 0 must be performed.
Rev. A | Page 13 of 35
ADF4355
Data Sheet
VCO
The VCO core in the ADF4355 consists of four separate VCOs,
each of which uses 256 overlapping bands, which allows covering
a wide frequency range without a large VCO sensitivity (KV) and
without resultant poor phase noise and spurious performance.
The correct VCO and band are chosen automatically by the
VCO and band select logic when Register 0 is updated and autocalibration is enabled. The VCO VTUNE is disconnected from
the output of the loop filter and is connected to an internal
reference voltage.
The R counter output is used as the clock for the band select logic.
After band selection, normal PLL action resumes. The nominal
value of KV is 15 MHz/V when the N divider is driven from the
VCO output, or the KV value is divided by D. D is the output
divider value if the N divider is driven from the RF output divider
(chosen by programming Bits[D23:D21] in Register 6).
The VCO shows variation of KV as the tuning voltage, VTUNE,
varies within the band and from band to band. For wideband
applications covering a wide frequency range (and changing
output dividers), a value of 15 MHz/V provides the most accurate
KV, because this value is closest to the average value. Figure 26
shows how KV varies with fundamental VCO frequency along with
an average value for the frequency band. Users may prefer this
figure when using narrow-band designs.
50
The RFOUTA+ and RFOUTA− pins of the ADF4355 connect to
the collectors of an NPN differential pair driven by buffered
outputs of the VCO, as shown in Figure 27. In this scheme, the
ADF4355 contains internal 50 Ω resistors connected to the VRF pin.
To optimize the power dissipation vs. the output power requirements,
the tail current of the differential pair is programmable using
Bits[D2:D1] in Register 6. Four current levels can be set. These
levels give approximate output power levels of −4 dBm, −1 dBm,
+2 dBm, and +5 dBm, respectively, using a 50 Ω resistor to VRF
and ac coupling into a 50 Ω load. For accurate power levels,
refer to the Typical Performance Characteristics section. With
an output power of 5 dBm, an external shunt inductor is necessary
to provide higher power levels; however, this addition results in
less wideband than the internal bias only. Terminate the unused
complementary output with a similar circuit to the used output.
VRF
50Ω
RFOUTA+
VCO
40
50Ω
RFOUTA–
BUFFER/
DIVIDE BY
1/2/4/8/
16/32/64
Figure 27. Output Stage
Another feature of the ADF4355 is that the supply current to the
output stages can shut down until the ADF4355 achieves lock as
measured by the digital lock detect circuitry. The mute till lock
detect (MTLD) bit (DB11) in Register 6 enables this.
35
30
LINEAR
TREND LINE
AVERAGE
VCO SENSITIVITY
25
20
15
10
3.8
4.3
4.8
5.3
5.8
FREQUENCY (GHz)
6.3
6.8
12910-133
5
0
3.3
VRF
The RFOUTB+/RFOUTB− pins are duplicate outputs that can be
used independently or in addition to the RFOUTA+/RFOUTA− pins.
45
VCO SENSITIVITY, KV (MHz/V)
OUTPUT STAGE
12910-032
For example, to ensure that the modulus value loads correctly,
every time the modulus value updates, Register 0 must be
written to. The RF divider select in Register 6 is also double
buffered, but only when Bit DB14 of Register 4 is high.
Figure 26. KV vs. Frequency
Rev. A | Page 14 of 35
Data Sheet
ADF4355
Table 6. Total IDD (RFOUTA± Refers to RFOUTA+/RFOUTA−)
Divide By
5 V Supply (IVCO and IP)
3.3 V Supply (AIDD, DIDD, IRF)
1
2
4
8
16
32
64
RFOUTA± Off
78 mA
RFOUTA± = −4 dBm
78 mA
RFOUTA± = −1 dBm
78 mA
RFOUTA± = +2 dBm
78 mA
RFOUTA± = +5 dBm
78 mA
79.8 mA
87.8 mA
97.1 mA
104.9 mA
109.8 mA
113.6 mA
115.9 mA
101.3 mA
110.1 mA
119.3 mA
127.1 mA
131.8 mA
135.5 mA
137.8 mA
111.9 mA
120.6 mA
130.1 mA
137.8 mA
142.7 mA
146.5 mA
148.9 mA
122.7 mA
131.9 mA
141.6 mA
149.2 mA
154.1 mA
157.8 mA
160.1 mA
132.8 mA
141.9 mA
152.1 mA
159.7 mA
164.6 mA
168.4 mA
170.8 mA
Rev. A | Page 15 of 35
ADF4355
Data Sheet
REGISTER MAPS
AUTOCAL
PRESCALER
REGISTER 0
RESERVED
CONTROL
BITS
16-BIT INTEGER VALUE (INT)
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9
0
0
0
0
0
0
0
0
0
0
PR1
AC1
N15
N16
N14
N13
N12
N11
N10
N8
N9
N7
DB8
DB7
DB6
DB5
DB4
N5
N4
N3
N2
N1
N6
DB3
DB2
C4(0) C3(0)
DB1
DB0
C2(0) C1(0)
REGISTER 1
RESERVED
CONTROL
BITS
DBR 1
24-BIT MAIN FRACTIONAL VALUE (FRAC1)
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8
0
0
0
F24
0
F22
F23
F21
F20
F19
F18
F17
F16
F15
F14
F13
F12
F11
F10
F9
F8
F7
F6
DB7 DB6
F5
F4
F3
DB5 DB4
F2
F1
DB3
DB2
DB1
DB0
C4(0) C3(0) C2(0) C1(1)
REGISTER 2
14-BIT AUXILIARY FRACTIONAL VALUE (FRAC2)
DBR 1
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9
F14
F13
F12
F11
F10
F9
F8
F7
F6
F5
CONTROL
BITS
14-BIT AUXILIARY MODULUS VALUE (MOD2) DBR 1
F4
F3
F2
M14
F1
M13
M12
M11
M10
M9
M8
M7
DB8
DB7
DB6
DB5
DB4
M5
M4
M3
M2
M1
M6
DB3
DB2
DB1
DB0
C4(0) C3(0) C2(1) C1(0)
PHASE
ADJUST
PHASE
RESYNC
SD LOAD
RESET
RESERVED
REGISTER 3
CONTROL
BITS
DBR 1
24-BIT PHASE VALUE (PHASE)
P23
P22
P21
P19
P20
P18
P17
P16
P15
P14
P13
P12
P11
P10
P9
P8
P7
DB5 DB4
DB3
P6
P5
P4
P3
P2
P1
C4(0) C3(0) C2(1) C1(1)
COUNTER
RESET
P24
CP THREESTATE
PA1
POWER-DOWN
PR1
PD
POLARIT Y
SD1
MUX LOGIC
0
REF MODE
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8
DB7 DB6
DB2
DB1
DB0
CONTROL
BITS
DBR 1
DOUBLE BUFF
MUXOUT
RDIV2
RESERVED
REFERENCE
DOUBLER DBR 1
REGISTER 4
DBR 1
10-BIT R COUNTER
CURRENT
SETTING
DBR 1
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8
0
0
M3
M2
M1
RD2
RD1
R10
R9
R8
R7
R6
R5
R4
R2
R3
R1
D1
CP4
CP3
CP2
CP1
U6
DB7 DB6
U5
U4
U3
DB5 DB4
DB3
U2
C4(0) C3(1) C2(0) C1(0)
U1
DB2
DB1
DB0
REGISTER 5
CONTROL
BITS
DB31 DB30 DB29 DB28 DB27 DB26
0
0
0
0
0
DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
DB9
DB8
DB7
DB6
DB5
DB4
0
0
0
0
1
0
RF OUTPUT
ENABLE
RESERVED
RF
OUTPUT
POWER
0
DB3
DB2
DB1
DB0
C4(0) C3(1) C2(0) C1(1)
AUX RF
OUTPUT
POWER
CONTROL
BITS
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3
0
BL10
BL9
1
0
1
0
D13
D12
D11
D10
BL8
BL7
BL6
BL5
BL4
BL3
BL2
BL1
0
D8
1DBR = DOUBLE BUFFERED REGISTER—BUFFERED BY THE WRITE TO REGISTER 0.
2DBB = DOUBLE BUFFERED BITS—BUFFERED BY A WRITE TO REGISTER 0 WHEN BIT DB14 OF REGISTER 4 IS HIGH.
Figure 28. Register Summary (Register 0 to Register 6)
Rev. A | Page 16 of 35
0
D6
D5
D4
D3
D2
D1
DB2
DB1
DB0
C4(0) C3(1) C2(1) C1(0)
12910-034
RESERVED
CHARGE PUMP BLEED CURRENT
AUX RF OUTPUT
ENABLE
RF DIVIDER
SELECT2
MTLD
RESERVED
RESERVED
FEEDBACK
SELECT
NEGATIVE
BLEED
GATED
BLEED
RESERVED
REGISTER 6
Data Sheet
ADF4355
LDO MODE
LD
CYCLE
COUNT
RESERVED
FRAC-N LD
PRECISION
RESERVED
LOL MODE
LE SYNC
REGISTER 7
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4
0
0
0
1
0
0
LE
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
LD4
LD5
LOL LD3
CONTROL
BITS
DB3
DB2
DB1
DB0
LD2 LD1 C4(0) C3(1) C2(1) C1(1)
REGISTER 8
CONTROL
BITS
RESERVED
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8
0
0
0
1
0
0
0
0
0
0
1
0
1
1
0
1
0
0
0
0
0
1
0
DB7 DB6
0
0
DB5 DB4
1
0
0
DB3
DB2
DB1
DB0
C4(1) C3(0) C2(0) C1(0)
REGISTER 9
VCO BAND DIVISION
SYNTHESIZER
LOCK TIMEOUT
AUTOMATIC LEVEL TIMEOUT
TIMEOUT
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8
VC8
VC7
VC6
VC5
VC4
VC3
VC2
VC1
TL10
TL9
TL8
TL7
TL6
TL5
TL4
TL3
TL2
TL1
AL5
AL4
AL3
AL2
AL1
SL5
CONTROL
BITS
DB7 DB6
DB5 DB4
SL4
SL2
SL3
DB3
DB2
DB1
DB0
SL1 C4(1) C3(0) C2(0) C1(1)
ADC
CLOCK DIVIDER
RESERVED
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
AD8
AD7
AD6
AD5
AD4
DB7 DB6
AD3 AD2
AD1
ADC ENABLE
ADC
CONVERSION
REGISTER 10
DB5 DB4
CONTROL
BITS
DB3
DB2
DB1
DB0
AE2 AE1 C4(1) C3(0) C2(1) C1(0)
REGISTER 11
CONTROL
BITS
RESERVED
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
1
0
0
1
1
0
0
0
DB7 DB6
0
0
0
DB5 DB4
0
0
DB3
DB2
DB1
DB0
C4(1) C3(0) C2(1) C1(1)
REGISTER 12
P15
P14
P13
P12
P11
P10
P9
P8
P7
P6
P5
P4
P3
P2
P1
0
0
0
0
0
1
Figure 29. Register Summary (Register 7 to Register 12)
Rev. A | Page 17 of 35
DB9
DB8
DB7
DB6
DB5
DB4
0
0
0
0
0
1
DB3
DB2
DB1
DB0
C4(1) C3(1) C2(0) C1(0)
12910-035
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10
P16
CONTROL
BITS
RESERVED
RESYNC CLOCK
CONTROL
BITS
16-BIT INTEGER VALUE (INT)
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9
0
0
0
0
0
0
0
0
0
0
AC1
PR1
N16
N15
N14
N13
N12
N11
N10
N9
N8
N7
N6
DB8
DB7
DB6
DB5
DB4
N5
N4
N3
N2
N1
PR1
PRESCALER
N16
N15
...
N5
N4
N3
N2
N1
0
4/5
0
0
...
0
0
0
0
0
NOT ALLOWED
1
8/9
0
0
...
0
0
0
0
1
NOT ALLOWED
0
0
...
0
0
0
1
0
NOT ALLOWED
DB3
DB2
DB1
DB0
C4(0) C3(0) C2(0) C1(0)
INTEGER VALUE (INT)
.
.
...
.
.
.
.
.
...
0
0
...
1
0
1
1
0
NOT ALLOWED
0
0
...
1
0
1
1
1
23
24
AC1
VCO
AUTOCAL
0
0
...
1
1
0
0
0
.
.
...
.
.
.
.
.
...
0
DISABLED
1
1
...
1
1
1
0
1
65533
1
ENABLED
1
1
...
1
1
1
1
0
65534
1
1
...
1
1
1
1
1
65535
INTMIN = 75 WITH PRESCALER = 8/9
12910-036
RESERVED
PRESCALER
Data Sheet
AUTOCAL
ADF4355
Figure 30. Register 0
REGISTER 0
Prescaler
Control Bits
The dual modulus prescaler (P/P + 1), along with the INT,
FRACx, and MODx counters, determines the overall division
ratio from the VCO output to the PFD input. The PR1 bit
(Bit DB20) in Register 0 sets the prescaler value.
With Bits[C4:C1] set to 0000, Register 0 is programmed. Figure 30
shows the input data format for programming this register.
Reserved
Bits[DB31:DB22] are reserved and must be set to 0.
Automatic Calibration (Autocalibration)
Write to Register 0 to enact (by default) the VCO autocalibration
and to choose the appropriate VCO and VCO subband. Write a
1 to the AUTOCAL bit (AC1, Bit DB21) (Bit DB21) to enable
the autocalibration, which is the recommended mode of
operation.
Set the AC1 bit to 0 to disable the autocalibration, leaving the
ADF4355 in the same band it is already in when Register 0
is updated.
Disable the autocalibration only for fixed frequency applications,
phase adjust applications, or very small (<10 kHz) frequency
jumps. Toggling AUTOCAL is also required when changing
frequency (see the Frequency Update Sequence section for
additional details).
Operating at current mode logic levels, the prescaler takes the
clock from the VCO output and divides it down for the counters. It
is based on a synchronous 4/5 core. When the prescaler is set to
4/5, the maximum RF frequency allowed is 6.8 GHz. The prescaler
limits the INT value; therefore, if P is 4/5, NMIN is 23, and if P is
8/9, NMIN is 75.
16-Bit Integer Value
The 16 INT bits (Bits[DB19:DB4]) set the INT value, which
determines the integer part of the feedback division factor. The
INT value is used in Equation 3 (see the INT, FRAC1, FRAC2,
MOD1, MOD2, and R Counter Relationship section). All
integer values from 23 to 32,767 are allowed for the 4/5 prescaler.
For the 8/9 prescaler, the minimum integer value is 75, and the
maximum value is 65,535.
Rev. A | Page 18 of 35
Data Sheet
ADF4355
CONTROL
BITS
DBR 1
24-BIT MAIN FRACTIONAL VALUE (FRAC1)
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8
0
0
0
0
F24
F23
F22
F21
F20
F19
F18
F17
F16
F15
F14
F13
F12
F11
F10
F9
F8
F7
F6
F24
F23
..........
F2
F1
MAIN FRACTIONAL VALUE (FRAC1)
0
0
..........
0
0
0
0
0
..........
0
1
1
0
0
..........
1
0
2
0
0
..........
1
1
3
.
.
..........
.
.
.
.
.
..........
.
.
.
.
.
..........
.
.
.
1
1
..........
0
0
16777212
1
1
..........
0
1
16777213
1
1
..........
1
0
16777214
1
1
.........
1
1
16777215
F5
DB7 DB6
F4
1DBR = DOUBLE BUFFERED REGISTER—BUFFERED BY THE WRITE TO REGISTER 0.
F3
DB5 DB4
DB3
F2
C4(0) C3(0) C2(0) C1(1)
F1
DB2
DB1
DB0
12910-037
RESERVED
Figure 31. Register 1
REGISTER 1
24-Bit Main Fractional Value
Control Bits
The 24 FRAC1 bits (Bits[DB27:DB4]) set the numerator of the
fraction that is input to the Σ-Δ modulator. This fraction, along
with the INT value, specifies the new frequency channel that
the synthesizer locks to, as shown in the RF Synthesizer—A
Worked Example section. FRAC1 values from 0 to (MOD1 − 1)
cover channels over a frequency range equal to the PFD
reference frequency.
With Bits[C4:C1] set to 0001, Register 1 is programmed. Figure 31
shows the input data format for programming this register.
Reserved
Bits[DB31:DB28] are reserved and must be set to 0.
Rev. A | Page 19 of 35
ADF4355
Data Sheet
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9
F14
F13
F12
F11
F10
F9
F8
F7
F6
F5
F4
CONTROL
BITS
14-BIT AUXILIARY MODULUS VALUE (MOD2) DBR 1
F3
F2
F1
M14
M13
M12
M11
M10
M9
M8
M7
M6
DB8
DB7
DB6
DB5
DB4
M5
M4
M3
M2
M1
DB3
DB2
DB1
DB0
C4(0) C3(0) C2(1) C1(0)
F14
F13
..........
F2
F1
FRAC2 WORD
M14
M13
..........
M2
M1
MODULUS VALUE (MOD2)
0
0
..........
0
0
0
0
0
..........
0
0
NOT ALLOWED
0
0
..........
0
1
1
0
0
..........
0
1
NOT ALLOWED
0
0
..........
1
0
2
0
0
..........
1
0
2
0
0
..........
1
1
3
0
0
..........
1
1
3
.
.
..........
.
.
.
.
.
..........
.
.
.
.
.
..........
.
.
.
.
.
..........
.
.
.
.
.
..........
.
.
.
.
.
..........
.
.
.
1
1
..........
0
0
16381
1
1
..........
0
0
16380
1
1
..........
0
1
16382
1
1
..........
0
1
16381
1
1
..........
1
0
16382
1
1
..........
1
0
16382
1
1
.........
1
1
16383
1
1
.........
1
1
16383
1DBR = DOUBLE BUFFERED REGISTER—BUFFERED BY THE WRITE TO REGISTER 0.
Figure 32. Register 2
REGISTER 2
14-Bit Auxiliary Modulus Value (MOD2)
Control Bits
The 14-bit auxiliary modulus value (Bits[DB17:DB4]) sets the
auxiliary fractional modulus. Use MOD2 to correct any residual
error due to the main fractional modulus.
With Bits[C4:C1] set to 0010, Register 2 is programmed. Figure 32
shows the input data format for programming this register.
14-Bit Auxiliary Fractional Value (FRAC2)
The 14-bit auxiliary fractional value (Bits[DB31:DB18]) controls
the auxiliary fractional word. FRAC2 must be less than the
MOD2 value programmed in Register 2.
Rev. A | Page 20 of 35
12910-038
DBR 1
14-BIT AUXILIARY FRACTIONAL VALUE (FRAC2)
ADF4355
PHASE
ADJUST
PHASE
RESYNC
SD LOAD
RESET
RESERVED
Data Sheet
CONTROL
BITS
DBR 1
24-BIT PHASE VALUE (PHASE)
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6
SD1
PR1
PA1
PA1
PR1
SD1
P24
P23
P22
P21
P20
P19
PHASE
ADJUST
P18
P17
P16
P15
P14
P13
P12
P11
P10
P9
P8
P24
P23
..........
P2
P1
PHASE VALUE (PHASE)
0
DISABLED
0
0
..........
0
0
0
1
ENABLED
0
0
..........
0
1
1
0
0
..........
1
0
2
0
0
..........
1
1
3
.
.
..........
.
.
.
.
.
..........
.
.
.
.
.
..........
.
.
.
1
1
..........
0
0
16777212
1
1
..........
0
1
16777213
1
1
..........
1
0
16777214
1
1
.........
1
1
16777215
PHASE
RESYNC
0
DISABLED
1
ENABLED
SD LOAD
RESET
0
ON REGISTER0 UPDATE
1
DISABLED
P7
P6
P5
P4
P3
DB3
P2
C4(0) C3(0) C2(1) C1(1)
P1
DB2
DB1
DB0
12910-039
0
DB5 DB4
1DBR = DOUBLE BUFFERED REGISTER—BUFFERED BY THE WRITE TO REGISTER 0.
Figure 33. Register 3
REGISTER 3
Control Bits
With Bits[C4:C1] set to 0011, Register 3 is programmed. Figure 33
shows the input data format for programming this register.
Reserved
This is achieved by programming the D13 bit (Bit DB24) in
Register 6 to 0, which ensures divided feedback to the N divider.
Phase resynchronization only operateswhen FRAC2 = 0.
For resync applications, enable the SD load reset in Register 3
by setting DB30 to 0.
Phase Adjust
Bit DB31 is reserved and must be set to 0.
SD Load Reset
When writing to Register 0, the Σ-Δ modulator resets. For
applications when the phase is continually adjusted, this may
not be desirable; therefore, in these cases, the Σ-Δ reset can be
disabled by writing a 1 to the SD1 bit (Bit DB30).
Phase Resync
To use the phase resynchronization feature, the PR1 bit (Bit DB29)
must be set to 1. If unused, the bit can be programmed to 0. The
phase resync timer must also be used in Register 12 to ensure that
the resynchronization feature is applied after the PLL has settled
to the final frequency. If the PLL has not settled to the final frequency,
phase resync may not function correctly. Resynchronization is
useful in phased array and beam forming applications. It ensures
repeatability of output phase when programming the same
frequency. In phase critical applications that use frequencies
requiring the output divider (<3400 MHz), it is necessary to
feed the N divider with the divided VCO frequency rather than
from the fundamental VCO frequency.
To adjust the relative output phase of the ADF4355 on each
Register 0 update, set the PA1 bit (Bit DB28) to 1. This feature
differs from the resynchronization feature in that it is useful
when adjustments to the phase are made continually in an
application. For this function, disable the VCO automatic
calibration by setting the AC1 bit (Bit DB21) in Register 0 to 1
and disable the SD load reset by setting the SD1 bit (Bit DB30)
in Register 3 to 1. Note that phase resync and phase adjust
cannot be used simultaneously.
24-Bit Phase Value
The phase of the RF output frequency can adjust in 24-bit steps;
from 0° (0) to 360° (224 − 1). For phase adjust applications, the
phase is set by
(Phase Value/16,777,216) × 360°
When the phase value is programmed to Register 3, each
subsequent adjustment of Register 0 increments the phase by
the value in this equation.
Rev. A | Page 21 of 35
COUNTER
RESET
CP THREESTATE
DBR 1
POWER-DOWN
CURRENT
SETTING
PD
POLARITY
DBR 1
10-BIT R COUNTER
REF MODE
DOUBLE BUFF
DBR 1
RDIV2
MUXOUT
RESERVED
MUX LOGIC
Data Sheet
REFERENCE
DOUBLER DBR 1
ADF4355
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4
0
M3
M2
M1
RD2
R10
RD2
REFERENCE
DOUBLER
0
DISABLED
1
R9
R8
R7
R6
R5
ENABLED
R4
R3
R2
R1
D1
CP4
CP3
COUNTER
RESET
DISABLED
1
ENABLED
1
DIFF
1
ENABLED
CP1
ICP (mA)
5.1kΩ
ENABLED
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0.31
0.63
0.94
1.25
1.56
1.88
2.19
2.50
2.81
3.13
3.44
3.75
4.06
4.38
4.69
5.00
0
1
1
0
0
..........
1
0
2
.
.
..........
.
.
.
.
.
..........
.
.
.
.
.
..........
.
.
.
1
1
..........
0
0
1020
1
1
..........
0
1
1021
1
1
..........
1
0
1022
1
1
..........
1
1
1023
M3
M2
M1
OUTPUT
0
0
0
THREE-STATE OUTPUT
0
0
1
DVDD
0
1
0
SDGND
0
1
1
R DIVIDER OUTPUT
1
0
0
N DIVIDER OUTPUT
1
0
1
ANALOG LOCK DETECT
1
1
0
DIGITAL LOCK DETECT
1
1
1
RESERVED
DB2
0
CP2
..........
DB3
DB1
C4(0) C3(1) C2(0)
U1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
U1
REFIN
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
U2
SINGLE
CP3
R DIVIDER (R)
U3
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
R1
U4
U6
CP4
R2
U5
DISABLED
DISABLED
..........
U6
DOUBLE BUFFERED
REGISTER 6, BITS[DB23:DB21]
0
R9
CP1
0
REFERENCE DIVIDE BY 2
R10
CP2
D1
RD1
1
1DBR
RD1
U5
LDP
U2
CP
THREE-STATE
0
1.8V
0
DISABLED
1
3.3V
1
ENABLED
U4
PD POLARITY
U3
POWER DOWN
0
NEGATIVE
0
DISABLED
1
POSITIVE
1
ENABLED
DB0
C1(0)
12910-040
0
CONTROL
BITS
= DOUBLE BUFFERED REGISTER—BUFFERED BY THE WRITE TO REGISTER 0.
Figure 34. Register 4
REGISTER 4
RDIV2
Control Bits
Setting the RD1 bit (Bit DB25) to 1 inserts a divide by 2 toggle
flip-flop between the R counter and PFD, which extends the
maximum reference frequency input rate. This function provides
a 50% duty cycle signal at the PFD input.
With Bits[C4:C1] set to 0100, Register 4 is programmed. Figure 34
shows the input data format for programming this register.
Reserved
10-Bit R Counter
Bits[DB31:DB30] are reserved and must be set to 0.
The 10-bit R counter divides the input reference frequency
(REFIN) to produce the reference clock to the PFD. Division
ratios range from 1 to 1023.
MUXOUT
The on-chip multiplexer (MUXOUT) is controlled by
Bits[DB29:DB27]. For additional details, see Figure 34.
Double Buffer
Reference Doubler
Setting the RD2 bit (Bit DB26) to 0 feeds the REFIN signal directly
to the 10-bit R counter, disabling the doubler. Setting this bit to
1 multiplies the reference frequency by a factor of 2 before feeding
it into the 10-bit R counter. When the doubler is disabled, the REFIN
falling edge is the active edge at the PFD input to the fractional
synthesizer. When the doubler is enabled, both the rising and
falling edges of the reference frequency become active edges at
the PFD input.
The D1 bit (Bit DB14) enables or disables double buffering of
the RF divider select bits (Bits[DB23:DB21]) in Register 6. The
Program Modes section explains how double buffering works.
Charge Pump Current Setting
The CP4 to CP1 bits (Bits[DB13:DB10]) set the charge pump
current. Set this value to the charge pump current that the loop
filter is designed with (see Figure 34). For the lowest spurs, the
0.9 mA setting is recommended.
The maximum allowable reference frequency when the doubler
is enabled is 100 MHz.
Rev. A | Page 22 of 35
Data Sheet
ADF4355
Reference Mode
When power-down activates, the following events occur:
The ADF4355 permits use of either differential or single-ended
reference sources.
•
For optimum integer boundary spur performance, use the
single-ended setting for all references up to 250 MHz (even if
using a differential reference signal). Use the differential setting for
reference frequencies above 250 MHz.
•
•
•
•
Level Select
The synthesizer counters are forced to their load state
conditions.
The VCO powers down.
The charge pump is forced into three-state mode.
The digital lock detect circuitry resets.
The RFOUTA+/RFOUTA− and RFOUTB+/RFOUTB− output
stages are disabled.
The input registers remain active and capable of loading
and latching data.
•
To assist with logic compatibility, MUXOUT is programmable to
two logic levels. Set the U5 bit (Bit DB8) to 0 to select 1.8 V logic,
and set it to 1 to select 3.3 V logic.
Charge Pump Three-State
Setting the U2 bit (Bit DB5) to 1 puts the charge pump into
three-state mode. Set DB5 to 0 for normal operation.
Phase Detector (PD) Polarity
The U4 bit (Bit DB7) sets the phase detector polarity. When a
passive loop filter or a noninverting active loop filter is used,
set DB7 to 1 (positive). If an active filter with an inverting
characteristic is used, set this bit to 0 (negative).
Counter Reset
The U1 bit (Bit DB4) resets the R counter, N counter, and
VCO band select of the ADF4355. When DB4 is set to 1, the RF
synthesizer N counter and R counter, and the VCO band select,
are reset. For normal operation, set DB4 to 0. Toggling counter
reset (Bit DB4) is also required when changing frequency (see
the Frequency Update Sequence section for additional details).
Power-Down
The U3 bit (Bit DB6) sets the programmable power-down mode.
Setting DB6 to 1 performs a power-down. Setting DB6 to 0
returns the synthesizer to normal operation. In software powerdown mode, the ADF4355 retains all information in its registers.
The register contents are only lost if the supply voltages are
removed.
REGISTER 5
The bits in Register 5 are reserved and must be programmed as
described in Figure 35, using a hexadecimal word of 0x00800025.
DB31 DB30 DB29 DB28 DB27 DB26
0
0
0
0
0
0
DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10
0
0
1
0
0
0
0
0
0
0
0
0
0
0
Figure 35. Register 5 (0x00800025)
Rev. A | Page 23 of 35
0
0
DB9
DB8
DB7
DB6
DB5
DB4
0
0
0
0
1
0
DB3
DB2
DB1
DB0
C4(0) C3(1) C2(0) C1(1)
12910-041
CONTROL
BITS
RESERVED
AUX RF
OUTPUT
POWER
RF OUTPUT
ENABLE
AUX RF OUTPUT
ENABLE
CHARGE PUMP BLEED CURRENT
RESERVED
RF DIVIDER
SELECT1
MTLD
RESERVED
RESERVED
FEEDBACK
SELECT
Data Sheet
NEGATIVE
BLEED
GATED
BLEED
RESERVED
ADF4355
RF
OUTPUT
POWER
CONTROL
BITS
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3
0
BL10
BL9
1
0
1
0
D13
D12
D11
D10
BL8
BL7
BL5
BL6
BL4
BL3
BL2
BL1
0
D8
0
D6
D5
D4
D3
FEEDBACK
D13 SELECT
0
1
DIVIDED
FUNDAMEN TAL
D2
D1
DB2
DB1
DB0
C4(0) C3(1) C2(1) C1(0)
D2
D1
OUTPUT POWER
0
0
–4dBm
0
1
–1dBm
1
0
+2dBm
1
1
+5dBm
BL9 BLEED CURRENT
1
DISABLED
ENABLED
BL10 GATED BLEED
0
1
DISABLED
ENABLED
D11
D10
RF DIVIDER SELECT
0
0
0
0
0
1
÷2
0
1
0
÷4
0
1
1
1
0
1
0
1
1
÷1
D8
MUTE TILL
LOCK DETECT
÷8
0
MUTE DISABLED
0
÷16
1
MUTE ENABLED
1
÷32
0
÷64
BL7
..........
BL2
BL1
0
0
..........
0
1
1
(3.75µA)
0
0
..........
1
0
2
(7.5µA)
.
.
..........
.
.
.
.
.
..........
.
.
.
.
.
..........
.
.
.
1
1
..........
0
0
252
(945µA)
1
1
..........
0
1
253
(948.75µA)
1
1
..........
1
0
254
(952.5µA)
1
1
..........
1
1
255
(956.25µA)
BL8
D3
RF OUT
0
DISABLED
1
ENABLED
D5
D4
AUXILIARY OUTPUT POWER
0
0
–4dBm
0
1
–1dBm
1
0
+2dBm
1
1
+5dBm
D6
AUXILIARY OUT
0
DISABLED
1
ENABLED
BLEED CURRENT
1BITS[DB23:DB21] ARE BUFFERED BY A WRITE TO REGISTER 0 WHEN THE DOUBLE BUFFER BIT IS ENABLED, BIT DB14 OF REGISTER 4.
12910-042
0
D12
Figure 36. Register 6
REGISTER 6
Control Bits
With Bits[C4:C1] set to 0110, Register 6 is programmed. Figure 36
shows the input data format for programming this register.
Use negative bleed only when operating in fractional-N mode,
that is, FRAC1 or FRAC2 is not equal to 0. Do not use negative
bleed for fPFD greater than 100 MHz.
Reserved
Reserved
Bits[DB28:DB25] are reserved and must be set to 1010.
Bit DB31 is reserved and must be set to 0.
Feedback Select
Gated Bleed
D13 (Bit DB24) selects the feedback from the output of the
VCO to the N counter. When D13 is set to 1, the signal is taken
directly from the VCO. When this bit is set to 0, the signal is
taken from the output of the output dividers. The dividers
enable coverage of the wide frequency band (54 MHz to
6800 MHz). When the divider is enabled and the feedback
signal is taken from the output, the RF output signals of two
separately configured PLLs are in phase. Divided feedback is
useful in some applications where the positive interference of
signals is required to increase the power.
Bleed currents can improve phase noise and spurs; however, due
to a potential impact on lock time, the gated bleed bit, BL10
(Bit DB30), if set to 1, ensures bleed currents are not switched
on until the digital lock detect asserts logic high. Note that this
function requires digital lock detect to be enabled.
Negative Bleed
Use of constant negative bleed is recommended for most
applications because it improves the linearity of the charge
pump leading to lower noise and spurs than leaving negative
bleed off. To enable negative bleed, write 1 to BL9 (Bit DB29),
and to disable negative bleed, write 0 to BL9 (Bit DB29).
RF Divider Select
D12 to D10 (Bits[DB23:DB21]) select the value of the RF output
divider (see Figure 36).
Rev. A | Page 24 of 35
Data Sheet
ADF4355
Charge Pump Bleed Current
Reserved
BL8 to BL1 (Bits[DB20:DB13]) control the level of the bleed
current added to the charge pump output. This current
optimizes the phase noise and spurious levels from the device.
Bit DB10 is reserved and must be set to 0.
Tests have shown that the optimal bleed set is the following:
4/N < IBLEED/ICP < 10/N
where:
IBLEED is the value of constant negative bleed applied to the
charge pump, which is set by the contents of Bits[BL8:BL1].
ICP is the value of charge pump current setting, Bits[DB13:DB10] of
Register 4.
N is the value of the feedback counter from the VCO to the PFD.
Reserved
Bit DB12 is reserved and must be set to 0.
Mute Till Lock Detect
When D8 (Bit DB11) is set to 1, the supply current to the RF
output stage is shut down until the device achieves lock, as
determined by the digital lock detect circuitry.
Auxiliary RF Output Enable
Bit DB9 enables or disables the auxiliary frequency RF output
(RFOUTB+/RFOUTB−). When DB9 is set to 1, the auxiliary
frequency RF output is enabled. When DB9 is set to 0, the
auxiliary RF output is disabled.
Auxiliary RF Output Power
Bits[DB8:DB7] set the value of the auxiliary RF output power
level (see Figure 36).
RF Output Enable
Bit DB6 enables or disables the primary RF output (RFOUTA+/
RFOUTA−). When DB6 is set to 0, the primary RF output is
disabled. When DB6 is set to 1, the primary RF output is
enabled.
Output Power
Bits[DB5:DB4] set the value of the primary RF output power
level (see Figure 36).
Rev. A | Page 25 of 35
LD
CYCLE
COUNT
RESERVED
LD MODE
LOL MODE
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4
0
0
0
1
0
0
LE
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
LD5
LD4
LOL LD3
LE SYNCHRONIZ ATION
DB3
DB2
DB1
DB0
LD2 LD1 C4(0) C3(1) C2(1) C1(1)
LD1
LE
CONTROL
BITS
LOCK DETECT MODE
0
FRACTIONAL-N
1
INTEGER-N (2.9ns)
LD3
LD2
FRACTIONAL-N LD PRECISION
0
0
5.0ns
0
1
6.0ns
1
0
8.0ns
1
1
12.0ns
LOL LOSS OF LOCK MODE
0
DISABLED
0
DISABLED
1
LE SYNCED TO REFIN
1
ENABLED
LD5
LD4
LOCK DETECT CYCLE COUNT
0
0
1024
0
1
2048
1
0
4096
1
1
8192
12910-043
RESERVED
FRAC-N LD
PRECISION
Data Sheet
LE SYNC
ADF4355
Figure 37. Register 7
REGISTER 7
Loss of Lock (LOL) Mode
Control Bits
Set LOL (Bit DB7) to 1 when the application is a fixed frequency
application in which the input reference frequency (REFIN) is likely
to be removed, such as a clocking application. The standard lock
detect circuit assumes that REFIN is always present; however, this
may not be the case with clocking applications. To enable this
functionality, set DB7 to 1. Loss of lock mode does not function
reliably when using a differential REFIN mode.
With Bits[C4:C1] set to 0111, Register 7 is programmed. Figure 37
shows the input data format for programming this register.
Reserved
Bits[DB31:DB29] are reserved and must be set to 0. Bit DB28 is
reserved and must be set to 1. Bits[DB27:DB26] are reserved
and must be set to 0.
LE Sync
When set to 1, Bit DB25 ensures that the load enable (LE) edge
is synchronized internally with the rising edge of reference
input frequency. This synchronization prevents the rare event of
reference and RF dividers from loading at the same time as a falling
edge of reference frequency, which can lead to longer lock times.
Reserved
Bits[DB24:DB10] are reserved and must be set to 0.
Fractional-N Lock Detect Count (LDC)
Fractional-N Lock Detect Precision (LDP)
LD3 and LD2 (Bits[DB6:DB5]) set the precision of the lock detect
circuitry in fractional-N mode. LDP is available at 5.0 ns, 6.0 ns,
8.0 ns, or 12.0 ns. If bleed currents are used, use 12 ns.
Lock Detect Mode (LDM)
If LD1 (Bit DB4) is set to 0, each reference cycle is set by
fractional-N lock detect precision as described in the
Fractional-N Lock Detect Count (LDC) section. If DB4 is
set to 1, each reference cycle is 2.9 ns long, which is more
appropriate for integer-N applications.
LD5 and LD4 (Bits[DB9:DB8]) set the number of consecutive
cycles counted by the lock detect circuitry before asserting lock
detect high. See Figure 37 for details.
Rev. A | Page 26 of 35
Data Sheet
ADF4355
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4
0
0
1
0
0
0
0
0
0
0
1
0
1
1
0
1
0
0
0
0
0
1
0
0
0
1
0
DB3
0
DB2
DB1
DB0
C4(1) C3(0) C2(0) C1(0)
12910-044
CONTROL
BITS
RESERVED
Figure 38. Register 8 (0x102D0428)
SYNTHESIZER
LOCK TIMEOUT
AUTOMATIC LEVEL TIMEOUT
TIMEOUT
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8
VC8
VC7
VC6
VC5
VC4
VC3
VC2
VC1
TL10
TL9
TL8
TL7
TL6
TL5
TL4
TL3
TL2
TL1
AL5
AL4
AL3
AL2
..........
TL2
TL1
VC8
VC7
..........
VC2
VC1
0
0
..........
0
1
1
0
0
..........
1
0
2
.
.
..........
.
.
.
.
.
..........
.
.
.
.
.
..........
.
.
.
1
1
..........
0
0
252
0
0
..........
0
1
1
0
0
..........
1
0
2
.
.
..........
.
.
.
.
.
..........
.
.
.
.
.
..........
.
.
.
1
1
..........
0
0
1020
1
1
..........
0
1
1021
1
1
..........
1
0
1022
1
1
..........
1
1
1023
AL5
VCO BAND DIV
1
1
..........
0
1
253
1
1
..........
1
0
254
1
1
..........
1
1
255
TIMEOUT
SL5
DB7 DB6
DB5 DB4
SL4
SL2
SL3
DB3
SL4
..........
SL2
SL1
0
..........
0
1
1
0
0
..........
1
0
2
.
.
..........
.
.
.
.
.
..........
.
.
.
.
.
..........
.
.
.
1
1
..........
0
0
28
1
1
..........
0
1
29
1
1
..........
1
0
30
1
1
..........
1
1
31
ALC WAIT
AL4
..........
AL2
AL1
0
0
..........
0
1
1
0
0
..........
1
0
2
.
.
..........
.
.
.
.
.
..........
.
.
.
.
..........
.
.
.
1
1
..........
0
0
28
1
1
..........
0
1
29
1
1
..........
1
0
30
1
1
..........
1
1
31
DB2
DB1
DB0
SL1 C4(1) C3(0) C2(0) C1(1)
0
SL5
TL9
TL10
AL1
CONTROL
BITS
SLC WAIT
.
12910-045
VCO BAND DIVISION
Figure 39. Register 9
REGISTER 8
Automatic Level Calibration Timeout
The bits in this register are reserved and must be programmed
as described in Figure 38, using a hexadecimal word of
0x102D0428.
AL5 to AL1 (Bits[DB13:DB9]) set the timer value used for the
automatic level calibration of the VCO. This function combines
the PFD frequency, the timeout variable, and ALC wait variable.
Choose ALC such that the following equation is always greater
than 50 μs.
REGISTER 9
Control Bits
With Bits[C4:C1] set to 1001, Register 9 is programmed. Figure 39
shows the input data format for programming this register.
VCO Band Division
VC8 to VC1 (Bits[DB31:DB24]) set the value of the VCO band
division clock. Determine the value of this clock by PFD/(band
division × 16) such that the result is <150 kHz.
(Timeout × ALC Wait/PFD Frequency) > 50 μs
Synthesizer Lock Timeout
SL5 to SL1 (Bits[DB8:DB4]) set the synthesizer lock timeout
value. Use this value to allow the VTUNE force to settle on the
VTUNE pin. The value must be 20 μs. Calculate the value using
the following equation:
Timeout
TL10 to TL1 (Bits[DB23:DB14]) set the timeout value for the
VCO band select. Use this value as a variable in the other VCO
calibration settings.
Rev. A | Page 27 of 35
(Timeout × Synthesizer Lock Timeout/PFD Frequency) > 20 μs
Data Sheet
ADC
CLOCK DIVIDER
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
AD8
AD7
AD6
AD5
AD4
DB7 DB6
AD3 AD2
AD7
..........
AD2
0
0
..........
0
1
1
0
0
..........
1
0
2
.
.
..........
.
.
.
.
.
..........
.
.
.
.
.
..........
.
.
.
1
1
..........
0
0
252
1
1
..........
0
1
253
1
1
..........
1
0
254
1
1
..........
1
1
255
AD8
DB5 DB4
AD1
CONTROL
BITS
DB3
DB2
DB1
DB0
AE2 AE1 C4(1) C3(0) C2(1) C1(0)
AE1
ADC
0
DISABLED
1
ENABLED
AE2
ADC CONVERSION
0
DISABLED
1
ENABLED
AD1 ADC CLK DIV
12910-047
RESERVED
ADC ENABLE
ADC
CONVERSION
ADF4355
Figure 40. Register 10
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
1
0
0
1
1
0
0
0
0
0
0
0
0
DB3
DB2
DB1
DB0
C4(1) C3(0) C2(1) C1(1)
12910-048
CONTROL
BITS
RESERVED
Figure 41. Register 11 (0x0061300B)
Choose the ADC_CLK_DIV value such that
REGISTER 10
Control Bits
ADC_CLK_DIV = ceiling(((fPFD/100,000) − 2)/4)
With Bits[C4:C1] set to 1010, Register 10 is programmed.
Figure 40 shows the input data format for programming this
register.
where ceiling() is a function to round up to the nearest integer.
For example, for fPFD = 61.44 MHz, set ADC_CLK_DIV = 154
so that the ADC clock frequency is 99.417 kHz. If ADC_CLK_DIV
is greater than 255, set it to 255.
Reserved
Bits[DB31:DB14] are reserved. Bits[DB23:DB22] must be set to
11, but all other bits in this range must be set to 0.
ADC Clock Divider (ADC_CLK_DIV)
An on-board analog-to-digital converter (ADC) determines the
VTUNE setpoint relative to the ambient temperature of the ADF4355
environment. The ADC ensures that the initial tuning voltage
in any application is chosen correctly to avoid any temperature
drift issues.
The ADC uses a clock that is equal to the output of the R counter
(or the PFD frequency) divided by ADC_CLK_DIV.
AD8 to AD1 (Bits[DB13:DB6]) set the value of this divider. On
power-up, the R counter is not programmed; however, in these
power-up cases, it defaults to R = 1.
ADC Conversion Enable
AE2 (Bit DB5) ensures that the ADC performs a conversion
when a write to Register 10 is performed. It is recommended to
enable this mode.
ADC Enable
AE1 (Bit DB4), when set to 1, powers up the ADC for the
temperature dependent VTUNE calibration. It is recommended to
always use this function.
REGISTER 11
The bits in this register are reserved and must be programmed as
described in Figure 41, using a hexadecimal word of 0x0061300B.
Rev. A | Page 28 of 35
Data Sheet
ADF4355
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10
P15
P14
P13
P12
P11
P10
P9
P8
P7
P6
P5
P4
P3
P2
P16
P15
...
P5
P4
P3
P2
P1
RESYNC CLOCK
0
0
...
0
0
0
0
0
NOT ALLOWED
0
0
...
0
0
0
0
1
1
0
0
...
0
0
0
1
0
2
.
.
...
.
.
.
.
.
...
0
0
...
1
0
1
1
0
22
0
0
...
1
0
1
1
1
23
0
0
...
1
1
0
0
0
24
.
.
...
.
.
.
.
.
...
1
1
...
1
1
1
0
1
65533
1
1
...
1
1
1
1
0
65534
1
1
...
1
1
1
1
1
65535
P1
0
0
0
0
0
1
DB9
DB8
DB7
DB6
DB5
DB4
0
0
0
0
0
1
DB3
DB2
DB1
DB0
C4(1) C3(1) C2(0) C1(0)
12910-049
P16
CONTROL
BITS
RESERVED
RESYNC CLOCK
Figure 42. Register 12
REGISTER 12
Control Bits
With Bits[C4:C1] set to 1100, Register 12 is programmed. Figure 42
shows the input data format for programming this register.
Phase Resync Clock Divider Value
P16 to P1 (Bits[DB31:DB16]) set the timeout counter for
activation of phase resync. This value must be set such that a
resync happens immediately after (and not before) the PLL has
achieved lock after reprogramming.
Calculate the timeout value using the following equation:
Time Out Value = Phase Resync Clock/PFD Frequency
Reserved
Bits[DB15:DB4] are reserved. Bit DB10 and Bit DB4 must be set
to 1, but all other bits in this range must be set to 0.
REGISTER INITIALIZATION SEQUENCE
At initial power-up, after the correct application of voltages to
the supply pins, registers must be programmed in sequence. For
fPFD ≤ 75 MHz, use the following sequence:
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
Register 12.
Register 11.
Register 10.
Register 9.
Register 8.
Register 7.
Register 6.
Register 5.
Register 4.
Register 3.
Register 2.
Register 1.
Wait >16 ADC_CLK cycles. For example, if
ADC_CLK = 99.417 kHz, wait 16/99,417 sec = 161 μs.
See the Register 10 section for more information.
14. Register 0.
For fPFD > 75 MHz (initially lock with half fPFD), use the
following sequence:
1. Register 12.
2. Register 11.
3. Register 10.
4. Register 9.
5. Register 8.
6. Register 7.
7. Register 6.
8. Register 5.
9. Register 4 (with the R divider doubled to output half fPFD).
10. Register 3.
11. Register 2 (for halved fPFD).
12. Register 1 (for halved fPFD).
13. Wait >16 ADC_CLK cycles. For example, if
ADC_CLK = 99.417 kHz, wait 16/99417 sec = 161 μs.
See the Register 10 section for more information.
14. Register 0 (for halved fPFD; autocalibration enabled).
15. Register 4 (with the R divider set for desired fPFD).
16. Register 2 (for desired fPFD).
17. Register 1 (for desired fPFD).
18. Register 0 (for desired fPFD; autocalibration disabled).
FREQUENCY UPDATE SEQUENCE
Frequency updates require updating the auxiliary modulator
(MOD2) in Register 2, the fractional value (FRAC1) in Register 1,
and the integer value (INT) in Register 0. It is recommended to
perform a temperature dependent VTUNE calibration by updating
Register 10 first. A counter reset (Bit DB4) is also required in
the frequency update sequence Therefore, for fPFD ≤ 75 MHz,
use the following sequence:
Rev. A | Page 29 of 35
1.
2.
3.
4.
5.
6.
Register 10.
Register 4 (counter reset enabled [DB4 = 1]).
Register 2.
Register 1.
Register 0 (autocalibration disabled [DB21 = 0]).
Register 4 (counter reset disabled [DB4 = 0]).
ADF4355
8.
In this example, divide the 122.88 MHz reference signal by 2 to
generate a fPFD of 61.44 MHz. The desired channel spacing is
200 kHz.
Wait >16 ADC_CLK_DIV cycles. For example, if
ADC_CLK_DIV = 99.417 kHz, wait 16/99417 sec =
161 µs. See the Register 10 section.
Register 0 (autocalibration enabled [DB21 = 1]).
fPFD
PFD
For fPFD > 75 MHz (initially lock with half fPFD), use the
following sequence:
1.
2.
3.
4.
5.
6.
7.
Register 10.
Register 4 (counter reset enabled [DB4 = 1]).
Register 2 (for halved fPFD).
Register 1 (for halved fPFD).
Register 0 (for halved fPFD; autocalibration disabled).
Register 4 (counter reset disabled [DB4 = 0])
Wait >16 ADC_CLK cycles. For example, if
ADC_CLK = 99.417 kHz, wait 16/99417 sec = 161 μs.
See the Register 10 section for more information.
8. Register 0 (for halved fPFD; autocalibration enabled).
9. Register 2 (for desired fPFD).
10. Register 1 (for desired fPFD).
11. Register 0 (for desired fPFD; autocalibration disabled).
The worked example is as follows:
•
•
•
•
•
•
•
N = VCOOUT/fPFD = 4225.6 MHz/61.44 MHz =
68.7760416666666667
INT = int(VCO frequency/fPFD) = 68
FRAC = 0.7760416666666667
MOD1 = 16,777,216
FRAC1 = int(MOD1 × FRAC) = 13019817
Remainder = 0.6666666667 or 2/3
MOD2 = fPFD/GCD(fPFD/fCHSP) = 61.44
MHz/GCD(61.44 MHz/200 kHz) = 1536
FRAC2 = remainder × 1536 = 1024
RF SYNTHESIZER—A WORKED EXAMPLE
From Equation 8,
Use the following equations to program the ADF4355 synthesizer:
where:
RFOUT is the RF frequency output.
INT is the integer division factor.
FRAC1 is the fractionality.
FRAC2 is the auxiliary fractionality.
MOD2 is the auxiliary modulus.
MOD1 is the fixed 24-bit modulus.
RF Divider is the output divider that divides down the VCO
frequency.
fPFD = REFIN × ((1 + D)/(R × (1 + T)))
RFOUT
Figure 43. Loop Closed Before Output Divider
•
(7)
÷2
N
DIVIDER
The frequency change only occurs when writing to Register 0.
FRAC2
FRAC1 +
MOD2 × (fPFD)/RF Divider
RFOUT = INT +
MOD1
VCO
12910-148
7.
Data Sheet
fPFD = (122.88 MHz × (1 + 0)/2) = 61.44 MHz
(9)
From Equation 7,
2112.8 MHz = 61.44 MHz × ((INT + (FRAC1 +
FRAC2/MOD2)/224))/2
(10)
where:
INT = 68
FRAC1 = 13,019,817
FRAC2 = 1024
MOD2 = 1536
RF Divider = 2 (see Equation 7)
REFERENCE DOUBLER AND REFERENCE DIVIDER
(8)
where:
REFIN is the reference frequency input.
D is the RF REFIN doubler bit.
R is the RF reference division factor.
T is the reference divide by 2 bit (0 or 1).
For example, in a universal mobile telecommunication system
(UMTS) where 2112.8 MHz RF frequency output (RFOUT) is
required, a 122.88 MHz reference frequency input (REFIN) is
available. Note that the ADF4355 VCO operates in the frequency
range of 3.4 GHz to 6.8 GHz. Therefore, an RF divider of 2 must
be used (VCO frequency = 4225.6 MHz, RFOUT = VCO frequency/
RF divider = 4225.6 MHz/2 = 2112.8 MHz).
The on-chip reference doubler allows the input reference signal
to be doubled. The doubler is useful for increasing the PFD
comparison frequency. To improve the noise performance of
the system, increase the PFD frequency. Doubling the PFD
frequency usually improves noise performance by 3 dB.
The reference divide by 2 divides the reference signal by 2,
resulting in a 50% duty cycle PFD frequency.
SPURIOUS OPTIMIZATION AND FAST LOCK
Narrow loop bandwidths can filter unwanted spurious signals,
but these bandwidths usually have a long lock time. A wider
loop bandwidth achieves faster lock times but may lead to
increased spurious signals inside the loop bandwidth.
The feedback path is also important. In this example, the VCO
output is fed back before the output divider (see Figure 43).
Rev. A | Page 30 of 35
Data Sheet
ADF4355
OPTIMIZING JITTER
By combining the following two equations:
For lowest jitter applications, use the highest possible PFD
frequency to minimize the contribution of in-band noise from
the PLL. Set the PLL filter bandwidth such that the in-band noise
of the PLL intersects with the open-loop noise of the VCO,
minimizing the contribution of both to the overall noise.
ALC Wait > (50 µs × fPFD)/Timeout
Synthesizer Lock Timeout > (20 µs × fPFD)/Timeout
The following is found:
ALC Wait = 2.5 × Synthesizer Lock Timeout
Maximize ALC Wait (to reduce Timeout to minimize time) so
that ALC Wait = 30 and Synthesizer Lock Timeout = 12.
Use the ADIsimPLL™ design tool for this task.
SPUR MECHANISMS
This section describes the two different spur mechanisms that
arise with a fractional-N synthesizer and how to minimize them
in the ADF4355.
Finally, ALC Wait > (50 µs × fPFD)/Timeout, is rearranged as
Timeout = Ceiling((fPFD × 50 µs)/ALC Wait)
Timeout = Ceiling((61.44 MHz × 50 µs)/30) = 103
Integer Boundary Spurs
Synthesizer Lock Timeout
One mechanism for fractional spur creation is the interactions
between the RF VCO frequency and the reference frequency.
When these frequencies are not integer related (the purpose of a
fractional-N synthesizer), spur sidebands appear on the VCO
output spectrum at an offset frequency that corresponds to the
beat note or the difference in frequency between an integer
multiple of the reference and the VCO frequency. These spurs
are attenuated by the loop filter and are more noticeable on
channels close to integer multiples of the reference where the
difference frequency can be inside the loop bandwidth (thus
the name, integer boundary spurs).
The synthesizer lock timeout ensures that the VCO calibration
DAC, which forces VTUNE, has settled to a steady value for the
band select circuitry.
The timeout and synthesizer lock timeout variables programmed
in Register 9 select the length of time the DAC is allowed to
settle to the final voltage before the VCO calibration process
continues to the next phase, which is VCO band selection. The
PFD frequency is used as the clock for this logic, and the
duration is set by
Timeout × Synthesizer Lock Timeout
PFD Frequency
Reference Spurs
Reference spurs are generally not a problem in fractional-N
synthesizers because the reference offset is far outside the loop
bandwidth. However, any reference feedthrough mechanism
that bypasses the loop may cause a problem. Feedthrough of
low levels of on-chip reference switching noise, through the
prescaler back to the VCO, can result in reference spur levels
as high as −80 dBc.
LOCK TIME
The PLL lock time divides into a number of settings. All of
these are modeled in the ADIsimPLL design tool. Faster lock
times than those detailed in this data sheet are possible; contact
your local Analog Devices, Inc., sales representative for more
information.
Lock Time—A Worked Example
Assuming fPFD = 61.44 MHz,
VCO Band Div = Ceiling(fPFD/2,400,000) = 26
where Ceiling() rounds up to the nearest integer.
The calculated time must be equal to or greater than 20 µs.
VCO Band Selection
Use the PFD frequency again as the clock for the band selection
process. Calculate this value by
PFD/(VCO Band Selection × 16) < 150 kHz
The band selection takes 11 cycles of the previously calculated
value. Calculate the duration by
11 × (VCO Band Selection × 16)/PFD Frequency
Automatic Level Calibration Timeout
Use the automatic level calibration (ALC) function to choose
the correct bias current in the ADF4355 VCO core. Calculate
the time taken by
5 × 11 × ALC Wait × Timeout/PFD Frequency
PLL Low-Pass Filter Settling Time
The time taken for the loop to settle is inversely proportional to
the low-pass filter bandwidth. The settling time is also modeled
in the ADIsimPLL design tool.
The total lock time for changing frequencies is the sum of the
four separate times (synthesizer lock, VCO band selection, ALC
timeout, and PLL settling time) and is all modeled in the
ADIsimPLL design tool.
Rev. A | Page 31 of 35
ADF4355
Data Sheet
APPLICATIONS INFORMATION
DIRECT CONVERSION MODULATOR
The LO ports of the ADL5375 can be driven differentially from
the complementary RFOUTA+/RFOUTA− outputs of the ADF4355.
Differential drive gives better second-order distortion performance
than a single-ended LO driver and eliminates the use of a balun
to convert from a single-ended LO input to the more desirable
differential LO input for the ADL5375.
Direct conversion architectures are increasingly being used to
implement base station transmitters. Figure 44 shows how to
use Analog Devices devices to implement such a system.
The circuit block diagram shows the AD9761 TxDAC+® being
used with the ADL5375. The use of a dual integrated DAC, such
as the AD9761, ensures minimum error contribution (over
temperature) from this portion of the signal chain.
The ADL5375 accepts LO drive levels from −6 dBm to +6 dBm.
The optimum LO power can be software programmed on the
ADF4355, which allows levels from −4 dBm to +5 dBm from
each output.
The local oscillator (LO) is implemented using the ADF4355.
The low-pass filter was designed using the ADIsimPLL design
tool for a PFD of 61.44 MHz and a closed-loop bandwidth of
20 kHz.
51Ω
REFIO
The RF output is designed to drive a 50 Ω load; however, it
must be ac-coupled, as shown in Figure 44. If the I and Q inputs
are driven in quadrature by 2 V p-p signals, the resulting output
power from the ADL5375 modulator is approximately 2 dBm.
51Ω
IOUTA
MODULATED
DIGITAL
DATA
AD9761
LOW-PASS
FILTER
IOUTB
TxDAC
QOUTA
LOW-PASS
FILTER
QOUTB
FSADJ
51Ω
51Ω
2kΩ
FREF IN
FREF IN
VDD
1nF 1nF
100nF
100nF
LOCK
DETECT
25
30
CREG1 MUXOUT
17
10
26
32
5
4
27
6
16
VVCO VP AV DD DVDD AV DD CE PDB RF VRF CREG2
RFOUTB+ 14
1nF 1nF
RFOUTB– 15
28 REF INB
SPI-COMPATIBLE SERIAL BUS
IBBN
VOUT
7.5nH
1 CLK
7.5nH
1nF
2 DATA
RFOUTA+ 11
ADF4355
3 LE
LOIN
1nF
VTUNE 20
4.7kΩ
1500pF
CPGND SDGND AGND AGNDRF AGNDVCO VREGVCO
31
9
13
18
21
10pF
VREF
VBIAS
23
24
19
0.1µF
10pF
33nF
LPF
QUADRATURE
PHASE
SPLITTER
RFOUT
DSOP
3.3kΩ
CPOUT 7
22 RSET
LOIP
LPF
RFOUTA– 12
8
ADL5375
IBBP
29 REF A
IN
QBBN
390pF
QBBP
1kΩ
0.1µF 10pF
0.1µF
Figure 44. Direct Conversion Modulator
Rev. A | Page 32 of 35
12910-138
VVCO
Data Sheet
ADF4355
The bottom of the chip-scale package has a central exposed
thermal pad. The thermal pad on the PCB must be at least as
large as the exposed pad. On the PCB, there must be a minimum
clearance of 0.25 mm between the thermal pad and the inner
edges of the pad pattern. This clearance ensures the avoidance
of shorting.
POWER SUPPLIES
The ADF4355-2 contains four multiband VCOs that cover an
octave range of frequencies. To ensure best performance, it is vital
to connect a low noise regulator, such as the ADM7170, to the
VVCO pin. Connect the same regulator to package pins VVCO,
VREGVCO, and VP.
To improve the thermal performance of the package, use thermal
vias on the PCB thermal pad. If vias are used, incorporate them
into the thermal pad at the 1.2 mm pitch grid. The via diameter
must be between 0.3 mm and 0.33 mm and the via barrel must
be plated with 1 oz. of copper to plug the via.
For the 3.3 V supply pins, use two ADM7170 regulators, one for
the DVDD and AVDD supplies and one for VRF. Figure 45 shows
the recommended connections.
PRINTED CIRCUIT BOARD (PCB) DESIGN
GUIDELINES FOR A CHIP-SCALE PACKAGE
For a microwave PLL and VCO synthesizer, such as the ADF4355,
take care with the board stack-up and layout. Do not consider
using FR4 material because it is too lossy above 3 GHz. Instead,
Rogers 4350, Rogers 4003, or Rogers 3003 dielectric material is
suitable.
The lands on the 32-lead lead frame chip-scale package are
rectangular. The PCB pad for these lands must be 0.1 mm
longer than the package land length and 0.05 mm wider than
the package land width. Center each land on the pad to
maximize the solder joint size.
Take care with the RF output traces to minimize discontinuities
and ensure the best signal integrity. Via placement and grounding
are critical.
VOUT = 3.3V
VIN
CIN
10µF
ON
OFF
EN
VOUT
VOUT
SENSE
ADM7170
SS
COUT
10µF
CSS
1nF
GND
100nF
25
30
CREG1 MUXOUT
17
VOUT = 3.3V
VIN
CIN
10µF
ON
OFF
EN
VOUT
VOUT
SENSE
ADM7170
SS
COUT
10µF
CSS
1nF
VOUT = 5.0V
VIN
CIN
10µF
ON
OFF
EN
VOUT
VOUT
SENSE
ADM7170
SS
FREF IN
1nF 1nF
10
26
4
27
6
32
16
VVCO VP DVDD AVDD CE PDB RF VRF CREG2
29 REF INA
RFOUTB+ 14
1nF 1nF
RFOUTB– 15
28 REF INB
COUT
10µF
VOUT
7.5nH
1 CLK
GND
VIN = 6.0V
FREF IN
SPI-COMPATIBLE SERIAL BUS
VIN = 6.0V
LOCK
DETECT
100nF
7.5nH
1nF
2 DATA
RFOUTA+ 11
ADF4355
3 LE
RFOUTA– 12
1nF
VTUNE 20
3.3kΩ
CPOUT 7
22 RSET
4.7kΩ
AVDD 5
CPGND SDGND AGND AGNDRF AGNDVCO VREGVCO
8
31
9
13
18
21
19
VREF
1500pF
390pF
1kΩ
VBIAS
23
33nF
24
CSS
1nF
10pF
GND
Figure 45. ADF4355 Power Supplies
Rev. A | Page 33 of 35
0.1µF
10pF
0.1µF 10pF
0.1µF
12910-050
VIN = 6.0V
ADF4355
Data Sheet
OUTPUT MATCHING
The low frequency output can simply be ac-coupled to the next
circuit, if desired; however, if higher output power is required,
use a pull-up inductor to increase the output power level.
VRF
7.5nH
50Ω
Figure 46. Optimum Output Stage
12910-051
100pF
RFOUTA+
When differential outputs are not needed, terminate the unused
output or combine it with both outputs using a balun.
For lower frequencies below 2 GHz, it is recommended to use a
100 nH inductor on the RFOUTA+/RFOUTA− pins.
The RFOUTA+/RFOUTA− pins are a differential circuit. Provide
each output with the same (or similar) components where
possible, such as the same shunt inductor value, bypass
capacitor, and termination.
The auxiliary frequency output, RFOUTB+/RFOUTB−, can be
treated the same as the RFOUTA+/RFOUTA− output. If unused,
leave both RFOUTB+/RFOUTB− pins open.
Rev. A | Page 34 of 35
Data Sheet
ADF4355
OUTLINE DIMENSIONS
0.30
0.25
0.18
32
25
1
24
0.50
BSC
*3.75
3.60 SQ
3.55
EXPOSED
PAD
17
TOP VIEW
0.80
0.75
0.70
0.50
0.40
0.30
8
16
0.05 MAX
0.02 NOM
COPLANARITY
0.08
0.20 REF
SEATING
PLANE
PIN 1
INDICATOR
9
BOTTOM VIEW
0.25 MIN
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
*COMPLIANT TO JEDEC STANDARDS MO-220-WHHD-5
WITH THE EXCEPTION OF THE EXPOSED PAD DIMENSION.
08-16-2010-B
PIN 1
INDICATOR
5.10
5.00 SQ
4.90
Figure 47. 32-Lead Lead Frame Chip Scale Package [LFCSP_WQ]
5 mm × 5 mm Body, Very, Very Thin Quad
(CP-32-12)
Dimensions shown in millimeters
ORDERING GUIDE
Model 1
ADF4355BCPZ
ADF4355BCPZ-RL7
EV-ADF4355SD1Z
1
Temperature Range
−40°C to +85°C
−40°C to +85°C
Package Description
32-Lead Lead Frame Chip Scale Package [LFCSP_WQ]
32-Lead Lead Frame Chip Scale Package [LFCSP_WQ]
Evaluation Board
Z = RoHS Compliant Part.
©2015–2016 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D12910-0-3/16(A)
Rev. A | Page 35 of 35
Package Option
CP-32-12
CP-32-12
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