a Mixed Signal DSP Controller ADSP-21991

a Mixed Signal DSP Controller ADSP-21991
a
Mixed Signal DSP Controller
ADSP-21991
KEY FEATURES
ADSP-219x, 16-Bit, Fixed Point DSP Core with up to
160 MIPS Sustained Performance
40K Words of On-Chip RAM, Configured as 32K Words
On-Chip 24-Bit Program RAM and 8K Words On-Chip
16-Bit Data RAM
External Memory Interface
Dedicated Memory DMA Controller for Data/Instruction
Transfer between Internal/External Memory
Programmable PLL and Flexible Clock Generation
Circuitry Enables Full Speed Operation from Low
Speed Input Clocks
IEEE JTAG Standard 1149.1 Test Access Port Supports
On-Chip Emulation and System Debugging
8-Channel, 14-Bit Analog-to-Digital Converter System,
with up to 20 MSPS Sampling Rate (at 160 MHz Core
Clock Rate)
Three Phase 16-Bit Center Based PWM Generation Unit
with 12.5 ns Resolution at 160 MHz Core Clock (CCLK)
Rate
Dedicated 32-Bit Encoder Interface Unit with
Companion Encoder Event Timer
Dual 16-Bit Auxiliary PWM Outputs
16 General-Purpose Flag I/O Pins
Three Programmable 32-Bit Interval Timers
SPI Communications Port with Master or Slave
Operation
Synchronous Serial Communications Port (SPORT)
Capable of Software UART Emulation
Integrated Watchdog Timer
Dedicated Peripheral Interrupt Controller with Software
Priority Control
Multiple Boot Modes
Precision 1.0 V Voltage Reference
FUNCTIONAL BLOCK DIAGRAM
CLOCK
GENERATOR/PLL
JTAG
TEST AND
EMULATION
ADSP-219x
8K ⴛ16
DM RAM
32K ⴛ24
PM RAM
4K ⴛ24
PM ROM
DSP CORE
ADDRESS
I/O
BUS
EXTERNAL
MEMORY
INTERFACE
(EMI)
PM ADDRESS/DATA
DATA
CONTROL
DM ADDRESS/DATA
I/O REGISTERS
SPI
PWM
GENERATION
UNIT
ENCODER
INTERFACE
UNIT
(AND EET)
TIMER 0
AUXILIARY
PWM
UNIT
TIMER 1
FLAG
I/O
TIMER 2
WATCHDOG
TIMER
MEMORY DMA
CONTROLLER
SPORT
INTERRUPT
CONTROLLER
(ICNTL)
ADC
CONTROL
POR
PIPELINE
FLASH ADC
VREF
REV. 0
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© 2003 Analog Devices, Inc. All rights reserved.
ADSP-21991
TIMING SPECIFICATIONS . . . . . . . . . . . . . . . .
Clock In and Clock Out Cycle Timing . . . . . . . . .
Programmable Flags Cycle Timing . . . . . . . . . . .
Timer PWM_OUT Cycle Timing . . . . . . . . . . . .
External Port Write Cycle Timing . . . . . . . . . . . .
External Port Read Cycle Timing . . . . . . . . . . . .
External Port Bus Request/Grant Cycle Timing . .
Serial Port Timing . . . . . . . . . . . . . . . . . . . . . . . .
Serial Peripheral Interface Port—Master Timing .
Serial Peripheral Interface Port—Slave Timing . .
JTAG Test And Emulation Port Timing . . . . . . .
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . .
Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output Disable Time . . . . . . . . . . . . . . . . . . . . . .
Output Enable Time . . . . . . . . . . . . . . . . . . . . . .
Example System Hold Time Calculation . . . . . . .
Pin Configurations . . . . . . . . . . . . . . . . . . . . . . . . .
OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . .
ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . .
KEY FEATURES (continued)
Integrated Power-On-Reset (POR) Generator
Flexible Power Management with Selectable PowerDown and Idle Modes
2.5 V Internal Operation with 3.3 V I/O
Operating Temperature Range of –40ºC to +85ºC
196-Ball Mini-BGA Package
176-Lead LQFP Package
TARGET APPLICATIONS
Industrial Motor Drives
Uninterruptible Power Supplies
Optical Networking Control
Data Acquisition Systems
Test and Measurement Systems
Portable Instrumentation
TABLE OF CONTENTS
GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . 2
DSP Core Architecture . . . . . . . . . . . . . . . . . . . . . . . 3
Memory Architecture . . . . . . . . . . . . . . . . . . . . . . . . 4
Internal (On-Chip) Memory . . . . . . . . . . . . . . . . . . 5
External (Off-Chip) Memory . . . . . . . . . . . . . . . . . 5
External Memory Space . . . . . . . . . . . . . . . . . . . . . 5
I/O Memory Space . . . . . . . . . . . . . . . . . . . . . . . . . 5
Boot Memory Space . . . . . . . . . . . . . . . . . . . . . . . . 6
Bus Request and Bus Grant . . . . . . . . . . . . . . . . . . . . 6
DMA Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
DSP Peripherals Architecture . . . . . . . . . . . . . . . . . . 6
Serial Peripheral Interface (SPI) Port . . . . . . . . . . . . . 7
DSP Serial Port (SPORT) . . . . . . . . . . . . . . . . . . . . . 7
Analog-to-Digital Conversion System . . . . . . . . . . . . 8
Voltage Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
PWM Generation Unit . . . . . . . . . . . . . . . . . . . . . . . 8
Auxiliary PWM Generation Unit . . . . . . . . . . . . . . . . 9
Encoder Interface Unit . . . . . . . . . . . . . . . . . . . . . . . 9
Flag I/O (FIO) Peripheral Unit . . . . . . . . . . . . . . . . 10
Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
General-Purpose Timers . . . . . . . . . . . . . . . . . . . . . 10
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Peripheral Interrupt Controller . . . . . . . . . . . . . . . . 11
Low Power Operation . . . . . . . . . . . . . . . . . . . . . . . 11
Idle Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Power-Down Core Mode . . . . . . . . . . . . . . . . . . . 11
Power-Down Core/Peripherals Mode . . . . . . . . . . 12
Power-Down All Mode . . . . . . . . . . . . . . . . . . . . 12
Clock Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Reset and Power-On Reset (POR) . . . . . . . . . . . . . . 12
Power Supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Booting Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Instruction Set Description . . . . . . . . . . . . . . . . . . . 13
Development Tools . . . . . . . . . . . . . . . . . . . . . . . . . 13
Designing an Emulator-Compatible DSP Board . . . 14
Additional Information . . . . . . . . . . . . . . . . . . . . . . 14
PIN FUNCTION DESCRIPTIONS . . . . . . . . . . . . . 14
SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . 17
ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . 22
ESD SENSITIVITY . . . . . . . . . . . . . . . . . . . . . . . . 22
22
23
24
25
26
27
28
29
32
33
34
35
35
35
35
35
36
41
42
GENERAL DESCRIPTION
The ADSP-21991 is a mixed signal DSP controller based on the
ADSP-219x DSP Core, suitable for a variety of high performance
industrial motor control and signal processing applications that
require the combination of a high performance DSP and the
mixed signal integration of embedded control peripherals such
as analog-to-digital conversion.
The ADSP-21991 integrates the fixed point ADSP-219x family
base architecture with a serial port, an SPI compatible port, a
DMA controller, three programmable timers, general-purpose
Programmable Flag pins, extensive interrupt capabilities, onchip program and data memory spaces, and a complete set of
embedded control peripherals that permits fast motor control
and signal processing in a highly integrated environment.
The ADSP-21991 architecture is code compatible with previous
ADSP-217x based ADMCxxx products. Although the architectures are compatible, the ADSP-21991, with ADSP-219x
architecture, has a number of enhancements over earlier architectures. The enhancements to computational units, data address
generators, and program sequencer make the ADSP-21991 more
flexible and easier to program than the previous ADSP-21xx
embedded DSPs.
Indirect addressing options provide addressing flexibility—
premodify with no update, pre- and post-modify by an immediate
8-bit, twos complement value and base address registers for easier
implementation of circular buffering.
The ADSP-21991 integrates 40K words of on-chip memory configured as 32K words (24-bit) of program RAM, and 8K words
(16-bit) of data RAM.
Fabricated in a high speed, low power, CMOS process, the
ADSP-21991 operates with a 6.25 ns instruction cycle time for
a 160 MHz CCLK and with a 6.67 ns instruction cycle time for
a 150 MHz CCLK. All instructions, except two multiword
instructions, execute in a single DSP cycle.
–2–
REV. 0
ADSP-21991
The flexible architecture and comprehensive instruction set of
the ADSP-21991 support multiple operations in parallel. For
example, in one processor cycle, the ADSP-21991 can:
The clock generator module of the ADSP-21991 includes clock
control logic that allows the user to select and change the main
clock frequency. The module generates two output clocks: the
DSP core clock, CCLK; and the peripheral clock, HCLK.
CCLK can sustain clock values of up to 160 MHz, while HCLK
can be equal to CCLK or CCLK/2 for values up to a maximum
80 MHz peripheral clock at the 160 MHz CCLK rate.
• Generate an address for the next instruction fetch
• Fetch the next instruction
• Perform one or two data moves
• Update one or two data address pointers
The ADSP-21991 instruction set provides flexible data moves
and multifunction (one or two data moves with a computation)
instructions. Every single word instruction can be executed in a
single processor cycle. The ADSP-21991 assembly language uses
an algebraic syntax for ease of coding and readability. A comprehensive set of development tools supports program development.
• Perform a computational operation
These operations take place while the processor continues to:
• Receive and transmit data through the serial port
• Receive or transmit data over the SPI port
• Access external memory through the external memory
interface
The block diagram Figure 1 shows the architecture of the
embedded ADSP-219x core. It contains three independent computational units: the ALU, the multiplier/accumulator (MAC),
and the shifter. The computational units process 16-bit data from
the register file and have provisions to support multiprecision
computations. The ALU performs a standard set of arithmetic
and logic operations; division primitives are also supported. The
MAC performs single cycle multiply, multiply/add, and multiply/subtract operations. The MAC has two 40-bit accumulators,
which help with overflow. The shifter performs logical and arithmetic shifts, normalization, denormalization, and derive
exponent operations. The shifter can be used to efficiently
implement numeric format control, including multiword and
block floating point representations.
• Decrement the timers
• Operate the embedded control peripherals (ADC, PWM,
EIU, etc.)
DSP Core Architecture
• 6.25 ns instruction cycle time (internal), for up to
160 MIPS sustained performance (6.67 ns instruction
cycle time for 150 MIPS sustained performance)
• ADSP-218x family code compatible with the same easy
to use algebraic syntax
• Single cycle instruction execution
• Up to 1M words of addressable memory space with
twenty four bits of addressing width
Register usage rules influence placement of input and results
within the computational units. For most operations, the data
registers of the computational units act as a data register file,
permitting any input or result register to provide input to any unit
for a computation. For feedback operations, the computational
units let the output (result) of any unit be input to any unit on
the next cycle. For conditional or multifunction instructions,
there are restrictions on which data registers may provide inputs
or receive results from each computational unit. For more information, see the ADSP-219x DSP Instruction Set Reference.
• Dual purpose program memory for both instruction and
data storage
• Fully transparent instruction cache allows dual operand
fetches in every instruction cycle
• Unified memory space permits flexible address generation, using two independent DAG units
• Independent ALU, multiplier/accumulator, and barrel
shifter computational units with dual 40-bit accumulators
A powerful program sequencer controls the flow of instruction
execution. The sequencer supports conditional jumps, subroutine calls, and low interrupt overhead. With internal loop
counters and loop stacks, the ADSP-21991 executes looped code
with zero overhead; no explicit jump instructions are required to
maintain loops.
• Single cycle context switch between two sets of computational and DAG registers
• Parallel execution of computation and memory
instructions
• Pipelined architecture supports efficient code execution
at speeds up to 160 MIPS
Two data address generators (DAGs) provide addresses for
simultaneous dual operand fetches (from data memory and
program memory). Each DAG maintains and updates four 16-bit
address pointers. Whenever the pointer is used to access data
(indirect addressing), it is pre- or post-modified by the value of
one of four possible modify registers. A length value and base
address may be associated with each pointer to implement
automatic modulo addressing for circular buffers. Page registers
in the DAGs allow circular addressing within 64K word boundaries of each of the 256 memory pages, but these buffers may not
cross page boundaries. Secondary registers duplicate all the
primary registers in the DAGs; switching between primary and
secondary registers provides a fast context switch.
• Register file computations with all nonconditional, nonparallel computational instructions
• Powerful program sequencer provides zero overhead
looping and conditional instruction execution
• Architectural enhancements for compiled C code
efficiency
• Architecture enhancements beyond ADSP-218x family
are supported with instruction set extensions for added
registers, ports, and peripherals.
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–3–
ADSP-21991
DAG1
DAG2
4 ⴛ 4 ⴛ 16 4 ⴛ 4 ⴛ 16
PROGRAM
SEQUENCER
BLOCK2
CACHE
64 ⴛ 24-BIT
BLOCK3
DATA
ADDRESS 24 BIT
DATA
ADDRESS 24 BIT
ADDRESS 16 BIT
DATA
DATA
ADDRESS 16 BIT
ADSP-219x DSP CORE
BLOCK0
BLOCK1
INTERNAL MEMORY
FOUR INDEPENDENT BLOCKS
JTAG
TEST AND
EMULATION
6
EXTERNAL PORT
PM ADDRESS BUS
I/O ADDRESS 18
24
ADDR BUS
MUX
DM ADDRESS BUS 24
DMA CONNECT
DATA
REGISTER
FILE
MULT
DATA BUS
MUX
DMA DATA 24
PX
PM DATA BUS
20
DMA ADDRESS 24
24
16
DM DATA BUS 16
I/O DATA
INPUT
REGISTERS
RESULT
REGISTERS
16 ⴛ 16-BIT
16
I/O PROCESSOR
I/O REGISTERS
(MEMORY-MAPPED)
BARREL
SHIFTER
EMBEDDED
CONTROL
PERIPHERALS
AND
COMMUNICATIONS
PORTS
CONTROL
STATUS
BUFFERS
ALU
DMA CONTROLLER
SYSTEM INTERRUPT
CONTROLLER
PROGRAMMABLE
FLAGS (16)
TIMERS
(3)
3
Figure 1. Block Diagram
Efficient data transfer in the core is achieved with the use of
internal buses:
Memory Architecture
The ADSP-21991 provides 40K words of on-chip SRAM
memory. This memory is divided into three blocks: two
16K × 24-bit blocks (blocks 0 and 1) and one 8K × 16-bit block
(block 2). In addition, the ADSP-21991 provides a 4K × 24-bit
block of program memory boot ROM (that is reserved by ADI
for boot load routines). The memory map of the ADSP-21991
is illustrated in Figure 2.
• Program Memory Address (PMA) Bus
• Program Memory Data (PMD) Bus
• Data Memory Address (DMA) Bus
• Data Memory Data (DMD) Bus
• Direct Memory Access Address Bus
As shown in Figure 2, the three internal memory RAM blocks
reside in memory page 0. The entire DSP memory map consists
of 256 pages (pages 0 to 255), and each page is 64K words long.
External memory space consists of four memory banks
(banks3–0) and supports a wide variety of memory devices. Each
bank is selectable using unique memory select lines (MS3–0) and
has configurable page boundaries, wait states, and wait state
modes. The 4K words of on-chip boot ROM populates the top
of page 255, while the remaining 254 pages are addressable offchip. I/O memory pages differ from external memory in that they
are 1K word long, and the external I/O pages have their own select
pin (IOMS). Pages 31–0 of I/O memory space reside on-chip and
• Direct Memory Access Data Bus
The two address buses (PMA and DMA) share a single external
address bus, allowing memory to be expanded off-chip, and the
two data buses (PMD and DMD) share a single external data
bus. Boot memory space and I/O memory space also share the
external buses.
Program memory can store both instructions and data, permitting the ADSP-21991 to fetch two operands in a single cycle, one
from program memory and one from data memory. The DSP
dual memory buses also let the embedded ADSP-219x core fetch
an operand from data memory and the next instruction from
program memory in a single cycle.
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ADSP-21991
contain the configuration registers for the peripherals. Both the
ADSP-219x core and DMA capable peripherals can access the
entire memory map of the DSP.
calls, and loops on the 24-bit program counter (PC). In
direct addressing instructions (two word instructions),
the instruction provides an immediate 24-bit address
value. The PC allows linear addressing of the full 24-bit
address range.
• For indirect jumps and calls that use a 16-bit DAG
address register for part of the branch address, the
Program Sequencer relies on an 8-bit Indirect Jump page
(IJPG) register to supply the most significant eight
address bits. Before a cross page jump or call, the program
must set the program sequencer IJPG register to the
appropriate memory page.
0x00 0000
0x00 3FFF
0x00 4000
0x00 7FFF
0x00 8000
0x00 9FFF
0x00 A000
BLOCK 0: 16K ⴛ 24-BIT PM RAM
BLOCK 1: 16K ⴛ 24-BIT PM RAM
BLOCK 2: 8K ⴛ 16-BIT DM RAM
PAGE 0 (64K) ON-CHIP
(0 WAIT STATE)
RESERVED (24K)
0x00 FFFF
0x01 0000
EXTERNAL MEMORY
(4M–64K)
PAGES 1 TO 63 BANK 0
(OFF-CHIP) MS0
The ADSP-21991 has 4K word of on-chip ROM that holds boot
routines. The DSP starts executing instructions from the on-chip
boot ROM, which starts the boot process. See Booting Modes
on Page 13. The on-chip boot ROM is located on Page 255 in
the DSP memory space map, starting at address 0xFF0000.
0x40 0000
EXTERNAL MEMORY (4M)
PAGES 64 TO 127 BANK 1
(OFF-CHIP) MS1
EXTERNAL MEMORY (4M)
PAGES 128 TO 191 BANK 2
(OFF-CHIP) MS2
EXTERNAL MEMORY
(4M–64K)
PAGES 192 TO 254 BANK 3
(OFF-CHIP) MS3
0x80 0000
External (Off-Chip) Memory
0xC0 0000
0xFF 0000
0xFF 0FFF
0xFF 1000
0xFF FFFF
BLOCK 3: 4K ⴛ 24-BIT
PM ROM
UNUSED ON-CHIP
MEMORY (60K)
Each of the off-chip memory spaces of the ADSP-21991 has a
separate control register, so applications can configure unique
access parameters for each space. The access parameters include
read and write wait counts, wait state completion mode, I/O clock
divide ratio, write hold time extension, strobe polarity, and data
bus width. The core clock and peripheral clock ratios influence
the external memory access strobe widths. See Clock Signals on
Page 12. The off-chip memory spaces are:
PAGE 255
(INCLUDES ON-CHIP BOOT ROM)
Figure 2. Core Memory Map at Reset
• External memory space (MS3–0 pins)
NOTE: The physical external memory addresses are limited by
20 address lines, and are determined by the external data width
and packing of the external memory space. The Strobe signals
(MS3-0) can be programmed to allow the user to change starting
page addresses at run time.
• I/O memory space (IOMS pin)
• Boot memory space (BMS pin)
All of these off-chip memory spaces are accessible through the
External Port, which can be configured for 8-bit or 16-bit data
widths.
Internal (On-Chip) Memory
The unified program and data memory space of the ADSP-21991
consists of 16M locations that are accessible through two 24-bit
address buses, the PMA, and DMA buses. The DSP uses slightly
different mechanisms to generate a 24-bit address for each bus.
The DSP has three functions that support access to the full
memory map.
External Memory Space
External memory space consists of four memory banks. These
banks can contain a configurable number of 64K word pages. At
reset, the page boundaries for external memory have Bank0 containing pages 1 to 63, Bank1 containing pages 64 to 127, Bank2
containing pages 128 to 191, and Bank3 containing pages 192 to
254. The MS3-0 memory bank pins select Banks 3-0, respectively. Both the ADSP-219x core and DMA capable peripherals
can access the DSP external memory space.
• The DAGs generate 24-bit addresses for data fetches from
the entire DSP memory address range. Because DAG
index (address) registers are 16 bits wide and hold the
lower 16 bits of the address, each of the DAGs has its own
8-bit page register (DMPGx) to hold the most significant
eight address bits. Before a DAG generates an address,
the program must set the DAG DMPGx register to the
appropriate memory page. The DMPG1 register is also
used as a page register when accessing external memory.
The program must set DMPG1 accordingly, when
accessing data variables in external memory. A “C”
program macro is provided for setting this register.
All accesses to external memory are managed by the External
Memory Interface Unit (EMI).
I/O Memory Space
The ADSP-21991 supports an additional external memory
called I/O memory space. The IO space consists of 256 pages,
each containing 1024 addresses. This space is designed to
support simple connections to peripherals (such as data converters and external registers) or to bus interface ASIC data registers.
The first 32K addresses (IO pages 0 to 31) are reserved for
on-chip peripherals. The upper 224K addresses (IO pages 32 to
• The program sequencer generates the addresses for
instruction fetches. For relative addressing instructions,
the program sequencer bases addresses for relative jumps,
REV. 0
–5–
ADSP-21991
255) are available for external peripheral devices. External I/O
pages have their own select pin (IOMS). The DSP instruction
set provides instructions for accessing I/O space.
two accesses. If an instruction requires an external memory read
and an external memory write access, the bus may be granted
between the two accesses. The external memory interface can be
configured so that the core will have exclusive use of the interface.
DMA and Bus Requests will be granted. When the external
device releases BR, the DSP releases BG and continues program
execution from the point at which it stopped.
0x00::0x000
ON-CHIP
PERIPHERALS
16-BITS
PAGES 0 TO 31
The bus request feature operates at all times, even while the DSP
is booting and RESET is active.
1024 WORDS/PAGE
2 PERIPHERALS/PAGE
0x1F::0x3FF
0x20::0x000
OFF-CHIP
PERIPHERALS
16-BITS
The ADSP-21991 asserts the BGH pin when it is ready to start
another external port access, but is held off because the bus was
previously granted. This mechanism can be extended to define
more complex arbitration protocols for implementing more
elaborate multimaster systems.
PAGES 32 TO 255
1024 WORDS/PAGE
DMA Controller
The ADSP-21991 has a DMA controller that supports
automated data transfers with minimal overhead for the DSP
core. Cycle stealing DMA transfers can occur between the
ADSP-21991 internal memory and any of its DMA capable
peripherals. Additionally, DMA transfers can be accomplished
between any of the DMA capable peripherals and external
devices connected to the external memory interface. DMA
capable peripherals include the SPORT and SPI ports, and ADC
Control module. Each individual DMA capable peripheral has a
dedicated DMA channel. To describe each DMA sequence, the
DMA controller uses a set of parameters—called a DMA descriptor. When successive DMA sequences are needed, these DMA
descriptors can be linked or chained together, so the completion
of one DMA sequence auto initiates and starts the next sequence.
DMA sequences do not contend for bus access with the DSP
core, instead DMAs “steal” cycles to access memory.
0xFF::0x3FF
Figure 3. I/O Memory Map
Boot Memory Space
Boot memory space consists of one off-chip bank with 254 pages.
The BMS memory bank pin selects boot memory space. Both
the ADSP-219x core and DMA capable peripherals can access
the off-chip boot memory space of the DSP. After reset, the DSP
always starts executing instructions from the on-chip boot ROM.
0x01 0000
OFF-CHIP
BOOT MEMORY
16-BITS
PAGES 1 TO 254
All DMA transfers use the DMA bus shown in Figure 1 on
Page 4. Because all of the peripherals use the same bus, arbitration for DMA bus access is needed. The arbitration for DMA bus
access appears in Table 1.
64K WORDS/PAGE
0xFE 0000
Figure 4. Boot Memory Map
Table 1. I/O Bus Arbitration Priority
Bus Request and Bus Grant
DMA Bus Master
Arbitration Priority
The ADSP-21991 can relinquish control of the data and address
buses to an external device. When the external device requires
access to the bus, it asserts the bus request (BR) signal. The (BR)
signal is arbitrated with core and peripheral requests. External
Bus requests have the lowest priority. If no other internal request
is pending, the external bus request will be granted. Due to synchronizer and arbitration delays, bus grants will be provided with
a minimum of three peripheral clock delays. The ADSP-21991
will respond to the bus grant by:
SPORT Receive DMA
SPORT Transmit DMA
ADC Control DMA
SPI Receive/Transmit DMA
Memory DMA
0—Highest
1
2
3
4—Lowest
DSP Peripherals Architecture
The ADSP-21991 contains a number of special purpose,
embedded control peripherals, which can be seen in the Functional Block Diagram on Page 1. The ADSP-21991 contains a
high performance, 8-channel, 14-bit ADC system with dual
channel simultaneous sampling ability across four pairs of inputs.
An internal precision voltage reference is also available as part of
the ADC system. In addition, a 3-phase, 16-bit, center based
PWM generation unit can be used to produce high accuracy
PWM signals with minimal processor overhead. The ADSP21991 also contains a flexible incremental encoder interface unit
• Three-stating the data and address buses and the MS3–0,
BMS, IOMS, RD, and WR output drivers.
• Asserting the bus grant (BG) signal.
The ADSP-21991 will halt program execution if the bus is
granted to an external device and an instruction fetch or data
read/write request is made to external general-purpose or peripheral memory spaces. If an instruction requires two external
memory read accesses, the bus will not be granted between the
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ADSP-21991
for position sensor feedback; two adjustable frequency auxiliary
PWM outputs, 16 lines of digital I/O; a 16-bit watchdog timer;
three general-purpose timers, and an interrupt controller that
manages all peripheral interrupts. Finally, the ADSP-21991
contains an integrated power-on-reset (POR) circuit that can be
used to generate the required reset signal for device power-on.
During transfers, the SPI port simultaneously transmits and
receives by serially shifting data in and out on the serial data line.
The serial clock line synchronizes the shifting and sampling of
data on the serial data line.
The ADSP-21991 has an external memory interface that is
shared by the DSP core, the DMA controller, and DMA capable
peripherals, which include the ADC, SPORT, and SPI communication ports. The external port consists of a 16-bit data bus, a
20-bit address bus, and control signals. The data bus is configurable to provide an 8- or 16-bit interface to external memory.
Support for word packing lets the DSP access 16- or 24-bit words
from external memory regardless of the external data bus width.
1. Enables and configures the SPI port operation (data size,
and transfer format).
In master mode, the DSP core performs the following sequence
to set up and initiate SPI transfers:
2. Selects the target SPI slave with the SPISELx output pin
(reconfigured Programmable Flag pin).
3. Defines one or more DMA descriptors in Page 0 of I/O
memory space (optional in DMA mode only).
4. Enables the SPI DMA engine and specifies transfer
direction (optional in DMA mode only).
The memory DMA controller lets the ADSP-21991 move data
and instructions from between memory spaces: internal-toexternal, internal-to-internal, and external-to- external. On-chip
peripherals can also use this controller for DMA transfers.
5. In non DMA mode only, reads or writes the SPI port
receive or transmit data buffer.
The SCK line generates the programmed clock pulses for simultaneously shifting data out on MOSI and shifting data in on
MISO. In DMA mode only, transfers continue until the SPI
DMA word count transitions from 1 to 0.
The embedded ADSP-219x core can respond to up to seventeen
interrupts at any given time: three internal (stack, emulator
kernel, and power-down), two external (emulator and reset), and
twelve user defined (peripherals) interrupts. Programmers assign
each of the 32 peripheral interrupt requests to one of the 12 user
defined interrupts. These assignments determine the priority of
each peripheral for interrupt service.
In slave mode, the DSP core performs the following sequence to
set up the SPI port to receive data from a master transmitter:
1. Enables and configures the SPI slave port to match the
operation parameters set up on the master (data size and
transfer format) SPI transmitter.
The following sections provide a functional overview of the
ADSP-21991 peripherals.
2. Defines and generates a receive DMA descriptor in
Page 0 of memory space to interrupt at the end of the
data transfer (optional in DMA mode only).
Serial Peripheral Interface (SPI) Port
The Serial Peripheral Interface (SPI) Port provides functionality
for a generic configurable serial port interface based on the SPI
standard, which enables the DSP to communicate with multiple
SPI compatible devices. Key features of the SPI port are:
3. Enables the SPI DMA engine for a receive access
(optional in DMA mode only).
4. Starts receiving the data on the appropriate SCK edges
after receiving an SPI chip select on the SPISS input pin
(reconfigured Programmable Flag pin) from a master
• Interface to host microcontroller or serial EEPROM
• Master or slave operation (3-wire interface MISO, MOSI,
SCK)
In DMA mode only, reception continues until the SPI DMA
word count transitions from 1 to 0. The DSP core could
continue, by queuing up the next DMA descriptor.
• Data rates to HCLKⴜ4 (16-bit baud rate selector)
• 8- or 16-bit transfer
A slave mode transmit operation is similar, except the DSP core
specifies the data buffer in memory space from which to transmit
data, generates and relinquishes control of the transmit DMA
descriptor, and begins filling the SPI port data buffer. If the SPI
controller is not ready on time to transmit, it can transmit a “zero”
word.
• Programmable clock phase and polarity
• Broadcast Mode – 1 master, multiple slaves
• DMA capability and dedicated interrupts
• PF0 can be used as slave select input line
• PF7–1 can be used as external slave select output
DSP Serial Port (SPORT)
SPI is a 3 wire interface consisting of 2 data pins (MOSI and
MISO), one clock pin (SCK), and a single Slave Select input
(SPISS) that is multiplexed with the PF0 Flag IO line and seven
Slave Select outputs (SPISEL1 to SPISEL7) that are multiplexed
with the PF1 to PF7 Flag IO lines. The SPISS input is used to
select the ADSP-21991 as a slave to an external master. The
SPISEL1 to SPISEL7 outputs can be used by the ADSP-21991
(acting as a master) to select/enable up to seven external slaves
in an multi device SPI configuration. In a multimaster or a multidevice configuration, all MOSI pins are tied together, all MISO
pins are tied together, and all SCK pins are tied together.
REV. 0
The ADSP-21991 incorporates a complete synchronous serial
port (SPORT) for serial and multiprocessor communications.
The SPORT supports the following features:
• Bidirectional: the SPORT has independent transmit and
receive sections.
• Double buffered: the SPORT section (both receive and
transmit) has a data register for transferring data words
to and from other parts of the processor and a register for
shifting data in or out. The double buffering provides
additional time to service the SPORT.
–7–
ADSP-21991
• Clocking: the SPORT can use an external serial clock or
generate its own in a wide range of frequencies down to
0 Hz.
• All 8 inputs converted in approximately 725 ns (at
20 MSPS).
• Word length: each SPORT section supports serial data
word lengths from three to sixteen bits that can be transferred either MSB first or LSB first.
• Multiple convert start sources.
• 2.0 V peak-to-peak input voltage range.
• Internal or external Voltage Reference.
• Out of range detection.
• Framing: each SPORT section (receive and transmit) can
operate with or without frame synchronization signals for
each data-word; with internally generated or externally
generated frame signals; with active high or active low
frame signals; with either of two pulsewidths and frame
signal timing.
• DMA capable transfers from ADC to memory.
The ADC system is based on a pipeline flash converter core, and
contains dual input sample-and-hold amplifiers so that simultaneous sampling of two input signals is supported. The ADC
system provides an analog input voltage range of 2.0 Vp-p and
provides 14-bit performance with a clock rate of up to HCLKⴜ4.
The ADC system can be programmed to operate at a clock rate
that is programmable from HCLK⁄4 to HCLK⁄30, to a maximum
of 20 MHz (at 160 MHz CCLK rate).
• Companding in hardware: each SPORT section can
perform A law and µ law companding according to
CCITT recommendation G.711.
• Direct Memory Access with single cycle overhead: using
the built-in DMA master, the SPORT can automatically
receive and/or transmit multiple memory buffers of data
with an overhead of only one DSP cycle per data-word.
The on-chip DSP via a linked list of memory space
resident DMA descriptor blocks can configure transfers
between the SPORT and memory space. This chained list
can be dynamically allocated and updated.
The ADC input structure supports 8 independent analog inputs;
four of which are multiplexed into one sample-and-hold amplifier
(A_SHA) and 4 of which are multiplexed into the other sampleand-hold amplifier (B_SHA).
At the 20 MHz sampling rate, the first data value is valid approximately 375 ns after the Convert Start command. All 8 channels
are converted in approximately 725 ns.
• Interrupts: each SPORT section (receive and transmit)
generates an interrupt upon completing a data-word
transfer, or after transferring an entire buffer or buffers if
DMA is used.
The core of the ADSP-21991 provides 14-bit data such that the
stored data values in the ADC data registers are 14 bits wide.
Voltage Reference
• Multichannel capability: The SPORT can receive and
transmit data selectively from channels of a serial bit
stream that is time division multiplexed into up to 128
channels. This is especially useful for T1 interfaces or as
a network communication scheme for multiple processors. The SPORTs also support T1 and E1 carrier
systems.
The ADSP-21991 contains an onboard band gap reference that
can be used to provide a precise 1.0 V output for use by the A/D
system and externally on the VREF pin for biasing and level
shifting functions. Additionally, the ADSP-21991 may be configured to operate with an external reference applied to the VREF
pin, if required.
• Each SPORT channel (Tx and Rx) supports a DMA
buffer of up to eight, 16-bit transfers.
Key features of the 3-phase PWM generation unit are:
PWM Generation Unit
• 16-bit, center based PWM generation unit
• The SPORT operates at a frequency of up to one-half the
clock frequency of the HCLK
• Programmable PWM pulsewidth, with resolutions to
12.5 ns (at 80 MHz HCLK Rate)
• The SPORT is capable of UART software emulation.
• Single/double update modes
Analog-to-Digital Conversion System
• Programmable dead time and switching frequency
The ADSP-21991 contains a fast, high accuracy, multiple input
analog-to-digital conversion system with simultaneous sampling
capabilities. This A/D conversion system permits the fast,
accurate conversion of analog signals needed in high performance
embedded systems. Key features of the ADC system are:
• Twos complement implementation permits smooth transition into full ON and full OFF states
• Possibility to synchronize the PWM generation to an
external synchronization
• Special provisions for BDCM Operation (crossover and
output enable functions)
• 14-bit Pipeline (6-Stage Pipeline) Flash Analog-toDigital Converter.
• Wide variety of special switched reluctance (SR)
operating modes
• 8 dedicated analog inputs.
• Dual channel simultaneous sampling capability.
• Output polarity and clock gating control
• Programmable ADC clock rate to maximum of
HCLKⴜ4.
• Dedicated asynchronous PWM shutdown signal
• Multiple shutdown sources, independently for each unit
• First channel ADC data valid approximately 375 ns after
CONVST (at 20 MSPS).
–8–
REV. 0
ADSP-21991
The ADSP-21991 integrates a flexible and programmable, 3phase PWM waveform generator that can be programmed to
generate the required switching patterns to drive a 3-phase
voltage source inverter for ac induction (ACIM) or permanent
magnet synchronous (PMSM) motor control. In addition, the
PWM block contains special functions that considerably simplify
the generation of the required PWM switching patterns for
control of the electronically commutated motor (ECM) or
brushless dc motor (BDCM). Tying a dedicated pin, PWMSR,
to GND, enables a special mode, for switched reluctance motors
(SRM).
Encoder Interface Unit
The six PWM output signals consist of three high side drive pins
(AH, BH, and CH) and three low side drive signals pins (AL,
BL, and CL). The polarity of the generated PWM signals may
be set via hardware by the PWMPOL input pin, so that either
active HI or active LO PWM patterns can be produced.
• Status of A/B signals latched with reading of EIU count
value.
The ADSP-21991 incorporates a powerful encoder interface
block to incremental shaft encoders that are often used for
position feedback in high performance motion control systems.
• Quadrature rates to 53 MHz (at 80 MHz HCLK rate).
• Programmable filtering of all encoder input signals
• 32-bit encoder counter
• Variety of hardware and software reset modes
• Two registration inputs to latch EIU count value with
corresponding registration interrupt
• Alternative frequency and direction mode
• Single north marker mode
• Count error monitor function with dedicated error
interrupt
The switching frequency of the generated PWM patterns is programmable using the 16-bit PWMTM register. The PWM
generator is capable of operating in two distinct modes, single
update mode or double update mode. In single update mode the
duty cycle values are programmable only once per PWM period,
so that the resultant PWM patterns are symmetrical about the
midpoint of the PWM period. In the double update mode, a
second updating of the PWM registers is implemented at the
midpoint of the PWM period. In this mode, it is possible to
produce asymmetrical PWM patterns that produce lower
harmonic distortion in 3-phase PWM inverters.
• Dedicated 16-bit loop timer with dedicated interrupt
• Companion encoder event (1⁄T) timer unit.
The encoder interface unit (EIU) includes a 32-bit quadrature
up/down counter, programmable input noise filtering of the
encoder input signals and the zero markers, and has four
dedicated chip pins. The quadrature encoder signals are applied
at the EIA and EIB pins. Alternatively, a frequency and direction
set of inputs may be applied to the EIA and EIB pins. In addition,
two north marker/strobe inputs are provided on pins EIZ and
EIS. These inputs may be used to latch the contents of the
encoder quadrature counter into dedicated registers,
EIZLATCH and EISLATCH, on the occurrence of external
events at the EIZ and EIS pins. These events may be programmed
to be either rising edge only (latch event) or rising edge if the
encoder is moving in the forward direction and falling edge if the
encoder is moving in the reverse direction (software latched north
marker functionality).
Auxiliary PWM Generation Unit
Key features of the auxiliary PWM generation unit are:
• 16-bit, programmable frequency, programmable duty
cycle PWM outputs
• Independent or offset operating modes
• Double buffered control of duty cycle and period registers
• Separate auxiliary PWM synchronization signal and associated interrupt (can be used to trigger ADC Convert
Start).
The encoder interface unit incorporates programmable noise
filtering on the four encoder inputs to prevent spurious noise
pulses from adversely affecting the operation of the quadrature
counter. The encoder interface unit operates at a clock frequency
equal to the HCLK rate. The encoder interface unit operates
correctly with encoder signals at frequencies of up to 13.25 MHz
at the 80 MHz HCLK rate, corresponding to a maximum
quadrature frequency of 53 MHz (assuming an ideal quadrature
relationship between the input EIA and EIB signals).
• Separate auxiliary PWM shutdown signal (AUXTRIP).
The ADSP-21991 integrates a 2-channel, 16-bit, auxiliary PWM
output unit that can be programmed with variable frequency,
variable duty cycle values and may operate in two different
modes, independent mode or offset mode. In independent mode,
the two auxiliary PWM generators are completely independent
and separate switching frequencies and duty cycles may be programmed for each auxiliary PWM output. In offset mode the
switching frequency of the two signals on the AUX0 and AUX1
pins is identical. Bit 4 of the AUXCTRL register places the
auxiliary PWM channel pair in independent or offset mode.
The EIU may be programmed to use the north marker on EIZ
to reset the quadrature encoder in hardware, if required.
Alternatively, the north marker can be ignored, and the encoder
quadrature counter is reset according to the contents of a
maximum count register, EIUMAXCNT. There is also a “single
north marker” mode available in which the encoder quadrature
counter is reset only on the first north marker pulse.
The Auxiliary PWM generation unit provides two chip output
pins, AUX0 and AUX1 (on which the switching signals appear),
and one chip input pin, AUXTRIP, which can be used to shut
down the switching signals—for example in a fault condition.
REV. 0
–9–
ADSP-21991
The encoder interface unit can also be made to implement some
error checking functions. If an encoder count error is detected
(due to a disconnected encoder line, for example), a status bit in
the EIUSTAT register is set, and an EIU count error interrupt is
generated.
General-Purpose Timers
The ADSP-21991 contains a general-purpose timer unit that
contains three identical 32-bit timers. The three programmable
interval timers (Timer0, Timer1, and Timer2) generate periodic
interrupts. Each timer can be independently set to operate in one
of three modes:
The encoder interface unit of the ADSP-21991 contains a 16-bit
loop timer that consists of a timer register, period register and
scale register so that it can be programmed to time out and reload
at appropriate intervals. When this loop timer times out, an EIU
loop timer timeout interrupt is generated. This interrupt could
be used to control the timing of speed and position control loops
in high performance drives.
• Pulse Waveform Generation (PWM_OUT) mode
• Pulsewidth Count/Capture (WDTH_CAP) mode
• External Event Watchdog (EXT_CLK) mode
The encoder interface unit also includes a high performance
encoder event timer (EET) block that permits the accurate timing
of successive events of the encoder inputs. The EET can be programmed to time the duration between up to 255 encoder pulses
and can be used to enhance velocity estimation, particularly at
low speeds of rotation.
Flag I/O (FIO) Peripheral Unit
The FIO module is a generic parallel I/O interface that supports
sixteen bidirectional multifunction flags or general-purpose
digital I/O signals (PF15–0).
All sixteen FLAG bits can be individually configured as an input
or output based on the content of the direction (DIR) register,
and can also be used as an interrupt source for one of two FIO
interrupts. When configured as input, the input signal can be
programmed to set the FLAG on either a level (level sensitive
input/interrupt) or an edge (edge sensitive input/interrupt).
Each Timer has one bidirectional chip pin, TMR2-0. For each
timer, the associated pin is configured as an output pin in
PWM_OUT Mode and as an input pin in WDTH_CAP and
EXT_CLK Modes.
Interrupts
The interrupt controller lets the DSP respond to 17 interrupts
with minimum overhead. The DSP core implements an interrupt
priority scheme as shown in Table 2. Applications can use the
unassigned slots for software and peripheral interrupts. The
Peripheral Interrupt Controller is used to assign the various
peripheral interrupts to the 12 user assignable interrupts of the
DSP core.
Table 2. Interrupt Priorities/Addresses
Interrupt
Emulator (NMI)
—Highest Priority
Reset (NMI)
Power-Down (NMI)
Loop and PC Stack
Emulation Kernel
User Assigned Interrupt
(USR0)
User Assigned Interrupt
(USR1)
User Assigned Interrupt
(USR2)
User Assigned Interrupt
(USR3)
User Assigned Interrupt
(USR4)
User Assigned Interrupt
(USR5)
User Assigned Interrupt
(USR6)
User Assigned Interrupt
(USR7)
User Assigned Interrupt
(USR8)
The FIO module can also be used to generate an asynchronous
unregistered wake-up signal FIO_WAKEUP for DSP core wake
up after power-down.
The FIO Lines, PF7–1 can also be configured as external slave
select outputs for the SPI communications port, while PF0 can
be configured to act as a slave select input.
The FIO Lines can be configured to act as a PWM shutdown
source for the 3-phase PWM generation unit of the
ADSP-21991.
Watchdog Timer
The ADSP-21991 integrates a watchdog timer that can be used
as a protection mechanism against unintentional software events.
It can be used to cause a complete DSP and peripheral reset in
such an event. The watchdog timer consists of a 16-bit timer that
is clocked at the external clock rate (CLKIN or crystal input
frequency).
In order to prevent an unwanted timeout or reset, it is necessary
to periodically write to the watchdog timer register. During
abnormal system operation, the watchdog count will eventually
decrement to 0 and a watchdog timeout will occur. In the system,
the watchdog timeout will cause a full reset of the DSP core and
peripherals.
–10–
IMASK/
IRPTL
Vector Address
NA
NA
0
1
2
3
4
0x00 0000
0x00 0020
0x00 0040
0x00 0060
0x00 0080
5
0x00 00A0
6
0x00 00C0
7
0x00 00E0
8
0x00 0100
9
0x00 0120
10
0x00 0140
11
0x00 0160
12
0x00 0180
REV. 0
ADSP-21991
Table 2. Interrupt Priorities/Addresses
Interrupt
User Assigned Interrupt
(USR9)
User Assigned Interrupt
(USR10)
User Assigned Interrupt
(USR11)
—Lowest Priority
IMASK/
IRPTL
Vector Address
13
0x00 01A0
14
0x00 01C0
15
0x00 01E0
of the ADSP-21991 contains eight, 16-bit Interrupt Priority
Registers (Interrupt Priority Register 0 (IPR0) to Interrupt
Priority Register 7 (IPR7)).
Each Interrupt Priority Register contains a four 4-bit codes; one
specifically assigned to each peripheral interrupt. The user may
write a value between 0x0 and 0xB to each 4-bit location in order
to effectively connect the particular interrupt source to the corresponding user assignable interrupt of the ADSP-219x core.
There is no assigned priority for the peripheral interrupts after
reset. To assign the peripheral interrupts a different priority,
applications write the new priority to their corresponding control
bits (determined by their ID) in the Interrupt Priority Control
register.
Interrupt routines can either be nested with higher priority interrupts taking precedence or processed sequentially. Interrupts can
be masked or unmasked with the IMASK register. Individual
interrupt requests are logically ANDed with the bits in IMASK;
the highest priority unmasked interrupt is then selected. The
emulation, power-down, and reset interrupts are nonmaskable
with the IMASK register, but software can use the DIS INT
instruction to mask the power-down interrupt.
The Interrupt Control (ICNTL) register controls interrupt
nesting and enables or disables interrupts globally.
ENA INT;
DIS INT;
At reset, interrupt servicing is disabled.
This scheme permits the user to assign the number of specific
interrupts that are unique to their application to the interrupt
scheme of the ADSP-219x core. The user can then use the
existing interrupt priority control scheme to dynamically control
the priorities of the 12 core interrupts.
Low Power Operation
The IRPTL register is used to force and clear interrupts. On-chip
stacks preserve the processor status and are automatically maintained during interrupt handling. To support interrupt, loop, and
subroutine nesting, the PC stack is 33 levels deep, the loop stack
is 8 levels deep, and the status stack is 16 levels deep. To prevent
stack overflow, the PC stack can generate a stack level interrupt
if the PC stack falls below 3 locations full or rises above 28
locations full.
The following instructions globally enable or disable interrupt
servicing, regardless of the state of IMASK.
Writing a value of 0x0 connects the peripheral interrupt to the
USR0 user assignable interrupt of the ADSP-219x core while
writing a value of 0xB connects the peripheral interrupt to the
USR11 user assignable interrupt. The core interrupt USR0 is the
highest priority user interrupt, while USR11 is the lowest priority.
Writing a value between 0xC and 0xF effectively disables the
peripheral interrupt by not connecting it to any ADSP-219x core
interrupt input. The user may assign more than one peripheral
interrupt to any given ADSP-219x core interrupt. In that case,
the onus is on the user software in the interrupt vector table to
determine the exact interrupt source through reading status bits.
The ADSP-21991 has four low power options that significantly
reduce the power dissipation when the device operates under
standby conditions. To enter any of these modes, the DSP
executes an IDLE instruction. The ADSP-21991 uses the configuration of the PD, STCK, and STALL bits in the PLLCTL
register to select between the low power modes as the DSP
executes the IDLE instruction. Depending on the mode, an
IDLE shuts off clocks to different parts of the DSP in the different
modes. The low power modes are:
• Idle
• Power-Down Core
• Power-Down Core/Peripherals
• Power-Down All
Idle Mode
For quick servicing of interrupts, a secondary set of DAG and
computational registers exist. Switching between the primary
and secondary registers lets programs quickly service interrupts,
while preserving the state of the DSP.
When the ADSP-21991 is in Idle mode, the DSP core stops
executing instructions, retains the contents of the instruction
pipeline, and waits for an interrupt. The core clock and peripheral
clock continue running.
Peripheral Interrupt Controller
To enter Idle mode, the DSP can execute the IDLE instruction
anywhere in code. To exit Idle mode, the DSP responds to an
interrupt and (after two cycles of latency) resumes executing
instructions.
The Peripheral Interrupt Controller is a dedicated peripheral unit
of the ADSP-21991 (accessed via IO mapped registers). The
peripheral interrupt controller manages the connection of up to
32 peripheral interrupt requests to the DSP core.
For each peripheral interrupt source, there is a unique 4-bit code
that allows the user to assign the particular peripheral interrupt
to any one of the 12 user assignable interrupts of the embedded
ADSP-219x core. Therefore, the peripheral interrupt controller
REV. 0
Power-Down Core Mode
When the ADSP-21991 is in Power-Down Core mode, the DSP
core clock is off, but the DSP retains the contents of the pipeline
and keeps the PLL running. The peripheral bus keeps running,
letting the peripherals receive data.
–11–
ADSP-21991
To exit Power-Down Core mode, the DSP responds to an
interrupt and (after two cycles of latency) resumes executing
instructions.
The maximum peripheral clock is 80 MHz for the ADSP21991BST and 75 MHz for the ADSP-21991BBC—the combination of the input clock and core/peripheral clock ratios may not
exceed these limits.
Power-Down Core/Peripherals Mode
When the ADSP-21991 is in Power-Down Core/Peripherals
mode, the DSP core clock and peripheral bus clock are off, but
the DSP keeps the PLL running. The DSP does not retain the
contents of the instruction pipeline.The peripheral bus is
stopped, so the peripherals cannot receive data.
CLKIN
To exit Power-Down Core/Peripherals mode, the DSP responds
to an interrupt and (after five to six cycles of latency) resumes
executing instructions.
XTAL
ADSP-2199x
Power-Down All Mode
When the ADSP-21991 is in Power-Down All mode, the DSP
core clock, the peripheral clock, and the PLL are all stopped. The
DSP does not retain the contents of the instruction pipeline. The
peripheral bus is stopped, so the peripherals cannot receive data.
To exit Power-Down Core/Peripherals mode, the DSP responds
to an interrupt and (after 500 cycles to re-stabilize the PLL)
resumes executing instructions.
Reset and Power-On Reset (POR)
The RESET pin initiates a complete hardware reset of the ADSP21991 when pulled low. The RESET signal must be asserted
when the device is powered up to assure proper initialization. The
ADSP-21991 contains an integrated power-on reset (POR)
circuit that provides an output reset signal, POR, from the ADSP21991 on power-up and if the power supply voltage falls below
the threshold level. The ADSP-21991 may be reset from an
external source using the RESET signal, or alternatively, the
internal power-on reset circuit may be used by connecting the
POR pin to the RESET pin. During power-up the RESET line
must be activated for long enough to allow the DSP core’s internal
clock to stabilize. The power-up sequence is defined as the total
time required for the crystal oscillator to stabilize after a valid
VDD is applied to the processor and for the internal phase-locked
loop (PLL) to lock onto the specific crystal frequency. A
minimum of 512 cycles will ensure that the PLL has locked (this
does not include the crystal oscillator start-up time).
Clock Signals
The ADSP-21991 can be clocked by a crystal oscillator or a
buffered, shaped clock derived from an external clock oscillator.
If a crystal oscillator is used, the crystal should be connected
across the CLKIN and XTAL pins, with two capacitors
connected as shown in Figure 5. Capacitor values are dependent
on crystal type and should be specified by the crystal manufacturer. A parallel resonant, fundamental frequency,
microprocessor grade crystal should be used for this
configuration.
If a buffered, shaped clock is used, this external clock connects
to the DSP CLKIN pin. CLKIN input cannot be halted,
changed, or operated below the specified frequency during
normal operation. This clock signal should be a TTL compatible
signal. When an external clock is used, the XTAL input must be
left unconnected.
The DSP provides a user programmable 1ⴛ to 32ⴛ multiplication of the input clock, including some fractional values, to
support 128 external to internal (DSP core) clock ratios. The
BYPASS pin, and MSEL6–0 and DF bits, in the PLL configuration register, decide the PLL multiplication factor at reset. At
run time, the multiplication factor can be controlled in software.
To support input clocks greater that 100 MHz, the PLL uses an
additional bit (DF). If the input clock is greater than 100 MHz,
DF must be set. If the input clock is less than 100 MHz, DF must
be cleared. For clock multiplier settings, see the ADSP-2199x
Mixed Signal DSP Controller Hardware Reference.
The peripheral clock is supplied to the CLKOUT pin.
All on-chip peripherals for the ADSP-21991 operate at the rate
set by the peripheral clock. The peripheral clock (HCLK) is
either equal to the core clock rate or one half the DSP core clock
rate (CCLK). This selection is controlled by the IOSEL bit in
the PLLCTL register. The maximum core clock is 160 MHz for
the ADSP-21991BST and 150 MHz for the ADSP-21991BBC.
Figure 5. External Crystal Connections
The RESET input contains some hysteresis. If an RC circuit is
used to generate the RESET signal, the circuit should use an
external Schmitt trigger.
The master reset sets all internal stack pointers to the empty stack
condition, masks all interrupts, and resets all registers to their
default values (where applicable). When RESET is released, if
there is no pending bus request, program control jumps to the
location of the on-chip boot ROM (0xFF0000) and the booting
sequence is performed.
Power Supplies
The ADSP-21991 has separate power supply connections for the
internal (VDDINT) and external (VDDEXT) power supplies. The
internal supply must meet the 2.5 V requirement. The external
supply must be connected to a 3.3 V supply. All external supply
pins must be connected to the same supply. The ideal power-on
sequence for the DSP is to provide power-up of all supplies simultaneously. If there is going to be some delay in power-up between
the supplies, provide VDD first, then VDD_IO.
–12–
REV. 0
ADSP-21991
RESET pin, or a software initiated reset, via writing to the
Software Reset register. Following either a hardware or a software
reset, execution always starts from the boot ROM at address
0xFF0000, irrespective of the settings of the BMODE2,
BMODE1, and BMODE0 pins. The dedicated BMODE2,
BMODE1, and BMODE0 pins are sampled at hardware reset.
Booting Modes
The ADSP-21991 supports a number of different boot modes
that are controlled by the three dedicated hardware boot mode
control pins (BMODE2, BMODE1, and BMODE0). The use
of three boot mode control pins means that up to eight different
boot modes are possible. Of these only five modes are valid on
the ADSP-21991. The ADSP-21991 exposes the boot
mechanism to software control by providing a nonmaskable boot
interrupt that vectors to the start of the on-chip ROM memory
block (at address 0xFF0000). A boot interrupt is automatically
initiated following either a hardware initiated reset, via the
The particular boot mode for the ADSP-21991 associated with
the settings of the BMODE2, BMODE1, BMODE0 pins is
defined in Table 3.
Table 3. Summary of Boot Modes
Boot Mode
BMODE2
BMODE1
BMODE0
Function
0
1
2
3
4
5
6
7
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Illegal – Reserved
Boot from External 8-bit Memory over EMI
Execute from External 8-bit Memory
Execute from External 16-bit Memory
Boot from SPI ≤ 4K bits
Boot from SPI > 4K bits
Illegal – Reserved
Illegal – Reserved
Instruction Set Description
Development Tools
The ADSP-21991 assembly language instruction set has an
algebraic syntax that was designed for ease of coding and readability. The assembly language, which takes full advantage of the
unique architecture of the processor, offers the following benefits:
The ADSP-21991 is supported with a complete set of
CROSSCORE™ software and hardware development tools,
including Analog Devices emulators and VisualDSP++™ development environment. The emulator hardware that supports
other ADSP-219x DSPs also fully emulates the ADSP-21991.
• ADSP-219x assembly language syntax is a superset of and
source code compatible (except for two data registers and
DAG base address registers) with ADSP-21xx family
syntax. It may be necessary to restructure ADSP-21xx
programs to accommodate the unified memory space of
the ADSP-21991 and to conform to its interrupt vector
map.
The VisualDSP++ project management environment lets programmers develop and debug an application. This environment
includes an easy to use assembler (which is based on an algebraic
syntax), an archiver (librarian/library builder), a linker, a loader,
a cycle-accurate instruction-level simulator, a C/C++ compiler,
and a C/C++ runtime library that includes DSP and mathematical functions. A key point for these tools is C/C++ code
efficiency. The compiler has been developed for efficient translation of C/C++ code to DSP assembly. The DSP has architectural
features that improve the efficiency of compiled C/C++ code.
• The algebraic syntax eliminates the need to remember
cryptic assembler mnemonics. For example, a typical
arithmetic add instruction, such as AR = AX0 + AY0,
resembles a simple equation.
• Every instruction, but two, assembles into a single, 24-bit
word that can execute in a single instruction cycle. The
exceptions are two dual word instructions. One writes
16-bit or 24-bit immediate data to memory, and the other
is an absolute jump/call with the 24-bit address specified
in the instruction.
• Multifunction instructions allow parallel execution of an
arithmetic, MAC, or shift instruction with up to two
fetches or one write to processor memory space during a
single instruction cycle.
• Program flow instructions support a wider variety of conditional and unconditional jumps/calls and a larger set of
conditions on which to base execution of conditional
instructions.
REV. 0
The VisualDSP++ debugger has a number of important features.
Data visualization is enhanced by a plotting package that offers
a significant level of flexibility. This graphical representation of
user data enables the programmer to quickly determine the performance of an algorithm. As algorithms grow in complexity, this
capability can have increasing influence on the design development schedule, increasing productivity. Statistical profiling
enables the programmer to nonintrusively poll the processor as
it is running the program. This feature, unique to VisualDSP++,
enables the software developer to passively gather important code
execution metrics without interrupting the real-time characteristics of the program. Essentially, the developer can identify
bottlenecks in software quickly and efficiently. By using the
profiler, the programmer can focus on those areas in the program
that impact performance and take corrective action.
–13–
ADSP-21991
Debugging both C/C++ and assembly programs with the
VisualDSP++ debugger, programmers can:
Linker is fully compatible with existing Linker Definition File
(LDF), allowing the developer to move between the graphical
and textual environments.
• View mixed C/C++ and assembly code (interleaved
source and object information)
Analog Devices DSP emulators use the IEEE 1149.1 JTAG Test
Access Port of the ADSP-21991 processor to monitor and control
the target board processor during emulation. The emulator
provides full speed emulation, allowing inspection and modification of memory, registers, and processor stacks. Non intrusive
in-circuit emulation is assured by the use of the processor JTAG
interface—target system loading and timing are not affected by
the emulator.
• Insert breakpoints
• Set conditional breakpoints on registers, memory,
and stacks
• Trace instruction execution
• Perform linear or statistical profiling of program
execution
• Fill, dump, and graphically plot the contents of memory
• Perform source level debugging
• Create custom debugger windows
The VisualDSP++ IDDE lets programmers define and manage
DSP software development. Its dialog boxes and property pages
let programmers configure and manage all of the ADSP-219x
development tools, including the color syntax highlighting in the
VisualDSP++ editor. This capability permits programmers to:
Designing an Emulator-Compatible DSP Board
• Control how the development tools process inputs and
generate outputs
• Maintain a one-to-one correspondence with the
command line switches of the tool
The VisualDSP++ Kernel (VDK) incorporates scheduling and
resource management tailored specifically to address the memory
and timing constraints of DSP programming. These capabilities
enable engineers to develop code more effectively, eliminating the
need to start from the very beginning, when developing new
application code. The VDK features include Threads, Critical
and Unscheduled regions, Semaphores, Events, and Device flags.
The VDK also supports Priority-based, Preemptive, Cooperative, and Time-Sliced scheduling approaches. In addition, the
VDK was designed to be scalable. If the application does not use
a specific feature, the support code for that feature is excluded
from the target system.
Because the VDK is a library, a developer can decide whether to
use it or not. The VDK is integrated into the VisualDSP++ development environment, but can also be used via standard
command line tools. When the VDK is used, the development
environment assists the developer with many error-prone tasks
and assists in managing system resources, automating the generation of various VDK based objects, and visualizing the system
state, when debugging an application that uses the VDK.
VCSE is Analog Devices technology for creating, using, and
reusing software components (independent modules of substantial functionality) to quickly and reliably assemble software
applications. Download components from the Web and drop
them into the application. Publish component archives from
within VisualDSP++. VCSE supports component implementation in C/C++ or assembly language.
Use the Expert Linker to visually manipulate the placement of
code and data on the embedded system. View memory utilization
in a color-coded graphical form, easily move code and data to
different areas of the DSP or external memory with the drag of
the mouse, examine run time stack and heap usage. The Expert
In addition to the software and hardware development tools
available from Analog Devices, third parties provide a wide range
of tools supporting the ADSP-219x processor family. Hardware
tools include ADSP-219x DSP PC plug-in cards. Third party
software tools include DSP libraries, real-time operating systems,
and block diagram design tools.
The Analog Devices family of emulators are tools that every DSP
developer needs to test and debug hardware and software
systems. Analog Devices has supplied an IEEE 1149.1 JTAG Test
Access Port (TAP) on each JTAG DSP. The emulator uses the
TAP to access the internal features of the DSP, allowing the
developer to load code, set breakpoints, observe variables,
observe memory, and examine registers. The DSP must be halted
to send data and commands, but once an operation has been
completed by the emulator, the DSP system is set running at full
speed with no impact on system timing.
To use these emulators, the target board must include a header
that connects the JTAG port of the DSP to the emulator.
For details on target board design issues including mechanical
layout, single processor connections, multiprocessor scan chains,
signal buffering, signal termination, and emulator pod logic, see
the EE-68: Analog Devices JTAG Emulation Technical Reference on
the Analog Devices website (www.analog.com)—use site search
on “EE-68.” This document is updated regularly to keep pace
with improvements to emulator support.
Additional Information
This data sheet provides a general overview of the ADSP-21991
architecture and functionality. For detailed information on the
ADSP-21991 embedded DSP core architecture, instruction set,
communications ports and embedded control peripherals, refer
to the ADSP-2199x Mixed Signal DSP Controller Hardware
Reference.
PIN FUNCTION DESCRIPTIONS
ADSP-21991 pin definitions are listed in Table 4. All ADSP21991 inputs are asynchronous and can be asserted asynchronously to CLKIN (or to TCK for TRST).
Unused inputs should be tied or pulled to VDDEXT or GND, except
for ADDR21–0, DATA15–0, PF7-0, and inputs that have
internal pull-up or pull-down resistors (TRST, BMODE0,
BMODE1, BMODE2, BYPASS, TCK, TMS, TDI, PWMPOL,
PWMSR, and RESET)—these pins can be left floating. These
–14–
REV. 0
ADSP-21991
pins have a logic level hold circuit that prevents input from
floating internally. PWMTRIP has an internal pull-down, but
should not be left floating to avoid unnecessary PWM shutdowns.
The following symbols appear in the Type column of Table 4:
G = Ground, I = Input, O = Output, P = Power Supply,
B = Bidirectional, T = Three-State, D = Digital, A = Analog,
CKG = Clock Generation pin, PU = Internal Pull-up, and
PD = Internal Pull-Down.
Table 4. Pin Descriptions
Pin
Type
Function
A19–0
D15–0
RD
WR
ACK
BR
BG
BGH
MS0
MS1
MS2
MS3
IOMS
BMS
CLKIN
XTAL
CLKOUT
BYPASS
RESET
POR
BMODE2
BMODE1
BMODE0
TCK
TMS
TDI
TDO
TRST
EMU
VIN0
VIN1
VIN2
VIN3
VIN4
VIN5
VIN6
VIN7
ASHAN
BSHAN
CAPT
CAPB
VREF
SENSE
CML
CONVST
PF15
PF14
PF13
D, OT
D, BT
D, OT
D, OT
D, I
D, I, PU
D, O
D, O
D, OT
D, OT
D, OT
D, OT
D, OT
D, OT
D, I, CKG
D, O, CKG
D, O
D, I, PU
D, I, PU
D, O
D, I, PU
D, I, PD
D, I, PU
D, I
D, I, PU
D, I, PU
D, OT
D, I, PU
D, OT, PU
A, I
A, I
A, I
A, I
A, I
A, I
A, I
A, I
A, I
A, I
A, O
A, O
A, I, O
A, I
A, O
D, I
D, BT, PD
D, BT, PD
D, BT, PD
External Port Address Bus
External Port Data Bus
External Port Read Strobe
External Port Write Strobe
External Port Access Ready Acknowledge
External Port Bus Request
External Port Bus Grant
External Port Bus Grant Hang
External Port Memory Select Strobe 0
External Port Memory Select Strobe 1
External Port Memory Select Strobe 2
External Port Memory Select Strobe 3
External Port IO Space Select Strobe
External Port Boot Memory Select Strobe
Clock Input/Oscillator Input/Crystal Connection 0
Oscillator Output/Crystal Connection 1
Clock Output (HCLK)
PLL Bypass Mode Select
Processor Reset Input
Power on Reset Output
Boot Mode Select Input 2
Boot Mode Select Input 1
Boot Mode Select Input 0
JTAG Test Clock
JTAG Test Mode Select
JTAG Test Data Input
JTAG Test Data Output
JTAG Test Reset Input
Emulation Status
ADC Input 0
ADC Input 1
ADC Input 2
ADC Input 3
ADC Input 4
ADC Input 5
ADC Input 6
ADC Input 7
Inverting SHA_A Input
Inverting SHA_B Input
Noise Reduction Pin
Noise Reduction Pin
Voltage Reference Pin (Mode Selected by State of SENSE)
Voltage Reference Select Pin
Common-Mode Level Pin
ADC Convert Start Input
General-Purpose IO15
General-Purpose IO14
General-Purpose IO13
REV. 0
–15–
ADSP-21991
Table 4. Pin Descriptions (Continued)
Pin
Type
Function
PF12
PF11
PF10
PF9
PF8
PF7/SPISEL7
PF6/SPISEL6
PF5/SPISEL5
PF4/SPISEL4
PF3/SPISEL3
PF2/SPISEL2
PF1/SPISEL1
PF0/SPISS
SCK
MISO
MOSI
DT
DR
RFS
TFS
TCLK
RCLK
EIA
EIB
EIZ
EIS
AUX0
AUX1
AUXTRIP
TMR2
TMR1
TMR0
AH
AL
BH
BL
CH
CL
PWMSYNC
PWMPOL
PWMTRIP
PWMSR
AVDD (2 pins)
AVSS (2 pins)
VDDINT (6 pins)
VDDEXT (10 pins)
GND (16 pins)
D, BT, PD
D, BT, PD
D, BT, PD
D, BT, PD
D, BT, PD
D, BT, PD
D, BT, PD
D, BT, PD
D, BT, PD
D, BT, PD
D, BT, PD
D, BT, PD
D, BT, PD
D, BT
D, BT
D, BT
D, OT
D, I
D, BT
D, BT
D, BT
D, BT
D, I
D, I
D, I
D, I
D, O
D, O
D, I, PD
D, BT
D, BT
D, BT
D, O
D, O
D, O
D, O
D, O
D, O
D, BT
D, I, PU
D, I, PD
D, I, PU
A, P
A, G
D, P
D, P
D, G
General-Purpose IO12
General-Purpose IO11
General-Purpose IO10
General-Purpose IO9
General-Purpose IO8
General-Purpose IO7/SPI Slave Select Output 7
General-Purpose IO6/SPI Slave Select Output 6
General-Purpose IO5/SPI Slave Select Output 5
General-Purpose IO4/SPI Slave Select Output 4
General-Purpose IO3/SPI Slave Select Output 3
General-Purpose IO2/SPI Slave Select Output 2
General-Purpose IO1/SPI Slave Select Output 1
General-Purpose IO0/SPI Slave Select Input 0
SPI Clock
SPI Master In Slave Out Data
SPI Master Out Slave In Data
SPORT Data Transmit
SPORT Data Receive
SPORT Receive Frame Sync
SPORT Transmit Frame Sync
SPORT Transmit Clock
SPORT Receive Clock
Encoder A Channel Input
Encoder B Channel Input
Encoder Z Channel Input
Encoder S Channel Input
Auxiliary PWM Channel 0 Output
Auxiliary PWM Channel 1 Output
Auxiliary PWM Shutdown Pin
Timer 0 Input/Output Pin
Timer 1 Input/Output Pin
Timer 2 Input/Output Pin
PWM Channel A HI PWM
PWM Channel A LO PWM
PWM Channel B HI PWM
PWM Channel B LO PWM
PWM Channel C HI PWM
PWM Channel C LO PWM
PWM Synchronization
PWM Polarity
PWM Trip
PWM SR Mode Select
Analog Supply Voltage
Analog Ground
Digital Internal Supply
Digital External Supply
Digital Ground
–16–
REV. 0
ADSP-21991
SPECIFICATIONS
Specifications subject to change without notice.
RECOMMENDED OPERATING CONDITIONS—ADSP-21991BBC
Parameter
VDDINT
VDDEXT
AVDD
CCLK
HCLK1, 2
CLKIN3
TJUNC4
TAMB
Internal (Core) Supply Voltage
External (I/O) Supply Voltage
Analog Supply Voltage
DSP Instruction Rate, Core Clock
Peripheral Clock Rate
Input Clock Frequency
Silicon Junction Temperature
Ambient Operating Temperature
Min
Typ
Max
Unit
2.375
3.135
2.375
0
0
0
2.5
3.3
2.5
2.625
3.465
2.625
150
75
150
+140
+85
V
V
V
MHz
MHz
MHz
ºC
ºC
–40
1
The HCLK frequency may be made to appear at the dedicated CLKOUT pin of the device. For low power operation, however, the CLKOUT pin can be
disabled.
2
The peripherals operate at the HCLK rate, which may be selected to be equal to CCLK or CCLKⴜ2, up to a maximum of a 75 MHz HCLK for the
ADSP-21991BBC.
3
In order to attain the correct CCLK and HCLK values, the input clock frequency or crystal frequency depends on the internal operation of the clock
generation PLL circuit and the associated frequency ratio.
4
The maximum junction temperature is limited to 140°C in order to meet all of the electrical specifications. It is ultimately the responsibility of the user to
ensure that the power dissipation of the ADSP-21991 (including all dc and ac loads) is such that the maximum junction temperature limit of 140°C is not
exceeded.
RECOMMENDED OPERATING CONDITIONS—ADSP-21991BST
Parameter
VDDINT
VDDEXT
AVDD
CCLK
HCLK1, 2
CLKIN3
TJUNC4
TAMB
Internal (Core) Supply Voltage
External (I/O) Supply Voltage
Analog Supply Voltage
DSP Instruction Rate, Core Clock
Peripheral Clock Rate
Input Clock Frequency
Silicon Junction Temperature
Ambient Operating Temperature
Min
Typ
Max
Unit
2.375
3.135
2.375
0
0
0
2.5
3.3
2.5
2.625
3.465
2.625
160
80
160
+140
+85
V
V
V
MHz
MHz
MHz
ºC
ºC
–40
1
The HCLK frequency may be made to appear at the dedicated CLKOUT pin of the device. For low power operation, however, the CLKOUT pin can be
disabled.
2
The peripherals operate at the HCLK rate, which may be selected to be equal to CCLK or CCLKⴜ2, up to a maximum of an 80 MHz HCLK for the
ADSP-21991BST.
3
In order to attain the correct CCLK and HCLK values, the input clock frequency or crystal frequency depends on the internal operation of the clock
generation PLL circuit and the associated frequency ratio.
4
The maximum junction temperature is limited to 140°C in order to meet all of the electrical specifications. It is ultimately the responsibility of the user to
ensure that the power dissipation of the ADSP-21991 (including all dc and ac loads) is such that the maximum junction temperature limit of 140°C is not
exceeded.
REV. 0
–17–
ADSP-21991
ELECTRICAL CHARACTERISTICS—ADSP-21991BBC
Parameter
1
VIH
VIH
VIL
VOH
High Level Input Voltage
High Level Input Voltage2
High Level Input Voltage1, 2
High Level Output Voltage3
VOL
Low Level Output Voltage3
IIH
High Level Input Current4
IIH
High Level Input Current5
IIH
High Level Input Current6
IIL
Low Level Input Current
IIL
Low Level Input Current
IIL
Low Level Input Current
IOZH
Three-State Leakage Current7
IOZL
Three-State Leakage Current7
CI
CO
IDD-PEAK
IDD-TYP
IDD-IDLE
IDD-STOPCLK
IDD-STOPALL
IDD-PDOWN
IAVDD
IAVDD-ADCOFF
Input Pin Capacitance
Output Pin Capacitance
Supply Current (Internal)8, 9
Supply Current (Internal)8
Supply Current (Idle)8
Supply Current (Power-Down)8, 10
Supply Current (Power-Down)8, 11
Supply Current (Power-Down)8, 12
Analog Supply Current13
Analog Supply Current12
Test Conditions
Min
@ VDDEXT = maximum
@ VDDEXT = maximum
@ VDDEXT = minimum
@ VDDEXT = minimum,
IOH = –0.5 mA
@ VDDEXT = minimum,
IOL = 2.0 mA
@ VDDINT = maximum,
VIN = 3.6 V
@ VDDINT = maximum,
VIN = 3.6 V
@ VDDINT = maximum,
VIN = 3.6 V
@ VDDINT = maximum,
VIN = 0 V
@ VDDINT = maximum,
VIN = 0 V
@ VDDINT = maximum,
VIN = 0 V
@ VDDINT = maximum,
VIN = 3.6 V
@ VDDINT = maximum,
VIN = 0 V
fIN = 1 MHz
fIN = 1 MHz
2.0
2.2
Typ
Max
Unit
VDDEXT
VDDEXT
0.8
V
V
V
V
0.4
V
10
µA
150
µA
10
µA
10
µA
10
µA
150
µA
10
µA
10
µA
325
275
250
125
40
30
65
15
pF
pF
mA
mA
mA
mA
mA
mA
mA
mA
2.4
10
10
190
155
145
60
12
6
46
5
1
Applies to all input and bidirectional pins.
Applies to input pins CLKIN, RESET, TRST.
3
Applies to all output and bidirectional pins.
4
Applies to all input only pins.
5
Applies to input pins with internal pull-down.
6
Applies to input pins with internal pull-up.
7
Applies to three-stateable pins.
8
The IDD supply currents are affected by the operating frequency of the device. The guaranteed numbers are based on an assumed CCLK = 150 MHz,
HCLK = 75 MHz for the ADSP-21991BBC. IDD refers only to the current consumption on the internal power supply lines (VDDINT). The current
consumption at the I/O on the VDDEXT power supply is very much dependent on the particular connection of the device in the final system.
9
IDD-PEAK represents worst-case processor operation and is not sustainable under normal application conditions. Actual internal power measurements made
using typical applications are less than specified. Measured at VDDINT = maximum.
10
IDLE denotes the current consumption during execution of the IDLE instruction. Measured at VDDINT = maximum.
11
IDD-PDOWN represents the processor operation in full power-down mode with both core and peripheral clocks disabled. Measured at VDDINT = maximum.
12
IAVDD represents the power consumption of the analog system. Measured at AVDD = maximum.
13
The responsibility lies with the user to ensure that the device is operated in such a manner that the maximum allowable junction temperature is not exceeded.
2
–18–
REV. 0
ADSP-21991
ELECTRICAL CHARACTERISTICS—ADSP-21991BST
Parameter
1
VIH
VIH
VIL
VOH
High Level Input Voltage
High Level Input Voltage2
High Level Input Voltage1, 2
High Level Output Voltage3
VOL
Low Level Output Voltage3
IIH
High Level Input Current4
IIH
High Level Input Current5
IIH
High Level Input Current6
IIL
Low Level Input Current
IIL
Low Level Input Current
IIL
Low Level Input Current
IOZH
Three-State Leakage Current7
IOZL
Three-State Leakage Current7
CI
CO
IDD-PEAK
IDD-TYP
IDD-IDLE
IDD-STOPCLK
IDD-STOPALL
IDD-PDOWN
IAVDD
IAVDD-ADCOFF
Input Pin Capacitance
Output Pin Capacitance
Supply Current (Internal)8, 9
Supply Current (Internal)8
Supply Current (Idle)8
Supply Current (Power-Down)8, 10
Supply Current (Power-Down)8, 11
Supply Current (Power-Down)8, 12
Analog Supply Current13
Analog Supply Current12
Test Conditions
Min
@ VDDEXT = maximum
@ VDDEXT = maximum
@ VDDEXT = minimum
@ VDDEXT = minimum,
IOH = –0.5 mA
@ VDDEXT = minimum,
IOL = 2.0 mA
@ VDDINT = maximum,
VIN = 3.6 V
@ VDDINT = maximum,
VIN = 3.6 V
@ VDDINT = maximum,
VIN = 3.6 V
@ VDDINT = maximum,
VIN = 0 V
@ VDDINT = maximum,
VIN = 0 V
@ VDDINT = maximum,
VIN = 0 V
@ VDDINT = maximum,
VIN = 3.6 V
@ VDDINT = maximum,
VIN = 0 V
fIN = 1 MHz
fIN = 1 MHz
2.0
2.2
1
Typ
Max
Unit
VDDEXT
VDDEXT
0.8
V
V
V
V
0.4
V
10
µA
150
µA
10
µA
10
µA
10
µA
150
µA
10
µA
10
µA
350
300
275
150
50
35
65
15
pF
pF
mA
mA
mA
mA
mA
mA
mA
mA
2.4
10
10
300
240
225
90
20
7
49
7
Applies to all input and bidirectional pins.
Applies to input pins CLKIN, RESET, TRST.
3
Applies to all output and bidirectional pins.
4
Applies to all input only pins.
5
Applies to input pins with internal pull-down.
6
Applies to input pins with internal pull-up.
7
Applies to three-stateable pins.
8
The IDD supply currents are affected by the operating frequency of the device. The guaranteed numbers are based on an assumed CCLK=160 MHz, HCLK
= 80 MHz for the ADSP-21991BST. IDD refers only to the current consumption on the internal power supply lines (VDDINT). The current consumption
at the I/O on the VDDEXT power supply is very much dependent on the particular connection of the device in the final system.
9
IDD-PEAK represents worst-case processor operation and is not sustainable under normal application conditions. Actual internal power measurements made
using typical applications are less than specified. Measured at VDDINT = maximum.
10
IDLE denotes the current consumption during execution of the IDLE instruction. Measured at VDDINT = maximum.
11
IDD-PDOWN represents the processor operation in full power-down mode with both core and peripheral clocks disabled. Measured at VDDINT = maximum.
12
IAVDD represents the power consumption of the analog system. Measured at AVDD = maximum.
13
The responsibility lies with the user to ensure that the device is operated in such a manner that the maximum allowable junction temperature is not exceeded.
2
REV. 0
–19–
ADSP-21991
PERIPHERALS ELECTRICAL CHARACTERISTICS—ADSP-21991BBC
Parameter
ANALOG-TO-DIGITAL CONVERTER
AC Specifications
SNR
Signal-to-Noise Ratio1
SNRD
Signal-to-Noise and Distortion1
THD
Total Harmonic Distortion1
CTLK
Channel-Channel Crosstalk1
CMRR
Common-Mode Rejection Ratio1
PSRR
Power Supply Rejection Ratio1
Accuracy
INL
Integral Nonlinearity1
DNL
Differential Nonlinearity1
No missing Codes
Zero Error1
Gain Error1
Input Voltage
VIN
Input Voltage Span
CIN
Input Capacitance2
Conversion Time
FCLK
ADC Clock Rate
Total Conversion Time All 8 Channels
tCONV
VOLTAGE REFERENCE
Internal Voltage Reference3
Output Voltage Tolerance
Output Current
Load Regulation4
Power Supply Rejection Ratio
Reference Input Resistance
POWER-ON RESET
Reset Threshold Voltage
VRST
VHYST
Hysteresis Voltage
Min
Typ
68
66
72
71
–80
–80
–82
0.05
±0.6
±0.5
12
1.25
0.5
Max
Unit
–66
–66
–66
0.2
dB
dB
dB
dB
dB
%FSR
±2.0
±1.25
2.5
1.5
2.0
10
0.94
–2
–2
0.98
40
100
+0.5
+0.5
8
1.4
V
pF
18.75
773
MHz
ns
1.02
V
mV
µA
mV
mV
kΩ
+2
+2
2.1
50
LSB
LSB
Bits
%FSR
%FSR
V
mV
1
In all cases, the input frequency to the ADC system is assumed to be <100 kHz.
Analog Input Pins VIN0 to VIN7.
3
These specifications are for operation of the internal voltage reference so that SENSE = REFCOM, with the default 1.0 V operating mode.
4
Operation with full 0.1 mA load current. For optimal operation, it is recommended to buffer the VREF output voltage before using it in other parts of the
system.
2
–20–
REV. 0
ADSP-21991
PERIPHERALS ELECTRICAL CHARACTERISTICS—ADSP-21991BST
Parameter
ANALOG-TO-DIGITAL CONVERTER
AC Specifications
SNR
Signal-to-Noise Ratio1
SNRD
Signal-to-Noise and Distortion1
THD
Total Harmonic Distortion1
CTLK
Channel-Channel Crosstalk1
CMRR
Common-Mode Rejection Ratio1
PSRR
Power Supply Rejection Ratio1
Accuracy
INL
Integral Nonlinearity1
DNL
Differential Nonlinearity1
No missing Codes
Zero Error1
Gain Error1
Input Voltage
VIN
Input Voltage Span
Input Capacitance2
CIN
Conversion Time
FCLK
ADC Clock Rate
tCONV
Total Conversion Time All 8 Channels
VOLTAGE REFERENCE
Internal Voltage Reference3
Output Voltage Tolerance
Output Current
Load Regulation4
Power Supply Rejection Ratio
Reference Input Resistance
POWER ON RESET
Reset Threshold Voltage
VRST
VHYST
Hysteresis Voltage
1
Min
Typ
68
68
72
71
–78
–80
–74
0.05
±0.6
±0.5
12
1.25
0.5
Max
Unit
–68
–66
–66
0.2
dB
dB
dB
dB
dB
%FSR
±2.0
±1.25
2.5
1.5
2.0
10
0.94
–2
–2
0.98
40
100
+0.5
+0.5
8
1.4
V
pF
20
725
MHz
ns
1.02
V
mV
µA
mV
mV
kΩ
+2
+2
2.1
50
LSB
LSB
Bits
%FSR
%FSR
V
mV
In all cases, the input frequency to the ADC system is assumed to be <100 kHz.
Analog Input Pins VIN0 to VIN7.
3
These specifications are for operation of the internal voltage reference so that SENSE = REFCOM, with the default 1.0 V operating mode.
4
Operation with full 0.1 mA load current. For optimal operation, it is recommended to buffer the VREF output voltage before using it in other parts of the
system.
2
REV. 0
–21–
ADSP-21991
ABSOLUTE MAXIMUM RATINGS
Internal (Core) Supply Voltage1 (VDDINT) . . –0.3 V to +3.0 V
External (I/O) Supply Voltage1 (VDDEXT). . . –0.3 V to +4.6 V
Input Voltage1, 2 (VIL–VIH) . . . . . . . . . . . . . –0.5 V to +5.5 V
Output Voltage Swing1, 2 (VOL–VOH) . . . . . . –0.5 V to +5.5 V
Load Capacitance1 (CL). . . . . . . . . . . . . . . . . . . . . . 200 pF
Core Clock Period1 (tCCLK). . . . . . . . . . . . . . . . . . . . 6.25 ns
Core Clock Frequency1 (fCCLK) . . . . . . . . . . . . . . 160 MHz
Peripheral Clock Period1 (tHCLK) . . . . . . . . . . . . . . . 12.5 ns
Peripheral Clock Frequency1 (fHCLK) . . . . . . . . . . . 80 MHz
Storage Temperature Range1 (TSTORE) . . . .–65ºC to +150ºC
Lead Temperature (5 seconds)1 (TLEAD) . . . . . . . . . . . 185ºC
1
Stresses greater than those listed above may cause permanent damage to the
device. These are stress ratings only; functional operation of the device at these
or any other conditions greater than those indicated in the operational sections
of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
2
Except CLKIN and analog pins.
ESD SENSITIVITY
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V
readily accumulate on the human body and test equipment and can discharge without
detection. Although the ADSP-21991 features proprietary ESD protection circuitry,
permanent damage may occur on devices subjected to high energy electrostatic
discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
TIMING SPECIFICATIONS
This section contains timing information for the DSP external
signals. Use the exact information given. Do not attempt to derive
parameters from the addition or subtraction of other information.
While addition or subtraction would yield meaningful results for
an individual device, the values given in this data sheet reflect
statistical variations and worst cases. Consequently, parameters
cannot be added meaningfully to derive longer times.
Switching characteristics specify how the processor changes its
signals. No control is possible over this timing; circuitry external
to the processor must be designed for compatibility with these
signal characteristics. Switching characteristics indicate what the
processor will do in a given circumstance. Switching characteristics can also be used to ensure that any timing requirement of
a device connected to the processor (such as memory) is satisfied.
Timing requirements apply to signals that are controlled by
circuitry external to the processor, such as the data input for a
read operation.Timing requirements guarantee that the
processor operates correctly with other devices.
–22–
REV. 0
ADSP-21991
Clock In and Clock Out Cycle Timing
Table 5 and Figure 6 describe clock and reset operations. Combinations of CLKIN and clock multipliers must not select
core/peripheral clocks in excess of 160 MHz/80 MHz for the
ADSP-21991BST and 150 MHz/75 MHz for the ADSP21991BBC, when the peripheral clock rate is one-half the core
clock rate. If the peripheral clock rate is equal to the core clock
rate, the maximum peripheral clock rate is 80 MHz for the
ADSP-21991BST and 75 MHz for the ADSP-21991BBC. The
peripheral clock is supplied to the CLKOUT pins.
When changing from bypass mode to PLL mode, allow 512
HCLK cycles for the PLL to stabilize.
Table 5. Clock In and Clock Out Cycle Timing
Parameter
Timing Requirements
CLKIN Period1, 2
tCK
tCKL
CLKIN Low Pulse
tCKH
CLKIN High Pulse
RESET Asserted Pulsewidth Low
tWRST
tMSS
MSELx/BYPASS Stable Before RESET Deasserted Setup
tMSH
MSELx/BYPASS Stable After RESET Deasserted Hold
tMSD
MSELx/BYPASS Stable After RESET Asserted
Flag Output Disable Time After RESET Asserted
tPFD
Switching Characteristics
tCKOD
CLKOUT Delay from CLKIN
tCKO
CLKOUT Period3
Min
Max
Unit
10
4.5
4.5
200tCLKOUT
40
1000
200
ns
ns
ns
ns
µs
ns
ns
ns
200
10
0
12.5
5.8
1
ns
ns
In clock multiplier mode and MSEL6–0 set for 1:1 (or CLKIN = CCLK), tCK = tCCLK.
In bypass mode, tCK = tCCLK.
3
CLKOUT jitter can be as great as 8 ns when CLKOUT frequency is less than 20 MHz. For frequencies greater than 20 MHz, jitter is less than 1 ns.
2
tCK
CLKIN
tCKL
tCKH
tWRST
RESET
tPFD
tMSD
tMSS
tMSH
MSEL6–0
BYPASS
DF
tCKOD
CLKOUT
Figure 6. Clock In and Clock Out Cycle Timing
REV. 0
–23–
tCKO
ADSP-21991
Programmable Flags Cycle Timing
Table 6 and Figure 7 describe Programmable Flag operations.
Table 6. Programmable Flags Cycle Timing
Parameter
Min
Timing Requirement
tHFI
Flag Input Hold is Asynchronous
3
Switching Characteristics
tDFO
Flag Output Delay with Respect to CLKOUT
tHFO
Flag Output Hold After CLKOUT High
Max
Unit
ns
7
6
ns
ns
CLKOUT
tDFO
tHFO
PF
(OUTPUT)
FLAG OUTPUT
tHFI
PF
(INPUT)
FLAG INPUT
Figure 7. Programmable Flags Cycle Timing
–24–
REV. 0
ADSP-21991
Timer PWM_OUT Cycle Timing
Table 7 and Figure 8 describe timer expired operations. The
input signal is asynchronous in “width capture mode” and has
an absolute maximum input frequency of 40 MHz.
Table 7. Timer PWM_OUT Cycle Timing
1
Parameter
Min
Max
Unit
Switching Characteristic
Timer Pulsewidth Output1
tHTO
12.5
(232 –1) cycles
ns
32
The minimum time for tHTO is one cycle, and the maximum time for tHTO equals (2 –1) cycles.
HCLK
tHTO
PWM_OUT
Figure 8. Timer PWM_OUT Cycle Timing
REV. 0
–25–
ADSP-21991
the rising edge of EMI clock. ACK low causes the DSP to wait,
and the DSP requires two EMI clock cycles after ACK goes high
to finish the access. For more information, see the External Port
chapter in the ADSP-2199x DSP Hardware Reference.
External Port Write Cycle Timing
Table 8 and Figure 9 describe external port write operations.
The external port lets systems extend read/write accesses in three
ways: wait states, ACK input, and combined wait states and
ACK. To add waits with ACK, the DSP must see ACK low at
Table 8. External Port Write Cycle Timing
Parameter1, 2
Min
Timing Requirements
ACK Strobe Pulsewidth
tAKW
tDWSAK
ACK Delay from XMS Low
12.5
Switching Characteristics
tCSWS
Chip Select Asserted to WR Asserted Delay
Address Valid to WR Setup and Delay
tAWS
tWSCS
WR Deasserted to Chip Select Deasserted
WR Deasserted to Address Invalid
tWSA
tWW
WR Strobe Pulsewidth
tCDA
WR to Data Enable Access Delay
tCDD
WR to Data Disable Access Delay
Data Valid to WR Deasserted Setup
tDSW
tDHW
WR Deasserted to Data Invalid Hold Time; E_WHC4, 5
tDHW
WR Deasserted to Data Invalid Hold Time; E_WHC4, 6
tWWR
WR Deasserted to WR, RD Asserted
Max
Unit
0.5tEMICLK –1
ns
ns
0.5tEMICLK –4
0.5tEMICLK –3
0.5tEMICLK –4
0.5tEMICLK –3
tEMICLK –2+W3
0.5tEMICLK –3
tEMICLK +1+W3
3.4
tEMICLK +3.4
tHCLK
0
0.5tEMICLK +4
tEMICLK +7+W3
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
1
tEMICLK is the External Memory Interface clock period. tHCLK is the peripheral clock period.
These are timing parameters that are based on worst-case operating conditions.
3
W = (number of wait states specified in wait register) ⴛ tEMICLK.
4
Write hold cycle–memory select control registers (MS ⴛ CTL).
5
Write wait state count (E_WWC) = 0
6
Write wait state count (E_WWC) = 1
2
tCSWS
tWSCS
MS3–0
IOMS
BMS
A21–0
tWW
tAWS
tWSA
WR
tWWR
tAKW
ACK
tCDD
tCDA
tDSW
tDHW
tDWSAK
D15–0
RD
Figure 9. External Port Write Cycle Timing
–26–
REV. 0
ADSP-21991
External Port Read Cycle Timing
Table 9 and Figure 10 describe external port read operations.
For additional information on the ACK signal, see the discussion
on Page 26.
Table 9. External Port Read Cycle Timing
Parameter1, 2
Min
Timing Requirements
ACK Strobe Pulsewidth
tAKW
tRDA
RD Asserted to Data Access Setup
tADA
Address Valid to Data Access Setup
tSDA
Chip Select Asserted to Data Access Setup
tSD
Data Valid to RD Deasserted Setup
tHRD
RD Deasserted to Data Invalid Hold
ACK Delay from XMS Low
tDRSAK
Max
tHCLK
tEMICLK –5+W3
tEMICLK +W3
tEMICLK +W3
5
0
0.5tEMICLK –1
Switching Characteristics
tCSRS
Chip Select Asserted to RD Asserted Delay
tARS
Address Valid to RD Setup and Delay
tRSCS
RD Deasserted to Chip Select Deasserted Setup
RD Strobe Pulsewidth
tRW
tRSA
RD Deasserted to Address Invalid Setup
tRWR
RD Deasserted to WR, RD Asserted
0.5tEMICLK –3
0.5tEMICLK –3
0.5tEMICLK –2
tEMICLK –2+W3
0.5tHCLK –2
tHCLK
1
tEMICLK is the External Memory Interface clock period. tHCLK is the peripheral clock period.
These are timing parameters that are based on worst-case operating conditions.
3
W = (number of wait states specified in wait register) ⴛ tEMICLK.
2
MS3--0
IOMS
BMS
tRSCS
tCSRS
A21–0
tRW
tARS
tRSA
RD
tDRSAK
tRWR
tAKW
ACK
tCDA
tSD
D15–0
tRDA
tADA
tSDA
WR
Figure 10. External Port Read Cycle Timing
REV. 0
–27–
tH R D
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ADSP-21991
External Port Bus Request/Grant Cycle Timing
Table 10 and Figure 11 describe external port bus request and
bus grant operations.
Table 10. External Port Bus Request and Grant Cycle Timing
1
2
Parameter1, 2
Min
Timing Requirements
BR Asserted to CLKOUT High Setup
tBS
tBH
CLKOUT High to BR Deasserted Hold Time
4.6
0
Switching Characteristics
tSD
CLKOUT High to xMS, Address, and RD/WR Disable
CLKOUT Low to xMS, Address, and RD/WR Enable
tSE
tDBG
CLKOUT High to BG Asserted Setup
CLKOUT High to BG Deasserted Hold Time
tEBG
tDBH
CLKOUT High to BGH Asserted Setup
tEBH
CLKOUT High to BGH Deasserted Hold Time
0
0
0
0
0
Max
Unit
ns
ns
0.5tHCLK +1
4
4
4
4
4
ns
ns
ns
ns
ns
ns
tHCLK is the peripheral clock period.
These are timing parameters that are based on worst-case operating conditions.
CLKOUT
tBS
tBH
BR
tSD
tSE
tSD
tSE
tSD
tSE
MS3--0
IOMS
BMS
A21–0
WR
RD
tDBG
tEBG
tDBH
tEBH
BG
BGH
Figure 11. External Port Bus Request and Grant Cycle Timing
–28–
REV. 0
ADSP-21991
Serial Port Timing
Table 11 and Figure 12 describe SPORT transmit and receive
operations, while Figure 13 and Figure 14 describe SPORT
Frame Sync operations.
Table 11. Serial Port1, 2
Parameter
Min
External Clock Timing Requirements
TFS/RFS Setup Before TCLK/RCLK3
tSFSE
tHFSE
TFS/RFS Hold After TCLK/RCLK3
tSDRE
Receive Data Setup Before RCLK3
tHDRE
Receive Data Hold After RCLK3
tSCLKW
TCLK/RCLK Width
tSCLK
TCLK/RCLK Period
4
4
1.5
4
0.5tHCLK –1
2tHCLK
ns
ns
ns
ns
ns
ns
Internal Clock Timing Requirements
TFS Setup Before TCLK4; RFS Setup Before RCLK3
tSFSI
TFS/RFS Hold After TCLK/RCLK3
tHFSI
tSDRI
Receive Data Setup Before RCLK3
tHDRI
Receive Data Hold After RCLK3
4
3
2
5
ns
ns
ns
ns
External or Internal Clock Switching Characteristics
TFS/RFS Delay After TCLK/RCLK (Internally
tDFSE
Generated FS)4
TFS/RFS Hold After TCLK/RCLK (Internally
tHOFSE
Generated FS)4
14
3
External Clock Switching Characteristics
Transmit Data Delay After TCLK4
tDDTE
Transmit Data Hold After TCLK4
tHDTE
4
Internal Clock Switching Characteristics
Transmit Data Delay After TCLK4
tDDTI
tHDTI
Transmit Data Hold After TCLK4
tSCLKIW
TCLK/RCLK Width
4
0.5tHCLK –3.5
Enable and Three-State5 Switching Characteristics
Data Enable from External TCLK4
tDTENE
tDDTTE
Data Disable from External TCLK4
Data Enable from Internal TCLK4
tDTENI
tDDTTI
Data Disable from External TCLK4
0
0
External Late Frame Sync Switching Characteristics
tDDTLFSE
Data Delay from Late External TFS with MCE=1, MFD=06, 7
Data Enable from Late FS or MCE=1, MFD=06, 7
3.5
tDTENLFSE
1
Max
Unit
ns
ns
13.4
ns
ns
13.4
0.5tHCLK +2.5
ns
ns
ns
12.1
13
13
12
ns
ns
ns
ns
10.5
ns
ns
To determine whether communication is possible between two devices at clock speed n, the following specifications must be confirmed: 1) frame sync delay
and frame sync setup-and-hold, 2) data delay and data setup-and-hold, and 3) SCLK width.
2
Word selected timing for I2S mode is the same as TFS/RFS timing (normal framing only).
3
Referenced to sample edge.
4
Referenced to drive edge.
5
Only applies to SPORT.
6
MCE=1, TFS enable, and TFS valid follow tDDTENFS and tDDTLFSE.
7
If external RFSD/TFS setup to RCLK/TCLK>0.5tLSCK, tDDTLSCK and tDTENLSCK apply; otherwise, tDDTLFSE and tDTENLFS apply.
REV. 0
–29–
ADSP-21991
DATA RECEIVE-INTERNAL CLOCK
DATA RECEIVE-EXTERNAL CLOCK
SAMPLE
EDGE
DRIVE
EDGE
DRIVE
EDGE
SAMPLE
EDGE
tSCLKIW
tSCLKW
RCLK
RCLK
tDFSE
tHOFSE
tSFSI
tDFSE
tHOFSE
tHFSI
RFS
tSFSE
tHFSE
tSDRE
tHDRE
RFS
tSDRI
tHDRI
DR
DR
NOTE: EITHER THE RISING EDGE OR FALLING EDGE OF RCLK OR TCLK CAN BE USED AS THE ACTIVE SAMPLING EDGE.
DATA TRANSMIT-INTERNAL CLOCK
DATA TRANSMIT-EXTERNAL CLOCK
SAMPLE
EDGE
DRIVE
EDGE
DRIVE
EDGE
SAMPLE
EDGE
tSCLKIW
tSCLKW
TCLK
TCLK
tDFSE
tHOFSE
tSFSI
tDFSE
tHOFSE
tHFSI
TFS
tSFSE
tHFSE
TFS
tHDTI
tDDTI
tHDTE
tDDTE
DT
DT
NOTE: EITHER THE RISING EDGE OR FALLING EDGE OF RCLK OR TCLK CAN BE USED AS THE ACTIVE SAMPLING EDGE.
DRIVE
EDGE
DRIVE
EDGE
TCLK (EXT)
TFS (“LATE,” EXT.)
TCLK/RCLK
tDDTEN
tDDTTE
DT
DRIVE
EDGE
TCLK (INT)
TFS (“LATE,” INT.)
DRIVE
EDGE
TCLK/RCLK
tDDTIN
tDDTTI
DT
Figure 12. Serial Port
–30–
REV. 0
ADSP-21991
EXTERNAL RFS WITH MCE = 1, MFD = 0
DRIVE
SAMPLE
DRIVE
RCLK
tHOSFSE/ I
tSFSE/ I
RFS
tDDTE/ I
tHDTE/ I
tDTENLFSE
DT
1ST BIT
2ND BIT
tDDTLFSE
LATE EXTERNAL TFS
DRIVE
SAMPLE
DRIVE
TCLK
tHOSFSE/ I
tSFSE / I
TFS
tDDTE / I
tHDTE/ I
tDTENLFSE
1ST BIT
DT
2ND BIT
tDDTLFSE
Figure 13. Serial Port—External Late Frame Sync (Frame Sync Setup > 0.5tSCLK)
EXTERNAL RFS WITH MCE = 1, MFD = 0
DRIVE
SAMPLE
DRIVE
RCLK
tSFSE/ I
tHOFSE/ I
RFS
tDDTE / I
tHDTE/ I
tDTENLFSE
1ST BIT
DT
2ND BIT
tDDTLFSE
LATE EXTERNAL TFS
DRIVE
SAMPLE
DRIVE
TCLK
tHOFSE/ I
tSFSE/ I
TFS
tDDTE/ I
tHDTE/ I
tDTENLFSE
1ST BIT
DT
2ND BIT
tDDTLFSE
Figure 14. Serial Port—External Late Frame Sync (Frame Sync Setup < 0.5tHCLK)
REV. 0
–31–
ADSP-21991
Serial Peripheral Interface Port—Master Timing
Table 12 and Figure 15 describe SPI port master operations.
Table 12. Serial Peripheral Interface (SPI) Port—Master Timing
Parameter
Min
Max
Unit
Timing Requirements
tSSPID
Data Input Valid to SCLK Edge (Data Input Setup)
tHSPID
SCLK Sampling Edge to Data Input Invalid (Data In Hold)
8
1
ns
ns
Switching Characteristics
tSDSCIM
SPISEL Low to First SCLK Edge
tSPICHM
Serial Clock High Period
tSPICLM
Serial Clock Low Period
Serial Clock Period
tSPICLK
tHDSM
Last SCLK Edge to SPISEL High
Sequential Transfer Delay
tSPITDM
tDDSPID
SCLK Edge to Data Output Valid (Data Out Delay)
tHDSPID
SCLK Edge to Data Output Invalid (Data Out Hold)
2tHCLK –3
2tHCLK –3
2tHCLK –3
4tHCLK –1
2tHCLK –3
2tHCLK –2
0
0
6
5
ns
ns
ns
ns
ns
ns
ns
ns
tHDSM
tSPITDM
tSPICHM
SPISEL
(OUTPUT)
tSDSCIM
tSPICLK
tSPICLM
SCLK
(CPOL = 0)
(OUTPUT)
tSPICLM
tSPICHM
SCLK
(CPOL = 1)
(OUTPUT)
tDDSPID
MOSI
(OUTPUT)
tHDSPID
MSB
tSSPID
CPHA = 1
LSB
tHSPID
tSSPID
LSB
VALID
MSB
VALID
MISO
(INPUT)
tDDSPID
MOSI
(OUTPUT)
CPHA = 0
MISO
(INPUT)
tHDSPID
MSB
tSSPID
tHSPID
LSB
tHSPID
MSB
VALID
LSB
VALID
Figure 15. Serial Peripheral Interface (SPI) Port—Master Timing
–32–
REV. 0
ADSP-21991
Serial Peripheral Interface Port—Slave Timing
Table 13 and Figure 16 describe SPI port slave operations.
Table 13. Serial Peripheral Interface (SPI) Port—Slave Timing
Parameter
Min
Max
Timing Requirements
tSPICHS
Serial Clock High Period
tSPICLS
Serial Clock Low Period
tSPICLK
Serial Clock Period
tHDS
Last SPICLK Edge to SPISS Not Asserted
Sequential Transfer Delay
tSPITDS
tSDSCI
SPISS Assertion to First SPICLK Edge
tSSPID
Data Input Valid to SCLK Edge (Data Input Setup)
SCLK Sampling Edge to Data Input Invalid (Data In Hold)
tHSPID
2tHCLK
2tHCLK
4tHCLK
2tHCLK
2tHCLK +4
2tHCLK
1.6
2.4
Switching Characteristics
tDSOE
SPISS Assertion to Data Out Active
tDSDHI
SPISS Deassertion to Data High Impedance
tDDSPID
SCLK Edge to Data Out Valid (Data Out Delay)
tHDSPID
SCLK Edge to Data Out Invalid (Data Out Hold)
0
0
0
0
ns
ns
ns
ns
ns
ns
ns
ns
8
10
10
10
SPISS
(INPUT)
tSPICHS
tSPICLS
tSPICLS
tSDSCI
tSPICHS
tSPICLK
tHDS
SCLK
(CPOL = 0)
(INPUT)
SCLK
(CPOL = 1)
(INPUT)
tDSOE
tDDSPID
MISO
(OUTPUT)
MOSI
(INPUT)
tDSOE
MISO
(OUTPUT)
tDSDHI
LSB
tSSPID
tHSPID
tHSPID
MSB
VALID
LSB
VALID
tDDSPID
tDSDHI
LSB
MSB
CPHA = 0
MOSI
(INPUT)
tDDSPID
MSB
tSSPID
CPHA = 1
tHDSPID
tSSPID
MSB
VALID
tHSPID
LSB
VALID
Figure 16. Serial Peripheral Interface (SPI) Port—Slave Timing
REV. 0
–33–
Unit
tSPITDS
ns
ns
ns
ns
ADSP-21991
JTAG Test And Emulation Port Timing
Table 14 and Figure 17 describe JTAG port operations.
Table 14. JTAG Port Timing
Parameter
Min
Timing Requirements
tTCK
TCK Period
tSTAP
TDI, TMS Setup Before TCK High
TDI, TMS Hold After TCK High
tHTAP
tSSYS
System Inputs Setup Before TCK Low1
tHSYS
System Inputs Hold After TCK Low1
TRST Pulsewidth2
tTRSTW
4tTCK
Switching Characteristics
tDTDO
TDO Delay from TCK Low
System Outputs Delay After TCK Low3
tDSYS
0
Max
Unit
4
4
4
5
ns
ns
ns
ns
ns
ns
8
22
ns
ns
20
System Outputs = DATA15–0, ADDR21–0, MS3–0, RD, WR, ACK, CLKOUT, BG, PF15–0, DT, TCLK, RCLK, TFS, RFS, BMS.
50 MHz maximum.
3
System Inputs = DATA15–0, ADDR21–0, RD, WR, ACK, BR, BG, PF15–0, DR, TCLK, RCLK, TFS, RFS, CLKOUT, RESET.
1
2
tTCK
TCK
tSTAP
tHTAP
TMS
TDI
tDTDO
TDO
tSSYS
tHSYS
SYSTEM
INPUTS
tDSYS
SYSTEM
OUTPUTS
Figure 17. JTAG Port Timing
–34–
REV. 0
ADSP-21991
Power Dissipation
The load capacitance includes the package capacitance (CIN of
the processor). The switching frequency includes driving the load
high and then back low. Address and data pins can drive high and
low at a maximum rate of 1/(2tCK). The write strobe can switch
every cycle at a frequency of 1/tCK. Select pins switch at 1/(2tCK),
but selects can switch on each cycle. For example, estimate PEXT
with the following assumptions:
Total power dissipation has two components, one due to internal
circuitry and one due to the switching of external output drivers.
Internal power dissipation is dependent on the instruction
execution sequence and the data operands involved.
The external component of total power dissipation is caused by
the switching of output pins. Its magnitude depends on:
• Number of output pins that switch during each cycle (O)
• The maximum frequency at which they can switch (f)
• A system with one bank of external data memory—asynchronous RAM (16-bit)
• One 64Kⴛ16 RAM chip is used with a load of 10 pF
• Their load capacitance (C)
• Maximum peripheral speed CCLK = 80 MHz, HCLK =
80 MHz
• Their voltage swing (VDD)
and is calculated by the formula below.
• External data memory writes occur every other cycle, a
rate of 1/(4tHCLK), with 50% of the pins switching
2
• The bus cycle time is 80 MHz (tHCLK = 12.5 ns)
P EXT = O × C × V DD × f
The PEXT equation is calculated for each class of pins that can
drive as shown in Table 15.
Table 15. PEXT Calculation Example
Pin Type
No. of Pins
% Switching
ⴛC
ⴛf
ⴛ VDD2
= PEXT
Address
MSx
WR
Data
CLKOUT
15
1
1
16
1
50
0
10 pF
10 pF
10 pF
10 pF
10 pF
20 MHz
20 MHz
40 MHz
20 MHz
80 MHz
10.9 V
10.9 V
10.9 V
10.9 V
10.9 V
= 0.01635 W
= 0.0 W
= 0.00436 W
= 0.01744 W
= 0.00872 W
=0.04687 W
50
A typical power consumption can now be calculated for these
conditions by adding a typical internal power dissipation with the
following formula.
C L ∆V
t DECAY = --------------IL
The output disable time tDIS is the difference between tMEASURED
and tDECAY as shown in Figure 18. The time tMEASURED is the
interval from when the reference signal switches to when the
output voltage decays ∆V from the measured output high or
output low voltage. The tDECAY is calculated with test loads CL and
IL, and with ∆V equal to 0.5 V.
P TOTAL = P EXT + P INT
Where:
• PEXT is from Table 15
• PINT is IDDINT ⴛ 2.5 V, using the calculation IDDINT listed
in Power Dissipation.
Note that the conditions causing a worst-case PEXT are different
from those causing a worst-case PINT. Maximum PINT cannot
occur while 100% of the output pins are switching from all ones
to all zeros. Note also that it is not common for an application to
have 100% or even 50% of the outputs switching simultaneously.
REFERENCE
SIGNAL
tMEASURED
tDIS
Test Conditions
tENA
VOH (MEASURED)
The DSP is tested for output enable, disable, and hold time.
VOH (MEASURED) – ⌬V 2.0V
Output Disable Time
VOL (MEASURED)
VOL (MEASURED) + ⌬V 1.0V
tDECAY
Output pins are considered to be disabled when they stop driving,
go into a high impedance state, and start to decay from their
output high or low voltage. The time for the voltage on the bus
to decay by ∆V is dependent on the capacitive load, CL and the
load current, IL. This decay time can be approximated by the
following equation.
OUTPUT STOPS
DRIVING
OUTPUT STARTS
DRIVING
HIGH IMPEDANCE STATE.
TEST CONDITIONS CAUSE THIS VOLTAGE
TO BE APPROXIMATELY 1.5V
Figure 18. Output Enable/Disable
REV. 0
–35–
ADSP-21991
Output Enable Time
IOL
TO
OUTPUT
PIN
1.5V
50pF
Output pins are considered to be enabled when they have made
a transition from a high impedance state to when they start
driving. The output enable time tENA is the interval from when a
reference signal reaches a high or low voltage level to when the
output has reached a specified high or low trip point, as shown
in the Output Enable/Disable diagram (Figure 18). If multiple
pins (such as the data bus) are enabled, the measurement value
is that of the first pin to start driving.
Example System Hold Time Calculation
IOH
Figure 19. Equivalent Device Loading for AC
Measurements (Includes All Fixtures)
INPUT
OR
OUTPUT
1.5V
1.5V
To determine the data output hold time in a particular system,
first calculate tDECAY using the equation at Output Disable Time
on Page 35. Choose ∆V to be the difference between the output
voltage of the ADSP-21991 and the input threshold for the device
requiring the hold time. A typical ∆V will be 0.4 V. CL is the total
bus capacitance (per data line), and IL is the total leakage or threestate current (per data line). The hold time will be tDECAY plus the
minimum disable time (i.e., tDATRWH for the write cycle).
Pin Configurations
Table 16 identifies the signal for each Mini-BGA ball number.
Figure 20. Voltage Reference Levels for AC
Measurements (Except Output Enable/Disable)
Table 17 identifies the Mini-BGA ball number for each signal
name.
Table 18 identifies the signal for each LQFP lead.
Table 19 identifies the LQFP lead for each signal name.
Table 4 describes each signal.
–36–
REV. 0
ADSP-21991
Table 16. 196-Ball Mini-BGA Signal by Ball Number
Ball No.
Signal
Ball No.
Signal
Ball No.
Signal
Ball No.
Signal
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
B14
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
C11
C12
C13
C14
D1
D2
D3
D4
D5
D6
D7
nc
DR
DT
RFS
VIN4
BSHAN
VIN0
VIN1
VIN3
PF0/SPISS
PF4/SPISEL4
PF6/SPISEL6
PF7/SPISEL7
nc
SCK
RCLK
TCLK
TFS
VIN6
ASHAN
VIN2
SENSE
CAPB
PF1/SPISEL1
PF5/SPISEL5
PF8
PF9
PF13
BR
RD
MISO
MOSI
VIN7
VIN5
CAPT
VREF
CML
PF2/SPISEL2
PF10
PF11
PF12
PF14
A18
A19
IOMS
ACK
AVDD
AVDD
AVSS
D8
D9
D10
D11
D12
D13
D14
E1
E2
E3
E4
E5
E6
E7
E8
E9
E10
E11
E12
E13
E14
F1
F2
F3
F4
F5
F6
F7
F8
F9
F10
F11
F12
F13
F14
G1
G2
G3
G4
G5
G6
G7
G8
G9
G10
G11
G12
G13
G14
AVSS
PF3/SPISEL3
AUXTRIP
VDDEXT
AUX1
AUX0
PF15
A16
A17
WR
GND
VDDEXT
nc
nc
nc
nc
nc
GND
EIA
EIB
EIS
A14
A15
BG
GND
nc
nc
nc
nc
nc
nc
VDDINT
EIZ
TMR2
XTAL
A12
A13
BGH
VDDINT
nc
nc
nc
nc
nc
nc
GND
TMR1
CONVST
CLKOUT
H1
H2
H3
H4
H5
H6
H7
H8
H9
H10
H11
H12
H13
H14
J1
J2
J3
J4
J5
J6
J7
J8
J9
J10
J11
J12
J13
J14
K1
K2
K3
K4
K5
K6
K7
K8
K9
K10
K11
K12
K13
K14
L1
L2
L3
L4
L5
L6
L7
A10
A11
MS3
GND
nc
nc
nc
nc
nc
nc
VDDEXT
TMR0
POR
RESET
A8
A9
BMS
VDDEXT
nc
nc
nc
nc
nc
nc
GND
TMS
TCK
TDI
A6
A7
MS0
GND
GND
GND
GND
GND
GND
GND
VDDINT
EMU
TRST
TDO
A4
A5
MS1
VDDEXT
VDDINT
VDDEXT
VDDINT
L8
L9
L10
L11
L12
L13
L14
M1
M2
M3
M4
M5
M6
M7
M8
M9
M10
M11
M12
M13
M14
N1
N2
N3
N4
N5
N6
N7
N8
N9
N10
N11
N12
N13
N14
P1
P2
P3
P4
P5
P6
P7
P8
P9
P10
P11
P12
P13
P14
VDDINT
VDDEXT
VDDEXT
GND
BMODE2
BMODE1
CLKIN
A2
A3
MS2
GND
VDDEXT
GND
VDDEXT
nc
CL
AL
PWMPOL
PWMTRIP
BYPASS
BMODE0
A0
A1
D13
D11
D9
D7
D5
D3
D1
CH
AH
nc
PWMSYNC
PWMSR
nc
D15
D14
D12
D10
D8
D6
D4
D2
D0
BL
BH
nc
nc
REV. 0
–37–
ADSP-21991
Table 17. 196-Ball Mini-BGA Ball Number by Signal
Signal
Ball No.
Signal
Ball No.
Signal
Ball No.
Signal
Ball No.
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
ACK
AH
AL
ASHAN
AUXTRIP
AUX1
AUX0
AVDD
AVDD
AVSS
AVSS
BG
BGH
BL
BH
BMODE0
BMODE1
BMODE2
BMS
BR
BSHAN
BYPASS
CAPB
CAPT
CH
CL
CLKIN
CLKOUT
CML
N1
N2
M1
M2
L1
L2
K1
K2
J1
J2
H1
H2
G1
G2
F1
F2
E1
E2
D1
D2
D4
N11
M10
B6
D10
D12
D13
D5
D6
D7
D8
F3
G3
P11
P12
M14
L13
L12
J3
C1
A6
M13
B9
C7
N10
M9
L14
G14
C9
CONVST
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
DR
DT
EIA
EIB
EIS
EIZ
EMU
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
IOMS
MISO
MOSI
MS0
MS1
MS2
MS3
nc
nc
G13
P10
N9
P9
N8
P8
N7
P7
N6
P6
N5
P5
N4
P4
N3
P3
P2
A2
A3
E12
E13
E14
F12
K12
E4
E11
F4
G11
H4
J11
K4
K5
K6
K7
K8
K9
K10
L11
M4
M6
D3
C3
C4
K3
L3
M3
H3
A1
A14
nc
nc
nc
nc
nc
nc
nc
nc
nc
nc
nc
nc
nc
nc
nc
nc
nc
nc
nc
nc
nc
nc
nc
nc
nc
nc
nc
nc
nc
nc
nc
nc
nc
nc
PF0/SPISS
PF1/SPISEL1
PF2/SPISEL2
PF3/SPISEL3
PF4/SPISEL4
PF5/SPISEL5
PF6/SPISEL6
PF7/SPISEL7
PF8
PF9
PF10
PF11
PF12
PF13
PF14
E6
E7
E8
E9
E10
F5
F6
F7
F8
F9
F10
G5
G6
G7
G8
G9
G10
H5
H6
H7
H8
H9
H10
J5
J6
J7
J8
J9
J10
M8
N12
P1
P13
P14
A10
B10
C10
D9
A11
B11
A12
A13
B12
B13
C11
C12
C13
B14
C14
PF15
POR
PWMPOL
PWMSYNC
PWMSR
PWMTRIP
RCLK
RD
RESET
RFS
SCK
SENSE
TCK
TCLK
TDI
TDO
TFS
TMR0
TMR1
TMR2
TMS
TRST
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDINT
VDDINT
VDDINT
VDDINT
VDDINT
VDDINT
VIN0
VIN1
VIN2
VIN3
VIN4
VIN5
VIN6
VIN7
VREF
WR
XTAL
D14
H13
M11
N13
N14
M12
B2
C2
H14
A4
B1
B8
J13
B3
J14
K14
B4
H12
G12
F13
J12
K13
D11
E5
H11
J4
L4
L6
L9
L10
M5
M7
G4
L5
L7
L8
K11
F11
A7
A8
B7
A9
A5
C6
B5
C5
C8
E3
F14
–38–
REV. 0
ADSP-21991
Table 18. 176-Lead LQFP Signal by Lead Number
Lead No.
Signal
Lead No.
Signal
Lead No.
Signal
Lead No.
Signal
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
nc
nc
VDDEXT
RCLK
SCK
MISO
MOSI
RD
WR
ACK
BR
BG
BGH
IOMS
BMS
MS3
GND
VDDEXT
MS2
MS1
MS0
GND
VDDINT
A19
A18
A17
A16
A15
A14
A13
GND
VDDEXT
A12
A11
A10
A9
A8
A7
A6
A5
GND
nc
nc
nc
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
VDDEXT
A4
A3
A2
A1
A0
D15
D14
D13
D12
D11
GND
VDDEXT
GND
VDDINT
D10
D9
D8
D7
D6
D5
GND
VDDINT
D4
D3
D2
D1
D0
nc
GND
VDDEXT
CL
CH
BL
BH
AL
AH
nc
nc
PWMSYNC
PWMPOL
PWMSR
PWMTRIP
GND
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
nc
nc
VDDEXT
BYPASS
BMODE0
BMODE1
BMODE2
nc
GND
VDDINT
EMU
TRST
TDO
TDI
TMS
TCK
POR
RESET
CLKIN
XTAL
CLKOUT
CONVST
TMR0
GND
VDDEXT
TMR1
TMR2
EIS
GND
VDDINT
EIZ
EIB
EIA
AUXTRIP
AUX1
AUX0
PF15
PF14
PF13
PF12
GND
nc
nc
nc
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
VDDEXT
PF11
PF10
PF9
PF8
PF7/SPISEL7
PF6/SPISEL6
PF5/SPISEL5
PF4/SPISEL4
GND
VDDEXT
PF3/SPISEL3
PF2/SPISEL2
PF1/SPISEL1
PF0/SPISS
GND
VDDINT
AVSS
AVDD
nc
VREF
CML
CAPT
CAPB
SENSE
VIN3
VIN2
VIN1
VIN0
ASHAN
BSHAN
VIN4
VIN5
VIN6
VIN7
AVSS
AVDD
DT
DR
RFS
TFS
TCLK
GND
nc
REV. 0
–39–
ADSP-21991
Table 19. 176-Lead LQFP Lead Number by Signal
Signal
Lead No.
Signal
Lead No.
Signal
Lead No.
Signal
Lead No.
A0
A1
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A2
A3
A4
A5
A6
A7
A8
A9
ACK
AH
AL
ASHAN
AUX0
AUX1
AUXTRIP
AVDD
AVDD
AVSS
AVSS
BG
BGH
BH
BL
BMODE0
BMODE1
BMODE2
BMS
BR
BSHAN
BYPASS
nc
nc
50
49
35
34
33
30
29
28
27
26
25
24
48
47
46
40
39
38
37
36
10
81
80
162
124
123
122
151
169
150
168
12
13
79
78
93
94
95
15
11
163
92
73
82
CAPB
CAPT
CH
CL
CLKIN
CLKOUT
CML
CONVST
D0
D1
D10
D11
D12
D13
D14
D15
D2
D3
D4
D5
D6
D7
D8
D9
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
DR
DT
EIA
EIB
156
155
77
76
107
109
154
110
72
71
60
55
54
53
52
51
70
69
68
65
64
63
62
61
17
22
31
41
56
58
66
74
88
97
112
117
129
142
148
175
171
170
121
120
EIS
EIZ
EMU
IOMS
MISO
MOSI
MS0
MS1
MS2
MS3
nc
nc
nc
nc
nc
nc
nc
nc
nc
nc
nc
nc
nc
nc
PF0/SPISS
PF1/SPISEL1
PF10
PF11
PF12
PF13
PF14
PF15
PF2/SPISEL2
PF3/SPISEL3
PF4/SPISEL4
PF5/SPISEL5
PF6/SPISEL6
PF7/SPISEL7
PF8
PF9
POR
PWMPOL
PWMSR
PWMSYNC
116
119
99
14
6
7
21
20
19
16
1
2
42
43
44
83
89
90
96
130
131
132
152
176
147
146
135
134
128
127
126
125
145
144
141
140
139
138
137
136
105
85
86
84
PWMTRIP
RCLK
RD
RESET
RFS
SCK
SENSE
TCK
TCLK
TDI
TDO
TFS
TMR0
TMR1
TMR2
TMS
TRST
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDINT
VDDINT
VDDINT
VDDINT
VDDINT
VDDINT
VIN0
VIN1
VIN2
VIN3
VIN4
VIN5
VIN6
VIN7
VREF
WR
XTAL
87
4
8
106
172
5
157
104
174
102
101
173
111
114
115
103
100
3
18
32
45
57
75
91
113
133
143
23
59
67
98
118
149
161
160
159
158
164
165
166
167
153
9
108
–40–
REV. 0
ADSP-21991
OUTLINE DIMENSIONS
Dimensions shown in millimeters.
196-Ball Mini-BGA (BC-196-2)
15.00
BSC SQ
DETAIL B
14 13 12 11 10 9 8 7 6 5 4 3 2 1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
13.00
BSC
1.00 BSC
1.85
1.70
1.55
TOP VIEW
1.00 BSC
DETAIL A
13.00 BSC
BOTTOM VIEW
0.75
0.70
0.65
1.10
1.00
0.90
0.55
NOM
0.70
0.60
0.50
BALL
DIAMETER
0.20
MAX BALL
COPLANARITY
1.10
1.00
0.90
0.57
0.52
0.47
SEATING PLANE
DETAIL A
DETAIL B
NOTES:
1. THE ACTUAL POSITION OF THE BALL GRID IS WITHIN 0.25 OF ITS IDEAL POSITION RELATIVE TO THE
PACKAGE EDGES.
2. THE ACTUAL POSITION OF EACH BALL IS WITHIN 0.10 OF ITS IDEAL POSITION
RELATIVE TO THE BALL GRID.
3. DIMENSIONS COMPLY WITH JEDEC STANDARD MO-192 VARIATION AAE-1 WITH THE EXCEPTION OF
MAXIMUM HEIGHT.
4. CENTER DIMENSIONS ARE NOMINAL.
176-Lead LQFP (ST-176-1)
26.00 BSC SQ
0.75
0.60
0.45
24.00 BSC SQ
133
132
176
1
PIN 1
0.27
0.22 TYP
0.17
SEATING
PLANE
0.08 MAX LEAD
COPLANARITY
0.15
0.05
1.45
1.40
1.35
89
44
45
1.60 MAX
DETAIL A
88
0.50 BSC
LEAD PITCH
DETAIL A
TOP VIEW (PINS DOWN)
NOTES:
1. DIMENSIONS IN MILLIMETERS.
2. ACTUAL POSITION OF EACH LEAD IS WITHIN 0.08 OF ITS IDEAL POSITION,
WHEN MEASURED IN THE LATERAL DIRECTION.
3. CENTER DIMENSIONS ARE NOMINAL.
4. DIMENSIONS COMPLY WITH JEDEC STANDARD MS-026-BGA.
REV. 0
–41–
ADSP-21991
ORDERING GUIDE
Part Number
Ambient Temperature Range Instruction Rate Operating Voltage
Package
ADSP-21991BBC
ADSP-21991BST
–40ºC to +85ºC
–40ºC to +85ºC
196-Ball Mini-BGA
176-Lead LQFP
150 MHz
160 MHz
–42–
2.5 Int./3.3 Ext. V
2.5 Int./3.3 Ext. V
REV. 0
–43–
–44–
C02996–0–5/03(0)
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