Precision, Micropower Operational Amplifiers /

Precision, Micropower Operational Amplifiers /
Precision, Micropower
Operational Amplifiers
OP193/OP293
Data Sheet
PIN CONFIGURATIONS
Operates from +1.7 V to ±18 V
Low supply current: 15 µA/amplifier
Low offset voltage: 100 µV maximum
Outputs sink and source: ±8 mA
No phase reversal
Single- or dual-supply operation
High open-loop gain: 600 V/mV
Unity-gain stable
NULL 1
–IN A 2
OP193
+IN A 3
TOP VIEW
V– 4 (Not to Scale)
8
NC
7
V+
6
OUT A
5
NULL
NC = NO CONNECT
00295-001
FEATURES
Figure 1. 8-Lead SOIC_N
(S Suffix)
OUT A 1
Digital scales
Strain gages
Portable medical equipment
Battery-powered instrumentation
Temperature transducer amplifier
–IN A 2
+IN A 3
8
OP293
TOP VIEW
V– 4 (Not to Scale)
V+
7
OUT B
6
–IN B
5
+IN B
00295-002
APPLICATIONS
Figure 2. 8-Lead SOIC_N
(S Suffix)
GENERAL DESCRIPTION
The OP193/OP293 are single-supply operational amplifiers that
feature a combination of high precision, low supply current, and
the ability to operate at low voltages. For high performance in
single-supply systems, the input and output ranges include
ground, and the outputs swing from the negative rail to within
600 mV of the positive supply. For low voltage operation, the
OP193/OP293 can operate down to +1.7 V or ±0.85 V.
The combination of high accuracy and low power operation
make the OP193/OP293 useful for battery-powered equipment.
The part’s low current drain and low voltage operation allow it
to continue performing long after other amplifiers have ceased
functioning either because of battery drain or headroom.
The OP193/OP293 are specified for single +2 V through dual
±15 V operation over the extended (−40°C to +125°C) temperature
range. They are available in SOIC surface-mount packages.
Rev. D
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OP193/OP293
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Input Overvoltage Protection ................................................... 14
Applications ....................................................................................... 1
Output Phase Reversal—OP193............................................... 14
General Description ......................................................................... 1
Output Phase Reversal—OP293............................................... 14
Pin Configurations ........................................................................... 1
Battery-Powered Applications .................................................. 14
Revision History ............................................................................... 2
A Micropower False-Ground Generator................................. 15
Specifications..................................................................................... 3
A Battery-Powered Voltage Reference ..................................... 15
Electrical Specifications ............................................................... 3
A Single-Supply Current Monitor ............................................ 15
Absolute Maximum Ratings............................................................ 8
A Single-Supply Instrumentation Amplifier .......................... 16
Thermal Resistance ...................................................................... 8
A Low Power, Temperature to 4 mA to 20 mA Transmitter ...16
ESD Caution .................................................................................. 8
A Micropower Voltage Controlled Oscillator ........................ 17
Typical Performance Characteristics ............................................. 9
Outline Dimensions ....................................................................... 18
Functional Description .................................................................. 13
Ordering Guide .......................................................................... 18
Driving Capacitive Loads .......................................................... 13
REVISION HISTORY
1/15—Rev. C to Rev. D
Changed Minimum Output Voltage Swing High Parameter
from 4.0 V to 3.9 V; Table 2 ............................................................. 4
Changes to Ordering Guide .......................................................... 18
9/09—Rev. B to Rev. C
Updated Format .................................................................. Universal
Deleted OP493 .................................................................... Universal
Changes to Features and General Description Sections.............. 1
Deleted 8-Lead Epoxy DIP Pin Configurations for OP193 and
OP293, and 14-Lead Epoxy DIP and 16-Lead Wide Body SOL
Pin Configurations for OP493 ........................................................ 1
Changes to Offset Voltage Parameter and Large Signal Voltage
Gain, RL = 100 kΩ, −10 V ≤ VOUT ≤ +10 V Parameter, and
Power Supply Rejection Ratio Parameter, Table 1........................ 3
Changes to Offset Voltage Parameter and Power Supply
Rejection Ratio Parameter, Table 2 ................................................ 4
Changes to Offset Voltage Parameter and Power Supply
Rejection Ratio Parameter, Table 3 ................................................ 6
Changes to Offset Voltage Parameter and Power Supply
Rejection Ratio Parameter, Table 4 ................................................ 7
Changes to Table 5 and Table 6 ....................................................... 8
Changes to Figure 3 to Figure 6 .......................................................9
Changes to Figure 10 and Figure 12............................................. 10
Changes to Functional Description Section and Figure 26 ...... 13
Deleted A Micropower, Single-Supply Quad Voltage Output
8-Bit DAC Section .......................................................................... 13
Deleted Figure 13; Renumbered Sequentially ............................ 14
Deleted A Single-Supply Micropower Quad ProgrammableGain Amplifier Section .................................................................. 14
Changes to Output Phase Reversal—OP293 Section, BatteryPowered Applications Section, and Figure 27 ............................ 14
Deleted Figure 14............................................................................ 15
Changes to Figure 31, A Single-Supply Current Monitor
Section, and Figure 32.................................................................... 15
Changes to A Low Power, Temperature to 4 mA to 20 mA
Transmitter Section and Figure 35 ............................................... 16
Updated Outline Dimensions ....................................................... 18
Changes to Ordering Guide .......................................................... 18
1/02—Rev. A to Rev. B
Deletion of Wafer Test Limits Table ................................................5
Deletion of Dice Characteristics Images ........................................6
Edits to Ordering Guide ...................................................................6
Rev. D | Page 2 of 20
Data Sheet
OP193/OP293
SPECIFICATIONS
ELECTRICAL SPECIFICATIONS
VS = ±15.0 V, TA = 25°C, unless otherwise noted.
Table 1.
Parameter
INPUT CHARACTERISTICS
Offset Voltage
Symbol
Conditions
VOS
OP193
OP193, −40°C ≤ TA ≤ +125°C
OP293
OP293, −40°C ≤ TA ≤ +125°C
VCM = 0 V, −40°C ≤ TA ≤ +125°C
VCM = 0 V, −40°C ≤ TA ≤ +125°C
Input Bias Current
Input Offset Current
Input Voltage Range
Common-Mode Rejection
IB
IOS
VCM
CMRR
Large Signal Voltage Gain
AVO
Large Signal Voltage Gain
Large Signal Voltage Gain
AVO
AVO
Long-Term Offset Voltage1
Offset Voltage Drift2
OUTPUT CHARACTERISTICS
Output Voltage Swing High
VOH
Output Voltage Swing Low
VOL
Short-Circuit Current
POWER SUPPLY
Power Supply Rejection Ratio
ISC
Supply Current per Amplifier
ISY
NOISE PERFORMANCE
Voltage Noise Density
Current Noise Density
Voltage Noise
Min
−14.9 V ≤ VCM ≤ +14 V
−14.9 V ≤ VCM ≤ +14 V,
−40°C ≤ TA ≤ +125°C
RL = 100 kΩ,
−10 V ≤ VOUT ≤ +10 V
−40°C ≤ TA ≤ +85°C
−40°C ≤ TA ≤ +125°C
RL = 10 kΩ,
−10 V ≤ VOUT ≤ +10 V
−40°C ≤ TA ≤ +85°C
−40°C ≤ TA ≤ +125°C
RL = 2 kΩ,
−10 V ≤ VOUT ≤ +10 V
−40°C ≤ TA ≤ +85°C
−40°C ≤ TA ≤ +125°C
−14.9
100
97
500
300
en
in
en p-p
100
200
15
2
+13.5
116
600
200
125
VS = ±1.5 V to ±18 V
−40°C ≤ TA ≤ +125°C
VOUT = 0 V, VS = ±18 V,
−40°C ≤ TA ≤ +125°C, RL = ∞
100
97
150
250
250
350
20
4
+13.5
116
600
150
V/mV
V/mV
V/mV
100
14.1
−14.7
+14.2
±25
300
14.1
14.0
13.9
−14.6
−14.4
−14.1
120
14.2
14.1
−14.7
+14.2
±25
97
94
−14.6
−14.4
−14.1
120
30
65
0.05
3
μV
μV
μV
μV
nA
nA
V
dB
dB
300
150
1.75
14.2
Unit
V/mV
V/mV
V/mV
200
125
100
14.1
14.0
13.9
F Grade
Typ
Max
350
200
150
IL = 1 mA
IL = 1 mA, −40°C ≤ TA ≤ +125°C
IL = 5 mA
IL = −1 mA
IL = −1 mA,
−40°C ≤ TA ≤ +125°C
IL = −5 mA
Rev. D | Page 3 of 20
−14.9
97
94
500
300
350
200
0.2
f = 1 kHz
f = 1 kHz
0.1 Hz to 10 Hz
Min
300
VOS
ΔVOS/ΔT
PSRR
E Grade
Typ
Max
30
65
0.05
3
V/mV
V/mV
V/mV
μV
μV/°C
V
V
V
V
V
V
mA
dB
dB
μA
nV/√Hz
pA/√Hz
μV p-p
OP193/OP293
Parameter
DYNAMIC PERFORMANCE
Slew Rate
Gain Bandwidth Product
Channel Separation
1
2
Data Sheet
Symbol
Conditions
SR
GBP
RL = 2 kΩ
Min
E Grade
Typ
Max
Min
15
35
120
VOUT = 10 V p-p, RL = 2 kΩ,
f = 1 kHz
F Grade
Typ
Max
15
35
120
Unit
V/ms
kHz
dB
Long-term offset voltage is guaranteed by a 1000 hour life test performed on three independent lots at 125 °C, with an LTPD of 1.3.
Offset voltage drift is the average of the −40°C to +25°C delta and the +25°C to +125°C delta.
VS = 5.0 V, VCM = 0.1 V, TA = 25°C, unless otherwise noted.
Table 2.
Parameter
INPUT CHARACTERISTICS
Offset Voltage
Symbol
Conditions
VOS
OP193
OP193, −40°C ≤ TA ≤ +125°C
OP293
OP293, −40°C ≤ TA ≤ +125°C
−40°C ≤ TA ≤ +125°C
−40°C ≤ TA ≤ +125°C
Input Bias Current
Input Offset Current
Input Voltage Range
Common-Mode Rejection
IB
IOS
VCM
CMRR
Large Signal Voltage Gain
AVO
Large Signal Voltage Gain
Long-Term Offset Voltage1
Offset Voltage Drift2
OUTPUT CHARACTERISTICS
Output Voltage Swing High
Output Voltage Swing Low
E Grade
Min
Typ
Max
AVO
0.1 V ≤ VCM ≤ 4 V
0.1 V ≤ VCM ≤ 4 V,
−40°C ≤ TA ≤ +125°C
RL = 100 kΩ,
0.03 V ≤ VOUT ≤ 4.0 V
−40°C ≤ TA ≤ +85°C
−40°C ≤ TA ≤ +125°C
RL = 10 kΩ,
0.03 V ≤ VOUT ≤ 4.0 V
−40°C ≤ TA ≤ +85°C
−40°C ≤ TA ≤ +125°C
0
100
92
VOL
Short-Circuit Current
POWER SUPPLY
Power Supply Rejection Ratio
ISC
Supply Current per Amplifier
ISY
PSRR
116
200
125
VS = ±1.7 V to ±6.0 V
−40°C ≤ TA ≤ +125°C
VCM = 2.5 V, RL = ∞
Rev. D | Page 4 of 20
70
150
1.25
4.4
4.4
4.4
140
300
4.1
4.0
3.9
160
700
±8
100
94
120
4.4
140
V
V
mV
14.5
160
220
700
±8
97
90
V/mV
V/mV
V/mV
μV
μV/°C
V
V
5
280
400
500
900
μV
μV
μV
μV
nA
nA
V
dB
dB
4.4
4.4
220
5
280
Unit
V/mV
V/mV
V/mV
75
50
70
4.0
3.9
116
130
75
50
4.1
150
250
250
350
20
4
4
200
125
0.2
IL = 100 μA
IL = 1 mA
IL = 1 mA,
−40°C ≤ TA ≤ +125°C
IL = 5 mA
IL = −100 μA
IL = −100 μA,
−40°C ≤ TA ≤ +125°C
No load
IL = −1 mA
IL = −1 mA, −40°C ≤ TA ≤ +125°C
IL = –5 mA
0
96
92
130
VOS
ΔVOS/ΔT
VOH
100
200
15
2
4
F Grade
Min
Typ
Max
120
14.5
400
500
900
mV
mV
mV
mV
mV
mA
dB
dB
μA
Data Sheet
Parameter
NOISE PERFORMANCE
Voltage Noise Density
Current Noise Density
Voltage Noise
DYNAMIC PERFORMANCE
Slew Rate
Gain Bandwidth Product
1
2
OP193/OP293
Min
E Grade
Typ
Max
Min
F Grade
Typ
Max
Symbol
Conditions
en
in
en p-p
f = 1 kHz
f = 1 kHz
0.1 Hz to 10 Hz
65
0.05
3
65
0.05
3
nV/√Hz
pA/√Hz
μV p-p
SR
GBP
RL = 2 kΩ
12
35
12
35
V/ms
kHz
Long-term offset voltage is guaranteed by a 1000 hour life test performed on three independent lots at 125 °C, with an LTPD of 1.3.
Offset voltage drift is the average of the −40°C to +25°C delta and the +25°C to +125°C delta.
Rev. D | Page 5 of 20
Unit
OP193/OP293
Data Sheet
VS = 3.0 V, VCM = 0.1 V, TA = 25°C, unless otherwise noted.
Table 3.
Parameter
Symbol
Conditions
INPUT CHARACTERISTICS
Offset Voltage
VOS
OP193
OP193, −40°C ≤ TA ≤ +125°C
OP293
OP293, −40°C ≤ TA ≤ +125°C
−40°C ≤ TA ≤ +125°C
−40°C ≤ TA ≤ +125°C
Input Bias Current
Input Offset Current
Input Voltage Range
Common-Mode Rejection
IB
IOS
VCM
CMRR
Large Signal Voltage Gain
AVO
Long-Term Offset Voltage1
Offset Voltage Drift2
VOH
Output Voltage Swing Low
VOL
Short-Circuit Current
POWER SUPPLY
Power Supply Rejection Ratio
ISC
Supply Current per Amplifier
ISY
DYNAMIC PERFORMANCE
Slew Rate
Gain Bandwidth Product
Channel Separation
1
2
0
97
90
PSRR
E Grade
Typ Max
100
200
15
2
2
116
100
75
0
94
87
IL = 1 mA
IL = 1 mA, –40°C ≤ TA ≤ +125°C
IL = 5 mA
IL = −1 mA
IL = −1 mA, −40°C ≤ TA ≤ +125°C
IL = −5 mA
2.1
1.9
1.9
VS = +1.7 V to +6 V
−40°C ≤ TA ≤ +125°C
VCM = 1.5 V, RL = ∞
−40°C ≤ TA ≤ +125°C
100
94
F Grade
Typ Max
150
250
250
350
20
4
2
116
100
75
0.2
VS
Min
100
VOS
ΔVOS/ΔT
OUTPUT CHARACTERISTICS
Output Voltage Swing High
Supply Voltage Range
NOISE PERFORMANCE
Voltage Noise Density
Current Noise Density
Voltage Noise
0.1 ≤ VCM ≤ 2 V
0.1 ≤ VCM ≤ 2 V,
−40°C ≤ TA ≤ +125°C
RL = 100 kΩ,
0.03 V ≤ VOUT ≤ 2 V
−40°C ≤ TA ≤ +85°C
−40°C ≤ TA ≤ +125°C
Min
100
150
1.25
2.14
2.1
280
700
±8
300
2.1
1.9
1.9
400
500
900
2.14
2.1
280
700
±8
400
500
900
97
90
14.5
+2
22
22
±18
14.5
+2
22
22
±18
Unit
μV
μV
μV
μV
nA
nA
V
dB
dB
V/mV
V/mV
V/mV
μV
μV/°C
V
V
V
mV
mV
mV
mA
dB
dB
μA
μA
V
en
in
en p-p
f = 1 kHz
f = 1 kHz
0.1 Hz to 10 Hz
65
0.05
3
65
0.05
3
nV/√Hz
pA/√Hz
μV p-p
SR
GBP
RL = 2 kΩ
10
25
120
10
25
120
V/ms
kHz
dB
VOUT = 10 V p-p, RL = 2 kΩ,
f = 1 kHz
Long-term offset voltage is guaranteed by a 1000 hour life test performed on three independent lots at 125 °C, with an LTPD of 1.3.
Offset voltage drift is the average of the –40°C to +25°C delta and the +25°C to +125°C delta.
Rev. D | Page 6 of 20
Data Sheet
OP193/OP293
VS = 2.0 V, VCM = 0.1 V, TA = 25°C, unless otherwise noted.
Table 4.
Parameter
INPUT CHARACTERISTICS
Offset Voltage
Input Bias Current
Input Offset Current
Input Voltage Range
Large Signal Voltage Gain
Long-Term Offset Voltage
POWER SUPPLY
Power Supply Rejection Ratio
Symbol
Conditions
VOS
OP193
OP193, −40°C ≤ TA ≤ +125°C
OP293
OP293, −40°C ≤ TA ≤ +125°C
−40°C ≤ TA ≤ +125°C
−40°C ≤ TA ≤ +125°C
IB
IOS
VCM
AVO
Min
E Grade
Typ
Max
100
175
15
2
1
0
RL = 100 kΩ,
0.03 V ≤ VOUT ≤ 1 V
−40°C ≤ TA ≤ +125°C
60
Supply Current/Amplifier
ISY
Supply Voltage Range
NOISE PERFORMANCE
Voltage Noise Density
Current Noise Density
Voltage Noise
DYNAMIC PERFORMANCE
Slew Rate
Gain Bandwidth Product
VS
F Grade
Typ
Max
0
VS = 1.7 V to 6 V
−40°C ≤ TA ≤ +125°C
VCM = 1.0 V, RL = ∞
−40°C ≤ TA ≤ +125°C
μV
μV
μV
μV
nA
nA
V
300
V/mV
V/mV
μV
20
25
±18
dB
dB
μA
μA
V
70
150
100
94
97
90
13.2
+2
20
25
±18
13.2
+2
Unit
150
250
250
350
20
4
1
60
70
VOS
PSRR
Min
en
in
en p-p
f = 1 kHz
f = 1 kHz
0.1 Hz to 10 Hz
65
0.05
3
65
0.05
3
nV/√Hz
pA/√Hz
μV p-p
SR
GBP
RL = 2 kΩ
10
25
25
V/ms
kHz
Rev. D | Page 7 of 20
OP193/OP293
Data Sheet
ABSOLUTE MAXIMUM RATINGS
Table 5.
Parameter
Supply Voltage1
Input Voltage1
Differential Input Voltage1
Output Short-Circuit Duration to GND
Storage Temperature Range
Operating Temperature Range
Junction Temperature Range
Lead Temperature (Soldering, 60 sec)
1
Rating
±18 V
±18 V
±18 V
Indefinite
−65°C to +150°C
−40°C to +125°C
−65°C to +150°C
300°C
For supply voltages less than ±18 V, the input voltage is limited to the
supply voltage.
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
THERMAL RESISTANCE
θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages.
Table 6. Thermal Resistance
Package Type
8-Lead SOIC_N (S)
1
θJA1
158
θJC
43
Unit
°C/W
θJA is specified for the worst-case conditions. θJA is specified for a device
soldered in a circuit board for the SOIC package.
ESD CAUTION
Rev. D | Page 8 of 20
Data Sheet
OP193/OP293
TYPICAL PERFORMANCE CHARACTERISTICS
150
200
VS = ±15V
–40°C ≤ TA ≤ +125°C
VS = ±15V
TA = 25°C
120
NUMBER OF AMPLIFIERS
120
80
90
60
–60
–45
–30
–15
0
15
30
45
60
75
OFFSET (µV)
0
00295-003
0
–75
1.0
0.8
Figure 6. TCVOS Distribution, VS = ±15 V
200
1
VS = 3V
VCM = 0.1V
TA = 25°C
160
VS = 5V
0
120
80
40
–40°C
–1
–2
+125°C
–3
–60
–45
–30
–15
0
15
30
45
60
75
OFFSET (µV)
–4
00295-004
0
–75
+25°C
0
1
2
3
4
5
COMMON-MODE VOLTAGE (V)
Figure 4. Offset Distribution, VS = +3 V
00295-007
INPUT BIAS CURRENT (nA)
NUMBER OF AMPLIFIERS
0.6
TCVOS (µV/°C)
Figure 3. Offset Distribution, VS = ±15 V
Figure 7. Input Bias Current vs. Common-Mode Voltage
150
120
VS = 3V
VCM = 0.1V
–40°C ≤ TA ≤ +125°C
5V ≤ VS ≤ 30V
TA = 25°C
100
120
–PSRR
80
PSRR (dB)
90
60
60
+PSRR
40
30
20
0
0
0.2
0.4
0.6
0.8
TCVOS (µV/°C)
1.0
00295-005
NUMBER OF AMPLIFIERS
0.4
0.2
0
00295-006
30
40
Figure 5. TCVOS Distribution, VS = +3 V
0
10
100
1k
FREQUENCY (Hz)
Figure 8. PSRR vs. Frequency
Rev. D | Page 9 of 20
10k
00295-008
NUMBER OF AMPLIFIERS
160
OP193/OP293
Data Sheet
120
0
TA = 25°C
60
VS = +5V
40
20
10k
1k
100
FREQUENCY (Hz)
–0.10
VS = +2V
VCM = 0.1V
–0.15
–0.20
–0.25
–50
00295-009
0
10
–0.05
20
–1
INPUT BIAS CURRENT (nA)
+SR = –SR
VS = ±15V
+SR = –SR
VS = +5V
10
25
50
75
100
125
–2
100
125
VS = ±15V
–3
VS = +2V
VCM = 0.1V
–5
–50
–25
0
25
50
75
100
125
TEMPERATURE (°C)
Figure 10. Slew Rate vs. Temperature
Figure 13. Input Bias Current vs. Temperature
40
25
+ISC
VS = ±15V
SUPPLY CURRENT (μA)
| –ISC |
VS = ±15V
20
| –ISC |
VS = +5V
–25
VS = ±18V
20
+ISC
VS = +5V
0
25
50
15
VS = +2V
VCM = 1V
10
5
75
100
TEMPERATURE (°C)
125
00295-011
SHORT-CIRCUIT CURRENT (mA)
75
00295-013
0
00295-010
–25
TEMPERATURE (°C)
0
–50
50
–4
5
10
25
Figure 11. Short-Circuit Current vs. Temperature
0
–50
–25
0
25
50
75
100
TEMPERATURE (°C)
Figure 14. Supply Current vs. Temperature
Rev. D | Page 10 of 20
125
00295-014
SLEW RATE (V/ms)
0
30
0
Figure 12. Input Offset Current vs. Temperature
25
0
–50
–25
TEMPERATURE (°C)
Figure 9. CMRR vs. Frequency
15
VS = ±15V
00295-012
VS = ±15V
80
CMRR (dB)
INPUT OFFSET CURRENT (nA)
100
Data Sheet
OP193/OP293
2500
5V ≤ VS ≤ 30V
TA = 25°C
VOLTAGE GAIN (V/mV)
2000
100
10
VS = ±15V
–10V ≤ VOUT ≤ +10V
1500
1000
VS = +5V
0.03V ≤ VOUT ≤ 4V
1
0.1
1
10
100
1k
FREQUENCY (Hz)
0
–50
75
125
100
1000
VOLTAGE GAIN (V/mV)
800
100
10
VS = ±15V
–10V ≤ VOUT ≤ +10V
600
400
VS = +5V
0.03V ≤ VOUT ≤ 4V
1
10
100
1k
FREQUENCY (Hz)
0
–50
100
DELTA
FROM VEE
75
125
100
VS = 5V
TA = 25°C
40
20
10
100
1k
CURRENT LOAD (µA)
10k
00295-017
1
–20
10
100
1k
10k
FREQUENCY (Hz)
Figure 20. Closed-Loop Gain vs. Frequency, VS = 5 V
Figure 17. Delta Output Swing vs. Current Load
Rev. D | Page 11 of 20
100k
00295-020
0
10
1
0.1
50
Figure 19. Voltage Gain (RL = 10 kΩ) vs. Temperature
GAIN (dB)
DELTA
FROM VCC
25
60
5V ≤ VS ≤ 30V
TA = 25°C
1k
0
TEMPERATURE (°C)
Figure 16. Current Noise Density vs. Frequency
10k
–25
00295-019
200
00295-016
CURRENT NOISE DENSITY (pA/ Hz)
50
25
Figure 18. Voltage Gain (RL = 100 kΩ) vs. Temperature
5V ≤ VS ≤ 30V
TA = 25°C
1
0.1
DELTA FROM SUPPLY RAIL (mV)
0
TEMPERATURE (°C)
Figure 15. Voltage Noise Density vs. Frequency
1k
–25
00295-018
500
00295-015
VOLTAGE NOISE DENSITY (nV/ Hz)
1k
OP193/OP293
Data Sheet
60
60
VS = ±15V
TA = 25°C
VS = 5V
40
PHASE
90
20
20
45
GAIN
0
0
PHASE (Degrees)
GAIN (dB)
GAIN (dB)
40
0
–20
1k
10k
100k
FREQUENCY (Hz)
–40
100
–90
1M
100k
10k
FREQUENCY (Hz)
Figure 21. Closed-Loop Gain vs. Frequency, VS = ±15 V
Figure 23. Open-Loop Gain and Phase vs. Frequency
60
60
VS = 5V
TA = 25°C
AV = 1
50mV ≤ VIN ≤ 150mV
LOADS TO GND
VS = ±15V
90
40
+OS = | –OS |
RL = 50kΩ
30
GAIN (dB)
40
+OS
RL = ∞
45
20
GAIN
0
0
20
–OS
RL = ∞
0
10
100
–20
+OS = | –OS |
RL = 10kΩ
1k
CAPACITIVE LOAD (pF)
10k
00295-022
10
Figure 22. Small Signal Overshoot vs. Capacitive Load
–40
100
–45
1k
10k
100k
–90
1M
FREQUENCY (Hz)
Figure 24. Open-Loop Gain and Phase vs. Frequency
Rev. D | Page 12 of 20
PHASE (Degrees)
PHASE
00295-024
50
OVERSHOOT (%)
1k
00295-023
100
00295-021
–20
10
–45
Data Sheet
OP193/OP293
FUNCTIONAL DESCRIPTION
V+
The OP193/OP293 operational amplifiers are single-supply,
micropower, precision amplifiers whose input and output ranges
both include ground. Input offset voltage (VOS) is only 100 μV
maximum, while the output delivers ±5 mA to a load. Supply
current is only 15 μA.
Q4
FROM
INPUT
STAGE
A simplified schematic of the input stage is shown in Figure 26.
The input transistors, Q1 and Q2, are PNP devices, which permit
the inputs to operate down to ground potential. The input transistors have resistors in series with the base terminals to protect
the junctions from overvoltage conditions. The second stage is
an NPN cascode that is buffered by an emitter follower before
driving the final PNP gain stage.
The OP193 includes connections to taps on the input load resistors, which can be used to null the input offset voltage, VOS.
The OP293 have two additional transistors, Q7 and Q8. The
behavior of these transistors is discussed in the Output Phase
Reversal— and Output Phase Reversal— sections.
The output stage, shown in Figure 25, is a noninverting NPN
totem-pole configuration. Current is sourced to the load by
Emitter Follower Q1, while Q2 provides current sink capability.
When Q2 saturates, the output is pulled to within 5 mV of
ground without an external pull-down resistor. The totem-pole
output stage supplies a minimum of 5 mA to an external load,
even when operating from a single 3.0 V power supply.
Q1
I3
I2
V–
Figure 25. OP193/OP293 Equivalent Output Circuit
By operating as an emitter follower, Q1 offers a high impedance
load to the final PNP collector of the input stage. Base drive to
Q2 is derived by monitoring Q1’s collector current. Transistor
Q5 tracks the collector current of Q1. When Q1 is on, Q5 keeps
Q4 off, and Current Source I1 keeps Q2 turned off. When Q1 is
driven to cutoff (that is, the output must move toward V−), Q5
allows Q4 to turn on. Q4’s collector current then provides the
base drive for Q3 and Q2, and the output low voltage swing is
set by Q2’s VCE,SAT, which is about 5 mV.
DRIVING CAPACITIVE LOADS
The OP193/OP293 amplifiers are unconditionally stable with
capacitive loads less than 200 pF. However, the small signal,
unity-gain overshoot improves if a resistive load is added. For
example, transient overshoot is 20% when driving a 1000 pF,
10 kΩ load. When driving large capacitive loads in unity-gain
configurations, an in-the-loop compensation technique is
recommended, as illustrated in Figure 30.
I2
I4
Q1
Q2
Q6
Q4
Q7
Q8
Q3
TO
OUTPUT
STAGE
D1
R1A
R2A
R1B
R2B
I5
I6
V–
NULLING
TERMINALS
(OP193 ONLY)
Figure 26. OP193/OP293 Equivalent Input Circuit
Rev. D | Page 13 of 20
00295-025
OP293
ONLY
I3
Q5
2kΩ
–INPUT
I1
00295-026
Q2
V+
2kΩ
OUTPUT
Q3
I1
+INPUT
Q5
OP193/OP293
Data Sheet
OUTPUT PHASE REVERSAL—OP293
The OP293 includes two lateral PNP transistors, Q7 and Q8, to
protect against phase reversal. If an input is brought more than
one diode drop (≈0.7 V) below ground, Q7 and Q8 combine to
level shift the entire cascode stage, including the bias to Q3 and
Q4, simultaneously. In this case, Q4 does not saturate and the
output remains low.
2
OP193
OP293
1
0
0
1000
2000
3000
4000
6000
5000
7000
HOURS
00295-027
The OP193’s input PNP collector-base junction can be forwardbiased if the inputs are brought more than one diode drop (0.7 V)
below ground. When this happens to the noninverting input,
Q4 of the cascode stage turns on and the output goes high. If
the positive input signal can go below ground, phase reversal
can be prevented by clamping the input to the negative supply
(that is, GND) with a diode. The reverse leakage of the diode
does add to the input bias current of the amplifier. If input bias
current is not critical, a 1N914 diode adds less than 10 nA of
leakage. However, its leakage current doubles for every 10°C
increase in ambient temperature. For critical applications, the
collector-base junction of a 2N3906 transistor adds only about
10 pA of additional bias current. To limit the current through
the diode under fault conditions, a 1 kΩ resistor is recommended
in series with the input. (The OP193’s internal current limiting
resistors do not protect the external diode.)
3
Figure 27. Lithium Sulfur Dioxide Cell Discharge Characteristic with
OP193/OP293 and 100 kΩ Loads Input Offset Voltage Nulling
The OP193 provides two offset nulling terminals that can be
used to adjust the OP193’s internal VOS. In general, operational
amplifier terminals should never be used to adjust system offset
voltages. The offset nulling circuit of Figure 28 provides about
±7 mV of offset adjustment range. A 100 kΩ resistor placed in
series with the wiper arm of the offset null potentiometer, as shown
in Figure 29, reduces the offset adjustment range to 400 μV and
is recommended for applications requiring high null resolution.
Offset nulling does not adversely affect TCVOS performance,
providing that the trimming potentiometer temperature coefficient does not exceed ±100 ppm/°C.
The OP293 does not exhibit output phase reversal for inputs up
to −5 V below V− at +25°C. The phase reversal limit at +125°C
is about −3 V. If the inputs can be driven below these levels, an
external clamp diode, as discussed in the previous section,
should be added.
V+
7
2
OP193
6
4
3
5
1
100kΩ
BATTERY-POWERED APPLICATIONS
OP193/OP293 series op amps can be operated on a minimum
supply voltage of 1.7 V, and draw only 13 μA of supply current
per amplifier from a 2.0 V supply. In many battery-powered circuits, OP193/OP293 devices can be continuously operated for
thousands of hours before requiring battery replacement, thus
reducing equipment downtime and operating cost.
High performance portable equipment and instruments frequently use lithium cells because of their long shelf life, light
weight, and high energy density relative to older primary cells.
Most lithium cells have a nominal output voltage of 3 V and are
noted for a flat discharge characteristic. The low supply voltage
requirement of the OP193/OP293, combined with the flat
discharge characteristic of the lithium cell, indicates that the
Rev. D | Page 14 of 20
V–
00295-028
OUTPUT PHASE REVERSAL—OP193
4
Figure 28. Offset Nulling Circuit
V+
7
2
OP193
6
4
3
5
1
100kΩ
100kΩ
V–
00295-029
As previously mentioned, the OP193/OP293 op amps use a
PNP input stage with protection resistors in series with the
inverting and noninverting inputs. The high breakdown of the
PNP transistors, coupled with the protection resistors, provides
a large amount of input protection from overvoltage conditions.
The inputs can therefore be taken 20 V beyond either supply
without damaging the amplifier.
OP193/OP293 can be operated over the entire useful life of the
cell. Figure 27 shows the typical discharge characteristic of a
1 Ah lithium cell powering the OP193 and OP293, with each
amplifier, in turn, driving 2.1 V into a 100 kΩ load.
LITHIUM SULFUR DIOXIDE
CELL VOLTAGE (V)
INPUT OVERVOLTAGE PROTECTION
Figure 29. High Resolution Offset Nulling Circuit
Data Sheet
OP193/OP293
A MICROPOWER FALSE-GROUND GENERATOR
Some single-supply circuits work best when inputs are biased
above ground, typically at ½ of the supply voltage. In these
cases, a false ground can be created by using a voltage divider
buffered by an amplifier. One such circuit is shown in Figure 30.
R1
240kΩ
V+
(2.5V TO 36V)
R2
1.5MΩ
7
2
C1
1000pF
OP193
3
This circuit generates a false-ground reference at ½ of the supply
voltage, while drawing only about 27 μA from a 5 V supply.
The circuit includes compensation to allow for a 1 μF bypass
capacitor at the false-ground output. The benefit of a large
capacitor is that not only does the false ground present a very
low dc resistance to the load, but its ac impedance is low as well.
The OP193 can both sink and source more than 5 mA, which
improves recovery time from transients in the load current.
6
VOUT
(1.23V @ 25°C)
5
4
Q2
MAT01AH
1
7
2
Q1
6
+
+
3 VBE2
5 VBE1
–
V1
–
5V OR 12V
–
R3
68kΩ
ΔVBE
+
R4
130kΩ
00295-031
R5, 20kΩ
OUTPUT
ADJUST
10kΩ
+
0.022µF
240kΩ
Figure 31. A Battery-Powered Voltage Reference
3
240kΩ
+
1µF
4
6
A SINGLE-SUPPLY CURRENT MONITOR
100Ω
2.5V OR 6V
+
1µF
Figure 30. A Micropower False-Ground Generator
A BATTERY-POWERED VOLTAGE REFERENCE
The circuit of Figure 31 is a battery-powered voltage reference
that draws only 17 μA of supply current. At this level, two AA
alkaline cells can power this reference for more than 18 months.
At an output voltage of 1.23 V at 25°C, drift of the reference is
only 5.5 μV/°C over the industrial temperature range. Load
regulation is 85 μV/mA with line regulation at 120 μV/V.
Design of the reference is based on the Brokaw band gap core
technique. Scaling of Resistor R1 and Resistor R2 produces
unequal currents in Q1 and Q2. The resulting ΔVBE across R3
creates a temperature-proportional voltage (PTAT), which, in
turn, produces a larger temperature-proportional voltage across
R4 and R5, V1. The temperature coefficient of V1 cancels (first
order) the complementary to absolute temperature (CTAT)
coefficient of VBE1. When adjusted to 1.23 V at 25°C, output
voltage temperature coefficient is at a minimum. Band gap
references can have start-up problems. With no current in R1
and R2, the OP193 is beyond its positive input range limit and
has an undefined output state. Shorting Pin 5 (an offset adjust
pin) to ground forces the output high under these circumstances
and ensures reliable startup without significantly degrading the
OP193’s offset drift.
Current monitoring essentially consists of amplifying the voltage
drop across a resistor placed in series with the current to be
measured. The difficulty is that only small voltage drops can be
tolerated, and with low precision op amps, this greatly limits the
overall resolution. The single-supply current monitor of Figure 32
has a resolution of 10 μA and is capable of monitoring 30 mA
of current. This range can be adjusted by changing the current
sense resistor, R1. When measuring total system current, it may
be necessary to include the supply current of the current monitor,
which bypasses the current sense resistor, in the final result.
This current can be measured and calibrated (together with the
residual offset) by adjustment of the offset trim potentiometer,
R2. This produces a deliberate temperature dependent offset.
However, the supply current of the OP193 is also proportional
to temperature, and the two effects tend to track. Voltage developed at the noninverting input and amplified by (1 + R4/R5)
appears at VOUT.
V+
+
TO CIRCUIT
UNDER TEST
–
7
3
OP193
ITEST
6
4
2
5
VOUT =
100mV/mA(I TEST )
1
R4
9.9kΩ
R1
1Ω
R2
100kΩ
R5
100Ω
R3
100kΩ
Figure 32. Single-Supply Current Monitor
Rev. D | Page 15 of 20
00295-032
OP193
00295-030
2
7
OP193/OP293
Data Sheet
A SINGLE-SUPPLY INSTRUMENTATION AMPLIFIER
R1
20kΩ
Designing a true single-supply instrumentation amplifier with
zero-input and zero-output operation requires special care. The
traditional configuration, shown in Figure 33, depends upon
Amplifier A1’s output being at 0 V when the applied commonmode input voltage is at 0 V. Any error at the output is multiplied
by the gain of A2. In addition, current flows through Resistor R3
as A2’s output voltage increases. A1’s output must remain at 0 V
while sinking the current through R3, or a gain error results. With
a maximum output voltage of 4 V, the current through R3 is
only 2 μA, but this still produces an appreciable error.
5V
–IN
5V
10kΩ
5V
Q2
V+
A2
1/2 OP293
–
VN2222
+
+IN
R2
1.98MΩ
V–
Figure 34. An Improved Single-Supply, 0 VIN, 0 VOUT Instrumentation Amplifier
R3
20kΩ
V+
–
A1
1/2 OP293
+
V–
A LOW POWER, TEMPERATURE TO 4 mA TO 20 mA
TRANSMITTER
R4
1.98MΩ
5V
V+
A2
1/2 OP293
–
+
+IN
A simple temperature to 4 mA to 20 mA transmitter is shown
in Figure 35. After calibration, this transmitter is accurate to
±0.5°C over the −50°C to +150°C temperature range. The
transmitter operates from 8 V to 40 V with supply rejection
better than 3 ppm/V. One half of the OP293 is used to buffer
the TEMP pin, and the other half regulates the output current
to satisfy the current summation at its noninverting input.
VOUT
00295-033
ISINK
V–
Figure 33. A Conventional Instrumentation Amplifier
One solution to this problem is to use a pull-down resistor. For
example, if R3 = 20 kΩ, then the pull-down resistor must be less
than 400 Ω. However, the pull-down resistor appears as a fixed
load when a common-mode voltage is applied. With a 4 V
common-mode voltage, the additional load current is 10 mA,
which is unacceptable in a low power application.
I OUT +
VTEMP × (R6 + R7 )
R2 × R10
 R2 + R6 + R7 

− VSET 
 R2 × R10 


The change in output current with temperature is the derivative
of the following transfer function:
Figure 34 shows a better solution. A1’s sink current is provided
by a pair of N-channel FET transistors, configured as a current
mirror. With the values shown, the sink current of Q2 is about
340 μA. Thus, with a common-mode voltage of 4 V, the additional load current is limited to 340 μA vs. 10 mA with a 400 Ω
resistor.
∆I OUT
∆T
∆VTEMP
(R6 + R7 )
= ∆T
R2 × R10
1N4002
V+
8V TO 40V
SPAN TRIM
R4
20kΩ
REF43GPZ
2
VIN 2
TEMP
GND 4
8
–
1/2
VOUT 6
3
VOUT
00295-034
Q1
5V
–IN
R4
1.98MΩ
R3
20kΩ
V+
A1
1/2 OP293
+
V–
–
3
R1, 10kΩ
1
R2
VTEMP 1kΩ
R6
3kΩ
R7
5kΩ
6
OP293
–
+
OP293
4
1/2
R3
100kΩ
R5
5kΩ
VSET
5
+
ZERO
TRIM
7
R8
1kΩ
2N1711
R9
100kΩ
R10
100Ω
1%, 1/2 W
IOUT
NOTES
1. ALL RESISTORS 1/4 W, 5% UNLESS OTHERWISE NOTED.
Figure 35. Temperature to 4 mA to 20 mA Transmitter
Rev. D | Page 16 of 20
RLOAD
00295-035
R1
20kΩ
R2
1.98MΩ
Data Sheet
OP193/OP293
From the formulas, it can be seen that if the span trim is adjusted
before the zero trim, the two trims are not interactive, which
greatly simplifies the calibration procedure.
Calibration of the transmitter is simple. First, the slope of the
output current vs. temperature is calibrated by adjusting the
span trim, R7. A couple of iterations may be required to be sure
the slope is correct.
C1
75nF
R1
200kΩ
2
3
R2
200kΩ
+
R4
200kΩ
1
6
R8
200kΩ
–
A2
1/2 OP293
4
7
SQUARE
OUT
+
TRIANGLE
OUT
R6
200kΩ
The zero trim can be set at any known temperature by adjusting
R5 until the output current equals:
R7
200kΩ
5V
CD4066

(TAMBIENT − TMIN ) + 4 mA


1 IN/OUT
VDD
14
5V
S1
Table 7 shows the values of R6 required for various temperature
ranges.
Table 7. R6 Values vs. Temperature
Temp Range
0°C to 70°C
−40°C to +85°C
−55°C to +150°C
8
–
A1
1/2 OP293
5
When the span trim has been adjusted, the zero trim can be
made. Adjusting the zero trim does not affect the gain.

∆I FS
I OUT = 
 ∆TOPERATING
R5
200kΩ
5V
VCONTROL
R3
100kΩ
5V
R6
10 kΩ
6.2 kΩ
3 kΩ
2
OUT/IN
3
OUT/IN
4
IN/OUT
5
CONT
6
CONT
CONT 13
S2
CONT 12
IN/OUT 11
S3
OUT/IN 10
OUT/IN 9
5V
S4
7
IN/OUT 8
00295-036
A MICROPOWER VOLTAGE CONTROLLED
OSCILLATOR
VSS
The OP293 CMOS analog switch forms the precision VCO of
Figure 36. This circuit provides triangle and square wave
outputs and draws only 50 μA from a single 5 V supply. A1 acts
as an integrator; S1 switches the charging current symmetrically
to yield positive and negative ramps. The integrator is bounded
by A2, which acts as a Schmitt trigger with a precise hysteresis
of 1.67 V, set by Resistor R5, Resistor R6, and Resistor R7, and
associated CMOS switches. The resulting output of A1 is a
triangle wave with upper and lower levels of 3.33 V and 1.67 V.
The output of A2 is a square wave with almost rail-to-rail swing.
With the components shown, frequency of operation is given by
the equation:
fOUT = VCONTROL V × 10 Hz/V
However, the frequency can easily be changed by varying C1.
The circuit operates well up to 500 Hz.
Rev. D | Page 17 of 20
Figure 36. Micropower Voltage Controlled Oscillator
OP193/OP293
Data Sheet
OUTLINE DIMENSIONS
5.00 (0.1968)
4.80 (0.1890)
1
5
4
1.27 (0.0500)
BSC
0.25 (0.0098)
0.10 (0.0040)
COPLANARITY
0.10
SEATING
PLANE
6.20 (0.2441)
5.80 (0.2284)
1.75 (0.0688)
1.35 (0.0532)
0.51 (0.0201)
0.31 (0.0122)
0.50 (0.0196)
0.25 (0.0099)
45°
8°
0°
0.25 (0.0098)
0.17 (0.0067)
1.27 (0.0500)
0.40 (0.0157)
COMPLIANT TO JEDEC STANDARDS MS-012-AA
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
012407-A
8
4.00 (0.1574)
3.80 (0.1497)
Figure 37. 8-Lead Standard Small Outline Package [SOIC_N]
Narrow Body (R-8)
Dimensions shown in millimeters and (inches)
ORDERING GUIDE
Model1
OP193FS-REEL
OP193FSZ
OP193FSZ-REEL
OP193FSZ-REEL7
OP293ESZ
OP293ESZ-REEL
OP293ESZ-REEL7
OP293FSZ
OP293FSZ-REEL
OP293FSZ-REEL7
1
Temperature Range
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
Package Description
8-Lead SOIC_N
8-Lead SOIC_N
8-Lead SOIC_N
8-Lead SOIC_N
8-Lead SOIC_N
8-Lead SOIC_N
8-Lead SOIC_N
8-Lead SOIC_N
8-Lead SOIC_N
8-Lead SOIC_N
Z = RoHS Compliant Part.
Rev. D | Page 18 of 20
Package Option
S-Suffix (R-8)
S-Suffix (R-8)
S-Suffix (R-8)
S-Suffix (R-8)
S-Suffix (R-8)
S-Suffix (R-8)
S-Suffix (R-8)
S-Suffix (R-8)
S-Suffix (R-8)
S-Suffix (R-8)
Data Sheet
OP193/OP293
NOTES
Rev. D | Page 19 of 20
OP193/OP293
Data Sheet
NOTES
©1995–2015 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D00295-0-1/15(D)
Rev. D | Page 20 of 20
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