EVAL-AD76XXEDZ: Evaluation Board For PulSAR 48 Lead ADCs PDF

EVAL-AD76XXEDZ: Evaluation Board For PulSAR 48 Lead ADCs PDF
Evaluation Board For PulSAR 48 Lead ADCs
Preliminary Technical Data
EVAL-AD76XXEDZ
www.Analog.com/PulSAR and should be consulted when
utilizing this evaluation board.
FEATURES
Converter and Evaluation Development (EVAL-CED1Z)
compatibility
Versatile analog signal conditioning circuitry
On-board reference, clock oscillator and buffers
Buffered 14, 16 (or 18) bit parallel outputs
Buffered serial port interface
Ideal for DSP and data acquisition card interfaces
Analog and digital prototyping area
PC software for control and data analysis
The evaluation board is ideal for use with Analog Devices USB
based Converter and Evaluation Development EVAL-CED1Z,
(CED) or as a stand-alone system. These boards are also
compatible for use with the EVAL-CONTROL BRDxZ capture
board and software for using this board is available on the
website. Since many newer PC’s do not offer a parallel port
along with overcomplicated BIOS port settings, the CED board
is strongly recommended.
GENERAL DESCRIPTION
The EVAL-AD76XXEDZ is an evaluation board for the 48 lead
AD761X, AD762X, AD763X, AD764X, AD765X, AD766X,
AD767X and AD795X 14-bit, 16-bit and 18- bit PulSAR®
analog to digital converter (ADC) family. These low power,
successive approximation register (SAR) architecture ADCs (see
ordering guide for product list ) offer very high performance
with 100kSPS to 3MSPS throughput rate range with a flexible
parallel or serial interface. The evaluation board is designed to
demonstrate the ADC's performance and to provide an easy to
understand interface for a variety of system applications. A full
description of the ADCs for this board are available at
The design offers the flexibility of applying external control
signals and is capable of generating conversion results on
parallel 14-bit, 16-bit or 18-bit wide buffered outputs. On-board
components include a high precision band gap reference,
(AD780, ADR431, or ADR435), reference buffers, a signal
conditioning circuit with two op-amps and digital logic.
The EVAL-AD76XXEDZ interfaces to the CED capture board
with a 96-pin DIN connector. A 40-pin IDC connector is used
for parallel output, and test points are provided for the serial
port. SMB connectors are provided for the low noise analog
signal source, and for an externally generated CNVST (convert
start input.
External CNVST
Reference/Buffer
96-Pin CED/ECB
Interface
PulSAR ADC
Analog Inputs
Supplies
Figure 1. Evaluation Board
Rev. PrB
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2009 Analog Devices, Inc. All rights reserved.
EVAL-AD76XXCB
Preliminary Technical Data
TABLE OF CONTENTS
FEATURES ........................................................................................ 1
GENERAL DESCRIPTION ............................................................ 1
Overview........................................................................................ 3
Conversion Control/Master Clock............................................. 3
Analog Inputs................................................................................ 3
Power Supplies and Grounding .................................................. 3
Using the Eval-AD762X/AD765X/AD766X/ AD767XCBZ as
Stand-Alone................................................................................... 3
Evaluation Board Setting for Bipolar ADC Input
Configurations...............................................................................4
Hardware Setup .............................................................................4
Software Installation .....................................................................5
Running the Evaluation Software ..............................................6
Setup Screen...................................................................................6
DC Testing - Histogram ...............................................................6
AC Testing ......................................................................................6
Schematics/PCB Layout............................................................... 4
Evaluation Board Schematics and Artwork............................ 16
Supplying Power for Stand-Alone use ....................................... 4
Ordering Guide .......................................................................... 22
LIST OF FIGURES
Figure 1. Evaluation Board .............................................................. 1
Figure 9. Schematic, Digital........................................................... 17
Figure 2. Setup Screen .................................................................... 10
Figure 10. Schematic, Power.......................................................... 18
Figure 3. Context Help ................................................................... 11
Figure 11. Top Side Silk-Screen .................................................... 19
Figure 4. Histogram Screen ........................................................... 12
Figure 12. Top Layer....................................................................... 19
Figure 5. Summary.......................................................................... 13
Figure 13. Ground Layer................................................................ 20
Figure 6. FFT Spectrum ................................................................. 14
Figure 14. Shield Layer................................................................... 20
Figure 7. Oscilloscope .................................................................... 15
Figure 15. Bottom Side Layer ........................................................ 21
Figure 8. Schematic, Analog .......................................................... 16
Figure 16. Bottom Side Silk-Screen.............................................. 21
LIST OF TABLES
Table 1. CNVST Generation, Analog Input Range....................... 7
Table 2. Jumper Description............................................................ 8
Table 5.Test Points .............................................................................9
Table 6. Bill of Materials for the Connectors .............................. 22
Table 3. S16 - Configuration Select Switch Description.............. 8
Table 4. S35 - Configuration Select Switch Description.............. 8
Rev. PrB | Page 2 of 23
Preliminary Technical Data
EVAL-AD76XXEDZ
OVERVIEW
ANALOG INPUTS
Figure 1 shows the EVAL-AD76XXEDZ evaluation board.
When used in stand-alone mode or in conjunction with the
EVAL-CED1Z, the gate array, U10, provides the necessary
control signals for conversion and buffers the ADC data. The
evaluation board is a flexible design that enables the user to
choose among many different board configurations, analog
signal conditioning, reference, and different modes of
conversion data.
The analog inputs amplifier circuitry (U6, U7 and discretes)
allows configuration changes such as positive or negative gain,
input range scaling, filtering, addition of a DC component, use
of different op-amp and supplies depending on the ADC. The
analog input amplifiers are set as unity gain buffers at the
factory. The supplies are selectable with solder pads and are set
for the ±12V range.
CONVERSION CONTROL/MASTER CLOCK
Conversion start (CNVST) controls the sample rate of the ADC
and is the only input needed for conversion; all SAR timing is
generated internally. CNVST is generated either by the gate
array or externally via J3 (SMB) and setting JP22 in the external
(EXT) position. The evaluation board is factory configured for
the CNVST range shown in Table 1. Externally generated
CNVST should have very low jitter and sharp edges for the
maximum dynamic performance of the part. Since CNVST
jitter usually results in poor SNR performance, it is
recommended to use the on-board CNVST generation
whenever possible.
The master clock (MCLK) source for the gate array is generated
from the CED capture board or from U12, the 40MHz local
oscillator selectable when using the accompanying software.
The range for CNVST in
Table 1is a ratio generated from this master clock. In standalone mode, other clock frequencies can be used to change the
gate array generated CNVST by this ratio. However, other
timings will be affected – namely the slave serial clock (SCLK)
interface. In serial slave mode, SCLK = MCLK.
While the ADC is converting, activity on the BUSY pin turns on
the LED, D2. Additionally, the BUSY signal can be monitored
test point TP1. Buffered conversion data (BD) is available at
U10 on the output bus BD[0:15] on the 40-pin IDC connector
P2, and on the 96-pin connector P3. When operating with the
CED, data is transferred using a 16 bit bus and corresponding
word and byte modes selectable with the software. For the 18 bit
converters two consecutive 16 bit words are read, however, the
ADC data is still read into the gate array as 18 bits. Additionally,
BD is updated on the falling edge of BBUSY on P3-C17, and on
the rising edge of DBUSY on P2-33. When either parallel or
serial reading mode of the ADC is used, data is available on this
parallel bus.
When using Serial Mode, serial data is available at T3, T4, T5,
and T6 (SDOUT, SCLK, SYNC and RDERROR) and buffered
serial data is output on TP17, TP18, and TP19 (SCLK, SYNC,
and SDOUT). When using Slave Serial Mode, the external serial
clock SCLK applied to the ADC is the MCLK, U12, frequency
(40MHz). Refer to the device specific datasheet for full details
of the interface modes.
Table 1 shows the analog input range for the available
evaluation boards.
The default configuration for the single ended (SE) unipolar
ADCs sets U6 at mid-scale from the voltage divider (VCM *
R6/(R6+R7)) and U7 at mid-scale from the voltage divider (VCM
* R29(R29+R60)) for the differential unipolar ADCs.
For the bipolar devices (AD7663, AD665, AD7671), the buffer
output is centered at 0V (mid-scale) as these boards are
configured for the +/-5V input range. Note the input impedance
is 1k ohm (R6, R29 =1k ohm to GND). To use another input
range, the solder pads S[7:1] need to be reconfigured.
These input configurations allows a transition noise test
(histogram) without any other equipment. In some applications,
it is desired to use a bipolar or wider analog input range, for
instance, ± 10V, ± 5V, ± 2.5V, or 0 to -5V. For ADCs which do
not use these input ranges directly, simple modifications of the
input driver circuitry can be made without any performance
degradation. Refer to the datasheet under the Application Hints
section for component values or to application note AN594 on
the product web page for other input ranges.
Note that the AD7663, AD7665, and AD7671 evaluation boards
are factory configured for the +/-5V range. For different ranges,
the board needs appropriate solder pad configurations.
For dynamic performance, an FFT test can be done by applying
a very low distortion AC source.
POWER SUPPLIES AND GROUNDING
The evaluation board ground plane is separated into two
sections: a plane for the digital interface circuitry and an analog
plane for the analog input and external reference circuitry. To
attain high resolution performance, the board was designed to
ensure that all digital ground return paths do not cross the
analog ground return paths by connecting the planes together
directly under the converter. Power is supplied to the board
through P3 when using with the EVAL-CED1Z
USING THE EVAL-AD762X/AD765X/AD766X/
AD767XEDZ AS STAND-ALONE
Using the evaluation board as stand-alone does not require the
CED nor does it require use of the accompanied software.
When the CONTROL input to the gate array is LOW, which is
pulled down by default, the gate array provides the necessary
signals for conversion and buffers the conversion data.
Rev. PrB | Page 3 of 23
EVAL-AD76XXEDZ
Preliminary Technical Data
In stand-alone mode, the gate arrays flexible logic buffers the
ADC data according to the read data mode configuration (word
or byte). In parallel reading mode the board is configured for
continuous reading since CS and RD are always driven LOW by
the gate array. Thus, the digital bus is not tri-stated in this mode
of operation and BD[0:15] will continuously be updated after a
new conversion. BD[0:15] is available on P2 after BUSY goes
HIGH. Note that with the 18 bit devices the full 18 bits of data
BD[-2:15] are output directly on P2 since the evaluation board
is not limited to 16 bit wide transfers in stand-alone operation.
When either parallel or serial reading mode, the data is available
on this parallel bus. Refer to Figure 9 to obtain the data output
pins on P2.
Configuration Switches
The evaluation board is configurable for the different operating
modes with 16 positions on the configuration select switches,
S16 and S35. A description of each switch setting and jumper
position is listed in Figure 9 and the available test points are
listed in Table 5. Note that the switches in the ON position
define a logic HIGH level (pulled up with 10kΩ,) and that the
switches are active only in stand-alone mode.
For all interface modes, S16 and S35 allows the selection of:
Warp, Normal or Impulse mode conversions (where applicable)
Binary or 2s complement data output
Reading during or after conversion
Resetting the ADC
ADC power-down
Internal Reference and Buffer power-down (where applicable)
In parallel reading mode, s16 allows the selection of:
Byte swapping for 8 bit interfacing (LSByte with MSByte)
18-bit, 16-bit and 8-bit interfacing (for 18-bit converters)
In serial reading mode, the default settings are Master Read
during Conversion Mode using the internal ADC serial clock.
Serial data is available at T3, T4, T5 and T6 for SDOUT, SCLK,
SYNC and RDERROR respectively. Buffered serial data is
output on the three test points TP17, TP18 and TP19 for SCLK,
SYNC, and SDOUT respectively.
For serial reading mode, S16 allows the selection of:
Choice of inverting SCLK and SYNC
Choice of using internal or external (slave mode) SCLK
SCHEMATICS/PCB LAYOUT
The EVAL-AD76XXEDZ is a 4-layer board carefully laid out
and tested to demonstrate the specific high accuracy
performance of the PulSAR ADC. Figure 8 to Figure 10 show
the schematics of the evaluation board. The printed circuit
layouts of the board are given in Figure 11 - Figure 16. Note
these layouts are not to scale.
Top side silk-screen - Figure 11
Top side layer - Figure 12
Ground layer - Figure 13
Shield layer - Figure 14
Bottom side layer - Figure 15
Bottom side silk-screen - Figure 16
SUPPLYING POWER FOR STAND-ALONE USE
Power needs to be supplied through the two power supply
blocks SJ1 and SJ2. Linear supplies are recommended. SJ1 is the
analog supply for the ADC (AVDD), front end op amps and
reference circuitry. SJ2 is the digital supply for the ADC
(DVDD, OVDD) and gate array. The supplies to the device are
configurable through the power supply jumpers shown in . In
most applications four supplies are required; ±12V and +5V for
analog, and +5V for digital. On board regulators, where
applicable, are used to reduce the operating voltages to the
correct levels. The analog and digital supplies can be from the
same source however, R27 (typically 20Ω) is required from
AVDD to DVDD. In this configuration, JP9, DVDD selection,
should be left open. Furthermore, the OVDD (ADC digital
output supply) may need to be brought up after the analog +5V
supply. See datasheet for details.
EVALUATION BOARD SETTING FOR BIPOLAR ADC
INPUT CONFIGURATIONS
The AD7610, AD7612, AD7631, AD7634, AD7663, AD7665,
AD7671, AD7951 and AD7952 can use both unipolar and
bipolar ranges. The available options are +/-10V, +/-5V, +/-2.5V,
0 to 10V, 0 to 5V and 0 to 2.5V (depending on the ADC).
For the AD7663, AD7665 and AD7671 the evaluation board is
set for the ±5V bipolar input range since these ADCs input
ranges are hardware pin strapped. Simple modifications to these
evaluation boards can be made to accommodate the different
input ranges by changing the INA-IND inputs with the available
solder pads.
iCMOS ADCs
For the AD7610, AD7612, AD7631 AD7634 and AD7951, the
evaluation board can use all input ranges since the input range
is controlled by software (or S16 DIP switches in stand-alone
mode).
For operating in unipolar mode for any of the bipolar
evaluation boards it is recommended to use the voltage divider
consisting of (VCM * R6/(R6+R7)) and (VCM * R29/(R29+R60)).
This allows a transition noise test without any additional
equipment.
HARDWARE SETUP
Using EVAL-CED1Z Capture Board
•
•
•
•
•
•
•
Rev. PrB | Page 4 of 23
EVAL-AD76XXEDZ PulSAR ADC evaluation board
EVAL-CED1Z
Enclosed World compatible 7V DC supply
Enclosed USB to mini USB cable
DC source (low noise for checking different input ranges)
AC source (low distortion)
Band pass filter suitable for 16 or 18 bit testing (value based
on signal frequency)
Preliminary Technical Data
EVAL-AD76XXEDZ
• PC operating Windows XP.
Proceed to the Software Installation section to install the
software. Note: The EVAL-CED1Z board must not be
connected to the PC’s USB port until the Software is
installed. The 7V DC supply can be connected however to
check the board has power (green LED lit).
SOFTWARE INSTALLATION
It is recommended to close all Windows’ applications prior to
installing the software.
System Requirements
• PC operating Windows XP.
• USB 2.0 (for CED board)
• Administrator privileges
CD-ROM –Navigate to Software\CED Version x.x, double click
on setup.exe and follow the instructions on the screen. If
another version of Analog Devices PulSAR Evaluation Software
is present, it may be necessary to remove this. To remove, click
on the Windows “Start” button, select “Control Panel” and “Add
or Remove Programs”. When the list populates, navigate to
Analog Devices High Resolution sampling ADC’s Evaluation
Software or PulSAR Evaluation Software and select Remove.
When installed properly, Windows displays the following.
Website Download
The software versions are also available from the Analog
Devices PulSAR Analog to Digital Converter Evaluation Kit
page. After downloading the software, it is recommended to use
the WinZip “Extract” function to extract all of the necessary
components as opposed to just clicking on setup.exe in the
zipped file. After extracting, click on seteup.exe in the folder
created during the extraction and follow the instructions on the
screen. If another version exists, it may be necessary to remove
as detailed in the above CD-ROM section.
USB Drivers
The software will also install the necessary USB drivers. After
installing the software, power up the CED board and connect to
the PC USB 2.0 port. The Windows “Found New Hardware”
Wizard will display. Click on Next to install the drivers
automatically.
On some PCs, the Found New hardware Wizard may show up
again and if so follow the same procedure to install it properly.
The “Device Manager” can be used to verify that the driver was
installed successfully.
Troubleshooting the Install
If the driver was not installed successfully the device manager
will display a question mark for “Other devices” as Windows
does not recognize the CED1Z board.
Rev. PrB | Page 5 of 23
EVAL-AD76XXEDZ
Preliminary Technical Data
• Histogram for determining code transition noise (DC)
• Fast Fourier transforms (FFT) for signal to noise ratio
(SNR), SNR and distortion (SINAD), total harmonic
distortion (THD) and spurious free dynamic range (SFDR)
The software is located at C:\Program Files\Analog Devices\
PulSAR ADC Evaluation Software\Eval PulSAR CED.exe.
A shortcut is also added to the Windows “Start” menu under
“Analog Devices PulSAR ADC Evaluation Software”, “Eval
PulSAR CED”. To run the software, select the program from
either location.
SETUP SCREEN
Figure 2 is the setup screen where ADC device selection, test
type, input voltage range, sample rate and number of samples
are selected.
DC TESTING - HISTOGRAM
Figure 4 shows a screen shot for the histogram screen. This tests
the ADC for the code distribution for DC input and computes
the mean and standard deviation, or transition noise of the
converter and displays the results. Raw data is captured and
passed to the PC for statistical computations. To perform a
histogram test, select “Histogram” from the test selection
window and click on the “Start” radio button. Note: a histogram
test can be performed without an external source since the
evaluation board has a buffered VREF/2 source at the ADC input
for unipolar parts and at 0V for bipolar devices. To test other
DC values, apply a source to the J1/J2 inputs. It is advised to
filter the signal to make the DC source noise compatible with
that of the ADC. C26/C41 provide this filtering.
The “USB Device” can be opened to view it’s uninstalled
properties.
AC TESTING
This is usually the case if the software and drivers were installed
by a user without administrator privileges. If so, log on as an
administrator with full privileges and reinstall the software.
RUNNING THE EVALUATION SOFTWARE
The evaluation board includes software for analyzing the
AD7682, AD7689, AD7699 and AD7949. The EVAL-CED1Z is
required when using the software. The software is used to
perform the following tests:
Figure 6 is a screen shot of the fast Fourier transform, FFT. This
tests the traditional AC characteristics of the converter and
displays an FFT of the result. As in the histogram test, raw data
is captured and passed to the PC where the FFT is performed
thus displaying SNR, SINAD, THD and SFDR. The data can also
be displayed in the time domain. To perform an AC test, apply a
sinusoidal signal to the evaluation board at the SMB inputs J1
for IN+ and J2 for IN-. Low distortion, better than 100dB, is
required to allow true evaluation of the part. One possibility is
to filter the input signal from the AC source. There is no
suggested bandpass filter but consideration should be taken in
the choice. Furthermore, if using a low frequency bandpass
filter when the full-scale input range is more than a few Vpp, it
is recommended to use the on board amplifiers to amplify the
signal, thus preventing the filter from distorting the input
signal.
Rev. PrB | Page 6 of 23
Preliminary Technical Data
EVAL-AD76XXEDZ
Table 1. CNVST Generation, Analog Input Range
Part
AD7621
AD7622
AD7623
AD7641
AD7643
AD7650
AD7651
AD7652
AD7653
AD7660
AD7661
AD7663
AD7664
AD7665
AD7666
AD7667
AD7671
AD7674
AD7675
AD7676
AD7677
AD7678
AD7679
1
Resolution
(bits)
16
16
16
18
18
16
16
16
16
16
16
16
16
16
16
16
16
18
16
16
16
18
18
Sample Rate
Analog Input Range
Analog Input Type
3 MSPS
2 MSPS
1.33 MSPS
2 MSPS
1.25 MSPS
100 kSPS
100 kSPS
500 kSPS
1 MSPS
100 kSPS
100 kSPS
250 kSPS
570 kSPS
570 kSPS
500 kSPS
1 MSPS
1 MSPS
800KSPS
100 kSpS
500 kSPS
1 MSPS
100KSPS
571KSPS
0 to 2.5V
0 to 2.5V
0 to 2.5V
0 to 2.5V
0 to 2.5V
0 to 2.5V
0 to 2.5V
0 to 2.5V
0 to 2.5V
0 to 2.5V
0 to 2.5V
-5V to +5V1
0 to 2.5V
-5V to +5V
0 to 2.5V
0 to 2.5V
-5V to +5V
0 to 5V
0 to 2.5V
0 to 2.5V
0 to 2.5V
0 to 5V
0 to 5V
Diff, Unipolar
Diff, Unipolar
Diff, Unipolar
Diff, Unipolar
Diff, Unipolar
Single Ended, Unipolar
Single Ended, Unipolar
Single Ended, Unipolar
Single Ended, Unipolar
Single Ended, Unipolar
Single Ended, Unipolar
Single Ended, Bipolar
Single Ended, Unipolar
Single Ended, Bipolar
Single Ended, Unipolar
Single Ended, Unipolar
Single Ended, Bipolar
Diff, Unipolar
Single Ended, Unipolar
Single Ended, Unipolar
Single Ended, Unipolar
Diff, Unipolar
Diff, Unipolar
Available Input Ranges are 0 to 2.5V, 0 to 5V, 0 to 10V, +/- 2.5V, +/-5V, and +/- 10V. however the board is factory configured for the +/-5V input range. Modify S1 to S7
accordingly (see schematics and datasheets) for different input range configuration.
Rev. PrB | Page 7 of 23
EVAL-AD76XXEDZ
Preliminary Technical Data
Table 2. Jumper Description
1
Jumper
Name
JP1, JP2
BUFF
Default
Position
BUFF
JP3
VDRV-
-12V
JP4
REFS
REF
JP6
OVDD
3.3V
JP7
VREF+
+12V
JP8
VDRV+
+12V
JP9
DVDD
VDIG/2.51
JP19
JP20
AVDD
REFB
+5V/2.51
BUF
JP21
VIO
3.3V
JP22
CNVST
INT
Function
Buffer amplifier: BUFF = use op amps to buffer analog input. NO BUFF = direct input from J1,
J2 (SMB).
Buffer amplifier negative supply: Selection of -12V, -5V or GND when using EVAL-CED1Z or
voltages on SJ1 in stand alone mode.
Reference selection: REF = use on board reference output for ADC reference. VDD = use
analog supply (AVDD) for ADC reference.
ADC digital output supply voltage: Selection of 2.5V, 3.3V and VDIG. VDIG = +5V when using
EVAL-CED1Z or voltage on SJ2 in stand-alone mode.
Reference circuit positive supply: Selection of +12V, +5V or AVDD when using EVAL-CED1Z or
voltages on SJ1 in stand alone mode.
Buffer amplifier positive supply: Selection of +12V, +5V or AVDD when using EVAL-CED1Z or
voltages on SJ1 in stand alone mode.
ADC digital supply voltage: Selection of +2.5V or VDIG (+5V) when using EVAL-CED1Z or
voltage on SJ2 in stand-alone mode.
ADC analog supply voltage: Selection of +2.5V, +5V or EXT when using EVAL-CED1Z
Reference buffer: BUFF = use U2 to buffer or amplify reference source. NO BUFF = use
reference directly into ADC.
Gate array I/O voltage: Selection of 3.3V or OVDD. Note: gate array will be damaged if >3.3V
(ie. when using OVDD = VDIG).
CNVST source: INT = use gate array to generate CNVST. EXT = use external source into J3, SMB
for CNVST.
For AD7621/22/23//25/41/43 these are set to +2.5V. Note that setting these to +5V will permanently destruct the ADC.
Table 3. S16 - Configuration Select Switch Description
Note: (OFF = LOW, ON = HIGH)
Position
Name
1
WARP
Default
Position
LOW
2
IMPULSE
LOW
3
4
5
BIP
TEN
A0/M0
LOW
LOW
LOW
6
BYTE/M1
LOW
7
8
9
OB/2C
SER/PAR
EXT/INT
HIGH
LOW
LOW
10
INVSYNC
LOW
11
INVSCLK
LOW
12
RDC
LOW
Function
Conversion mode selection: Used in conjunction with IMPULSE. When HIGH with IMPULSE=
LOW, the fastest (Warp) mode is used for maximum throughput. When LOW and IMPULSE =
LOW, Normal mode is used.
Conversion mode selection: Used in conjunction with WARP. When HIGH with WARP = LOW, a
reduced power mode is used in which the power consumption is proportional to the
throughput rate.
For future use.
For future use.
A0, input Mux selection: Used for AD7654/AD7655 (refer to datasheet).
M0, data output interface selection: Used along with M1 for 18-bit ADCs.
BYTESWAP, used for 8-bit interface mode on 16-bit ADCs: MSByte is swapped with LSByte on 8
data lines.
M1, data output interface selection: Used along with M0 for 18-bit ADCs.
Data output select: LOW = Use 2’s complement output. HIGH = Straight binary output.
Data output interface select: LOW = Parallel interface. HIGH = Serial interface.
Serial clock source select: LOW = Use ADC internal serial clock, SCLK is an output. HIGH= Use
external clock, which is MCLK (40 MHz) and SCLK is an input. Not used in parallel reading mode.
Serial sync (SYNC) active state: LOW = SYNC is active HIGH. HIGH = SYNC is active LOW. Used
only for Master mode (internal SCLK). Not used in parallel reading mode.
Serial clock (SCLK) active edge: LOW = Use SCLK falling edge. HIGH = Use SCLK rising edge.
Active in all serial modes. Not used in parallel reading mode.
Read during convert: LOW = Read data after conversion (BUSY = LOW). HIGH = Read data
during conversions (BUSY = HIGH). Used in both parallel and serial interface modes.
Table 4. S35 - Configuration Select Switch Description
Note: (OFF = LOW, ON = HIGH)
Rev. PrB | Page 8 of 23
Preliminary Technical Data
Position
Name
1
2
RESET
PD
Default
Position
LOW
LOW
3
PDBUF
LOW
4
PDREF
LOW
EVAL-AD76XXEDZ
Function
Reset ADC: LOW = Enables the converter. HIGH = Abort conversion (if any).
Power down: LOW = Enables the converter . HIGH = Powers down the converter. Power
consumption is reduced to a minimum after the current conversion.
Internal reference buffer power down: LOW = Enable on chip buffer. HIGH = Power down
internal buffer.
Internal reference power down: LOW = Enable on chip reference. HIGH = Power down internal
reference. Note that when using the on chip reference, the buffer also needs to be enabled
(PDREF = PDBUF = HIGH).
Table 5.Test Points
Test
Point
TP1
TP2
TP3
TP4
TP5
TP7
TP8
TP9
TP10
TP11
TP12
TP13
TP14
TP15
TP16
TP17
TP18
TP19
TP20
Available
Signal
BUSY
A0/M0
SIG+
AGND
REF
DGND
CNVST
AGND
CS
RD
OVDD
DVDD
AVDD
AGND
SIGSCLK
SYNC
SDOUT
TEMP
Type
Description
Output
Input
Input
GND
Input/Output
GND
Input
GND
Input
Input
Power
Power
Power
GND
Input
Input/Output
Output
Output
Output
TP22
REFIN
Input/Output
TP23
T3
T4
T5
T6
BVDD
SDOUT
SCLK
SYNC
RDERROR
Output
Output
Input/Output
Output
Output
BUSY signal.
Same as S16, position 5
Analog +input.
Analog ground close to SIG+.
Reference input. Output for devices with on-chip reference.
Digital ground near SJ2.
CNVST signal.
Analog ground close to REF.
CS, chip select signal.
RD, read signal.
Digital output supply.
Digital core supply.
Analog supply.
Analog ground close to SIG-.
Analog –input for differential parts.
Buffered serial clock.
Buffered serial sync.
Buffered serial data.
TEMP, for ADC with internal reference. Outputs temperature dependant voltage (approx.
300mV with TA = 25°C).
For ADCs with internal reference, REFBUFIN can be used to connect external reference into
the reference buffer input when PDBUF = LOW and PDREF = HIGH. With the internal
reference (and buffer) enabled, this pin will produce the internal bandgap reference voltage.
Internal reference bandgap supply. Connected to AVDD via s19.
Direct ADC serial data.
Direct ADC serial clock.
Direct ADC serial SYNC.
Direct ADC serial read error.
Rev. PrB | Page 9 of 23
EVAL-AD76XXEDZ
Preliminary Technical Data
1
3
4
5
Figure 2. Setup Screen
2. The part to be evaluated is selected here.
Coding – Another subset to the digital interface mode, this can
be used to select straight binary or 2’s complement output. Note
the time domain chart and data output (F5) plots and saves data
in straight binary.
3. The controls are used to set:
Reset – Resets the ADC.
Sample Frequency – Enter in kHz Units can be used such as 3k
(case sensitive) for 3,000,000 Hz or 3MSPS.
PD, PDREF, PDBUF – These can be used to power down the
ADC, internal reference and internal reference buffer.
Clock Source - Selections between control (capture) board or
evaluation board.
4. These controls are used for saving, printing, help, etc. and are
also accessed in the File menu.
Mode – This selects the conversion mode of operation. Some
ADCs have different modes Warp, Normal, and Impulse.
Save (F5): type – LabView config, allows the current
configuration to be saved to a filename.dat file. Useful when
changing many of the default controls. To load the saved
configuration, use the Load Previous Configuration.
1. The arrow
is used to start the software. When running
is displayed.
Cnv Mode – Conversion mode; this selects between continuous
(Cont.) or Burst conversion modes. In continuous mode, the
ADC is continuously converting. In Burst mode, the ADC is not
converting (sample clock held in inactive state) and the
conversions begin once the “Single Capture” or “Continuous
Capture” buttons have been selected.
Interface mode – This selects the digital interface to the onboard FPGA.
Byteswap – A subset of the digital interface mode, this is used
to demonstrate byte-wide transfers to the FPGA.
Type – Html, saves the current screen shot to an Html file.
Type – Spreadsheet, saves the current data displayed in the chart
in a tab delimited spreadsheet. Raw ADC Data is time domain
in Codes, FFT or Decimated is in dB.
can also be
5. Stop (F10) is used to stops the software. The
used to stop the software. RESET is used to reset the CED or
ECB capture boards.
Rev. PrB | Page 10 of 23
Preliminary Technical Data
EVAL-AD76XXEDZ
1
Figure 3. Context Help
2
1. To use the on-screen help. Select Help, Show Context Help or
click the Help (F1). An example of the Context Help is shown
above for the Sample Frequency. Placing the curser on most
screen items displays useful help for the particular control or
displayed unit.
,
are used to set axes properties such as format,
precision, color, etc. Right mouse click to change to
Hexadecimal, number of digits, etc.
Displays the cursor.
2. These controls are used for axes and zooming panning.
Is used For zooming in and out.
Locks the graph axis to automatically fit the data.
Uses last axis set by user.
automatic values.
,
Is used for panning.
rescale the axes to the
Is used to set various graph properties such as graph
type, colors, lines, etc.
Rev. PrB | Page 11 of 23
EVAL-AD76XXEDZ
Preliminary Technical Data
1
Figure 4. Histogram Screen
3
2
1. These radio buttons are used to perform a Single Capture or
Continuous Capture of data set in the # of Samples field. The
results are displayed in the chart. Note that the results can be
displayed as:
Or an
(time domain)
2., 3.These display the statistics for the X and Y-axes,
respectively.
A
Rev. PrB | Page 12 of 23
Preliminary Technical Data
EVAL-AD76XXEDZ
Figure 5. Summary
The charts can be displayed together when the
tab is selected.
Rev. PrB | Page 13 of 23
EVAL-AD76XXEDZ
Preliminary Technical Data
1
1
3
Figure 6. FFT Spectrum
2
1. Displays the FFT when the Spectrum chart is selected
2., 3. Display the data for the X and Y-axes, respectively.
.
Rev. PrB | Page 14 of 23
Preliminary Technical Data
EVAL-AD76XXEDZ
1
Figure 7. Oscilloscope
1. Time domain data can be viewed with the oscilloscope also.
Rev. PrB | Page 15 of 23
A
B
C
+VA
-VS
GND
VREF+
1
TP15
AGND
S32
DAC+
GND
J2
AIN-
AIN-
S33
DAC-
GND
J1
AIN+
AIN+
DAC-
TP4
GND
DAC+
+VA
-VS
GND
VREF+
C52
.1uF
R7
590
R29
590
0.0
GND
C41
R61
49.9
R34
R42
49.9
R43
C36
R44
GND
GND R59
C26
VCMT
IN
3
2
U6A
U7A
2
0.0
R90
10pF-NPO
0.0
R91
10pF-NPO
C35
VDRV- .1uF GND
C42
5
6
GND
VDRV+ C37
.1uF
VDRV-
C34
GND
C6
1uF
1
VDRV- .1uF GND
C22
5
6
.1uF
C20
GND
VDRV+
AD8021
3
2
VDRV+
C64
5
6
AD158X
OUT
C29
.1uF
TRIM
VOUT
AD8021
49.9
0
0.0
VCMT
R35
R6
590
U5A
R31
R3
C19
TEMP
R5
R1
R2
GND
GND
590
R60
AIN-
VCM
VCM
C53
.1uF
AIN+
C28
.1uF
3
ADR43X
GND
3
GND
2
VREF+
2
+VIN
GND
2.5/3v
4
8
REF
BUF
JP2
JP1
JP4
REFS
NOBUF
BUF
NOBUF
VDD A
AVDD
REFOUT
NOTE:
R9
C59
SIG-
SIG+
SIG-
SIG+
3
TP16
SIG-
R97
0.0
R96
0.0
TP3
SIG+
C38
0.0
R45
0.0
R46
3
2
C9
1uF
10K
R37
ANY PASSIVE COMPONENTS WITHOUT VALUE
ARE NOT POPULATED
10K
R4
GND
R10
C60
15
1
BUF
C39
C40
GND
-VS
S17
S1
+VS
S3
S21
VCM
S2
C25
.1uF
VREF+
AGND
TP9
AD8032AR
GND
R47
15
R48
U2A
8
4
4
S5
S4
A
S20
BVDD
TP23
S15
GND
S8
TP22
VBG
1uF
C31B
REF
REF
GND
S7
S6
C31T
NOBUF
BUF
JP20
REFB
S14
S10
TEMP
S9
5
C55
C13
S34
46
44
45
43
42
41
40
39
38
37
OVDD
C9B
.1uF
DVDD
C5B
.1uF
DVDD
C56
REFIN/INA1
INA2
INAN/TEMP
AVDD
GND
GND
AD76XX
IN_D/IN+
IN_C
IN_B/INB2
IN_A/INBN
INGND/IN-/INB1
REFGND
REF
U1
GND
GND
IN_D
IN_C
IN_B
IN_A
INGND
S31
GND
VCM
S13
C8
10uF
TP5
REF
S12
7
TP20
TEMP
S19
TEMP
S18
S11
AVDD
S30
U2B
REFOUT
47uF
C32B
5
6
DVDD
TP13
DVDD
AVDD
TP14
AVDD
AVDD
18
OVDD
C27
.1uF
5
19
DVDD
D
4
2
AVDD
U5B
3
1
C5T
.1uF
C9T
.1uF
AGND
2
OVDD
17
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
3 A0
31 RD
32 CS
47
36
30
48
8-Feb-2005
A0
RD
CS
PDRT0
T0PDR
T1/EOC
PDBT1
6
Rev. : J
ANALOG
EVAL-AD76XXCB
GND
D[0..15]
6
35 CNVST
CNVST
29 BUSY
BUSY
9
10
11
12
13
14
15
16
21
22
23
24
25
26
27
28
TP12
OVDD
OB/2C
WARP
IMPULSE
IMPULSE
SER/PAR
SER/PAR
RESET
RESET
BYTE/M1
PD
PD
A0
RD
CS
PDREF/T0
T0/PDREF
T1/EOC
PDBUF/T1
CNVST
BUSY
C7B
.1uF
GND
OVDD
D0
D1
D2/DIVSCLK(0)
D3/DIVSCLK(1)
D4/EXT/INT
D5/INVSYNC
D6/INVSCLK
D7/RDC/SDIN
D8/SDOUT
D9/SCLK
D10/SYNC
D11/RDERROR
D12
D13
D14
D15
DGND
NOTE:
EITHER U5A OR U5B
IS USED AT A TIME
7
4
20
DGND
PD
BYTESWAP
RESET
SER/PAR
IMPULSE
WARP
OB/2C A/B
1
7
Rev. PrB | Page 16 of 23
34
4
33
8
7
6
5
Figure 8. Schematic, Analog
4
C7T
.1uF
M.M
D[0..15]
A
B
C
D
EVAL-AD76XXEDZ
Preliminary Technical Data
EVALUATION BOARD SCHEMATICS AND ARTWORK
A
B
C
D
GND
P3C
P3B
GND
GND
B25
B24
B23
B22
B21
A29
A26
A25
A24
A23
A32
B32
C32
A31
B31
C31
C30
A8
B8
C8
A30
A4
A12
A16
A20
B4
B12
B16
B20
C4
C12
C16
C20
B26
B27
B28
B29
B30
C21
C22
C23
C24
C25
C26
C29
A21
A22
J3
CNVSTIN
CNVOUT
1
GND
PDREF
PDBUF
PD
RESET
BYTE/M1
A0/M0
TEN
BIP
IMPULSE
-12V
VDIG
+12V
-VA
+VA
R28
100
EXT
INT
WARP
A
JP22
CNV SEL
R77
1K
10K
R99
1K
R101
10K
R98
1K
R100
10K
R93
1K
R89
10K
R92
R88
1K
10K
1K
R81
10K
R76
1K
R22
10K
R71
1K
R21
10K
R70
1K
R20
10K
R69
1K
R19
10K
R33
R15
-12V
VDIG
+12V
-VA
+VA
R30
100
R36
1M
3.3V
4
3
2
1
6
5
4
3
2
1
S35D
S35C
S35B
S35A
S16F
S16E
S16D
S16C
S16B
S16A
R83
TP8
CNVST
5
6
7
8
19
20
21
22
23
24
PDREF
PDBUF
PD
RESET
BYTE/M1
A0/M0
TEN
BIPOLAR
IMPULSE
WARP
VIO
JP11
R85
10K
3.3V
CNVST
VIO
2
RDC
INVSCLK
INVSYNC
EXT/ INT
SER/PAR
OB/ 2C
VIO
CNVST
2
13
14
15
16
17
18
S16L
S16K
S16J
S16I
S16H
S16G
12
11
10
9
8
7
1K
10K
R79
10K
R78
1K
R14
1K
R16
10K
R75
1K
R17
10K
R74
1K
R13
1K
R12
10K
R73
10K
R72
R11
PDRT0
A0
GND
C57
BUSY
RD
CS
GND
TP2
A0
TP10
CS
D7
D6
D5
D4
SER/PAR
OB/2C
PDBT1
T1/EOC
T0PDR
GND
TP21
GND
D[0..15]
VIO
S29
T1
S28
S23
S22
3
100
R54
10K
JP14
S26
TEMP
GND
R55
10K
61
60
59
TEMP
41
PDBUF 62
TEN
BIP
PDREF 58
26
25
T1 24
T2 23
22
21
16
15
T3 14
T4 12
T5 11
T6 10
144
143
142
141
13
140
139
138
137
R68
134
49.9
2
39
BYTE/M1
RESET
136
37
WARP
OB/2C
38
35
SER/PAR
36
IMPULSE
135
PD
A0/M0 57
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
D9
10k
GND
R32
R82
S25
S24
BYTE/M1
RESET
WARP
OB/2C
SER/PAR
IMPULSE
PD
CNVOUT
PDRT0
A0
49.9
R86
TP11 TP1
RD BUSY
S27
D[0..15]
3
TEMP
PDBUF
EPF6010ATC144-3
TEST1_OUT
EOC
TEST0
PDREF
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
SCLKIN
BUSY
RD
CS
CNVST
CNVSTOUTB
CNVSTOUT
BYTE
RESET
WARP
OB/2C
SER/PAR
IMPULSE
PD
A0
U10A
4
DSPCLK
MCLK
SCLK0
TFS0
RFS0
DT0
DR0
MODE0
AD2
AD1
AD0
MODE1
MODE2
MODE3
BWR
BRD
RESETD
RESETS
CONTROL
BCS
FSYNC
BBUSY
DBUSY
ADCOK
BD-1
BD-2
BD0
BD1
BD2
BD3
BD4
BD5
BD6
BD7
BD8
BD9
BD10
BD11
BD12
BD13
BD14
BD15
CONF_D
STATUS
CONFIG
CE
MSEL
DCLK
DATA
4
71
69
116
118
119
121
122
47
95
96
93
46
45
44
114
113
86
43
130
111
131
85
40
49
107
108
129
124
123
120
117
115
112
110
109
94
87
84
72
81
82
73
105
56
53
4
33
128
125
GND
R51
10K
10K
10K
C47
10K
10K
10K
0
R49
TP19
SDOUT
TP18
SYNC
TP17
SCLK
R65
R64
R63
10K
R66 10K
R58 10K
R57 10K
R62
GND
DSPCLK
SCLK
TFS0
SYNC
SDIN
SDOUT
M0
AD2
AD1
AD0
M1
M2
M3
BWR
BRD
1K
U11
1
3
R80
100
6
5
3
4
VDIG
U12
GND
3.3V
GND
SYNC-FFT
TP6
GND
OE
CS
CASC
OUT
EPC1441
3.3V
DCLK
DATA
3.3V
3.3V
R67 10K
RESETS R56
RESETD
D2
2
1
8
7
R41
CONTROLR52
BCS
FSYNC
BBUSY
DBUSY
ADCOK
BD-1
BD-2
BD0
BD1
BD2
BD3
BD4
BD5
BD6
BD7
BD8
BD9
BD10
BD11
BD12
BD13
BD14
BD15
CONF_D
STATUS
CONFIG
DCLK
DATA
3.3V
R38
1K
VIO
BD15
BD14
BD13
BD12
BD11
BD10
BD9
BD8
BD7
BD6
BD5
BD4
BD3
BD2
BD1
BD0
DBUSY
BD-1
BD-2
BCS
5
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
R40
1K
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
3.3V
P2
R39
1K
GND
VDIG
7
19
32
55
78
91
104
127
6
31
77
103
EPF6010ATC144
C30
.1uF
2
4
5
GND
3.3V
GND
TP7
GND
U10B
126
5
18
30
54
76
90
102
Rev. PrB | Page 17 of 23
C17
.1uF
VIO
VIO
VIO
VIO
VIO
VIO
VIO
VIO
3.3V
3.3V
3.3V
3.3V
Figure 9. Schematic, Digital
GND
GND
GND
GND
GND
GND
GND
GND
1
GND
C21
.1uF
C16
.1uF
.1uF
C18
GND
3.3V
.1uF
C4
C24
.1uF
C3
.1uF
DIGITAL
6
Rev. : J
.1uF
C11
GND
3.3V
C19
C18
B18
A18
B17
B15
B14
B13
B11
B10
B9
B7
B6
B5
B3
B2
C14
A14
C15
C10
C17
A9
C9
A17
B1
A5
A6
A19
C5
C7
C6
A27
C27
VIO
GND
.1uF
C12
BD15
BD14
BD13
BD12
BD11
BD10
BD9
BD8
BD7
BD6
BD5
BD4
BD3
BD2
BD1
BD0
AD2
AD1
AD0
BCS
BBUSY
BRD
BWR
RESETD
CONTROL
SDIN
TFS0
DSPCLK
SDOUT
SCLK
SYNC
DAC+
DAC+
DACDAC-
.1uF
C10
EVAL-AD76XXCB
.1uF
C7
8-Feb-2005
.1uF
C5
C23
.1uF
GND
R53
10K
3.3V
6
M.M
P3A
A
B
C
D
Preliminary Technical Data
EVAL-AD76XXEDZ
A
B
C
1
GND
VDIG
VDIG
SJ2
C1
10uF
VDIG
C32
1uF
GND
GND
VDIG
C45
1uF
4
7
8
4
7
8
NC
IN
IN
2
FB
OUT
FB
OUT
OUT
U4
ADP3334ARM
NC
IN
OUT
U5
ADP3334ARM
IN
2
GND
SD
5
6
GND
SD
5
6
Rev. PrB | Page 18 of 23
3
2
1
3
2
1
C46
1uF
C33
1uF
GND
R26
78.7K
R23
140K
3.3V
GND
R24
94.5k
R8
106.1k
2.5V
VDIG
VDIG
3.3V
1
2
1
2
3
JP9
JP6
3
4
C48
10uF
3
GND
C49
10uF
DVDD
GND
3
R27
AVDD
3.3V
C43
1uF
D1
GND
+VA
JP21
R84
0
OVDD
VIO
VIO
4
7
8
GND
NC
IN
IN
FB
OUT
OUT
U8
ADP3334ARM
C14
10uF
GND
SD
Figure 10. Schematic, Power
5
6
D
1
3
2
1
4
GND
EXT
+12V
+5V
-5V
-12V
4
+12V
EXT
4
5
GND
R25
94.5k
R18
106.1k
+VA
3
GND
-VA
2
6
-12V
1
C44
1uF
SJ1
3
2
1
2
EXT 1
+12V
GND
-VA -12V
JP10
JP5
5
3
4
5
JP3
C31
10uF
3
2
1
GND
+VS
GND
-VS
JP19
JP7
GND
JP8
1
2
3
-VS
C2
10uF
-VS
VDIG
VIO
OVDD
DVDD
AVDD
GND
VREF+
3.3V
+12V
+VA
-VA
-12V
+VA
GND
AVDD
C51
10uF
VDRVC50
10uF
C15
10uF
4
4
VDIG
VIO
OVDD
DVDD
AVDD
GND
VREF+
3.3V
+12V
+VA
-VA
-12V
+VA
GND
VREF+
VDRV+
6
Rev. : J
POWER
EVAL-AD76XXCB
GND
VDRV+
8-Feb-2005
C54
10uF
VDRV-
6
M.M
A
B
C
D
EVAL-AD76XXEDZ
Preliminary Technical Data
Preliminary Technical Data
EVAL-AD76XXEDZ
Figure 11. Top Side Silk-Screen
Figure 12. Top Layer
Rev. PrB | Page 19 of 23
EVAL-AD76XXEDZ
Preliminary Technical Data
Figure 13. Ground Layer
Figure 14. Shield Layer
Rev. PrB | Page 20 of 23
Preliminary Technical Data
EVAL-AD76XXEDZ
Figure 15. Bottom Side Layer
a
Figure 16. Bottom Side Silk-Screen
Rev. PrB | Page 21 of 23
EVAL-AD76XXEDZ
Preliminary Technical Data
Table 6. Bill of Materials for the Connectors
Ref Des
J1 – J3
P2
P3
Connector Type
RT Angle SMB Male
0.100 X 0.100 straight IDC header 2X20
32X3 RT PC MOUNT CONNECTOR
Manf.
Pasternack
3M
ERNI
Part No.
PE4177
2540-6002UB
533402
ORDERING GUIDE
These evaluation boards are compatible with both EVAL-CED1Z and EVAL-CONTROL BRDxZ. For simplicity, this document was made
especially for EVAL-CED1Z usage. Refer to Analog Devices PulSAR Evaluation Kit product page for the user’s guide specific to EVALCONTROL BRDxZ usage.
Evaluation Board Model
EVAL-AD7621CBZ
EVAL-AD7622CBZ
EVAL-AD7623CBZ
EVAL-AD7641CBZ
EVAL-AD7643CBZ
EVAL-AD7650CBZ
EVAL-AD7651CBZ
EVAL-AD7652CBZ
EVAL-AD7653CBZ
EVAL-AD7660CBZ
EVAL-AD7661CBZ
EVAL-AD7663CBZ
EVAL-AD7664CBZ
EVAL-AD7665CBZ
EVAL-AD7666CBZ
EVAL-AD7667CBZ
EVAL-AD7671CBZ
EVAL-AD7674CBZ
EVAL-AD7675CBZ
EVAL-AD7676CBZ
EVAL-AD7677CBZ
EVAL-AD7678CBZ
EVAL-AD7679CBZ
EVAL-CED1Z
Product
AD7621ASTZ/ACPZ
AD7622BSTZ/BCPZ
AD7623ASTZ/ACPZ
AD7641BSTZ/BCPZ
AD7643BSTZ/BCPZ
AD7650ASTZ/ACPZ
AD7651ASTZ/ACPZ
AD7652ASTZ/ACPZ
AD7653ASTZ/ACPZ
AD7660ASTZ/ACPZ
AD7661ASTZ/ACPZ
AD7663ASTZ/ACPZ
AD7664ASTZ/ACPZ
AD7665ASTZ/ACPZ
AD7666ASTZ/ACPZ
AD7667ASTZ/ACPZ
AD7671ASTZ/ACPZ
AD7674ASTZ/ACPZ
AD7675ASTZ/ACPZ
AD7676ASTZ/ACPZ
AD7677ASTZ/ACPZ
AD7678ASTZ/ACPZ
AD7679ASTZ/ACPZ
USB Capture Board
Rev. PrB | Page 22 of 23
Preliminary Technical Data
EVAL-AD76XXEDZ
NOTES
©2009 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
PR07201-0-3/09(PrB)
Rev. PrB | Page 23 of 23
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