EVAL-AD76MUXEDZ: Evaluation Board For AD7682/89/99/7949 PulSAR ADCs PDF

EVAL-AD76MUXEDZ: Evaluation Board For AD7682/89/99/7949 PulSAR ADCs PDF
Preliminary Technical Data
Evaluation Board For AD7682/89/99/7949
PulSAR® ADCs
EVAL-AD76MUXEDZ
www.analog.com and should be consulted when utilizing this
evaluation board.
FEATURES
Converter and Evaluation Development (EVAL-CED1Z)
compatibility
Versatile analog signal conditioning circuitry
On-board reference, clock oscillator and buffers
PC software for control and data analysis of time and
frequency domain
Stand alone operation
The evaluation board can be operated as a stand alone or can be
used in conjunction with the Analog Devices EVAL-CED1Z
(CED) USB based data capture board. Since the ADC’s being
evaluated are serial interface only, the EVAL-AD76MUXCBZ
contains the necessary logic to perform serial to parallel
conversion for this interface using the on board FPGA.
GENERAL DESCRIPTION
The EVAL-AD76MUXCBZ is an evaluation board for the 20
lead PulSAR AD7682, AD7689, AD7699, and AD7949 14-bit
and 16-bit PulSAR analog to digital converter (ADC) family.
These low power, successive approximation register (SAR)
architect-ture ADCs (see Ordering Guide for product list) offer
very high performance with up to 500kSPS throughput rate and
4 – 8 channels. The evaluation board is designed to demonstrate
the ADC's performance and to provide an easy to understand
interface for a variety of system applications. A full description
of the AD7682, AD7689, AD7699, and AD7949 is available in at
Signal conditioning
Reference Source, COM Select
On-board components include a high precision band gap
reference, (ADR435), reference buffers, 8-signal conditioning
circuits with an op amp and an FGPA for digital logic. Also
included are separate low drop out regulators for supplying
special voltages of 1.2V and 7V which are not available from the
EVAL-CED1Z.
The board interfaces to the EVAL-CED1Z with a 96-pin DIN
connector. J1, J2 SMB connectors are provided for the low noise
analog signal source for CH0 and CH1 with the remaining
channels (and CH0/1) available on an IDC connector, P1. J3 can
be used for providing an external common (COM) or
configured for any input channel.
FPGA
FPGA
POWER
96-Pin EVAL-CED1Z Interface
Analog
Inputs
External COM
(or Input)
ADC
ANALOG, VDD
POWER
DIGITAL
INTERFACE
P3, 40-Pin IDC
Header
Figure 1.Evaluation Board
Rev. PrD
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2009 Analog Devices, Inc. All rights reserved.
EVAL-AD76MUXEDZ
Preliminary Technical Data
TABLE OF CONTENTS
Features .............................................................................................. 1
Software Installation .....................................................................4
Revision History ............................................................................... 2
Running the Evaluation Software ..............................................5
Overview........................................................................................ 3
Setup Screen...................................................................................5
Conversion Control...................................................................... 3
Configuring the ADC ...................................................................5
Analog Inputs................................................................................ 3
DC Testing - Histogram ...............................................................5
Serial Interface .............................................................................. 3
AC Testing ......................................................................................5
Reference ....................................................................................... 3
Software Operation .......................................................................8
Power Supplies and Grounding .................................................. 3
ADC Configuration ......................................................................9
Schematics/PCB Layout............................................................... 4
Evaluation Board Schematics and Artwork............................ 15
Hardware Setup ............................................................................ 4
Ordering Guide .......................................................................... 26
LIST OF FIGURES
Figure 1.Evaluation Board ............................................................... 1
Figure 14. Schematic, Supplies ...................................................... 16
Figure 2. Setup Screen ...................................................................... 8
Figure 15. Schematic, Reference, Buffer, VCM, VBIAS .................... 17
Figure 3. Default CFG ..................................................................... 9
Figure 16. Schematic, AnalogCH0-CH3...................................... 18
Figure 4. CGF Enable/Disable Selection....................................... 9
Figure 17. Schematic, AnalogCH4-CH7...................................... 19
Figure 5. Input Configuration/Channel Selection........................ 9
Figure 18. Schematic, FPGA.......................................................... 20
Figure 6.BW Select............................................................................ 9
Figure 19. Schematic, 96-Pin Interface ........................................ 21
Figure 7. Reference Selection .......................................................... 9
Figure 20. Top Side Silk-Screen .................................................... 22
Figure 8. Context Help, User Controls ......................................... 10
Figure 21. Inner Layer 1................................................................. 22
Figure 9. Histogram Screen ........................................................... 11
Figure 22. Ground Plane................................................................ 23
Figure 10. Summary ....................................................................... 12
Figure 23. Inner Layer 2................................................................. 23
Figure 11. FFT Spectrum ............................................................... 13
Figure 24.Inner Layer 3.................................................................. 24
Figure 12 .Oscilloscope .................................................................. 14
Figure 25. Bottom Layer ................................................................ 24
Figure 13. Schematic, ADC + Block Diagram............................. 15
Figure 26. Bottom Layer ................................................................ 25
LIST OF TABLES
Table 1. Jumper Description............................................................ 6
Table 3. Bill of Materials for the Connectors .................................7
Table 2.Test Points ............................................................................ 7
REVISION HISTORY
Rev. PrD | Page 2 of 26
Preliminary Technical Data
EVAL-AD76MUXEDZ
OVERVIEW
Figure 1 shows the EVAL-AD76MUXCBZ evaluation board.
When used in conjunction with the EVAL-CED1Z, the FPGA,
U6, provides the necessary control signals for conversion and
buffers the ADC serial output data into 16-bit wide transfers.
The evaluation board is a flexible design that enables the user to
choose among many different board configurations, analog
signal conditioning, reference, and different interfaces for
conversion results.
In stand alone operation, the FPGA can be used to buffer the 4wire interface via. P3, or directly to the 4 digital interface test
points SDO, SCK, DIN and CNV. For stand alone mode, supply
power to the evaluation board as detailed in the Power Supplies
and Grounding section below.
For FPGA buffered serial interface, supplying power is all that is
necessary. For direct serial connection to the ADC, place a
jumper across P3-39 and P3-40 as P3-40 pulled low places the
FPGA into high impedance.
CONVERSION CONTROL
Conversion start (CNV) controls the sample rate of the ADC
and is the only input needed for conversion; all SAR timing is
internally generated on the ADC. CNV is generated by the gate
array and the frequency is selected with the software.
While the ADC is converting, activity is indicated by the green
LED, CR1. Operating the software in Burst mode as opposed to
Continuous mode, will only light the LED when conversion is
taking place.
For stand alone operation, connect a low jitter source to either
P3-8 or CNV.
ANALOG INPUTS
SMB connectors, J1 and J2, are provided for the ADC input
channels IN0 and IN1 (IN0 only on AD7682). These inputs are
also on the IDC connector P1-2 and P1-4. The remaining inputs
are also on P1-6 through P1-16 (even pins only). J3 can be
configured for providing a common point (COM) for all input
signals or for any analog input IN0-IN7. For using J3 as an
external common point, remove the solder pad (bottom of
PCB) from “COMS to COM” and solder “EXT_COM to COM”
as shown below.
To configure J3 to drive any of the analog input channels,
remove R35 from the left pads (bottom of PCB) and solder it to
the rightmost pads.
The analog input amplifier circuitry U13 – U20 (see schematic Figure 13) allows flexible configuration changes such as positive
or negative gain, input range scaling, filtering, addition of a DC
component, use of different op-amp and supplies. The analog
input amplifiers are set as unity gain buffers at the factory. The
supplies are selectable with solder pads VDRV- and VDRV+
and are set for the +7V, -5V range.
Note that when using the unipolar configuration, COMS (P8) is
set to (P8, 2-3) and for bipolar input configuration set to (P8, 12) with pin 1 being the leftmost pin.
SERIAL INTERFACE
The 3-wire serial interface DIN, SCK, and SDO along with CNV
are present on the digital interface test points and FPGA
buffered versions are on the 40-pin IDC connector, P3-2, -4, -6,
-8. When connected to the EVAL-CED1Z and stand alone
(without P3-39 to P3-40 jumper), signals are present at both
locations. With P3-39 to P3-40 connected, these signals are only
present at the test points SDO, SCK DIN and CNV.
REFERENCE
All of the ADCs for this evaluation board can use a precision
trimmed on-chip band gap reference, an on-board precision
ADR435 band gap reference, or an external reference connected
to the EXTREF test point (TP17). The on-chip reference is
enabled or disabled with the software. The on-chip reference
can be set for 2.5V or 4.096V outputs and also includes an
internal buffer, useful for external reference applications. When
using the on-chip reference, remove the jumper on TP7 since
this will overdrive the on-chip reference with the external one.
The default configuration is for on-board ADR435 reference
with a buffered output (P5 2-3), (P6 1-2) and (P7 1-2).
For using an external reference connect to the EXTREF test
point (TP17), select a buffer or not with P6 and select if driving
the ADC REF directly or using the ADC’s internal reference
buffer. When using the internal reference buffer with gain=1,
the maximum output is limited to 4.096V (headroom from 5V
supply).
The default configuration sets the amplifiers output to be at
VREF/2 (mid-scale) from the voltage divider at U1B (VBIAS).
POWER SUPPLIES AND GROUNDING
To attain high resolution performance, the board was designed
to ensure that all digital ground return paths do not cross the
analog ground return paths by connecting the planes together
directly under the converter. Power is supplied to the board
through P3 when using with the EVAL-CED1Z. For stand alone
Rev. PrD | Page 3 of 26
EVAL-AD76MUXEDZ
Preliminary Technical Data
operation, the evaluation board requires three diffeetn supplies
and system ground. Connect a supply (7V to 12V) to the analog
supplies tests points +12V and +5VA. Connect -5V to the -5VA
test point. Connect a supply (+3.3V to +5.5V max) to the FPGA
power test point, VDIG.
Connect the power supply GNDs to the GND test point at the
power supplies section of test points making certain the both
analog and digital GNDs are at the same potential.
SCHEMATICS/PCB LAYOUT
The EVAL-AD76MUXCBZ is a 6-layer board carefully laid out
and tested to demonstrate the specific high accuracy
performance of the ADC. Figure 13 through Figure 19 shows
the schematics of the evaluation board. The silkscreens for the
PCB are given in Figure 20 and Figure 22.
page. After downloading the software, it is recommended to use
the WinZip “Extract” function to extract all of the necessary
components as opposed to just clicking on setup.exe in the
zipped file. After extracting, click on seteup.exe in the folder
created during the extraction and follow the instructions on the
screen. If another version exists, it may be necessary to remove
as detailed in the above CD-ROM section.
USB Drivers
The software will also install the necessary USB drivers. After
installing the software, power up the CED board and connect to
the PC USB 2.0 port. The Windows “Found New Hardware”
Wizard will display. Click on Next to install the drivers
automatically.
HARDWARE SETUP
System Requirements
• EVAL-AD7682CBZ, EVAL-AD7689CBZ, EVALAD7699CBZ, EVAL-AD7949CBZ
• Evaluation Converter Evaluation and Development board,
EVAL-CED1Z
• Enclosed World compatible 7V DC supply
• Enlcosed USB to mini USB cable
• DC source (low noise for checking different input ranges)
• AC source (low distortion)
• Band pass filter suitable for 16 or 18 bit testing (value based
on signal frequency)
• PC operating Windows XP.
Proceed to the Software Installation section to install the
software. Note: The EVAL-CED1Z board must not be
connected to the PC’s USB port until the Software is
installed. The 7V DC supply can be connected however to
check the board has power (green LED lit).
When installed properly, Windows displays the following.
SOFTWARE INSTALLATION
It is recommended to close all Windows’ applications prior to
installing the software.
System Requirements
• PC operating Windows XP.
• USB 2.0 (for CED board)
• Administrator privileges
CD-ROM –Navigate to Software\CED Version x.x, double click
on setup.exe and follow the instructions on the screen. If
another version of Analog Devices PulSAR Evaluation Software
is present, it may be necessary to remove this. To remove, click
on the Windows “Start” button, select “Control Panel” and “Add
or Remove Programs”. When the list populates, navigate to
Analog Devices High Resolution sampling ADC’s Evaluation
Software or PulSAR Evaluation Software and select Remove.
Website Download
The software versions are also available from the Analog
Devices PulSAR Analog to Digital Converter Evaluation Kit
On some PCs, the Found New hardware Wizard may show up
again and if so follow the same procedure to install it properly.
The “Device Manager” can be used to verify that the driver was
installed successfully.
Rev. PrD | Page 4 of 26
Preliminary Technical Data
EVAL-AD76MUXEDZ
This is usually the case if the software and drivers were installed
by a user without administrator privileges. If so, log on as an
administrator with full privileges and reinstall the software.
RUNNING THE EVALUATION SOFTWARE
Troubleshooting the Install
If the driver was not installed successfully the device manager
will display a question mark for “Other devices” as Windows
does not recognize the CED1Z board.
The evaluation board includes software for analyzing the
AD7682, AD7689, AD7699 and AD7949. The EVAL-CED1Z is
required when using the software. The software is used to
perform the following tests:
• Histogram for determining code transition noise (DC)
• Fast Fourier transforms (FFT) for signal to noise ratio
(SNR), SNR and distortion (SINAD), total harmonic
distortion (THD) and spurious free dynamic range (SFDR)
• Decimation (digital filtering)
The software is located at C:\Program Files\Analog Devices\
PulSAR ADC Evaluation Software\Eval PulSAR CED.exe.
A shortcut is also added to the Windows “Start” menu under
“Analog Devices PulSAR ADC Evaluation Software”, “Eval
PulSAR CED”. To run the software, select the program from
either location.
SETUP SCREEN
Figure 2 is the setup screen where ADC device selection, test
type, input voltage range, sample rate and number of samples
are selected.
CONFIGURING THE ADC
The “USB Device” can be opened to view it’s uninstalled
properties.
These ADCs need to be configured through a dedicated SPI
compatible serial port. The included SW configures the part to a
default configuration. Each of the different configurable
parameters are shown in the ADC Configuration section,
detailed in Figure 3 to Figure 7.
DC TESTING - HISTOGRAM
Figure 9 is the histogram screen, which tests the code
distribution for DC input and computes the mean and standard
deviation or transition noise. To perform a histogram test, select
“Histogram” from the test selection window and click on the
“Start” radio button. Note: a histogram test can be performed
without an external source since the evaluation board has a
buffered VREF/2 source at the ADC input. To test other DC
values, apply a source to the J1/J2/P1-x inputs. It is advised to
filter the signal to make the DC source noise compatible with
that of the ADC.
AC TESTING
Figure 11 is the FFT screen, which performs an FFT on the
captured data and computes the SNR, SINAD, THD and SFDR.
Figure 12 is the time domain representation of the output. To
perform an AC test, apply a sinusoidal signal to the evaluation
board at the SMB inputs J1 for CH0 and J2 for CH1. Low
distortion, better than 100dB, is required to allow true
evaluation of the part. One possibility is to filter the input signal
from the AC source. There is no suggested bandpass filter but
Rev. PrD | Page 5 of 26
EVAL-AD76MUXEDZ
Preliminary Technical Data
consideration should be taken in the choice. Furthermore, if
using a low frequency bandpass filter when the full-scale input
range is more than a few Vpp, it is recommended to use the on
board amplifiers to amplify the signal, thus preventing the filter
from distorting the input signal.
Table 1. Jumper Description
Jumper
Name
P5
-
Default
Position
REFS
P6
-
BUF
P7
REF/REFIN
REF
P8
COMS
VCM
JP9
JP10
JP11
SB0-7
5V
4.096V
2.5V
BUF Select
5V
Open
Open
BUF
VDRVVDRV+
VCCREF
VDDR
VDD
VIO
-5V
7V
12V
5V
5V
3.3V
-
Function
Reference source selection.
REFS to middle pin: uses ADR435 (A1) 5V, 4.096V or 2.5V output.
VDD to middle pin: VDD supply is used as a reference.
Open: optional source can be connected to TP17/VREF.
Reference buffer selection.
BUF to middle pin: buffer selection from P5 with the AD8032-A (U2).
NOBUFF to middle pin: use P5 direct (no buffer).
ADC REF/REFIN input selection.
REF to middle pin: external source drives ADC REF pin.
REFIN to middle pin: external source drives REFIN, reference buffer input pin
Open: When using the on-chip reference.
Common channel select.
VCM to middle pin: for bipolar mode, selects VREF/2.
GND to middle pin: for unipolar operation, selects GND.
External reference selection of 5V.
External reference selection of 4.096V.
External reference selection of 2.5V.
Use on-board analog amplifiers (U13 – U20)
BUF: use amplifier
NO BUF: bypass amplifier
Amplifiers (U13-U20) (-) supply.
Amplifiers (U13-U20) (+) supply.
ADR435(A1) (+) supply.
ADC (U7) VDD supply. Must always be the same as VDD.
ADC (U7) VDD supply.
ADC (U7) VIO interface supply.
Rev. PrD | Page 6 of 26
Preliminary Technical Data
EVAL-AD76MUXEDZ
Table 2.Test Points
Test
Point
TP8
TP9
TP10
TP11
TP12
TP13
TP14
TP15
TP17
TP18
TP19
Available
Signal
GND
-5VA1
+5VA1
+12VA1
GND
VDD
VDDR
VIO
VREF
REF
REFIN
Type
Description
P
P
P
P
P
P
P
P
AI
AI/O
AI/O
TP20
TP21
TP22
TP24
TP25
TP26
TP27
TP71
TP76
IN0
IN1
COM
SDO
SCK
DIN
CNV
GND
VDIG1
AI
AI
AI
DO
DI
DI
DI
P
P
FPGA power supply GND.
Amplifier negative supply.
5V analog supply.
12V analog supply.
Analog supply GND.
ADC (U7) VDD supply.
ADC (U7) VDD supply. Must always be = AVDD above.
ADC (U7) VIO interface supply.
External reference input.
ADC on-chip reference output or external reference input.
ADC on-chip band-gap output or external reference input when using on-chip reference
buffer.
Analog input for ADC IN0 on both 4 and 8-channel ADCs.
Analog input for channel 1 on 8-channel ADCs only.
Sets the level on ADC COM; GND or VREF/2.
Serial data output from ADC.
Serial clock data input to ADC.
Serial data input for part configuration.
Conversion input to ADC
Analog supply GND.
FPGA power supply.
Table 3. Bill of Materials for the Connectors
Ref Des
J1, J2, J3
P1
P2
P4
1
Connector Type
RT Angle SMB Male
0.100 X 0.100 straight IDC header 2X10
0.100 X 0.100 straight IDC header 2X20
32X3 RT PC MOUNT CONNECTOR
Manf.
Pasternack
3M
3M
ERNI
Part No.
PE4177
2540-6002UB
2540-6002UB
533402
Supplied by EVAL-CED1Z when connected.
Rev. PrD | Page 7 of 26
EVAL-AD76MUXEDZ
Preliminary Technical Data
SOFTWARE OPERATION
1
2
3
4
5
Figure 2. Setup Screen
The following details the operation of the software.
1. The arrow
Input Range – this is used to adjust the LSB size in the data field
of the plot window.
is used to start the software. When running
is displayed.
2. The part to be evaluated is selected here.
3. The controls are used to set:
Sample Frequency – units can be used such as 500k (case
sensitive) for 500,000 Hz.
Capture Mode – This selects between continuous (Cont.) or
burst conversion modes. In continuous mode, the ADC is
continuously converting. In Burst mode, the ADC is not
converting (sample clock held in inactive state) and the
conversions begin once the “Single Capture” or “Continuous
Capture” buttons have been selected.
Interface mode – This selects the digital interface to the onboard FPGA.
4. These controls are used for saving, printing, help, etc. and are
also accessed in the File menu.
Save (F5): type – LabView config, allows the current
configuration to be saved to a filename.dat file. Useful when
changing many of the default controls. To load the saved
configuration, use the Load Previous Configuration. Note the
location of the .dat file. It is recommended to place into the
Support Files directory in the directory where the software was
installed.
Type – Html, saves the current screen shot to an Html file.
Type – Spreadsheet, saves the current data displayed in the chart
in a tab delimited spreadsheet. Raw ADC Data is time domain
in V or Code, FFT or Decimated is in dB.
5. Stop (F10) is used to stops the software. The
can also be
used to stop the software. RESET is used to reset the EVALCED1Z.
Rev. PrD | Page 8 of 26
Preliminary Technical Data
EVAL-AD76MUXEDZ
ADC CONFIGURATION
The ADC needs to be configured for input configuration,
reference, channel to be converted, temperature sensor, and onchip low pass (LP) filter (optional) for full bandwidth (BW) or
¼ BW. These next figures show the pull down configurations
available. Note the default value when the program is started is
indicated by the √; or CFG writing enabled, unipolar INn to
GND, CH0, full BW, and external reference. Note that after
updating the CFG, the first conversion (when using burst
mode) will be of the last configuration since the ADC has a 1depp delay for the CFG.
Figure 3 shows the default values.
Figure 5. Input Configuration/Channel Selection
Figure 6 details the bandwidth selection of the 1-pole low pass
filter, which can reduce the noise from the amplifier circuit, if
desired. Note that the throughout of the converter must also
reduce to ¼ of the maximum when setting to ¼ BW.
Figure 3. Default CFG
Figure 4 details CFG Write Enabled/Disabled. When enabled,
the MSB of the CFG is set high. When disabled the MSB is set
low thus the remaining 13 bits are ignored.
Figure 6.BW Select
Figure 7 details the reference selection. Note that the TEMP
sensor can be used with an external reference. The Temp sensor
can be used to monitor the temperature of the ADC and the
output is straight binary and referenced to the ADC GND. The
displayed results should be in Volts format as opposed to Hex.
Figure 4. CGF Enable/Disable Selection
Figure 5 details the inputs (IN0-IN7) configuration and channel
selection. Refer to the datasheet for more information about the
input configure-ations. Note that in the bipolar mode, the input,
IN+ and COM (or IN-) must be centered around VREF/2.
Figure 7. Reference Selection
Rev. PrD | Page 9 of 26
EVAL-AD76MUXEDZ
Preliminary Technical Data
1
Figure 8. Context Help, User Controls
2
1. To use the on-screen help. Select Help, Show Context Help or
click the Help (F1). An example of the Context Help is shown
above for the Sample Frequency. Placing the curser on most
screen items displays useful help for the particular control or
displayed unit.
,
are used to set axes properties such as format,
precision, color, etc.
Displays the cursor.
2. These controls are used for axes and zooming panning.
Is used For zooming in and out.
Locks the graph axis to automatically fit the data.
Uses last axis set by user.
automatic values.
,
Is used for panning.
rescale the axes to the
Is used to set various graph properties such as graph
type, colors, lines, etc.
Rev. PrD | Page 10 of 26
Preliminary Technical Data
EVAL-AD76MUXEDZ
1
Figure 9. Histogram Screen
2
3
1. These radio buttons are used to perform a Single Capture or
Continuous Capture of data set in the # of Samples field. The
results are displayed in the chart. Note that the results can be
displayed as:
Or an
(time domain)
2., 3.These display the statistics for the X and Y-axes,
respectively.
A
Rev. PrD | Page 11 of 26
EVAL-AD76MUXEDZ
Preliminary Technical Data
Figure 10. Summary
The charts can be displayed together when the
tab is selected.
Rev. PrD | Page 12 of 26
Preliminary Technical Data
EVAL-AD76MUXEDZ
1
1
3
2
Figure 11. FFT Spectrum
1. Displays the FFT when the Spectrum chart is selected
2., 3. Display the data for the X and Y-axes, respectively.
Rev. PrD | Page 13 of 26
EVAL-AD76MUXEDZ
Preliminary Technical Data
1
Figure 12 .Oscilloscope
1. Time domain data can be viewed with the oscilloscope also.
Rev. PrD | Page 14 of 26
Figure 13. Schematic, ADC + Block Diagram
Rev. PrD | Page 15 of 26
A
B
C
8
7
7
VDRV -
VDRV +
VDD
VCCRE F
ANALO G
6
COM
I N7 / I N 3
I N6
I N5 / I N 2
I N4
I N3
I N2 / I N 1
I N1
I N0 / I N 0
REFI N
REF
1
TP1
BL K
GND
- 5VA
VDI G
TP2
BL K
EN_ 7V_ N
VI O
1
EN_ 5V_ N
VDDR
VDD
EN_ 3. 3V_ N
+5VA
1
5
GND
C1
2
3
4
5
1
1
TOP
VCCRE F
+1 2V A
VPL LA 2
POWE R
VPL LA 1
VDRV -
2
VDRV +
VFPGA
VI O_FPG A
5
C2
TP3
BL K
7
6
BOTTOM
1
8
9
TBD0805
PAD
20
6
10UF
C3
19
18
17
16
TP4
BL K
10
2
BOTTOM
0. 1UF
0. 1UF
BOTTOM
BOTTOM
TP6
BL K
1
TP7
BL K
4
TP8
BL K
1
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TP7 4
BL K
3
DSPCL K
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D I N FURNI SHIGN I NFORMATIN O TO OTHERS
,
I T I S NOT TO BE REPRODUCE
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.
A N A L OG
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CONTRO L
RESE T
RESE T
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BWR_ N
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BRD_ N
BCS_ N
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TP7 1
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9 6_ pi n
AD<0. . 4 >
BD<0. . 15 >
GND
VDI G
- 5VA
+5VA
BWR_ N
GND
GND
- 12 V A
+12 V A
BRD_ N
1
3
BBUS Y
BCS_ N
BD<0 . . 15 >
SCK
1
VI O
FPGA
VFPGA
VI O_FPGA
VPLLA1
VPLLA2
SDO
CNV
1
BOTTOM
DI N
TP5
BL K
0. 1UF
11
1
0. 1UF
GND
4
EN_3. 3V_N
EN_5V_N
EN_7V_N
15
14
13
12
U7
1
2
C4
1
2
C5
1
2
C6
1
D
8
2
2
<PTDE_ENGI NEER>
PTDE ENGI NEER
ad7689_c s p_t opl evl e
DESI GN VI EW
Topl evel
AD7689/ 82/ 99/ 92
<PRODUCT_1
>
REV
REVI SI ON S
DD
SI ZE
SCALE
1
1
SHEET
DATE
DRAWI NG NO.
SCHEMATI C
DESCRI PTI O
N
1
OF 7
A
REV
APPROVED
A
B
C
D
Preliminary Technical Data
EVAL-AD76MUXEDZ
EVALUATION BOARD SCHEMATICS AND ARTWORK
VDI G
8
EN_7V_N
EN_5V_N
EN_3. 3V_N
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
IN
IN
IN
IN
IN
IN
IN
VI O_FPGA
VPLLA2
VPLLA1
VFPGA
VCCREF
VDDR
VDD
VI O
VDRV-
VDRV+
7
EXT
EXT
1
TP1 2
YEL
- 5VA
- 5VA
TP9
1 WHT
+3. 3V
EXT
+5V
EXT
+5V
EXT
+5V
+7V
+12VA
GND
GND
TP44 TP45 TP46
1 RED 1 RED 1 RED
A
B
C
- 5VA
+5VA
+12VA
- 5VA
+5V
TP31
RED
TP37
+7V
GND
GND
TP1 6
BL K
1
GND
C1 2
10UF
GND
C11
10UF
1
1
1
+5VA
+5VA
TP1 0
1 RED
VI O
VDDR
VDD
GND
C1 3
10UF
VCCREF
VDRV-
VDRV+
6
+12VA
+12VA
TP1 1
1 RED
GND
C1 6
10UF
TP1 5
BL U
VI O
GND
C1 5
10UF
VDDR
TP1 4
BL U
GND
C1 4
10UF
TP1 3
BL U
VDD
1
GND
1K
R5
GND
R2
2K
GND
ADP1715ARMZ-7R
R1
1K 1
EN
2 I N U9 OUT 3
4 ADJ
GND
5 6 7 8
LDO ADJ USTE D TO 1 . 2 V
R6
2K
ADP1715ARMZ-7R
EN
2 I N U11 OUT 3
4 ADJ
GND
5 6 7 8
1
LDO ADJ USTED TO 1. 2V
R4
2K
ADP1715ARMZ-7R
EN
2 I N U1 0 OUT 3
4 ADJ
GND
5 6 7 8
1
LDO ADJ USTED TO 1. 2V
1K
R3
0
1 R7 2
0
1 R9 2
0
1 R8 2
5
VDI G
U8
GND
8 I N2 OUT2 2
6 SD*
FB 3
PAD GND
PAD
5
ADP3334ACP
Z
7 I N1 OUT1 1
R5 5
140 K
4
VFPGA
VPLLA2
VPLLA1
VI O_FPGA
REGUL ATE S FPGA VI O SUPPLI E S TO 3 . 3 V ( MAX AL LOWED)
VDI G
VDI G
TP7 6
RED
VDI G
FPGA SUPPLI ES
3
3
A N A L OG
DE V CE S
10K
1 R1 2 2
10K
1 R11 2
10K
1 R1 0 2
THE EQUI PMEN
T SHOW
N HEREO
N MAY BE PROTECTE
D BY PATENT
S
OWNE
D OR CONTROLLE
D BY OWNE
D ANALO
G DEVI CES
.
OF ANALO
G DEVI CES.
OR FOR ANY OTHE
R PURPOS
E DETRI MENTA
L TO THE I NTEREST
S
I N PART
, OR USE
D I N FURNI SHIGN I NFORMATIN O TO OTHERS
,
I T I S NOT TO BE REPRODUCE
D OR COPI ED
, I N WHOL
E OR
THIS DRAWI G
N I S THE PROPERT
Y OF ANALO
G DEVI CE
S I NC
.
VI O_FPGA
EN_7V_N
+12VA
VI O_FPGA
EN_5V_N
+12VA
VI O_FPGA
EN_3. 3V_N
+5VA
2
U1 2
R1 3
140 K
2
DD
SCALE
DRAWI NG NO.
<PTDE_ENGI NEER>
powe r
SI ZE
1
OF 7
A
REV
APPROVED
SHEET 2
+7V
+5V
+3. 3V
PTDE ENGI NEER
SCHEMATI C
0
1 R21 2
0
1 R2 0 2
0
1
DATE
DESI GN VI EW
<PRODUCT_1
>
Topl evel
AD7689/ 82/ 99/ 92
GND
8 I N2 OUT2 2
6 SD*
FB 3
PAD GND
PAD
5
ADP3334ACP
Z
7 I N1 OUT1 1
U4
GND
8 I N2 OUT2 2
6 SD*
FB 3
PAD GND
PAD
5
ADP3334ACP
Z
7 I N1 OUT1 1
U3
GND
7 I N1 OUT1 1
8 I N2 OUT2 2
6 SD*
FB 3
PAD GND
PAD
5
ADP3334ACP
Z
1 R1 9 2
REVI SI ON S
DESCRI PTI O
N
ANALOG SUPPLI ES
REV
1000PF
SUPPLY OPTI ONS
C24
2
C25
2
2
2
4
1
1
1
TP34
1 RED
RED
1
TP43
1 RED
TP40
C18
2
C19
2
C17
2
C7
RED
1
C22
2
+12VA
2. 2UF
C30
2
5
P9
6
1
2. 2UF
D
7
2
Rev. PrD | Page 16 of 26
C8
Figure 14. Schematic, Supplies
1000PF
C32
C33
8
TP38
TP39
1 RED 1 RED
C9
TP41
TP42
1 RED 1 RED
TP47
1 RED
1
1
1
2. 2UF
2. 2UF
2. 2UF
C21
1 2
1
C20
1 2
0. 1UF
0. 1UF
2. 2UF
2. 2UF
2. 2UF
C23
1 2
2
2
2
2
1
R56
TP35
TP36
1 RED 1 RED
0. 1UF
1
2. 2UF
C26
C27
C28
2. 2UF
2. 2UF
2. 2UF
C29
1 2
1
C31
1 2
1 R14 2 2
78. 7K
1000PF
1 R15 2
210K
1 R16 2
64. 9K
300K
TP32
TP33
1 RED 1 RED
1000PF
1 R17 2
TP28 TP29 TP30
1 RED 1 RED 1 RED
1
1 R182
60. 4K
1
2. 2UF
1
C34
1
2. 2UF
1
78. 7K
A
B
C
D
EVAL-AD76MUXEDZ
Preliminary Technical Data
Figure 15. Schematic, Reference, Buffer, VCM, VBIAS
Rev. PrD | Page 17 of 26
A
B
C
8
VCCREF
0
R2 2
OUT
REFI N
REF
C35
OUT
10UF
GND
1
TP
8
NC2 7
6
TP1
VOUT
5
TRI M
ADR435BR
Z
2 VI N
3 NC1
4 GND
A1
C37
7
10K
1 R2 3 2
5V
1 JP9 2
VDD
4. 096V
1 R242 1 JP10 2
45. 3K
VCCREF
2. 5V
1 R252 1 JP11 2
P5
VREF
REFS
VDD
5
1
6
2
3
VDD
VREF
TP1 7
1 YEL
1K
R2 6
1 R2 7 2
TBD0 805
GND
C3 8
10UF
3
2
C3 9
2
5
U2
1K
R2 8
1
P6
BUF
NOBUF
AD8032AR
Z
TBD0805
1
8
VCCREF
4
V-
V+
GND
U2
4
0. 1UF
C4 0
1
1K
R2 9
REFI N
TP1 9
1 BL U
REFI N
TP1 8
BL U
REF
REF
P7
4
REFI N
1
2
3
1
REF
2
3
AD8032AR
Z
EXTERNAL REFERENCE OPTI ONS
6
GND
C4 1
10UF
5
6
U2
7
AD8032AR
Z
3
3
THE EQUI PMEN
T SHOW
N HEREO
N MAY BE PROTECTE
D BY PATENT
S
OWNE
D OR CONTROLLE
D BY OWNE
D ANALO
G DEVI CES
.
OF ANALO
G DEVI CES.
OR FOR ANY OTHE
R PURPOS
E DETRI MENTA
L TO THE I NTEREST
S
I N PART
, OR USE
D I N FURNI SHIGN I NFORMATI
N O TO OTHERS
,
I T I S NOT TO BE REPRODUCE
D OR COPI ED
, I N WHOL
E OR
THIS DRAWI G
N I S THE PROPERT
Y OF ANALO
G DEVI CE
S I NC
.
A N A L OG
DE V CE S
10K
1 R31 2
10K
R3 0
REV
2
GND
5
6
U1
AD8032AR
Z
GND
C4 3
10UF
7
0. 1UF
C4 4
VBI AS
VCM
2
D
SCALE
DRAWI NG NO.
<PTDE_ENGI NEER>
anal og
SI ZE
GND
PTDE ENGI NEER
SCHEMATI C
1
2
GND
VCCREF
AD8032AR
Z
V-
4
1
AD8032AR
Z
V+
8
U1
U1
1
1
OF 7
A
REV
APPROVED
SHEET 3
DATE
DESI GN VI EW
Topl evel
AD7689/ 82/ 99/ 92
<PRODUCT_1
>
GND
C4 2
10UF
GND
3
2
C4 5
10UF
REVI SI ON S
DESCRI PTI O
N
BI ASI NG USI NG ADC REF
10K
D
7
R32
1 R33 2
10K
8
A
B
C
D
Preliminary Technical Data
EVAL-AD76MUXEDZ
GND
10K
2. 2UF
1
0. 1UF
C36
2
1
1
8
GND
2 3 4 5
EXT_COM
R4 9
TBD0805
0
CH7/ CH3
CH6
CH5/ CH2
CH4
CH3
CH2/ CH1
CH1
CH0/ CH0
COM
I N7/ I N3
I N6
I N5/ I N2
I N4
I N3
I N2/ I N1
I N1
I N0/ I N0
R3 5
12
13
14
15
16
11
10
8
9
7
2
3
4
5
6
J3
GND
P1
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
1
CH1
GND
2 3 4 5
J2
GND
2 3 4 5
J1
1
CH0/ CH0
7
VBI AS
VBI AS
2
1
GND
C4 7
0. 1U F
59 0
R4 3
0
1 R41 2
TBD0805
1 R4 2 2
1 R4 0 2
TBD0805
GND
59 0
C4 6
0. 1U F
1 R3 9 2
0
1 R3 7 2
TBD0805
1 R3 8 2
1 R3 6 2
TBD0805
TBD0805
2
6
TBD0805
C4 9
49. 9
1 R4 7 2
C4 8
1
49. 9
1 R4 6 2
V+
4
C5 6
C5 7
0. 1U F
0
ADA4841- 1YR
Z
1 U1 4
1 R5 2 2
6
N1
PD_N
8
5
N2
TBD0805
V-
0. 1U F
C5 5
0
1 R5 0 2
V+
7
VDRV-
3
2
C51
1
C5 4
0. 1U F
TBD0805
VDRV+
2
C5 3
TBD0805
0
ADA4841- 1YR
Z
1 U1 3
1 R5 1 2
6
N1
0. 1U F
C5 2
0
1 R4 8 2
PD_N
N2
V8
5
4
VDRV-
3
7
VDRV+
2
C5 0
2
1
TBD0805
5
1
I N1
1
5
BL U
TP2 0
I N0/ I N0
TP2 1
BL U
22
1 R5 3 2
22
1 R5 4 2
2700PF
2
GND
C5 9
1
I N1
2700PF
2
GND
C5 8
1
I N0/ I N0
ADC BUFFERS
4
4
CH3
CH2/ CH1
VBI AS
VBI AS
2
1
2
1
GND
A
B
C
D
R45
R156
VDRV-
1 R442
TBD0805
TBD0805
6
RED
GND
GND
GND
GND
RED
TP58
1 RED
TP57
10K
10K
1
RED
R157
Rev. PrD | Page 18 of 26
1
TP54
TP55
1 RED
1
Figure 16. Schematic, AnalogCH0-CH3
RED
1
TP56
TP59
VDRV+
7
59 0
GND
C6 2
0. 1U F
59 0
1 R6 4 2
0
1 R6 2 2
TBD0805
1 R6 3 2
1 R61 2
TBD0805
GND
0. 1U F
C61
1 R6 0 2
0
1 R5 8 2
TBD0805
1 R5 9 2
1 R5 7 2
TBD0805
3
3
1 R652
TBD0805
2
1
2
1
3
2
4
I N PART
, OR USE
D I N FURNI SHIGN I NFORMATIN O TO OTHERS
,
I T I S NOT TO BE REPRODUCE
D OR COPI ED
, I N WHOL
E OR
OR FOR ANY OTHE
R PURPOS
E DETRI MENTA
L TO THE I NTEREST
S
0
C7 0
N2
2
0
C71
C7 2
2
<PTDE_ENGI NEER>
PTDE ENGI NEER
anal og
DESI GN VI EW
<PRODUCT_1
>
Topl evel
AD7689/ 82/ 99/ 92
0. 1U F
0
ADA4841- 1YR
Z
1 U1 6
6
1 R7 3 2
N1
PD_N
8
5
0. 1U F
TBD0805
V-
V+
THE EQUI PMEN
T SHOW
N HEREO
N MAY BE PROTECTE
D BY PATENT
S
OWNE
D OR CONTROLLE
D BY OWNE
D ANALO
G DEVI CES
.
OF ANALO
G DEVI CES.
C6 6
2
1 R71 2
7
VDRV-
3
C6 9
0. 1U F
TBD0805
VDRV+
2
C6 8
TBD0805
1
REV
ADA4841- 1YR
Z
1 U1 5
1 R7 2 2
6
N1
0. 1U F
PD_N
N2
V8
5
4
V+
C6 7
0
1 R6 9 2
7
VDRV-
A N A L OG
DE V CE S
TBD0805
C6 4
49. 9
1 R6 8 2
TBD0805
C6 3
49. 9
1 R6 7 2
C6 5
2
1
TBD0805
VDRV+
THIS DRAWI G
N I S THE PROPERT
Y OF ANALO
G DEVI CE
S I NC
.
1 R66 2
TBD0805
GND
GND
GND
GND
GND
DD
SI ZE
SCALE
1
SHEET 4
2700PF
2
GND
C7 4
1
I N3
2700PF
GND
OF 7
A
REV
APPROVED
I N2/ I N1
C7 3
1
DRAWI NG NO.
SCHEMATI C
22
1 R7 5 2
22
1 R7 4 2
1
DATE
2
REVI SI ON S
DESCRI PTI O
N
RED
TP52
1 RED
RED
TP51
1
RED
1
TP48
TP49
1 RED
1
GND
RED
1
TP50
TP53
8
A
B
C
D
EVAL-AD76MUXEDZ
Preliminary Technical Data
GND
8
CH5/ CH2
VBI AS
VBI AS
1
2
1
GND
Figure 17. Schematic, AnalogCH4-CH7
2
1 R8 2 2
GND
7
59 0
C7 7
0. 1U F
1 R8 5 2
0
1 R8 3 2
TBD080
5
1 R8 4 2
TBD0805
GND
59 0
C7 6
0. 1U F
1 R81 2
0
2
1
TBD0805
TBD0805
C7 9
49. 9
1 R8 9 2
C7 8
1
2
1 R8 8 2
49. 9
V+
7
N1
C8 6
0. 1U F
C8 7
6
0
ADA4841- 1YR
Z
1 U1 8
6
1 R9 4 2
N1
PD_N
8
5
N2
TBD0805
V-
V+
4
VDRV-
3
0. 1U F
C8 5
1 R9 2 2
0
7
VDRV+
2
2
C81
1
C8 4
0. 1U F
TBD0805
VDRV-
C8 3
TBD0805
0
ADA4841- 1YR
Z
1 U1 7
1 R9 3 2
6
0. 1U F
C8 2
PD_N
3
N2
V8
5
4
2
VDRV+
0
1 R9 0 2
TBD0805
C8 0
1 2
6
RED
TP67
1 RED
A
B
C
CH4
1 R7 9 2
TBD0805
1 R8 0 2
1 R7 8 2
TBD0805
1 R862
TBD0805
1 R87 2
TBD0805
GND
GND
GND
GND
TP63
TP64
1 RED
1 RED
TP66
1
RED
1
RED
1
TP65
TP68
7
EXT_COM
VCM
22
1 R9 8 2
22
1 R9 7 2
22
R9 9
5
1
2
3
2700PF P8
GND
C91
2700PF
2
GND
C8 9
1
I N5/ I N2
2700PF
2
GND
C8 8
1
I N4
GND
4
CH7/ CH3
CH6
ADC BUFFERS CONTI NUED
4
1
COM
BL U
TP2 2
COM
VBI AS
VBI AS
1
2
1
2
R10 62
GND
59 0
C9 3
0. 1U F
1 R10 92
0
1 R10 72
TBD080
5
1 R10 82
1
TBD0805
GND
59 0
C9 2
0. 1U F
1 R10 52
0
1 R10 32
TBD0805
1 R10 42
1 R10 22
TBD0805
1
2
3
V+
7
N1
A N A L OG
DE V CE S
0. 1U F
C10 3
I N PART
, OR USE
D I N FURNI SHIGN I NFORMATIN O TO OTHERS
,
I T I S NOT TO BE REPRODUCE
D OR COPI ED
, I N WHOL
E OR
OR FOR ANY OTHE
R PURPOS
E DETRI MENTA
L TO THE I NTEREST
S
THE EQUI PMEN
T SHOW
N HEREO
N MAY BE PROTECTE
D BY PATENT
S
OWNE
D OR CONTROLLE
D BY OWNE
D ANALO
G DEVI CES
.
OF ANALO
G DEVI CES.
0
2
2
<PTDE_ENGI NEER>
PTDE ENGI NEER
anal og
DESI GN VI EW
<PRODUCT_1
>
Topl evel
AD7689/ 82/ 99/ 92
ADA4841- 1YR
Z
1 U2 0
6
1 R11 82
N1
C10 2
N2
PD_N
8
5
0. 1U F
C10 1
0
R11 62
TBD0805
V-
V+
4
VDRV-
3
1
7
VDRV+
2
C9 7
2
1
0. 1U F
C10 0
TBD0805
VDRV-
C9 9
TBD0805
0
ADA4841- 1YR
Z
1 U1 9
1 R11 72
6
0. 1U F
C9 8
0
1 R11 42
PD_N
3
N2
V8
5
4
2
VDRV+
TBD0805
C9 6
1 2
REV
TP70
1 RED
THIS DRAWI G
N I S THE PROPERT
Y OF ANALO
G DEVI CE
S I NC
.
TBD0805
C9 5
49. 9
1 R11 32
C9 4
TBD0805
1
49. 9
R11 22
2
1
3
RED
5
1
Rev. PrD | Page 19 of 26
TP79
GND
GND
D
8
GND
RED
TP77
1
1 R1102
TBD0805
1 R111 2
TBD0805
GND
GND
GND
GND
RED
1
1
1 RED
TP69
1
TP62
TP72
TP60
TP61
RED
1 RED
RED
2700PF
GND
C10 5
1
2
I N7/ I N3
2700PF
GND
C10 4
1
2
DD
SI ZE
SCALE
1
1
OF 7
A
REV
APPROVED
SHEET 5
DATE
DRAWI NG NO.
SCHEMATI C
22
1 R12 02
22
1 R11 92
I N6
REVI SI ON S
DESCRI PTI O
N
A
B
C
D
Preliminary Technical Data
EVAL-AD76MUXEDZ
TP78
1 RED
A
B
C
SUPPLI ES
CNV
DI N
SCK
1
1
1
1
OUT
OUT
OUT
OUT
OUT
8
DSPCLK
OUT
CONTROL
OUT
RESET
BWR_N
BRD_N
BBUSY
BCS_N
BD<0. . 15>
OUT
AD<0. . 4>
OUT
96_PI N_I / O
IN
IN
IN
IN
SDO
OUT
OUT
OUT
GND
DUT_I / O
GND
EN_7V_N
EN_5V_N
EN_3. 3V_N
VI O_FPGA
VPLLA2
VPLLA1
VFPGA
VI O
BL U
TP2 7
BL U
TP2 6
BL U
TP2 5
BL U
TP2 4
CNV
DI N
SDO
SCK
R128
VI O
GND
GND
7
TBD0603
0
R12 4
C10 7
C108
10K
R12 3
GND
10K
. 1UF
GND
1
GND
GND
MCLK
MCLK
TP7 3
YEL
1
6
U6
VFPGA
L6
GND
L4
M4
C2
D5
E5
E3
E4
D3
G2
C1
P2
P3
P1
L3
N2
N1
J4
M2
M3
L2
N_CSO F4
M1
L1
K4
K5
K1
K2
E2
E1
F3
GND_PLL1
VPLLA1
GND
N5
NCE
DCLK
DATA0
CLK2
CLK3
L5
TMS
TDI
TCK
NCONFI G
BANK_1
GND
LA_D<0. . 31>
LA_D<0. . 31>
TDO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
J2
EP2C5F256C7
N
G1
H5
F2
G5 PS_STATUS_N
J 5 PS_CONFI G_N
H4 PS_DCLK
J1
F1 DATA
ASDO C3 I O VCCD_PLL1CLK0 H2 MCLK
D4
H1
CLK1
IO
EN_5V_N
EN_7V_N
Y3
3
OUT 3
EN
GND
2
GND
P3
V+
5
7
4
3
15K
VCCA_PLL2
0
0
1
4
4
100MH Z
VI O
VCCI NT
H7
VI O_FPGA
1
1
2
5
5
4
5
6
2
2
3
6
6
7
8
7
10
15K
P10
H10
L7
U6
R3
T3
P5
P4
T4
R4
T5
R5
T6
N8
T7
R7
10
11
9
8
9
GND
8
10
R125
1
13
11
10K
2
14
GND
15
R130
VFPGA
G9
P11
VCCI O1
VCCI O1
J7
B1
12
10K
1
G3
16
13
C110
2
2
D10
2
K3
R1
17
14
M5
VI O_FPGA
BANK_2
VI O_FPGA
VCCI O2
VCCI O3
GND
POWER_FPGA
A2
BANK_4
19
R126
R132
A15
LA_CLK1
20
16
20
12
9
11
23
10K
24
C109
GND
T1
26
1000PF
E12
U6
B14
A14
C13
C12
B13
A13
B11
B12
A12
A11
C11
G10
G11
B10
A10
F10
F9
D11
VCCA_PLL1
C7
21
17
21
18
15
12
13
14
15
16
17
18
19
22
18
R12 2
19
8
9
20
GND
10
3M2510- 5002U
B
R15
25
21
VPLLA2
VCCI O4
EP2C5F256C7
N
J8
4
30
8N
J9
28
1000PF
T16
22
22
23
24
25
26
27
7
K9
H9
29
30
27
23
28
29
PS_CDONE_N
VI O_FPGA
PS_CONFI G_N
PS_STATUS_N
DATA
N_CSO
ASDO
25
D
A16
U6
LA_CLK2
LA_CLK1
26
1
30
nCS
2
8
DATA
PS_DCLK 6 DCLK DATA
5
ASDO
ASDI
GND
4
EPCS4SI
GND
B2
27
N_CSO
A1
31
24
31
MSEL0
MSEL1
DSPCLK
CLK7
VFPGA
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
LA_CLK2
F1 2
GND
3
GND
BWR_N
RESET
CONTROL
BBUSY
BRD_N
BCS_N
ADCOK
BD<11>
AD<0>
AD<1>
AD<2>
AD<3>
AD<4>
BD<12>
BD<13>
BD<14>
BD<15>
BD<10>
BD<0>
BD<1>
BD<2>
BD<3>
BD<4>
BD<5>
BD<6>
BD<7>
BD<8>
BD<9>
PS_CDONE_N
GND
. 1UF
C11 2
VFPGA
. 1UF
C11 4
EP2C5F256C7
N
U6
L1 3
H1 3
D1 5
D1 6
E1 6
C1 4
D1 3
E1 4
D1 4
N1 2
M1 2
N1 3
N1 4
P1 4
P1 5
P1 6
N1 5
N1 6
M1 5
M1 6
M1 4
L1 4
L1 5
L1 6
K1 6
K1 5
H1 2
J12
G1 6
G1 5
F1 5
F1 6
J 11
H11
G1 2
G1 3
M1 3
VI O_FPGA
D1 2
NSTATUS
GND_PLL2
BANK_3
MSEL1
J13
MSEL0
K1 2
F11
VCCD_PLL2
H1 6
CLK4
CONF_DONE
H1 5
CLK5
IO
J15
CLK6
IO
J16
GND
R12 1
10K
B15
28
GND
A9
B9
A8
A7
B7
F7
F8
D8
B6
A6
G6
G7
C10
E7
E10
B16
G14
K14
R16
M7
M10
P7
P10
T2
G8
C9
E8
E9
H3
H14
J3
J14
M8
M9
P8
H8
P9
R2
T15
C8
29
32
33
34
35
36
EP2C5F256C7N M6
VI O_FPGA
31
37
GNDA_PLL2
EP2C5F256C7N
E11
D6
C6
C5
C4
B5
A5
B4
A4
A3
B3
E6
F6
GNDA_PLL1
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
L8
T8
R8
T9
R9
N9
N10
T11
R11
P11
L9
L10
R10
T10
K11
K10
N11
P12
P13
T12
R12
L12
T13
R13
T14
R14
M11
L11
38
39
. 1UF
GND
C111
PS_DCLK
A N A L OG
DE V CE S
VI O_FPGA
OR FOR ANY OTHE
R PURPOS
E DETRI MENTA
L TO THE I NTEREST
S
THE EQUI PMEN
T SHOW
N HEREO
N MAY BE PROTECTE
D BY PATENT
S
OWNE
D OR CONTROLLE
D BY OWNE
D ANALO
G DEVI CES
.
OF ANALO
G DEVI CES.
10K
R13 4
VI O_FPGA
I N PART
, OR USE
D I N FURNI SHIGN I NFORMATIN O TO OTHERS
,
I T I S NOT TO BE REPRODUCE
D OR COPI ED
, I N WHOL
E OR
THIS DRAWI G
N I S THE PROPERT
Y OF ANALO
G DEVI CE
S I NC
.
. 1UF
1
C115
2
3
4
5
6
. 1UF
2
2
C11 9
. 1UF
REV
. 1UF
. 1UF
C11 7
10K
R13 5
. 1UF
P2
C116
U5
2
<PTDE_ENGI NEER>
PTDE ENGI NEER
f pga
DESI GN VI EW
<PRODUCT_1
>
ADCOK
R13 6
MSEL1
60. 4
1 R14 52
10K
1 R14 42
10K
1 R14 32
10K
1 R14 22
10K
1 R14 12
10K
1 R14 02
10K
1 R13 92
10K
1 R13 82
GND
R13 7
0
CR1
. 1UF
C12 3
A
R15 0
0
CADCOK
GND
R15 1
VCCI O1
GND
DD
SI ZE
SCALE
DRAWI NG NO.
SCHEMATI C
VI O_FPGA
VI O_FPGA
APPROVED
. 1UF
1
SHEET 6
. 1UF
1
DATE
OF 7
A
REV
. 1UF
REVI SI ON S
DESCRI PTI O
N
VI O_FPGA
C12 1
. 1UF
DSPCLK
CONTROL
RESET
BWR_N
BRD_N
BBUSY
BCS_N
MSEL0
2
Topl evel
AD7689/ 82/ 99/ 92
C118
3
C120
2
4
. 1UF
2
. 1UF
5
C122
3 7
VCC
6
C131
VI O_FPGA
C124
2
2
GND
GND
GND
GND
GND
7
. 1UF
GND
. 1UF
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
40
C127
8
C125
GND
. 1UF
. 1UF
Rev. PrD | Page 20 of 26
C126
Figure 18. Schematic, FPGA
C129
1
C128
1
1
1
. 1UF
1
1
C130
1
1
C113
A
B
C
D
EVAL-AD76MUXEDZ
Preliminary Technical Data
EN_3. 3V_N
Figure 19. Schematic, 96-Pin Interface
Rev. PrD | Page 21 of 26
A
B
C
D
8
8
7
7
BD<10>
BD<11>
BD<12>
BD<13>
BD<14>
BD<15>
BD<0>
BD<1>
BD<2>
BD<3>
BD<4>
BD<5>
BD<6>
BD<7>
BD<8>
BD<9>
4
3
2
1
0
AD<0>
AD<1>
AD<2>
AD<3>
AD<4>
OUT
6
OUT VDI G
OUT GND
OUT +5VA
OUT - 5VA
OUT +12VA
OUT - 12VA
OUT CONTROL
OUT DSPCLK
OUT BWR_N
OUT RESET
BCS_N
OUT BBUSY
OUT BRD_N
OUT
AD<0. . 4>
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
BD<0. . 15>
OUT
6
GND
- 12VA
- 5VA
+5VA
RESET
BD<12>
DSPCLK
AD<3>
AD<1>
VDI G
BRD_N
A1 0
A11
A1 2
A1 3
A1 4
A1 5
A1 6
A1 7
A1 8
A1 9
A2 0
A21
A2 2
A2 3
A2 4
A2 5
A2 6
A2 7
A2 8
A2 9
A3 0
A31
A3 2
A7
A8
A9
A2
A3
A4
A5
A6
A1
5
ERNI 53340
2
P4
5
GND
- 5VA
+5VA
BD<11>
BD<13>
BD<10>
BD<8>
BD<9>
BD<5>
BD<6>
BD<7>
VDI G
BD<2>
BD<3>
BD<4>
BD<0>
BD<1>
CONTROL
B1 0
B11
B1 2
B1 3
B1 4
B1 5
B1 6
B1 7
B1 8
B1 9
B2 0
B21
B2 2
B2 3
B2 4
B2 5
B2 6
B2 7
B2 8
B2 9
B3 0
B31
B3 2
B7
B8
B9
B2
B3
B4
B5
B6
B1
4
ERNI 53340
2
P4
4
GND
+12VA
- 5VA
+5VA
BBUSY
BD<14>
BD<15>
AD<4>
AD<2>
AD<0>
VDI G
BWR_N
BCS_N
C1 0
C11
C1 2
C1 3
C1 4
C1 5
C1 6
C1 7
C1 8
C1 9
C2 0
C21
C2 2
C2 3
C2 4
C2 5
C2 6
C2 7
C2 8
C2 9
C3 0
C31
C3 2
C7
C8
C9
C2
C3
C4
C5
C6
C1
3
ERNI 53340
2
P4
3
THE EQUI PMEN
T SHOW
N HEREO
N MAY BE PROTECTE
D BY PATENT
S
OWNE
D OR CONTROLLE
D BY OWNE
D ANALO
G DEVI CES
.
OF ANALO
G DEVI CES.
OR FOR ANY OTHE
R PURPOS
E DETRI MENTA
L TO THE I NTEREST
S
I N PART
, OR USE
D I N FURNI SHIGN I NFORMATIN O TO OTHERS
,
I T I S NOT TO BE REPRODUCE
D OR COPI ED
, I N WHOL
E OR
THIS DRAWI G
N I S THE PROPERT
Y OF ANALO
G DEVI CE
S I NC
.
A N A L OG
DE V CE S
2
<PTDE_ENGI NEER>
PTDE ENGI NEER
96_pin
DESI GN VI EW
<PRODUCT_1
>
2
Topl evel
AD7689/ 82/ 99/ 92
REV
REVI SI ON S
DD
SI ZE
SCALE
1
1
SHEET
DATE
DRAWI NG NO.
SCHEMATI C
DESCRI PTI O
N
7
OF 7
A
REV
APPROVED
A
B
C
D
Preliminary Technical Data
EVAL-AD76MUXEDZ
EVAL-AD76MUXEDZ
Preliminary Technical Data
Figure 20. Top Side Silk-Screen
(Viewed from top side)
Figure 21. Inner Layer 1
(Viewed from top side)
Rev. PrD | Page 22 of 26
Preliminary Technical Data
EVAL-AD76MUXEDZ
Figure 22. Ground Plane
(Viewed from top side)
Figure 23. Inner Layer 2
(Viewed from top side)
Rev. PrD | Page 23 of 26
EVAL-AD76MUXEDZ
Preliminary Technical Data
Figure 24.Inner Layer 3
(Viewed from top side)
Figure 25. Bottom Layer
(Viewed from top side)
Rev. PrD | Page 24 of 26
Preliminary Technical Data
EVAL-AD76MUXEDZ
Figure 26. Bottom Layer
(Viewed from Bottom Side)
Rev. PrD | Page 25 of 26
EVAL-AD76MUXEDZ
Preliminary Technical Data
ORDERING GUIDE
Evaluation Board Model
EVAL-AD7682EDZ
EVAL-AD7689EDZ
EVAL-AD7699EDZ
EVAL-AD7949EDZ
EVAL-CED1Z
Product
AD7682BCPZ
AD7689BCPZ
AD7699BCPZ
AD7949BCPZ
Capture/Controller Board
©2009 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
EB08140-0-3/09(PrD)
Rev. PrD | Page 26 of 26
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