16-Bit, 8-Channel, 500 kSPS PulSAR ADC AD7699

16-Bit, 8-Channel, 500 kSPS PulSAR ADC AD7699

Data Sheet

FEATURES

16-bit resolution with no missing codes

8-channel multiplexer with choice of inputs

Unipolar single-ended

Differential (GND sense)

Pseudobipolar

Throughput: 500 kSPS

INL: ±0.5 LSB typical, ±1.5 LSB maximum (±23 ppm or FSR)

Dynamic range: 93.3 dB

SINAD: 91.5 dB at 20 kHz

THD: −97 dB at 20 kHz

Analog input range: 0 V to V

REF

with V

REF

up to VDD

Multiple reference types

Internal 4.096 V

External buffered (up to 4.096 V)

External (up to VDD)

Internal temperature sensor

Channel sequencer, selectable 1-pole filter, busy indicator

No pipeline delay, SAR architecture

Single-supply 5 V operation with

1.8 V to 5 V logic interface

Serial interface compatible with SPI, MICROWIRE,

QSPI, and DSP

Power dissipation

26 mW at 500 kSPS

5.2 μW at 100 SPS

Standby current: 50 nA

20-lead 4 mm × 4 mm LFCSP package

APPLICATIONS

Battery-powered equipment

Medical instruments: ECG/EKG

Mobile communications: GPS

Personal digital assistants

Power line monitoring

Data acquisition

Seismic data acquisition systems

Instrumentation

Process control

16-Bit, 8-Channel,

500 kSPS PulSAR ADC

AD7699

FUNCTIONAL BLOCK DIAGRAM

0.5V TO 4.096V

0.1µF

0.5V TO VDD

10µF

5V

REFIN REF VDD

BAND GAP

REF

TEMP

SENSOR

AD7699

VIO

1.8V

TO

VDD

IN0

IN1

IN2

IN3

IN4

IN5

IN6

IN7

COM

MUX

16-BIT SAR

ADC

ONE-POLE

LPF

SEQUENCER

SPI SERIAL

INTERFACE

CNV

SCK

SDO

DIN

GND

Figure 1.

Table 1. Multichannel 14-/16-Bit PulSAR® ADC

Type Channels 250 kSPS

500 kSPS ADC

14-Bit 8 AD7949 ADA4841-1

16-Bit 4

16-Bit 8

AD7682 ADA4841-1

GENERAL DESCRIPTION

The AD7699 is an 8-channel, 16-bit, charge redistribution successive approximation register (SAR) analog-to-digital converter (ADC) that operates from a single power supply, VDD.

The AD7699 contains all components for use in a multichannel, low power data acquisition system, including a true 16-bit SAR

ADC with no missing codes; an 8-channel low crosstalk multiplexer useful for configuring the inputs as single-ended (with or without ground sense), differential, or bipolar; an internal 4.096 V low drift reference and buffer; a temperature sensor; a selectable one-pole filter; and a sequencer that is useful when channels are continuously scanned in order.

The AD7699 uses a simple serial port interface (SPI) for writing to the configuration register and receiving conversion results.

The SPI interface uses a separate supply, VIO, which is set to the host logic level. Power dissipation scales with throughput.

The AD7699 is housed in a tiny 20-lead LFCSP with operation specified from −40°C to +85°C.

Rev. E Document Feedback

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarks and registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700 ©2008–2015 Analog Devices, Inc. All rights reserved.

Technical Support www.analog.com

AD7699

TABLE OF CONTENTS

Features .............................................................................................. 1

Applications ....................................................................................... 1

Functional Block Diagram .............................................................. 1

General Description ......................................................................... 1

Revision History ............................................................................... 2

Specifications ..................................................................................... 3

Timing Specifications ....................................................................... 5

Absolute Maximum Ratings ............................................................ 6

ESD Caution .................................................................................. 6

Pin Configuration and Function Descriptions ............................. 7

Typical Performance Characteristics ............................................. 8

Terminology .................................................................................... 12

Theory of Operation ...................................................................... 13

Overview ...................................................................................... 13

Converter Operation .................................................................. 13

Transfer Functions...................................................................... 14

Typical Connection Diagrams .................................................. 15

Analog Inputs .............................................................................. 16

Driver Amplifier Choice ............................................................ 18

REVISION HISTORY

9/15—Rev. D to Rev. E

Changed ADSP-BF53x to ADSP-BF531/ADSP-BF532/ADSP-

BF533/ADSP-BF535/ADSP-BF536/ADSP-BF537/ADSP-

BF538/ADSP-BF539; Changed ADSP-219x to ADSP-2191M/

ADSP-2196M, and Changed ADSP-218x to ADSP-2181/ADSP-

2183/ADSP-2185/ADSP-2186/ADSP-2189N ............ Throughout

Moved General Timing with a Busy Indicator Section and

Figure 36 .......................................................................................... 24

Added Channel Sequencer Section, Examples Section, and

Figure 41; Renumbered Sequentially ........................................... 27

5/15—Rev. C to Rev. D

Changed ADA4841-x to ADA4841-1, ADR43x to ADR430/

ADR431/ADR433/ADR434/ADR435, and AD44x to ADR440/

ADR441/ADR443/ADR444/ADR445 ........................ Throughout

Updated Outline Dimensions ....................................................... 27

Changes to Ordering Guide .......................................................... 27

5/14—Rev. B to Rev. C

Changes to Table 3 ............................................................................ 5

Changes to Ordering Guide .......................................................... 27

Data Sheet

Voltage Reference Output/Input .............................................. 18

Power Supply ............................................................................... 19

Supplying the ADC from the Reference .................................. 20

Digital Interface .............................................................................. 21

Reading/Writing During Conversion, Fast Hosts .................. 21

Reading/Writing During Acquisition, Any Speed Hosts ...... 21

Reading/Writing Spanning Conversion, Any Speed Host .... 21

Configuration Register, CFG .................................................... 21

General Timing Without a Busy Indicator ............................. 23

General Timing With a Busy Indicator ................................... 24

Read/Write Spanning Conversion Without a Busy

Indicator ...................................................................................... 25

Read/Write Spanning Conversion with a Busy Indicator ..... 26

Channel Sequencer .................................................................... 27

Application Hints ........................................................................... 28

Layout .......................................................................................... 28

Evaluating AD7699 Performance ............................................. 28

Outline Dimensions ....................................................................... 29

Ordering Guide .......................................................................... 29

3/12—Rev. A to Rev. B

Changes to Figure 28 ...................................................................... 15

Changes to Internal Reference/Temperature Sensor and

External Reference and Internal Buffer Sections ....................... 18

Changes to Bits[5:3] Function, Table 8 ........................................ 21

Updated Outline Dimensions ....................................................... 27

9/11—Rev. 0 to Rev. A

Changed Internal Reference/Temperature Sensor Section to

Internal Reference Section ............................................................ 18

Changes to Internal Reference Section, External Reference

Section and Internal Buffer Section, and External Reference

Section .............................................................................................. 18

Changes to Table 8 .......................................................................... 21

10/08—Revision 0: Initial Version

Rev. E | Page 2 of 29

Data Sheet

SPECIFICATIONS

VDD = 4.5 V to 5.5 V, V

REF

= 4.096 to VDD, VIO = 1.8 V to VDD, all specifications T

MIN

to T

MAX

, unless otherwise noted.

Table 2.

Parameter Test Conditions/Comments

RESOLUTION

ANALOG INPUT

Voltage Range

Absolute Input Voltage

Unipolar mode

Bipolar mode

Positive input, unipolar and bipolar modes

Negative or COM input, unipolar mode

Negative or COM input, bipolar mode f

IN

= 250 kHz

Acquisition phase

Analog Input CMRR

Leakage Current at 25°C Input

Impedance 1

THROUGHPUT

Conversion Rate

Full Bandwidth

¼ Bandwidth 2

2

Transient Response Full-scale step, full bandwidth

Full-scale step, ¼ bandwidth

ACCURACY

No Missing Codes

Integral Linearity Error

Differential Linearity Error

Transition Noise

Gain Error 4

Gain Error Match

Gain Error Temperature Drift

REF = VDD = 5 V

All modes

Offset Error 4

Offset Error Match

Offset Error Temperature Drift

All modes

Power Supply Sensitivity

VDD = 5 V ± 5%

AC Accuracy

Dynamic Range

Signal-to-Noise

SINAD f f f

IN

IN

IN f

IN

= 20 kHz, VREF = 5 V

= 20 kHz, VREF = 4.096 V internal REF

= 20 kHz, VREF = 5 V

= 20 kHz, VREF = 5 V, −60 dB input

Total Harmonic Distortion f f

IN

IN

= 20 kHz, VREF = 4.096 V internal REF

= 20 kHz

Spurious-Free Dynamic Range f

IN

= 20 kHz

Channel-to-Channel Crosstalk f

IN

= 100 kHz on adjacent channel(s)

SAMPLING DYNAMICS

−3 dB Input Bandwidth

Aperture Delay

Full bandwidth

¼ bandwidth

VDD = 5 V

93.3

92.5

91.5

91.5

33.5

90.5

−97

112

−125

14

3.6

2.5

±0.5 +1.5

±0.25 +1.5

0.5

±1

±1

±0.3

+10

+3

500

125

400

1600

±1

±1

±0.3

±1.5

+10

+3

89

92

89.5

90

16

−1.5

−1

−10

−3

0

0

−10

−3

AD7699

Min

16

Typ Max Unit

Bits

0

−V

REF

/2

+V

REF

+V

REF

/2

−0.1

−0.1

V

REF

+ 0.1

+0.1

V

V

V

REF

/2 − 0.1 V

REF

/2 V

REF

/2 + 0.1 V

68

1

V

V dB nA kSPS kSPS ns ns

Bits

LSB 3

LSB

LSB

LSB

LSB ppm/°C

LSB

LSB ppm/°C

LSB dB dB dB dB dB 5 dB dB dB dB

MHz

MHz ns

Rev. E | Page 3 of 29

AD7699 Data Sheet

Parameter

INTERNAL REFERENCE

REF Output Voltage

REFIN Output Voltage 6

REF Output Current

Temperature Drift

Line Regulation

Long-Term Drift

Turn-On Settling Time

EXTERNAL REFERENCE

Voltage Range

Current Drain

TEMPERATURE SENSOR

Output Voltage 7

Temperature Sensitivity

DIGITAL INPUTS

Logic Levels

V

IL

V

IH

I

IL

I

IH

DIGITAL OUTPUTS

Data Format 8

Pipeline Delay 9

V

OL

V

OH

POWER SUPPLIES

VDD

VIO

Standby Current 10, 11

Power Dissipation

Energy per Conversion

Test Conditions/Comments

At 25°C

At 25°C

VDD = 5 V ± 5%

1000 hours

CREF = 10 µF

REF input

REFIN input (buffered)

500 kSPS, REF = 5 V

At 25°C

I

SINK

= +500 µA

I

SOURCE

= −500 µA

Specified performance

Specified performance

VDD and VIO = 5 V, at 25°C

VDD = 5 V, 100 kSPS throughput

VDD = 5 V, 500 kSPS throughput

VDD = 5 V, 500 kSPS throughput with internal reference

4.5

1.8

VIO − 0.3

−0.3

0.7 × VIO

−1

−1

0.5

0.5

Min

4.086

TEMPERATURE RANGE 12

Specified Performance T

MIN

to T

MAX

−40 +85 °C

1

2

See the Analog Inputs section.

3

4

The bandwidth is set with the configuration register.

LSB means least significant bit. With the 5 V input range, one LSB = 76.3 µV.

5

6

See the Terminology section. These specifications include full temperature range variation but not the error contribution from the reference.

All specifications expressed in decibels are referred to a full-scale input FSR and tested with an input signal at 0.5 dB below full scale, unless otherwise specified.

7

8

This is the output from the internal band gap.

The output voltage is internal and present on a dedicated multiplexer input.

Unipolar mode: serial 16-bit straight binary.

Bipolar mode: serial 16-bit twos complement.

9

Conversion results available immediately after completed conversion.

10 With all digital inputs forced to VIO or GND as required.

11 During acquisition phase.

12 Contact an Analog Devices, Inc., sales representative for the extended temperature range.

5.2

26

28

52

50

283

1

Typ Max

4.096 4.106

2.3

±300

±10

±15

50

5

100

VDD + 0.3 V

VDD − 0.2 V

µA

Unit

V

V

µA ppm/°C ppm/V ppm ms

+0.3 × VIO V

VIO + 0.3

+1

+1

0.4

29

32 mV mV/°C

V

µA

µA

V

V

5.5 V

VDD + 0.3 V nA

µW mW mW nJ

Rev. E | Page 4 of 29

Data Sheet

TIMING SPECIFICATIONS

VDD = 4.5 V to 5.5 V, V

REF

= 4.096 to VDD, VIO = 1.8 V to VDD, all specifications T

MIN

to T

MAX

, unless otherwise noted.

Table 3.

Parameter

1

Conversion Time: CNV Rising Edge to Data Available

Acquisition Time

Time Between Conversions

CNV Pulse Width

Data Write/Read During Conversion

SCK Period

SCK Low Time

SCK High Time

SCK Falling Edge to Data Remains Valid

SCK Falling Edge to Data Valid Delay

VIO Above 4.5 V

VIO Above 3 V

VIO Above 2.7 V

VIO Above 2.3 V

VIO Above 1.8 V

CNV Low to SDO D15 MSB Valid

VIO Above 4.5 V

VIO Above 3 V

VIO Above 2.7 V

VIO Above 2.3 V

VIO Above 1.8 V

CNV High or Last SCK Falling Edge to SDO High Impedance

CNV Low to SCK Rising Edge

DIN Valid Setup Time from SCK Rising Edge

DIN Valid Hold Time from SCK Rising Edge

1

See Figure 2 and Figure 3 for load conditions.

t

DIS t

EN t

CLSCK t

SDIN t

HDIN t

SCKH t

HSDO t

DSDO

Symbol

t

CONV t

ACQ t

CYC t

CNVH t

DATA t

SCK t

SCKL

11

4

10

5

5

Min

400

2

10 t

DSDO

+ 2

11

Typ

18

22

25

32

28

15

17

16

17

18

21

1.2

Max

1.6

I

OL

500µA

AD7699

ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns

µs ns ns ns ns

Unit

µs ns

µs

TO SDO

C

L

50pF

1.4V

500µA I

OH

Figure 2. Load Circuit for Digital Interface Timing

70% VIO

30% VIO t

DELAY

2V OR VIO – 0.5V

1

0.8V OR 0.5V

2 t

DELAY

2V OR VIO – 0.5V

1

0.8V OR 0.5V

2

1

2V IF VIO ABOVE 2.5V, VIO – 0.5V IF VIO BELOW 2.5V.

2

0.8V IF VIO ABOVE 2.5V, 0.5V IF VIO BELOW 2.5V.

Figure 3. Voltage Levels for Timing

Rev. E | Page 5 of 29

AD7699

ABSOLUTE MAXIMUM RATINGS

Table 4.

Parameter

Analog Inputs

INx, 1

COM 1

REF, REFIN

Supply Voltages

VDD, VIO to GND

VDD to VIO

DIN, CNV, SCK to GND

SDO to GND

Storage Temperature Range

Junction Temperature

θ

JA

Thermal Impedance (LFCSP)

θ

JC

Thermal Impedance (LFCSP)

1

See the Analog Inputs section.

Rating

GND − 0.3 V to VDD + 0.3 V or VDD ± 130 mA

GND − 0.3 V to VDD + 0.3 V

−0.3 V to +7 V

±7 V

−0.3 V to VIO + 0.3 V

−0.3 V to VIO + 0.3 V

−65°C to +150°C

150°C

47.6°C/W

4.4°C/W

Data Sheet

Stresses at or above those listed under Absolute Maximum

Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability.

ESD CAUTION

Rev. E | Page 6 of 29

Data Sheet

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

VDD

REF

REFIN

GND

GND

4

5

1

2

3

AD7699

TOP VIEW

(Not to Scale)

15 VIO

14

13

SDO

SCK

12

11

DIN

CNV

AD7699

NOTES

1. THE EXPOSED PAD IS NOT CONNECTED

INTERNALLY. FOR INCREASED

RELIABILITY OF THE SOLDER JOINTS, IT

IS RECOMMENDED THAT THE PAD BE

SOLDERED TO THE SYSTEM

GROUND PLANE.

Figure 4. Pin Configuration

Table 5. Pin Function Descriptions

Pin No. Mnemonic Type 1 Description

1, 20

2

3

4, 5

6 to 9

10

11

12

13

14

15

16 to 19

VDD

REF

REFIN

GND P

IN4 to IN7 AI

COM AI

CNV

DIN

P Power Supply. Nominally 4.5 to 5.5 V and should be decoupled with 10 μF and 100 nF capacitors.

AI/O

Reference Input/Output. See the Voltage Reference Output/Input section.

When the internal reference is enabled, this pin produces 4.096 V. When the internal reference is disabled and the buffer is enabled, REF produces a buffered version of the voltage present on the REFIN pin

(VDD – 0.5 V maximum) useful when using low cost, low power references.

For improved drift performance, connect a precision reference to REF (0.5 V to VDD).

For any reference method, this pin needs decoupling with an external 10 μF capacitor connected as

close to REF as possible. See the Reference Decoupling section.

AI/O

Internal Reference Output/Reference Buffer Input. See the Voltage Reference Output/Input section.

When using the internal reference, the internal unbuffered reference voltage is present and needs decoupling with a 0.1 μF capacitor.

When using the internal reference buffer, apply a source between 0.5 V and 4.096 V that is buffered to the REF pin as previously described.

DI

DI

Power Supply Ground.

Analog Input Channel 4, Analog Input Channel 5, Analog Input Channel 6, and Analog Input Channel 7.

Common Channel Input. All input channels, IN[7:0], can be referenced to a common-mode point of 0 V or V

REF

/2 V.

Conversion Input. On the rising edge, CNV initiates the conversion. During conversion, if CNV is held high, the busy indictor is enabled.

Data Input. This input is used for writing to the 14-bit configuration register. The configuration register can be written to during and after conversion.

SCK

SDO

VIO

IN0 to IN3

DI

DO

P

AI

Serial Data Clock Input. This input is used to clock out the data on SDO and clock in data on DIN in an

MSB first fashion.

Serial Data Output. The conversion result is output on this pin and synchronized to SCK. In unipolar modes, conversion results are straight binary; in bipolar modes, conversion results are twos complement.

Input/Output Interface Digital Power. Nominally at the same supply as the host interface (1.8 V, 2.5 V,

3 V, or 5 V).

Analog Input Channel 0, Analog Input Channel 1, Analog Input Channel 2, and Analog Input Channel 3.

21 (EPAD) Exposed

Paddle

(EPAD)

The exposed paddle is not connected internally. For increased reliability of the solder joints, it is recommended that the pad be soldered to the GND plane.

1

AI = analog input, AI/O = analog input/output, DI = digital input, DO = digital output, and P = power.

Rev. E | Page 7 of 29

AD7699

TYPICAL PERFORMANCE CHARACTERISTICS

VDD = 5 V, VREF = 5 V, VIO = VDD, unless otherwise noted.

1.5

1.0

0.5

0

–0.5

–1.0

–1.5

0

250,000

16,384 32,768

CODES

49,152

Figure 5. Integral Nonlinearity vs. Code

220,840

65,536

σ = 0.51 LSB

V

REF

= 5V

200,000

150,000

100,000

50,000

0

26,926

13,341

0 0 3 10 0 0

7FF9 7FFA 7FFB 7FFC 7FFD 7FFE 7FFF 8000 8001

CODE IN HEX

Figure 6. Histogram of a DC Input at Code Center

0

–20

–40

–60

–80

V

REF f

S

= 5V

= 500kSPS f

IN

= 19.94kHz

SNR = 92.3dB

SINAD = 91.5dB

THD = –98dB

SFDR = 100dB

SECOND HARMONIC = –111dB

THIRD HARMONIC = –101dB

–100

–120

–140

–160

–180

0 25 50 75 100 125 150 175 200 225 250

FREQUENCY (kHz)

Figure 7. 20 kHz FFT, VREF = 5 V

Data Sheet

0.5

0

–0.5

1.5

1.0

–1.0

0

250,000

200,000

16,384 32,768

CODES

49,152

Figure 8. Differential Nonlinearity vs. Code

65,536

σ = 0.78 LSB

V

REF

= 4.096V

191,013

150,000

100,000

50,000

38,420

31,411

0

–20

–40

–60

–80

–100

–120

–140

–160

–180

0

0

0 0 119 157 0 0

7FF9 7FFA 7FFB 7FFC 7FFD 7FFE 7FFF 8000 8001

CODE IN HEX

Figure 9. Histogram of a DC Input at Code Center

V

REF f

S

= 4.096V

= 500kSPS f

IN

= 19.94kHz

SNR = 91.1dB

SINAD = 90.4dB

THD = –98dB

SFDR = 100dB

SECOND HARMONIC = –104dB

THIRD HARMONIC = –101dB

25 50 75 100 125 150 175 200 225 250

FREQUENCY (kHz)

Figure 10. 20 kHz FFT, VREF = 4.096 V

Rev. E | Page 8 of 29

Data Sheet

100

V

REF

= 5V

95

–10dB

90

85

80

75

70

–0.5dB

65

60

0 50 100 150 200 250 300 350 400 450 500

FREQUENCY (kHz)

Figure 11. SNR vs. Frequency

–85

–90

–95

–100

–105

–110

–115

–120

0

–60

–65

V

REF

= 5V

–70

–75

–80

50

–0.5dB

–10dB

100 150 200 250 300 350 400 450 500

FREQUENCY (kHz)

Figure 12. THD vs. Frequency

96 f

IN

= 20kHz

SNR, V

REF

= 5V

94

SINAD, V

REF

= 5V

92

90

SINAD, V

REF

= 4.096V

SNR, V

REF

= 4.096V

88

86

–55 –35 –15 5 25 45 65

TEMPERATURE (°C)

85

Figure 13. SNR, SINAD vs. Temperature

105 125

AD7699

14

13

12

11

75

70

65

100

V

REF

= 5V

95

90

85

80

–10dB

–0.5dB

60

0 50 100 150 200 250 300 350 400 450 500

FREQUENCY (kHz)

Figure 14. SINAD vs. Frequency

16

V

REF

= 5V

15

–10dB

–0.5dB

10

0

–80

50 100 150 200 250 300 350 400 450 500

FREQUENCY (kHz)

Figure 15. ENOB vs. Frequency

115 f

IN

= 20kHz SFDR, V

REF

= 5V

–85

SFDR,

V

REF

= 4.096V

110

105 –90

–95

THD, V

REF

= 5V THD, V

REF

= 4.096V

100

–100

–55 –35 –15 5 25 45 65

TEMPERATURE (°C)

85

Figure 16. THD, SFDR vs. Temperature

105

95

125

Rev. E | Page 9 of 29

AD7699

94

92 f

IN

= 20kHz

90

88

SNR

SINAD

ENOB

86

4.0

4.5

5.0

REFERENCE VOLTAGE (V)

Figure 17. SNR, SINAD, ENOB vs. Reference Voltage

5.5

13

95

94 f

IN

= 20kHz

V

REF

= 5V

93

89

88

87

92

91

90

86

85

–10

SNR

SINAD

ENOB

–8 –6 –4

INPUT LEVEL (dB)

–2

Figure 18. SNR, SINAD, and ENOB vs. Input Level

0

14.6

15.6

15.5

15.4

15.3

15.2

15.1

15.0

14.9

14.8

14.7

3

2

1

BIPOLAR GAIN

0

UNIPOLAR OFFSET

–1

BIPOLAR OFFSET

–2

UNIPOLAR GAIN

–3

–55 –35 –15 5 25 45 65 85 105 125

TEMPERATURE (°C)

Figure 19. Offset and Gain Errors vs. Temperature, Not Normalized

15

14

17

16

Data Sheet

–80

–85

–90

–95

–100

SFDR

THD

–105

–110

4.0

85

4.5

5.0

REFERENCE VOLTAGE (V)

Figure 20. THD, SFDR vs. Reference Voltage

5.5

80

5500 f s

= 500kSPS

V

DD

, INT REF

180

160

4750

4500

4250

4000

3750

4.5

5250

5000

140

120

100

80

V

DD

, EXT REF

4750

VIO

60

40

4500

–55 –35 –15 5 25 45 65

TEMPERATURE (°C)

85 105

Figure 21. Operating Currents vs. Temperature

5750 f

S

= 500kSPS

5500

4.096V INTERNAL REF

INTERNAL BUFFER, TEMP ON

5250

INTERNAL BUFFER, TEMP OFF

5000

20

125

100

90

80

70

60

50

EXTERNAL REF, TEMP ON

40

EXTERNAL REF, TEMP OFF

30

VIO

5.0

VDD SUPPLY (V)

Figure 22. Operating Currents vs. Supply

20

5.5

95

90

110

105

100

Rev. E | Page 10 of 29

Data Sheet

4.099

4.098

4.097

4.096

4.095

4.094

4.093

4.092

–55 –35 –15 5 25 45 65

TEMPERATURE (°C)

85 105 125

Figure 23. Internal Reference Output Voltage vs. Temperature, Three devices

AD7699

15

10

25

20

5

VDD = 5V, 85°C

VDD = 5V, 25°C

0

0 20 40 60 80

SDO CAPACITIVE LOAD (pF)

100 120

Figure 24. t

DSDO

Delay vs. SDO Capacitance Load and Supply

Rev. E | Page 11 of 29

AD7699

TERMINOLOGY

Least Significant Bit (LSB)

The LSB is the smallest increment that can be represented by a converter. For an analog-to-digital converter with N bits of resolution, the LSB expressed in volts is

LSB

(V) =

V

2

REF

N

Integral Nonlinearity Error (INL)

INL refers to the deviation of each individual code from a line drawn from negative full scale through positive full scale. The point used as negative full scale occurs ½ LSB before the first code transition. Positive full scale is defined as a level 1½ LSB beyond the last code transition. The deviation is measured from

the middle of each code to the true straight line (see Figure 26).

Differential Nonlinearity Error (DNL)

In an ideal ADC, code transitions are 1 LSB apart. DNL is the maximum deviation from this ideal value. It is often specified in terms of resolution for which no missing codes are guaranteed.

Offset Error

For unipolar mode, the first transition should occur at a level

½ LSB above analog ground. The unipolar offset error is the deviation of the actual transition from that point. For bipolar mode, the first transition should occur at a level ½ LSB above

V

REF

/2. The bipolar offset error is the deviation of the actual transition from that point.

Gain Error

The last transition (from 111 … 10 to 111 … 11) should occur for an analog voltage 1½ LSB below the nominal full scale. The gain error is the deviation in LSB (or percentage of full-scale range) of the actual level of the last transition from the ideal level after the offset error is adjusted out. Closely related is the full-scale error (also in LSB or percentage of full-scale range), which includes the effects of the offset error.

Aperture Delay

Aperture delay is the measure of the acquisition performance. It is the time between the rising edge of the CNV input and the point at which the input signal is held for a conversion.

Transient Response

Transient response is the time required for the ADC to accurately acquire its input after a full-scale step function is applied.

Dynamic Range

Dynamic range is the ratio of the rms value of the full scale to the total rms noise measured with the inputs shorted together.

The value for dynamic range is expressed in decibels.

Data Sheet

Signal-to-Noise Ratio (SNR)

SNR is the ratio of the rms value of the actual input signal to the rms sum of all other spectral components below the Nyquist frequency, excluding harmonics and dc. The value for SNR is expressed in decibels.

Signal-to-(Noise + Distortion) Ratio (SINAD)

SINAD is the ratio of the rms value of the actual input signal to the rms sum of all other spectral components below the Nyquist frequency, including harmonics but excluding dc. The value for

SINAD is expressed in decibels.

Total Harmonic Distortion (THD)

THD is the ratio of the rms sum of the first five harmonic components to the rms value of a full-scale input signal and is expressed in decibels.

Spurious-Free Dynamic Range (SFDR)

SFDR is the difference, in decibels, between the rms amplitude of the input signal and the peak spurious signal.

Effective Number of Bits (ENOB)

ENOB is a measurement of the resolution with a sine wave input. It is related to SINAD by the formula

ENOB = (SINAD dB

− 1.76)/6.02 and is expressed in bits.

Channel-to-Channel Crosstalk

Channel-to-channel crosstalk is a measure of the level of crosstalk between any two adjacent channels. It is measured by applying a dc to the channel under test and applying a full-scale, 100 kHz sine wave signal to the adjacent channel(s). The crosstalk is the amount of signal that leaks into the test channel and is expressed in decibels.

Reference Voltage Temperature Coefficient

Reference voltage temperature coefficient is derived from the typical shift of output voltage at 25°C on a sample of parts at the maximum and minimum reference output voltage (V

REF

) measured at T

MIN

, T (25°C), and T

MAX

. It is expressed in ppm/°C as

TCV

REF

( ppm/

°

C )

=

V

V

REF

REF

(

Max

( 25

°

C )

)

×

V

REF

(

T

MAX

(

Min

)

T

MIN

)

×

10

6 where:

V

REF

(Max) = maximum V

REF

at T

MIN

, T (25°C), or T

MAX

.

V

REF

(Min) = minimum V

REF

at T

MIN

, T (25°C), or T

MAX

.

V

REF

(25°C) = V

REF

at 25°C.

T

MAX

= +85°C.

T

MIN

= –40°C.

Rev. E | Page 12 of 29

Data Sheet

THEORY OF OPERATION

INx+

AD7699

REF

GND

32,768C

MSB

16,384C

32,768C 16,384C

MSB

4C 2C

4C 2C

C

C

C

C

LSB SW+

SWITCHES CONTROL

COMP

CONTROL

LOGIC

BUSY

OUTPUT CODE

LSB SW–

CNV

INx– OR

COM

Figure 25. ADC Simplified Schematic

OVERVIEW

The AD7699 is an 8-channel, 16-bit, charge redistribution successive approximation register (SAR) analog-to-digital converter (ADC). It is capable of converting 500,000 samples per second (500 kSPS) and power down between conversions.

For example, when operating with an external reference at

1 kSPS, it consumes 52 µW typically, ideal for battery-powered applications.

The AD7699 contains all of the components for use in a multichannel, low power data acquisition system, including

• 16-bit SAR ADC with no missing codes

• 8-channel, low crosstalk multiplexer

• Internal low drift reference and buffer

• Temperature sensor

• Selectable one-pole filter

• Channel sequencer

These components are configured through an SPI-compatible,

14-bit register. Conversion results, also SPI compatible, can be read after or during conversions with the option for reading back the configuration.

The AD7699 provides the user with an on-chip track-and-hold and does not exhibit pipeline delay or latency.

The AD7699 is specified from 4.5 V to 5.5 V and can be interfaced to any 1.8 V to 5 V digital logic family. It is housed in a 20-lead,

4 mm × 4 mm LFCSP that combines space savings and allows flexible configurations and is also pin-for-pin compatible with the 16-bit AD7682 and AD7689, and the 14-bit AD7949 .

CONVERTER OPERATION

The AD7699 is a successive approximation ADC based on a

charge redistribution DAC. Figure 25 shows the simplified

schematic of the ADC. The capacitive DAC consists of two identical arrays of 16 binary-weighted capacitors, which are connected to the two comparator inputs.

During the acquisition phase, terminals of the array tied to the comparator input are connected to GND via SW+ and SW−. All independent switches are connected to the analog inputs.

Thus, the capacitor arrays are used as sampling capacitors and acquire the analog signal on the INx+ and INx− (or COM) inputs. When the acquisition phase is complete and the CNV input goes high, a conversion phase is initiated. When the conversion phase begins, SW+ and SW− are opened first. The two capacitor arrays are then disconnected from the inputs and connected to the GND input. Therefore, the differential voltage between the INx+ and INx− (or COM) inputs captured at the end of the acquisition phase is applied to the comparator inputs, causing the comparator to become unbalanced. By switching each element of the capacitor array between GND and REF, the comparator input varies by binary-weighted voltage steps

(V

REF

/2, V

REF

/4, ... V

REF

/32,768). The control logic toggles these switches, starting with the MSB, to bring the comparator back into a balanced condition. After the completion of this process, the part returns to the acquisition phase, and the control logic generates the ADC output code and a busy signal indicator.

Because the AD7699 has an on-board conversion clock, the serial clock, SCK, is not required for the conversion process.

Rev. E | Page 13 of 29

AD7699

TRANSFER FUNCTIONS

With the inputs configured for unipolar range (single ended,

COM with ground sense, or paired differentially with INx− as ground sense), the data output is straight binary.

With the inputs configured for bipolar range (COM = V

REF

/2 or paired differentially with INx− = V

REF

/2), the data outputs are twos complement.

The ideal transfer characteristic for the AD7699 is shown in

Figure 26 and for both unipolar and bipolar ranges with the

internal 4.096 V reference.

TWOS

COMPLEMENT

STRAIGHT

BINARY

011...111

011...110

011...101

111...111

111...110

111...101

Data Sheet

100...010

100...001

100...000

000...010

000...001

000...000

–FSR

–FSR + 1LSB

–FSR + 0.5LSB

+FSR – 1LSB

+FSR – 1.5LSB

ANALOG INPUT

Figure 26. ADC Ideal Transfer Function

Table 6. Output Codes and Ideal Input Voltages

Description

Unipolar Analog Input

1

V

REF

= 4.096 V

FSR − 1 LSB 4.095938 V

Digital Output Code

(Straight Binary Hex)

Bipolar Analog Input

V

REF

= 4.096 V

2

Digital Output Code

(Twos Complement Hex)

0xFFFF

3

2.047938

3

Midscale + 1 LSB 2.048063 V

Midscale 2.048 V

Midscale − 1 LSB 2.047938 V

0x8001

0x8000

0x7FFF

62.5 μV

0 V

−62.5 μV

0x0001

0x0000

0xFFFF 4

−FSR + 1 LSB 62.5 μV 0x0001 −2.047938 V 0x8001

0x0000

3

−2.048 0x8000

1 With COM or INx− = 0 V or all INx referenced to GND.

2

With COM or INx− = V

REF

/2.

3

This is also the code for an overranged analog input ((INx+) − (INx−), or COM, above V

REF

− V

GND

).

4 This is also the code for an underranged analog input ((INx+) − (INx−), or COM, below V

GND

).

Rev. E | Page 14 of 29

Data Sheet

TYPICAL CONNECTION DIAGRAMS

5V 1.8V TO VDD

100nF

100nF

10µF

2

100nF

V+

0V TO V

REF

ADA4841-x

3

V–

V+

IN0

REF REFIN VDD VIO

IN[7:1]

AD7699

DIN

SCK

SDO

CNV

MOSI

SCK

MISO

SS

0V TO V

REF

ADA4841-x

3

V–

0V OR

V

REF

/2

COM

GND

NOTES

1. INTERNAL REFERENCE SHOWN. SEE THE VOLTAGE REFERENCE OUTPUT/INPUT SECTION FOR

REFERENCE SELECTION.

2. C

REF

IS USUALLY A 10µF CERAMIC CAPACITOR (X5R).

3. SEE THE DRIVER AMPLIFIER CHOICE SECTION FOR ADDITIONAL RECOMMENDED AMPLIFIERS.

4. SEE THE DIGITAL INTERFACE SECTION FOR CONFIGURING AND READING CONVERSION DATA.

Figure 27. Typical Application Diagram with Multiple Supplies

10µF

2

100nF

V+

V+

ADA4841-x

3

REF REFIN VDD

IN0

IN[7:1]

AD7699

ADA4841-x

3

5V 1.8V TO VDD

100nF

100nF

VIO

DIN

SCK

SDO

CNV

MOSI

SCK

MISO

SS

V

REF

p-p

V

REF

/2

COM

GND

NOTES

1. INTERNAL REFERENCE SHOWN. SEE THE VOLTAGE REFERENCE OUTPUT/INPUT SECTION FOR

REFERENCE SELECTION.

2. C

REF

IS USUALLY A 10µF CERAMIC CAPACITOR (X5R).

3. SEE THE DRIVER AMPLIFIER CHOICE SECTION FOR ADDITIONAL RECOMMENDED AMPLIFIERS.

4. SEE THE DIGITAL INTERFACE SECTION FOR CONFIGURING AND READING CONVERSION DATA.

Figure 28. Typical Application Diagram Using Bipolar Input

AD7699

Rev. E | Page 15 of 29

AD7699

Unipolar or Bipolar

Figure 27 shows an example of the recommended connection

diagram for the AD7699 when multiple supplies are available.

Bipolar Single Supply

Figure 28 shows an example of a system with a bipolar input

using single supplies with the internal reference (optional different VIO supply). This circuit is also useful when the amplifier/signal conditioning circuit is remotely located with some common mode present. Note that for any input configuration, the inputs, INx, are unipolar and always referenced to

GND (no negative voltages even in bipolar range).

For this circuit, a rail-to-rail input/output amplifier can be used; however, the offset voltage vs. input common-mode range should be noted and taken into consideration (1 LSB = 62.5 μV with

V

REF

= 4.096 V). Note that the conversion results are in twos complement format when using the bipolar input configuration.

Refer to the AN-581 Application Note, Biasing and Decoupling

Op Amps in Single Supply Applications

, at www.analog.com

for additional details about using single-supply amplifiers.

ANALOG INPUTS

Input Structure

Figure 29 shows an equivalent circuit of the input structure of

the AD7699 . The two diodes, D1 and D2, provide ESD protection for the analog inputs, IN[7:0] and COM. Care must be taken to ensure that the analog input signal does not exceed the supply rails by more than 0.3 V because this causes the diodes to become forward-biased and to start conducting current.

These diodes can handle a forward-biased current of 130 mA maximum. For instance, these conditions may eventually occur when the input buffer supplies are different from VDD. In such a case, for example, an input buffer with a short circuit, the current limitation can be used to protect the part.

VDD

INx+

OR INx–

OR COM

D1

R

IN

C

IN

C

PIN

D2

GND

Figure 29. Equivalent Analog Input Circuit

This analog input structure allows the sampling of the true differential signal between INx+ and COM or INx+ and INx−.

(COM or INx− = GND ± 0.1 V or V

REF

± 0.1 V). By using these differential inputs, signals common to both inputs are rejected,

as shown in Figure 30.

Data Sheet

70

65

60

55

50

45

40

35

30

1

10

100

FREQUENCY (kHz)

1k 10k

Figure 30. Analog Input CMRR vs. Frequency

During the acquisition phase, the impedance of the analog inputs can be modeled as a parallel combination of the capacitor, C

PIN

, and the network formed by the series connection of R

IN

and C

IN

.

C

PIN

is primarily the pin capacitance. R

IN

is typically 400 Ω (8.8 kΩ when the one-pole filter is active) and is a lumped component made up of serial resistors and the on resistance of the switches.

C

IN

is typically 27 pF and is mainly the ADC sampling capacitor.

Selectable Low-Pass Filter

During the conversion phase, where the switches are opened, the input impedance is limited to C

PIN

. While the AD7699 is acquiring, R

IN

and C

IN

make a one-pole, low-pass filter that reduces undesirable aliasing effects and limits the noise from the driving circuitry. The low-pass filter can be programmed for the full bandwidth or ¼ of the bandwidth with CFG[6], as

shown in Table 8. Note that the converter throughput must also be

reduced by ¼ when using the filter. If the maximum throughput is used with the BW set to ¼, the acquisition time of the converter, t

ACQ

, is violated, resulting in poor THD.

Input Configurations

Figure 31 shows the different methods for configuring the analog

inputs with the configuration register (CFG[12:10]). Refer to

the Configuration Register, CFG section for more details.

Rev. E | Page 16 of 29

Data Sheet

CH0+

CH1+

CH2+

CH3+

CH4+

CH5+

CH6+

CH7+

IN0

IN1

IN2

IN3

IN4

IN5

IN6

IN7

COM

GND

A—8 CHANNELS,

SINGLE ENDED

CH0+

CH1+

CH2+

CH3+

CH4+

CH5+

CH6+

CH7+

COM–

IN0

IN1

IN2

IN3

IN4

IN5

IN6

IN7

COM

GND

B—8 CHANNELS,

COMMON REFERENCE

CH0+ (–)

CH0– (+)

CH1+ (–)

CH1– (+)

CH2+ (–)

CH2– (+)

CH3+ (–)

CH3– (+)

IN0

IN1

IN2

IN3

IN4

IN5

IN6

IN7

COM

GND

CH0+ (–)

CH0– (+)

CH1+ (–)

CH1– (+)

CH2+

CH3+

CH4+

CH5+

COM–

IN0

IN1

IN2

IN3

IN4

IN5

IN6

IN7

COM

GND

C—4 CHANNELS,

DIFFERENTIAL

D—COMBINATION

Figure 31. Multiplexed Analog Input Configurations

The analog inputs can be configured as

• Figure 31A, single-ended referenced to system ground;

CFG[12:10] = 111

2

.

• Figure 31B, bipolar differential with a common reference

point; COM = V

REF

/2; CFG[12:10] = 010

2

.

Unipolar differential with COM connected to a ground sense; CFG[12:10] = 110

2

.

• Figure 31C, bipolar differential pairs with INx− referenced

to V

REF

/2; CFG[12:10] = 00X

2

.

Unipolar differential pairs with INx− referenced to a ground sense; CFG[12:10] = 10X

2

.

In this configuration, the INx+ is identified by the channel in CFG[9:7]. For example, for IN0 = IN1+ and IN1 =

IN1−, CFG[9:7] = 000

2

; for IN1 = IN1+ and IN0 = IN1−,

CFG[9:7] = 001

2

.

• Figure 31D, inputs configured in any of the above

combinations (showing that the AD7699 can be configured dynamically).

AD7699

Sequencer

The AD7699 includes a channel sequencer useful for scanning channels in a IN0 to IN[7:0] fashion. Channels are scanned as singles or pairs, with or without the temperature sensor, after the last channel is sequenced.

The sequencer starts with IN0 and finishes with IN[7:0] set in

CFG[9:7]. For paired channels, the channels are paired depending on the last channel set in CFG[9:7]. Note that the channel pairs are always paired as IN (even) = INx+ and IN

(odd) = INx− regardless of CFG[7].

To enable the sequencer, CFG[2:1] are written to for initializing the sequencer. After CFG[13:0] are updated, DIN must be held low while reading data out (at least for Bit 13), or the CFG register begins updating again.

While operating in a sequence, the CFG register can be changed by writing 01

2

to CFG[2:1]. However, if changing CFG11 (paired or single channel) or CFG[9:7] (last channel in sequence), the sequence reinitializes and converts IN0 (or IN1) after CFG is updated.

Examples

Bit[13], Bits[6:3], and Bit 0 are configured for the input and sequencer.

As a first example, scan all IN[7:0] referenced to COM = GND with the temperature sensor.

13 12 11 10 9 8 7 6

CFG INCC INx BW

1 1 0 1 1 1

5 4 3 2 1 0

REF SEQ RB

1 0

As a second example, scan three paired channels without the temperature sensor and referenced to V

REF

/2.

13 12 11 10 9 8 7 6

CFG INCC INx BW

0 0

1 X = don’t care.

X 1 1 0 X 1

Source Resistance

5 4 3 2 1 0

REF SEQ RB

1 1

When the source impedance of the driving circuit is low, the

AD7699 can be driven directly. Large source impedances significantly affect the ac performance, especially total harmonic distortion (THD). The dc performances are less sensitive to the input impedance. The maximum source impedance depends on the amount of THD that can be tolerated. The THD degrades as a function of the source impedance and the maximum input frequency.

Rev. E | Page 17 of 29

AD7699

DRIVER AMPLIFIER CHOICE

Although the AD7699 is easy to drive, the driver amplifier must meet the following requirements:

• The noise generated by the driver amplifier must be kept as low as possible to preserve the SNR and transition noise performance of the AD7699 . Note that the AD7699 has a noise much lower than most of the other 16-bit ADCs and, therefore, can be driven by a noisier amplifier to meet a given system noise specification. The noise from the amplifier is filtered by the AD7699 analog input circuit low-pass filter made by R

IN

and C

IN

or by an external filter, if one is used.

Because the typical noise of the AD7699 is 35 µV rms (with

V

REF

= 5 V), the SNR degradation due to the amplifier is

SNR

LOSS

=

20 log

35

2

+

π

2

35

f

3dB

(

Ne

N

)

2

 where:

f

−3dB

is the input bandwidth in megahertz of the AD7699

(14.7 MHz in full BW or 670 kHz in ¼ BW) or the cutoff frequency of an input filter, if one is used.

N is the noise gain of the amplifier (for example, 1 in buffer configuration).

e

N

is the equivalent input noise voltage of the op amp, in nV/√Hz.

• For ac applications, the driver should have a THD performance commensurate with the AD7699

. Figure 12 shows

THD vs. frequency for the AD7699 .

• For multichannel, multiplexed applications on each input or input pair, the driver amplifier and the AD7699 analog input circuit must settle a full-scale step onto the capacitor array at a 16-bit level (0.0015%). In amplifier data sheets, settling at 0.1% to 0.01% is more commonly specified. This may differ significantly from the settling time at a 16-bit level and should be verified prior to driver selection.

Table 7. Recommended Driver Amplifiers

Amplifier Typical Application

ADA4841-1

AD8655

AD8021

AD8022

OP184

Very low noise, small, and low power

5 V single supply, low noise

Very low noise and high frequency

Low noise and high frequency

Low power, low noise, and low frequency

AD8605 , AD8615 5 V single supply, low power

Data Sheet

VOLTAGE REFERENCE OUTPUT/INPUT

The AD7699 allows the choice of a very low temperature drift internal voltage reference, an external reference, or an external buffered reference.

The internal reference of the AD7699 provides excellent performance and can be used in almost all applications. There are five possible choices of voltage reference schemes briefly described

in Table 8 with more details in each of the following sections.

Internal Reference/Temperature Sensor

The internal reference can be set for a 4.096 V output as

detailed in Table 8. With the internal reference enabled, the

band gap voltage is also present on the REFIN pin, which requires an external 0.1 μF capacitor. Because the current output of REFIN is limited, it can be used as a source if followed by a suitable buffer, such as the AD8605 .

Enabling the reference also enables the internal temperature sensor, which measures the internal temperature of the AD7699 and is thus useful for performing a system calibration. For applications requiring the use of the temperature sensor, the internal reference must be active (internal buffer can be disabled in this case). Note that, when using the temperature sensor, the output is straight binary referenced from the

AD7699 GND pin.

The internal reference is temperature-compensated to within

15 mV. The reference is trimmed to provide a typical drift of

3 ppm/°C.

External Reference and Internal Buffer

For improved drift performance, an external reference can be used with the internal buffer. The external reference is connected to REFIN, and the output is produced on the REF pin. An external reference can be used with the internal buffer with or

without the temperature sensor enabled. Refer to Table 8 for

register details. With the buffer enabled, the gain is unity and is limited to an input/output of 4.096 V.

The internal reference buffer is useful in multiconverter applications because a buffer is typically required in these applications. In addition, a low power reference can be used because the internal buffer provides the necessary performance to drive the SAR architecture of the AD7699 .

External Reference

In any of the five voltage reference schemes, an external reference can be connected directly on the REF pin because the output impedance of REF is >5 kΩ. To reduce power consumption, the reference and buffer can be powered down independently or together for the lowest power consumption. When only using the external reference (and optional reference buffer as shown in

Figure 34), an internal buffer is disabled. Refer to Table 8 for

register details. For improved drift performance, an external reference such as the ADR430 / ADR431 / ADR433 / ADR434 /

ADR435 or ADR440 / ADR441 / ADR443 / ADR444 / ADR445 is recommended.

Rev. E | Page 18 of 29

Data Sheet

Reference Decoupling

Whether using an internal or external reference, the AD7699 voltage reference output/input, REF, has a dynamic input impedance and should therefore be driven by a low impedance source with efficient decoupling between the REF and GND pins. This decoupling depends on the choice of the voltage reference but usually consists of a low ESR capacitor connected to REF and GND with minimum parasitic inductance. A 10 µF

(X5R, 1206 size) ceramic chip capacitor is appropriate when using the internal reference, the ADR430 / ADR431 / ADR433 /

ADR434 / ADR435 or ADR440 / ADR441 / ADR443 / ADR444 /

ADR445 external reference, or a low impedance buffer such as the AD8031 or the AD8605 .

The placement of the reference decoupling capacitor is also important to the performance of the AD7699 , as explained in the

Layout section. Mount the decoupling capacitor on the same side as

the ADC at the REF pin with a thick PCB trace. The GND should also connect to the reference decoupling capacitor with the shortest distance and to the analog ground plane with several vias.

If desired, smaller reference decoupling capacitor values down to 2.2 µF can be used with a minimal impact on performance, especially on DNL.

Regardless, there is no need for an additional lower value ceramic decoupling capacitor (for example, 100 nF) between the REF and GND pins.

For applications that use multiple AD7699 s or other PulSAR devices, it is more effective to use the internal reference buffer to buffer the external reference voltage, thus reducing SAR conversion crosstalk.

The voltage reference temperature coefficient (TC) directly impacts full scale; therefore, in applications where full-scale accuracy matters, care must be taken with the TC. For instance, a ±15 ppm/°C TC of the reference changes full scale by ±1 LSB/°C.

POWER SUPPLY

The AD7699 uses two power supply pins: an analog and digital core supply (VDD) and a digital input/output interface supply

(VIO). VIO allows direct interface with any logic between 1.8 V and VDD. To reduce the supplies needed, the VIO and VDD pins can be tied together. The AD7699 is independent of power supply sequencing between VIO and VDD. The only restriction is that

CNV must be low when powering up the AD7699 . Additionally, it is very insensitive to power supply variations over a wide

frequency range, as shown in Figure 32.

Rev. E | Page 19 of 29

AD7699

55

50

45

40

35

75

70

65

60

30

1 10 100

FREQUENCY (kHz)

Figure 32. PSRR vs. Frequency

1k 10k

The AD7699 powers down automatically at the end of each conversion phase; therefore, the operating currents and power scale linearly with the sampling rate. This makes the part ideal for low sampling rates (even of a few hertz) and low batterypowered applications.

10,000

1000 VDD = 5V, INTERNAL REF

100

10

1

0.1

0.010

VDD = 5V, EXTERNAL REF

VIO

0.001

10 100 1k 10k

SAMPLING RATE (sps)

100k

Figure 33. Operating Currents vs. Sampling Rate

1M

AD7699

SUPPLYING THE ADC FROM THE REFERENCE

For simplified applications, the AD7699 , with its low operating current, can be supplied directly using the reference circuit, as

shown in Figure 34. The reference line can be driven by

 The system power supply directly

 A reference voltage with enough current output capability, such as the ADR430 / ADR431 / ADR433 / ADR434 / ADR435 or ADR440 / ADR441 / ADR443 / ADR444 / ADR445

 A reference buffer, such as the

AD8605 , which can also

filter the system power supply, as shown in Figure 34

Data Sheet

5V

5V

5V 10kΩ

1µF

AD8605

10µF

1

10Ω

1µF

0.1µF 0.1µF

REF VDD

AD7699

VIO

1

OPTIONAL REFERENCE BUFFER AND FILTER.

Figure 34. Example of an Application Circuit

Rev. E | Page 20 of 29

Data Sheet

DIGITAL INTERFACE

The AD7699 uses a simple 4-wire interface and is compatible with SPI, MICROWIRE™, QSPI™, digital hosts, and DSPs, for example, Blackfin® ADSP-BF531 / ADSP-BF532 / ADSP-

BF533 / ADSP-BF535 / ADSP-BF536 / ADSP-BF537 / ADSP-

BF538 / ADSP-BF539 , SHARC®, ADSP-2191M / ADSP-2196M , and ADSP-2181 / ADSP-2183 / ADSP-2185 / ADSP-2186 / ADSP-

2189N .

The interface uses the CNV, DIN, SCK, and SDO signals and allows CNV, which initiates the conversion, to be independent of the readback timing. This is useful in low jitter sampling or simultaneous sampling applications.

A 14-bit register, CFG[13:0], is used to configure the ADC for the channel to be converted, the reference selection, and other

components, which are detailed in the Configuration Register,

CFG section.

When CNV is low, reading/writing can occur during conversion, acquisition, and spanning conversion (acquisition plus conversion), as detailed in the following sections. The CFG word is updated on the first 14 SCK rising edges, and conversion results are output on the first 15 (or 16 if busy mode is selected) SCK falling edges. If the CFG readback is enabled, an additional

14 SCK falling edges are required to output the CFG word associated with the conversion results, with the CFG MSB following the LSB of the conversion result.

A discontinuous SCK is recommended because the part is selected with CNV low, and SCK activity begins to write a new configuration word and clock out data.

Note that in the following sections, the timing diagrams indicate digital activity (SCK, CNV, DIN, SDO) during the conversion.

However, due to the possibility of performance degradation, digital activity should occur only prior to the safe data reading/ writing time, t

DATA

, because the AD7699 provides error correction circuitry that can correct for an incorrect bit during this time.

From t

DATA

to t

CONV

, there is no error correction and conversion results may be corrupted. The user should configure the AD7699 and initiate the busy indicator (if desired) prior to t

DATA

. It is also possible to corrupt the sample by having SCK or DIN transitions near the sampling instant. Therefore, it is recommended to keep the digital pins quiet for approximately 30 ns before and 10 ns after the rising edge of CNV, using a discontinuous SCK whenever possible to avoid any potential performance degradation.

READING/WRITING DURING CONVERSION, FAST

HOSTS

When reading/writing during conversion (n), conversion results are for the previous (n − 1) conversion, and writing the

CFG is for the next (n + 1) acquisition and conversion.

After the CNV is brought high to initiate conversion, it must be brought low again to allow reading/writing during conversion.

Reading/writing should only occur up to t

DATA

and, because this time is limited, the host must use a fast SCK.

Rev. E | Page 21 of 29

AD7699

The SCK frequency required is calculated by

f

SCK

Number

_

SCK t

DATA

_

Edges

The time between t

DATA

and t

CONV

is a safe time when digital activity should not occur, or sensitive bit decisions may be corrupt.

READING/WRITING DURING ACQUISITION, ANY

SPEED HOSTS

When reading/writing after conversion, or during acquisition

(n), conversion results are for the previous (n − 1) conversion, and writing is for the (n + 1) acquisition.

For the maximum throughput, the only time restriction is that the reading/writing take place during the t

ACQ

(min) time. For slow throughputs, the time restriction is dictated by throughput required by the user, and the host is free to run at any speed.

Thus for slow hosts, data access must take place during the acquisition phase.

READING/WRITING SPANNING CONVERSION, ANY

SPEED HOST

When reading/writing spanning conversion, the data access starts at the current acquisition (n) and spans into the conversion (n).

Conversion results are for the previous (n − 1) conversion, and writing the CFG register is for the next (n + 1) acquisition and conversion.

Similar to reading/writing during conversion, reading/writing should only occur up to t

DATA

. For the maximum throughput, the only time restriction is that reading/writing take place during the t

ACQ

(min) + t

DATA

time.

For slow throughputs, the time restriction is dictated by the user’s required throughput, and the host is free to run at any speed. Similar to reading/writing during acquisition, for slow hosts, the data access must take place during the acquisition phase with additional time into the conversion.

Note that data access spanning conversion requires the CNV to be driven high to initiate a new conversion, and data access is not allowed when CNV is high. Thus, the host must perform two bursts of data access when using this method.

CONFIGURATION REGISTER, CFG

The AD7699 uses a 14-bit configuration register (CFG[13:0]) as

detailed in Table 8 for configuring the inputs, the channel to be

converted, one-pole filter bandwidth, the reference, and the channel sequencer. The CFG register is latched (MSB first) on

DIN with 14 SCK rising edges. CFG update is edge dependent, allowing for asynchronous or synchronous hosts.

AD7699

The register can be written to during conversion, during acquisition, or spanning acquisition/conversion and is updated at the end of conversion, t

CONV

(maximum). There is always a one deep delay when writing the CFG register. Note that at power-up, the

CFG register is undefined and two dummy conversions are required to update the register. To preload the CFG register with a factory setting, hold DIN high for two conversions. Thus

CFG[13:0] = 0x3FFF. This sets the AD7699 for the following:

Data Sheet

• IN[7:0] unipolar referenced to GND, sequenced in order

• Full bandwidth for a one-pole filter

• Internal reference/temperature sensor disabled, buffer enabled

• Enables the sequencer

• No readback of the CFG register

Table 8 summarizes the configuration register bit details. See

the Theory of Operation section for more details.

6

BW

5

REF

4

REF

3

REF

2

SEQ

1

SEQ

0

RB

13

CFG

12

INCC

11

INCC

10

INCC

9

INx

8

INx

7

INx

0

[2:1]

Table 8. Configuration Register Description

Bit(s) Name Description

[13] CFG

[12:10] INCC Input channel configuration. Selection of pseudobipolar, pseudodifferential, pairs, single-ended, or temperature sensor. Refer to

the Input Configurations section.

1 = Overwrite contents of register.

Bit 12

0

0

0

1

Bit 11

0

1

1

0

Bit 10

X

0

1

X

1

1

Function

Bipolar differential pairs; INx− referenced to V

Bipolar; INx referenced to COM = V

REF

/2 ± 0.1 V.

Temperature sensor.

REF

/2 ± 0.1 V.

Unipolar differential pairs; INx− referenced to GND ± 0.1 V.

[9:7] INx

Configuration update.

0 = Keep current configuration settings.

1

1

1

1

0

1

Input channel selection in binary fashion.

Bit 9

0

Bit 8

0

Bit 7

0

Channel

IN0

0

0

1

IN1

[6] BW

Unipolar, IN0 to IN7 referenced to COM = GND ± 0.1 V (GND sense).

Unipolar, IN0 to IN7 referenced to GND.

1 1 1 IN7

Select bandwidth for low-pass filter. Refer to the Selectable Low-Pass Filter section.

0 = ¼ of BW, uses an additional series resistor to further bandwidth limit the noise. Maximum throughput must also be reduced to ¼.

1 = Full BW.

[5:3] REF

SEQ

RB

Reference/buffer selection. Selection of internal, external, and external buffered references, and enabling of the on-chip

temperature sensor. Refer to the Voltage Reference Output/Input section.

1

1

0

0

Bit 5

0

0

Bit 4

0

0

1

1

1

1

Bit 3

0

1

0

1

0

1

Function

Not used

Internal reference, REF = 4.096 V output, temperature enabled

.

External reference, temperature enabled.

External reference, internal buffer, temperature enabled.

External reference, temperature disabled.

External reference, internal buffer, temperature disabled.

1

1

0

0

Channel sequencer. Allows for scanning channels in an IN0 to IN[7:0] fashion. Refer to the Sequencer section.

Bit 2 Bit 1 Function

0

1

Disable sequencer.

Update configuration during sequence.

0

1

Scan IN0 to IN[7:0] (set in CFG[9:7]), then temperature.

Scan IN0 to IN[7:0] (set in CFG[9:7]).

Read back the CFG register.

0 = Read back current configuration at end of data.

1 = Do not read back contents of configuration.

1 X = don’t care.

Rev. E | Page 22 of 29

Data Sheet AD7699

GENERAL TIMING WITHOUT A BUSY INDICATOR

Figure 35 details the timing for all three modes: reading/writing

during conversion, after conversion, and spanning conversion.

Note that the gating item for both CFG and data readback is at the end of conversion (EOC). At the end of conversions (EOC), if CNV is high, the busy indicator is disabled.

As detailed previously, the data access should occur up to safe data reading/writing time, t

DATA

. If the full CFG word was not written to prior to EOC, it is discarded and the current configuration remains. If the conversion result is not read out fully prior to EOC, it is lost as the ADC updates SDO with the

START OF CONVERSION t

CYC

POWER

UP t

CONV t

DATA

END OF CONVERSION (EOC)

MSB of the current conversion. For detailed timing, refer to

Figure 37 and Figure 38, which depict reading/writing spanning

conversion with all timing details, including setup, hold, and SCK.

When CNV is brought low after EOC, SDO is driven from high impedance to the MSB. Falling SCK edges clock out bits starting with MSB − 1.

The SCK can idle high or low depending on the clock polarity

(CPOL) and clock phase (CPHA) settings if SPI is used. A simple

solution is to use CPOL = CPHA = 0 as shown in Figure 35 with

SCK idling low.

EOC EOC

PHASE CONVERSION (n – 2)

ACQUISITION

(n – 1)

CONVERSION (n – 1)

ACQUISITION

(n)

CONVERSION (n)

ACQUISITION

(n + 1)

CONVERSION (n + 1)

ACQUISITION

(n + 2)

CNV

DIN

SDO

SCK

XXX

1

XXX

16/30

MSB

(n – 2)

CFG (n)

1

DATA (n – 2)

16/30

MSB

(n – 1)

CFG (n + 1)

1

DATA (n – 1)

16/30

MSB

(n)

CFG (n + 2)

1

DATA (n)

16/30

MSB

(n + 1)

CNV

DIN

SDO

SCK

CFG (n)

1

DATA

(n – 2)

16/30

CFG (n + 1)

1

DATA

(n – 1)

16/30

CFG (n + 2)

DATA (n)

1 16/30

CNV

DIN

SDO

SCK

1

DATA

(n – 2)

CFG (n)

DATA

(n – 2)

16/30 1

DATA

(n – 1)

CFG (n + 1)

DATA

(n – 1)

16/30 1

DATA (n)

CFG (n + 2)

DATA (n)

16/30

NOTES

1. CNV MUST BE HIGH PRIOR TO THE END OF CONVERSION (EOC) TO AVOID THE BUSY INDICATOR.

A TOTAL OF 16 SCK FALLING EDGES IS REQUIRED TO RETURN SDO TO HIGH-Z. IF CFG READBACK

IS ENABLED, A TOTAL OF 30 SCK FALLING EDGES IS REQUIRED TO RETURN SDO TO HIGH-Z.

Figure 35. General Interface Timing for the AD7699 Without a Busy Indicator

Rev. E | Page 23 of 29

1

CFG (n + 3)

DATA (n + 1)

1

CFG (n + 3)

DATA

(n + 1)

AD7699 Data Sheet

GENERAL TIMING WITH A BUSY INDICATOR

Figure 36 details the timing for all three modes: reading/writing

during conversion, after conversion, and spanning conversion.

Note that the gating item for both CFG and data readback is at the end of conversion (EOC). As detailed previously, the data access should occur up to safe data reading/writing time, t

DATA

.

If the full CFG word is not written to prior to EOC, it is discarded and the current configuration remains.

At the EOC, if CNV is low, the busy indicator is enabled. In addition, to generate the busy indicator properly, the host must assert a minimum of 17 SCK falling edges to return SDO to high impedance because the last bit of data on SDO remains

active. Unlike the case detailed in the General Timing Without a Busy Indicator section, if the conversion result is not read out

START OF CONVERSION t

CYC

POWER

UP t

CONV t

DATA

END OF CONVERSION (EOC)

fully prior to EOC, the last bit clocked out remains. If this bit is low, the busy signal indicator cannot be generated because the digital output requires a high impedance, or a bit remaining high, to low transition for the interrupt input of the host. A good example of this occurs when an SPI host sends 16 SCKs because these are usually limited to 8-bit or 16-bit bursts, thus the LSB remains. Because the transition noise of the AD7699 is 4 LSBs peak to peak (or greater), the LSB is low 50% of the time. For this interface, the SPI host needs to burst 24 SCKs, or a QSPI interface can be used and programmed for 17 SCKs.

The SCK can idle high or low depending on the CPOL and

CPHA settings if SPI is used. A simple solution is to use CPOL

= CPHA = 1 (not shown) with SCK idling high.

EOC EOC

PHASE CONVERSION (n – 2)

ACQUISITION

(n –1)

CONVERSION (n – 1)

ACQUISITION

(n)

CONVERSION (n)

ACQUISITION

(n + 1)

CONVERSION (n + 1)

ACQUISITION

(n + 2)

CNV

DIN

SDO

SCK

XXX

1

XXX

17/31 1

CFG (n)

DATA

(n – 2)

17/31 1

CFG (n + 1)

DATA

(n – 1)

17/31

CFG (n + 2)

1

DATA (n)

17/31

CNV

DIN

SDO

SCK

1

CFG (n)

DATA

(n – 2)

17/31 1

CFG (n + 1)

DATA

(n – 1)

17/31

CFG (n + 2)

DATA (n)

1 17/31

CNV

DIN

SDO

CFG (n)

1

DATA (n – 2)

DATA

(n – 2)

17/31 1

CFG (n + 1)

DATA

(n – 1)

DATA

(n – 1)

17/31

SCK

NOTES

1. CNV MUST BE HIGH PRIOR TO THE END OF CONVERSION (EOC) TO AVOID THE BUSY INDICATOR.

A TOTAL OF 17 SCK FALLING EDGES IS REQUIRED TO RETURN SDO TO HIGH-Z. IF CFG READBACK

IS ENABLED, A TOTAL OF 31 SCK FALLING EDGES IS REQUIRED TO RETURN SDO TO HIGH-Z.

Figure 36. General Interface Timing for the AD7699 with a Busy Indicator

1

CFG (n + 2)

DATA (n) DATA (n)

17/31

Rev. E | Page 24 of 29

1

CFG (n + 3)

DATA (n + 1)

1

CFG (n + 3)

DATA (n + 1)

Data Sheet

READ/WRITE SPANNING CONVERSION WITHOUT

A BUSY INDICATOR

This mode is used when the AD7699 is connected to any host using an SPI, serial port, or FPGA. The connection diagram is

shown in Figure 37, and the corresponding timing is given in

Figure 38. For SPI, the host should use CPHA = CPOL = 0.

Reading/writing spanning conversion is shown, which covers

all three modes detailed in the Digital Interface section. For this

mode, the host must generate the data transfer based on the conversion time. For an interrupt driven transfer, refer to the next section, which uses a busy indicator.

A rising edge on CNV initiates a conversion, forces SDO to high impedance, and ignores data present on DIN. After a conversion is initiated, it continues until completion irrespective of the state of CNV. CNV must be returned high before the safe data transfer time, t

DATA

, and then held high beyond the conversion time, t

CONV

, to avoid generation of the busy signal indicator.

After the conversion is complete, the AD7699 enters the acquisition phase and powers down. When the host brings CNV low after t

CONV

(max), the MSB is enabled on SDO. The host also must enable the MSB of CFG at this time (if necessary) to begin

AD7699

CNV

SDO

DIN

SCK

AD7699

the CFG update. While CNV is low, both a CFG update and a data readback take place. The first 14 SCK rising edges are used to update the CFG, and the first 15 SCK falling edges clock out the conversion results starting with MSB − 1. The restriction for both configuring and reading is that they both must occur before the t

DATA

time of the next conversion elapses. All 14 bits of CFG[13:0] must be written, or they are ignored. In addition, if the 16-bit conversion result is not read back before t

DATA

elapses, it is lost.

The SDO data is valid on both SCK edges. Although the rising edge can be used to capture the data, a digital host using the

SCK falling edge allows a faster reading rate, provided it has an acceptable hold time. After the 16 th

(or 30 th

) SCK falling edge, or when CNV goes high (whichever occurs first), SDO returns to high impedance.

If CFG readback is enabled, the CFG associated with the conversion result is read back MSB first following the LSB of the conversion result. A total of 30 SCK falling edges is required to return SDO to high impedance if this is enabled.

DIGITAL HOST

SS

MISO

MOSI

SCK

CNV

ACQUISITION

(n – 1)

SCK

DIN

SDO

FOR SPI USE CPHA = 0, CPOL = 0.

Figure 37. Connection Diagram for the AD7699 Without a Busy Indicator

t

CYC t

DATA

> t

CONV t

CONV t

DATA t

CONV t

CNVH

RETURN CNV HIGH

FOR NO BUSY

RETURN CNV HIGH

FOR NO BUSY t

ACQ t

DIS t

CONVERSION (n – 1)

SCKH t

SCKL t

EN t

14

SCK

CFG

LSB

15

X

END CFG (n)

16/

30

X

LSB + 1

LSB

END DATA (n – 2)

(QUIET

TIME)

UPDATE (n)

CFG/SDO

ACQUISITION (n)

CONVERSION (n)

1

2 14 15

SEE NOTE

16/

30 t

CLSCK t

EN

CFG

MSB t

SDIN

CFG

MSB – 1 t

HDIN

BEGIN CFG (n + 1) t

HSDO t

DSDO

MSB

MSB – 1 t

EN

CFG

LSB

X

END CFG (n + 1)

X

LSB + 1

SEE NOTE

LSB t

DIS t

DIS

BEGIN DATA (n – 1) t

DIS

END DATA (n – 1)

NOTES

1. THE LSB IS FOR CONVERSION RESULTS OR THE CONFIGURATION REGISTER CFG (n – 1) IF.

15 SCK FALLING EDGES = LSB OF CONVERSION RESULTS.

29 SCK FALLING EDGES = LSB OF CONFIGURATION REGISTER.

ON THE 16TH OR 30TH SCK FALLING EDGE, SDO IS DRIVEN TO HIGH IMPENDANCE.

(QUIET

TIME)

ACQUISITION

(n + 1)

UPDATE (n + 1)

CFG/SDO

Figure 38. Serial Interface Timing for the AD7699 Without a Busy Indicator

Rev. E | Page 25 of 29

AD7699

READ/WRITE SPANNING CONVERSION WITH A

BUSY INDICATOR

This mode is used when the AD7699 is connected to any host using an SPI, serial port, or FPGA with an interrupt input. The

connection diagram is shown in Figure 39, and the corresponding timing is given in Figure 40. For SPI, the host

should use CPHA = CPOL = 1. Reading/writing spanning conversion is shown, which covers all three modes detailed in

the Digital Interface section.

A rising edge on CNV initiates a conversion, forces SDO to high impedance, and ignores data present on DIN. After a conversion is initiated, it continues until completion irrespective of the state of CNV. CNV must be returned low before the safe data transfer time, t

DATA

, and then held low beyond the conversion time, t

CONV

, to generate the busy signal indicator.

When the conversion is complete, SDO transitions from high impedance to low with a pull-up to VIO, which can be used to interrupt the host to begin data transfer.

After the conversion is complete, the AD7699 enters the acquisition phase and power-down. The host must enable the

MSB of CFG at this time (if necessary) to begin the CFG

VIO

AD7699

DIGITAL HOST

SDO

CNV

DIN

SCK

MISO

IRQ

SS

MOSI

SCK

FOR SPI USE CPHA = 1, CPOL = 1.

Figure 39. Connection Diagram for the AD7699 with a Busy Indicator

t

CYC t

DATA t

ACQ

CNV

Data Sheet

update. While CNV is low, both a CFG update and a data readback take place. The first 14 SCK rising edges are used to update the CFG register, and the first 16 SCK falling edges clock out the conversion results starting with the MSB. The restriction for both configuring and reading is that they both occur before the t

DATA

time elapses for the next conversion. All 14 bits of

CFG[13:0] must be written or they are ignored. Also, if the 16-bit conversion result is not read back before t

DATA

elapses, it is lost.

The SDO data is valid on both SCK edges. Although the rising edge can be used to capture the data, a digital host using the

SCK falling edge allows a faster reading rate, provided it has an acceptable hold time. After the optional 17 th SCK falling edge,

SDO returns to high impedance. Note that, if the optional SCK falling edge is not used, the busy feature cannot be detected if the LSB for the conversion is low.

If CFG readback is enabled, the CFG register associated with the conversion result (n − 1) is read back MSB first following the LSB of the conversion result. A total of 31 SCK falling edges is required to return SDO to high impedance if this is enabled.

t

CNVH t

DATA t

CONV

CONVERSION

(n – 1)

SCK

DIN

SDO t

SCKH

CONVERSION (n – 1) t

SCK

15 16

17/

31 t

SCKL

X

END CFG (n)

X

LSB

+ 1

END DATA (n – 2)

X

LSB

(QUIET

TIME)

UPDATE (n)

CFG/SDO

ACQUISITION (n) CONVERSION (n) t

DIS

1 2

CFG

MSB t

HDIN t

SDIN

CFG

MSB –1

BEIGN CFG (n + 1) t

HSDO t

DSDO

MSB

MSB

– 1

BEGIN DATA (n – 1) t

EN

15

X

SEE NOTE

16

17/

31

X

END CFG (n + 1)

X

LSB

+ 1

END DATA (n – 1)

LSB

SEE NOTE t

EN t

DIS

NOTES

1. THE LSB IS FOR CONVERSION RESULTS OR THE CONFIGURATION REGISTER CFG (n – 1) IF.

16 SCK FALLING EDGES = LSB OF CONVERSION RESULTS.

30 SCK FALLING EDGES = LSB OF CONFIGURATION REGISTER.

ON THE 17TH OR 31st SCK FALLING EDGE, SDO IS DRIVEN TO HIGH IMPENDANCE.

OTHERWISE, THE LSB REMAINS ACTIVE UNTIL THE BUSY INDICATOR IS DRIVEN LOW.

t

DIS

(QUIET

TIME)

ACQUISITION

(n + 1)

UPDATE (n + 1)

CFG/SDO t

EN

Figure 40. Serial Interface Timing for the AD7699 with a Busy Indicator

Rev. E | Page 26 of 29

Data Sheet AD7699

CHANNEL SEQUENCER

The AD7699 include a channel sequencer useful for scanning channels in a repeated fashion. Channels are scanned as singles or pairs, with or without the temperature sensor, after the last channel is sequenced.

The sequencer starts with IN0 and finishes with IN[7:0] set in

CFG[9:7]. For paired channels, the channels are paired depending on the last channel set in CFG[9:7]. Note that in sequencer mode, the channels are always paired with the positive input on the even channels (IN0, IN2, IN4, and IN6), and with the negative input on the odd channels (IN1, IN3, IN5, and IN7).

For example, setting CFG[9:7] = 110 or 111 scans all pairs with the positive inputs dedicated to IN0, IN2, IN4, and IN6.

CFG[2:1] are used to enable the sequencer. After the CFG register is updated, DIN must be held low while reading data out for Bit 13, or the CFG register begins updating again.

Figure 41 details the timing for all three modes without a busy

indicator. The sequencer can also be used with the busy indicator and details for these timings can be found in the

General Timing With a Busy Indicator section and the

Read/Write Spanning Conversion with a Busy Indicator section.

For sequencer operation, the CFG register must be set during the (n − 1) phase after power-up. On phase (n), the sequencer setting takes place and acquires IN0. The first valid conversion result is available at phase (n + 1). After the last channel set in

CFG[9:7] is converted, the internal temperature sensor data is output (if enabled), followed by acquisition of IN0.

Examples

With all channels configured for unipolar mode to GND, including the internal temperature sensor, the sequence scans in the following order:

Note that while operating in a sequence, some bits of the CFG register can be changed. However, if changing CFG[11] (paired or single channel) or CFG[9:7] (last channel in sequence), the sequence reinitializes and converts IN0 (or IN0/IN1 pairs) after the CFG register is updated.

PHASE

POWER

UP

SOC t

CYC

EOC t

CONV

CONVERSION

(n – 2) UNDEFINED

ACQUISITION

(n – 1) UNDEFINED t

DATA

CONVERSION

(n – 1) UNDEFINED

EOC

ACQUISITION

(n), IN0

IN0, IN1, IN2, IN3, IN4, IN5, IN6, IN7, TEMP, IN0, IN1, IN2…

For paired channels with the internal temperature sensor enabled, the sequencer scans in the following order:

IN0, IN2, IN4, IN6, TEMP, IN0…

Note that IN1, IN3, IN5, and IN7 are referenced to a GND sense or V

REF

/2, as detailed in the Input Configurations section.

CONVERSION

(n), IN0

EOC

ACQUISITION

(n + 1), IN1

CONVERSION

(n + 1), IN1

EOC

ACQUISITION

(n + 2), IN2

NOTE 1

CNV

DIN

RDC

SDO

SCK

MSB

XXX

XXX

1

DATA (n – 3)

XXX

16

2

CFG (n)

1

DATA (n – 2)

XXX

16

NOTE 2

MSB

XXX

1

DATA (n – 1)

XXX

16 1

DATA IN0

16

CNV

DIN

RAC

SDO

SCK

CFG (n)

1

DATA (n – 2)

XXX

16

NOTE 2

1

DATA (n – 1)

XXX

16 1

DATA IN0

16

CNV

DIN

RSC

SDO

CFG (n)

DATA (n – 2)

XXX

CFG (n)

DATA (n – 2)

XXX

DATA (n – 1)

XXX

DATA (n – 1)

XXX

DATA IN0

SCK

1 n n + 1 16 1 n n + 1 16

NOTE 2

NOTES

1. CNV MUST BE HIGH PRIOR TO THE END OF CONVERSION (EOC) TO AVOID THE BUSY INDICATOR.

2. A TOTAL OF 16 SCK FALLING EDGES ARE REQUIRED TO RETURN SDO TO HIGH-Z. IF CFG READBACK IS ENABLED,

A TOTAL OF 30 SCK FALLING EDGES IS REQUIRED TO RETURN SDO TO HIGH-Z.

1

Figure 41. General Channel Sequencer Timing Without a Busy Indicator

n n + 1

DATA IN0

16

1

DATA IN1

1

DATA IN1 n

Rev. E | Page 27 of 29

AD7699

APPLICATION HINTS

LAYOUT

The printed circuit board that houses the AD7699 should be designed so that the analog and digital sections are separated and confined to certain areas of the board. The pinout of the

AD7699 , with all its analog signals on the left side and all its digital signals on the right side, eases this task.

Avoid running digital lines under the device because these couple noise onto the die unless a ground plane under the AD7699 is used as a shield. Fast switching signals, such as CNV or clocks, should not run near analog signal paths. Crossover of digital and analog signals should be avoided.

At least one ground plane should be used. It can be common or split between the digital and analog sections. In the latter case, the planes should be joined underneath the AD7699 .

The AD7699 voltage reference input, REF, has a dynamic input impedance and should be decoupled with minimal parasitic

Data Sheet

inductances. This is done by placing the reference decoupling ceramic capacitor close to, ideally right up against, the REF and

GND pins and connecting them with wide, low impedance traces.

Finally, the power supplies, VDD and VIO, of the AD7699 should be decoupled with ceramic capacitors, typically 100 nF, placed close to the AD7699 and connected using short, wide traces to provide low impedance paths and to reduce the effect of glitches on the power supply lines.

EVALUATING

AD7699

PERFORMANCE

Other recommended layouts for the AD7699 are outlined in the documentation of the evaluation board for the AD7699 ( EVAL-

AD76MUXEDZ ). The evaluation board package includes a fully assembled and tested evaluation board, documentation, and software for controlling the board from a PC via the evaluation controller board, EVAL-CED1Z .

Rev. E | Page 28 of 29

Data Sheet

OUTLINE DIMENSIONS

AD7699

PIN 1

INDICATOR

0.80

0.75

0.70

SEATING

PLANE

4.10

4.00 SQ

3.90

TOP VIEW

0.50

BSC

15

16

0.30

0.25

0.20

EXPOSED

PAD

20

1

PIN 1

INDICATOR

2.65

2.50 SQ

2.35

11

10

BOTTOM VIEW

6

5

0.50

0.40

0.30

0.25 MIN

0.05 MAX

0.02 NOM

COPLANARITY

0.08

0.20 REF

FOR PROPER CONNECTION OF

THE EXPOSED PAD, REFER TO

THE PIN CONFIGURATION AND

FUNCTION DESCRIPTIONS

SECTION OF THIS DATA SHEET.

COMPLIANT TO JEDEC STANDARDS MO-220-WGGD.

Figure 42. 20-Lead Lead Frame Chip Scale Package (LFCSP_WQ)

4 mm × 4 mm Body, Very Very Thin Quad

(CP-20-10)

Dimensions shown in millimeters

ORDERING GUIDE

Model

1, 2

AD7699BCPZ

AD7699BCPZRL7

Integral

Nonlinearity

No Missing

Code

±1.5 LSB max 16 bits

±1.5 LSB max 16 bits

Temperature

Range Package Description

−40°C to +85°C 20-Lead LFCSP_WQ, Tray

−40°C to +85°C 20-Lead LFCSP_WQ, Reel

Package

Option

Ordering

Quantity

CP-20-10 490

CP-20-10 1500

EVAL-AD7699EDZ

EVAL-CED1Z Controller

1

Z = RoHS Compliant Part.

2

The EVAL-CED1Z controller board allows a PC to control and communicate with all Analog Devices evaluation boards with model numbers ending in ED.

©2008–2015 Analog Devices, Inc. All rights reserved. Trademarks and

registered trademarks are the property of their respective owners.

D07354-0-9/15(E)

Rev. E | Page 29 of 29

Was this manual useful for you? yes no
Thank you for your participation!

* Your assessment is very important for improving the work of artificial intelligence, which forms the content of this project